rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_78 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_78( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_9 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_18 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_19 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_9( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_17 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock inst q of Queue3_EgressFlit_17 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0hc), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h8), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h6), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0he), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h0), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_32 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h4), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_33 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h2), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_34 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0ha), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_35 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_29) node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_30) node _q_io_enq_bits_ingress_id_T_39 = or(_q_io_enq_bits_ingress_id_T_38, _q_io_enq_bits_ingress_id_T_31) node _q_io_enq_bits_ingress_id_T_40 = or(_q_io_enq_bits_ingress_id_T_39, _q_io_enq_bits_ingress_id_T_32) node _q_io_enq_bits_ingress_id_T_41 = or(_q_io_enq_bits_ingress_id_T_40, _q_io_enq_bits_ingress_id_T_33) node _q_io_enq_bits_ingress_id_T_42 = or(_q_io_enq_bits_ingress_id_T_41, _q_io_enq_bits_ingress_id_T_34) node _q_io_enq_bits_ingress_id_T_43 = or(_q_io_enq_bits_ingress_id_T_42, _q_io_enq_bits_ingress_id_T_35) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_43 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow	module EgressUnit_17( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_25 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_282 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_26 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_282( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_26 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_103 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_113 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_103( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_113 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0h80))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 64, 39) node _adjustedSig_T_1 = bits(io.in.sig, 38, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [9:0] _sAdjustedExp_T = {io_in_sExp_0[8], io_in_sExp_0} + 10'h80; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [25:0] _adjustedSig_T = io_in_sig_0[64:39]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [38:0] _adjustedSig_T_1 = io_in_sig_0[38:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = \|_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig \| 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_15 = {25'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReqGen : input clock : Clock input reset : Reset output io : { flip send_reqs : UInt<1>, sent_done : UInt<1>, req_fire : UInt<1>, flip global_stream_info : { valid : UInt<1>, bits : { stream_cnt : UInt<5>, addr_range : UInt<64>, max_reqs : UInt<64>}}, flip local_stream_info : { valid : UInt<1>, bits : { data : { start_addr : UInt<64>, stride : UInt<64>, stream_type : UInt<3>}, idx : UInt<4>}}, req : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : { addr : UInt, cmd : UInt, size : UInt, data : UInt<128>}, idx : UInt<4>}}} inst rand_val_prng of MaxPeriodFibonacciLFSR_9 connect rand_val_prng.clock, clock connect rand_val_prng.reset, reset connect rand_val_prng.io.seed.valid, UInt<1>(0h0) invalidate rand_val_prng.io.seed.bits[0] invalidate rand_val_prng.io.seed.bits[1] invalidate rand_val_prng.io.seed.bits[2] invalidate rand_val_prng.io.seed.bits[3] invalidate rand_val_prng.io.seed.bits[4] invalidate rand_val_prng.io.seed.bits[5] invalidate rand_val_prng.io.seed.bits[6] invalidate rand_val_prng.io.seed.bits[7] invalidate rand_val_prng.io.seed.bits[8] invalidate rand_val_prng.io.seed.bits[9] invalidate rand_val_prng.io.seed.bits[10] invalidate rand_val_prng.io.seed.bits[11] invalidate rand_val_prng.io.seed.bits[12] invalidate rand_val_prng.io.seed.bits[13] invalidate rand_val_prng.io.seed.bits[14] invalidate rand_val_prng.io.seed.bits[15] invalidate rand_val_prng.io.seed.bits[16] invalidate rand_val_prng.io.seed.bits[17] invalidate rand_val_prng.io.seed.bits[18] invalidate rand_val_prng.io.seed.bits[19] invalidate rand_val_prng.io.seed.bits[20] invalidate rand_val_prng.io.seed.bits[21] invalidate rand_val_prng.io.seed.bits[22] invalidate rand_val_prng.io.seed.bits[23] invalidate rand_val_prng.io.seed.bits[24] invalidate rand_val_prng.io.seed.bits[25] invalidate rand_val_prng.io.seed.bits[26] invalidate rand_val_prng.io.seed.bits[27] invalidate rand_val_prng.io.seed.bits[28] invalidate rand_val_prng.io.seed.bits[29] connect rand_val_prng.io.increment, UInt<1>(0h1) node rand_val_lo_lo_lo_hi = cat(rand_val_prng.io.out[2], rand_val_prng.io.out[1]) node rand_val_lo_lo_lo = cat(rand_val_lo_lo_lo_hi, rand_val_prng.io.out[0]) node rand_val_lo_lo_hi_lo = cat(rand_val_prng.io.out[4], rand_val_prng.io.out[3]) node rand_val_lo_lo_hi_hi = cat(rand_val_prng.io.out[6], rand_val_prng.io.out[5]) node rand_val_lo_lo_hi = cat(rand_val_lo_lo_hi_hi, rand_val_lo_lo_hi_lo) node rand_val_lo_lo = cat(rand_val_lo_lo_hi, rand_val_lo_lo_lo) node rand_val_lo_hi_lo_lo = cat(rand_val_prng.io.out[8], rand_val_prng.io.out[7]) node rand_val_lo_hi_lo_hi = cat(rand_val_prng.io.out[10], rand_val_prng.io.out[9]) node rand_val_lo_hi_lo = cat(rand_val_lo_hi_lo_hi, rand_val_lo_hi_lo_lo) node rand_val_lo_hi_hi_lo = cat(rand_val_prng.io.out[12], rand_val_prng.io.out[11]) node rand_val_lo_hi_hi_hi = cat(rand_val_prng.io.out[14], rand_val_prng.io.out[13]) node rand_val_lo_hi_hi = cat(rand_val_lo_hi_hi_hi, rand_val_lo_hi_hi_lo) node rand_val_lo_hi = cat(rand_val_lo_hi_hi, rand_val_lo_hi_lo) node rand_val_lo = cat(rand_val_lo_hi, rand_val_lo_lo) node rand_val_hi_lo_lo_hi = cat(rand_val_prng.io.out[17], rand_val_prng.io.out[16]) node rand_val_hi_lo_lo = cat(rand_val_hi_lo_lo_hi, rand_val_prng.io.out[15]) node rand_val_hi_lo_hi_lo = cat(rand_val_prng.io.out[19], rand_val_prng.io.out[18]) node rand_val_hi_lo_hi_hi = cat(rand_val_prng.io.out[21], rand_val_prng.io.out[20]) node rand_val_hi_lo_hi = cat(rand_val_hi_lo_hi_hi, rand_val_hi_lo_hi_lo) node rand_val_hi_lo = cat(rand_val_hi_lo_hi, rand_val_hi_lo_lo) node rand_val_hi_hi_lo_lo = cat(rand_val_prng.io.out[23], rand_val_prng.io.out[22]) node rand_val_hi_hi_lo_hi = cat(rand_val_prng.io.out[25], rand_val_prng.io.out[24]) node rand_val_hi_hi_lo = cat(rand_val_hi_hi_lo_hi, rand_val_hi_hi_lo_lo) node rand_val_hi_hi_hi_lo = cat(rand_val_prng.io.out[27], rand_val_prng.io.out[26]) node rand_val_hi_hi_hi_hi = cat(rand_val_prng.io.out[29], rand_val_prng.io.out[28]) node rand_val_hi_hi_hi = cat(rand_val_hi_hi_hi_hi, rand_val_hi_hi_hi_lo) node rand_val_hi_hi = cat(rand_val_hi_hi_hi, rand_val_hi_hi_lo) node rand_val_hi = cat(rand_val_hi_hi, rand_val_hi_lo) node rand_val = cat(rand_val_hi, rand_val_lo) regreset stream_cnt : UInt<5>, clock, reset, UInt<5>(0h0) regreset addr_range : UInt<64>, clock, reset, UInt<64>(0h0) regreset max_reqs : UInt<64>, clock, reset, UInt<64>(0h0) wire _start_addr_WIRE : UInt<64>[16] connect _start_addr_WIRE[0], UInt<64>(0h0) connect _start_addr_WIRE[1], UInt<64>(0h0) connect _start_addr_WIRE[2], UInt<64>(0h0) connect _start_addr_WIRE[3], UInt<64>(0h0) connect _start_addr_WIRE[4], UInt<64>(0h0) connect _start_addr_WIRE[5], UInt<64>(0h0) connect _start_addr_WIRE[6], UInt<64>(0h0) connect _start_addr_WIRE[7], UInt<64>(0h0) connect _start_addr_WIRE[8], UInt<64>(0h0) connect _start_addr_WIRE[9], UInt<64>(0h0) connect _start_addr_WIRE[10], UInt<64>(0h0) connect _start_addr_WIRE[11], UInt<64>(0h0) connect _start_addr_WIRE[12], UInt<64>(0h0) connect _start_addr_WIRE[13], UInt<64>(0h0) connect _start_addr_WIRE[14], UInt<64>(0h0) connect _start_addr_WIRE[15], UInt<64>(0h0) regreset start_addr : UInt<64>[16], clock, reset, _start_addr_WIRE wire _stride_WIRE : UInt<64>[16] connect _stride_WIRE[0], UInt<64>(0h0) connect _stride_WIRE[1], UInt<64>(0h0) connect _stride_WIRE[2], UInt<64>(0h0) connect _stride_WIRE[3], UInt<64>(0h0) connect _stride_WIRE[4], UInt<64>(0h0) connect _stride_WIRE[5], UInt<64>(0h0) connect _stride_WIRE[6], UInt<64>(0h0) connect _stride_WIRE[7], UInt<64>(0h0) connect _stride_WIRE[8], UInt<64>(0h0) connect _stride_WIRE[9], UInt<64>(0h0) connect _stride_WIRE[10], UInt<64>(0h0) connect _stride_WIRE[11], UInt<64>(0h0) connect _stride_WIRE[12], UInt<64>(0h0) connect _stride_WIRE[13], UInt<64>(0h0) connect _stride_WIRE[14], UInt<64>(0h0) connect _stride_WIRE[15], UInt<64>(0h0) regreset stride : UInt<64>[16], clock, reset, _stride_WIRE wire _stream_type_WIRE : UInt<3>[16] connect _stream_type_WIRE[0], UInt<3>(0h0) connect _stream_type_WIRE[1], UInt<3>(0h0) connect _stream_type_WIRE[2], UInt<3>(0h0) connect _stream_type_WIRE[3], UInt<3>(0h0) connect _stream_type_WIRE[4], UInt<3>(0h0) connect _stream_type_WIRE[5], UInt<3>(0h0) connect _stream_type_WIRE[6], UInt<3>(0h0) connect _stream_type_WIRE[7], UInt<3>(0h0) connect _stream_type_WIRE[8], UInt<3>(0h0) connect _stream_type_WIRE[9], UInt<3>(0h0) connect _stream_type_WIRE[10], UInt<3>(0h0) connect _stream_type_WIRE[11], UInt<3>(0h0) connect _stream_type_WIRE[12], UInt<3>(0h0) connect _stream_type_WIRE[13], UInt<3>(0h0) connect _stream_type_WIRE[14], UInt<3>(0h0) connect _stream_type_WIRE[15], UInt<3>(0h0) regreset stream_type : UInt<3>[16], clock, reset, _stream_type_WIRE wire _end_addr_WIRE : UInt<64>[16] connect _end_addr_WIRE[0], UInt<64>(0h0) connect _end_addr_WIRE[1], UInt<64>(0h0) connect _end_addr_WIRE[2], UInt<64>(0h0) connect _end_addr_WIRE[3], UInt<64>(0h0) connect _end_addr_WIRE[4], UInt<64>(0h0) connect _end_addr_WIRE[5], UInt<64>(0h0) connect _end_addr_WIRE[6], UInt<64>(0h0) connect _end_addr_WIRE[7], UInt<64>(0h0) connect _end_addr_WIRE[8], UInt<64>(0h0) connect _end_addr_WIRE[9], UInt<64>(0h0) connect _end_addr_WIRE[10], UInt<64>(0h0) connect _end_addr_WIRE[11], UInt<64>(0h0) connect _end_addr_WIRE[12], UInt<64>(0h0) connect _end_addr_WIRE[13], UInt<64>(0h0) connect _end_addr_WIRE[14], UInt<64>(0h0) connect _end_addr_WIRE[15], UInt<64>(0h0) regreset end_addr : UInt<64>[16], clock, reset, _end_addr_WIRE wire _cur_addr_WIRE : UInt<64>[16] connect _cur_addr_WIRE[0], UInt<64>(0h0) connect _cur_addr_WIRE[1], UInt<64>(0h0) connect _cur_addr_WIRE[2], UInt<64>(0h0) connect _cur_addr_WIRE[3], UInt<64>(0h0) connect _cur_addr_WIRE[4], UInt<64>(0h0) connect _cur_addr_WIRE[5], UInt<64>(0h0) connect _cur_addr_WIRE[6], UInt<64>(0h0) connect _cur_addr_WIRE[7], UInt<64>(0h0) connect _cur_addr_WIRE[8], UInt<64>(0h0) connect _cur_addr_WIRE[9], UInt<64>(0h0) connect _cur_addr_WIRE[10], UInt<64>(0h0) connect _cur_addr_WIRE[11], UInt<64>(0h0) connect _cur_addr_WIRE[12], UInt<64>(0h0) connect _cur_addr_WIRE[13], UInt<64>(0h0) connect _cur_addr_WIRE[14], UInt<64>(0h0) connect _cur_addr_WIRE[15], UInt<64>(0h0) regreset cur_addr : UInt<64>[16], clock, reset, _cur_addr_WIRE node _io_req_fire_T = and(io.req.ready, io.req.valid) connect io.req_fire, _io_req_fire_T connect io.sent_done, UInt<1>(0h0) connect io.req.valid, UInt<1>(0h0) connect io.req.bits.data.addr, UInt<1>(0h0) connect io.req.bits.data.cmd, UInt<1>(0h0) connect io.req.bits.data.size, UInt<3>(0h4) connect io.req.bits.data.data, UInt<1>(0h0) connect io.req.bits.idx, UInt<1>(0h0) when io.global_stream_info.valid : connect stream_cnt, io.global_stream_info.bits.stream_cnt connect addr_range, io.global_stream_info.bits.addr_range connect max_reqs, io.global_stream_info.bits.max_reqs regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Global Stream Info, stream_cnt: %d, addr_range: 0x%x, max_reqs: %d\n", io.global_stream_info.bits.stream_cnt, io.global_stream_info.bits.addr_range, io.global_stream_info.bits.max_reqs) : printf_1 when io.local_stream_info.valid : connect start_addr[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.start_addr connect stride[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.stride connect stream_type[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.stream_type node _end_addr_T = add(io.local_stream_info.bits.data.start_addr, addr_range) node _end_addr_T_1 = tail(_end_addr_T, 1) connect end_addr[io.local_stream_info.bits.idx], _end_addr_T_1 connect cur_addr[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.start_addr regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Local Stream Info[%d], start_addr: 0x%x, stride: 0x%x, stream_type: %d\n", io.local_stream_info.bits.idx, io.local_stream_info.bits.data.start_addr, io.local_stream_info.bits.data.stride, io.local_stream_info.bits.data.stream_type) : printf_3 regreset s_idx : UInt<5>, clock, reset, UInt<5>(0h0) wire _s_sent_WIRE : UInt<64>[16] connect _s_sent_WIRE[0], UInt<64>(0h0) connect _s_sent_WIRE[1], UInt<64>(0h0) connect _s_sent_WIRE[2], UInt<64>(0h0) connect _s_sent_WIRE[3], UInt<64>(0h0) connect _s_sent_WIRE[4], UInt<64>(0h0) connect _s_sent_WIRE[5], UInt<64>(0h0) connect _s_sent_WIRE[6], UInt<64>(0h0) connect _s_sent_WIRE[7], UInt<64>(0h0) connect _s_sent_WIRE[8], UInt<64>(0h0) connect _s_sent_WIRE[9], UInt<64>(0h0) connect _s_sent_WIRE[10], UInt<64>(0h0) connect _s_sent_WIRE[11], UInt<64>(0h0) connect _s_sent_WIRE[12], UInt<64>(0h0) connect _s_sent_WIRE[13], UInt<64>(0h0) connect _s_sent_WIRE[14], UInt<64>(0h0) connect _s_sent_WIRE[15], UInt<64>(0h0) regreset s_sent : UInt<64>[16], clock, reset, _s_sent_WIRE wire _s_sent_done_WIRE : UInt<1>[16] connect _s_sent_done_WIRE[0], UInt<1>(0h0) connect _s_sent_done_WIRE[1], UInt<1>(0h0) connect _s_sent_done_WIRE[2], UInt<1>(0h0) connect _s_sent_done_WIRE[3], UInt<1>(0h0) connect _s_sent_done_WIRE[4], UInt<1>(0h0) connect _s_sent_done_WIRE[5], UInt<1>(0h0) connect _s_sent_done_WIRE[6], UInt<1>(0h0) connect _s_sent_done_WIRE[7], UInt<1>(0h0) connect _s_sent_done_WIRE[8], UInt<1>(0h0) connect _s_sent_done_WIRE[9], UInt<1>(0h0) connect _s_sent_done_WIRE[10], UInt<1>(0h0) connect _s_sent_done_WIRE[11], UInt<1>(0h0) connect _s_sent_done_WIRE[12], UInt<1>(0h0) connect _s_sent_done_WIRE[13], UInt<1>(0h0) connect _s_sent_done_WIRE[14], UInt<1>(0h0) connect _s_sent_done_WIRE[15], UInt<1>(0h0) regreset s_sent_done : UInt<1>[16], clock, reset, _s_sent_done_WIRE when io.send_reqs : node _cur_stream_T = bits(s_idx, 3, 0) wire addr : UInt<64> connect addr, UInt<64>(0h0) node _data_T = dshl(UInt<1>(0h1), UInt<8>(0h80)) node _data_T_1 = sub(_data_T, UInt<1>(0h1)) node _data_T_2 = tail(_data_T_1, 1) node _data_T_3 = dshl(UInt<1>(0h1), s_idx) node data = xor(_data_T_2, _data_T_3) node _T_8 = eq(stream_type[_cur_stream_T], UInt<3>(0h4)) node _T_9 = eq(stream_type[_cur_stream_T], UInt<3>(0h5)) node _T_10 = or(_T_8, _T_9) when _T_10 : node _msb_T = shl(UInt<32>(0hffffffff), 32) node _msb_T_1 = xor(UInt<64>(0hffffffffffffffff), _msb_T) node _msb_T_2 = shr(addr_range, 32) node _msb_T_3 = and(_msb_T_2, _msb_T_1) node _msb_T_4 = bits(addr_range, 31, 0) node _msb_T_5 = shl(_msb_T_4, 32) node _msb_T_6 = not(_msb_T_1) node _msb_T_7 = and(_msb_T_5, _msb_T_6) node _msb_T_8 = or(_msb_T_3, _msb_T_7) node _msb_T_9 = bits(_msb_T_1, 47, 0) node _msb_T_10 = shl(_msb_T_9, 16) node _msb_T_11 = xor(_msb_T_1, _msb_T_10) node _msb_T_12 = shr(_msb_T_8, 16) node _msb_T_13 = and(_msb_T_12, _msb_T_11) node _msb_T_14 = bits(_msb_T_8, 47, 0) node _msb_T_15 = shl(_msb_T_14, 16) node _msb_T_16 = not(_msb_T_11) node _msb_T_17 = and(_msb_T_15, _msb_T_16) node _msb_T_18 = or(_msb_T_13, _msb_T_17) node _msb_T_19 = bits(_msb_T_11, 55, 0) node _msb_T_20 = shl(_msb_T_19, 8) node _msb_T_21 = xor(_msb_T_11, _msb_T_20) node _msb_T_22 = shr(_msb_T_18, 8) node _msb_T_23 = and(_msb_T_22, _msb_T_21) node _msb_T_24 = bits(_msb_T_18, 55, 0) node _msb_T_25 = shl(_msb_T_24, 8) node _msb_T_26 = not(_msb_T_21) node _msb_T_27 = and(_msb_T_25, _msb_T_26) node _msb_T_28 = or(_msb_T_23, _msb_T_27) node _msb_T_29 = bits(_msb_T_21, 59, 0) node _msb_T_30 = shl(_msb_T_29, 4) node _msb_T_31 = xor(_msb_T_21, _msb_T_30) node _msb_T_32 = shr(_msb_T_28, 4) node _msb_T_33 = and(_msb_T_32, _msb_T_31) node _msb_T_34 = bits(_msb_T_28, 59, 0) node _msb_T_35 = shl(_msb_T_34, 4) node _msb_T_36 = not(_msb_T_31) node _msb_T_37 = and(_msb_T_35, _msb_T_36) node _msb_T_38 = or(_msb_T_33, _msb_T_37) node _msb_T_39 = bits(_msb_T_31, 61, 0) node _msb_T_40 = shl(_msb_T_39, 2) node _msb_T_41 = xor(_msb_T_31, _msb_T_40) node _msb_T_42 = shr(_msb_T_38, 2) node _msb_T_43 = and(_msb_T_42, _msb_T_41) node _msb_T_44 = bits(_msb_T_38, 61, 0) node _msb_T_45 = shl(_msb_T_44, 2) node _msb_T_46 = not(_msb_T_41) node _msb_T_47 = and(_msb_T_45, _msb_T_46) node _msb_T_48 = or(_msb_T_43, _msb_T_47) node _msb_T_49 = bits(_msb_T_41, 62, 0) node _msb_T_50 = shl(_msb_T_49, 1) node _msb_T_51 = xor(_msb_T_41, _msb_T_50) node _msb_T_52 = shr(_msb_T_48, 1) node _msb_T_53 = and(_msb_T_52, _msb_T_51) node _msb_T_54 = bits(_msb_T_48, 62, 0) node _msb_T_55 = shl(_msb_T_54, 1) node _msb_T_56 = not(_msb_T_51) node _msb_T_57 = and(_msb_T_55, _msb_T_56) node _msb_T_58 = or(_msb_T_53, _msb_T_57) node _msb_T_59 = bits(_msb_T_58, 0, 0) node _msb_T_60 = bits(_msb_T_58, 1, 1) node _msb_T_61 = bits(_msb_T_58, 2, 2) node _msb_T_62 = bits(_msb_T_58, 3, 3) node _msb_T_63 = bits(_msb_T_58, 4, 4) node _msb_T_64 = bits(_msb_T_58, 5, 5) node _msb_T_65 = bits(_msb_T_58, 6, 6) node _msb_T_66 = bits(_msb_T_58, 7, 7) node _msb_T_67 = bits(_msb_T_58, 8, 8) node _msb_T_68 = bits(_msb_T_58, 9, 9) node _msb_T_69 = bits(_msb_T_58, 10, 10) node _msb_T_70 = bits(_msb_T_58, 11, 11) node _msb_T_71 = bits(_msb_T_58, 12, 12) node _msb_T_72 = bits(_msb_T_58, 13, 13) node _msb_T_73 = bits(_msb_T_58, 14, 14) node _msb_T_74 = bits(_msb_T_58, 15, 15) node _msb_T_75 = bits(_msb_T_58, 16, 16) node _msb_T_76 = bits(_msb_T_58, 17, 17) node _msb_T_77 = bits(_msb_T_58, 18, 18) node _msb_T_78 = bits(_msb_T_58, 19, 19) node _msb_T_79 = bits(_msb_T_58, 20, 20) node _msb_T_80 = bits(_msb_T_58, 21, 21) node _msb_T_81 = bits(_msb_T_58, 22, 22) node _msb_T_82 = bits(_msb_T_58, 23, 23) node _msb_T_83 = bits(_msb_T_58, 24, 24) node _msb_T_84 = bits(_msb_T_58, 25, 25) node _msb_T_85 = bits(_msb_T_58, 26, 26) node _msb_T_86 = bits(_msb_T_58, 27, 27) node _msb_T_87 = bits(_msb_T_58, 28, 28) node _msb_T_88 = bits(_msb_T_58, 29, 29) node _msb_T_89 = bits(_msb_T_58, 30, 30) node _msb_T_90 = bits(_msb_T_58, 31, 31) node _msb_T_91 = bits(_msb_T_58, 32, 32) node _msb_T_92 = bits(_msb_T_58, 33, 33) node _msb_T_93 = bits(_msb_T_58, 34, 34) node _msb_T_94 = bits(_msb_T_58, 35, 35) node _msb_T_95 = bits(_msb_T_58, 36, 36) node _msb_T_96 = bits(_msb_T_58, 37, 37) node _msb_T_97 = bits(_msb_T_58, 38, 38) node _msb_T_98 = bits(_msb_T_58, 39, 39) node _msb_T_99 = bits(_msb_T_58, 40, 40) node _msb_T_100 = bits(_msb_T_58, 41, 41) node _msb_T_101 = bits(_msb_T_58, 42, 42) node _msb_T_102 = bits(_msb_T_58, 43, 43) node _msb_T_103 = bits(_msb_T_58, 44, 44) node _msb_T_104 = bits(_msb_T_58, 45, 45) node _msb_T_105 = bits(_msb_T_58, 46, 46) node _msb_T_106 = bits(_msb_T_58, 47, 47) node _msb_T_107 = bits(_msb_T_58, 48, 48) node _msb_T_108 = bits(_msb_T_58, 49, 49) node _msb_T_109 = bits(_msb_T_58, 50, 50) node _msb_T_110 = bits(_msb_T_58, 51, 51) node _msb_T_111 = bits(_msb_T_58, 52, 52) node _msb_T_112 = bits(_msb_T_58, 53, 53) node _msb_T_113 = bits(_msb_T_58, 54, 54) node _msb_T_114 = bits(_msb_T_58, 55, 55) node _msb_T_115 = bits(_msb_T_58, 56, 56) node _msb_T_116 = bits(_msb_T_58, 57, 57) node _msb_T_117 = bits(_msb_T_58, 58, 58) node _msb_T_118 = bits(_msb_T_58, 59, 59) node _msb_T_119 = bits(_msb_T_58, 60, 60) node _msb_T_120 = bits(_msb_T_58, 61, 61) node _msb_T_121 = bits(_msb_T_58, 62, 62) node _msb_T_122 = bits(_msb_T_58, 63, 63) node _msb_T_123 = mux(_msb_T_121, UInt<6>(0h3e), UInt<6>(0h3f)) node _msb_T_124 = mux(_msb_T_120, UInt<6>(0h3d), _msb_T_123) node _msb_T_125 = mux(_msb_T_119, UInt<6>(0h3c), _msb_T_124) node _msb_T_126 = mux(_msb_T_118, UInt<6>(0h3b), _msb_T_125) node _msb_T_127 = mux(_msb_T_117, UInt<6>(0h3a), _msb_T_126) node _msb_T_128 = mux(_msb_T_116, UInt<6>(0h39), _msb_T_127) node _msb_T_129 = mux(_msb_T_115, UInt<6>(0h38), _msb_T_128) node _msb_T_130 = mux(_msb_T_114, UInt<6>(0h37), _msb_T_129) node _msb_T_131 = mux(_msb_T_113, UInt<6>(0h36), _msb_T_130) node _msb_T_132 = mux(_msb_T_112, UInt<6>(0h35), _msb_T_131) node _msb_T_133 = mux(_msb_T_111, UInt<6>(0h34), _msb_T_132) node _msb_T_134 = mux(_msb_T_110, UInt<6>(0h33), _msb_T_133) node _msb_T_135 = mux(_msb_T_109, UInt<6>(0h32), _msb_T_134) node _msb_T_136 = mux(_msb_T_108, UInt<6>(0h31), _msb_T_135) node _msb_T_137 = mux(_msb_T_107, UInt<6>(0h30), _msb_T_136) node _msb_T_138 = mux(_msb_T_106, UInt<6>(0h2f), _msb_T_137) node _msb_T_139 = mux(_msb_T_105, UInt<6>(0h2e), _msb_T_138) node _msb_T_140 = mux(_msb_T_104, UInt<6>(0h2d), _msb_T_139) node _msb_T_141 = mux(_msb_T_103, UInt<6>(0h2c), _msb_T_140) node _msb_T_142 = mux(_msb_T_102, UInt<6>(0h2b), _msb_T_141) node _msb_T_143 = mux(_msb_T_101, UInt<6>(0h2a), _msb_T_142) node _msb_T_144 = mux(_msb_T_100, UInt<6>(0h29), _msb_T_143) node _msb_T_145 = mux(_msb_T_99, UInt<6>(0h28), _msb_T_144) node _msb_T_146 = mux(_msb_T_98, UInt<6>(0h27), _msb_T_145) node _msb_T_147 = mux(_msb_T_97, UInt<6>(0h26), _msb_T_146) node _msb_T_148 = mux(_msb_T_96, UInt<6>(0h25), _msb_T_147) node _msb_T_149 = mux(_msb_T_95, UInt<6>(0h24), _msb_T_148) node _msb_T_150 = mux(_msb_T_94, UInt<6>(0h23), _msb_T_149) node _msb_T_151 = mux(_msb_T_93, UInt<6>(0h22), _msb_T_150) node _msb_T_152 = mux(_msb_T_92, UInt<6>(0h21), _msb_T_151) node _msb_T_153 = mux(_msb_T_91, UInt<6>(0h20), _msb_T_152) node _msb_T_154 = mux(_msb_T_90, UInt<5>(0h1f), _msb_T_153) node _msb_T_155 = mux(_msb_T_89, UInt<5>(0h1e), _msb_T_154) node _msb_T_156 = mux(_msb_T_88, UInt<5>(0h1d), _msb_T_155) node _msb_T_157 = mux(_msb_T_87, UInt<5>(0h1c), _msb_T_156) node _msb_T_158 = mux(_msb_T_86, UInt<5>(0h1b), _msb_T_157) node _msb_T_159 = mux(_msb_T_85, UInt<5>(0h1a), _msb_T_158) node _msb_T_160 = mux(_msb_T_84, UInt<5>(0h19), _msb_T_159) node _msb_T_161 = mux(_msb_T_83, UInt<5>(0h18), _msb_T_160) node _msb_T_162 = mux(_msb_T_82, UInt<5>(0h17), _msb_T_161) node _msb_T_163 = mux(_msb_T_81, UInt<5>(0h16), _msb_T_162) node _msb_T_164 = mux(_msb_T_80, UInt<5>(0h15), _msb_T_163) node _msb_T_165 = mux(_msb_T_79, UInt<5>(0h14), _msb_T_164) node _msb_T_166 = mux(_msb_T_78, UInt<5>(0h13), _msb_T_165) node _msb_T_167 = mux(_msb_T_77, UInt<5>(0h12), _msb_T_166) node _msb_T_168 = mux(_msb_T_76, UInt<5>(0h11), _msb_T_167) node _msb_T_169 = mux(_msb_T_75, UInt<5>(0h10), _msb_T_168) node _msb_T_170 = mux(_msb_T_74, UInt<4>(0hf), _msb_T_169) node _msb_T_171 = mux(_msb_T_73, UInt<4>(0he), _msb_T_170) node _msb_T_172 = mux(_msb_T_72, UInt<4>(0hd), _msb_T_171) node _msb_T_173 = mux(_msb_T_71, UInt<4>(0hc), _msb_T_172) node _msb_T_174 = mux(_msb_T_70, UInt<4>(0hb), _msb_T_173) node _msb_T_175 = mux(_msb_T_69, UInt<4>(0ha), _msb_T_174) node _msb_T_176 = mux(_msb_T_68, UInt<4>(0h9), _msb_T_175) node _msb_T_177 = mux(_msb_T_67, UInt<4>(0h8), _msb_T_176) node _msb_T_178 = mux(_msb_T_66, UInt<3>(0h7), _msb_T_177) node _msb_T_179 = mux(_msb_T_65, UInt<3>(0h6), _msb_T_178) node _msb_T_180 = mux(_msb_T_64, UInt<3>(0h5), _msb_T_179) node _msb_T_181 = mux(_msb_T_63, UInt<3>(0h4), _msb_T_180) node _msb_T_182 = mux(_msb_T_62, UInt<2>(0h3), _msb_T_181) node _msb_T_183 = mux(_msb_T_61, UInt<2>(0h2), _msb_T_182) node _msb_T_184 = mux(_msb_T_60, UInt<1>(0h1), _msb_T_183) node _msb_T_185 = mux(_msb_T_59, UInt<1>(0h0), _msb_T_184) node _msb_T_186 = sub(UInt<7>(0h40), _msb_T_185) node msb = tail(_msb_T_186, 1) node _addr_T = bits(s_idx, 3, 0) node _addr_T_1 = dshl(rand_val, UInt<3>(0h4)) node _addr_T_2 = dshl(UInt<1>(0h1), msb) node _addr_T_3 = sub(_addr_T_2, UInt<1>(0h1)) node _addr_T_4 = tail(_addr_T_3, 1) node _addr_T_5 = and(_addr_T_1, _addr_T_4) node _addr_T_6 = add(start_addr[_addr_T], _addr_T_5) node _addr_T_7 = tail(_addr_T_6, 1) connect addr, _addr_T_7 else : node _T_11 = eq(stream_type[_cur_stream_T], UInt<3>(0h0)) node _T_12 = eq(stream_type[_cur_stream_T], UInt<3>(0h1)) node _T_13 = or(_T_11, _T_12) when _T_13 : node _nxt_addr_T = bits(s_idx, 3, 0) node _nxt_addr_T_1 = bits(s_idx, 3, 0) node _nxt_addr_T_2 = add(cur_addr[_nxt_addr_T], stride[_nxt_addr_T_1]) node nxt_addr = tail(_nxt_addr_T_2, 1) node _T_14 = bits(s_idx, 3, 0) node _T_15 = geq(nxt_addr, end_addr[_T_14]) when _T_15 : node _addr_T_8 = bits(s_idx, 3, 0) connect addr, start_addr[_addr_T_8] else : connect addr, nxt_addr node _T_16 = bits(s_idx, 3, 0) connect cur_addr[_T_16], addr else : node _T_17 = eq(stream_type[_cur_stream_T], UInt<3>(0h2)) node _T_18 = eq(stream_type[_cur_stream_T], UInt<3>(0h3)) node _T_19 = or(_T_17, _T_18) when _T_19 : node _addr_T_9 = bits(s_idx, 3, 0) connect addr, start_addr[_addr_T_9] wire cur_cmd : UInt connect cur_cmd, UInt<1>(0h0) node _T_20 = eq(stream_type[_cur_stream_T], UInt<3>(0h0)) node _T_21 = eq(stream_type[_cur_stream_T], UInt<3>(0h2)) node _T_22 = or(_T_20, _T_21) node _T_23 = eq(stream_type[_cur_stream_T], UInt<3>(0h4)) node _T_24 = or(_T_22, _T_23) when _T_24 : connect cur_cmd, UInt<1>(0h0) else : connect cur_cmd, UInt<1>(0h1) node _io_req_valid_T = bits(s_idx, 3, 0) node _io_req_valid_T_1 = eq(s_sent_done[_io_req_valid_T], UInt<1>(0h0)) connect io.req.valid, _io_req_valid_T_1 connect io.req.bits.data.addr, addr connect io.req.bits.data.cmd, cur_cmd connect io.req.bits.data.size, UInt<3>(0h4) connect io.req.bits.data.data, data connect io.req.bits.idx, s_idx node _T_25 = and(io.req.ready, io.req.valid) when _T_25 : node _T_26 = bits(s_idx, 3, 0) regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "MemReq -> s_idx: %d, s_sent: %d, addr: 0x%x, data: 0x%x streamtype: %d\n", s_idx, s_sent[_T_26], addr, data, stream_type[_cur_stream_T]) : printf_5 node _T_31 = bits(s_idx, 3, 0) when s_sent_done[_T_31] : node _s_idx_T = sub(stream_cnt, UInt<1>(0h1)) node _s_idx_T_1 = tail(_s_idx_T, 1) node _s_idx_T_2 = eq(s_idx, _s_idx_T_1) node _s_idx_T_3 = add(s_idx, UInt<1>(0h1)) node _s_idx_T_4 = tail(_s_idx_T_3, 1) node _s_idx_T_5 = mux(_s_idx_T_2, UInt<1>(0h0), _s_idx_T_4) connect s_idx, _s_idx_T_5 else : node _T_32 = and(io.req.ready, io.req.valid) when _T_32 : node _s_idx_T_6 = sub(stream_cnt, UInt<1>(0h1)) node _s_idx_T_7 = tail(_s_idx_T_6, 1) node _s_idx_T_8 = eq(s_idx, _s_idx_T_7) node _s_idx_T_9 = add(s_idx, UInt<1>(0h1)) node _s_idx_T_10 = tail(_s_idx_T_9, 1) node _s_idx_T_11 = mux(_s_idx_T_8, UInt<1>(0h0), _s_idx_T_10) connect s_idx, _s_idx_T_11 node _T_33 = bits(s_idx, 3, 0) node _s_sent_T = bits(s_idx, 3, 0) node _s_sent_T_1 = add(s_sent[_s_sent_T], UInt<1>(0h1)) node _s_sent_T_2 = tail(_s_sent_T_1, 1) connect s_sent[_T_33], _s_sent_T_2 node _T_34 = bits(s_idx, 3, 0) node _T_35 = sub(max_reqs, UInt<1>(0h1)) node _T_36 = tail(_T_35, 1) node _T_37 = eq(s_sent[_T_34], _T_36) when _T_37 : node _T_38 = bits(s_idx, 3, 0) connect s_sent_done[_T_38], UInt<1>(0h1) wire sent_done_0 : UInt<1> connect sent_done_0, UInt<1>(0h1) node _sent_done_done_T = lt(UInt<1>(0h0), stream_cnt) when _sent_done_done_T : connect sent_done_0, s_sent_done[0] wire sent_done_1 : UInt<1> connect sent_done_1, UInt<1>(0h1) node _sent_done_done_T_1 = lt(UInt<1>(0h1), stream_cnt) when _sent_done_done_T_1 : connect sent_done_1, s_sent_done[1] wire sent_done_2 : UInt<1> connect sent_done_2, UInt<1>(0h1) node _sent_done_done_T_2 = lt(UInt<2>(0h2), stream_cnt) when _sent_done_done_T_2 : connect sent_done_2, s_sent_done[2] wire sent_done_3 : UInt<1> connect sent_done_3, UInt<1>(0h1) node _sent_done_done_T_3 = lt(UInt<2>(0h3), stream_cnt) when _sent_done_done_T_3 : connect sent_done_3, s_sent_done[3] wire sent_done_4 : UInt<1> connect sent_done_4, UInt<1>(0h1) node _sent_done_done_T_4 = lt(UInt<3>(0h4), stream_cnt) when _sent_done_done_T_4 : connect sent_done_4, s_sent_done[4] wire sent_done_5 : UInt<1> connect sent_done_5, UInt<1>(0h1) node _sent_done_done_T_5 = lt(UInt<3>(0h5), stream_cnt) when _sent_done_done_T_5 : connect sent_done_5, s_sent_done[5] wire sent_done_6 : UInt<1> connect sent_done_6, UInt<1>(0h1) node _sent_done_done_T_6 = lt(UInt<3>(0h6), stream_cnt) when _sent_done_done_T_6 : connect sent_done_6, s_sent_done[6] wire sent_done_7 : UInt<1> connect sent_done_7, UInt<1>(0h1) node _sent_done_done_T_7 = lt(UInt<3>(0h7), stream_cnt) when _sent_done_done_T_7 : connect sent_done_7, s_sent_done[7] wire sent_done_8 : UInt<1> connect sent_done_8, UInt<1>(0h1) node _sent_done_done_T_8 = lt(UInt<4>(0h8), stream_cnt) when _sent_done_done_T_8 : connect sent_done_8, s_sent_done[8] wire sent_done_9 : UInt<1> connect sent_done_9, UInt<1>(0h1) node _sent_done_done_T_9 = lt(UInt<4>(0h9), stream_cnt) when _sent_done_done_T_9 : connect sent_done_9, s_sent_done[9] wire sent_done_10 : UInt<1> connect sent_done_10, UInt<1>(0h1) node _sent_done_done_T_10 = lt(UInt<4>(0ha), stream_cnt) when _sent_done_done_T_10 : connect sent_done_10, s_sent_done[10] wire sent_done_11 : UInt<1> connect sent_done_11, UInt<1>(0h1) node _sent_done_done_T_11 = lt(UInt<4>(0hb), stream_cnt) when _sent_done_done_T_11 : connect sent_done_11, s_sent_done[11] wire sent_done_12 : UInt<1> connect sent_done_12, UInt<1>(0h1) node _sent_done_done_T_12 = lt(UInt<4>(0hc), stream_cnt) when _sent_done_done_T_12 : connect sent_done_12, s_sent_done[12] wire sent_done_13 : UInt<1> connect sent_done_13, UInt<1>(0h1) node _sent_done_done_T_13 = lt(UInt<4>(0hd), stream_cnt) when _sent_done_done_T_13 : connect sent_done_13, s_sent_done[13] wire sent_done_14 : UInt<1> connect sent_done_14, UInt<1>(0h1) node _sent_done_done_T_14 = lt(UInt<4>(0he), stream_cnt) when _sent_done_done_T_14 : connect sent_done_14, s_sent_done[14] wire sent_done_15 : UInt<1> connect sent_done_15, UInt<1>(0h1) node _sent_done_done_T_15 = lt(UInt<4>(0hf), stream_cnt) when _sent_done_done_T_15 : connect sent_done_15, s_sent_done[15] node _T_39 = and(sent_done_0, sent_done_1) node _T_40 = and(_T_39, sent_done_2) node _T_41 = and(_T_40, sent_done_3) node _T_42 = and(_T_41, sent_done_4) node _T_43 = and(_T_42, sent_done_5) node _T_44 = and(_T_43, sent_done_6) node _T_45 = and(_T_44, sent_done_7) node _T_46 = and(_T_45, sent_done_8) node _T_47 = and(_T_46, sent_done_9) node _T_48 = and(_T_47, sent_done_10) node _T_49 = and(_T_48, sent_done_11) node _T_50 = and(_T_49, sent_done_12) node _T_51 = and(_T_50, sent_done_13) node _T_52 = and(_T_51, sent_done_14) node _T_53 = and(_T_52, sent_done_15) when _T_53 : connect io.sent_done, UInt<1>(0h1) else : connect io.req.valid, UInt<1>(0h0)	module ReqGen( // @[reqgen.scala:26:7] input clock, // @[reqgen.scala:26:7] input reset, // @[reqgen.scala:26:7] input io_send_reqs, // @[reqgen.scala:27:14] output io_sent_done, // @[reqgen.scala:27:14] output io_req_fire, // @[reqgen.scala:27:14] input io_global_stream_info_valid, // @[reqgen.scala:27:14] input [4:0] io_global_stream_info_bits_stream_cnt, // @[reqgen.scala:27:14] input [63:0] io_global_stream_info_bits_addr_range, // @[reqgen.scala:27:14] input [63:0] io_global_stream_info_bits_max_reqs, // @[reqgen.scala:27:14] input io_local_stream_info_valid, // @[reqgen.scala:27:14] input [63:0] io_local_stream_info_bits_data_start_addr, // @[reqgen.scala:27:14] input [63:0] io_local_stream_info_bits_data_stride, // @[reqgen.scala:27:14] input [2:0] io_local_stream_info_bits_data_stream_type, // @[reqgen.scala:27:14] input [3:0] io_local_stream_info_bits_idx, // @[reqgen.scala:27:14] input io_req_ready, // @[reqgen.scala:27:14] output io_req_valid, // @[reqgen.scala:27:14] output [63:0] io_req_bits_data_addr, // @[reqgen.scala:27:14] output io_req_bits_data_cmd, // @[reqgen.scala:27:14] output [127:0] io_req_bits_data_data, // @[reqgen.scala:27:14] output [3:0] io_req_bits_idx // @[reqgen.scala:27:14] ); wire _rand_val_prng_io_out_0; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_1; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_2; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_3; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_4; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_5; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_6; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_7; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_8; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_9; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_10; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_11; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_12; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_13; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_14; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_15; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_16; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_17; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_18; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_19; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_20; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_21; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_22; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_23; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_24; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_25; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_26; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_27; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_28; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_29; // @[PRNG.scala:91:22] wire io_send_reqs_0 = io_send_reqs; // @[reqgen.scala:26:7] wire io_global_stream_info_valid_0 = io_global_stream_info_valid; // @[reqgen.scala:26:7] wire [4:0] io_global_stream_info_bits_stream_cnt_0 = io_global_stream_info_bits_stream_cnt; // @[reqgen.scala:26:7] wire [63:0] io_global_stream_info_bits_addr_range_0 = io_global_stream_info_bits_addr_range; // @[reqgen.scala:26:7] wire [63:0] io_global_stream_info_bits_max_reqs_0 = io_global_stream_info_bits_max_reqs; // @[reqgen.scala:26:7] wire io_local_stream_info_valid_0 = io_local_stream_info_valid; // @[reqgen.scala:26:7] wire [63:0] io_local_stream_info_bits_data_start_addr_0 = io_local_stream_info_bits_data_start_addr; // @[reqgen.scala:26:7] wire [63:0] io_local_stream_info_bits_data_stride_0 = io_local_stream_info_bits_data_stride; // @[reqgen.scala:26:7] wire [2:0] io_local_stream_info_bits_data_stream_type_0 = io_local_stream_info_bits_data_stream_type; // @[reqgen.scala:26:7] wire [3:0] io_local_stream_info_bits_idx_0 = io_local_stream_info_bits_idx; // @[reqgen.scala:26:7] wire io_req_ready_0 = io_req_ready; // @[reqgen.scala:26:7] wire [2:0] io_req_bits_data_size = 3'h4; // @[reqgen.scala:26:7] wire [63:0] _msb_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[reqgen.scala:89:47] wire [63:0] _msb_T_51 = 64'h5555555555555555; // @[reqgen.scala:89:47] wire [63:0] _msb_T_50 = 64'h6666666666666666; // @[reqgen.scala:89:47] wire [62:0] _msb_T_49 = 63'h3333333333333333; // @[reqgen.scala:89:47] wire [63:0] _msb_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[reqgen.scala:89:47] wire [63:0] _msb_T_41 = 64'h3333333333333333; // @[reqgen.scala:89:47] wire [63:0] _msb_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[reqgen.scala:89:47] wire [61:0] _msb_T_39 = 62'hF0F0F0F0F0F0F0F; // @[reqgen.scala:89:47] wire [63:0] _msb_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[reqgen.scala:89:47] wire [63:0] _msb_T_31 = 64'hF0F0F0F0F0F0F0F; // @[reqgen.scala:89:47] wire [63:0] _msb_T_30 = 64'hFF00FF00FF00FF0; // @[reqgen.scala:89:47] wire [59:0] _msb_T_29 = 60'hFF00FF00FF00FF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_26 = 64'hFF00FF00FF00FF00; // @[reqgen.scala:89:47] wire [63:0] _msb_T_21 = 64'hFF00FF00FF00FF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_20 = 64'hFFFF0000FFFF00; // @[reqgen.scala:89:47] wire [55:0] _msb_T_19 = 56'hFFFF0000FFFF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_16 = 64'hFFFF0000FFFF0000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_11 = 64'hFFFF0000FFFF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_10 = 64'hFFFFFFFF0000; // @[reqgen.scala:89:47] wire [47:0] _msb_T_9 = 48'hFFFFFFFF; // @[reqgen.scala:89:47] wire [63:0] _msb_T = 64'hFFFFFFFF00000000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_6 = 64'hFFFFFFFF00000000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_1 = 64'hFFFFFFFF; // @[reqgen.scala:89:47] wire [255:0] _data_T_2 = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[reqgen.scala:86:32] wire [256:0] _data_T_1 = 257'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[reqgen.scala:86:32] wire _s_sent_done_WIRE_0 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_1 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_2 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_3 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_4 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_5 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_6 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_7 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_8 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_9 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_10 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_11 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_12 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_13 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_14 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_15 = 1'h0; // @[reqgen.scala:81:36] wire [63:0] _start_addr_WIRE_0 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_1 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_2 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_3 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_4 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_5 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_6 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_7 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_8 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_9 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_10 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_11 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_12 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_13 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_14 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_15 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _stride_WIRE_0 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_1 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_2 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_3 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_4 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_5 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_6 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_7 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_8 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_9 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_10 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_11 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_12 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_13 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_14 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_15 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _end_addr_WIRE_0 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_1 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_2 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_3 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_4 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_5 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_6 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_7 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_8 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_9 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_10 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_11 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_12 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_13 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_14 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_15 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _cur_addr_WIRE_0 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_1 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_2 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_3 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_4 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_5 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_6 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_7 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_8 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_9 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_10 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_11 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_12 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_13 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_14 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_15 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _s_sent_WIRE_0 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_1 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_2 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_3 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_4 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_5 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_6 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_7 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_8 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_9 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_10 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_11 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_12 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_13 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_14 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_15 = 64'h0; // @[reqgen.scala:80:36] wire [2:0] _stream_type_WIRE_0 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_1 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_2 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_3 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_4 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_5 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_6 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_7 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_8 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_9 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_10 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_11 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_12 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_13 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_14 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_15 = 3'h0; // @[reqgen.scala:39:39] wire [255:0] _data_T = 256'h100000000000000000000000000000000; // @[reqgen.scala:86:22] wire _io_req_fire_T; // @[Decoupled.scala:51:35] wire [63:0] io_req_bits_data_addr_0; // @[reqgen.scala:26:7] wire io_req_bits_data_cmd_0; // @[reqgen.scala:26:7] wire [127:0] io_req_bits_data_data_0; // @[reqgen.scala:26:7] wire [3:0] io_req_bits_idx_0; // @[reqgen.scala:26:7] wire io_req_valid_0; // @[reqgen.scala:26:7] wire io_sent_done_0; // @[reqgen.scala:26:7] wire io_req_fire_0; // @[reqgen.scala:26:7] wire [1:0] rand_val_lo_lo_lo_hi = {_rand_val_prng_io_out_2, _rand_val_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] rand_val_lo_lo_lo = {rand_val_lo_lo_lo_hi, _rand_val_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_lo_hi_lo = {_rand_val_prng_io_out_4, _rand_val_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_lo_hi_hi = {_rand_val_prng_io_out_6, _rand_val_prng_io_out_5}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_lo_lo_hi = {rand_val_lo_lo_hi_hi, rand_val_lo_lo_hi_lo}; // @[PRNG.scala:95:17] wire [6:0] rand_val_lo_lo = {rand_val_lo_lo_hi, rand_val_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_lo_hi_lo_lo = {_rand_val_prng_io_out_8, _rand_val_prng_io_out_7}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_hi_lo_hi = {_rand_val_prng_io_out_10, _rand_val_prng_io_out_9}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_lo_hi_lo = {rand_val_lo_hi_lo_hi, rand_val_lo_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_lo_hi_hi_lo = {_rand_val_prng_io_out_12, _rand_val_prng_io_out_11}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_hi_hi_hi = {_rand_val_prng_io_out_14, _rand_val_prng_io_out_13}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_lo_hi_hi = {rand_val_lo_hi_hi_hi, rand_val_lo_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] rand_val_lo_hi = {rand_val_lo_hi_hi, rand_val_lo_hi_lo}; // @[PRNG.scala:95:17] wire [14:0] rand_val_lo = {rand_val_lo_hi, rand_val_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_hi_lo_lo_hi = {_rand_val_prng_io_out_17, _rand_val_prng_io_out_16}; // @[PRNG.scala:91:22, :95:17] wire [2:0] rand_val_hi_lo_lo = {rand_val_hi_lo_lo_hi, _rand_val_prng_io_out_15}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_lo_hi_lo = {_rand_val_prng_io_out_19, _rand_val_prng_io_out_18}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_lo_hi_hi = {_rand_val_prng_io_out_21, _rand_val_prng_io_out_20}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_hi_lo_hi = {rand_val_hi_lo_hi_hi, rand_val_hi_lo_hi_lo}; // @[PRNG.scala:95:17] wire [6:0] rand_val_hi_lo = {rand_val_hi_lo_hi, rand_val_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_hi_hi_lo_lo = {_rand_val_prng_io_out_23, _rand_val_prng_io_out_22}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_hi_lo_hi = {_rand_val_prng_io_out_25, _rand_val_prng_io_out_24}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_hi_hi_lo = {rand_val_hi_hi_lo_hi, rand_val_hi_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_hi_hi_hi_lo = {_rand_val_prng_io_out_27, _rand_val_prng_io_out_26}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_hi_hi_hi = {_rand_val_prng_io_out_29, _rand_val_prng_io_out_28}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_hi_hi_hi = {rand_val_hi_hi_hi_hi, rand_val_hi_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] rand_val_hi_hi = {rand_val_hi_hi_hi, rand_val_hi_hi_lo}; // @[PRNG.scala:95:17] wire [14:0] rand_val_hi = {rand_val_hi_hi, rand_val_hi_lo}; // @[PRNG.scala:95:17] wire [29:0] rand_val = {rand_val_hi, rand_val_lo}; // @[PRNG.scala:95:17] reg [4:0] stream_cnt; // @[reqgen.scala:33:31] reg [63:0] addr_range; // @[reqgen.scala:34:31] reg [63:0] max_reqs; // @[reqgen.scala:35:31] reg [63:0] start_addr_0; // @[reqgen.scala:37:31] reg [63:0] start_addr_1; // @[reqgen.scala:37:31] reg [63:0] start_addr_2; // @[reqgen.scala:37:31] reg [63:0] start_addr_3; // @[reqgen.scala:37:31] reg [63:0] start_addr_4; // @[reqgen.scala:37:31] reg [63:0] start_addr_5; // @[reqgen.scala:37:31] reg [63:0] start_addr_6; // @[reqgen.scala:37:31] reg [63:0] start_addr_7; // @[reqgen.scala:37:31] reg [63:0] start_addr_8; // @[reqgen.scala:37:31] reg [63:0] start_addr_9; // @[reqgen.scala:37:31] reg [63:0] start_addr_10; // @[reqgen.scala:37:31] reg [63:0] start_addr_11; // @[reqgen.scala:37:31] reg [63:0] start_addr_12; // @[reqgen.scala:37:31] reg [63:0] start_addr_13; // @[reqgen.scala:37:31] reg [63:0] start_addr_14; // @[reqgen.scala:37:31] reg [63:0] start_addr_15; // @[reqgen.scala:37:31] reg [63:0] stride_0; // @[reqgen.scala:38:31] reg [63:0] stride_1; // @[reqgen.scala:38:31] reg [63:0] stride_2; // @[reqgen.scala:38:31] reg [63:0] stride_3; // @[reqgen.scala:38:31] reg [63:0] stride_4; // @[reqgen.scala:38:31] reg [63:0] stride_5; // @[reqgen.scala:38:31] reg [63:0] stride_6; // @[reqgen.scala:38:31] reg [63:0] stride_7; // @[reqgen.scala:38:31] reg [63:0] stride_8; // @[reqgen.scala:38:31] reg [63:0] stride_9; // @[reqgen.scala:38:31] reg [63:0] stride_10; // @[reqgen.scala:38:31] reg [63:0] stride_11; // @[reqgen.scala:38:31] reg [63:0] stride_12; // @[reqgen.scala:38:31] reg [63:0] stride_13; // @[reqgen.scala:38:31] reg [63:0] stride_14; // @[reqgen.scala:38:31] reg [63:0] stride_15; // @[reqgen.scala:38:31] reg [2:0] stream_type_0; // @[reqgen.scala:39:31] reg [2:0] stream_type_1; // @[reqgen.scala:39:31] reg [2:0] stream_type_2; // @[reqgen.scala:39:31] reg [2:0] stream_type_3; // @[reqgen.scala:39:31] reg [2:0] stream_type_4; // @[reqgen.scala:39:31] reg [2:0] stream_type_5; // @[reqgen.scala:39:31] reg [2:0] stream_type_6; // @[reqgen.scala:39:31] reg [2:0] stream_type_7; // @[reqgen.scala:39:31] reg [2:0] stream_type_8; // @[reqgen.scala:39:31] reg [2:0] stream_type_9; // @[reqgen.scala:39:31] reg [2:0] stream_type_10; // @[reqgen.scala:39:31] reg [2:0] stream_type_11; // @[reqgen.scala:39:31] reg [2:0] stream_type_12; // @[reqgen.scala:39:31] reg [2:0] stream_type_13; // @[reqgen.scala:39:31] reg [2:0] stream_type_14; // @[reqgen.scala:39:31] reg [2:0] stream_type_15; // @[reqgen.scala:39:31] reg [63:0] end_addr_0; // @[reqgen.scala:40:31] reg [63:0] end_addr_1; // @[reqgen.scala:40:31] reg [63:0] end_addr_2; // @[reqgen.scala:40:31] reg [63:0] end_addr_3; // @[reqgen.scala:40:31] reg [63:0] end_addr_4; // @[reqgen.scala:40:31] reg [63:0] end_addr_5; // @[reqgen.scala:40:31] reg [63:0] end_addr_6; // @[reqgen.scala:40:31] reg [63:0] end_addr_7; // @[reqgen.scala:40:31] reg [63:0] end_addr_8; // @[reqgen.scala:40:31] reg [63:0] end_addr_9; // @[reqgen.scala:40:31] reg [63:0] end_addr_10; // @[reqgen.scala:40:31] reg [63:0] end_addr_11; // @[reqgen.scala:40:31] reg [63:0] end_addr_12; // @[reqgen.scala:40:31] reg [63:0] end_addr_13; // @[reqgen.scala:40:31] reg [63:0] end_addr_14; // @[reqgen.scala:40:31] reg [63:0] end_addr_15; // @[reqgen.scala:40:31] reg [63:0] cur_addr_0; // @[reqgen.scala:41:31] reg [63:0] cur_addr_1; // @[reqgen.scala:41:31] reg [63:0] cur_addr_2; // @[reqgen.scala:41:31] reg [63:0] cur_addr_3; // @[reqgen.scala:41:31] reg [63:0] cur_addr_4; // @[reqgen.scala:41:31] reg [63:0] cur_addr_5; // @[reqgen.scala:41:31] reg [63:0] cur_addr_6; // @[reqgen.scala:41:31] reg [63:0] cur_addr_7; // @[reqgen.scala:41:31] reg [63:0] cur_addr_8; // @[reqgen.scala:41:31] reg [63:0] cur_addr_9; // @[reqgen.scala:41:31] reg [63:0] cur_addr_10; // @[reqgen.scala:41:31] reg [63:0] cur_addr_11; // @[reqgen.scala:41:31] reg [63:0] cur_addr_12; // @[reqgen.scala:41:31] reg [63:0] cur_addr_13; // @[reqgen.scala:41:31] reg [63:0] cur_addr_14; // @[reqgen.scala:41:31] reg [63:0] cur_addr_15; // @[reqgen.scala:41:31] assign _io_req_fire_T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] assign io_req_fire_0 = _io_req_fire_T; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles; // @[util.scala:14:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[util.scala:14:33, :15:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[util.scala:15:38] wire [64:0] _end_addr_T = {1'h0, io_local_stream_info_bits_data_start_addr_0} + {1'h0, addr_range}; // @[reqgen.scala:26:7, :34:31, :72:38] wire [63:0] _end_addr_T_1 = _end_addr_T[63:0]; // @[reqgen.scala:72:38] reg [63:0] loginfo_cycles_1; // @[util.scala:14:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[util.scala:14:33, :15:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[util.scala:15:38] reg [4:0] s_idx; // @[reqgen.scala:79:28] reg [63:0] s_sent_0; // @[reqgen.scala:80:28] reg [63:0] s_sent_1; // @[reqgen.scala:80:28] reg [63:0] s_sent_2; // @[reqgen.scala:80:28] reg [63:0] s_sent_3; // @[reqgen.scala:80:28] reg [63:0] s_sent_4; // @[reqgen.scala:80:28] reg [63:0] s_sent_5; // @[reqgen.scala:80:28] reg [63:0] s_sent_6; // @[reqgen.scala:80:28] reg [63:0] s_sent_7; // @[reqgen.scala:80:28] reg [63:0] s_sent_8; // @[reqgen.scala:80:28] reg [63:0] s_sent_9; // @[reqgen.scala:80:28] reg [63:0] s_sent_10; // @[reqgen.scala:80:28] reg [63:0] s_sent_11; // @[reqgen.scala:80:28] reg [63:0] s_sent_12; // @[reqgen.scala:80:28] reg [63:0] s_sent_13; // @[reqgen.scala:80:28] reg [63:0] s_sent_14; // @[reqgen.scala:80:28] reg [63:0] s_sent_15; // @[reqgen.scala:80:28] reg s_sent_done_0; // @[reqgen.scala:81:28] reg s_sent_done_1; // @[reqgen.scala:81:28] reg s_sent_done_2; // @[reqgen.scala:81:28] reg s_sent_done_3; // @[reqgen.scala:81:28] reg s_sent_done_4; // @[reqgen.scala:81:28] reg s_sent_done_5; // @[reqgen.scala:81:28] reg s_sent_done_6; // @[reqgen.scala:81:28] reg s_sent_done_7; // @[reqgen.scala:81:28] reg s_sent_done_8; // @[reqgen.scala:81:28] reg s_sent_done_9; // @[reqgen.scala:81:28] reg s_sent_done_10; // @[reqgen.scala:81:28] reg s_sent_done_11; // @[reqgen.scala:81:28] reg s_sent_done_12; // @[reqgen.scala:81:28] reg s_sent_done_13; // @[reqgen.scala:81:28] reg s_sent_done_14; // @[reqgen.scala:81:28] reg s_sent_done_15; // @[reqgen.scala:81:28] wire [3:0] _cur_stream_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _addr_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _nxt_addr_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _nxt_addr_T_1 = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _addr_T_8 = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _addr_T_9 = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _io_req_valid_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _s_sent_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [63:0] addr; // @[reqgen.scala:85:24] wire [31:0] _data_T_3 = 32'h1 << s_idx; // @[reqgen.scala:79:28, :86:46] wire [255:0] data = {224'hFFFFFFFFFFFFFFFFFFFFFFFF, ~_data_T_3}; // @[reqgen.scala:86:{39,46}] wire [15:0][2:0] _GEN = {{stream_type_15}, {stream_type_14}, {stream_type_13}, {stream_type_12}, {stream_type_11}, {stream_type_10}, {stream_type_9}, {stream_type_8}, {stream_type_7}, {stream_type_6}, {stream_type_5}, {stream_type_4}, {stream_type_3}, {stream_type_2}, {stream_type_1}, {stream_type_0}}; // @[reqgen.scala:39:31, :88:22] wire _T_23 = _GEN[_cur_stream_T] == 3'h4; // @[reqgen.scala:88:22] wire _T_10 = _T_23 \| _GEN[_cur_stream_T] == 3'h5; // @[reqgen.scala:88:{22,41,55}] wire [31:0] _msb_T_2 = addr_range[63:32]; // @[reqgen.scala:34:31, :89:47] wire [63:0] _msb_T_3 = {32'h0, _msb_T_2}; // @[reqgen.scala:89:47] wire [31:0] _msb_T_4 = addr_range[31:0]; // @[reqgen.scala:34:31, :89:47] wire [63:0] _msb_T_5 = {_msb_T_4, 32'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_7 = _msb_T_5 & 64'hFFFFFFFF00000000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_8 = _msb_T_3 \| _msb_T_7; // @[reqgen.scala:89:47] wire [47:0] _msb_T_12 = _msb_T_8[63:16]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_13 = {16'h0, _msb_T_12 & 48'hFFFF0000FFFF}; // @[reqgen.scala:89:47] wire [47:0] _msb_T_14 = _msb_T_8[47:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_15 = {_msb_T_14, 16'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_17 = _msb_T_15 & 64'hFFFF0000FFFF0000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_18 = _msb_T_13 \| _msb_T_17; // @[reqgen.scala:89:47] wire [55:0] _msb_T_22 = _msb_T_18[63:8]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_23 = {8'h0, _msb_T_22 & 56'hFF00FF00FF00FF}; // @[reqgen.scala:89:47] wire [55:0] _msb_T_24 = _msb_T_18[55:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_25 = {_msb_T_24, 8'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_27 = _msb_T_25 & 64'hFF00FF00FF00FF00; // @[reqgen.scala:89:47] wire [63:0] _msb_T_28 = _msb_T_23 \| _msb_T_27; // @[reqgen.scala:89:47] wire [59:0] _msb_T_32 = _msb_T_28[63:4]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_33 = {4'h0, _msb_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[reqgen.scala:89:47] wire [59:0] _msb_T_34 = _msb_T_28[59:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_35 = {_msb_T_34, 4'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_37 = _msb_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[reqgen.scala:89:47] wire [63:0] _msb_T_38 = _msb_T_33 \| _msb_T_37; // @[reqgen.scala:89:47] wire [61:0] _msb_T_42 = _msb_T_38[63:2]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_43 = {2'h0, _msb_T_42 & 62'h3333333333333333}; // @[reqgen.scala:89:47] wire [61:0] _msb_T_44 = _msb_T_38[61:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_45 = {_msb_T_44, 2'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_47 = _msb_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[reqgen.scala:89:47] wire [63:0] _msb_T_48 = _msb_T_43 \| _msb_T_47; // @[reqgen.scala:89:47] wire [62:0] _msb_T_52 = _msb_T_48[63:1]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_53 = {1'h0, _msb_T_52 & 63'h5555555555555555}; // @[reqgen.scala:89:47] wire [62:0] _msb_T_54 = _msb_T_48[62:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_55 = {_msb_T_54, 1'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_57 = _msb_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[reqgen.scala:89:47] wire [63:0] _msb_T_58 = _msb_T_53 \| _msb_T_57; // @[reqgen.scala:89:47] wire _msb_T_59 = _msb_T_58[0]; // @[OneHot.scala:48:45] wire _msb_T_60 = _msb_T_58[1]; // @[OneHot.scala:48:45] wire _msb_T_61 = _msb_T_58[2]; // @[OneHot.scala:48:45] wire _msb_T_62 = _msb_T_58[3]; // @[OneHot.scala:48:45] wire _msb_T_63 = _msb_T_58[4]; // @[OneHot.scala:48:45] wire _msb_T_64 = _msb_T_58[5]; // @[OneHot.scala:48:45] wire _msb_T_65 = _msb_T_58[6]; // @[OneHot.scala:48:45] wire _msb_T_66 = _msb_T_58[7]; // @[OneHot.scala:48:45] wire _msb_T_67 = _msb_T_58[8]; // @[OneHot.scala:48:45] wire _msb_T_68 = _msb_T_58[9]; // @[OneHot.scala:48:45] wire _msb_T_69 = _msb_T_58[10]; // @[OneHot.scala:48:45] wire _msb_T_70 = _msb_T_58[11]; // @[OneHot.scala:48:45] wire _msb_T_71 = _msb_T_58[12]; // @[OneHot.scala:48:45] wire _msb_T_72 = _msb_T_58[13]; // @[OneHot.scala:48:45] wire _msb_T_73 = _msb_T_58[14]; // @[OneHot.scala:48:45] wire _msb_T_74 = _msb_T_58[15]; // @[OneHot.scala:48:45] wire _msb_T_75 = _msb_T_58[16]; // @[OneHot.scala:48:45] wire _msb_T_76 = _msb_T_58[17]; // @[OneHot.scala:48:45] wire _msb_T_77 = _msb_T_58[18]; // @[OneHot.scala:48:45] wire _msb_T_78 = _msb_T_58[19]; // @[OneHot.scala:48:45] wire _msb_T_79 = _msb_T_58[20]; // @[OneHot.scala:48:45] wire _msb_T_80 = _msb_T_58[21]; // @[OneHot.scala:48:45] wire _msb_T_81 = _msb_T_58[22]; // @[OneHot.scala:48:45] wire _msb_T_82 = _msb_T_58[23]; // @[OneHot.scala:48:45] wire _msb_T_83 = _msb_T_58[24]; // @[OneHot.scala:48:45] wire _msb_T_84 = _msb_T_58[25]; // @[OneHot.scala:48:45] wire _msb_T_85 = _msb_T_58[26]; // @[OneHot.scala:48:45] wire _msb_T_86 = _msb_T_58[27]; // @[OneHot.scala:48:45] wire _msb_T_87 = _msb_T_58[28]; // @[OneHot.scala:48:45] wire _msb_T_88 = _msb_T_58[29]; // @[OneHot.scala:48:45] wire _msb_T_89 = _msb_T_58[30]; // @[OneHot.scala:48:45] wire _msb_T_90 = _msb_T_58[31]; // @[OneHot.scala:48:45] wire _msb_T_91 = _msb_T_58[32]; // @[OneHot.scala:48:45] wire _msb_T_92 = _msb_T_58[33]; // @[OneHot.scala:48:45] wire _msb_T_93 = _msb_T_58[34]; // @[OneHot.scala:48:45] wire _msb_T_94 = _msb_T_58[35]; // @[OneHot.scala:48:45] wire _msb_T_95 = _msb_T_58[36]; // @[OneHot.scala:48:45] wire _msb_T_96 = _msb_T_58[37]; // @[OneHot.scala:48:45] wire _msb_T_97 = _msb_T_58[38]; // @[OneHot.scala:48:45] wire _msb_T_98 = _msb_T_58[39]; // @[OneHot.scala:48:45] wire _msb_T_99 = _msb_T_58[40]; // @[OneHot.scala:48:45] wire _msb_T_100 = _msb_T_58[41]; // @[OneHot.scala:48:45] wire _msb_T_101 = _msb_T_58[42]; // @[OneHot.scala:48:45] wire _msb_T_102 = _msb_T_58[43]; // @[OneHot.scala:48:45] wire _msb_T_103 = _msb_T_58[44]; // @[OneHot.scala:48:45] wire _msb_T_104 = _msb_T_58[45]; // @[OneHot.scala:48:45] wire _msb_T_105 = _msb_T_58[46]; // @[OneHot.scala:48:45] wire _msb_T_106 = _msb_T_58[47]; // @[OneHot.scala:48:45] wire _msb_T_107 = _msb_T_58[48]; // @[OneHot.scala:48:45] wire _msb_T_108 = _msb_T_58[49]; // @[OneHot.scala:48:45] wire _msb_T_109 = _msb_T_58[50]; // @[OneHot.scala:48:45] wire _msb_T_110 = _msb_T_58[51]; // @[OneHot.scala:48:45] wire _msb_T_111 = _msb_T_58[52]; // @[OneHot.scala:48:45] wire _msb_T_112 = _msb_T_58[53]; // @[OneHot.scala:48:45] wire _msb_T_113 = _msb_T_58[54]; // @[OneHot.scala:48:45] wire _msb_T_114 = _msb_T_58[55]; // @[OneHot.scala:48:45] wire _msb_T_115 = _msb_T_58[56]; // @[OneHot.scala:48:45] wire _msb_T_116 = _msb_T_58[57]; // @[OneHot.scala:48:45] wire _msb_T_117 = _msb_T_58[58]; // @[OneHot.scala:48:45] wire _msb_T_118 = _msb_T_58[59]; // @[OneHot.scala:48:45] wire _msb_T_119 = _msb_T_58[60]; // @[OneHot.scala:48:45] wire _msb_T_120 = _msb_T_58[61]; // @[OneHot.scala:48:45] wire _msb_T_121 = _msb_T_58[62]; // @[OneHot.scala:48:45] wire _msb_T_122 = _msb_T_58[63]; // @[OneHot.scala:48:45] wire [5:0] _msb_T_123 = {5'h1F, ~_msb_T_121}; // @[OneHot.scala:48:45] wire [5:0] _msb_T_124 = _msb_T_120 ? 6'h3D : _msb_T_123; // @[OneHot.scala:48:45] wire [5:0] _msb_T_125 = _msb_T_119 ? 6'h3C : _msb_T_124; // @[OneHot.scala:48:45] wire [5:0] _msb_T_126 = _msb_T_118 ? 6'h3B : _msb_T_125; // @[OneHot.scala:48:45] wire [5:0] _msb_T_127 = _msb_T_117 ? 6'h3A : _msb_T_126; // @[OneHot.scala:48:45] wire [5:0] _msb_T_128 = _msb_T_116 ? 6'h39 : _msb_T_127; // @[OneHot.scala:48:45] wire [5:0] _msb_T_129 = _msb_T_115 ? 6'h38 : _msb_T_128; // @[OneHot.scala:48:45] wire [5:0] _msb_T_130 = _msb_T_114 ? 6'h37 : _msb_T_129; // @[OneHot.scala:48:45] wire [5:0] _msb_T_131 = _msb_T_113 ? 6'h36 : _msb_T_130; // @[OneHot.scala:48:45] wire [5:0] _msb_T_132 = _msb_T_112 ? 6'h35 : _msb_T_131; // @[OneHot.scala:48:45] wire [5:0] _msb_T_133 = _msb_T_111 ? 6'h34 : _msb_T_132; // @[OneHot.scala:48:45] wire [5:0] _msb_T_134 = _msb_T_110 ? 6'h33 : _msb_T_133; // @[OneHot.scala:48:45] wire [5:0] _msb_T_135 = _msb_T_109 ? 6'h32 : _msb_T_134; // @[OneHot.scala:48:45] wire [5:0] _msb_T_136 = _msb_T_108 ? 6'h31 : _msb_T_135; // @[OneHot.scala:48:45] wire [5:0] _msb_T_137 = _msb_T_107 ? 6'h30 : _msb_T_136; // @[OneHot.scala:48:45] wire [5:0] _msb_T_138 = _msb_T_106 ? 6'h2F : _msb_T_137; // @[OneHot.scala:48:45] wire [5:0] _msb_T_139 = _msb_T_105 ? 6'h2E : _msb_T_138; // @[OneHot.scala:48:45] wire [5:0] _msb_T_140 = _msb_T_104 ? 6'h2D : _msb_T_139; // @[OneHot.scala:48:45] wire [5:0] _msb_T_141 = _msb_T_103 ? 6'h2C : _msb_T_140; // @[OneHot.scala:48:45] wire [5:0] _msb_T_142 = _msb_T_102 ? 6'h2B : _msb_T_141; // @[OneHot.scala:48:45] wire [5:0] _msb_T_143 = _msb_T_101 ? 6'h2A : _msb_T_142; // @[OneHot.scala:48:45] wire [5:0] _msb_T_144 = _msb_T_100 ? 6'h29 : _msb_T_143; // @[OneHot.scala:48:45] wire [5:0] _msb_T_145 = _msb_T_99 ? 6'h28 : _msb_T_144; // @[OneHot.scala:48:45] wire [5:0] _msb_T_146 = _msb_T_98 ? 6'h27 : _msb_T_145; // @[OneHot.scala:48:45] wire [5:0] _msb_T_147 = _msb_T_97 ? 6'h26 : _msb_T_146; // @[OneHot.scala:48:45] wire [5:0] _msb_T_148 = _msb_T_96 ? 6'h25 : _msb_T_147; // @[OneHot.scala:48:45] wire [5:0] _msb_T_149 = _msb_T_95 ? 6'h24 : _msb_T_148; // @[OneHot.scala:48:45] wire [5:0] _msb_T_150 = _msb_T_94 ? 6'h23 : _msb_T_149; // @[OneHot.scala:48:45] wire [5:0] _msb_T_151 = _msb_T_93 ? 6'h22 : _msb_T_150; // @[OneHot.scala:48:45] wire [5:0] _msb_T_152 = _msb_T_92 ? 6'h21 : _msb_T_151; // @[OneHot.scala:48:45] wire [5:0] _msb_T_153 = _msb_T_91 ? 6'h20 : _msb_T_152; // @[OneHot.scala:48:45] wire [5:0] _msb_T_154 = _msb_T_90 ? 6'h1F : _msb_T_153; // @[OneHot.scala:48:45] wire [5:0] _msb_T_155 = _msb_T_89 ? 6'h1E : _msb_T_154; // @[OneHot.scala:48:45] wire [5:0] _msb_T_156 = _msb_T_88 ? 6'h1D : _msb_T_155; // @[OneHot.scala:48:45] wire [5:0] _msb_T_157 = _msb_T_87 ? 6'h1C : _msb_T_156; // @[OneHot.scala:48:45] wire [5:0] _msb_T_158 = _msb_T_86 ? 6'h1B : _msb_T_157; // @[OneHot.scala:48:45] wire [5:0] _msb_T_159 = _msb_T_85 ? 6'h1A : _msb_T_158; // @[OneHot.scala:48:45] wire [5:0] _msb_T_160 = _msb_T_84 ? 6'h19 : _msb_T_159; // @[OneHot.scala:48:45] wire [5:0] _msb_T_161 = _msb_T_83 ? 6'h18 : _msb_T_160; // @[OneHot.scala:48:45] wire [5:0] _msb_T_162 = _msb_T_82 ? 6'h17 : _msb_T_161; // @[OneHot.scala:48:45] wire [5:0] _msb_T_163 = _msb_T_81 ? 6'h16 : _msb_T_162; // @[OneHot.scala:48:45] wire [5:0] _msb_T_164 = _msb_T_80 ? 6'h15 : _msb_T_163; // @[OneHot.scala:48:45] wire [5:0] _msb_T_165 = _msb_T_79 ? 6'h14 : _msb_T_164; // @[OneHot.scala:48:45] wire [5:0] _msb_T_166 = _msb_T_78 ? 6'h13 : _msb_T_165; // @[OneHot.scala:48:45] wire [5:0] _msb_T_167 = _msb_T_77 ? 6'h12 : _msb_T_166; // @[OneHot.scala:48:45] wire [5:0] _msb_T_168 = _msb_T_76 ? 6'h11 : _msb_T_167; // @[OneHot.scala:48:45] wire [5:0] _msb_T_169 = _msb_T_75 ? 6'h10 : _msb_T_168; // @[OneHot.scala:48:45] wire [5:0] _msb_T_170 = _msb_T_74 ? 6'hF : _msb_T_169; // @[OneHot.scala:48:45] wire [5:0] _msb_T_171 = _msb_T_73 ? 6'hE : _msb_T_170; // @[OneHot.scala:48:45] wire [5:0] _msb_T_172 = _msb_T_72 ? 6'hD : _msb_T_171; // @[OneHot.scala:48:45] wire [5:0] _msb_T_173 = _msb_T_71 ? 6'hC : _msb_T_172; // @[OneHot.scala:48:45] wire [5:0] _msb_T_174 = _msb_T_70 ? 6'hB : _msb_T_173; // @[OneHot.scala:48:45] wire [5:0] _msb_T_175 = _msb_T_69 ? 6'hA : _msb_T_174; // @[OneHot.scala:48:45] wire [5:0] _msb_T_176 = _msb_T_68 ? 6'h9 : _msb_T_175; // @[OneHot.scala:48:45] wire [5:0] _msb_T_177 = _msb_T_67 ? 6'h8 : _msb_T_176; // @[OneHot.scala:48:45] wire [5:0] _msb_T_178 = _msb_T_66 ? 6'h7 : _msb_T_177; // @[OneHot.scala:48:45] wire [5:0] _msb_T_179 = _msb_T_65 ? 6'h6 : _msb_T_178; // @[OneHot.scala:48:45] wire [5:0] _msb_T_180 = _msb_T_64 ? 6'h5 : _msb_T_179; // @[OneHot.scala:48:45] wire [5:0] _msb_T_181 = _msb_T_63 ? 6'h4 : _msb_T_180; // @[OneHot.scala:48:45] wire [5:0] _msb_T_182 = _msb_T_62 ? 6'h3 : _msb_T_181; // @[OneHot.scala:48:45] wire [5:0] _msb_T_183 = _msb_T_61 ? 6'h2 : _msb_T_182; // @[OneHot.scala:48:45] wire [5:0] _msb_T_184 = _msb_T_60 ? 6'h1 : _msb_T_183; // @[OneHot.scala:48:45] wire [5:0] _msb_T_185 = _msb_T_59 ? 6'h0 : _msb_T_184; // @[OneHot.scala:48:45] wire [7:0] _msb_T_186 = 8'h40 - {2'h0, _msb_T_185}; // @[Mux.scala:50:70] wire [6:0] msb = _msb_T_186[6:0]; // @[reqgen.scala:89:22] wire [36:0] _addr_T_1 = {3'h0, rand_val, 4'h0}; // @[PRNG.scala:95:17] wire [127:0] _addr_T_2 = 128'h1 << msb; // @[reqgen.scala:89:22, :90:62] wire [128:0] _addr_T_3 = {1'h0, _addr_T_2} - 129'h1; // @[reqgen.scala:90:{62,70}] wire [127:0] _addr_T_4 = _addr_T_3[127:0]; // @[reqgen.scala:90:70] wire [127:0] _addr_T_5 = {91'h0, _addr_T_4[36:0] & _addr_T_1}; // @[reqgen.scala:90:{46,54,70}] wire [15:0][63:0] _GEN_0 = {{start_addr_15}, {start_addr_14}, {start_addr_13}, {start_addr_12}, {start_addr_11}, {start_addr_10}, {start_addr_9}, {start_addr_8}, {start_addr_7}, {start_addr_6}, {start_addr_5}, {start_addr_4}, {start_addr_3}, {start_addr_2}, {start_addr_1}, {start_addr_0}}; // @[reqgen.scala:37:31, :90:33] wire [128:0] _addr_T_6 = {65'h0, _GEN_0[_addr_T]} + {1'h0, _addr_T_5}; // @[reqgen.scala:90:{33,54}] wire [127:0] _addr_T_7 = _addr_T_6[127:0]; // @[reqgen.scala:90:33] wire _T_13 = ~(\|_GEN[_cur_stream_T]) \| _GEN[_cur_stream_T] == 3'h1; // @[reqgen.scala:88:22, :91:{28,49,63}] wire [15:0][63:0] _GEN_1 = {{cur_addr_15}, {cur_addr_14}, {cur_addr_13}, {cur_addr_12}, {cur_addr_11}, {cur_addr_10}, {cur_addr_9}, {cur_addr_8}, {cur_addr_7}, {cur_addr_6}, {cur_addr_5}, {cur_addr_4}, {cur_addr_3}, {cur_addr_2}, {cur_addr_1}, {cur_addr_0}}; // @[reqgen.scala:41:31, :92:38] wire [15:0][63:0] _GEN_2 = {{stride_15}, {stride_14}, {stride_13}, {stride_12}, {stride_11}, {stride_10}, {stride_9}, {stride_8}, {stride_7}, {stride_6}, {stride_5}, {stride_4}, {stride_3}, {stride_2}, {stride_1}, {stride_0}}; // @[reqgen.scala:38:31, :92:38] wire [64:0] _nxt_addr_T_2 = {1'h0, _GEN_1[_nxt_addr_T]} + {1'h0, _GEN_2[_nxt_addr_T_1]}; // @[reqgen.scala:92:38] wire [63:0] nxt_addr = _nxt_addr_T_2[63:0]; // @[reqgen.scala:92:38] wire [15:0][63:0] _GEN_3 = {{end_addr_15}, {end_addr_14}, {end_addr_13}, {end_addr_12}, {end_addr_11}, {end_addr_10}, {end_addr_9}, {end_addr_8}, {end_addr_7}, {end_addr_6}, {end_addr_5}, {end_addr_4}, {end_addr_3}, {end_addr_2}, {end_addr_1}, {end_addr_0}}; // @[reqgen.scala:40:31, :93:22] assign addr = _T_10 ? _addr_T_7[63:0] : _T_13 ? (nxt_addr >= _GEN_3[s_idx[3:0]] ? _GEN_0[_addr_T_8] : nxt_addr) : _GEN[_cur_stream_T] == 3'h2 \| _GEN[_cur_stream_T] == 3'h3 ? _GEN_0[_addr_T_9] : 64'h0; // @[reqgen.scala:79:28, :85:24, :88:{22,41,75}, :90:{12,33}, :91:{49,85}, :92:38, :93:{22,42}, :94:14, :96:14, :99:{28,48,62,83}, :103:12] wire cur_cmd; // @[reqgen.scala:106:27] assign cur_cmd = ~(~(\|_GEN[_cur_stream_T]) \| _GEN[_cur_stream_T] == 3'h2 \| _T_23); // @[reqgen.scala:88:22, :91:28, :106:27, :107:{22,43}, :108:{22,42}, :109:42, :110:15, :112:15] wire [15:0] _GEN_4 = {{s_sent_done_15}, {s_sent_done_14}, {s_sent_done_13}, {s_sent_done_12}, {s_sent_done_11}, {s_sent_done_10}, {s_sent_done_9}, {s_sent_done_8}, {s_sent_done_7}, {s_sent_done_6}, {s_sent_done_5}, {s_sent_done_4}, {s_sent_done_3}, {s_sent_done_2}, {s_sent_done_1}, {s_sent_done_0}}; // @[reqgen.scala:81:28, :115:25] wire _io_req_valid_T_1 = ~_GEN_4[_io_req_valid_T]; // @[reqgen.scala:115:25] assign io_req_bits_data_addr_0 = io_send_reqs_0 ? addr : 64'h0; // @[reqgen.scala:26:7, :47:25, :83:23, :85:24, :116:27] assign io_req_bits_data_cmd_0 = io_send_reqs_0 & cur_cmd; // @[reqgen.scala:26:7, :48:25, :83:23, :106:27, :117:27] assign io_req_bits_data_data_0 = io_send_reqs_0 ? data[127:0] : 128'h0; // @[reqgen.scala:26:7, :50:25, :83:23, :86:39, :119:27] assign io_req_bits_idx_0 = io_send_reqs_0 ? s_idx[3:0] : 4'h0; // @[reqgen.scala:26:7, :51:19, :79:28, :83:23, :120:21] reg [63:0] loginfo_cycles_2; // @[util.scala:14:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[util.scala:14:33, :15:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[util.scala:15:38] wire [15:0][63:0] _GEN_5 = {{s_sent_15}, {s_sent_14}, {s_sent_13}, {s_sent_12}, {s_sent_11}, {s_sent_10}, {s_sent_9}, {s_sent_8}, {s_sent_7}, {s_sent_6}, {s_sent_5}, {s_sent_4}, {s_sent_3}, {s_sent_2}, {s_sent_1}, {s_sent_0}}; // @[util.scala:22:13] wire [63:0] _GEN_6 = _GEN_5[s_idx[3:0]]; // @[util.scala:22:13]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_153 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_153( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[1]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of SystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst xbar of IntXbar_i1_o1_1 inst xbar_1 of IntXbar_i1_o1_2 inst xbar_2 of IntXbar_i1_o1_3 inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1 inst broadcast of BundleBridgeNexus_UInt32_1 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_5 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_1 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[1] invalidate tileHaltSinkNodeIn[0] wire tileWFISinkNodeIn : UInt<1>[1] invalidate tileWFISinkNodeIn[0] wire tileCeaseSinkNodeIn : UInt<1>[1] invalidate tileCeaseSinkNodeIn[0] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}} invalidate traceNodesIn.custom.rob_empty invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid invalidate traceNodesIn.insns[1].tval invalidate traceNodesIn.insns[1].cause invalidate traceNodesIn.insns[1].interrupt invalidate traceNodesIn.insns[1].exception invalidate traceNodesIn.insns[1].priv invalidate traceNodesIn.insns[1].insn invalidate traceNodesIn.insns[1].iaddr invalidate traceNodesIn.insns[1].valid invalidate traceNodesIn.insns[2].tval invalidate traceNodesIn.insns[2].cause invalidate traceNodesIn.insns[2].interrupt invalidate traceNodesIn.insns[2].exception invalidate traceNodesIn.insns[2].priv invalidate traceNodesIn.insns[2].insn invalidate traceNodesIn.insns[2].iaddr invalidate traceNodesIn.insns[2].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_boom_tile_hartid_in, tileHartIdNexusNode.auto.out connect tile_prci_domain.auto.element_reset_domain_boom_tile_reset_vector_in, broadcast.auto.out connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect sbus.auto.coupler_from_boom_tile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell	module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9] wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [4:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [10:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [15:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7] wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7] wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7] wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7] wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7] wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7] wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7] wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7] wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7] wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7] wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7] wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [39:0] nexus_auto_in_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_1_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_1_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_2_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_2_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_1_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_1_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_2_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_2_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_nodeIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_1_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_1_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_2_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_2_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_1_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_1_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_2_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_2_tval = 40'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_auto_in_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_1_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_2_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_1_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_2_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_nodeIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_1_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_2_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] nexus_nodeOut_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] nexus_nodeOut_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_insns_1_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_insns_2_cause = 64'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_auto_in_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_1_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_2_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_1_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_2_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_nodeIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_1_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_2_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nexus_nodeOut_insns_1_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nexus_nodeOut_insns_2_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] traceNodesIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceNodesIn_insns_1_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceNodesIn_insns_2_priv = 3'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_auto_in_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_1_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_2_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_1_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_2_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_nodeIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_1_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_2_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_nodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_nodeOut_insns_2_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_1_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_2_insn = 32'h0; // @[MixedNode.scala:551:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_auto_in_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_nodeIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileWFISinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17] wire ioNodeIn_txd; // @[MixedNode.scala:551:17] wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17] wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7] wire debug_ndreset; // @[DigitalTop.scala:47:7] wire debug_dmactive_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] wire uart_0_txd_0; // @[DigitalTop.scala:47:7] wire clockTapIn_clock; // @[MixedNode.scala:551:17] wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9] wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9] wire ibus_childClock; // @[LazyModuleImp.scala:155:31] wire ibus_childReset; // @[LazyModuleImp.scala:158:31] assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17] wire nexus_nodeIn_custom_rob_empty = nexus_auto_in_custom_rob_empty; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17] wire traceNodesIn_custom_rob_empty = nexus_auto_out_custom_rob_empty; // @[MixedNode.scala:551:17] assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_custom_rob_empty = nexus_nodeIn_custom_rob_empty; // @[MixedNode.scala:542:17, :551:17] assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17] assign nexus_auto_out_custom_rob_empty = nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17] wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17] assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire domainIn_clock; // @[MixedNode.scala:551:17] wire domainIn_reset; // @[MixedNode.scala:551:17] wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17] wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17] assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24] wire int_rtc_tick; // @[Counter.scala:117:24] assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24] wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24] wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge) IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27] .auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9] .auto_anon_out_0 (ibus_auto_int_bus_anon_out_0) ); // @[InterruptBus.scala:19:27] SystemBus sbus ( // @[SystemBus.scala:31:26] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), // @[HasTiles.scala:163:38] .auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), .auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset), .auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock), .auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset), .auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), .auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) ); // @[SystemBus.scala:31:26] PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44] .auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset), .auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17] .auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt) ); // @[PeripheryBus.scala:37:26] FrontBus fbus ( // @[FrontBus.scala:23:26] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset), .auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17] .auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26] ); // @[FrontBus.scala:23:26] PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), .auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), .auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26] .auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), .auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), .auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), .auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), .auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), .auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset), .auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), .auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset), .auto_fixedClockNode_anon_out_2_clock (domainIn_clock), .auto_fixedClockNode_anon_out_2_reset (domainIn_reset), .auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), .auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17] .auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), .custom_boot (custom_boot) ); // @[PeripheryBus.scala:37:26] MemoryBus mbus ( // @[MemoryBus.scala:30:26] .auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28] .auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17] .auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset), .auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17] .auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt) ); // @[MemoryBus.scala:30:26] CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), .auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), .auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), .auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), .auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), .auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), .auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), .auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), .auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), .auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), .auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), .auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), .auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), .auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), .auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26] .auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), .auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), .auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), .auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), .auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), .auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), .auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26] .auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26] ); // @[BankedCoherenceParams.scala:56:31] TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38] .auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17] .auto_element_reset_domain_boom_tile_trace_source_out_time (nexus_auto_in_time), .auto_element_reset_domain_boom_tile_trace_source_out_custom_rob_empty (nexus_auto_in_custom_rob_empty), .auto_element_reset_domain_boom_tile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39] .auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28] .auto_tl_master_clock_xing_out_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), .auto_tl_master_clock_xing_out_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), .auto_tl_master_clock_xing_out_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), .auto_tl_master_clock_xing_out_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), .auto_tl_master_clock_xing_out_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), .auto_tl_master_clock_xing_out_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), .auto_tl_master_clock_xing_out_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), .auto_tl_master_clock_xing_out_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), .auto_tl_master_clock_xing_out_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), .auto_tl_master_clock_xing_out_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), .auto_tl_master_clock_xing_out_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), .auto_tl_master_clock_xing_out_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), .auto_tl_master_clock_xing_out_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), .auto_tl_master_clock_xing_out_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), .auto_tl_master_clock_xing_out_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), .auto_tl_master_clock_xing_out_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), .auto_tl_master_clock_xing_out_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), .auto_tl_master_clock_xing_out_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), .auto_tl_master_clock_xing_out_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), .auto_tl_master_clock_xing_out_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), .auto_tl_master_clock_xing_out_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), .auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26] .auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26] ); // @[HasTiles.scala:163:38] IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26] IntXbar_i1_o1_2 xbar_1 (); // @[Xbar.scala:52:26] IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26] BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39] .auto_out (_tileHartIdNexusNode_auto_out) ); // @[HasTiles.scala:75:39] CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28] .auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready), .auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid), .auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), .auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), .auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), .auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), .auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), .auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26] .tick (int_rtc_tick), // @[Counter.scala:117:24] .clock (_clint_domain_clock), .reset (_clint_domain_reset) ); // @[BusWrapper.scala:89:28] PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28] .auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9] .auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready), .auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid), .auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), .auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), .auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), .auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), .auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), .auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] TLDebugModule tlDM ( // @[Periphery.scala:88:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), .auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), .auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), .auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), .auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), .auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), .auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), .auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), .auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0), .io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7] .io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7] .io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17] .io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17] .io_ctrl_ndreset (debug_ndreset), .io_ctrl_dmactive (debug_dmactive_0), .io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7] .io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), .io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), .io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), .io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), .io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:88:26] DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75] BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28] .auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), .auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), .auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), .auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), .auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ScratchpadBank bank ( // @[Scratchpad.scala:65:28] .auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), .auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), .auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), .auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), .auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), .auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26] .auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26] ); // @[Scratchpad.scala:65:28] SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38] .auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), .auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), .auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), .auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), .auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), .auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), .auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), .auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), .auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), .auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), .auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26] .auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26] .serial_tl_0_in_ready (serial_tl_0_in_ready_0), .serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7] .serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_valid (serial_tl_0_out_valid_0), .serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0), .serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7] .serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy), .serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy) ); // @[PeripheryTLSerial.scala:116:38] TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44] .auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0), .auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), .auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), .auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), .auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), .auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), .auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), .auto_uart_0_io_out_txd (ioNodeIn_txd), .auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17] .auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26] ); // @[UART.scala:270:44] IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (ibus_auto_int_bus_anon_in_0) ); // @[Crossing.scala:109:29] ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28] .auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7] .auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7] .auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), .auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), .auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30] .auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock), .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset), .auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock), .auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset), .auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock), .auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset), .auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock), .auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset), .auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock), .auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset), .auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock), .auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset), .auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock), .auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset) ); // @[HasChipyardPRCI.scala:51:30] ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15] .auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock), .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset), .auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset) ); // @[ClockGroupCombiner.scala:19:15] ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40] .auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26] .auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26] ); // @[GlobalNoC.scala:45:40] BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44] DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21] .io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26] .io_dmi_req_valid (_dtm_io_dmi_req_valid), .io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), .io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), .io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), .io_dmi_resp_ready (_dtm_io_dmi_resp_ready), .io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26] .io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26] .io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26] .io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7] .io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7] .io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0), .io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven), .rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:166:21] assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7] assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_73 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_159 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_160 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_73( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_23 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_d : { bits : UInt<32>}, out_a : { bits : UInt<32>}, out_b : { bits : UInt<32>}, out_c : { bits : UInt<32>}, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<4>, out_id : UInt<4>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_7 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : { bits : UInt<32>}, clock reg c2 : { bits : UInt<32>}, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a.bits, io.in_a.bits reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node io_out_c_self_rec_rawIn_sign = bits(c1.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn = bits(c1.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn = bits(c1.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn = eq(io_out_c_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn = eq(io_out_c_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T = bits(io_out_c_self_rec_rawIn_fractIn, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_1 = bits(io_out_c_self_rec_rawIn_fractIn, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_2 = bits(io_out_c_self_rec_rawIn_fractIn, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_3 = bits(io_out_c_self_rec_rawIn_fractIn, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_4 = bits(io_out_c_self_rec_rawIn_fractIn, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_5 = bits(io_out_c_self_rec_rawIn_fractIn, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_6 = bits(io_out_c_self_rec_rawIn_fractIn, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_7 = bits(io_out_c_self_rec_rawIn_fractIn, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_8 = bits(io_out_c_self_rec_rawIn_fractIn, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_9 = bits(io_out_c_self_rec_rawIn_fractIn, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_10 = bits(io_out_c_self_rec_rawIn_fractIn, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_11 = bits(io_out_c_self_rec_rawIn_fractIn, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_12 = bits(io_out_c_self_rec_rawIn_fractIn, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_13 = bits(io_out_c_self_rec_rawIn_fractIn, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_14 = bits(io_out_c_self_rec_rawIn_fractIn, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_15 = bits(io_out_c_self_rec_rawIn_fractIn, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_16 = bits(io_out_c_self_rec_rawIn_fractIn, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_17 = bits(io_out_c_self_rec_rawIn_fractIn, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_18 = bits(io_out_c_self_rec_rawIn_fractIn, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_19 = bits(io_out_c_self_rec_rawIn_fractIn, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_20 = bits(io_out_c_self_rec_rawIn_fractIn, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_21 = bits(io_out_c_self_rec_rawIn_fractIn, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_22 = bits(io_out_c_self_rec_rawIn_fractIn, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_23 = mux(_io_out_c_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_24 = mux(_io_out_c_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_23) node _io_out_c_self_rec_rawIn_normDist_T_25 = mux(_io_out_c_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_24) node _io_out_c_self_rec_rawIn_normDist_T_26 = mux(_io_out_c_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_25) node _io_out_c_self_rec_rawIn_normDist_T_27 = mux(_io_out_c_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_26) node _io_out_c_self_rec_rawIn_normDist_T_28 = mux(_io_out_c_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_27) node _io_out_c_self_rec_rawIn_normDist_T_29 = mux(_io_out_c_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_28) node _io_out_c_self_rec_rawIn_normDist_T_30 = mux(_io_out_c_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_29) node _io_out_c_self_rec_rawIn_normDist_T_31 = mux(_io_out_c_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_30) node _io_out_c_self_rec_rawIn_normDist_T_32 = mux(_io_out_c_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_31) node _io_out_c_self_rec_rawIn_normDist_T_33 = mux(_io_out_c_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_32) node _io_out_c_self_rec_rawIn_normDist_T_34 = mux(_io_out_c_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_33) node _io_out_c_self_rec_rawIn_normDist_T_35 = mux(_io_out_c_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_34) node _io_out_c_self_rec_rawIn_normDist_T_36 = mux(_io_out_c_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_35) node _io_out_c_self_rec_rawIn_normDist_T_37 = mux(_io_out_c_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_36) node _io_out_c_self_rec_rawIn_normDist_T_38 = mux(_io_out_c_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_37) node _io_out_c_self_rec_rawIn_normDist_T_39 = mux(_io_out_c_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_38) node _io_out_c_self_rec_rawIn_normDist_T_40 = mux(_io_out_c_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_39) node _io_out_c_self_rec_rawIn_normDist_T_41 = mux(_io_out_c_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_40) node _io_out_c_self_rec_rawIn_normDist_T_42 = mux(_io_out_c_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_41) node _io_out_c_self_rec_rawIn_normDist_T_43 = mux(_io_out_c_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_42) node io_out_c_self_rec_rawIn_normDist = mux(_io_out_c_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_43) node _io_out_c_self_rec_rawIn_subnormFract_T = dshl(io_out_c_self_rec_rawIn_fractIn, io_out_c_self_rec_rawIn_normDist) node _io_out_c_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_self_rec_rawIn_subnormFract = shl(_io_out_c_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T = xor(io_out_c_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, _io_out_c_self_rec_rawIn_adjustedExp_T, io_out_c_self_rec_rawIn_expIn) node _io_out_c_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_1, _io_out_c_self_rec_rawIn_adjustedExp_T_3) node io_out_c_self_rec_rawIn_adjustedExp = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_self_rec_rawIn_isZero = and(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_isZeroFractIn) node _io_out_c_self_rec_rawIn_isSpecial_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 7) node io_out_c_self_rec_rawIn_isSpecial = eq(_io_out_c_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T = eq(io_out_c_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_1 = and(io_out_c_self_rec_rawIn_isSpecial, _io_out_c_self_rec_rawIn_out_isNaN_T) connect io_out_c_self_rec_rawIn.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_1 node _io_out_c_self_rec_rawIn_out_isInf_T = and(io_out_c_self_rec_rawIn_isSpecial, io_out_c_self_rec_rawIn_isZeroFractIn) connect io_out_c_self_rec_rawIn.isInf, _io_out_c_self_rec_rawIn_out_isInf_T connect io_out_c_self_rec_rawIn.isZero, io_out_c_self_rec_rawIn_isZero connect io_out_c_self_rec_rawIn.sign, io_out_c_self_rec_rawIn_sign node _io_out_c_self_rec_rawIn_out_sExp_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T) connect io_out_c_self_rec_rawIn.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_1 node _io_out_c_self_rec_rawIn_out_sig_T = eq(io_out_c_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T) node _io_out_c_self_rec_rawIn_out_sig_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_subnormFract, io_out_c_self_rec_rawIn_fractIn) node _io_out_c_self_rec_rawIn_out_sig_T_3 = cat(_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2) connect io_out_c_self_rec_rawIn.sig, _io_out_c_self_rec_rawIn_out_sig_T_3 node _io_out_c_self_rec_T = bits(io_out_c_self_rec_rawIn.sExp, 8, 6) node _io_out_c_self_rec_T_1 = mux(io_out_c_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_self_rec_T) node _io_out_c_self_rec_T_2 = mux(io_out_c_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_3 = or(_io_out_c_self_rec_T_1, _io_out_c_self_rec_T_2) node _io_out_c_self_rec_T_4 = cat(io_out_c_self_rec_rawIn.sign, _io_out_c_self_rec_T_3) node _io_out_c_self_rec_T_5 = bits(io_out_c_self_rec_rawIn.sExp, 5, 0) node _io_out_c_self_rec_T_6 = cat(_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5) node _io_out_c_self_rec_T_7 = bits(io_out_c_self_rec_rawIn.sig, 22, 0) node io_out_c_self_rec = cat(_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7) wire io_out_c_shift_exp : UInt<8> node _io_out_c_shift_exp_T = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_1 = tail(_io_out_c_shift_exp_T, 1) connect io_out_c_shift_exp, _io_out_c_shift_exp_T_1 node io_out_c_shift_fn_hi = cat(UInt<1>(0h0), io_out_c_shift_exp) node io_out_c_shift_fn = cat(io_out_c_shift_fn_hi, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign = bits(io_out_c_shift_fn, 31, 31) node io_out_c_shift_rec_rawIn_expIn = bits(io_out_c_shift_fn, 30, 23) node io_out_c_shift_rec_rawIn_fractIn = bits(io_out_c_shift_fn, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn = eq(io_out_c_shift_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn = eq(io_out_c_shift_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T = bits(io_out_c_shift_rec_rawIn_fractIn, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_1 = bits(io_out_c_shift_rec_rawIn_fractIn, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_2 = bits(io_out_c_shift_rec_rawIn_fractIn, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_3 = bits(io_out_c_shift_rec_rawIn_fractIn, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_4 = bits(io_out_c_shift_rec_rawIn_fractIn, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_5 = bits(io_out_c_shift_rec_rawIn_fractIn, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_6 = bits(io_out_c_shift_rec_rawIn_fractIn, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_7 = bits(io_out_c_shift_rec_rawIn_fractIn, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_8 = bits(io_out_c_shift_rec_rawIn_fractIn, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_9 = bits(io_out_c_shift_rec_rawIn_fractIn, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_10 = bits(io_out_c_shift_rec_rawIn_fractIn, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_11 = bits(io_out_c_shift_rec_rawIn_fractIn, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_12 = bits(io_out_c_shift_rec_rawIn_fractIn, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_13 = bits(io_out_c_shift_rec_rawIn_fractIn, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_14 = bits(io_out_c_shift_rec_rawIn_fractIn, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_15 = bits(io_out_c_shift_rec_rawIn_fractIn, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_16 = bits(io_out_c_shift_rec_rawIn_fractIn, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_17 = bits(io_out_c_shift_rec_rawIn_fractIn, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_18 = bits(io_out_c_shift_rec_rawIn_fractIn, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_19 = bits(io_out_c_shift_rec_rawIn_fractIn, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_20 = bits(io_out_c_shift_rec_rawIn_fractIn, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_21 = bits(io_out_c_shift_rec_rawIn_fractIn, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_22 = bits(io_out_c_shift_rec_rawIn_fractIn, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_23 = mux(_io_out_c_shift_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_24 = mux(_io_out_c_shift_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_23) node _io_out_c_shift_rec_rawIn_normDist_T_25 = mux(_io_out_c_shift_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_24) node _io_out_c_shift_rec_rawIn_normDist_T_26 = mux(_io_out_c_shift_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_25) node _io_out_c_shift_rec_rawIn_normDist_T_27 = mux(_io_out_c_shift_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_26) node _io_out_c_shift_rec_rawIn_normDist_T_28 = mux(_io_out_c_shift_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_27) node _io_out_c_shift_rec_rawIn_normDist_T_29 = mux(_io_out_c_shift_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_28) node _io_out_c_shift_rec_rawIn_normDist_T_30 = mux(_io_out_c_shift_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_29) node _io_out_c_shift_rec_rawIn_normDist_T_31 = mux(_io_out_c_shift_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_30) node _io_out_c_shift_rec_rawIn_normDist_T_32 = mux(_io_out_c_shift_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_31) node _io_out_c_shift_rec_rawIn_normDist_T_33 = mux(_io_out_c_shift_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_32) node _io_out_c_shift_rec_rawIn_normDist_T_34 = mux(_io_out_c_shift_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_33) node _io_out_c_shift_rec_rawIn_normDist_T_35 = mux(_io_out_c_shift_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_34) node _io_out_c_shift_rec_rawIn_normDist_T_36 = mux(_io_out_c_shift_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_35) node _io_out_c_shift_rec_rawIn_normDist_T_37 = mux(_io_out_c_shift_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_36) node _io_out_c_shift_rec_rawIn_normDist_T_38 = mux(_io_out_c_shift_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_37) node _io_out_c_shift_rec_rawIn_normDist_T_39 = mux(_io_out_c_shift_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_38) node _io_out_c_shift_rec_rawIn_normDist_T_40 = mux(_io_out_c_shift_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_39) node _io_out_c_shift_rec_rawIn_normDist_T_41 = mux(_io_out_c_shift_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_40) node _io_out_c_shift_rec_rawIn_normDist_T_42 = mux(_io_out_c_shift_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_41) node _io_out_c_shift_rec_rawIn_normDist_T_43 = mux(_io_out_c_shift_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_42) node io_out_c_shift_rec_rawIn_normDist = mux(_io_out_c_shift_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_43) node _io_out_c_shift_rec_rawIn_subnormFract_T = dshl(io_out_c_shift_rec_rawIn_fractIn, io_out_c_shift_rec_rawIn_normDist) node _io_out_c_shift_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T = xor(io_out_c_shift_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, _io_out_c_shift_rec_rawIn_adjustedExp_T, io_out_c_shift_rec_rawIn_expIn) node _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_2) node _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_3) node io_out_c_shift_rec_rawIn_adjustedExp = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_shift_rec_rawIn_isZero = and(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_isZeroFractIn) node _io_out_c_shift_rec_rawIn_isSpecial_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial = eq(_io_out_c_shift_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T = eq(io_out_c_shift_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial, _io_out_c_shift_rec_rawIn_out_isNaN_T) connect io_out_c_shift_rec_rawIn.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_1 node _io_out_c_shift_rec_rawIn_out_isInf_T = and(io_out_c_shift_rec_rawIn_isSpecial, io_out_c_shift_rec_rawIn_isZeroFractIn) connect io_out_c_shift_rec_rawIn.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T connect io_out_c_shift_rec_rawIn.isZero, io_out_c_shift_rec_rawIn_isZero connect io_out_c_shift_rec_rawIn.sign, io_out_c_shift_rec_rawIn_sign node _io_out_c_shift_rec_rawIn_out_sExp_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T) connect io_out_c_shift_rec_rawIn.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_1 node _io_out_c_shift_rec_rawIn_out_sig_T = eq(io_out_c_shift_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T) node _io_out_c_shift_rec_rawIn_out_sig_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_subnormFract, io_out_c_shift_rec_rawIn_fractIn) node _io_out_c_shift_rec_rawIn_out_sig_T_3 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2) connect io_out_c_shift_rec_rawIn.sig, _io_out_c_shift_rec_rawIn_out_sig_T_3 node _io_out_c_shift_rec_T = bits(io_out_c_shift_rec_rawIn.sExp, 8, 6) node _io_out_c_shift_rec_T_1 = mux(io_out_c_shift_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T) node _io_out_c_shift_rec_T_2 = mux(io_out_c_shift_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_3 = or(_io_out_c_shift_rec_T_1, _io_out_c_shift_rec_T_2) node _io_out_c_shift_rec_T_4 = cat(io_out_c_shift_rec_rawIn.sign, _io_out_c_shift_rec_T_3) node _io_out_c_shift_rec_T_5 = bits(io_out_c_shift_rec_rawIn.sExp, 5, 0) node _io_out_c_shift_rec_T_6 = cat(_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5) node _io_out_c_shift_rec_T_7 = bits(io_out_c_shift_rec_rawIn.sig, 22, 0) node io_out_c_shift_rec = cat(_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7) node _io_out_c_T = neq(io_out_c_shift_exp, UInt<1>(0h0)) node _io_out_c_T_1 = asUInt(reset) node _io_out_c_T_2 = eq(_io_out_c_T_1, UInt<1>(0h0)) when _io_out_c_T_2 : node _io_out_c_T_3 = eq(_io_out_c_T, UInt<1>(0h0)) when _io_out_c_T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf assert(clock, _io_out_c_T, UInt<1>(0h1), "") : io_out_c_assert inst io_out_c_muladder of MulRecFN_38 connect io_out_c_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder.io.a, io_out_c_self_rec connect io_out_c_muladder.io.b, io_out_c_shift_rec wire io_out_c_result : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp = bits(io_out_c_muladder.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T = bits(io_out_c_result_bits_rawIn_exp, 8, 6) node io_out_c_result_bits_rawIn_isZero = eq(_io_out_c_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T = bits(io_out_c_result_bits_rawIn_exp, 8, 7) node io_out_c_result_bits_rawIn_isSpecial = eq(_io_out_c_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_1 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isNaN_T) connect io_out_c_result_bits_rawIn.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_1 node _io_out_c_result_bits_rawIn_out_isInf_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_1 = eq(_io_out_c_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_2 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isInf_T_1) connect io_out_c_result_bits_rawIn.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_2 connect io_out_c_result_bits_rawIn.isZero, io_out_c_result_bits_rawIn_isZero node _io_out_c_result_bits_rawIn_out_sign_T = bits(io_out_c_muladder.io.out, 32, 32) connect io_out_c_result_bits_rawIn.sign, _io_out_c_result_bits_rawIn_out_sign_T node _io_out_c_result_bits_rawIn_out_sExp_T = cvt(io_out_c_result_bits_rawIn_exp) connect io_out_c_result_bits_rawIn.sExp, _io_out_c_result_bits_rawIn_out_sExp_T node _io_out_c_result_bits_rawIn_out_sig_T = eq(io_out_c_result_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T) node _io_out_c_result_bits_rawIn_out_sig_T_2 = bits(io_out_c_muladder.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_3 = cat(_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2) connect io_out_c_result_bits_rawIn.sig, _io_out_c_result_bits_rawIn_out_sig_T_3 node io_out_c_result_bits_isSubnormal = lt(io_out_c_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T = bits(io_out_c_result_bits_rawIn.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T) node io_out_c_result_bits_denormShiftDist = tail(_io_out_c_result_bits_denormShiftDist_T_1, 1) node _io_out_c_result_bits_denormFract_T = shr(io_out_c_result_bits_rawIn.sig, 1) node _io_out_c_result_bits_denormFract_T_1 = dshr(_io_out_c_result_bits_denormFract_T, io_out_c_result_bits_denormShiftDist) node io_out_c_result_bits_denormFract = bits(_io_out_c_result_bits_denormFract_T_1, 22, 0) node _io_out_c_result_bits_expOut_T = bits(io_out_c_result_bits_rawIn.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_1 = sub(_io_out_c_result_bits_expOut_T, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_2 = tail(_io_out_c_result_bits_expOut_T_1, 1) node _io_out_c_result_bits_expOut_T_3 = mux(io_out_c_result_bits_isSubnormal, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_2) node _io_out_c_result_bits_expOut_T_4 = or(io_out_c_result_bits_rawIn.isNaN, io_out_c_result_bits_rawIn.isInf) node _io_out_c_result_bits_expOut_T_5 = mux(_io_out_c_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut = or(_io_out_c_result_bits_expOut_T_3, _io_out_c_result_bits_expOut_T_5) node _io_out_c_result_bits_fractOut_T = bits(io_out_c_result_bits_rawIn.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_1 = mux(io_out_c_result_bits_rawIn.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T) node io_out_c_result_bits_fractOut = mux(io_out_c_result_bits_isSubnormal, io_out_c_result_bits_denormFract, _io_out_c_result_bits_fractOut_T_1) node io_out_c_result_bits_hi = cat(io_out_c_result_bits_rawIn.sign, io_out_c_result_bits_expOut) node _io_out_c_result_bits_T = cat(io_out_c_result_bits_hi, io_out_c_result_bits_fractOut) connect io_out_c_result.bits, _io_out_c_result_bits_T node io_out_c_self_rec_rawIn_sign_1 = bits(io_out_c_result.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_1 = bits(io_out_c_result.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_1 = bits(io_out_c_result.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_self_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_self_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_44 = bits(io_out_c_self_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_45 = bits(io_out_c_self_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_46 = bits(io_out_c_self_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_47 = bits(io_out_c_self_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_48 = bits(io_out_c_self_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_49 = bits(io_out_c_self_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_50 = bits(io_out_c_self_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_51 = bits(io_out_c_self_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_52 = bits(io_out_c_self_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_53 = bits(io_out_c_self_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_54 = bits(io_out_c_self_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_55 = bits(io_out_c_self_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_56 = bits(io_out_c_self_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_57 = bits(io_out_c_self_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_58 = bits(io_out_c_self_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_59 = bits(io_out_c_self_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_60 = bits(io_out_c_self_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_61 = bits(io_out_c_self_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_62 = bits(io_out_c_self_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_63 = bits(io_out_c_self_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_64 = bits(io_out_c_self_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_65 = bits(io_out_c_self_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_66 = bits(io_out_c_self_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_67 = mux(_io_out_c_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_68 = mux(_io_out_c_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_67) node _io_out_c_self_rec_rawIn_normDist_T_69 = mux(_io_out_c_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_68) node _io_out_c_self_rec_rawIn_normDist_T_70 = mux(_io_out_c_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_69) node _io_out_c_self_rec_rawIn_normDist_T_71 = mux(_io_out_c_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_70) node _io_out_c_self_rec_rawIn_normDist_T_72 = mux(_io_out_c_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_71) node _io_out_c_self_rec_rawIn_normDist_T_73 = mux(_io_out_c_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_72) node _io_out_c_self_rec_rawIn_normDist_T_74 = mux(_io_out_c_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_73) node _io_out_c_self_rec_rawIn_normDist_T_75 = mux(_io_out_c_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_74) node _io_out_c_self_rec_rawIn_normDist_T_76 = mux(_io_out_c_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_75) node _io_out_c_self_rec_rawIn_normDist_T_77 = mux(_io_out_c_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_76) node _io_out_c_self_rec_rawIn_normDist_T_78 = mux(_io_out_c_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_77) node _io_out_c_self_rec_rawIn_normDist_T_79 = mux(_io_out_c_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_78) node _io_out_c_self_rec_rawIn_normDist_T_80 = mux(_io_out_c_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_79) node _io_out_c_self_rec_rawIn_normDist_T_81 = mux(_io_out_c_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_80) node _io_out_c_self_rec_rawIn_normDist_T_82 = mux(_io_out_c_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_81) node _io_out_c_self_rec_rawIn_normDist_T_83 = mux(_io_out_c_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_82) node _io_out_c_self_rec_rawIn_normDist_T_84 = mux(_io_out_c_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_83) node _io_out_c_self_rec_rawIn_normDist_T_85 = mux(_io_out_c_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_84) node _io_out_c_self_rec_rawIn_normDist_T_86 = mux(_io_out_c_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_85) node _io_out_c_self_rec_rawIn_normDist_T_87 = mux(_io_out_c_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_86) node io_out_c_self_rec_rawIn_normDist_1 = mux(_io_out_c_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_87) node _io_out_c_self_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_self_rec_rawIn_fractIn_1, io_out_c_self_rec_rawIn_normDist_1) node _io_out_c_self_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_1 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_self_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, _io_out_c_self_rec_rawIn_adjustedExp_T_5, io_out_c_self_rec_rawIn_expIn_1) node _io_out_c_self_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_7) node _io_out_c_self_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_6, _io_out_c_self_rec_rawIn_adjustedExp_T_8) node io_out_c_self_rec_rawIn_adjustedExp_1 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_self_rec_rawIn_isZero_1 = and(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) node _io_out_c_self_rec_rawIn_isSpecial_T_1 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_1 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_1, _io_out_c_self_rec_rawIn_out_isNaN_T_2) connect io_out_c_self_rec_rawIn_1.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_3 node _io_out_c_self_rec_rawIn_out_isInf_T_1 = and(io_out_c_self_rec_rawIn_isSpecial_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) connect io_out_c_self_rec_rawIn_1.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_1 connect io_out_c_self_rec_rawIn_1.isZero, io_out_c_self_rec_rawIn_isZero_1 connect io_out_c_self_rec_rawIn_1.sign, io_out_c_self_rec_rawIn_sign_1 node _io_out_c_self_rec_rawIn_out_sExp_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_2) connect io_out_c_self_rec_rawIn_1.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_3 node _io_out_c_self_rec_rawIn_out_sig_T_4 = eq(io_out_c_self_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_4) node _io_out_c_self_rec_rawIn_out_sig_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_subnormFract_1, io_out_c_self_rec_rawIn_fractIn_1) node _io_out_c_self_rec_rawIn_out_sig_T_7 = cat(_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6) connect io_out_c_self_rec_rawIn_1.sig, _io_out_c_self_rec_rawIn_out_sig_T_7 node _io_out_c_self_rec_T_8 = bits(io_out_c_self_rec_rawIn_1.sExp, 8, 6) node _io_out_c_self_rec_T_9 = mux(io_out_c_self_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_8) node _io_out_c_self_rec_T_10 = mux(io_out_c_self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_11 = or(_io_out_c_self_rec_T_9, _io_out_c_self_rec_T_10) node _io_out_c_self_rec_T_12 = cat(io_out_c_self_rec_rawIn_1.sign, _io_out_c_self_rec_T_11) node _io_out_c_self_rec_T_13 = bits(io_out_c_self_rec_rawIn_1.sExp, 5, 0) node _io_out_c_self_rec_T_14 = cat(_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13) node _io_out_c_self_rec_T_15 = bits(io_out_c_self_rec_rawIn_1.sig, 22, 0) node io_out_c_self_rec_1 = cat(_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15) inst io_out_c_resizer of RecFNToRecFN_188 connect io_out_c_resizer.io.in, io_out_c_self_rec_1 connect io_out_c_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_1 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_1 = bits(io_out_c_resizer.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 6) node io_out_c_result_bits_rawIn_isZero_1 = eq(_io_out_c_result_bits_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_1 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_2 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_3 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isNaN_T_2) connect io_out_c_result_bits_rawIn_1.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_3 node _io_out_c_result_bits_rawIn_out_isInf_T_3 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_4 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isInf_T_4) connect io_out_c_result_bits_rawIn_1.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_5 connect io_out_c_result_bits_rawIn_1.isZero, io_out_c_result_bits_rawIn_isZero_1 node _io_out_c_result_bits_rawIn_out_sign_T_1 = bits(io_out_c_resizer.io.out, 32, 32) connect io_out_c_result_bits_rawIn_1.sign, _io_out_c_result_bits_rawIn_out_sign_T_1 node _io_out_c_result_bits_rawIn_out_sExp_T_1 = cvt(io_out_c_result_bits_rawIn_exp_1) connect io_out_c_result_bits_rawIn_1.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_1 node _io_out_c_result_bits_rawIn_out_sig_T_4 = eq(io_out_c_result_bits_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_4) node _io_out_c_result_bits_rawIn_out_sig_T_6 = bits(io_out_c_resizer.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_7 = cat(_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6) connect io_out_c_result_bits_rawIn_1.sig, _io_out_c_result_bits_rawIn_out_sig_T_7 node io_out_c_result_bits_isSubnormal_1 = lt(io_out_c_result_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_2 = bits(io_out_c_result_bits_rawIn_1.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_2) node io_out_c_result_bits_denormShiftDist_1 = tail(_io_out_c_result_bits_denormShiftDist_T_3, 1) node _io_out_c_result_bits_denormFract_T_2 = shr(io_out_c_result_bits_rawIn_1.sig, 1) node _io_out_c_result_bits_denormFract_T_3 = dshr(_io_out_c_result_bits_denormFract_T_2, io_out_c_result_bits_denormShiftDist_1) node io_out_c_result_bits_denormFract_1 = bits(_io_out_c_result_bits_denormFract_T_3, 22, 0) node _io_out_c_result_bits_expOut_T_6 = bits(io_out_c_result_bits_rawIn_1.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_7 = sub(_io_out_c_result_bits_expOut_T_6, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_8 = tail(_io_out_c_result_bits_expOut_T_7, 1) node _io_out_c_result_bits_expOut_T_9 = mux(io_out_c_result_bits_isSubnormal_1, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_8) node _io_out_c_result_bits_expOut_T_10 = or(io_out_c_result_bits_rawIn_1.isNaN, io_out_c_result_bits_rawIn_1.isInf) node _io_out_c_result_bits_expOut_T_11 = mux(_io_out_c_result_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_1 = or(_io_out_c_result_bits_expOut_T_9, _io_out_c_result_bits_expOut_T_11) node _io_out_c_result_bits_fractOut_T_2 = bits(io_out_c_result_bits_rawIn_1.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_3 = mux(io_out_c_result_bits_rawIn_1.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_2) node io_out_c_result_bits_fractOut_1 = mux(io_out_c_result_bits_isSubnormal_1, io_out_c_result_bits_denormFract_1, _io_out_c_result_bits_fractOut_T_3) node io_out_c_result_bits_hi_1 = cat(io_out_c_result_bits_rawIn_1.sign, io_out_c_result_bits_expOut_1) node _io_out_c_result_bits_T_1 = cat(io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1) connect io_out_c_result_1.bits, _io_out_c_result_bits_T_1 connect io.out_c, io_out_c_result_1 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_1 : UInt<32> connect _mac_unit_io_in_b_WIRE_1, io.in_b.bits node _mac_unit_io_in_b_T = bits(_mac_unit_io_in_b_WIRE_1, 31, 0) connect _mac_unit_io_in_b_WIRE.bits, _mac_unit_io_in_b_T connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE.bits connect mac_unit.io.in_c.bits, c2.bits connect c2, mac_unit.io.out_d node c1_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c1_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c1_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c1_self_rec_rawIn_isZeroExpIn = eq(c1_self_rec_rawIn_expIn, UInt<1>(0h0)) node c1_self_rec_rawIn_isZeroFractIn = eq(c1_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_normDist_T = bits(c1_self_rec_rawIn_fractIn, 0, 0) node _c1_self_rec_rawIn_normDist_T_1 = bits(c1_self_rec_rawIn_fractIn, 1, 1) node _c1_self_rec_rawIn_normDist_T_2 = bits(c1_self_rec_rawIn_fractIn, 2, 2) node _c1_self_rec_rawIn_normDist_T_3 = bits(c1_self_rec_rawIn_fractIn, 3, 3) node _c1_self_rec_rawIn_normDist_T_4 = bits(c1_self_rec_rawIn_fractIn, 4, 4) node _c1_self_rec_rawIn_normDist_T_5 = bits(c1_self_rec_rawIn_fractIn, 5, 5) node _c1_self_rec_rawIn_normDist_T_6 = bits(c1_self_rec_rawIn_fractIn, 6, 6) node _c1_self_rec_rawIn_normDist_T_7 = bits(c1_self_rec_rawIn_fractIn, 7, 7) node _c1_self_rec_rawIn_normDist_T_8 = bits(c1_self_rec_rawIn_fractIn, 8, 8) node _c1_self_rec_rawIn_normDist_T_9 = bits(c1_self_rec_rawIn_fractIn, 9, 9) node _c1_self_rec_rawIn_normDist_T_10 = bits(c1_self_rec_rawIn_fractIn, 10, 10) node _c1_self_rec_rawIn_normDist_T_11 = bits(c1_self_rec_rawIn_fractIn, 11, 11) node _c1_self_rec_rawIn_normDist_T_12 = bits(c1_self_rec_rawIn_fractIn, 12, 12) node _c1_self_rec_rawIn_normDist_T_13 = bits(c1_self_rec_rawIn_fractIn, 13, 13) node _c1_self_rec_rawIn_normDist_T_14 = bits(c1_self_rec_rawIn_fractIn, 14, 14) node _c1_self_rec_rawIn_normDist_T_15 = bits(c1_self_rec_rawIn_fractIn, 15, 15) node _c1_self_rec_rawIn_normDist_T_16 = bits(c1_self_rec_rawIn_fractIn, 16, 16) node _c1_self_rec_rawIn_normDist_T_17 = bits(c1_self_rec_rawIn_fractIn, 17, 17) node _c1_self_rec_rawIn_normDist_T_18 = bits(c1_self_rec_rawIn_fractIn, 18, 18) node _c1_self_rec_rawIn_normDist_T_19 = bits(c1_self_rec_rawIn_fractIn, 19, 19) node _c1_self_rec_rawIn_normDist_T_20 = bits(c1_self_rec_rawIn_fractIn, 20, 20) node _c1_self_rec_rawIn_normDist_T_21 = bits(c1_self_rec_rawIn_fractIn, 21, 21) node _c1_self_rec_rawIn_normDist_T_22 = bits(c1_self_rec_rawIn_fractIn, 22, 22) node _c1_self_rec_rawIn_normDist_T_23 = mux(_c1_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c1_self_rec_rawIn_normDist_T_24 = mux(_c1_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c1_self_rec_rawIn_normDist_T_23) node _c1_self_rec_rawIn_normDist_T_25 = mux(_c1_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c1_self_rec_rawIn_normDist_T_24) node _c1_self_rec_rawIn_normDist_T_26 = mux(_c1_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c1_self_rec_rawIn_normDist_T_25) node _c1_self_rec_rawIn_normDist_T_27 = mux(_c1_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c1_self_rec_rawIn_normDist_T_26) node _c1_self_rec_rawIn_normDist_T_28 = mux(_c1_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c1_self_rec_rawIn_normDist_T_27) node _c1_self_rec_rawIn_normDist_T_29 = mux(_c1_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c1_self_rec_rawIn_normDist_T_28) node _c1_self_rec_rawIn_normDist_T_30 = mux(_c1_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c1_self_rec_rawIn_normDist_T_29) node _c1_self_rec_rawIn_normDist_T_31 = mux(_c1_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c1_self_rec_rawIn_normDist_T_30) node _c1_self_rec_rawIn_normDist_T_32 = mux(_c1_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c1_self_rec_rawIn_normDist_T_31) node _c1_self_rec_rawIn_normDist_T_33 = mux(_c1_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c1_self_rec_rawIn_normDist_T_32) node _c1_self_rec_rawIn_normDist_T_34 = mux(_c1_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c1_self_rec_rawIn_normDist_T_33) node _c1_self_rec_rawIn_normDist_T_35 = mux(_c1_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c1_self_rec_rawIn_normDist_T_34) node _c1_self_rec_rawIn_normDist_T_36 = mux(_c1_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c1_self_rec_rawIn_normDist_T_35) node _c1_self_rec_rawIn_normDist_T_37 = mux(_c1_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c1_self_rec_rawIn_normDist_T_36) node _c1_self_rec_rawIn_normDist_T_38 = mux(_c1_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c1_self_rec_rawIn_normDist_T_37) node _c1_self_rec_rawIn_normDist_T_39 = mux(_c1_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c1_self_rec_rawIn_normDist_T_38) node _c1_self_rec_rawIn_normDist_T_40 = mux(_c1_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c1_self_rec_rawIn_normDist_T_39) node _c1_self_rec_rawIn_normDist_T_41 = mux(_c1_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c1_self_rec_rawIn_normDist_T_40) node _c1_self_rec_rawIn_normDist_T_42 = mux(_c1_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c1_self_rec_rawIn_normDist_T_41) node _c1_self_rec_rawIn_normDist_T_43 = mux(_c1_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c1_self_rec_rawIn_normDist_T_42) node c1_self_rec_rawIn_normDist = mux(_c1_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c1_self_rec_rawIn_normDist_T_43) node _c1_self_rec_rawIn_subnormFract_T = dshl(c1_self_rec_rawIn_fractIn, c1_self_rec_rawIn_normDist) node _c1_self_rec_rawIn_subnormFract_T_1 = bits(_c1_self_rec_rawIn_subnormFract_T, 21, 0) node c1_self_rec_rawIn_subnormFract = shl(_c1_self_rec_rawIn_subnormFract_T_1, 1) node _c1_self_rec_rawIn_adjustedExp_T = xor(c1_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c1_self_rec_rawIn_adjustedExp_T_1 = mux(c1_self_rec_rawIn_isZeroExpIn, _c1_self_rec_rawIn_adjustedExp_T, c1_self_rec_rawIn_expIn) node _c1_self_rec_rawIn_adjustedExp_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c1_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c1_self_rec_rawIn_adjustedExp_T_2) node _c1_self_rec_rawIn_adjustedExp_T_4 = add(_c1_self_rec_rawIn_adjustedExp_T_1, _c1_self_rec_rawIn_adjustedExp_T_3) node c1_self_rec_rawIn_adjustedExp = tail(_c1_self_rec_rawIn_adjustedExp_T_4, 1) node c1_self_rec_rawIn_isZero = and(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_isZeroFractIn) node _c1_self_rec_rawIn_isSpecial_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 7) node c1_self_rec_rawIn_isSpecial = eq(_c1_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_self_rec_rawIn_out_isNaN_T = eq(c1_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_isNaN_T_1 = and(c1_self_rec_rawIn_isSpecial, _c1_self_rec_rawIn_out_isNaN_T) connect c1_self_rec_rawIn.isNaN, _c1_self_rec_rawIn_out_isNaN_T_1 node _c1_self_rec_rawIn_out_isInf_T = and(c1_self_rec_rawIn_isSpecial, c1_self_rec_rawIn_isZeroFractIn) connect c1_self_rec_rawIn.isInf, _c1_self_rec_rawIn_out_isInf_T connect c1_self_rec_rawIn.isZero, c1_self_rec_rawIn_isZero connect c1_self_rec_rawIn.sign, c1_self_rec_rawIn_sign node _c1_self_rec_rawIn_out_sExp_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 0) node _c1_self_rec_rawIn_out_sExp_T_1 = cvt(_c1_self_rec_rawIn_out_sExp_T) connect c1_self_rec_rawIn.sExp, _c1_self_rec_rawIn_out_sExp_T_1 node _c1_self_rec_rawIn_out_sig_T = eq(c1_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_self_rec_rawIn_out_sig_T) node _c1_self_rec_rawIn_out_sig_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_subnormFract, c1_self_rec_rawIn_fractIn) node _c1_self_rec_rawIn_out_sig_T_3 = cat(_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2) connect c1_self_rec_rawIn.sig, _c1_self_rec_rawIn_out_sig_T_3 node _c1_self_rec_T = bits(c1_self_rec_rawIn.sExp, 8, 6) node _c1_self_rec_T_1 = mux(c1_self_rec_rawIn.isZero, UInt<3>(0h0), _c1_self_rec_T) node _c1_self_rec_T_2 = mux(c1_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c1_self_rec_T_3 = or(_c1_self_rec_T_1, _c1_self_rec_T_2) node _c1_self_rec_T_4 = cat(c1_self_rec_rawIn.sign, _c1_self_rec_T_3) node _c1_self_rec_T_5 = bits(c1_self_rec_rawIn.sExp, 5, 0) node _c1_self_rec_T_6 = cat(_c1_self_rec_T_4, _c1_self_rec_T_5) node _c1_self_rec_T_7 = bits(c1_self_rec_rawIn.sig, 22, 0) node c1_self_rec = cat(_c1_self_rec_T_6, _c1_self_rec_T_7) inst c1_resizer of RecFNToRecFN_189 connect c1_resizer.io.in, c1_self_rec connect c1_resizer.io.roundingMode, UInt<3>(0h0) connect c1_resizer.io.detectTininess, UInt<1>(0h1) wire c1_result : { bits : UInt<32>} node c1_result_bits_rawIn_exp = bits(c1_resizer.io.out, 31, 23) node _c1_result_bits_rawIn_isZero_T = bits(c1_result_bits_rawIn_exp, 8, 6) node c1_result_bits_rawIn_isZero = eq(_c1_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_isSpecial_T = bits(c1_result_bits_rawIn_exp, 8, 7) node c1_result_bits_rawIn_isSpecial = eq(_c1_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_result_bits_rawIn_out_isNaN_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isNaN_T_1 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isNaN_T) connect c1_result_bits_rawIn.isNaN, _c1_result_bits_rawIn_out_isNaN_T_1 node _c1_result_bits_rawIn_out_isInf_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isInf_T_1 = eq(_c1_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_isInf_T_2 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isInf_T_1) connect c1_result_bits_rawIn.isInf, _c1_result_bits_rawIn_out_isInf_T_2 connect c1_result_bits_rawIn.isZero, c1_result_bits_rawIn_isZero node _c1_result_bits_rawIn_out_sign_T = bits(c1_resizer.io.out, 32, 32) connect c1_result_bits_rawIn.sign, _c1_result_bits_rawIn_out_sign_T node _c1_result_bits_rawIn_out_sExp_T = cvt(c1_result_bits_rawIn_exp) connect c1_result_bits_rawIn.sExp, _c1_result_bits_rawIn_out_sExp_T node _c1_result_bits_rawIn_out_sig_T = eq(c1_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_result_bits_rawIn_out_sig_T) node _c1_result_bits_rawIn_out_sig_T_2 = bits(c1_resizer.io.out, 22, 0) node _c1_result_bits_rawIn_out_sig_T_3 = cat(_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2) connect c1_result_bits_rawIn.sig, _c1_result_bits_rawIn_out_sig_T_3 node c1_result_bits_isSubnormal = lt(c1_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c1_result_bits_denormShiftDist_T = bits(c1_result_bits_rawIn.sExp, 4, 0) node _c1_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c1_result_bits_denormShiftDist_T) node c1_result_bits_denormShiftDist = tail(_c1_result_bits_denormShiftDist_T_1, 1) node _c1_result_bits_denormFract_T = shr(c1_result_bits_rawIn.sig, 1) node _c1_result_bits_denormFract_T_1 = dshr(_c1_result_bits_denormFract_T, c1_result_bits_denormShiftDist) node c1_result_bits_denormFract = bits(_c1_result_bits_denormFract_T_1, 22, 0) node _c1_result_bits_expOut_T = bits(c1_result_bits_rawIn.sExp, 7, 0) node _c1_result_bits_expOut_T_1 = sub(_c1_result_bits_expOut_T, UInt<8>(0h81)) node _c1_result_bits_expOut_T_2 = tail(_c1_result_bits_expOut_T_1, 1) node _c1_result_bits_expOut_T_3 = mux(c1_result_bits_isSubnormal, UInt<1>(0h0), _c1_result_bits_expOut_T_2) node _c1_result_bits_expOut_T_4 = or(c1_result_bits_rawIn.isNaN, c1_result_bits_rawIn.isInf) node _c1_result_bits_expOut_T_5 = mux(_c1_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c1_result_bits_expOut = or(_c1_result_bits_expOut_T_3, _c1_result_bits_expOut_T_5) node _c1_result_bits_fractOut_T = bits(c1_result_bits_rawIn.sig, 22, 0) node _c1_result_bits_fractOut_T_1 = mux(c1_result_bits_rawIn.isInf, UInt<1>(0h0), _c1_result_bits_fractOut_T) node c1_result_bits_fractOut = mux(c1_result_bits_isSubnormal, c1_result_bits_denormFract, _c1_result_bits_fractOut_T_1) node c1_result_bits_hi = cat(c1_result_bits_rawIn.sign, c1_result_bits_expOut) node _c1_result_bits_T = cat(c1_result_bits_hi, c1_result_bits_fractOut) connect c1_result.bits, _c1_result_bits_T connect c1, c1_result else : node io_out_c_self_rec_rawIn_sign_2 = bits(c2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_2 = bits(c2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_2 = bits(c2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_2 = eq(io_out_c_self_rec_rawIn_expIn_2, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_2 = eq(io_out_c_self_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_88 = bits(io_out_c_self_rec_rawIn_fractIn_2, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_89 = bits(io_out_c_self_rec_rawIn_fractIn_2, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_90 = bits(io_out_c_self_rec_rawIn_fractIn_2, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_91 = bits(io_out_c_self_rec_rawIn_fractIn_2, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_92 = bits(io_out_c_self_rec_rawIn_fractIn_2, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_93 = bits(io_out_c_self_rec_rawIn_fractIn_2, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_94 = bits(io_out_c_self_rec_rawIn_fractIn_2, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_95 = bits(io_out_c_self_rec_rawIn_fractIn_2, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_96 = bits(io_out_c_self_rec_rawIn_fractIn_2, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_97 = bits(io_out_c_self_rec_rawIn_fractIn_2, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_98 = bits(io_out_c_self_rec_rawIn_fractIn_2, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_99 = bits(io_out_c_self_rec_rawIn_fractIn_2, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_100 = bits(io_out_c_self_rec_rawIn_fractIn_2, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_101 = bits(io_out_c_self_rec_rawIn_fractIn_2, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_102 = bits(io_out_c_self_rec_rawIn_fractIn_2, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_103 = bits(io_out_c_self_rec_rawIn_fractIn_2, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_104 = bits(io_out_c_self_rec_rawIn_fractIn_2, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_105 = bits(io_out_c_self_rec_rawIn_fractIn_2, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_106 = bits(io_out_c_self_rec_rawIn_fractIn_2, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_107 = bits(io_out_c_self_rec_rawIn_fractIn_2, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_108 = bits(io_out_c_self_rec_rawIn_fractIn_2, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_109 = bits(io_out_c_self_rec_rawIn_fractIn_2, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_110 = bits(io_out_c_self_rec_rawIn_fractIn_2, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_111 = mux(_io_out_c_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_112 = mux(_io_out_c_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_111) node _io_out_c_self_rec_rawIn_normDist_T_113 = mux(_io_out_c_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_112) node _io_out_c_self_rec_rawIn_normDist_T_114 = mux(_io_out_c_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_113) node _io_out_c_self_rec_rawIn_normDist_T_115 = mux(_io_out_c_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_114) node _io_out_c_self_rec_rawIn_normDist_T_116 = mux(_io_out_c_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_115) node _io_out_c_self_rec_rawIn_normDist_T_117 = mux(_io_out_c_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_116) node _io_out_c_self_rec_rawIn_normDist_T_118 = mux(_io_out_c_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_117) node _io_out_c_self_rec_rawIn_normDist_T_119 = mux(_io_out_c_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_118) node _io_out_c_self_rec_rawIn_normDist_T_120 = mux(_io_out_c_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_119) node _io_out_c_self_rec_rawIn_normDist_T_121 = mux(_io_out_c_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_120) node _io_out_c_self_rec_rawIn_normDist_T_122 = mux(_io_out_c_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_121) node _io_out_c_self_rec_rawIn_normDist_T_123 = mux(_io_out_c_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_122) node _io_out_c_self_rec_rawIn_normDist_T_124 = mux(_io_out_c_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_123) node _io_out_c_self_rec_rawIn_normDist_T_125 = mux(_io_out_c_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_124) node _io_out_c_self_rec_rawIn_normDist_T_126 = mux(_io_out_c_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_125) node _io_out_c_self_rec_rawIn_normDist_T_127 = mux(_io_out_c_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_126) node _io_out_c_self_rec_rawIn_normDist_T_128 = mux(_io_out_c_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_127) node _io_out_c_self_rec_rawIn_normDist_T_129 = mux(_io_out_c_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_128) node _io_out_c_self_rec_rawIn_normDist_T_130 = mux(_io_out_c_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_129) node _io_out_c_self_rec_rawIn_normDist_T_131 = mux(_io_out_c_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_130) node io_out_c_self_rec_rawIn_normDist_2 = mux(_io_out_c_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_131) node _io_out_c_self_rec_rawIn_subnormFract_T_4 = dshl(io_out_c_self_rec_rawIn_fractIn_2, io_out_c_self_rec_rawIn_normDist_2) node _io_out_c_self_rec_rawIn_subnormFract_T_5 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_4, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_2 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_5, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_10 = xor(io_out_c_self_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_11 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, _io_out_c_self_rec_rawIn_adjustedExp_T_10, io_out_c_self_rec_rawIn_expIn_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_12 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_12) node _io_out_c_self_rec_rawIn_adjustedExp_T_14 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_11, _io_out_c_self_rec_rawIn_adjustedExp_T_13) node io_out_c_self_rec_rawIn_adjustedExp_2 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_14, 1) node io_out_c_self_rec_rawIn_isZero_2 = and(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) node _io_out_c_self_rec_rawIn_isSpecial_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_2 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_4 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_5 = and(io_out_c_self_rec_rawIn_isSpecial_2, _io_out_c_self_rec_rawIn_out_isNaN_T_4) connect io_out_c_self_rec_rawIn_2.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_5 node _io_out_c_self_rec_rawIn_out_isInf_T_2 = and(io_out_c_self_rec_rawIn_isSpecial_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) connect io_out_c_self_rec_rawIn_2.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_2 connect io_out_c_self_rec_rawIn_2.isZero, io_out_c_self_rec_rawIn_isZero_2 connect io_out_c_self_rec_rawIn_2.sign, io_out_c_self_rec_rawIn_sign_2 node _io_out_c_self_rec_rawIn_out_sExp_T_4 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_5 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_4) connect io_out_c_self_rec_rawIn_2.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_5 node _io_out_c_self_rec_rawIn_out_sig_T_8 = eq(io_out_c_self_rec_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_8) node _io_out_c_self_rec_rawIn_out_sig_T_10 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_subnormFract_2, io_out_c_self_rec_rawIn_fractIn_2) node _io_out_c_self_rec_rawIn_out_sig_T_11 = cat(_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10) connect io_out_c_self_rec_rawIn_2.sig, _io_out_c_self_rec_rawIn_out_sig_T_11 node _io_out_c_self_rec_T_16 = bits(io_out_c_self_rec_rawIn_2.sExp, 8, 6) node _io_out_c_self_rec_T_17 = mux(io_out_c_self_rec_rawIn_2.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_16) node _io_out_c_self_rec_T_18 = mux(io_out_c_self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_19 = or(_io_out_c_self_rec_T_17, _io_out_c_self_rec_T_18) node _io_out_c_self_rec_T_20 = cat(io_out_c_self_rec_rawIn_2.sign, _io_out_c_self_rec_T_19) node _io_out_c_self_rec_T_21 = bits(io_out_c_self_rec_rawIn_2.sExp, 5, 0) node _io_out_c_self_rec_T_22 = cat(_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21) node _io_out_c_self_rec_T_23 = bits(io_out_c_self_rec_rawIn_2.sig, 22, 0) node io_out_c_self_rec_2 = cat(_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23) wire io_out_c_shift_exp_1 : UInt<8> node _io_out_c_shift_exp_T_2 = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_3 = tail(_io_out_c_shift_exp_T_2, 1) connect io_out_c_shift_exp_1, _io_out_c_shift_exp_T_3 node io_out_c_shift_fn_hi_1 = cat(UInt<1>(0h0), io_out_c_shift_exp_1) node io_out_c_shift_fn_1 = cat(io_out_c_shift_fn_hi_1, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign_1 = bits(io_out_c_shift_fn_1, 31, 31) node io_out_c_shift_rec_rawIn_expIn_1 = bits(io_out_c_shift_fn_1, 30, 23) node io_out_c_shift_rec_rawIn_fractIn_1 = bits(io_out_c_shift_fn_1, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_shift_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_shift_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T_44 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_45 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_46 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_47 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_48 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_49 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_50 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_51 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_52 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_53 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_54 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_55 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_56 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_57 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_58 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_59 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_60 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_61 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_62 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_63 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_64 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_65 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_66 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_67 = mux(_io_out_c_shift_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_68 = mux(_io_out_c_shift_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_67) node _io_out_c_shift_rec_rawIn_normDist_T_69 = mux(_io_out_c_shift_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_68) node _io_out_c_shift_rec_rawIn_normDist_T_70 = mux(_io_out_c_shift_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_69) node _io_out_c_shift_rec_rawIn_normDist_T_71 = mux(_io_out_c_shift_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_70) node _io_out_c_shift_rec_rawIn_normDist_T_72 = mux(_io_out_c_shift_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_71) node _io_out_c_shift_rec_rawIn_normDist_T_73 = mux(_io_out_c_shift_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_72) node _io_out_c_shift_rec_rawIn_normDist_T_74 = mux(_io_out_c_shift_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_73) node _io_out_c_shift_rec_rawIn_normDist_T_75 = mux(_io_out_c_shift_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_74) node _io_out_c_shift_rec_rawIn_normDist_T_76 = mux(_io_out_c_shift_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_75) node _io_out_c_shift_rec_rawIn_normDist_T_77 = mux(_io_out_c_shift_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_76) node _io_out_c_shift_rec_rawIn_normDist_T_78 = mux(_io_out_c_shift_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_77) node _io_out_c_shift_rec_rawIn_normDist_T_79 = mux(_io_out_c_shift_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_78) node _io_out_c_shift_rec_rawIn_normDist_T_80 = mux(_io_out_c_shift_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_79) node _io_out_c_shift_rec_rawIn_normDist_T_81 = mux(_io_out_c_shift_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_80) node _io_out_c_shift_rec_rawIn_normDist_T_82 = mux(_io_out_c_shift_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_81) node _io_out_c_shift_rec_rawIn_normDist_T_83 = mux(_io_out_c_shift_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_82) node _io_out_c_shift_rec_rawIn_normDist_T_84 = mux(_io_out_c_shift_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_83) node _io_out_c_shift_rec_rawIn_normDist_T_85 = mux(_io_out_c_shift_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_84) node _io_out_c_shift_rec_rawIn_normDist_T_86 = mux(_io_out_c_shift_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_85) node _io_out_c_shift_rec_rawIn_normDist_T_87 = mux(_io_out_c_shift_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_86) node io_out_c_shift_rec_rawIn_normDist_1 = mux(_io_out_c_shift_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_87) node _io_out_c_shift_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_shift_rec_rawIn_fractIn_1, io_out_c_shift_rec_rawIn_normDist_1) node _io_out_c_shift_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract_1 = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_shift_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_5, io_out_c_shift_rec_rawIn_expIn_1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_7) node _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_6, _io_out_c_shift_rec_rawIn_adjustedExp_T_8) node io_out_c_shift_rec_rawIn_adjustedExp_1 = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_shift_rec_rawIn_isZero_1 = and(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) node _io_out_c_shift_rec_rawIn_isSpecial_T_1 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial_1 = eq(_io_out_c_shift_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_shift_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = and(io_out_c_shift_rec_rawIn_isSpecial_1, _io_out_c_shift_rec_rawIn_out_isNaN_T_2) connect io_out_c_shift_rec_rawIn_1.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_3 node _io_out_c_shift_rec_rawIn_out_isInf_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) connect io_out_c_shift_rec_rawIn_1.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T_1 connect io_out_c_shift_rec_rawIn_1.isZero, io_out_c_shift_rec_rawIn_isZero_1 connect io_out_c_shift_rec_rawIn_1.sign, io_out_c_shift_rec_rawIn_sign_1 node _io_out_c_shift_rec_rawIn_out_sExp_T_2 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T_2) connect io_out_c_shift_rec_rawIn_1.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_3 node _io_out_c_shift_rec_rawIn_out_sig_T_4 = eq(io_out_c_shift_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T_4) node _io_out_c_shift_rec_rawIn_out_sig_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_subnormFract_1, io_out_c_shift_rec_rawIn_fractIn_1) node _io_out_c_shift_rec_rawIn_out_sig_T_7 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6) connect io_out_c_shift_rec_rawIn_1.sig, _io_out_c_shift_rec_rawIn_out_sig_T_7 node _io_out_c_shift_rec_T_8 = bits(io_out_c_shift_rec_rawIn_1.sExp, 8, 6) node _io_out_c_shift_rec_T_9 = mux(io_out_c_shift_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T_8) node _io_out_c_shift_rec_T_10 = mux(io_out_c_shift_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_11 = or(_io_out_c_shift_rec_T_9, _io_out_c_shift_rec_T_10) node _io_out_c_shift_rec_T_12 = cat(io_out_c_shift_rec_rawIn_1.sign, _io_out_c_shift_rec_T_11) node _io_out_c_shift_rec_T_13 = bits(io_out_c_shift_rec_rawIn_1.sExp, 5, 0) node _io_out_c_shift_rec_T_14 = cat(_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13) node _io_out_c_shift_rec_T_15 = bits(io_out_c_shift_rec_rawIn_1.sig, 22, 0) node io_out_c_shift_rec_1 = cat(_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15) node _io_out_c_T_4 = neq(io_out_c_shift_exp_1, UInt<1>(0h0)) node _io_out_c_T_5 = asUInt(reset) node _io_out_c_T_6 = eq(_io_out_c_T_5, UInt<1>(0h0)) when _io_out_c_T_6 : node _io_out_c_T_7 = eq(_io_out_c_T_4, UInt<1>(0h0)) when _io_out_c_T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf_1 assert(clock, _io_out_c_T_4, UInt<1>(0h1), "") : io_out_c_assert_1 inst io_out_c_muladder_1 of MulRecFN_39 connect io_out_c_muladder_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder_1.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder_1.io.a, io_out_c_self_rec_2 connect io_out_c_muladder_1.io.b, io_out_c_shift_rec_1 wire io_out_c_result_2 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_2 = bits(io_out_c_muladder_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 6) node io_out_c_result_bits_rawIn_isZero_2 = eq(_io_out_c_result_bits_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_2 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_4 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isNaN_T_4) connect io_out_c_result_bits_rawIn_2.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_5 node _io_out_c_result_bits_rawIn_out_isInf_T_6 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_7 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_8 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isInf_T_7) connect io_out_c_result_bits_rawIn_2.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_8 connect io_out_c_result_bits_rawIn_2.isZero, io_out_c_result_bits_rawIn_isZero_2 node _io_out_c_result_bits_rawIn_out_sign_T_2 = bits(io_out_c_muladder_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_2.sign, _io_out_c_result_bits_rawIn_out_sign_T_2 node _io_out_c_result_bits_rawIn_out_sExp_T_2 = cvt(io_out_c_result_bits_rawIn_exp_2) connect io_out_c_result_bits_rawIn_2.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_2 node _io_out_c_result_bits_rawIn_out_sig_T_8 = eq(io_out_c_result_bits_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_8) node _io_out_c_result_bits_rawIn_out_sig_T_10 = bits(io_out_c_muladder_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_11 = cat(_io_out_c_result_bits_rawIn_out_sig_T_9, _io_out_c_result_bits_rawIn_out_sig_T_10) connect io_out_c_result_bits_rawIn_2.sig, _io_out_c_result_bits_rawIn_out_sig_T_11 node io_out_c_result_bits_isSubnormal_2 = lt(io_out_c_result_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_4 = bits(io_out_c_result_bits_rawIn_2.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_4) node io_out_c_result_bits_denormShiftDist_2 = tail(_io_out_c_result_bits_denormShiftDist_T_5, 1) node _io_out_c_result_bits_denormFract_T_4 = shr(io_out_c_result_bits_rawIn_2.sig, 1) node _io_out_c_result_bits_denormFract_T_5 = dshr(_io_out_c_result_bits_denormFract_T_4, io_out_c_result_bits_denormShiftDist_2) node io_out_c_result_bits_denormFract_2 = bits(_io_out_c_result_bits_denormFract_T_5, 22, 0) node _io_out_c_result_bits_expOut_T_12 = bits(io_out_c_result_bits_rawIn_2.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_13 = sub(_io_out_c_result_bits_expOut_T_12, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_14 = tail(_io_out_c_result_bits_expOut_T_13, 1) node _io_out_c_result_bits_expOut_T_15 = mux(io_out_c_result_bits_isSubnormal_2, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_14) node _io_out_c_result_bits_expOut_T_16 = or(io_out_c_result_bits_rawIn_2.isNaN, io_out_c_result_bits_rawIn_2.isInf) node _io_out_c_result_bits_expOut_T_17 = mux(_io_out_c_result_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_2 = or(_io_out_c_result_bits_expOut_T_15, _io_out_c_result_bits_expOut_T_17) node _io_out_c_result_bits_fractOut_T_4 = bits(io_out_c_result_bits_rawIn_2.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_5 = mux(io_out_c_result_bits_rawIn_2.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_4) node io_out_c_result_bits_fractOut_2 = mux(io_out_c_result_bits_isSubnormal_2, io_out_c_result_bits_denormFract_2, _io_out_c_result_bits_fractOut_T_5) node io_out_c_result_bits_hi_2 = cat(io_out_c_result_bits_rawIn_2.sign, io_out_c_result_bits_expOut_2) node _io_out_c_result_bits_T_2 = cat(io_out_c_result_bits_hi_2, io_out_c_result_bits_fractOut_2) connect io_out_c_result_2.bits, _io_out_c_result_bits_T_2 node io_out_c_self_rec_rawIn_sign_3 = bits(io_out_c_result_2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_3 = bits(io_out_c_result_2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_3 = bits(io_out_c_result_2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_3 = eq(io_out_c_self_rec_rawIn_expIn_3, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_3 = eq(io_out_c_self_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_132 = bits(io_out_c_self_rec_rawIn_fractIn_3, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_133 = bits(io_out_c_self_rec_rawIn_fractIn_3, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_134 = bits(io_out_c_self_rec_rawIn_fractIn_3, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_135 = bits(io_out_c_self_rec_rawIn_fractIn_3, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_136 = bits(io_out_c_self_rec_rawIn_fractIn_3, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_137 = bits(io_out_c_self_rec_rawIn_fractIn_3, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_138 = bits(io_out_c_self_rec_rawIn_fractIn_3, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_139 = bits(io_out_c_self_rec_rawIn_fractIn_3, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_140 = bits(io_out_c_self_rec_rawIn_fractIn_3, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_141 = bits(io_out_c_self_rec_rawIn_fractIn_3, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_142 = bits(io_out_c_self_rec_rawIn_fractIn_3, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_143 = bits(io_out_c_self_rec_rawIn_fractIn_3, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_144 = bits(io_out_c_self_rec_rawIn_fractIn_3, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_145 = bits(io_out_c_self_rec_rawIn_fractIn_3, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_146 = bits(io_out_c_self_rec_rawIn_fractIn_3, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_147 = bits(io_out_c_self_rec_rawIn_fractIn_3, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_148 = bits(io_out_c_self_rec_rawIn_fractIn_3, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_149 = bits(io_out_c_self_rec_rawIn_fractIn_3, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_150 = bits(io_out_c_self_rec_rawIn_fractIn_3, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_151 = bits(io_out_c_self_rec_rawIn_fractIn_3, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_152 = bits(io_out_c_self_rec_rawIn_fractIn_3, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_153 = bits(io_out_c_self_rec_rawIn_fractIn_3, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_154 = bits(io_out_c_self_rec_rawIn_fractIn_3, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_155 = mux(_io_out_c_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_156 = mux(_io_out_c_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_155) node _io_out_c_self_rec_rawIn_normDist_T_157 = mux(_io_out_c_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_156) node _io_out_c_self_rec_rawIn_normDist_T_158 = mux(_io_out_c_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_157) node _io_out_c_self_rec_rawIn_normDist_T_159 = mux(_io_out_c_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_158) node _io_out_c_self_rec_rawIn_normDist_T_160 = mux(_io_out_c_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_159) node _io_out_c_self_rec_rawIn_normDist_T_161 = mux(_io_out_c_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_160) node _io_out_c_self_rec_rawIn_normDist_T_162 = mux(_io_out_c_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_161) node _io_out_c_self_rec_rawIn_normDist_T_163 = mux(_io_out_c_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_162) node _io_out_c_self_rec_rawIn_normDist_T_164 = mux(_io_out_c_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_163) node _io_out_c_self_rec_rawIn_normDist_T_165 = mux(_io_out_c_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_164) node _io_out_c_self_rec_rawIn_normDist_T_166 = mux(_io_out_c_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_165) node _io_out_c_self_rec_rawIn_normDist_T_167 = mux(_io_out_c_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_166) node _io_out_c_self_rec_rawIn_normDist_T_168 = mux(_io_out_c_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_167) node _io_out_c_self_rec_rawIn_normDist_T_169 = mux(_io_out_c_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_168) node _io_out_c_self_rec_rawIn_normDist_T_170 = mux(_io_out_c_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_169) node _io_out_c_self_rec_rawIn_normDist_T_171 = mux(_io_out_c_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_170) node _io_out_c_self_rec_rawIn_normDist_T_172 = mux(_io_out_c_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_171) node _io_out_c_self_rec_rawIn_normDist_T_173 = mux(_io_out_c_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_172) node _io_out_c_self_rec_rawIn_normDist_T_174 = mux(_io_out_c_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_173) node _io_out_c_self_rec_rawIn_normDist_T_175 = mux(_io_out_c_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_174) node io_out_c_self_rec_rawIn_normDist_3 = mux(_io_out_c_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_175) node _io_out_c_self_rec_rawIn_subnormFract_T_6 = dshl(io_out_c_self_rec_rawIn_fractIn_3, io_out_c_self_rec_rawIn_normDist_3) node _io_out_c_self_rec_rawIn_subnormFract_T_7 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_6, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_3 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_7, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_15 = xor(io_out_c_self_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_16 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, _io_out_c_self_rec_rawIn_adjustedExp_T_15, io_out_c_self_rec_rawIn_expIn_3) node _io_out_c_self_rec_rawIn_adjustedExp_T_17 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_17) node _io_out_c_self_rec_rawIn_adjustedExp_T_19 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_16, _io_out_c_self_rec_rawIn_adjustedExp_T_18) node io_out_c_self_rec_rawIn_adjustedExp_3 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_19, 1) node io_out_c_self_rec_rawIn_isZero_3 = and(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) node _io_out_c_self_rec_rawIn_isSpecial_T_3 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_3 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_6 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_7 = and(io_out_c_self_rec_rawIn_isSpecial_3, _io_out_c_self_rec_rawIn_out_isNaN_T_6) connect io_out_c_self_rec_rawIn_3.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_7 node _io_out_c_self_rec_rawIn_out_isInf_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) connect io_out_c_self_rec_rawIn_3.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_3 connect io_out_c_self_rec_rawIn_3.isZero, io_out_c_self_rec_rawIn_isZero_3 connect io_out_c_self_rec_rawIn_3.sign, io_out_c_self_rec_rawIn_sign_3 node _io_out_c_self_rec_rawIn_out_sExp_T_6 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_7 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_6) connect io_out_c_self_rec_rawIn_3.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_7 node _io_out_c_self_rec_rawIn_out_sig_T_12 = eq(io_out_c_self_rec_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_12) node _io_out_c_self_rec_rawIn_out_sig_T_14 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_subnormFract_3, io_out_c_self_rec_rawIn_fractIn_3) node _io_out_c_self_rec_rawIn_out_sig_T_15 = cat(_io_out_c_self_rec_rawIn_out_sig_T_13, _io_out_c_self_rec_rawIn_out_sig_T_14) connect io_out_c_self_rec_rawIn_3.sig, _io_out_c_self_rec_rawIn_out_sig_T_15 node _io_out_c_self_rec_T_24 = bits(io_out_c_self_rec_rawIn_3.sExp, 8, 6) node _io_out_c_self_rec_T_25 = mux(io_out_c_self_rec_rawIn_3.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_24) node _io_out_c_self_rec_T_26 = mux(io_out_c_self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_27 = or(_io_out_c_self_rec_T_25, _io_out_c_self_rec_T_26) node _io_out_c_self_rec_T_28 = cat(io_out_c_self_rec_rawIn_3.sign, _io_out_c_self_rec_T_27) node _io_out_c_self_rec_T_29 = bits(io_out_c_self_rec_rawIn_3.sExp, 5, 0) node _io_out_c_self_rec_T_30 = cat(_io_out_c_self_rec_T_28, _io_out_c_self_rec_T_29) node _io_out_c_self_rec_T_31 = bits(io_out_c_self_rec_rawIn_3.sig, 22, 0) node io_out_c_self_rec_3 = cat(_io_out_c_self_rec_T_30, _io_out_c_self_rec_T_31) inst io_out_c_resizer_1 of RecFNToRecFN_190 connect io_out_c_resizer_1.io.in, io_out_c_self_rec_3 connect io_out_c_resizer_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer_1.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_3 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_3 = bits(io_out_c_resizer_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 6) node io_out_c_result_bits_rawIn_isZero_3 = eq(_io_out_c_result_bits_rawIn_isZero_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_3 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_6 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_7 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isNaN_T_6) connect io_out_c_result_bits_rawIn_3.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_7 node _io_out_c_result_bits_rawIn_out_isInf_T_9 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_10 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_9, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_11 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isInf_T_10) connect io_out_c_result_bits_rawIn_3.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_11 connect io_out_c_result_bits_rawIn_3.isZero, io_out_c_result_bits_rawIn_isZero_3 node _io_out_c_result_bits_rawIn_out_sign_T_3 = bits(io_out_c_resizer_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_3.sign, _io_out_c_result_bits_rawIn_out_sign_T_3 node _io_out_c_result_bits_rawIn_out_sExp_T_3 = cvt(io_out_c_result_bits_rawIn_exp_3) connect io_out_c_result_bits_rawIn_3.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_3 node _io_out_c_result_bits_rawIn_out_sig_T_12 = eq(io_out_c_result_bits_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_12) node _io_out_c_result_bits_rawIn_out_sig_T_14 = bits(io_out_c_resizer_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_15 = cat(_io_out_c_result_bits_rawIn_out_sig_T_13, _io_out_c_result_bits_rawIn_out_sig_T_14) connect io_out_c_result_bits_rawIn_3.sig, _io_out_c_result_bits_rawIn_out_sig_T_15 node io_out_c_result_bits_isSubnormal_3 = lt(io_out_c_result_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_6 = bits(io_out_c_result_bits_rawIn_3.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_6) node io_out_c_result_bits_denormShiftDist_3 = tail(_io_out_c_result_bits_denormShiftDist_T_7, 1) node _io_out_c_result_bits_denormFract_T_6 = shr(io_out_c_result_bits_rawIn_3.sig, 1) node _io_out_c_result_bits_denormFract_T_7 = dshr(_io_out_c_result_bits_denormFract_T_6, io_out_c_result_bits_denormShiftDist_3) node io_out_c_result_bits_denormFract_3 = bits(_io_out_c_result_bits_denormFract_T_7, 22, 0) node _io_out_c_result_bits_expOut_T_18 = bits(io_out_c_result_bits_rawIn_3.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_19 = sub(_io_out_c_result_bits_expOut_T_18, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_20 = tail(_io_out_c_result_bits_expOut_T_19, 1) node _io_out_c_result_bits_expOut_T_21 = mux(io_out_c_result_bits_isSubnormal_3, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_20) node _io_out_c_result_bits_expOut_T_22 = or(io_out_c_result_bits_rawIn_3.isNaN, io_out_c_result_bits_rawIn_3.isInf) node _io_out_c_result_bits_expOut_T_23 = mux(_io_out_c_result_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_3 = or(_io_out_c_result_bits_expOut_T_21, _io_out_c_result_bits_expOut_T_23) node _io_out_c_result_bits_fractOut_T_6 = bits(io_out_c_result_bits_rawIn_3.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_7 = mux(io_out_c_result_bits_rawIn_3.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_6) node io_out_c_result_bits_fractOut_3 = mux(io_out_c_result_bits_isSubnormal_3, io_out_c_result_bits_denormFract_3, _io_out_c_result_bits_fractOut_T_7) node io_out_c_result_bits_hi_3 = cat(io_out_c_result_bits_rawIn_3.sign, io_out_c_result_bits_expOut_3) node _io_out_c_result_bits_T_3 = cat(io_out_c_result_bits_hi_3, io_out_c_result_bits_fractOut_3) connect io_out_c_result_3.bits, _io_out_c_result_bits_T_3 connect io.out_c, io_out_c_result_3 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_2 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_3 : UInt<32> connect _mac_unit_io_in_b_WIRE_3, io.in_b.bits node _mac_unit_io_in_b_T_1 = bits(_mac_unit_io_in_b_WIRE_3, 31, 0) connect _mac_unit_io_in_b_WIRE_2.bits, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_2.bits connect mac_unit.io.in_c.bits, c1.bits connect c1, mac_unit.io.out_d node c2_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c2_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c2_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c2_self_rec_rawIn_isZeroExpIn = eq(c2_self_rec_rawIn_expIn, UInt<1>(0h0)) node c2_self_rec_rawIn_isZeroFractIn = eq(c2_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_normDist_T = bits(c2_self_rec_rawIn_fractIn, 0, 0) node _c2_self_rec_rawIn_normDist_T_1 = bits(c2_self_rec_rawIn_fractIn, 1, 1) node _c2_self_rec_rawIn_normDist_T_2 = bits(c2_self_rec_rawIn_fractIn, 2, 2) node _c2_self_rec_rawIn_normDist_T_3 = bits(c2_self_rec_rawIn_fractIn, 3, 3) node _c2_self_rec_rawIn_normDist_T_4 = bits(c2_self_rec_rawIn_fractIn, 4, 4) node _c2_self_rec_rawIn_normDist_T_5 = bits(c2_self_rec_rawIn_fractIn, 5, 5) node _c2_self_rec_rawIn_normDist_T_6 = bits(c2_self_rec_rawIn_fractIn, 6, 6) node _c2_self_rec_rawIn_normDist_T_7 = bits(c2_self_rec_rawIn_fractIn, 7, 7) node _c2_self_rec_rawIn_normDist_T_8 = bits(c2_self_rec_rawIn_fractIn, 8, 8) node _c2_self_rec_rawIn_normDist_T_9 = bits(c2_self_rec_rawIn_fractIn, 9, 9) node _c2_self_rec_rawIn_normDist_T_10 = bits(c2_self_rec_rawIn_fractIn, 10, 10) node _c2_self_rec_rawIn_normDist_T_11 = bits(c2_self_rec_rawIn_fractIn, 11, 11) node _c2_self_rec_rawIn_normDist_T_12 = bits(c2_self_rec_rawIn_fractIn, 12, 12) node _c2_self_rec_rawIn_normDist_T_13 = bits(c2_self_rec_rawIn_fractIn, 13, 13) node _c2_self_rec_rawIn_normDist_T_14 = bits(c2_self_rec_rawIn_fractIn, 14, 14) node _c2_self_rec_rawIn_normDist_T_15 = bits(c2_self_rec_rawIn_fractIn, 15, 15) node _c2_self_rec_rawIn_normDist_T_16 = bits(c2_self_rec_rawIn_fractIn, 16, 16) node _c2_self_rec_rawIn_normDist_T_17 = bits(c2_self_rec_rawIn_fractIn, 17, 17) node _c2_self_rec_rawIn_normDist_T_18 = bits(c2_self_rec_rawIn_fractIn, 18, 18) node _c2_self_rec_rawIn_normDist_T_19 = bits(c2_self_rec_rawIn_fractIn, 19, 19) node _c2_self_rec_rawIn_normDist_T_20 = bits(c2_self_rec_rawIn_fractIn, 20, 20) node _c2_self_rec_rawIn_normDist_T_21 = bits(c2_self_rec_rawIn_fractIn, 21, 21) node _c2_self_rec_rawIn_normDist_T_22 = bits(c2_self_rec_rawIn_fractIn, 22, 22) node _c2_self_rec_rawIn_normDist_T_23 = mux(_c2_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c2_self_rec_rawIn_normDist_T_24 = mux(_c2_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c2_self_rec_rawIn_normDist_T_23) node _c2_self_rec_rawIn_normDist_T_25 = mux(_c2_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c2_self_rec_rawIn_normDist_T_24) node _c2_self_rec_rawIn_normDist_T_26 = mux(_c2_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c2_self_rec_rawIn_normDist_T_25) node _c2_self_rec_rawIn_normDist_T_27 = mux(_c2_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c2_self_rec_rawIn_normDist_T_26) node _c2_self_rec_rawIn_normDist_T_28 = mux(_c2_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c2_self_rec_rawIn_normDist_T_27) node _c2_self_rec_rawIn_normDist_T_29 = mux(_c2_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c2_self_rec_rawIn_normDist_T_28) node _c2_self_rec_rawIn_normDist_T_30 = mux(_c2_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c2_self_rec_rawIn_normDist_T_29) node _c2_self_rec_rawIn_normDist_T_31 = mux(_c2_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c2_self_rec_rawIn_normDist_T_30) node _c2_self_rec_rawIn_normDist_T_32 = mux(_c2_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c2_self_rec_rawIn_normDist_T_31) node _c2_self_rec_rawIn_normDist_T_33 = mux(_c2_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c2_self_rec_rawIn_normDist_T_32) node _c2_self_rec_rawIn_normDist_T_34 = mux(_c2_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c2_self_rec_rawIn_normDist_T_33) node _c2_self_rec_rawIn_normDist_T_35 = mux(_c2_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c2_self_rec_rawIn_normDist_T_34) node _c2_self_rec_rawIn_normDist_T_36 = mux(_c2_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c2_self_rec_rawIn_normDist_T_35) node _c2_self_rec_rawIn_normDist_T_37 = mux(_c2_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c2_self_rec_rawIn_normDist_T_36) node _c2_self_rec_rawIn_normDist_T_38 = mux(_c2_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c2_self_rec_rawIn_normDist_T_37) node _c2_self_rec_rawIn_normDist_T_39 = mux(_c2_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c2_self_rec_rawIn_normDist_T_38) node _c2_self_rec_rawIn_normDist_T_40 = mux(_c2_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c2_self_rec_rawIn_normDist_T_39) node _c2_self_rec_rawIn_normDist_T_41 = mux(_c2_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c2_self_rec_rawIn_normDist_T_40) node _c2_self_rec_rawIn_normDist_T_42 = mux(_c2_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c2_self_rec_rawIn_normDist_T_41) node _c2_self_rec_rawIn_normDist_T_43 = mux(_c2_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c2_self_rec_rawIn_normDist_T_42) node c2_self_rec_rawIn_normDist = mux(_c2_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c2_self_rec_rawIn_normDist_T_43) node _c2_self_rec_rawIn_subnormFract_T = dshl(c2_self_rec_rawIn_fractIn, c2_self_rec_rawIn_normDist) node _c2_self_rec_rawIn_subnormFract_T_1 = bits(_c2_self_rec_rawIn_subnormFract_T, 21, 0) node c2_self_rec_rawIn_subnormFract = shl(_c2_self_rec_rawIn_subnormFract_T_1, 1) node _c2_self_rec_rawIn_adjustedExp_T = xor(c2_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c2_self_rec_rawIn_adjustedExp_T_1 = mux(c2_self_rec_rawIn_isZeroExpIn, _c2_self_rec_rawIn_adjustedExp_T, c2_self_rec_rawIn_expIn) node _c2_self_rec_rawIn_adjustedExp_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c2_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c2_self_rec_rawIn_adjustedExp_T_2) node _c2_self_rec_rawIn_adjustedExp_T_4 = add(_c2_self_rec_rawIn_adjustedExp_T_1, _c2_self_rec_rawIn_adjustedExp_T_3) node c2_self_rec_rawIn_adjustedExp = tail(_c2_self_rec_rawIn_adjustedExp_T_4, 1) node c2_self_rec_rawIn_isZero = and(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_isZeroFractIn) node _c2_self_rec_rawIn_isSpecial_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 7) node c2_self_rec_rawIn_isSpecial = eq(_c2_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_self_rec_rawIn_out_isNaN_T = eq(c2_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_isNaN_T_1 = and(c2_self_rec_rawIn_isSpecial, _c2_self_rec_rawIn_out_isNaN_T) connect c2_self_rec_rawIn.isNaN, _c2_self_rec_rawIn_out_isNaN_T_1 node _c2_self_rec_rawIn_out_isInf_T = and(c2_self_rec_rawIn_isSpecial, c2_self_rec_rawIn_isZeroFractIn) connect c2_self_rec_rawIn.isInf, _c2_self_rec_rawIn_out_isInf_T connect c2_self_rec_rawIn.isZero, c2_self_rec_rawIn_isZero connect c2_self_rec_rawIn.sign, c2_self_rec_rawIn_sign node _c2_self_rec_rawIn_out_sExp_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 0) node _c2_self_rec_rawIn_out_sExp_T_1 = cvt(_c2_self_rec_rawIn_out_sExp_T) connect c2_self_rec_rawIn.sExp, _c2_self_rec_rawIn_out_sExp_T_1 node _c2_self_rec_rawIn_out_sig_T = eq(c2_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_self_rec_rawIn_out_sig_T) node _c2_self_rec_rawIn_out_sig_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_subnormFract, c2_self_rec_rawIn_fractIn) node _c2_self_rec_rawIn_out_sig_T_3 = cat(_c2_self_rec_rawIn_out_sig_T_1, _c2_self_rec_rawIn_out_sig_T_2) connect c2_self_rec_rawIn.sig, _c2_self_rec_rawIn_out_sig_T_3 node _c2_self_rec_T = bits(c2_self_rec_rawIn.sExp, 8, 6) node _c2_self_rec_T_1 = mux(c2_self_rec_rawIn.isZero, UInt<3>(0h0), _c2_self_rec_T) node _c2_self_rec_T_2 = mux(c2_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c2_self_rec_T_3 = or(_c2_self_rec_T_1, _c2_self_rec_T_2) node _c2_self_rec_T_4 = cat(c2_self_rec_rawIn.sign, _c2_self_rec_T_3) node _c2_self_rec_T_5 = bits(c2_self_rec_rawIn.sExp, 5, 0) node _c2_self_rec_T_6 = cat(_c2_self_rec_T_4, _c2_self_rec_T_5) node _c2_self_rec_T_7 = bits(c2_self_rec_rawIn.sig, 22, 0) node c2_self_rec = cat(_c2_self_rec_T_6, _c2_self_rec_T_7) inst c2_resizer of RecFNToRecFN_191 connect c2_resizer.io.in, c2_self_rec connect c2_resizer.io.roundingMode, UInt<3>(0h0) connect c2_resizer.io.detectTininess, UInt<1>(0h1) wire c2_result : { bits : UInt<32>} node c2_result_bits_rawIn_exp = bits(c2_resizer.io.out, 31, 23) node _c2_result_bits_rawIn_isZero_T = bits(c2_result_bits_rawIn_exp, 8, 6) node c2_result_bits_rawIn_isZero = eq(_c2_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_isSpecial_T = bits(c2_result_bits_rawIn_exp, 8, 7) node c2_result_bits_rawIn_isSpecial = eq(_c2_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_result_bits_rawIn_out_isNaN_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isNaN_T_1 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isNaN_T) connect c2_result_bits_rawIn.isNaN, _c2_result_bits_rawIn_out_isNaN_T_1 node _c2_result_bits_rawIn_out_isInf_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isInf_T_1 = eq(_c2_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_isInf_T_2 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isInf_T_1) connect c2_result_bits_rawIn.isInf, _c2_result_bits_rawIn_out_isInf_T_2 connect c2_result_bits_rawIn.isZero, c2_result_bits_rawIn_isZero node _c2_result_bits_rawIn_out_sign_T = bits(c2_resizer.io.out, 32, 32) connect c2_result_bits_rawIn.sign, _c2_result_bits_rawIn_out_sign_T node _c2_result_bits_rawIn_out_sExp_T = cvt(c2_result_bits_rawIn_exp) connect c2_result_bits_rawIn.sExp, _c2_result_bits_rawIn_out_sExp_T node _c2_result_bits_rawIn_out_sig_T = eq(c2_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_result_bits_rawIn_out_sig_T) node _c2_result_bits_rawIn_out_sig_T_2 = bits(c2_resizer.io.out, 22, 0) node _c2_result_bits_rawIn_out_sig_T_3 = cat(_c2_result_bits_rawIn_out_sig_T_1, _c2_result_bits_rawIn_out_sig_T_2) connect c2_result_bits_rawIn.sig, _c2_result_bits_rawIn_out_sig_T_3 node c2_result_bits_isSubnormal = lt(c2_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c2_result_bits_denormShiftDist_T = bits(c2_result_bits_rawIn.sExp, 4, 0) node _c2_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c2_result_bits_denormShiftDist_T) node c2_result_bits_denormShiftDist = tail(_c2_result_bits_denormShiftDist_T_1, 1) node _c2_result_bits_denormFract_T = shr(c2_result_bits_rawIn.sig, 1) node _c2_result_bits_denormFract_T_1 = dshr(_c2_result_bits_denormFract_T, c2_result_bits_denormShiftDist) node c2_result_bits_denormFract = bits(_c2_result_bits_denormFract_T_1, 22, 0) node _c2_result_bits_expOut_T = bits(c2_result_bits_rawIn.sExp, 7, 0) node _c2_result_bits_expOut_T_1 = sub(_c2_result_bits_expOut_T, UInt<8>(0h81)) node _c2_result_bits_expOut_T_2 = tail(_c2_result_bits_expOut_T_1, 1) node _c2_result_bits_expOut_T_3 = mux(c2_result_bits_isSubnormal, UInt<1>(0h0), _c2_result_bits_expOut_T_2) node _c2_result_bits_expOut_T_4 = or(c2_result_bits_rawIn.isNaN, c2_result_bits_rawIn.isInf) node _c2_result_bits_expOut_T_5 = mux(_c2_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c2_result_bits_expOut = or(_c2_result_bits_expOut_T_3, _c2_result_bits_expOut_T_5) node _c2_result_bits_fractOut_T = bits(c2_result_bits_rawIn.sig, 22, 0) node _c2_result_bits_fractOut_T_1 = mux(c2_result_bits_rawIn.isInf, UInt<1>(0h0), _c2_result_bits_fractOut_T) node c2_result_bits_fractOut = mux(c2_result_bits_isSubnormal, c2_result_bits_denormFract, _c2_result_bits_fractOut_T_1) node c2_result_bits_hi = cat(c2_result_bits_rawIn.sign, c2_result_bits_expOut) node _c2_result_bits_T = cat(c2_result_bits_hi, c2_result_bits_fractOut) connect c2_result.bits, _c2_result_bits_T connect c2, c2_result else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_4 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_5 : UInt<32> connect _mac_unit_io_in_b_WIRE_5, c2.bits node _mac_unit_io_in_b_T_2 = bits(_mac_unit_io_in_b_WIRE_5, 31, 0) connect _mac_unit_io_in_b_WIRE_4.bits, _mac_unit_io_in_b_T_2 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_4.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_6 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_7 : UInt<32> connect _mac_unit_io_in_b_WIRE_7, c1.bits node _mac_unit_io_in_b_T_3 = bits(_mac_unit_io_in_b_WIRE_7, 31, 0) connect _mac_unit_io_in_b_WIRE_6.bits, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_6.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c.bits invalidate io.out_b.bits wire _mac_unit_io_in_b_WIRE_8 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_9 : UInt<32> connect _mac_unit_io_in_b_WIRE_9, io.in_b.bits node _mac_unit_io_in_b_T_4 = bits(_mac_unit_io_in_b_WIRE_9, 31, 0) connect _mac_unit_io_in_b_WIRE_8.bits, _mac_unit_io_in_b_T_4 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_8.bits connect mac_unit.io.in_c.bits, c2.bits node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b.bits invalidate mac_unit.io.in_c.bits	module PE_23( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [31:0] io_in_a_bits, // @[PE.scala:35:14] input [31:0] io_in_b_bits, // @[PE.scala:35:14] input [31:0] io_in_d_bits, // @[PE.scala:35:14] output [31:0] io_out_a_bits, // @[PE.scala:35:14] output [31:0] io_out_b_bits, // @[PE.scala:35:14] output [31:0] io_out_c_bits, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [3:0] io_in_id, // @[PE.scala:35:14] output [3:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30] wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30] wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7] wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15] wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7] wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37] wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37] wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7] wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7] reg [31:0] c1_bits; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38] reg [31:0] c2_bits; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] \| _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29] wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34] wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34] wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] \| _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T = \|io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15] wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}] wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26] wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN \| io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 \| _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] \| _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26] wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN \| io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 \| _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37] assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37] wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] \| _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26] wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN \| c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 \| _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] \| _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29] wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] \| _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T_4 = \|io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15] wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_76 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_89 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_76( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_89 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EntropyCompressorMemwriter_2 : input clock : Clock input reset : Reset output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, l2io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip decompress_dest_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>}}, bufs_completed : UInt<64>, no_writes_inflight : UInt<1>} inst incoming_writes_Q of Queue4_WriterBundle_8 connect incoming_writes_Q.clock, clock connect incoming_writes_Q.reset, reset connect incoming_writes_Q.io.enq, io.memwrites_in inst decompress_dest_info_Q of Queue4_DstInfo_9 connect decompress_dest_info_Q.clock, clock connect decompress_dest_info_Q.reset, reset connect decompress_dest_info_Q.io.enq, io.decompress_dest_info node _decompress_dest_last_fire_T = and(decompress_dest_info_Q.io.deq.ready, decompress_dest_info_Q.io.deq.valid) reg decompress_dest_last_fire : UInt<1>, clock connect decompress_dest_last_fire, _decompress_dest_last_fire_T reg decompress_dest_last_valid : UInt<1>, clock connect decompress_dest_last_valid, decompress_dest_info_Q.io.deq.valid node _decompress_dest_printhelp_T = eq(decompress_dest_last_valid, UInt<1>(0h0)) node _decompress_dest_printhelp_T_1 = or(decompress_dest_last_fire, _decompress_dest_printhelp_T) node decompress_dest_printhelp = and(decompress_dest_info_Q.io.deq.valid, _decompress_dest_printhelp_T_1) when decompress_dest_printhelp : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] got dest info op: 0x%x, cmpflag 0x%x\n", decompress_dest_info_Q.io.deq.bits.op, decompress_dest_info_Q.io.deq.bits.cmpflag) : printf_1 inst buf_lens_Q of Queue10_UInt64_13 connect buf_lens_Q.clock, clock connect buf_lens_Q.reset, reset node _T_4 = and(buf_lens_Q.io.enq.ready, buf_lens_Q.io.enq.valid) when _T_4 : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits) : printf_3 regreset buf_len_tracker : UInt<64>, clock, reset, UInt<64>(0h0) node _T_9 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_9 : when incoming_writes_Q.io.deq.bits.end_of_message : connect buf_len_tracker, UInt<1>(0h0) else : node _buf_len_tracker_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_len_tracker, _buf_len_tracker_T node _T_10 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_10 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_5 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue16_UInt8 of Queue16_UInt8_96 connect Queue16_UInt8.clock, clock connect Queue16_UInt8.reset, reset inst Queue16_UInt8_1 of Queue16_UInt8_97 connect Queue16_UInt8_1.clock, clock connect Queue16_UInt8_1.reset, reset inst Queue16_UInt8_2 of Queue16_UInt8_98 connect Queue16_UInt8_2.clock, clock connect Queue16_UInt8_2.reset, reset inst Queue16_UInt8_3 of Queue16_UInt8_99 connect Queue16_UInt8_3.clock, clock connect Queue16_UInt8_3.reset, reset inst Queue16_UInt8_4 of Queue16_UInt8_100 connect Queue16_UInt8_4.clock, clock connect Queue16_UInt8_4.reset, reset inst Queue16_UInt8_5 of Queue16_UInt8_101 connect Queue16_UInt8_5.clock, clock connect Queue16_UInt8_5.reset, reset inst Queue16_UInt8_6 of Queue16_UInt8_102 connect Queue16_UInt8_6.clock, clock connect Queue16_UInt8_6.reset, reset inst Queue16_UInt8_7 of Queue16_UInt8_103 connect Queue16_UInt8_7.clock, clock connect Queue16_UInt8_7.reset, reset inst Queue16_UInt8_8 of Queue16_UInt8_104 connect Queue16_UInt8_8.clock, clock connect Queue16_UInt8_8.reset, reset inst Queue16_UInt8_9 of Queue16_UInt8_105 connect Queue16_UInt8_9.clock, clock connect Queue16_UInt8_9.reset, reset inst Queue16_UInt8_10 of Queue16_UInt8_106 connect Queue16_UInt8_10.clock, clock connect Queue16_UInt8_10.reset, reset inst Queue16_UInt8_11 of Queue16_UInt8_107 connect Queue16_UInt8_11.clock, clock connect Queue16_UInt8_11.reset, reset inst Queue16_UInt8_12 of Queue16_UInt8_108 connect Queue16_UInt8_12.clock, clock connect Queue16_UInt8_12.reset, reset inst Queue16_UInt8_13 of Queue16_UInt8_109 connect Queue16_UInt8_13.clock, clock connect Queue16_UInt8_13.reset, reset inst Queue16_UInt8_14 of Queue16_UInt8_110 connect Queue16_UInt8_14.clock, clock connect Queue16_UInt8_14.reset, reset inst Queue16_UInt8_15 of Queue16_UInt8_111 connect Queue16_UInt8_15.clock, clock connect Queue16_UInt8_15.reset, reset inst Queue16_UInt8_16 of Queue16_UInt8_112 connect Queue16_UInt8_16.clock, clock connect Queue16_UInt8_16.reset, reset inst Queue16_UInt8_17 of Queue16_UInt8_113 connect Queue16_UInt8_17.clock, clock connect Queue16_UInt8_17.reset, reset inst Queue16_UInt8_18 of Queue16_UInt8_114 connect Queue16_UInt8_18.clock, clock connect Queue16_UInt8_18.reset, reset inst Queue16_UInt8_19 of Queue16_UInt8_115 connect Queue16_UInt8_19.clock, clock connect Queue16_UInt8_19.reset, reset inst Queue16_UInt8_20 of Queue16_UInt8_116 connect Queue16_UInt8_20.clock, clock connect Queue16_UInt8_20.reset, reset inst Queue16_UInt8_21 of Queue16_UInt8_117 connect Queue16_UInt8_21.clock, clock connect Queue16_UInt8_21.reset, reset inst Queue16_UInt8_22 of Queue16_UInt8_118 connect Queue16_UInt8_22.clock, clock connect Queue16_UInt8_22.reset, reset inst Queue16_UInt8_23 of Queue16_UInt8_119 connect Queue16_UInt8_23.clock, clock connect Queue16_UInt8_23.reset, reset inst Queue16_UInt8_24 of Queue16_UInt8_120 connect Queue16_UInt8_24.clock, clock connect Queue16_UInt8_24.reset, reset inst Queue16_UInt8_25 of Queue16_UInt8_121 connect Queue16_UInt8_25.clock, clock connect Queue16_UInt8_25.reset, reset inst Queue16_UInt8_26 of Queue16_UInt8_122 connect Queue16_UInt8_26.clock, clock connect Queue16_UInt8_26.reset, reset inst Queue16_UInt8_27 of Queue16_UInt8_123 connect Queue16_UInt8_27.clock, clock connect Queue16_UInt8_27.reset, reset inst Queue16_UInt8_28 of Queue16_UInt8_124 connect Queue16_UInt8_28.clock, clock connect Queue16_UInt8_28.reset, reset inst Queue16_UInt8_29 of Queue16_UInt8_125 connect Queue16_UInt8_29.clock, clock connect Queue16_UInt8_29.reset, reset inst Queue16_UInt8_30 of Queue16_UInt8_126 connect Queue16_UInt8_30.clock, clock connect Queue16_UInt8_30.reset, reset inst Queue16_UInt8_31 of Queue16_UInt8_127 connect Queue16_UInt8_31.clock, clock connect Queue16_UInt8_31.reset, reset connect Queue16_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_15 = eq(UInt<1>(0h0), idx) when _T_15 : node _T_16 = shl(UInt<1>(0h0), 3) node _T_17 = dshr(incoming_writes_Q.io.deq.bits.data, _T_16) node _T_18 = bits(_T_17, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_18 node _T_19 = eq(UInt<1>(0h1), idx) when _T_19 : node _T_20 = shl(UInt<1>(0h0), 3) node _T_21 = dshr(incoming_writes_Q.io.deq.bits.data, _T_20) node _T_22 = bits(_T_21, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_22 node _T_23 = eq(UInt<2>(0h2), idx) when _T_23 : node _T_24 = shl(UInt<1>(0h0), 3) node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24) node _T_26 = bits(_T_25, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_26 node _T_27 = eq(UInt<2>(0h3), idx) when _T_27 : node _T_28 = shl(UInt<1>(0h0), 3) node _T_29 = dshr(incoming_writes_Q.io.deq.bits.data, _T_28) node _T_30 = bits(_T_29, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_30 node _T_31 = eq(UInt<3>(0h4), idx) when _T_31 : node _T_32 = shl(UInt<1>(0h0), 3) node _T_33 = dshr(incoming_writes_Q.io.deq.bits.data, _T_32) node _T_34 = bits(_T_33, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_34 node _T_35 = eq(UInt<3>(0h5), idx) when _T_35 : node _T_36 = shl(UInt<1>(0h0), 3) node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36) node _T_38 = bits(_T_37, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_38 node _T_39 = eq(UInt<3>(0h6), idx) when _T_39 : node _T_40 = shl(UInt<1>(0h0), 3) node _T_41 = dshr(incoming_writes_Q.io.deq.bits.data, _T_40) node _T_42 = bits(_T_41, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_42 node _T_43 = eq(UInt<3>(0h7), idx) when _T_43 : node _T_44 = shl(UInt<1>(0h0), 3) node _T_45 = dshr(incoming_writes_Q.io.deq.bits.data, _T_44) node _T_46 = bits(_T_45, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_46 node _T_47 = eq(UInt<4>(0h8), idx) when _T_47 : node _T_48 = shl(UInt<1>(0h0), 3) node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48) node _T_50 = bits(_T_49, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_50 node _T_51 = eq(UInt<4>(0h9), idx) when _T_51 : node _T_52 = shl(UInt<1>(0h0), 3) node _T_53 = dshr(incoming_writes_Q.io.deq.bits.data, _T_52) node _T_54 = bits(_T_53, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_54 node _T_55 = eq(UInt<4>(0ha), idx) when _T_55 : node _T_56 = shl(UInt<1>(0h0), 3) node _T_57 = dshr(incoming_writes_Q.io.deq.bits.data, _T_56) node _T_58 = bits(_T_57, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_58 node _T_59 = eq(UInt<4>(0hb), idx) when _T_59 : node _T_60 = shl(UInt<1>(0h0), 3) node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60) node _T_62 = bits(_T_61, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_62 node _T_63 = eq(UInt<4>(0hc), idx) when _T_63 : node _T_64 = shl(UInt<1>(0h0), 3) node _T_65 = dshr(incoming_writes_Q.io.deq.bits.data, _T_64) node _T_66 = bits(_T_65, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_66 node _T_67 = eq(UInt<4>(0hd), idx) when _T_67 : node _T_68 = shl(UInt<1>(0h0), 3) node _T_69 = dshr(incoming_writes_Q.io.deq.bits.data, _T_68) node _T_70 = bits(_T_69, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_70 node _T_71 = eq(UInt<4>(0he), idx) when _T_71 : node _T_72 = shl(UInt<1>(0h0), 3) node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72) node _T_74 = bits(_T_73, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_74 node _T_75 = eq(UInt<4>(0hf), idx) when _T_75 : node _T_76 = shl(UInt<1>(0h0), 3) node _T_77 = dshr(incoming_writes_Q.io.deq.bits.data, _T_76) node _T_78 = bits(_T_77, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_78 node _T_79 = eq(UInt<5>(0h10), idx) when _T_79 : node _T_80 = shl(UInt<1>(0h0), 3) node _T_81 = dshr(incoming_writes_Q.io.deq.bits.data, _T_80) node _T_82 = bits(_T_81, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_82 node _T_83 = eq(UInt<5>(0h11), idx) when _T_83 : node _T_84 = shl(UInt<1>(0h0), 3) node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84) node _T_86 = bits(_T_85, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_86 node _T_87 = eq(UInt<5>(0h12), idx) when _T_87 : node _T_88 = shl(UInt<1>(0h0), 3) node _T_89 = dshr(incoming_writes_Q.io.deq.bits.data, _T_88) node _T_90 = bits(_T_89, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_90 node _T_91 = eq(UInt<5>(0h13), idx) when _T_91 : node _T_92 = shl(UInt<1>(0h0), 3) node _T_93 = dshr(incoming_writes_Q.io.deq.bits.data, _T_92) node _T_94 = bits(_T_93, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_94 node _T_95 = eq(UInt<5>(0h14), idx) when _T_95 : node _T_96 = shl(UInt<1>(0h0), 3) node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96) node _T_98 = bits(_T_97, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_98 node _T_99 = eq(UInt<5>(0h15), idx) when _T_99 : node _T_100 = shl(UInt<1>(0h0), 3) node _T_101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_100) node _T_102 = bits(_T_101, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_102 node _T_103 = eq(UInt<5>(0h16), idx) when _T_103 : node _T_104 = shl(UInt<1>(0h0), 3) node _T_105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_104) node _T_106 = bits(_T_105, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_106 node _T_107 = eq(UInt<5>(0h17), idx) when _T_107 : node _T_108 = shl(UInt<1>(0h0), 3) node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108) node _T_110 = bits(_T_109, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_110 node _T_111 = eq(UInt<5>(0h18), idx) when _T_111 : node _T_112 = shl(UInt<1>(0h0), 3) node _T_113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_112) node _T_114 = bits(_T_113, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_114 node _T_115 = eq(UInt<5>(0h19), idx) when _T_115 : node _T_116 = shl(UInt<1>(0h0), 3) node _T_117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_116) node _T_118 = bits(_T_117, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_118 node _T_119 = eq(UInt<5>(0h1a), idx) when _T_119 : node _T_120 = shl(UInt<1>(0h0), 3) node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120) node _T_122 = bits(_T_121, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_122 node _T_123 = eq(UInt<5>(0h1b), idx) when _T_123 : node _T_124 = shl(UInt<1>(0h0), 3) node _T_125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_124) node _T_126 = bits(_T_125, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_126 node _T_127 = eq(UInt<5>(0h1c), idx) when _T_127 : node _T_128 = shl(UInt<1>(0h0), 3) node _T_129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_128) node _T_130 = bits(_T_129, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_130 node _T_131 = eq(UInt<5>(0h1d), idx) when _T_131 : node _T_132 = shl(UInt<1>(0h0), 3) node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132) node _T_134 = bits(_T_133, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_134 node _T_135 = eq(UInt<5>(0h1e), idx) when _T_135 : node _T_136 = shl(UInt<1>(0h0), 3) node _T_137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_136) node _T_138 = bits(_T_137, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_138 node _T_139 = eq(UInt<5>(0h1f), idx) when _T_139 : node _T_140 = shl(UInt<1>(0h0), 3) node _T_141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_140) node _T_142 = bits(_T_141, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_142 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_143 = eq(UInt<1>(0h0), idx_1) when _T_143 : node _T_144 = shl(UInt<1>(0h1), 3) node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144) node _T_146 = bits(_T_145, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_146 node _T_147 = eq(UInt<1>(0h1), idx_1) when _T_147 : node _T_148 = shl(UInt<1>(0h1), 3) node _T_149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_148) node _T_150 = bits(_T_149, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_150 node _T_151 = eq(UInt<2>(0h2), idx_1) when _T_151 : node _T_152 = shl(UInt<1>(0h1), 3) node _T_153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_152) node _T_154 = bits(_T_153, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_154 node _T_155 = eq(UInt<2>(0h3), idx_1) when _T_155 : node _T_156 = shl(UInt<1>(0h1), 3) node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156) node _T_158 = bits(_T_157, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_158 node _T_159 = eq(UInt<3>(0h4), idx_1) when _T_159 : node _T_160 = shl(UInt<1>(0h1), 3) node _T_161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_160) node _T_162 = bits(_T_161, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_162 node _T_163 = eq(UInt<3>(0h5), idx_1) when _T_163 : node _T_164 = shl(UInt<1>(0h1), 3) node _T_165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_164) node _T_166 = bits(_T_165, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_166 node _T_167 = eq(UInt<3>(0h6), idx_1) when _T_167 : node _T_168 = shl(UInt<1>(0h1), 3) node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168) node _T_170 = bits(_T_169, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_170 node _T_171 = eq(UInt<3>(0h7), idx_1) when _T_171 : node _T_172 = shl(UInt<1>(0h1), 3) node _T_173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_172) node _T_174 = bits(_T_173, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_174 node _T_175 = eq(UInt<4>(0h8), idx_1) when _T_175 : node _T_176 = shl(UInt<1>(0h1), 3) node _T_177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_176) node _T_178 = bits(_T_177, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_178 node _T_179 = eq(UInt<4>(0h9), idx_1) when _T_179 : node _T_180 = shl(UInt<1>(0h1), 3) node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180) node _T_182 = bits(_T_181, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_182 node _T_183 = eq(UInt<4>(0ha), idx_1) when _T_183 : node _T_184 = shl(UInt<1>(0h1), 3) node _T_185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_184) node _T_186 = bits(_T_185, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_186 node _T_187 = eq(UInt<4>(0hb), idx_1) when _T_187 : node _T_188 = shl(UInt<1>(0h1), 3) node _T_189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_188) node _T_190 = bits(_T_189, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_190 node _T_191 = eq(UInt<4>(0hc), idx_1) when _T_191 : node _T_192 = shl(UInt<1>(0h1), 3) node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192) node _T_194 = bits(_T_193, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_194 node _T_195 = eq(UInt<4>(0hd), idx_1) when _T_195 : node _T_196 = shl(UInt<1>(0h1), 3) node _T_197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_196) node _T_198 = bits(_T_197, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_198 node _T_199 = eq(UInt<4>(0he), idx_1) when _T_199 : node _T_200 = shl(UInt<1>(0h1), 3) node _T_201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_200) node _T_202 = bits(_T_201, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_202 node _T_203 = eq(UInt<4>(0hf), idx_1) when _T_203 : node _T_204 = shl(UInt<1>(0h1), 3) node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204) node _T_206 = bits(_T_205, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_206 node _T_207 = eq(UInt<5>(0h10), idx_1) when _T_207 : node _T_208 = shl(UInt<1>(0h1), 3) node _T_209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_208) node _T_210 = bits(_T_209, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_210 node _T_211 = eq(UInt<5>(0h11), idx_1) when _T_211 : node _T_212 = shl(UInt<1>(0h1), 3) node _T_213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_212) node _T_214 = bits(_T_213, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_214 node _T_215 = eq(UInt<5>(0h12), idx_1) when _T_215 : node _T_216 = shl(UInt<1>(0h1), 3) node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216) node _T_218 = bits(_T_217, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_218 node _T_219 = eq(UInt<5>(0h13), idx_1) when _T_219 : node _T_220 = shl(UInt<1>(0h1), 3) node _T_221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_220) node _T_222 = bits(_T_221, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_222 node _T_223 = eq(UInt<5>(0h14), idx_1) when _T_223 : node _T_224 = shl(UInt<1>(0h1), 3) node _T_225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_224) node _T_226 = bits(_T_225, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_226 node _T_227 = eq(UInt<5>(0h15), idx_1) when _T_227 : node _T_228 = shl(UInt<1>(0h1), 3) node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228) node _T_230 = bits(_T_229, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_230 node _T_231 = eq(UInt<5>(0h16), idx_1) when _T_231 : node _T_232 = shl(UInt<1>(0h1), 3) node _T_233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_232) node _T_234 = bits(_T_233, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_234 node _T_235 = eq(UInt<5>(0h17), idx_1) when _T_235 : node _T_236 = shl(UInt<1>(0h1), 3) node _T_237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_236) node _T_238 = bits(_T_237, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_238 node _T_239 = eq(UInt<5>(0h18), idx_1) when _T_239 : node _T_240 = shl(UInt<1>(0h1), 3) node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240) node _T_242 = bits(_T_241, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_242 node _T_243 = eq(UInt<5>(0h19), idx_1) when _T_243 : node _T_244 = shl(UInt<1>(0h1), 3) node _T_245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_244) node _T_246 = bits(_T_245, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_246 node _T_247 = eq(UInt<5>(0h1a), idx_1) when _T_247 : node _T_248 = shl(UInt<1>(0h1), 3) node _T_249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_248) node _T_250 = bits(_T_249, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_250 node _T_251 = eq(UInt<5>(0h1b), idx_1) when _T_251 : node _T_252 = shl(UInt<1>(0h1), 3) node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252) node _T_254 = bits(_T_253, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_254 node _T_255 = eq(UInt<5>(0h1c), idx_1) when _T_255 : node _T_256 = shl(UInt<1>(0h1), 3) node _T_257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_256) node _T_258 = bits(_T_257, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_258 node _T_259 = eq(UInt<5>(0h1d), idx_1) when _T_259 : node _T_260 = shl(UInt<1>(0h1), 3) node _T_261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_260) node _T_262 = bits(_T_261, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_262 node _T_263 = eq(UInt<5>(0h1e), idx_1) when _T_263 : node _T_264 = shl(UInt<1>(0h1), 3) node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264) node _T_266 = bits(_T_265, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_266 node _T_267 = eq(UInt<5>(0h1f), idx_1) when _T_267 : node _T_268 = shl(UInt<1>(0h1), 3) node _T_269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_268) node _T_270 = bits(_T_269, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_270 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_271 = eq(UInt<1>(0h0), idx_2) when _T_271 : node _T_272 = shl(UInt<2>(0h2), 3) node _T_273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_272) node _T_274 = bits(_T_273, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_274 node _T_275 = eq(UInt<1>(0h1), idx_2) when _T_275 : node _T_276 = shl(UInt<2>(0h2), 3) node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276) node _T_278 = bits(_T_277, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_278 node _T_279 = eq(UInt<2>(0h2), idx_2) when _T_279 : node _T_280 = shl(UInt<2>(0h2), 3) node _T_281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_280) node _T_282 = bits(_T_281, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_282 node _T_283 = eq(UInt<2>(0h3), idx_2) when _T_283 : node _T_284 = shl(UInt<2>(0h2), 3) node _T_285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_284) node _T_286 = bits(_T_285, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_286 node _T_287 = eq(UInt<3>(0h4), idx_2) when _T_287 : node _T_288 = shl(UInt<2>(0h2), 3) node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288) node _T_290 = bits(_T_289, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_290 node _T_291 = eq(UInt<3>(0h5), idx_2) when _T_291 : node _T_292 = shl(UInt<2>(0h2), 3) node _T_293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_292) node _T_294 = bits(_T_293, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_294 node _T_295 = eq(UInt<3>(0h6), idx_2) when _T_295 : node _T_296 = shl(UInt<2>(0h2), 3) node _T_297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_296) node _T_298 = bits(_T_297, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_298 node _T_299 = eq(UInt<3>(0h7), idx_2) when _T_299 : node _T_300 = shl(UInt<2>(0h2), 3) node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300) node _T_302 = bits(_T_301, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_302 node _T_303 = eq(UInt<4>(0h8), idx_2) when _T_303 : node _T_304 = shl(UInt<2>(0h2), 3) node _T_305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_304) node _T_306 = bits(_T_305, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_306 node _T_307 = eq(UInt<4>(0h9), idx_2) when _T_307 : node _T_308 = shl(UInt<2>(0h2), 3) node _T_309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_308) node _T_310 = bits(_T_309, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_310 node _T_311 = eq(UInt<4>(0ha), idx_2) when _T_311 : node _T_312 = shl(UInt<2>(0h2), 3) node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312) node _T_314 = bits(_T_313, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_314 node _T_315 = eq(UInt<4>(0hb), idx_2) when _T_315 : node _T_316 = shl(UInt<2>(0h2), 3) node _T_317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_316) node _T_318 = bits(_T_317, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_318 node _T_319 = eq(UInt<4>(0hc), idx_2) when _T_319 : node _T_320 = shl(UInt<2>(0h2), 3) node _T_321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_320) node _T_322 = bits(_T_321, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_322 node _T_323 = eq(UInt<4>(0hd), idx_2) when _T_323 : node _T_324 = shl(UInt<2>(0h2), 3) node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324) node _T_326 = bits(_T_325, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_326 node _T_327 = eq(UInt<4>(0he), idx_2) when _T_327 : node _T_328 = shl(UInt<2>(0h2), 3) node _T_329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_328) node _T_330 = bits(_T_329, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_330 node _T_331 = eq(UInt<4>(0hf), idx_2) when _T_331 : node _T_332 = shl(UInt<2>(0h2), 3) node _T_333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_332) node _T_334 = bits(_T_333, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_334 node _T_335 = eq(UInt<5>(0h10), idx_2) when _T_335 : node _T_336 = shl(UInt<2>(0h2), 3) node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336) node _T_338 = bits(_T_337, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_338 node _T_339 = eq(UInt<5>(0h11), idx_2) when _T_339 : node _T_340 = shl(UInt<2>(0h2), 3) node _T_341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_340) node _T_342 = bits(_T_341, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_342 node _T_343 = eq(UInt<5>(0h12), idx_2) when _T_343 : node _T_344 = shl(UInt<2>(0h2), 3) node _T_345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_344) node _T_346 = bits(_T_345, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_346 node _T_347 = eq(UInt<5>(0h13), idx_2) when _T_347 : node _T_348 = shl(UInt<2>(0h2), 3) node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348) node _T_350 = bits(_T_349, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_350 node _T_351 = eq(UInt<5>(0h14), idx_2) when _T_351 : node _T_352 = shl(UInt<2>(0h2), 3) node _T_353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_352) node _T_354 = bits(_T_353, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_354 node _T_355 = eq(UInt<5>(0h15), idx_2) when _T_355 : node _T_356 = shl(UInt<2>(0h2), 3) node _T_357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_356) node _T_358 = bits(_T_357, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_358 node _T_359 = eq(UInt<5>(0h16), idx_2) when _T_359 : node _T_360 = shl(UInt<2>(0h2), 3) node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360) node _T_362 = bits(_T_361, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_362 node _T_363 = eq(UInt<5>(0h17), idx_2) when _T_363 : node _T_364 = shl(UInt<2>(0h2), 3) node _T_365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_364) node _T_366 = bits(_T_365, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_366 node _T_367 = eq(UInt<5>(0h18), idx_2) when _T_367 : node _T_368 = shl(UInt<2>(0h2), 3) node _T_369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_368) node _T_370 = bits(_T_369, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_370 node _T_371 = eq(UInt<5>(0h19), idx_2) when _T_371 : node _T_372 = shl(UInt<2>(0h2), 3) node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372) node _T_374 = bits(_T_373, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_374 node _T_375 = eq(UInt<5>(0h1a), idx_2) when _T_375 : node _T_376 = shl(UInt<2>(0h2), 3) node _T_377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_376) node _T_378 = bits(_T_377, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_378 node _T_379 = eq(UInt<5>(0h1b), idx_2) when _T_379 : node _T_380 = shl(UInt<2>(0h2), 3) node _T_381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_380) node _T_382 = bits(_T_381, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_382 node _T_383 = eq(UInt<5>(0h1c), idx_2) when _T_383 : node _T_384 = shl(UInt<2>(0h2), 3) node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384) node _T_386 = bits(_T_385, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_386 node _T_387 = eq(UInt<5>(0h1d), idx_2) when _T_387 : node _T_388 = shl(UInt<2>(0h2), 3) node _T_389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_388) node _T_390 = bits(_T_389, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_390 node _T_391 = eq(UInt<5>(0h1e), idx_2) when _T_391 : node _T_392 = shl(UInt<2>(0h2), 3) node _T_393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_392) node _T_394 = bits(_T_393, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_394 node _T_395 = eq(UInt<5>(0h1f), idx_2) when _T_395 : node _T_396 = shl(UInt<2>(0h2), 3) node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396) node _T_398 = bits(_T_397, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_398 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_399 = eq(UInt<1>(0h0), idx_3) when _T_399 : node _T_400 = shl(UInt<2>(0h3), 3) node _T_401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_400) node _T_402 = bits(_T_401, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_402 node _T_403 = eq(UInt<1>(0h1), idx_3) when _T_403 : node _T_404 = shl(UInt<2>(0h3), 3) node _T_405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_404) node _T_406 = bits(_T_405, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_406 node _T_407 = eq(UInt<2>(0h2), idx_3) when _T_407 : node _T_408 = shl(UInt<2>(0h3), 3) node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408) node _T_410 = bits(_T_409, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_410 node _T_411 = eq(UInt<2>(0h3), idx_3) when _T_411 : node _T_412 = shl(UInt<2>(0h3), 3) node _T_413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_412) node _T_414 = bits(_T_413, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_414 node _T_415 = eq(UInt<3>(0h4), idx_3) when _T_415 : node _T_416 = shl(UInt<2>(0h3), 3) node _T_417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_416) node _T_418 = bits(_T_417, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_418 node _T_419 = eq(UInt<3>(0h5), idx_3) when _T_419 : node _T_420 = shl(UInt<2>(0h3), 3) node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420) node _T_422 = bits(_T_421, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_422 node _T_423 = eq(UInt<3>(0h6), idx_3) when _T_423 : node _T_424 = shl(UInt<2>(0h3), 3) node _T_425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_424) node _T_426 = bits(_T_425, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_426 node _T_427 = eq(UInt<3>(0h7), idx_3) when _T_427 : node _T_428 = shl(UInt<2>(0h3), 3) node _T_429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_428) node _T_430 = bits(_T_429, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_430 node _T_431 = eq(UInt<4>(0h8), idx_3) when _T_431 : node _T_432 = shl(UInt<2>(0h3), 3) node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432) node _T_434 = bits(_T_433, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_434 node _T_435 = eq(UInt<4>(0h9), idx_3) when _T_435 : node _T_436 = shl(UInt<2>(0h3), 3) node _T_437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_436) node _T_438 = bits(_T_437, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_438 node _T_439 = eq(UInt<4>(0ha), idx_3) when _T_439 : node _T_440 = shl(UInt<2>(0h3), 3) node _T_441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_440) node _T_442 = bits(_T_441, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_442 node _T_443 = eq(UInt<4>(0hb), idx_3) when _T_443 : node _T_444 = shl(UInt<2>(0h3), 3) node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444) node _T_446 = bits(_T_445, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_446 node _T_447 = eq(UInt<4>(0hc), idx_3) when _T_447 : node _T_448 = shl(UInt<2>(0h3), 3) node _T_449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_448) node _T_450 = bits(_T_449, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_450 node _T_451 = eq(UInt<4>(0hd), idx_3) when _T_451 : node _T_452 = shl(UInt<2>(0h3), 3) node _T_453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_452) node _T_454 = bits(_T_453, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_454 node _T_455 = eq(UInt<4>(0he), idx_3) when _T_455 : node _T_456 = shl(UInt<2>(0h3), 3) node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456) node _T_458 = bits(_T_457, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_458 node _T_459 = eq(UInt<4>(0hf), idx_3) when _T_459 : node _T_460 = shl(UInt<2>(0h3), 3) node _T_461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_460) node _T_462 = bits(_T_461, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_462 node _T_463 = eq(UInt<5>(0h10), idx_3) when _T_463 : node _T_464 = shl(UInt<2>(0h3), 3) node _T_465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_464) node _T_466 = bits(_T_465, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_466 node _T_467 = eq(UInt<5>(0h11), idx_3) when _T_467 : node _T_468 = shl(UInt<2>(0h3), 3) node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468) node _T_470 = bits(_T_469, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_470 node _T_471 = eq(UInt<5>(0h12), idx_3) when _T_471 : node _T_472 = shl(UInt<2>(0h3), 3) node _T_473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_472) node _T_474 = bits(_T_473, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_474 node _T_475 = eq(UInt<5>(0h13), idx_3) when _T_475 : node _T_476 = shl(UInt<2>(0h3), 3) node _T_477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_476) node _T_478 = bits(_T_477, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_478 node _T_479 = eq(UInt<5>(0h14), idx_3) when _T_479 : node _T_480 = shl(UInt<2>(0h3), 3) node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480) node _T_482 = bits(_T_481, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_482 node _T_483 = eq(UInt<5>(0h15), idx_3) when _T_483 : node _T_484 = shl(UInt<2>(0h3), 3) node _T_485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_484) node _T_486 = bits(_T_485, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_486 node _T_487 = eq(UInt<5>(0h16), idx_3) when _T_487 : node _T_488 = shl(UInt<2>(0h3), 3) node _T_489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_488) node _T_490 = bits(_T_489, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_490 node _T_491 = eq(UInt<5>(0h17), idx_3) when _T_491 : node _T_492 = shl(UInt<2>(0h3), 3) node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492) node _T_494 = bits(_T_493, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_494 node _T_495 = eq(UInt<5>(0h18), idx_3) when _T_495 : node _T_496 = shl(UInt<2>(0h3), 3) node _T_497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_496) node _T_498 = bits(_T_497, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_498 node _T_499 = eq(UInt<5>(0h19), idx_3) when _T_499 : node _T_500 = shl(UInt<2>(0h3), 3) node _T_501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_500) node _T_502 = bits(_T_501, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_502 node _T_503 = eq(UInt<5>(0h1a), idx_3) when _T_503 : node _T_504 = shl(UInt<2>(0h3), 3) node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504) node _T_506 = bits(_T_505, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_506 node _T_507 = eq(UInt<5>(0h1b), idx_3) when _T_507 : node _T_508 = shl(UInt<2>(0h3), 3) node _T_509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_508) node _T_510 = bits(_T_509, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_510 node _T_511 = eq(UInt<5>(0h1c), idx_3) when _T_511 : node _T_512 = shl(UInt<2>(0h3), 3) node _T_513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_512) node _T_514 = bits(_T_513, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_514 node _T_515 = eq(UInt<5>(0h1d), idx_3) when _T_515 : node _T_516 = shl(UInt<2>(0h3), 3) node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516) node _T_518 = bits(_T_517, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_518 node _T_519 = eq(UInt<5>(0h1e), idx_3) when _T_519 : node _T_520 = shl(UInt<2>(0h3), 3) node _T_521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_520) node _T_522 = bits(_T_521, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_522 node _T_523 = eq(UInt<5>(0h1f), idx_3) when _T_523 : node _T_524 = shl(UInt<2>(0h3), 3) node _T_525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_524) node _T_526 = bits(_T_525, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_526 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_527 = eq(UInt<1>(0h0), idx_4) when _T_527 : node _T_528 = shl(UInt<3>(0h4), 3) node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528) node _T_530 = bits(_T_529, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_530 node _T_531 = eq(UInt<1>(0h1), idx_4) when _T_531 : node _T_532 = shl(UInt<3>(0h4), 3) node _T_533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_532) node _T_534 = bits(_T_533, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_534 node _T_535 = eq(UInt<2>(0h2), idx_4) when _T_535 : node _T_536 = shl(UInt<3>(0h4), 3) node _T_537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_536) node _T_538 = bits(_T_537, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_538 node _T_539 = eq(UInt<2>(0h3), idx_4) when _T_539 : node _T_540 = shl(UInt<3>(0h4), 3) node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540) node _T_542 = bits(_T_541, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_542 node _T_543 = eq(UInt<3>(0h4), idx_4) when _T_543 : node _T_544 = shl(UInt<3>(0h4), 3) node _T_545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_544) node _T_546 = bits(_T_545, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_546 node _T_547 = eq(UInt<3>(0h5), idx_4) when _T_547 : node _T_548 = shl(UInt<3>(0h4), 3) node _T_549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_548) node _T_550 = bits(_T_549, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_550 node _T_551 = eq(UInt<3>(0h6), idx_4) when _T_551 : node _T_552 = shl(UInt<3>(0h4), 3) node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552) node _T_554 = bits(_T_553, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_554 node _T_555 = eq(UInt<3>(0h7), idx_4) when _T_555 : node _T_556 = shl(UInt<3>(0h4), 3) node _T_557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_556) node _T_558 = bits(_T_557, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_558 node _T_559 = eq(UInt<4>(0h8), idx_4) when _T_559 : node _T_560 = shl(UInt<3>(0h4), 3) node _T_561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_560) node _T_562 = bits(_T_561, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_562 node _T_563 = eq(UInt<4>(0h9), idx_4) when _T_563 : node _T_564 = shl(UInt<3>(0h4), 3) node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564) node _T_566 = bits(_T_565, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_566 node _T_567 = eq(UInt<4>(0ha), idx_4) when _T_567 : node _T_568 = shl(UInt<3>(0h4), 3) node _T_569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_568) node _T_570 = bits(_T_569, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_570 node _T_571 = eq(UInt<4>(0hb), idx_4) when _T_571 : node _T_572 = shl(UInt<3>(0h4), 3) node _T_573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_572) node _T_574 = bits(_T_573, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_574 node _T_575 = eq(UInt<4>(0hc), idx_4) when _T_575 : node _T_576 = shl(UInt<3>(0h4), 3) node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576) node _T_578 = bits(_T_577, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_578 node _T_579 = eq(UInt<4>(0hd), idx_4) when _T_579 : node _T_580 = shl(UInt<3>(0h4), 3) node _T_581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_580) node _T_582 = bits(_T_581, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_582 node _T_583 = eq(UInt<4>(0he), idx_4) when _T_583 : node _T_584 = shl(UInt<3>(0h4), 3) node _T_585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_584) node _T_586 = bits(_T_585, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_586 node _T_587 = eq(UInt<4>(0hf), idx_4) when _T_587 : node _T_588 = shl(UInt<3>(0h4), 3) node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588) node _T_590 = bits(_T_589, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_590 node _T_591 = eq(UInt<5>(0h10), idx_4) when _T_591 : node _T_592 = shl(UInt<3>(0h4), 3) node _T_593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_592) node _T_594 = bits(_T_593, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_594 node _T_595 = eq(UInt<5>(0h11), idx_4) when _T_595 : node _T_596 = shl(UInt<3>(0h4), 3) node _T_597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_596) node _T_598 = bits(_T_597, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_598 node _T_599 = eq(UInt<5>(0h12), idx_4) when _T_599 : node _T_600 = shl(UInt<3>(0h4), 3) node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600) node _T_602 = bits(_T_601, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_602 node _T_603 = eq(UInt<5>(0h13), idx_4) when _T_603 : node _T_604 = shl(UInt<3>(0h4), 3) node _T_605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_604) node _T_606 = bits(_T_605, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_606 node _T_607 = eq(UInt<5>(0h14), idx_4) when _T_607 : node _T_608 = shl(UInt<3>(0h4), 3) node _T_609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_608) node _T_610 = bits(_T_609, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_610 node _T_611 = eq(UInt<5>(0h15), idx_4) when _T_611 : node _T_612 = shl(UInt<3>(0h4), 3) node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612) node _T_614 = bits(_T_613, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_614 node _T_615 = eq(UInt<5>(0h16), idx_4) when _T_615 : node _T_616 = shl(UInt<3>(0h4), 3) node _T_617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_616) node _T_618 = bits(_T_617, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_618 node _T_619 = eq(UInt<5>(0h17), idx_4) when _T_619 : node _T_620 = shl(UInt<3>(0h4), 3) node _T_621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_620) node _T_622 = bits(_T_621, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_622 node _T_623 = eq(UInt<5>(0h18), idx_4) when _T_623 : node _T_624 = shl(UInt<3>(0h4), 3) node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624) node _T_626 = bits(_T_625, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_626 node _T_627 = eq(UInt<5>(0h19), idx_4) when _T_627 : node _T_628 = shl(UInt<3>(0h4), 3) node _T_629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_628) node _T_630 = bits(_T_629, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_630 node _T_631 = eq(UInt<5>(0h1a), idx_4) when _T_631 : node _T_632 = shl(UInt<3>(0h4), 3) node _T_633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_632) node _T_634 = bits(_T_633, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_634 node _T_635 = eq(UInt<5>(0h1b), idx_4) when _T_635 : node _T_636 = shl(UInt<3>(0h4), 3) node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636) node _T_638 = bits(_T_637, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_638 node _T_639 = eq(UInt<5>(0h1c), idx_4) when _T_639 : node _T_640 = shl(UInt<3>(0h4), 3) node _T_641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_640) node _T_642 = bits(_T_641, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_642 node _T_643 = eq(UInt<5>(0h1d), idx_4) when _T_643 : node _T_644 = shl(UInt<3>(0h4), 3) node _T_645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_644) node _T_646 = bits(_T_645, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_646 node _T_647 = eq(UInt<5>(0h1e), idx_4) when _T_647 : node _T_648 = shl(UInt<3>(0h4), 3) node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648) node _T_650 = bits(_T_649, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_650 node _T_651 = eq(UInt<5>(0h1f), idx_4) when _T_651 : node _T_652 = shl(UInt<3>(0h4), 3) node _T_653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_652) node _T_654 = bits(_T_653, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_654 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_655 = eq(UInt<1>(0h0), idx_5) when _T_655 : node _T_656 = shl(UInt<3>(0h5), 3) node _T_657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_656) node _T_658 = bits(_T_657, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_658 node _T_659 = eq(UInt<1>(0h1), idx_5) when _T_659 : node _T_660 = shl(UInt<3>(0h5), 3) node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660) node _T_662 = bits(_T_661, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_662 node _T_663 = eq(UInt<2>(0h2), idx_5) when _T_663 : node _T_664 = shl(UInt<3>(0h5), 3) node _T_665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_664) node _T_666 = bits(_T_665, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_666 node _T_667 = eq(UInt<2>(0h3), idx_5) when _T_667 : node _T_668 = shl(UInt<3>(0h5), 3) node _T_669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_668) node _T_670 = bits(_T_669, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_670 node _T_671 = eq(UInt<3>(0h4), idx_5) when _T_671 : node _T_672 = shl(UInt<3>(0h5), 3) node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672) node _T_674 = bits(_T_673, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_674 node _T_675 = eq(UInt<3>(0h5), idx_5) when _T_675 : node _T_676 = shl(UInt<3>(0h5), 3) node _T_677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_676) node _T_678 = bits(_T_677, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_678 node _T_679 = eq(UInt<3>(0h6), idx_5) when _T_679 : node _T_680 = shl(UInt<3>(0h5), 3) node _T_681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_680) node _T_682 = bits(_T_681, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_682 node _T_683 = eq(UInt<3>(0h7), idx_5) when _T_683 : node _T_684 = shl(UInt<3>(0h5), 3) node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684) node _T_686 = bits(_T_685, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_686 node _T_687 = eq(UInt<4>(0h8), idx_5) when _T_687 : node _T_688 = shl(UInt<3>(0h5), 3) node _T_689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_688) node _T_690 = bits(_T_689, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_690 node _T_691 = eq(UInt<4>(0h9), idx_5) when _T_691 : node _T_692 = shl(UInt<3>(0h5), 3) node _T_693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_692) node _T_694 = bits(_T_693, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_694 node _T_695 = eq(UInt<4>(0ha), idx_5) when _T_695 : node _T_696 = shl(UInt<3>(0h5), 3) node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696) node _T_698 = bits(_T_697, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_698 node _T_699 = eq(UInt<4>(0hb), idx_5) when _T_699 : node _T_700 = shl(UInt<3>(0h5), 3) node _T_701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_700) node _T_702 = bits(_T_701, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_702 node _T_703 = eq(UInt<4>(0hc), idx_5) when _T_703 : node _T_704 = shl(UInt<3>(0h5), 3) node _T_705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_704) node _T_706 = bits(_T_705, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_706 node _T_707 = eq(UInt<4>(0hd), idx_5) when _T_707 : node _T_708 = shl(UInt<3>(0h5), 3) node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708) node _T_710 = bits(_T_709, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_710 node _T_711 = eq(UInt<4>(0he), idx_5) when _T_711 : node _T_712 = shl(UInt<3>(0h5), 3) node _T_713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_712) node _T_714 = bits(_T_713, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_714 node _T_715 = eq(UInt<4>(0hf), idx_5) when _T_715 : node _T_716 = shl(UInt<3>(0h5), 3) node _T_717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_716) node _T_718 = bits(_T_717, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_718 node _T_719 = eq(UInt<5>(0h10), idx_5) when _T_719 : node _T_720 = shl(UInt<3>(0h5), 3) node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720) node _T_722 = bits(_T_721, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_722 node _T_723 = eq(UInt<5>(0h11), idx_5) when _T_723 : node _T_724 = shl(UInt<3>(0h5), 3) node _T_725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_724) node _T_726 = bits(_T_725, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_726 node _T_727 = eq(UInt<5>(0h12), idx_5) when _T_727 : node _T_728 = shl(UInt<3>(0h5), 3) node _T_729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_728) node _T_730 = bits(_T_729, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_730 node _T_731 = eq(UInt<5>(0h13), idx_5) when _T_731 : node _T_732 = shl(UInt<3>(0h5), 3) node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732) node _T_734 = bits(_T_733, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_734 node _T_735 = eq(UInt<5>(0h14), idx_5) when _T_735 : node _T_736 = shl(UInt<3>(0h5), 3) node _T_737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_736) node _T_738 = bits(_T_737, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_738 node _T_739 = eq(UInt<5>(0h15), idx_5) when _T_739 : node _T_740 = shl(UInt<3>(0h5), 3) node _T_741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_740) node _T_742 = bits(_T_741, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_742 node _T_743 = eq(UInt<5>(0h16), idx_5) when _T_743 : node _T_744 = shl(UInt<3>(0h5), 3) node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744) node _T_746 = bits(_T_745, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_746 node _T_747 = eq(UInt<5>(0h17), idx_5) when _T_747 : node _T_748 = shl(UInt<3>(0h5), 3) node _T_749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_748) node _T_750 = bits(_T_749, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_750 node _T_751 = eq(UInt<5>(0h18), idx_5) when _T_751 : node _T_752 = shl(UInt<3>(0h5), 3) node _T_753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_752) node _T_754 = bits(_T_753, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_754 node _T_755 = eq(UInt<5>(0h19), idx_5) when _T_755 : node _T_756 = shl(UInt<3>(0h5), 3) node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756) node _T_758 = bits(_T_757, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_758 node _T_759 = eq(UInt<5>(0h1a), idx_5) when _T_759 : node _T_760 = shl(UInt<3>(0h5), 3) node _T_761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_760) node _T_762 = bits(_T_761, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_762 node _T_763 = eq(UInt<5>(0h1b), idx_5) when _T_763 : node _T_764 = shl(UInt<3>(0h5), 3) node _T_765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_764) node _T_766 = bits(_T_765, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_766 node _T_767 = eq(UInt<5>(0h1c), idx_5) when _T_767 : node _T_768 = shl(UInt<3>(0h5), 3) node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768) node _T_770 = bits(_T_769, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_770 node _T_771 = eq(UInt<5>(0h1d), idx_5) when _T_771 : node _T_772 = shl(UInt<3>(0h5), 3) node _T_773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_772) node _T_774 = bits(_T_773, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_774 node _T_775 = eq(UInt<5>(0h1e), idx_5) when _T_775 : node _T_776 = shl(UInt<3>(0h5), 3) node _T_777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_776) node _T_778 = bits(_T_777, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_778 node _T_779 = eq(UInt<5>(0h1f), idx_5) when _T_779 : node _T_780 = shl(UInt<3>(0h5), 3) node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780) node _T_782 = bits(_T_781, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_782 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_783 = eq(UInt<1>(0h0), idx_6) when _T_783 : node _T_784 = shl(UInt<3>(0h6), 3) node _T_785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_784) node _T_786 = bits(_T_785, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_786 node _T_787 = eq(UInt<1>(0h1), idx_6) when _T_787 : node _T_788 = shl(UInt<3>(0h6), 3) node _T_789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_788) node _T_790 = bits(_T_789, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_790 node _T_791 = eq(UInt<2>(0h2), idx_6) when _T_791 : node _T_792 = shl(UInt<3>(0h6), 3) node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792) node _T_794 = bits(_T_793, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_794 node _T_795 = eq(UInt<2>(0h3), idx_6) when _T_795 : node _T_796 = shl(UInt<3>(0h6), 3) node _T_797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_796) node _T_798 = bits(_T_797, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_798 node _T_799 = eq(UInt<3>(0h4), idx_6) when _T_799 : node _T_800 = shl(UInt<3>(0h6), 3) node _T_801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_800) node _T_802 = bits(_T_801, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_802 node _T_803 = eq(UInt<3>(0h5), idx_6) when _T_803 : node _T_804 = shl(UInt<3>(0h6), 3) node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804) node _T_806 = bits(_T_805, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_806 node _T_807 = eq(UInt<3>(0h6), idx_6) when _T_807 : node _T_808 = shl(UInt<3>(0h6), 3) node _T_809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_808) node _T_810 = bits(_T_809, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_810 node _T_811 = eq(UInt<3>(0h7), idx_6) when _T_811 : node _T_812 = shl(UInt<3>(0h6), 3) node _T_813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_812) node _T_814 = bits(_T_813, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_814 node _T_815 = eq(UInt<4>(0h8), idx_6) when _T_815 : node _T_816 = shl(UInt<3>(0h6), 3) node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816) node _T_818 = bits(_T_817, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_818 node _T_819 = eq(UInt<4>(0h9), idx_6) when _T_819 : node _T_820 = shl(UInt<3>(0h6), 3) node _T_821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_820) node _T_822 = bits(_T_821, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_822 node _T_823 = eq(UInt<4>(0ha), idx_6) when _T_823 : node _T_824 = shl(UInt<3>(0h6), 3) node _T_825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_824) node _T_826 = bits(_T_825, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_826 node _T_827 = eq(UInt<4>(0hb), idx_6) when _T_827 : node _T_828 = shl(UInt<3>(0h6), 3) node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828) node _T_830 = bits(_T_829, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_830 node _T_831 = eq(UInt<4>(0hc), idx_6) when _T_831 : node _T_832 = shl(UInt<3>(0h6), 3) node _T_833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_832) node _T_834 = bits(_T_833, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_834 node _T_835 = eq(UInt<4>(0hd), idx_6) when _T_835 : node _T_836 = shl(UInt<3>(0h6), 3) node _T_837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_836) node _T_838 = bits(_T_837, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_838 node _T_839 = eq(UInt<4>(0he), idx_6) when _T_839 : node _T_840 = shl(UInt<3>(0h6), 3) node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840) node _T_842 = bits(_T_841, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_842 node _T_843 = eq(UInt<4>(0hf), idx_6) when _T_843 : node _T_844 = shl(UInt<3>(0h6), 3) node _T_845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_844) node _T_846 = bits(_T_845, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_846 node _T_847 = eq(UInt<5>(0h10), idx_6) when _T_847 : node _T_848 = shl(UInt<3>(0h6), 3) node _T_849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_848) node _T_850 = bits(_T_849, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_850 node _T_851 = eq(UInt<5>(0h11), idx_6) when _T_851 : node _T_852 = shl(UInt<3>(0h6), 3) node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852) node _T_854 = bits(_T_853, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_854 node _T_855 = eq(UInt<5>(0h12), idx_6) when _T_855 : node _T_856 = shl(UInt<3>(0h6), 3) node _T_857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_856) node _T_858 = bits(_T_857, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_858 node _T_859 = eq(UInt<5>(0h13), idx_6) when _T_859 : node _T_860 = shl(UInt<3>(0h6), 3) node _T_861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_860) node _T_862 = bits(_T_861, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_862 node _T_863 = eq(UInt<5>(0h14), idx_6) when _T_863 : node _T_864 = shl(UInt<3>(0h6), 3) node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864) node _T_866 = bits(_T_865, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_866 node _T_867 = eq(UInt<5>(0h15), idx_6) when _T_867 : node _T_868 = shl(UInt<3>(0h6), 3) node _T_869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_868) node _T_870 = bits(_T_869, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_870 node _T_871 = eq(UInt<5>(0h16), idx_6) when _T_871 : node _T_872 = shl(UInt<3>(0h6), 3) node _T_873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_872) node _T_874 = bits(_T_873, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_874 node _T_875 = eq(UInt<5>(0h17), idx_6) when _T_875 : node _T_876 = shl(UInt<3>(0h6), 3) node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876) node _T_878 = bits(_T_877, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_878 node _T_879 = eq(UInt<5>(0h18), idx_6) when _T_879 : node _T_880 = shl(UInt<3>(0h6), 3) node _T_881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_880) node _T_882 = bits(_T_881, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_882 node _T_883 = eq(UInt<5>(0h19), idx_6) when _T_883 : node _T_884 = shl(UInt<3>(0h6), 3) node _T_885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_884) node _T_886 = bits(_T_885, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_886 node _T_887 = eq(UInt<5>(0h1a), idx_6) when _T_887 : node _T_888 = shl(UInt<3>(0h6), 3) node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888) node _T_890 = bits(_T_889, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_890 node _T_891 = eq(UInt<5>(0h1b), idx_6) when _T_891 : node _T_892 = shl(UInt<3>(0h6), 3) node _T_893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_892) node _T_894 = bits(_T_893, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_894 node _T_895 = eq(UInt<5>(0h1c), idx_6) when _T_895 : node _T_896 = shl(UInt<3>(0h6), 3) node _T_897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_896) node _T_898 = bits(_T_897, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_898 node _T_899 = eq(UInt<5>(0h1d), idx_6) when _T_899 : node _T_900 = shl(UInt<3>(0h6), 3) node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900) node _T_902 = bits(_T_901, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_902 node _T_903 = eq(UInt<5>(0h1e), idx_6) when _T_903 : node _T_904 = shl(UInt<3>(0h6), 3) node _T_905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_904) node _T_906 = bits(_T_905, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_906 node _T_907 = eq(UInt<5>(0h1f), idx_6) when _T_907 : node _T_908 = shl(UInt<3>(0h6), 3) node _T_909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_908) node _T_910 = bits(_T_909, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_910 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_911 = eq(UInt<1>(0h0), idx_7) when _T_911 : node _T_912 = shl(UInt<3>(0h7), 3) node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912) node _T_914 = bits(_T_913, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_914 node _T_915 = eq(UInt<1>(0h1), idx_7) when _T_915 : node _T_916 = shl(UInt<3>(0h7), 3) node _T_917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_916) node _T_918 = bits(_T_917, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_918 node _T_919 = eq(UInt<2>(0h2), idx_7) when _T_919 : node _T_920 = shl(UInt<3>(0h7), 3) node _T_921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_920) node _T_922 = bits(_T_921, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_922 node _T_923 = eq(UInt<2>(0h3), idx_7) when _T_923 : node _T_924 = shl(UInt<3>(0h7), 3) node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924) node _T_926 = bits(_T_925, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_926 node _T_927 = eq(UInt<3>(0h4), idx_7) when _T_927 : node _T_928 = shl(UInt<3>(0h7), 3) node _T_929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_928) node _T_930 = bits(_T_929, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_930 node _T_931 = eq(UInt<3>(0h5), idx_7) when _T_931 : node _T_932 = shl(UInt<3>(0h7), 3) node _T_933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_932) node _T_934 = bits(_T_933, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_934 node _T_935 = eq(UInt<3>(0h6), idx_7) when _T_935 : node _T_936 = shl(UInt<3>(0h7), 3) node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936) node _T_938 = bits(_T_937, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_938 node _T_939 = eq(UInt<3>(0h7), idx_7) when _T_939 : node _T_940 = shl(UInt<3>(0h7), 3) node _T_941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_940) node _T_942 = bits(_T_941, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_942 node _T_943 = eq(UInt<4>(0h8), idx_7) when _T_943 : node _T_944 = shl(UInt<3>(0h7), 3) node _T_945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_944) node _T_946 = bits(_T_945, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_946 node _T_947 = eq(UInt<4>(0h9), idx_7) when _T_947 : node _T_948 = shl(UInt<3>(0h7), 3) node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948) node _T_950 = bits(_T_949, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_950 node _T_951 = eq(UInt<4>(0ha), idx_7) when _T_951 : node _T_952 = shl(UInt<3>(0h7), 3) node _T_953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_952) node _T_954 = bits(_T_953, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_954 node _T_955 = eq(UInt<4>(0hb), idx_7) when _T_955 : node _T_956 = shl(UInt<3>(0h7), 3) node _T_957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_956) node _T_958 = bits(_T_957, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_958 node _T_959 = eq(UInt<4>(0hc), idx_7) when _T_959 : node _T_960 = shl(UInt<3>(0h7), 3) node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960) node _T_962 = bits(_T_961, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_962 node _T_963 = eq(UInt<4>(0hd), idx_7) when _T_963 : node _T_964 = shl(UInt<3>(0h7), 3) node _T_965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_964) node _T_966 = bits(_T_965, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_966 node _T_967 = eq(UInt<4>(0he), idx_7) when _T_967 : node _T_968 = shl(UInt<3>(0h7), 3) node _T_969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_968) node _T_970 = bits(_T_969, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_970 node _T_971 = eq(UInt<4>(0hf), idx_7) when _T_971 : node _T_972 = shl(UInt<3>(0h7), 3) node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972) node _T_974 = bits(_T_973, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_974 node _T_975 = eq(UInt<5>(0h10), idx_7) when _T_975 : node _T_976 = shl(UInt<3>(0h7), 3) node _T_977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_976) node _T_978 = bits(_T_977, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_978 node _T_979 = eq(UInt<5>(0h11), idx_7) when _T_979 : node _T_980 = shl(UInt<3>(0h7), 3) node _T_981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_980) node _T_982 = bits(_T_981, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_982 node _T_983 = eq(UInt<5>(0h12), idx_7) when _T_983 : node _T_984 = shl(UInt<3>(0h7), 3) node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984) node _T_986 = bits(_T_985, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_986 node _T_987 = eq(UInt<5>(0h13), idx_7) when _T_987 : node _T_988 = shl(UInt<3>(0h7), 3) node _T_989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_988) node _T_990 = bits(_T_989, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_990 node _T_991 = eq(UInt<5>(0h14), idx_7) when _T_991 : node _T_992 = shl(UInt<3>(0h7), 3) node _T_993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_992) node _T_994 = bits(_T_993, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_994 node _T_995 = eq(UInt<5>(0h15), idx_7) when _T_995 : node _T_996 = shl(UInt<3>(0h7), 3) node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996) node _T_998 = bits(_T_997, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_998 node _T_999 = eq(UInt<5>(0h16), idx_7) when _T_999 : node _T_1000 = shl(UInt<3>(0h7), 3) node _T_1001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1000) node _T_1002 = bits(_T_1001, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1002 node _T_1003 = eq(UInt<5>(0h17), idx_7) when _T_1003 : node _T_1004 = shl(UInt<3>(0h7), 3) node _T_1005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1004) node _T_1006 = bits(_T_1005, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1006 node _T_1007 = eq(UInt<5>(0h18), idx_7) when _T_1007 : node _T_1008 = shl(UInt<3>(0h7), 3) node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008) node _T_1010 = bits(_T_1009, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1010 node _T_1011 = eq(UInt<5>(0h19), idx_7) when _T_1011 : node _T_1012 = shl(UInt<3>(0h7), 3) node _T_1013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1012) node _T_1014 = bits(_T_1013, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1014 node _T_1015 = eq(UInt<5>(0h1a), idx_7) when _T_1015 : node _T_1016 = shl(UInt<3>(0h7), 3) node _T_1017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1016) node _T_1018 = bits(_T_1017, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1018 node _T_1019 = eq(UInt<5>(0h1b), idx_7) when _T_1019 : node _T_1020 = shl(UInt<3>(0h7), 3) node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020) node _T_1022 = bits(_T_1021, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1022 node _T_1023 = eq(UInt<5>(0h1c), idx_7) when _T_1023 : node _T_1024 = shl(UInt<3>(0h7), 3) node _T_1025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1024) node _T_1026 = bits(_T_1025, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1026 node _T_1027 = eq(UInt<5>(0h1d), idx_7) when _T_1027 : node _T_1028 = shl(UInt<3>(0h7), 3) node _T_1029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1028) node _T_1030 = bits(_T_1029, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1030 node _T_1031 = eq(UInt<5>(0h1e), idx_7) when _T_1031 : node _T_1032 = shl(UInt<3>(0h7), 3) node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032) node _T_1034 = bits(_T_1033, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1034 node _T_1035 = eq(UInt<5>(0h1f), idx_7) when _T_1035 : node _T_1036 = shl(UInt<3>(0h7), 3) node _T_1037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1036) node _T_1038 = bits(_T_1037, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1038 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_1039 = eq(UInt<1>(0h0), idx_8) when _T_1039 : node _T_1040 = shl(UInt<4>(0h8), 3) node _T_1041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1040) node _T_1042 = bits(_T_1041, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1042 node _T_1043 = eq(UInt<1>(0h1), idx_8) when _T_1043 : node _T_1044 = shl(UInt<4>(0h8), 3) node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044) node _T_1046 = bits(_T_1045, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1046 node _T_1047 = eq(UInt<2>(0h2), idx_8) when _T_1047 : node _T_1048 = shl(UInt<4>(0h8), 3) node _T_1049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1048) node _T_1050 = bits(_T_1049, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1050 node _T_1051 = eq(UInt<2>(0h3), idx_8) when _T_1051 : node _T_1052 = shl(UInt<4>(0h8), 3) node _T_1053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1052) node _T_1054 = bits(_T_1053, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1054 node _T_1055 = eq(UInt<3>(0h4), idx_8) when _T_1055 : node _T_1056 = shl(UInt<4>(0h8), 3) node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056) node _T_1058 = bits(_T_1057, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1058 node _T_1059 = eq(UInt<3>(0h5), idx_8) when _T_1059 : node _T_1060 = shl(UInt<4>(0h8), 3) node _T_1061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1060) node _T_1062 = bits(_T_1061, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1062 node _T_1063 = eq(UInt<3>(0h6), idx_8) when _T_1063 : node _T_1064 = shl(UInt<4>(0h8), 3) node _T_1065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1064) node _T_1066 = bits(_T_1065, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1066 node _T_1067 = eq(UInt<3>(0h7), idx_8) when _T_1067 : node _T_1068 = shl(UInt<4>(0h8), 3) node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068) node _T_1070 = bits(_T_1069, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1070 node _T_1071 = eq(UInt<4>(0h8), idx_8) when _T_1071 : node _T_1072 = shl(UInt<4>(0h8), 3) node _T_1073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1072) node _T_1074 = bits(_T_1073, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1074 node _T_1075 = eq(UInt<4>(0h9), idx_8) when _T_1075 : node _T_1076 = shl(UInt<4>(0h8), 3) node _T_1077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1076) node _T_1078 = bits(_T_1077, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1078 node _T_1079 = eq(UInt<4>(0ha), idx_8) when _T_1079 : node _T_1080 = shl(UInt<4>(0h8), 3) node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080) node _T_1082 = bits(_T_1081, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1082 node _T_1083 = eq(UInt<4>(0hb), idx_8) when _T_1083 : node _T_1084 = shl(UInt<4>(0h8), 3) node _T_1085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1084) node _T_1086 = bits(_T_1085, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1086 node _T_1087 = eq(UInt<4>(0hc), idx_8) when _T_1087 : node _T_1088 = shl(UInt<4>(0h8), 3) node _T_1089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1088) node _T_1090 = bits(_T_1089, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1090 node _T_1091 = eq(UInt<4>(0hd), idx_8) when _T_1091 : node _T_1092 = shl(UInt<4>(0h8), 3) node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092) node _T_1094 = bits(_T_1093, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1094 node _T_1095 = eq(UInt<4>(0he), idx_8) when _T_1095 : node _T_1096 = shl(UInt<4>(0h8), 3) node _T_1097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1096) node _T_1098 = bits(_T_1097, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1098 node _T_1099 = eq(UInt<4>(0hf), idx_8) when _T_1099 : node _T_1100 = shl(UInt<4>(0h8), 3) node _T_1101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1100) node _T_1102 = bits(_T_1101, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1102 node _T_1103 = eq(UInt<5>(0h10), idx_8) when _T_1103 : node _T_1104 = shl(UInt<4>(0h8), 3) node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104) node _T_1106 = bits(_T_1105, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1106 node _T_1107 = eq(UInt<5>(0h11), idx_8) when _T_1107 : node _T_1108 = shl(UInt<4>(0h8), 3) node _T_1109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1108) node _T_1110 = bits(_T_1109, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1110 node _T_1111 = eq(UInt<5>(0h12), idx_8) when _T_1111 : node _T_1112 = shl(UInt<4>(0h8), 3) node _T_1113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1112) node _T_1114 = bits(_T_1113, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1114 node _T_1115 = eq(UInt<5>(0h13), idx_8) when _T_1115 : node _T_1116 = shl(UInt<4>(0h8), 3) node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116) node _T_1118 = bits(_T_1117, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1118 node _T_1119 = eq(UInt<5>(0h14), idx_8) when _T_1119 : node _T_1120 = shl(UInt<4>(0h8), 3) node _T_1121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1120) node _T_1122 = bits(_T_1121, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1122 node _T_1123 = eq(UInt<5>(0h15), idx_8) when _T_1123 : node _T_1124 = shl(UInt<4>(0h8), 3) node _T_1125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1124) node _T_1126 = bits(_T_1125, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1126 node _T_1127 = eq(UInt<5>(0h16), idx_8) when _T_1127 : node _T_1128 = shl(UInt<4>(0h8), 3) node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128) node _T_1130 = bits(_T_1129, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1130 node _T_1131 = eq(UInt<5>(0h17), idx_8) when _T_1131 : node _T_1132 = shl(UInt<4>(0h8), 3) node _T_1133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1132) node _T_1134 = bits(_T_1133, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1134 node _T_1135 = eq(UInt<5>(0h18), idx_8) when _T_1135 : node _T_1136 = shl(UInt<4>(0h8), 3) node _T_1137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1136) node _T_1138 = bits(_T_1137, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1138 node _T_1139 = eq(UInt<5>(0h19), idx_8) when _T_1139 : node _T_1140 = shl(UInt<4>(0h8), 3) node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140) node _T_1142 = bits(_T_1141, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1142 node _T_1143 = eq(UInt<5>(0h1a), idx_8) when _T_1143 : node _T_1144 = shl(UInt<4>(0h8), 3) node _T_1145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1144) node _T_1146 = bits(_T_1145, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1146 node _T_1147 = eq(UInt<5>(0h1b), idx_8) when _T_1147 : node _T_1148 = shl(UInt<4>(0h8), 3) node _T_1149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1148) node _T_1150 = bits(_T_1149, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1150 node _T_1151 = eq(UInt<5>(0h1c), idx_8) when _T_1151 : node _T_1152 = shl(UInt<4>(0h8), 3) node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152) node _T_1154 = bits(_T_1153, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1154 node _T_1155 = eq(UInt<5>(0h1d), idx_8) when _T_1155 : node _T_1156 = shl(UInt<4>(0h8), 3) node _T_1157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1156) node _T_1158 = bits(_T_1157, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1158 node _T_1159 = eq(UInt<5>(0h1e), idx_8) when _T_1159 : node _T_1160 = shl(UInt<4>(0h8), 3) node _T_1161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1160) node _T_1162 = bits(_T_1161, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1162 node _T_1163 = eq(UInt<5>(0h1f), idx_8) when _T_1163 : node _T_1164 = shl(UInt<4>(0h8), 3) node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164) node _T_1166 = bits(_T_1165, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1166 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_1167 = eq(UInt<1>(0h0), idx_9) when _T_1167 : node _T_1168 = shl(UInt<4>(0h9), 3) node _T_1169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1168) node _T_1170 = bits(_T_1169, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1170 node _T_1171 = eq(UInt<1>(0h1), idx_9) when _T_1171 : node _T_1172 = shl(UInt<4>(0h9), 3) node _T_1173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1172) node _T_1174 = bits(_T_1173, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1174 node _T_1175 = eq(UInt<2>(0h2), idx_9) when _T_1175 : node _T_1176 = shl(UInt<4>(0h9), 3) node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176) node _T_1178 = bits(_T_1177, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1178 node _T_1179 = eq(UInt<2>(0h3), idx_9) when _T_1179 : node _T_1180 = shl(UInt<4>(0h9), 3) node _T_1181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1180) node _T_1182 = bits(_T_1181, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1182 node _T_1183 = eq(UInt<3>(0h4), idx_9) when _T_1183 : node _T_1184 = shl(UInt<4>(0h9), 3) node _T_1185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1184) node _T_1186 = bits(_T_1185, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1186 node _T_1187 = eq(UInt<3>(0h5), idx_9) when _T_1187 : node _T_1188 = shl(UInt<4>(0h9), 3) node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188) node _T_1190 = bits(_T_1189, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1190 node _T_1191 = eq(UInt<3>(0h6), idx_9) when _T_1191 : node _T_1192 = shl(UInt<4>(0h9), 3) node _T_1193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1192) node _T_1194 = bits(_T_1193, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1194 node _T_1195 = eq(UInt<3>(0h7), idx_9) when _T_1195 : node _T_1196 = shl(UInt<4>(0h9), 3) node _T_1197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1196) node _T_1198 = bits(_T_1197, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1198 node _T_1199 = eq(UInt<4>(0h8), idx_9) when _T_1199 : node _T_1200 = shl(UInt<4>(0h9), 3) node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200) node _T_1202 = bits(_T_1201, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1202 node _T_1203 = eq(UInt<4>(0h9), idx_9) when _T_1203 : node _T_1204 = shl(UInt<4>(0h9), 3) node _T_1205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1204) node _T_1206 = bits(_T_1205, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1206 node _T_1207 = eq(UInt<4>(0ha), idx_9) when _T_1207 : node _T_1208 = shl(UInt<4>(0h9), 3) node _T_1209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1208) node _T_1210 = bits(_T_1209, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1210 node _T_1211 = eq(UInt<4>(0hb), idx_9) when _T_1211 : node _T_1212 = shl(UInt<4>(0h9), 3) node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212) node _T_1214 = bits(_T_1213, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1214 node _T_1215 = eq(UInt<4>(0hc), idx_9) when _T_1215 : node _T_1216 = shl(UInt<4>(0h9), 3) node _T_1217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1216) node _T_1218 = bits(_T_1217, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1218 node _T_1219 = eq(UInt<4>(0hd), idx_9) when _T_1219 : node _T_1220 = shl(UInt<4>(0h9), 3) node _T_1221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1220) node _T_1222 = bits(_T_1221, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1222 node _T_1223 = eq(UInt<4>(0he), idx_9) when _T_1223 : node _T_1224 = shl(UInt<4>(0h9), 3) node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224) node _T_1226 = bits(_T_1225, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1226 node _T_1227 = eq(UInt<4>(0hf), idx_9) when _T_1227 : node _T_1228 = shl(UInt<4>(0h9), 3) node _T_1229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1228) node _T_1230 = bits(_T_1229, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1230 node _T_1231 = eq(UInt<5>(0h10), idx_9) when _T_1231 : node _T_1232 = shl(UInt<4>(0h9), 3) node _T_1233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1232) node _T_1234 = bits(_T_1233, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1234 node _T_1235 = eq(UInt<5>(0h11), idx_9) when _T_1235 : node _T_1236 = shl(UInt<4>(0h9), 3) node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236) node _T_1238 = bits(_T_1237, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1238 node _T_1239 = eq(UInt<5>(0h12), idx_9) when _T_1239 : node _T_1240 = shl(UInt<4>(0h9), 3) node _T_1241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1240) node _T_1242 = bits(_T_1241, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1242 node _T_1243 = eq(UInt<5>(0h13), idx_9) when _T_1243 : node _T_1244 = shl(UInt<4>(0h9), 3) node _T_1245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1244) node _T_1246 = bits(_T_1245, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1246 node _T_1247 = eq(UInt<5>(0h14), idx_9) when _T_1247 : node _T_1248 = shl(UInt<4>(0h9), 3) node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248) node _T_1250 = bits(_T_1249, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1250 node _T_1251 = eq(UInt<5>(0h15), idx_9) when _T_1251 : node _T_1252 = shl(UInt<4>(0h9), 3) node _T_1253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1252) node _T_1254 = bits(_T_1253, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1254 node _T_1255 = eq(UInt<5>(0h16), idx_9) when _T_1255 : node _T_1256 = shl(UInt<4>(0h9), 3) node _T_1257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1256) node _T_1258 = bits(_T_1257, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1258 node _T_1259 = eq(UInt<5>(0h17), idx_9) when _T_1259 : node _T_1260 = shl(UInt<4>(0h9), 3) node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260) node _T_1262 = bits(_T_1261, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1262 node _T_1263 = eq(UInt<5>(0h18), idx_9) when _T_1263 : node _T_1264 = shl(UInt<4>(0h9), 3) node _T_1265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1264) node _T_1266 = bits(_T_1265, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1266 node _T_1267 = eq(UInt<5>(0h19), idx_9) when _T_1267 : node _T_1268 = shl(UInt<4>(0h9), 3) node _T_1269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1268) node _T_1270 = bits(_T_1269, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1270 node _T_1271 = eq(UInt<5>(0h1a), idx_9) when _T_1271 : node _T_1272 = shl(UInt<4>(0h9), 3) node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272) node _T_1274 = bits(_T_1273, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1274 node _T_1275 = eq(UInt<5>(0h1b), idx_9) when _T_1275 : node _T_1276 = shl(UInt<4>(0h9), 3) node _T_1277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1276) node _T_1278 = bits(_T_1277, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1278 node _T_1279 = eq(UInt<5>(0h1c), idx_9) when _T_1279 : node _T_1280 = shl(UInt<4>(0h9), 3) node _T_1281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1280) node _T_1282 = bits(_T_1281, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1282 node _T_1283 = eq(UInt<5>(0h1d), idx_9) when _T_1283 : node _T_1284 = shl(UInt<4>(0h9), 3) node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284) node _T_1286 = bits(_T_1285, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1286 node _T_1287 = eq(UInt<5>(0h1e), idx_9) when _T_1287 : node _T_1288 = shl(UInt<4>(0h9), 3) node _T_1289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1288) node _T_1290 = bits(_T_1289, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1290 node _T_1291 = eq(UInt<5>(0h1f), idx_9) when _T_1291 : node _T_1292 = shl(UInt<4>(0h9), 3) node _T_1293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1292) node _T_1294 = bits(_T_1293, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1294 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_1295 = eq(UInt<1>(0h0), idx_10) when _T_1295 : node _T_1296 = shl(UInt<4>(0ha), 3) node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296) node _T_1298 = bits(_T_1297, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1298 node _T_1299 = eq(UInt<1>(0h1), idx_10) when _T_1299 : node _T_1300 = shl(UInt<4>(0ha), 3) node _T_1301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1300) node _T_1302 = bits(_T_1301, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1302 node _T_1303 = eq(UInt<2>(0h2), idx_10) when _T_1303 : node _T_1304 = shl(UInt<4>(0ha), 3) node _T_1305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1304) node _T_1306 = bits(_T_1305, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1306 node _T_1307 = eq(UInt<2>(0h3), idx_10) when _T_1307 : node _T_1308 = shl(UInt<4>(0ha), 3) node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308) node _T_1310 = bits(_T_1309, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1310 node _T_1311 = eq(UInt<3>(0h4), idx_10) when _T_1311 : node _T_1312 = shl(UInt<4>(0ha), 3) node _T_1313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1312) node _T_1314 = bits(_T_1313, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1314 node _T_1315 = eq(UInt<3>(0h5), idx_10) when _T_1315 : node _T_1316 = shl(UInt<4>(0ha), 3) node _T_1317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1316) node _T_1318 = bits(_T_1317, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1318 node _T_1319 = eq(UInt<3>(0h6), idx_10) when _T_1319 : node _T_1320 = shl(UInt<4>(0ha), 3) node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320) node _T_1322 = bits(_T_1321, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1322 node _T_1323 = eq(UInt<3>(0h7), idx_10) when _T_1323 : node _T_1324 = shl(UInt<4>(0ha), 3) node _T_1325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1324) node _T_1326 = bits(_T_1325, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1326 node _T_1327 = eq(UInt<4>(0h8), idx_10) when _T_1327 : node _T_1328 = shl(UInt<4>(0ha), 3) node _T_1329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1328) node _T_1330 = bits(_T_1329, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1330 node _T_1331 = eq(UInt<4>(0h9), idx_10) when _T_1331 : node _T_1332 = shl(UInt<4>(0ha), 3) node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332) node _T_1334 = bits(_T_1333, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1334 node _T_1335 = eq(UInt<4>(0ha), idx_10) when _T_1335 : node _T_1336 = shl(UInt<4>(0ha), 3) node _T_1337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1336) node _T_1338 = bits(_T_1337, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1338 node _T_1339 = eq(UInt<4>(0hb), idx_10) when _T_1339 : node _T_1340 = shl(UInt<4>(0ha), 3) node _T_1341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1340) node _T_1342 = bits(_T_1341, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1342 node _T_1343 = eq(UInt<4>(0hc), idx_10) when _T_1343 : node _T_1344 = shl(UInt<4>(0ha), 3) node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344) node _T_1346 = bits(_T_1345, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1346 node _T_1347 = eq(UInt<4>(0hd), idx_10) when _T_1347 : node _T_1348 = shl(UInt<4>(0ha), 3) node _T_1349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1348) node _T_1350 = bits(_T_1349, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1350 node _T_1351 = eq(UInt<4>(0he), idx_10) when _T_1351 : node _T_1352 = shl(UInt<4>(0ha), 3) node _T_1353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1352) node _T_1354 = bits(_T_1353, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1354 node _T_1355 = eq(UInt<4>(0hf), idx_10) when _T_1355 : node _T_1356 = shl(UInt<4>(0ha), 3) node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356) node _T_1358 = bits(_T_1357, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1358 node _T_1359 = eq(UInt<5>(0h10), idx_10) when _T_1359 : node _T_1360 = shl(UInt<4>(0ha), 3) node _T_1361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1360) node _T_1362 = bits(_T_1361, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1362 node _T_1363 = eq(UInt<5>(0h11), idx_10) when _T_1363 : node _T_1364 = shl(UInt<4>(0ha), 3) node _T_1365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1364) node _T_1366 = bits(_T_1365, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1366 node _T_1367 = eq(UInt<5>(0h12), idx_10) when _T_1367 : node _T_1368 = shl(UInt<4>(0ha), 3) node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368) node _T_1370 = bits(_T_1369, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1370 node _T_1371 = eq(UInt<5>(0h13), idx_10) when _T_1371 : node _T_1372 = shl(UInt<4>(0ha), 3) node _T_1373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1372) node _T_1374 = bits(_T_1373, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1374 node _T_1375 = eq(UInt<5>(0h14), idx_10) when _T_1375 : node _T_1376 = shl(UInt<4>(0ha), 3) node _T_1377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1376) node _T_1378 = bits(_T_1377, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1378 node _T_1379 = eq(UInt<5>(0h15), idx_10) when _T_1379 : node _T_1380 = shl(UInt<4>(0ha), 3) node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380) node _T_1382 = bits(_T_1381, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1382 node _T_1383 = eq(UInt<5>(0h16), idx_10) when _T_1383 : node _T_1384 = shl(UInt<4>(0ha), 3) node _T_1385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1384) node _T_1386 = bits(_T_1385, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1386 node _T_1387 = eq(UInt<5>(0h17), idx_10) when _T_1387 : node _T_1388 = shl(UInt<4>(0ha), 3) node _T_1389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1388) node _T_1390 = bits(_T_1389, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1390 node _T_1391 = eq(UInt<5>(0h18), idx_10) when _T_1391 : node _T_1392 = shl(UInt<4>(0ha), 3) node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392) node _T_1394 = bits(_T_1393, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1394 node _T_1395 = eq(UInt<5>(0h19), idx_10) when _T_1395 : node _T_1396 = shl(UInt<4>(0ha), 3) node _T_1397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1396) node _T_1398 = bits(_T_1397, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1398 node _T_1399 = eq(UInt<5>(0h1a), idx_10) when _T_1399 : node _T_1400 = shl(UInt<4>(0ha), 3) node _T_1401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1400) node _T_1402 = bits(_T_1401, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1402 node _T_1403 = eq(UInt<5>(0h1b), idx_10) when _T_1403 : node _T_1404 = shl(UInt<4>(0ha), 3) node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404) node _T_1406 = bits(_T_1405, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1406 node _T_1407 = eq(UInt<5>(0h1c), idx_10) when _T_1407 : node _T_1408 = shl(UInt<4>(0ha), 3) node _T_1409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1408) node _T_1410 = bits(_T_1409, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1410 node _T_1411 = eq(UInt<5>(0h1d), idx_10) when _T_1411 : node _T_1412 = shl(UInt<4>(0ha), 3) node _T_1413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1412) node _T_1414 = bits(_T_1413, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1414 node _T_1415 = eq(UInt<5>(0h1e), idx_10) when _T_1415 : node _T_1416 = shl(UInt<4>(0ha), 3) node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416) node _T_1418 = bits(_T_1417, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1418 node _T_1419 = eq(UInt<5>(0h1f), idx_10) when _T_1419 : node _T_1420 = shl(UInt<4>(0ha), 3) node _T_1421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1420) node _T_1422 = bits(_T_1421, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1422 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_1423 = eq(UInt<1>(0h0), idx_11) when _T_1423 : node _T_1424 = shl(UInt<4>(0hb), 3) node _T_1425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1424) node _T_1426 = bits(_T_1425, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1426 node _T_1427 = eq(UInt<1>(0h1), idx_11) when _T_1427 : node _T_1428 = shl(UInt<4>(0hb), 3) node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428) node _T_1430 = bits(_T_1429, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1430 node _T_1431 = eq(UInt<2>(0h2), idx_11) when _T_1431 : node _T_1432 = shl(UInt<4>(0hb), 3) node _T_1433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1432) node _T_1434 = bits(_T_1433, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1434 node _T_1435 = eq(UInt<2>(0h3), idx_11) when _T_1435 : node _T_1436 = shl(UInt<4>(0hb), 3) node _T_1437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1436) node _T_1438 = bits(_T_1437, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1438 node _T_1439 = eq(UInt<3>(0h4), idx_11) when _T_1439 : node _T_1440 = shl(UInt<4>(0hb), 3) node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440) node _T_1442 = bits(_T_1441, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1442 node _T_1443 = eq(UInt<3>(0h5), idx_11) when _T_1443 : node _T_1444 = shl(UInt<4>(0hb), 3) node _T_1445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1444) node _T_1446 = bits(_T_1445, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1446 node _T_1447 = eq(UInt<3>(0h6), idx_11) when _T_1447 : node _T_1448 = shl(UInt<4>(0hb), 3) node _T_1449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1448) node _T_1450 = bits(_T_1449, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1450 node _T_1451 = eq(UInt<3>(0h7), idx_11) when _T_1451 : node _T_1452 = shl(UInt<4>(0hb), 3) node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452) node _T_1454 = bits(_T_1453, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1454 node _T_1455 = eq(UInt<4>(0h8), idx_11) when _T_1455 : node _T_1456 = shl(UInt<4>(0hb), 3) node _T_1457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1456) node _T_1458 = bits(_T_1457, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1458 node _T_1459 = eq(UInt<4>(0h9), idx_11) when _T_1459 : node _T_1460 = shl(UInt<4>(0hb), 3) node _T_1461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1460) node _T_1462 = bits(_T_1461, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1462 node _T_1463 = eq(UInt<4>(0ha), idx_11) when _T_1463 : node _T_1464 = shl(UInt<4>(0hb), 3) node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464) node _T_1466 = bits(_T_1465, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1466 node _T_1467 = eq(UInt<4>(0hb), idx_11) when _T_1467 : node _T_1468 = shl(UInt<4>(0hb), 3) node _T_1469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1468) node _T_1470 = bits(_T_1469, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1470 node _T_1471 = eq(UInt<4>(0hc), idx_11) when _T_1471 : node _T_1472 = shl(UInt<4>(0hb), 3) node _T_1473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1472) node _T_1474 = bits(_T_1473, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1474 node _T_1475 = eq(UInt<4>(0hd), idx_11) when _T_1475 : node _T_1476 = shl(UInt<4>(0hb), 3) node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476) node _T_1478 = bits(_T_1477, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1478 node _T_1479 = eq(UInt<4>(0he), idx_11) when _T_1479 : node _T_1480 = shl(UInt<4>(0hb), 3) node _T_1481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1480) node _T_1482 = bits(_T_1481, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1482 node _T_1483 = eq(UInt<4>(0hf), idx_11) when _T_1483 : node _T_1484 = shl(UInt<4>(0hb), 3) node _T_1485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1484) node _T_1486 = bits(_T_1485, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1486 node _T_1487 = eq(UInt<5>(0h10), idx_11) when _T_1487 : node _T_1488 = shl(UInt<4>(0hb), 3) node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488) node _T_1490 = bits(_T_1489, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1490 node _T_1491 = eq(UInt<5>(0h11), idx_11) when _T_1491 : node _T_1492 = shl(UInt<4>(0hb), 3) node _T_1493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1492) node _T_1494 = bits(_T_1493, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1494 node _T_1495 = eq(UInt<5>(0h12), idx_11) when _T_1495 : node _T_1496 = shl(UInt<4>(0hb), 3) node _T_1497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1496) node _T_1498 = bits(_T_1497, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1498 node _T_1499 = eq(UInt<5>(0h13), idx_11) when _T_1499 : node _T_1500 = shl(UInt<4>(0hb), 3) node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500) node _T_1502 = bits(_T_1501, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1502 node _T_1503 = eq(UInt<5>(0h14), idx_11) when _T_1503 : node _T_1504 = shl(UInt<4>(0hb), 3) node _T_1505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1504) node _T_1506 = bits(_T_1505, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1506 node _T_1507 = eq(UInt<5>(0h15), idx_11) when _T_1507 : node _T_1508 = shl(UInt<4>(0hb), 3) node _T_1509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1508) node _T_1510 = bits(_T_1509, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1510 node _T_1511 = eq(UInt<5>(0h16), idx_11) when _T_1511 : node _T_1512 = shl(UInt<4>(0hb), 3) node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512) node _T_1514 = bits(_T_1513, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1514 node _T_1515 = eq(UInt<5>(0h17), idx_11) when _T_1515 : node _T_1516 = shl(UInt<4>(0hb), 3) node _T_1517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1516) node _T_1518 = bits(_T_1517, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1518 node _T_1519 = eq(UInt<5>(0h18), idx_11) when _T_1519 : node _T_1520 = shl(UInt<4>(0hb), 3) node _T_1521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1520) node _T_1522 = bits(_T_1521, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1522 node _T_1523 = eq(UInt<5>(0h19), idx_11) when _T_1523 : node _T_1524 = shl(UInt<4>(0hb), 3) node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524) node _T_1526 = bits(_T_1525, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1526 node _T_1527 = eq(UInt<5>(0h1a), idx_11) when _T_1527 : node _T_1528 = shl(UInt<4>(0hb), 3) node _T_1529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1528) node _T_1530 = bits(_T_1529, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1530 node _T_1531 = eq(UInt<5>(0h1b), idx_11) when _T_1531 : node _T_1532 = shl(UInt<4>(0hb), 3) node _T_1533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1532) node _T_1534 = bits(_T_1533, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1534 node _T_1535 = eq(UInt<5>(0h1c), idx_11) when _T_1535 : node _T_1536 = shl(UInt<4>(0hb), 3) node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536) node _T_1538 = bits(_T_1537, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1538 node _T_1539 = eq(UInt<5>(0h1d), idx_11) when _T_1539 : node _T_1540 = shl(UInt<4>(0hb), 3) node _T_1541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1540) node _T_1542 = bits(_T_1541, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1542 node _T_1543 = eq(UInt<5>(0h1e), idx_11) when _T_1543 : node _T_1544 = shl(UInt<4>(0hb), 3) node _T_1545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1544) node _T_1546 = bits(_T_1545, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1546 node _T_1547 = eq(UInt<5>(0h1f), idx_11) when _T_1547 : node _T_1548 = shl(UInt<4>(0hb), 3) node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548) node _T_1550 = bits(_T_1549, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1550 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_1551 = eq(UInt<1>(0h0), idx_12) when _T_1551 : node _T_1552 = shl(UInt<4>(0hc), 3) node _T_1553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1552) node _T_1554 = bits(_T_1553, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1554 node _T_1555 = eq(UInt<1>(0h1), idx_12) when _T_1555 : node _T_1556 = shl(UInt<4>(0hc), 3) node _T_1557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1556) node _T_1558 = bits(_T_1557, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1558 node _T_1559 = eq(UInt<2>(0h2), idx_12) when _T_1559 : node _T_1560 = shl(UInt<4>(0hc), 3) node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560) node _T_1562 = bits(_T_1561, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1562 node _T_1563 = eq(UInt<2>(0h3), idx_12) when _T_1563 : node _T_1564 = shl(UInt<4>(0hc), 3) node _T_1565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1564) node _T_1566 = bits(_T_1565, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1566 node _T_1567 = eq(UInt<3>(0h4), idx_12) when _T_1567 : node _T_1568 = shl(UInt<4>(0hc), 3) node _T_1569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1568) node _T_1570 = bits(_T_1569, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1570 node _T_1571 = eq(UInt<3>(0h5), idx_12) when _T_1571 : node _T_1572 = shl(UInt<4>(0hc), 3) node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572) node _T_1574 = bits(_T_1573, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1574 node _T_1575 = eq(UInt<3>(0h6), idx_12) when _T_1575 : node _T_1576 = shl(UInt<4>(0hc), 3) node _T_1577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1576) node _T_1578 = bits(_T_1577, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1578 node _T_1579 = eq(UInt<3>(0h7), idx_12) when _T_1579 : node _T_1580 = shl(UInt<4>(0hc), 3) node _T_1581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1580) node _T_1582 = bits(_T_1581, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1582 node _T_1583 = eq(UInt<4>(0h8), idx_12) when _T_1583 : node _T_1584 = shl(UInt<4>(0hc), 3) node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584) node _T_1586 = bits(_T_1585, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1586 node _T_1587 = eq(UInt<4>(0h9), idx_12) when _T_1587 : node _T_1588 = shl(UInt<4>(0hc), 3) node _T_1589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1588) node _T_1590 = bits(_T_1589, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1590 node _T_1591 = eq(UInt<4>(0ha), idx_12) when _T_1591 : node _T_1592 = shl(UInt<4>(0hc), 3) node _T_1593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1592) node _T_1594 = bits(_T_1593, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1594 node _T_1595 = eq(UInt<4>(0hb), idx_12) when _T_1595 : node _T_1596 = shl(UInt<4>(0hc), 3) node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596) node _T_1598 = bits(_T_1597, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1598 node _T_1599 = eq(UInt<4>(0hc), idx_12) when _T_1599 : node _T_1600 = shl(UInt<4>(0hc), 3) node _T_1601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1600) node _T_1602 = bits(_T_1601, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1602 node _T_1603 = eq(UInt<4>(0hd), idx_12) when _T_1603 : node _T_1604 = shl(UInt<4>(0hc), 3) node _T_1605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1604) node _T_1606 = bits(_T_1605, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1606 node _T_1607 = eq(UInt<4>(0he), idx_12) when _T_1607 : node _T_1608 = shl(UInt<4>(0hc), 3) node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608) node _T_1610 = bits(_T_1609, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1610 node _T_1611 = eq(UInt<4>(0hf), idx_12) when _T_1611 : node _T_1612 = shl(UInt<4>(0hc), 3) node _T_1613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1612) node _T_1614 = bits(_T_1613, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1614 node _T_1615 = eq(UInt<5>(0h10), idx_12) when _T_1615 : node _T_1616 = shl(UInt<4>(0hc), 3) node _T_1617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1616) node _T_1618 = bits(_T_1617, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1618 node _T_1619 = eq(UInt<5>(0h11), idx_12) when _T_1619 : node _T_1620 = shl(UInt<4>(0hc), 3) node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620) node _T_1622 = bits(_T_1621, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1622 node _T_1623 = eq(UInt<5>(0h12), idx_12) when _T_1623 : node _T_1624 = shl(UInt<4>(0hc), 3) node _T_1625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1624) node _T_1626 = bits(_T_1625, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1626 node _T_1627 = eq(UInt<5>(0h13), idx_12) when _T_1627 : node _T_1628 = shl(UInt<4>(0hc), 3) node _T_1629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1628) node _T_1630 = bits(_T_1629, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1630 node _T_1631 = eq(UInt<5>(0h14), idx_12) when _T_1631 : node _T_1632 = shl(UInt<4>(0hc), 3) node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632) node _T_1634 = bits(_T_1633, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1634 node _T_1635 = eq(UInt<5>(0h15), idx_12) when _T_1635 : node _T_1636 = shl(UInt<4>(0hc), 3) node _T_1637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1636) node _T_1638 = bits(_T_1637, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1638 node _T_1639 = eq(UInt<5>(0h16), idx_12) when _T_1639 : node _T_1640 = shl(UInt<4>(0hc), 3) node _T_1641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1640) node _T_1642 = bits(_T_1641, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1642 node _T_1643 = eq(UInt<5>(0h17), idx_12) when _T_1643 : node _T_1644 = shl(UInt<4>(0hc), 3) node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644) node _T_1646 = bits(_T_1645, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1646 node _T_1647 = eq(UInt<5>(0h18), idx_12) when _T_1647 : node _T_1648 = shl(UInt<4>(0hc), 3) node _T_1649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1648) node _T_1650 = bits(_T_1649, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1650 node _T_1651 = eq(UInt<5>(0h19), idx_12) when _T_1651 : node _T_1652 = shl(UInt<4>(0hc), 3) node _T_1653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1652) node _T_1654 = bits(_T_1653, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1654 node _T_1655 = eq(UInt<5>(0h1a), idx_12) when _T_1655 : node _T_1656 = shl(UInt<4>(0hc), 3) node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656) node _T_1658 = bits(_T_1657, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1658 node _T_1659 = eq(UInt<5>(0h1b), idx_12) when _T_1659 : node _T_1660 = shl(UInt<4>(0hc), 3) node _T_1661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1660) node _T_1662 = bits(_T_1661, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1662 node _T_1663 = eq(UInt<5>(0h1c), idx_12) when _T_1663 : node _T_1664 = shl(UInt<4>(0hc), 3) node _T_1665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1664) node _T_1666 = bits(_T_1665, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1666 node _T_1667 = eq(UInt<5>(0h1d), idx_12) when _T_1667 : node _T_1668 = shl(UInt<4>(0hc), 3) node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668) node _T_1670 = bits(_T_1669, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1670 node _T_1671 = eq(UInt<5>(0h1e), idx_12) when _T_1671 : node _T_1672 = shl(UInt<4>(0hc), 3) node _T_1673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1672) node _T_1674 = bits(_T_1673, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1674 node _T_1675 = eq(UInt<5>(0h1f), idx_12) when _T_1675 : node _T_1676 = shl(UInt<4>(0hc), 3) node _T_1677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1676) node _T_1678 = bits(_T_1677, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1678 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_1679 = eq(UInt<1>(0h0), idx_13) when _T_1679 : node _T_1680 = shl(UInt<4>(0hd), 3) node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680) node _T_1682 = bits(_T_1681, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1682 node _T_1683 = eq(UInt<1>(0h1), idx_13) when _T_1683 : node _T_1684 = shl(UInt<4>(0hd), 3) node _T_1685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1684) node _T_1686 = bits(_T_1685, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1686 node _T_1687 = eq(UInt<2>(0h2), idx_13) when _T_1687 : node _T_1688 = shl(UInt<4>(0hd), 3) node _T_1689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1688) node _T_1690 = bits(_T_1689, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1690 node _T_1691 = eq(UInt<2>(0h3), idx_13) when _T_1691 : node _T_1692 = shl(UInt<4>(0hd), 3) node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692) node _T_1694 = bits(_T_1693, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1694 node _T_1695 = eq(UInt<3>(0h4), idx_13) when _T_1695 : node _T_1696 = shl(UInt<4>(0hd), 3) node _T_1697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1696) node _T_1698 = bits(_T_1697, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1698 node _T_1699 = eq(UInt<3>(0h5), idx_13) when _T_1699 : node _T_1700 = shl(UInt<4>(0hd), 3) node _T_1701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1700) node _T_1702 = bits(_T_1701, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1702 node _T_1703 = eq(UInt<3>(0h6), idx_13) when _T_1703 : node _T_1704 = shl(UInt<4>(0hd), 3) node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704) node _T_1706 = bits(_T_1705, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1706 node _T_1707 = eq(UInt<3>(0h7), idx_13) when _T_1707 : node _T_1708 = shl(UInt<4>(0hd), 3) node _T_1709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1708) node _T_1710 = bits(_T_1709, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1710 node _T_1711 = eq(UInt<4>(0h8), idx_13) when _T_1711 : node _T_1712 = shl(UInt<4>(0hd), 3) node _T_1713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1712) node _T_1714 = bits(_T_1713, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1714 node _T_1715 = eq(UInt<4>(0h9), idx_13) when _T_1715 : node _T_1716 = shl(UInt<4>(0hd), 3) node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716) node _T_1718 = bits(_T_1717, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1718 node _T_1719 = eq(UInt<4>(0ha), idx_13) when _T_1719 : node _T_1720 = shl(UInt<4>(0hd), 3) node _T_1721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1720) node _T_1722 = bits(_T_1721, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1722 node _T_1723 = eq(UInt<4>(0hb), idx_13) when _T_1723 : node _T_1724 = shl(UInt<4>(0hd), 3) node _T_1725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1724) node _T_1726 = bits(_T_1725, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1726 node _T_1727 = eq(UInt<4>(0hc), idx_13) when _T_1727 : node _T_1728 = shl(UInt<4>(0hd), 3) node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728) node _T_1730 = bits(_T_1729, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1730 node _T_1731 = eq(UInt<4>(0hd), idx_13) when _T_1731 : node _T_1732 = shl(UInt<4>(0hd), 3) node _T_1733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1732) node _T_1734 = bits(_T_1733, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1734 node _T_1735 = eq(UInt<4>(0he), idx_13) when _T_1735 : node _T_1736 = shl(UInt<4>(0hd), 3) node _T_1737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1736) node _T_1738 = bits(_T_1737, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1738 node _T_1739 = eq(UInt<4>(0hf), idx_13) when _T_1739 : node _T_1740 = shl(UInt<4>(0hd), 3) node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740) node _T_1742 = bits(_T_1741, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1742 node _T_1743 = eq(UInt<5>(0h10), idx_13) when _T_1743 : node _T_1744 = shl(UInt<4>(0hd), 3) node _T_1745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1744) node _T_1746 = bits(_T_1745, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1746 node _T_1747 = eq(UInt<5>(0h11), idx_13) when _T_1747 : node _T_1748 = shl(UInt<4>(0hd), 3) node _T_1749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1748) node _T_1750 = bits(_T_1749, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1750 node _T_1751 = eq(UInt<5>(0h12), idx_13) when _T_1751 : node _T_1752 = shl(UInt<4>(0hd), 3) node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752) node _T_1754 = bits(_T_1753, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1754 node _T_1755 = eq(UInt<5>(0h13), idx_13) when _T_1755 : node _T_1756 = shl(UInt<4>(0hd), 3) node _T_1757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1756) node _T_1758 = bits(_T_1757, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1758 node _T_1759 = eq(UInt<5>(0h14), idx_13) when _T_1759 : node _T_1760 = shl(UInt<4>(0hd), 3) node _T_1761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1760) node _T_1762 = bits(_T_1761, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1762 node _T_1763 = eq(UInt<5>(0h15), idx_13) when _T_1763 : node _T_1764 = shl(UInt<4>(0hd), 3) node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764) node _T_1766 = bits(_T_1765, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1766 node _T_1767 = eq(UInt<5>(0h16), idx_13) when _T_1767 : node _T_1768 = shl(UInt<4>(0hd), 3) node _T_1769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1768) node _T_1770 = bits(_T_1769, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1770 node _T_1771 = eq(UInt<5>(0h17), idx_13) when _T_1771 : node _T_1772 = shl(UInt<4>(0hd), 3) node _T_1773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1772) node _T_1774 = bits(_T_1773, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1774 node _T_1775 = eq(UInt<5>(0h18), idx_13) when _T_1775 : node _T_1776 = shl(UInt<4>(0hd), 3) node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776) node _T_1778 = bits(_T_1777, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1778 node _T_1779 = eq(UInt<5>(0h19), idx_13) when _T_1779 : node _T_1780 = shl(UInt<4>(0hd), 3) node _T_1781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1780) node _T_1782 = bits(_T_1781, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1782 node _T_1783 = eq(UInt<5>(0h1a), idx_13) when _T_1783 : node _T_1784 = shl(UInt<4>(0hd), 3) node _T_1785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1784) node _T_1786 = bits(_T_1785, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1786 node _T_1787 = eq(UInt<5>(0h1b), idx_13) when _T_1787 : node _T_1788 = shl(UInt<4>(0hd), 3) node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788) node _T_1790 = bits(_T_1789, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1790 node _T_1791 = eq(UInt<5>(0h1c), idx_13) when _T_1791 : node _T_1792 = shl(UInt<4>(0hd), 3) node _T_1793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1792) node _T_1794 = bits(_T_1793, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1794 node _T_1795 = eq(UInt<5>(0h1d), idx_13) when _T_1795 : node _T_1796 = shl(UInt<4>(0hd), 3) node _T_1797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1796) node _T_1798 = bits(_T_1797, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1798 node _T_1799 = eq(UInt<5>(0h1e), idx_13) when _T_1799 : node _T_1800 = shl(UInt<4>(0hd), 3) node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800) node _T_1802 = bits(_T_1801, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1802 node _T_1803 = eq(UInt<5>(0h1f), idx_13) when _T_1803 : node _T_1804 = shl(UInt<4>(0hd), 3) node _T_1805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1804) node _T_1806 = bits(_T_1805, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1806 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_1807 = eq(UInt<1>(0h0), idx_14) when _T_1807 : node _T_1808 = shl(UInt<4>(0he), 3) node _T_1809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1808) node _T_1810 = bits(_T_1809, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1810 node _T_1811 = eq(UInt<1>(0h1), idx_14) when _T_1811 : node _T_1812 = shl(UInt<4>(0he), 3) node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812) node _T_1814 = bits(_T_1813, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1814 node _T_1815 = eq(UInt<2>(0h2), idx_14) when _T_1815 : node _T_1816 = shl(UInt<4>(0he), 3) node _T_1817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1816) node _T_1818 = bits(_T_1817, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1818 node _T_1819 = eq(UInt<2>(0h3), idx_14) when _T_1819 : node _T_1820 = shl(UInt<4>(0he), 3) node _T_1821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1820) node _T_1822 = bits(_T_1821, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1822 node _T_1823 = eq(UInt<3>(0h4), idx_14) when _T_1823 : node _T_1824 = shl(UInt<4>(0he), 3) node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824) node _T_1826 = bits(_T_1825, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1826 node _T_1827 = eq(UInt<3>(0h5), idx_14) when _T_1827 : node _T_1828 = shl(UInt<4>(0he), 3) node _T_1829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1828) node _T_1830 = bits(_T_1829, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1830 node _T_1831 = eq(UInt<3>(0h6), idx_14) when _T_1831 : node _T_1832 = shl(UInt<4>(0he), 3) node _T_1833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1832) node _T_1834 = bits(_T_1833, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1834 node _T_1835 = eq(UInt<3>(0h7), idx_14) when _T_1835 : node _T_1836 = shl(UInt<4>(0he), 3) node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836) node _T_1838 = bits(_T_1837, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1838 node _T_1839 = eq(UInt<4>(0h8), idx_14) when _T_1839 : node _T_1840 = shl(UInt<4>(0he), 3) node _T_1841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1840) node _T_1842 = bits(_T_1841, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1842 node _T_1843 = eq(UInt<4>(0h9), idx_14) when _T_1843 : node _T_1844 = shl(UInt<4>(0he), 3) node _T_1845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1844) node _T_1846 = bits(_T_1845, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1846 node _T_1847 = eq(UInt<4>(0ha), idx_14) when _T_1847 : node _T_1848 = shl(UInt<4>(0he), 3) node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848) node _T_1850 = bits(_T_1849, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1850 node _T_1851 = eq(UInt<4>(0hb), idx_14) when _T_1851 : node _T_1852 = shl(UInt<4>(0he), 3) node _T_1853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1852) node _T_1854 = bits(_T_1853, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1854 node _T_1855 = eq(UInt<4>(0hc), idx_14) when _T_1855 : node _T_1856 = shl(UInt<4>(0he), 3) node _T_1857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1856) node _T_1858 = bits(_T_1857, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1858 node _T_1859 = eq(UInt<4>(0hd), idx_14) when _T_1859 : node _T_1860 = shl(UInt<4>(0he), 3) node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860) node _T_1862 = bits(_T_1861, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1862 node _T_1863 = eq(UInt<4>(0he), idx_14) when _T_1863 : node _T_1864 = shl(UInt<4>(0he), 3) node _T_1865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1864) node _T_1866 = bits(_T_1865, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1866 node _T_1867 = eq(UInt<4>(0hf), idx_14) when _T_1867 : node _T_1868 = shl(UInt<4>(0he), 3) node _T_1869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1868) node _T_1870 = bits(_T_1869, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1870 node _T_1871 = eq(UInt<5>(0h10), idx_14) when _T_1871 : node _T_1872 = shl(UInt<4>(0he), 3) node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872) node _T_1874 = bits(_T_1873, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1874 node _T_1875 = eq(UInt<5>(0h11), idx_14) when _T_1875 : node _T_1876 = shl(UInt<4>(0he), 3) node _T_1877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1876) node _T_1878 = bits(_T_1877, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1878 node _T_1879 = eq(UInt<5>(0h12), idx_14) when _T_1879 : node _T_1880 = shl(UInt<4>(0he), 3) node _T_1881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1880) node _T_1882 = bits(_T_1881, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1882 node _T_1883 = eq(UInt<5>(0h13), idx_14) when _T_1883 : node _T_1884 = shl(UInt<4>(0he), 3) node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884) node _T_1886 = bits(_T_1885, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1886 node _T_1887 = eq(UInt<5>(0h14), idx_14) when _T_1887 : node _T_1888 = shl(UInt<4>(0he), 3) node _T_1889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1888) node _T_1890 = bits(_T_1889, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1890 node _T_1891 = eq(UInt<5>(0h15), idx_14) when _T_1891 : node _T_1892 = shl(UInt<4>(0he), 3) node _T_1893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1892) node _T_1894 = bits(_T_1893, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1894 node _T_1895 = eq(UInt<5>(0h16), idx_14) when _T_1895 : node _T_1896 = shl(UInt<4>(0he), 3) node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896) node _T_1898 = bits(_T_1897, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1898 node _T_1899 = eq(UInt<5>(0h17), idx_14) when _T_1899 : node _T_1900 = shl(UInt<4>(0he), 3) node _T_1901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1900) node _T_1902 = bits(_T_1901, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1902 node _T_1903 = eq(UInt<5>(0h18), idx_14) when _T_1903 : node _T_1904 = shl(UInt<4>(0he), 3) node _T_1905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1904) node _T_1906 = bits(_T_1905, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1906 node _T_1907 = eq(UInt<5>(0h19), idx_14) when _T_1907 : node _T_1908 = shl(UInt<4>(0he), 3) node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908) node _T_1910 = bits(_T_1909, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1910 node _T_1911 = eq(UInt<5>(0h1a), idx_14) when _T_1911 : node _T_1912 = shl(UInt<4>(0he), 3) node _T_1913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1912) node _T_1914 = bits(_T_1913, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1914 node _T_1915 = eq(UInt<5>(0h1b), idx_14) when _T_1915 : node _T_1916 = shl(UInt<4>(0he), 3) node _T_1917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1916) node _T_1918 = bits(_T_1917, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1918 node _T_1919 = eq(UInt<5>(0h1c), idx_14) when _T_1919 : node _T_1920 = shl(UInt<4>(0he), 3) node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920) node _T_1922 = bits(_T_1921, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1922 node _T_1923 = eq(UInt<5>(0h1d), idx_14) when _T_1923 : node _T_1924 = shl(UInt<4>(0he), 3) node _T_1925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1924) node _T_1926 = bits(_T_1925, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1926 node _T_1927 = eq(UInt<5>(0h1e), idx_14) when _T_1927 : node _T_1928 = shl(UInt<4>(0he), 3) node _T_1929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1928) node _T_1930 = bits(_T_1929, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1930 node _T_1931 = eq(UInt<5>(0h1f), idx_14) when _T_1931 : node _T_1932 = shl(UInt<4>(0he), 3) node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932) node _T_1934 = bits(_T_1933, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1934 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1935 = eq(UInt<1>(0h0), idx_15) when _T_1935 : node _T_1936 = shl(UInt<4>(0hf), 3) node _T_1937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1936) node _T_1938 = bits(_T_1937, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1938 node _T_1939 = eq(UInt<1>(0h1), idx_15) when _T_1939 : node _T_1940 = shl(UInt<4>(0hf), 3) node _T_1941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1940) node _T_1942 = bits(_T_1941, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1942 node _T_1943 = eq(UInt<2>(0h2), idx_15) when _T_1943 : node _T_1944 = shl(UInt<4>(0hf), 3) node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944) node _T_1946 = bits(_T_1945, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1946 node _T_1947 = eq(UInt<2>(0h3), idx_15) when _T_1947 : node _T_1948 = shl(UInt<4>(0hf), 3) node _T_1949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1948) node _T_1950 = bits(_T_1949, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1950 node _T_1951 = eq(UInt<3>(0h4), idx_15) when _T_1951 : node _T_1952 = shl(UInt<4>(0hf), 3) node _T_1953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1952) node _T_1954 = bits(_T_1953, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1954 node _T_1955 = eq(UInt<3>(0h5), idx_15) when _T_1955 : node _T_1956 = shl(UInt<4>(0hf), 3) node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956) node _T_1958 = bits(_T_1957, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1958 node _T_1959 = eq(UInt<3>(0h6), idx_15) when _T_1959 : node _T_1960 = shl(UInt<4>(0hf), 3) node _T_1961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1960) node _T_1962 = bits(_T_1961, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1962 node _T_1963 = eq(UInt<3>(0h7), idx_15) when _T_1963 : node _T_1964 = shl(UInt<4>(0hf), 3) node _T_1965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1964) node _T_1966 = bits(_T_1965, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1966 node _T_1967 = eq(UInt<4>(0h8), idx_15) when _T_1967 : node _T_1968 = shl(UInt<4>(0hf), 3) node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968) node _T_1970 = bits(_T_1969, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1970 node _T_1971 = eq(UInt<4>(0h9), idx_15) when _T_1971 : node _T_1972 = shl(UInt<4>(0hf), 3) node _T_1973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1972) node _T_1974 = bits(_T_1973, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1974 node _T_1975 = eq(UInt<4>(0ha), idx_15) when _T_1975 : node _T_1976 = shl(UInt<4>(0hf), 3) node _T_1977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1976) node _T_1978 = bits(_T_1977, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1978 node _T_1979 = eq(UInt<4>(0hb), idx_15) when _T_1979 : node _T_1980 = shl(UInt<4>(0hf), 3) node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980) node _T_1982 = bits(_T_1981, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1982 node _T_1983 = eq(UInt<4>(0hc), idx_15) when _T_1983 : node _T_1984 = shl(UInt<4>(0hf), 3) node _T_1985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1984) node _T_1986 = bits(_T_1985, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1986 node _T_1987 = eq(UInt<4>(0hd), idx_15) when _T_1987 : node _T_1988 = shl(UInt<4>(0hf), 3) node _T_1989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1988) node _T_1990 = bits(_T_1989, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1990 node _T_1991 = eq(UInt<4>(0he), idx_15) when _T_1991 : node _T_1992 = shl(UInt<4>(0hf), 3) node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992) node _T_1994 = bits(_T_1993, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1994 node _T_1995 = eq(UInt<4>(0hf), idx_15) when _T_1995 : node _T_1996 = shl(UInt<4>(0hf), 3) node _T_1997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1996) node _T_1998 = bits(_T_1997, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1998 node _T_1999 = eq(UInt<5>(0h10), idx_15) when _T_1999 : node _T_2000 = shl(UInt<4>(0hf), 3) node _T_2001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2000) node _T_2002 = bits(_T_2001, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2002 node _T_2003 = eq(UInt<5>(0h11), idx_15) when _T_2003 : node _T_2004 = shl(UInt<4>(0hf), 3) node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004) node _T_2006 = bits(_T_2005, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2006 node _T_2007 = eq(UInt<5>(0h12), idx_15) when _T_2007 : node _T_2008 = shl(UInt<4>(0hf), 3) node _T_2009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2008) node _T_2010 = bits(_T_2009, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2010 node _T_2011 = eq(UInt<5>(0h13), idx_15) when _T_2011 : node _T_2012 = shl(UInt<4>(0hf), 3) node _T_2013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2012) node _T_2014 = bits(_T_2013, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2014 node _T_2015 = eq(UInt<5>(0h14), idx_15) when _T_2015 : node _T_2016 = shl(UInt<4>(0hf), 3) node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016) node _T_2018 = bits(_T_2017, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2018 node _T_2019 = eq(UInt<5>(0h15), idx_15) when _T_2019 : node _T_2020 = shl(UInt<4>(0hf), 3) node _T_2021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2020) node _T_2022 = bits(_T_2021, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2022 node _T_2023 = eq(UInt<5>(0h16), idx_15) when _T_2023 : node _T_2024 = shl(UInt<4>(0hf), 3) node _T_2025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2024) node _T_2026 = bits(_T_2025, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2026 node _T_2027 = eq(UInt<5>(0h17), idx_15) when _T_2027 : node _T_2028 = shl(UInt<4>(0hf), 3) node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028) node _T_2030 = bits(_T_2029, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2030 node _T_2031 = eq(UInt<5>(0h18), idx_15) when _T_2031 : node _T_2032 = shl(UInt<4>(0hf), 3) node _T_2033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2032) node _T_2034 = bits(_T_2033, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2034 node _T_2035 = eq(UInt<5>(0h19), idx_15) when _T_2035 : node _T_2036 = shl(UInt<4>(0hf), 3) node _T_2037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2036) node _T_2038 = bits(_T_2037, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2038 node _T_2039 = eq(UInt<5>(0h1a), idx_15) when _T_2039 : node _T_2040 = shl(UInt<4>(0hf), 3) node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040) node _T_2042 = bits(_T_2041, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2042 node _T_2043 = eq(UInt<5>(0h1b), idx_15) when _T_2043 : node _T_2044 = shl(UInt<4>(0hf), 3) node _T_2045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2044) node _T_2046 = bits(_T_2045, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2046 node _T_2047 = eq(UInt<5>(0h1c), idx_15) when _T_2047 : node _T_2048 = shl(UInt<4>(0hf), 3) node _T_2049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2048) node _T_2050 = bits(_T_2049, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2050 node _T_2051 = eq(UInt<5>(0h1d), idx_15) when _T_2051 : node _T_2052 = shl(UInt<4>(0hf), 3) node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052) node _T_2054 = bits(_T_2053, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2054 node _T_2055 = eq(UInt<5>(0h1e), idx_15) when _T_2055 : node _T_2056 = shl(UInt<4>(0hf), 3) node _T_2057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2056) node _T_2058 = bits(_T_2057, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2058 node _T_2059 = eq(UInt<5>(0h1f), idx_15) when _T_2059 : node _T_2060 = shl(UInt<4>(0hf), 3) node _T_2061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2060) node _T_2062 = bits(_T_2061, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2062 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_2063 = eq(UInt<1>(0h0), idx_16) when _T_2063 : node _T_2064 = shl(UInt<5>(0h10), 3) node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064) node _T_2066 = bits(_T_2065, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2066 node _T_2067 = eq(UInt<1>(0h1), idx_16) when _T_2067 : node _T_2068 = shl(UInt<5>(0h10), 3) node _T_2069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2068) node _T_2070 = bits(_T_2069, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2070 node _T_2071 = eq(UInt<2>(0h2), idx_16) when _T_2071 : node _T_2072 = shl(UInt<5>(0h10), 3) node _T_2073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2072) node _T_2074 = bits(_T_2073, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2074 node _T_2075 = eq(UInt<2>(0h3), idx_16) when _T_2075 : node _T_2076 = shl(UInt<5>(0h10), 3) node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076) node _T_2078 = bits(_T_2077, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2078 node _T_2079 = eq(UInt<3>(0h4), idx_16) when _T_2079 : node _T_2080 = shl(UInt<5>(0h10), 3) node _T_2081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2080) node _T_2082 = bits(_T_2081, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2082 node _T_2083 = eq(UInt<3>(0h5), idx_16) when _T_2083 : node _T_2084 = shl(UInt<5>(0h10), 3) node _T_2085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2084) node _T_2086 = bits(_T_2085, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2086 node _T_2087 = eq(UInt<3>(0h6), idx_16) when _T_2087 : node _T_2088 = shl(UInt<5>(0h10), 3) node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088) node _T_2090 = bits(_T_2089, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2090 node _T_2091 = eq(UInt<3>(0h7), idx_16) when _T_2091 : node _T_2092 = shl(UInt<5>(0h10), 3) node _T_2093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2092) node _T_2094 = bits(_T_2093, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2094 node _T_2095 = eq(UInt<4>(0h8), idx_16) when _T_2095 : node _T_2096 = shl(UInt<5>(0h10), 3) node _T_2097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2096) node _T_2098 = bits(_T_2097, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2098 node _T_2099 = eq(UInt<4>(0h9), idx_16) when _T_2099 : node _T_2100 = shl(UInt<5>(0h10), 3) node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100) node _T_2102 = bits(_T_2101, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2102 node _T_2103 = eq(UInt<4>(0ha), idx_16) when _T_2103 : node _T_2104 = shl(UInt<5>(0h10), 3) node _T_2105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2104) node _T_2106 = bits(_T_2105, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2106 node _T_2107 = eq(UInt<4>(0hb), idx_16) when _T_2107 : node _T_2108 = shl(UInt<5>(0h10), 3) node _T_2109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2108) node _T_2110 = bits(_T_2109, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2110 node _T_2111 = eq(UInt<4>(0hc), idx_16) when _T_2111 : node _T_2112 = shl(UInt<5>(0h10), 3) node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112) node _T_2114 = bits(_T_2113, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2114 node _T_2115 = eq(UInt<4>(0hd), idx_16) when _T_2115 : node _T_2116 = shl(UInt<5>(0h10), 3) node _T_2117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2116) node _T_2118 = bits(_T_2117, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2118 node _T_2119 = eq(UInt<4>(0he), idx_16) when _T_2119 : node _T_2120 = shl(UInt<5>(0h10), 3) node _T_2121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2120) node _T_2122 = bits(_T_2121, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2122 node _T_2123 = eq(UInt<4>(0hf), idx_16) when _T_2123 : node _T_2124 = shl(UInt<5>(0h10), 3) node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124) node _T_2126 = bits(_T_2125, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2126 node _T_2127 = eq(UInt<5>(0h10), idx_16) when _T_2127 : node _T_2128 = shl(UInt<5>(0h10), 3) node _T_2129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2128) node _T_2130 = bits(_T_2129, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2130 node _T_2131 = eq(UInt<5>(0h11), idx_16) when _T_2131 : node _T_2132 = shl(UInt<5>(0h10), 3) node _T_2133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2132) node _T_2134 = bits(_T_2133, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2134 node _T_2135 = eq(UInt<5>(0h12), idx_16) when _T_2135 : node _T_2136 = shl(UInt<5>(0h10), 3) node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136) node _T_2138 = bits(_T_2137, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2138 node _T_2139 = eq(UInt<5>(0h13), idx_16) when _T_2139 : node _T_2140 = shl(UInt<5>(0h10), 3) node _T_2141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2140) node _T_2142 = bits(_T_2141, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2142 node _T_2143 = eq(UInt<5>(0h14), idx_16) when _T_2143 : node _T_2144 = shl(UInt<5>(0h10), 3) node _T_2145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2144) node _T_2146 = bits(_T_2145, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2146 node _T_2147 = eq(UInt<5>(0h15), idx_16) when _T_2147 : node _T_2148 = shl(UInt<5>(0h10), 3) node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148) node _T_2150 = bits(_T_2149, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2150 node _T_2151 = eq(UInt<5>(0h16), idx_16) when _T_2151 : node _T_2152 = shl(UInt<5>(0h10), 3) node _T_2153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2152) node _T_2154 = bits(_T_2153, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2154 node _T_2155 = eq(UInt<5>(0h17), idx_16) when _T_2155 : node _T_2156 = shl(UInt<5>(0h10), 3) node _T_2157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2156) node _T_2158 = bits(_T_2157, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2158 node _T_2159 = eq(UInt<5>(0h18), idx_16) when _T_2159 : node _T_2160 = shl(UInt<5>(0h10), 3) node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160) node _T_2162 = bits(_T_2161, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2162 node _T_2163 = eq(UInt<5>(0h19), idx_16) when _T_2163 : node _T_2164 = shl(UInt<5>(0h10), 3) node _T_2165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2164) node _T_2166 = bits(_T_2165, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2166 node _T_2167 = eq(UInt<5>(0h1a), idx_16) when _T_2167 : node _T_2168 = shl(UInt<5>(0h10), 3) node _T_2169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2168) node _T_2170 = bits(_T_2169, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2170 node _T_2171 = eq(UInt<5>(0h1b), idx_16) when _T_2171 : node _T_2172 = shl(UInt<5>(0h10), 3) node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172) node _T_2174 = bits(_T_2173, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2174 node _T_2175 = eq(UInt<5>(0h1c), idx_16) when _T_2175 : node _T_2176 = shl(UInt<5>(0h10), 3) node _T_2177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2176) node _T_2178 = bits(_T_2177, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2178 node _T_2179 = eq(UInt<5>(0h1d), idx_16) when _T_2179 : node _T_2180 = shl(UInt<5>(0h10), 3) node _T_2181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2180) node _T_2182 = bits(_T_2181, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2182 node _T_2183 = eq(UInt<5>(0h1e), idx_16) when _T_2183 : node _T_2184 = shl(UInt<5>(0h10), 3) node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184) node _T_2186 = bits(_T_2185, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2186 node _T_2187 = eq(UInt<5>(0h1f), idx_16) when _T_2187 : node _T_2188 = shl(UInt<5>(0h10), 3) node _T_2189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2188) node _T_2190 = bits(_T_2189, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2190 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_2191 = eq(UInt<1>(0h0), idx_17) when _T_2191 : node _T_2192 = shl(UInt<5>(0h11), 3) node _T_2193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2192) node _T_2194 = bits(_T_2193, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2194 node _T_2195 = eq(UInt<1>(0h1), idx_17) when _T_2195 : node _T_2196 = shl(UInt<5>(0h11), 3) node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196) node _T_2198 = bits(_T_2197, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2198 node _T_2199 = eq(UInt<2>(0h2), idx_17) when _T_2199 : node _T_2200 = shl(UInt<5>(0h11), 3) node _T_2201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2200) node _T_2202 = bits(_T_2201, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2202 node _T_2203 = eq(UInt<2>(0h3), idx_17) when _T_2203 : node _T_2204 = shl(UInt<5>(0h11), 3) node _T_2205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2204) node _T_2206 = bits(_T_2205, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2206 node _T_2207 = eq(UInt<3>(0h4), idx_17) when _T_2207 : node _T_2208 = shl(UInt<5>(0h11), 3) node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208) node _T_2210 = bits(_T_2209, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2210 node _T_2211 = eq(UInt<3>(0h5), idx_17) when _T_2211 : node _T_2212 = shl(UInt<5>(0h11), 3) node _T_2213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2212) node _T_2214 = bits(_T_2213, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2214 node _T_2215 = eq(UInt<3>(0h6), idx_17) when _T_2215 : node _T_2216 = shl(UInt<5>(0h11), 3) node _T_2217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2216) node _T_2218 = bits(_T_2217, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2218 node _T_2219 = eq(UInt<3>(0h7), idx_17) when _T_2219 : node _T_2220 = shl(UInt<5>(0h11), 3) node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220) node _T_2222 = bits(_T_2221, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2222 node _T_2223 = eq(UInt<4>(0h8), idx_17) when _T_2223 : node _T_2224 = shl(UInt<5>(0h11), 3) node _T_2225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2224) node _T_2226 = bits(_T_2225, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2226 node _T_2227 = eq(UInt<4>(0h9), idx_17) when _T_2227 : node _T_2228 = shl(UInt<5>(0h11), 3) node _T_2229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2228) node _T_2230 = bits(_T_2229, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2230 node _T_2231 = eq(UInt<4>(0ha), idx_17) when _T_2231 : node _T_2232 = shl(UInt<5>(0h11), 3) node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232) node _T_2234 = bits(_T_2233, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2234 node _T_2235 = eq(UInt<4>(0hb), idx_17) when _T_2235 : node _T_2236 = shl(UInt<5>(0h11), 3) node _T_2237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2236) node _T_2238 = bits(_T_2237, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2238 node _T_2239 = eq(UInt<4>(0hc), idx_17) when _T_2239 : node _T_2240 = shl(UInt<5>(0h11), 3) node _T_2241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2240) node _T_2242 = bits(_T_2241, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2242 node _T_2243 = eq(UInt<4>(0hd), idx_17) when _T_2243 : node _T_2244 = shl(UInt<5>(0h11), 3) node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244) node _T_2246 = bits(_T_2245, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2246 node _T_2247 = eq(UInt<4>(0he), idx_17) when _T_2247 : node _T_2248 = shl(UInt<5>(0h11), 3) node _T_2249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2248) node _T_2250 = bits(_T_2249, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2250 node _T_2251 = eq(UInt<4>(0hf), idx_17) when _T_2251 : node _T_2252 = shl(UInt<5>(0h11), 3) node _T_2253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2252) node _T_2254 = bits(_T_2253, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2254 node _T_2255 = eq(UInt<5>(0h10), idx_17) when _T_2255 : node _T_2256 = shl(UInt<5>(0h11), 3) node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256) node _T_2258 = bits(_T_2257, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2258 node _T_2259 = eq(UInt<5>(0h11), idx_17) when _T_2259 : node _T_2260 = shl(UInt<5>(0h11), 3) node _T_2261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2260) node _T_2262 = bits(_T_2261, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2262 node _T_2263 = eq(UInt<5>(0h12), idx_17) when _T_2263 : node _T_2264 = shl(UInt<5>(0h11), 3) node _T_2265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2264) node _T_2266 = bits(_T_2265, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2266 node _T_2267 = eq(UInt<5>(0h13), idx_17) when _T_2267 : node _T_2268 = shl(UInt<5>(0h11), 3) node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268) node _T_2270 = bits(_T_2269, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2270 node _T_2271 = eq(UInt<5>(0h14), idx_17) when _T_2271 : node _T_2272 = shl(UInt<5>(0h11), 3) node _T_2273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2272) node _T_2274 = bits(_T_2273, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2274 node _T_2275 = eq(UInt<5>(0h15), idx_17) when _T_2275 : node _T_2276 = shl(UInt<5>(0h11), 3) node _T_2277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2276) node _T_2278 = bits(_T_2277, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2278 node _T_2279 = eq(UInt<5>(0h16), idx_17) when _T_2279 : node _T_2280 = shl(UInt<5>(0h11), 3) node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280) node _T_2282 = bits(_T_2281, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2282 node _T_2283 = eq(UInt<5>(0h17), idx_17) when _T_2283 : node _T_2284 = shl(UInt<5>(0h11), 3) node _T_2285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2284) node _T_2286 = bits(_T_2285, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2286 node _T_2287 = eq(UInt<5>(0h18), idx_17) when _T_2287 : node _T_2288 = shl(UInt<5>(0h11), 3) node _T_2289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2288) node _T_2290 = bits(_T_2289, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2290 node _T_2291 = eq(UInt<5>(0h19), idx_17) when _T_2291 : node _T_2292 = shl(UInt<5>(0h11), 3) node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292) node _T_2294 = bits(_T_2293, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2294 node _T_2295 = eq(UInt<5>(0h1a), idx_17) when _T_2295 : node _T_2296 = shl(UInt<5>(0h11), 3) node _T_2297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2296) node _T_2298 = bits(_T_2297, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2298 node _T_2299 = eq(UInt<5>(0h1b), idx_17) when _T_2299 : node _T_2300 = shl(UInt<5>(0h11), 3) node _T_2301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2300) node _T_2302 = bits(_T_2301, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2302 node _T_2303 = eq(UInt<5>(0h1c), idx_17) when _T_2303 : node _T_2304 = shl(UInt<5>(0h11), 3) node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304) node _T_2306 = bits(_T_2305, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2306 node _T_2307 = eq(UInt<5>(0h1d), idx_17) when _T_2307 : node _T_2308 = shl(UInt<5>(0h11), 3) node _T_2309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2308) node _T_2310 = bits(_T_2309, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2310 node _T_2311 = eq(UInt<5>(0h1e), idx_17) when _T_2311 : node _T_2312 = shl(UInt<5>(0h11), 3) node _T_2313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2312) node _T_2314 = bits(_T_2313, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2314 node _T_2315 = eq(UInt<5>(0h1f), idx_17) when _T_2315 : node _T_2316 = shl(UInt<5>(0h11), 3) node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316) node _T_2318 = bits(_T_2317, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2318 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_2319 = eq(UInt<1>(0h0), idx_18) when _T_2319 : node _T_2320 = shl(UInt<5>(0h12), 3) node _T_2321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2320) node _T_2322 = bits(_T_2321, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2322 node _T_2323 = eq(UInt<1>(0h1), idx_18) when _T_2323 : node _T_2324 = shl(UInt<5>(0h12), 3) node _T_2325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2324) node _T_2326 = bits(_T_2325, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2326 node _T_2327 = eq(UInt<2>(0h2), idx_18) when _T_2327 : node _T_2328 = shl(UInt<5>(0h12), 3) node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328) node _T_2330 = bits(_T_2329, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2330 node _T_2331 = eq(UInt<2>(0h3), idx_18) when _T_2331 : node _T_2332 = shl(UInt<5>(0h12), 3) node _T_2333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2332) node _T_2334 = bits(_T_2333, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2334 node _T_2335 = eq(UInt<3>(0h4), idx_18) when _T_2335 : node _T_2336 = shl(UInt<5>(0h12), 3) node _T_2337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2336) node _T_2338 = bits(_T_2337, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2338 node _T_2339 = eq(UInt<3>(0h5), idx_18) when _T_2339 : node _T_2340 = shl(UInt<5>(0h12), 3) node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340) node _T_2342 = bits(_T_2341, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2342 node _T_2343 = eq(UInt<3>(0h6), idx_18) when _T_2343 : node _T_2344 = shl(UInt<5>(0h12), 3) node _T_2345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2344) node _T_2346 = bits(_T_2345, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2346 node _T_2347 = eq(UInt<3>(0h7), idx_18) when _T_2347 : node _T_2348 = shl(UInt<5>(0h12), 3) node _T_2349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2348) node _T_2350 = bits(_T_2349, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2350 node _T_2351 = eq(UInt<4>(0h8), idx_18) when _T_2351 : node _T_2352 = shl(UInt<5>(0h12), 3) node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352) node _T_2354 = bits(_T_2353, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2354 node _T_2355 = eq(UInt<4>(0h9), idx_18) when _T_2355 : node _T_2356 = shl(UInt<5>(0h12), 3) node _T_2357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2356) node _T_2358 = bits(_T_2357, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2358 node _T_2359 = eq(UInt<4>(0ha), idx_18) when _T_2359 : node _T_2360 = shl(UInt<5>(0h12), 3) node _T_2361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2360) node _T_2362 = bits(_T_2361, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2362 node _T_2363 = eq(UInt<4>(0hb), idx_18) when _T_2363 : node _T_2364 = shl(UInt<5>(0h12), 3) node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364) node _T_2366 = bits(_T_2365, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2366 node _T_2367 = eq(UInt<4>(0hc), idx_18) when _T_2367 : node _T_2368 = shl(UInt<5>(0h12), 3) node _T_2369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2368) node _T_2370 = bits(_T_2369, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2370 node _T_2371 = eq(UInt<4>(0hd), idx_18) when _T_2371 : node _T_2372 = shl(UInt<5>(0h12), 3) node _T_2373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2372) node _T_2374 = bits(_T_2373, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2374 node _T_2375 = eq(UInt<4>(0he), idx_18) when _T_2375 : node _T_2376 = shl(UInt<5>(0h12), 3) node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376) node _T_2378 = bits(_T_2377, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2378 node _T_2379 = eq(UInt<4>(0hf), idx_18) when _T_2379 : node _T_2380 = shl(UInt<5>(0h12), 3) node _T_2381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2380) node _T_2382 = bits(_T_2381, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2382 node _T_2383 = eq(UInt<5>(0h10), idx_18) when _T_2383 : node _T_2384 = shl(UInt<5>(0h12), 3) node _T_2385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2384) node _T_2386 = bits(_T_2385, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2386 node _T_2387 = eq(UInt<5>(0h11), idx_18) when _T_2387 : node _T_2388 = shl(UInt<5>(0h12), 3) node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388) node _T_2390 = bits(_T_2389, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2390 node _T_2391 = eq(UInt<5>(0h12), idx_18) when _T_2391 : node _T_2392 = shl(UInt<5>(0h12), 3) node _T_2393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2392) node _T_2394 = bits(_T_2393, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2394 node _T_2395 = eq(UInt<5>(0h13), idx_18) when _T_2395 : node _T_2396 = shl(UInt<5>(0h12), 3) node _T_2397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2396) node _T_2398 = bits(_T_2397, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2398 node _T_2399 = eq(UInt<5>(0h14), idx_18) when _T_2399 : node _T_2400 = shl(UInt<5>(0h12), 3) node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400) node _T_2402 = bits(_T_2401, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2402 node _T_2403 = eq(UInt<5>(0h15), idx_18) when _T_2403 : node _T_2404 = shl(UInt<5>(0h12), 3) node _T_2405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2404) node _T_2406 = bits(_T_2405, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2406 node _T_2407 = eq(UInt<5>(0h16), idx_18) when _T_2407 : node _T_2408 = shl(UInt<5>(0h12), 3) node _T_2409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2408) node _T_2410 = bits(_T_2409, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2410 node _T_2411 = eq(UInt<5>(0h17), idx_18) when _T_2411 : node _T_2412 = shl(UInt<5>(0h12), 3) node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412) node _T_2414 = bits(_T_2413, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2414 node _T_2415 = eq(UInt<5>(0h18), idx_18) when _T_2415 : node _T_2416 = shl(UInt<5>(0h12), 3) node _T_2417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2416) node _T_2418 = bits(_T_2417, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2418 node _T_2419 = eq(UInt<5>(0h19), idx_18) when _T_2419 : node _T_2420 = shl(UInt<5>(0h12), 3) node _T_2421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2420) node _T_2422 = bits(_T_2421, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2422 node _T_2423 = eq(UInt<5>(0h1a), idx_18) when _T_2423 : node _T_2424 = shl(UInt<5>(0h12), 3) node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424) node _T_2426 = bits(_T_2425, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2426 node _T_2427 = eq(UInt<5>(0h1b), idx_18) when _T_2427 : node _T_2428 = shl(UInt<5>(0h12), 3) node _T_2429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2428) node _T_2430 = bits(_T_2429, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2430 node _T_2431 = eq(UInt<5>(0h1c), idx_18) when _T_2431 : node _T_2432 = shl(UInt<5>(0h12), 3) node _T_2433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2432) node _T_2434 = bits(_T_2433, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2434 node _T_2435 = eq(UInt<5>(0h1d), idx_18) when _T_2435 : node _T_2436 = shl(UInt<5>(0h12), 3) node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436) node _T_2438 = bits(_T_2437, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2438 node _T_2439 = eq(UInt<5>(0h1e), idx_18) when _T_2439 : node _T_2440 = shl(UInt<5>(0h12), 3) node _T_2441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2440) node _T_2442 = bits(_T_2441, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2442 node _T_2443 = eq(UInt<5>(0h1f), idx_18) when _T_2443 : node _T_2444 = shl(UInt<5>(0h12), 3) node _T_2445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2444) node _T_2446 = bits(_T_2445, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2446 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_2447 = eq(UInt<1>(0h0), idx_19) when _T_2447 : node _T_2448 = shl(UInt<5>(0h13), 3) node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448) node _T_2450 = bits(_T_2449, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2450 node _T_2451 = eq(UInt<1>(0h1), idx_19) when _T_2451 : node _T_2452 = shl(UInt<5>(0h13), 3) node _T_2453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2452) node _T_2454 = bits(_T_2453, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2454 node _T_2455 = eq(UInt<2>(0h2), idx_19) when _T_2455 : node _T_2456 = shl(UInt<5>(0h13), 3) node _T_2457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2456) node _T_2458 = bits(_T_2457, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2458 node _T_2459 = eq(UInt<2>(0h3), idx_19) when _T_2459 : node _T_2460 = shl(UInt<5>(0h13), 3) node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460) node _T_2462 = bits(_T_2461, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2462 node _T_2463 = eq(UInt<3>(0h4), idx_19) when _T_2463 : node _T_2464 = shl(UInt<5>(0h13), 3) node _T_2465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2464) node _T_2466 = bits(_T_2465, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2466 node _T_2467 = eq(UInt<3>(0h5), idx_19) when _T_2467 : node _T_2468 = shl(UInt<5>(0h13), 3) node _T_2469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2468) node _T_2470 = bits(_T_2469, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2470 node _T_2471 = eq(UInt<3>(0h6), idx_19) when _T_2471 : node _T_2472 = shl(UInt<5>(0h13), 3) node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472) node _T_2474 = bits(_T_2473, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2474 node _T_2475 = eq(UInt<3>(0h7), idx_19) when _T_2475 : node _T_2476 = shl(UInt<5>(0h13), 3) node _T_2477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2476) node _T_2478 = bits(_T_2477, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2478 node _T_2479 = eq(UInt<4>(0h8), idx_19) when _T_2479 : node _T_2480 = shl(UInt<5>(0h13), 3) node _T_2481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2480) node _T_2482 = bits(_T_2481, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2482 node _T_2483 = eq(UInt<4>(0h9), idx_19) when _T_2483 : node _T_2484 = shl(UInt<5>(0h13), 3) node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484) node _T_2486 = bits(_T_2485, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2486 node _T_2487 = eq(UInt<4>(0ha), idx_19) when _T_2487 : node _T_2488 = shl(UInt<5>(0h13), 3) node _T_2489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2488) node _T_2490 = bits(_T_2489, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2490 node _T_2491 = eq(UInt<4>(0hb), idx_19) when _T_2491 : node _T_2492 = shl(UInt<5>(0h13), 3) node _T_2493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2492) node _T_2494 = bits(_T_2493, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2494 node _T_2495 = eq(UInt<4>(0hc), idx_19) when _T_2495 : node _T_2496 = shl(UInt<5>(0h13), 3) node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496) node _T_2498 = bits(_T_2497, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2498 node _T_2499 = eq(UInt<4>(0hd), idx_19) when _T_2499 : node _T_2500 = shl(UInt<5>(0h13), 3) node _T_2501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2500) node _T_2502 = bits(_T_2501, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2502 node _T_2503 = eq(UInt<4>(0he), idx_19) when _T_2503 : node _T_2504 = shl(UInt<5>(0h13), 3) node _T_2505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2504) node _T_2506 = bits(_T_2505, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2506 node _T_2507 = eq(UInt<4>(0hf), idx_19) when _T_2507 : node _T_2508 = shl(UInt<5>(0h13), 3) node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508) node _T_2510 = bits(_T_2509, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2510 node _T_2511 = eq(UInt<5>(0h10), idx_19) when _T_2511 : node _T_2512 = shl(UInt<5>(0h13), 3) node _T_2513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2512) node _T_2514 = bits(_T_2513, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2514 node _T_2515 = eq(UInt<5>(0h11), idx_19) when _T_2515 : node _T_2516 = shl(UInt<5>(0h13), 3) node _T_2517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2516) node _T_2518 = bits(_T_2517, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2518 node _T_2519 = eq(UInt<5>(0h12), idx_19) when _T_2519 : node _T_2520 = shl(UInt<5>(0h13), 3) node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520) node _T_2522 = bits(_T_2521, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2522 node _T_2523 = eq(UInt<5>(0h13), idx_19) when _T_2523 : node _T_2524 = shl(UInt<5>(0h13), 3) node _T_2525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2524) node _T_2526 = bits(_T_2525, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2526 node _T_2527 = eq(UInt<5>(0h14), idx_19) when _T_2527 : node _T_2528 = shl(UInt<5>(0h13), 3) node _T_2529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2528) node _T_2530 = bits(_T_2529, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2530 node _T_2531 = eq(UInt<5>(0h15), idx_19) when _T_2531 : node _T_2532 = shl(UInt<5>(0h13), 3) node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532) node _T_2534 = bits(_T_2533, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2534 node _T_2535 = eq(UInt<5>(0h16), idx_19) when _T_2535 : node _T_2536 = shl(UInt<5>(0h13), 3) node _T_2537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2536) node _T_2538 = bits(_T_2537, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2538 node _T_2539 = eq(UInt<5>(0h17), idx_19) when _T_2539 : node _T_2540 = shl(UInt<5>(0h13), 3) node _T_2541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2540) node _T_2542 = bits(_T_2541, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2542 node _T_2543 = eq(UInt<5>(0h18), idx_19) when _T_2543 : node _T_2544 = shl(UInt<5>(0h13), 3) node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544) node _T_2546 = bits(_T_2545, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2546 node _T_2547 = eq(UInt<5>(0h19), idx_19) when _T_2547 : node _T_2548 = shl(UInt<5>(0h13), 3) node _T_2549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2548) node _T_2550 = bits(_T_2549, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2550 node _T_2551 = eq(UInt<5>(0h1a), idx_19) when _T_2551 : node _T_2552 = shl(UInt<5>(0h13), 3) node _T_2553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2552) node _T_2554 = bits(_T_2553, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2554 node _T_2555 = eq(UInt<5>(0h1b), idx_19) when _T_2555 : node _T_2556 = shl(UInt<5>(0h13), 3) node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556) node _T_2558 = bits(_T_2557, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2558 node _T_2559 = eq(UInt<5>(0h1c), idx_19) when _T_2559 : node _T_2560 = shl(UInt<5>(0h13), 3) node _T_2561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2560) node _T_2562 = bits(_T_2561, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2562 node _T_2563 = eq(UInt<5>(0h1d), idx_19) when _T_2563 : node _T_2564 = shl(UInt<5>(0h13), 3) node _T_2565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2564) node _T_2566 = bits(_T_2565, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2566 node _T_2567 = eq(UInt<5>(0h1e), idx_19) when _T_2567 : node _T_2568 = shl(UInt<5>(0h13), 3) node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568) node _T_2570 = bits(_T_2569, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2570 node _T_2571 = eq(UInt<5>(0h1f), idx_19) when _T_2571 : node _T_2572 = shl(UInt<5>(0h13), 3) node _T_2573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2572) node _T_2574 = bits(_T_2573, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2574 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_2575 = eq(UInt<1>(0h0), idx_20) when _T_2575 : node _T_2576 = shl(UInt<5>(0h14), 3) node _T_2577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2576) node _T_2578 = bits(_T_2577, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2578 node _T_2579 = eq(UInt<1>(0h1), idx_20) when _T_2579 : node _T_2580 = shl(UInt<5>(0h14), 3) node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580) node _T_2582 = bits(_T_2581, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2582 node _T_2583 = eq(UInt<2>(0h2), idx_20) when _T_2583 : node _T_2584 = shl(UInt<5>(0h14), 3) node _T_2585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2584) node _T_2586 = bits(_T_2585, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2586 node _T_2587 = eq(UInt<2>(0h3), idx_20) when _T_2587 : node _T_2588 = shl(UInt<5>(0h14), 3) node _T_2589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2588) node _T_2590 = bits(_T_2589, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2590 node _T_2591 = eq(UInt<3>(0h4), idx_20) when _T_2591 : node _T_2592 = shl(UInt<5>(0h14), 3) node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592) node _T_2594 = bits(_T_2593, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2594 node _T_2595 = eq(UInt<3>(0h5), idx_20) when _T_2595 : node _T_2596 = shl(UInt<5>(0h14), 3) node _T_2597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2596) node _T_2598 = bits(_T_2597, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2598 node _T_2599 = eq(UInt<3>(0h6), idx_20) when _T_2599 : node _T_2600 = shl(UInt<5>(0h14), 3) node _T_2601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2600) node _T_2602 = bits(_T_2601, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2602 node _T_2603 = eq(UInt<3>(0h7), idx_20) when _T_2603 : node _T_2604 = shl(UInt<5>(0h14), 3) node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604) node _T_2606 = bits(_T_2605, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2606 node _T_2607 = eq(UInt<4>(0h8), idx_20) when _T_2607 : node _T_2608 = shl(UInt<5>(0h14), 3) node _T_2609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2608) node _T_2610 = bits(_T_2609, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2610 node _T_2611 = eq(UInt<4>(0h9), idx_20) when _T_2611 : node _T_2612 = shl(UInt<5>(0h14), 3) node _T_2613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2612) node _T_2614 = bits(_T_2613, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2614 node _T_2615 = eq(UInt<4>(0ha), idx_20) when _T_2615 : node _T_2616 = shl(UInt<5>(0h14), 3) node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616) node _T_2618 = bits(_T_2617, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2618 node _T_2619 = eq(UInt<4>(0hb), idx_20) when _T_2619 : node _T_2620 = shl(UInt<5>(0h14), 3) node _T_2621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2620) node _T_2622 = bits(_T_2621, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2622 node _T_2623 = eq(UInt<4>(0hc), idx_20) when _T_2623 : node _T_2624 = shl(UInt<5>(0h14), 3) node _T_2625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2624) node _T_2626 = bits(_T_2625, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2626 node _T_2627 = eq(UInt<4>(0hd), idx_20) when _T_2627 : node _T_2628 = shl(UInt<5>(0h14), 3) node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628) node _T_2630 = bits(_T_2629, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2630 node _T_2631 = eq(UInt<4>(0he), idx_20) when _T_2631 : node _T_2632 = shl(UInt<5>(0h14), 3) node _T_2633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2632) node _T_2634 = bits(_T_2633, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2634 node _T_2635 = eq(UInt<4>(0hf), idx_20) when _T_2635 : node _T_2636 = shl(UInt<5>(0h14), 3) node _T_2637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2636) node _T_2638 = bits(_T_2637, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2638 node _T_2639 = eq(UInt<5>(0h10), idx_20) when _T_2639 : node _T_2640 = shl(UInt<5>(0h14), 3) node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640) node _T_2642 = bits(_T_2641, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2642 node _T_2643 = eq(UInt<5>(0h11), idx_20) when _T_2643 : node _T_2644 = shl(UInt<5>(0h14), 3) node _T_2645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2644) node _T_2646 = bits(_T_2645, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2646 node _T_2647 = eq(UInt<5>(0h12), idx_20) when _T_2647 : node _T_2648 = shl(UInt<5>(0h14), 3) node _T_2649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2648) node _T_2650 = bits(_T_2649, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2650 node _T_2651 = eq(UInt<5>(0h13), idx_20) when _T_2651 : node _T_2652 = shl(UInt<5>(0h14), 3) node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652) node _T_2654 = bits(_T_2653, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2654 node _T_2655 = eq(UInt<5>(0h14), idx_20) when _T_2655 : node _T_2656 = shl(UInt<5>(0h14), 3) node _T_2657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2656) node _T_2658 = bits(_T_2657, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2658 node _T_2659 = eq(UInt<5>(0h15), idx_20) when _T_2659 : node _T_2660 = shl(UInt<5>(0h14), 3) node _T_2661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2660) node _T_2662 = bits(_T_2661, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2662 node _T_2663 = eq(UInt<5>(0h16), idx_20) when _T_2663 : node _T_2664 = shl(UInt<5>(0h14), 3) node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664) node _T_2666 = bits(_T_2665, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2666 node _T_2667 = eq(UInt<5>(0h17), idx_20) when _T_2667 : node _T_2668 = shl(UInt<5>(0h14), 3) node _T_2669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2668) node _T_2670 = bits(_T_2669, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2670 node _T_2671 = eq(UInt<5>(0h18), idx_20) when _T_2671 : node _T_2672 = shl(UInt<5>(0h14), 3) node _T_2673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2672) node _T_2674 = bits(_T_2673, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2674 node _T_2675 = eq(UInt<5>(0h19), idx_20) when _T_2675 : node _T_2676 = shl(UInt<5>(0h14), 3) node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676) node _T_2678 = bits(_T_2677, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2678 node _T_2679 = eq(UInt<5>(0h1a), idx_20) when _T_2679 : node _T_2680 = shl(UInt<5>(0h14), 3) node _T_2681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2680) node _T_2682 = bits(_T_2681, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2682 node _T_2683 = eq(UInt<5>(0h1b), idx_20) when _T_2683 : node _T_2684 = shl(UInt<5>(0h14), 3) node _T_2685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2684) node _T_2686 = bits(_T_2685, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2686 node _T_2687 = eq(UInt<5>(0h1c), idx_20) when _T_2687 : node _T_2688 = shl(UInt<5>(0h14), 3) node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688) node _T_2690 = bits(_T_2689, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2690 node _T_2691 = eq(UInt<5>(0h1d), idx_20) when _T_2691 : node _T_2692 = shl(UInt<5>(0h14), 3) node _T_2693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2692) node _T_2694 = bits(_T_2693, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2694 node _T_2695 = eq(UInt<5>(0h1e), idx_20) when _T_2695 : node _T_2696 = shl(UInt<5>(0h14), 3) node _T_2697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2696) node _T_2698 = bits(_T_2697, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2698 node _T_2699 = eq(UInt<5>(0h1f), idx_20) when _T_2699 : node _T_2700 = shl(UInt<5>(0h14), 3) node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700) node _T_2702 = bits(_T_2701, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2702 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_2703 = eq(UInt<1>(0h0), idx_21) when _T_2703 : node _T_2704 = shl(UInt<5>(0h15), 3) node _T_2705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2704) node _T_2706 = bits(_T_2705, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2706 node _T_2707 = eq(UInt<1>(0h1), idx_21) when _T_2707 : node _T_2708 = shl(UInt<5>(0h15), 3) node _T_2709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2708) node _T_2710 = bits(_T_2709, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2710 node _T_2711 = eq(UInt<2>(0h2), idx_21) when _T_2711 : node _T_2712 = shl(UInt<5>(0h15), 3) node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712) node _T_2714 = bits(_T_2713, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2714 node _T_2715 = eq(UInt<2>(0h3), idx_21) when _T_2715 : node _T_2716 = shl(UInt<5>(0h15), 3) node _T_2717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2716) node _T_2718 = bits(_T_2717, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2718 node _T_2719 = eq(UInt<3>(0h4), idx_21) when _T_2719 : node _T_2720 = shl(UInt<5>(0h15), 3) node _T_2721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2720) node _T_2722 = bits(_T_2721, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2722 node _T_2723 = eq(UInt<3>(0h5), idx_21) when _T_2723 : node _T_2724 = shl(UInt<5>(0h15), 3) node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724) node _T_2726 = bits(_T_2725, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2726 node _T_2727 = eq(UInt<3>(0h6), idx_21) when _T_2727 : node _T_2728 = shl(UInt<5>(0h15), 3) node _T_2729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2728) node _T_2730 = bits(_T_2729, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2730 node _T_2731 = eq(UInt<3>(0h7), idx_21) when _T_2731 : node _T_2732 = shl(UInt<5>(0h15), 3) node _T_2733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2732) node _T_2734 = bits(_T_2733, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2734 node _T_2735 = eq(UInt<4>(0h8), idx_21) when _T_2735 : node _T_2736 = shl(UInt<5>(0h15), 3) node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736) node _T_2738 = bits(_T_2737, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2738 node _T_2739 = eq(UInt<4>(0h9), idx_21) when _T_2739 : node _T_2740 = shl(UInt<5>(0h15), 3) node _T_2741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2740) node _T_2742 = bits(_T_2741, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2742 node _T_2743 = eq(UInt<4>(0ha), idx_21) when _T_2743 : node _T_2744 = shl(UInt<5>(0h15), 3) node _T_2745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2744) node _T_2746 = bits(_T_2745, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2746 node _T_2747 = eq(UInt<4>(0hb), idx_21) when _T_2747 : node _T_2748 = shl(UInt<5>(0h15), 3) node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748) node _T_2750 = bits(_T_2749, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2750 node _T_2751 = eq(UInt<4>(0hc), idx_21) when _T_2751 : node _T_2752 = shl(UInt<5>(0h15), 3) node _T_2753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2752) node _T_2754 = bits(_T_2753, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2754 node _T_2755 = eq(UInt<4>(0hd), idx_21) when _T_2755 : node _T_2756 = shl(UInt<5>(0h15), 3) node _T_2757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2756) node _T_2758 = bits(_T_2757, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2758 node _T_2759 = eq(UInt<4>(0he), idx_21) when _T_2759 : node _T_2760 = shl(UInt<5>(0h15), 3) node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760) node _T_2762 = bits(_T_2761, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2762 node _T_2763 = eq(UInt<4>(0hf), idx_21) when _T_2763 : node _T_2764 = shl(UInt<5>(0h15), 3) node _T_2765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2764) node _T_2766 = bits(_T_2765, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2766 node _T_2767 = eq(UInt<5>(0h10), idx_21) when _T_2767 : node _T_2768 = shl(UInt<5>(0h15), 3) node _T_2769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2768) node _T_2770 = bits(_T_2769, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2770 node _T_2771 = eq(UInt<5>(0h11), idx_21) when _T_2771 : node _T_2772 = shl(UInt<5>(0h15), 3) node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772) node _T_2774 = bits(_T_2773, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2774 node _T_2775 = eq(UInt<5>(0h12), idx_21) when _T_2775 : node _T_2776 = shl(UInt<5>(0h15), 3) node _T_2777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2776) node _T_2778 = bits(_T_2777, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2778 node _T_2779 = eq(UInt<5>(0h13), idx_21) when _T_2779 : node _T_2780 = shl(UInt<5>(0h15), 3) node _T_2781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2780) node _T_2782 = bits(_T_2781, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2782 node _T_2783 = eq(UInt<5>(0h14), idx_21) when _T_2783 : node _T_2784 = shl(UInt<5>(0h15), 3) node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784) node _T_2786 = bits(_T_2785, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2786 node _T_2787 = eq(UInt<5>(0h15), idx_21) when _T_2787 : node _T_2788 = shl(UInt<5>(0h15), 3) node _T_2789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2788) node _T_2790 = bits(_T_2789, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2790 node _T_2791 = eq(UInt<5>(0h16), idx_21) when _T_2791 : node _T_2792 = shl(UInt<5>(0h15), 3) node _T_2793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2792) node _T_2794 = bits(_T_2793, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2794 node _T_2795 = eq(UInt<5>(0h17), idx_21) when _T_2795 : node _T_2796 = shl(UInt<5>(0h15), 3) node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796) node _T_2798 = bits(_T_2797, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2798 node _T_2799 = eq(UInt<5>(0h18), idx_21) when _T_2799 : node _T_2800 = shl(UInt<5>(0h15), 3) node _T_2801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2800) node _T_2802 = bits(_T_2801, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2802 node _T_2803 = eq(UInt<5>(0h19), idx_21) when _T_2803 : node _T_2804 = shl(UInt<5>(0h15), 3) node _T_2805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2804) node _T_2806 = bits(_T_2805, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2806 node _T_2807 = eq(UInt<5>(0h1a), idx_21) when _T_2807 : node _T_2808 = shl(UInt<5>(0h15), 3) node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808) node _T_2810 = bits(_T_2809, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2810 node _T_2811 = eq(UInt<5>(0h1b), idx_21) when _T_2811 : node _T_2812 = shl(UInt<5>(0h15), 3) node _T_2813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2812) node _T_2814 = bits(_T_2813, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2814 node _T_2815 = eq(UInt<5>(0h1c), idx_21) when _T_2815 : node _T_2816 = shl(UInt<5>(0h15), 3) node _T_2817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2816) node _T_2818 = bits(_T_2817, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2818 node _T_2819 = eq(UInt<5>(0h1d), idx_21) when _T_2819 : node _T_2820 = shl(UInt<5>(0h15), 3) node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820) node _T_2822 = bits(_T_2821, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2822 node _T_2823 = eq(UInt<5>(0h1e), idx_21) when _T_2823 : node _T_2824 = shl(UInt<5>(0h15), 3) node _T_2825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2824) node _T_2826 = bits(_T_2825, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2826 node _T_2827 = eq(UInt<5>(0h1f), idx_21) when _T_2827 : node _T_2828 = shl(UInt<5>(0h15), 3) node _T_2829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2828) node _T_2830 = bits(_T_2829, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2830 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_2831 = eq(UInt<1>(0h0), idx_22) when _T_2831 : node _T_2832 = shl(UInt<5>(0h16), 3) node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832) node _T_2834 = bits(_T_2833, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2834 node _T_2835 = eq(UInt<1>(0h1), idx_22) when _T_2835 : node _T_2836 = shl(UInt<5>(0h16), 3) node _T_2837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2836) node _T_2838 = bits(_T_2837, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2838 node _T_2839 = eq(UInt<2>(0h2), idx_22) when _T_2839 : node _T_2840 = shl(UInt<5>(0h16), 3) node _T_2841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2840) node _T_2842 = bits(_T_2841, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2842 node _T_2843 = eq(UInt<2>(0h3), idx_22) when _T_2843 : node _T_2844 = shl(UInt<5>(0h16), 3) node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844) node _T_2846 = bits(_T_2845, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2846 node _T_2847 = eq(UInt<3>(0h4), idx_22) when _T_2847 : node _T_2848 = shl(UInt<5>(0h16), 3) node _T_2849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2848) node _T_2850 = bits(_T_2849, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2850 node _T_2851 = eq(UInt<3>(0h5), idx_22) when _T_2851 : node _T_2852 = shl(UInt<5>(0h16), 3) node _T_2853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2852) node _T_2854 = bits(_T_2853, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2854 node _T_2855 = eq(UInt<3>(0h6), idx_22) when _T_2855 : node _T_2856 = shl(UInt<5>(0h16), 3) node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856) node _T_2858 = bits(_T_2857, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2858 node _T_2859 = eq(UInt<3>(0h7), idx_22) when _T_2859 : node _T_2860 = shl(UInt<5>(0h16), 3) node _T_2861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2860) node _T_2862 = bits(_T_2861, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2862 node _T_2863 = eq(UInt<4>(0h8), idx_22) when _T_2863 : node _T_2864 = shl(UInt<5>(0h16), 3) node _T_2865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2864) node _T_2866 = bits(_T_2865, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2866 node _T_2867 = eq(UInt<4>(0h9), idx_22) when _T_2867 : node _T_2868 = shl(UInt<5>(0h16), 3) node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868) node _T_2870 = bits(_T_2869, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2870 node _T_2871 = eq(UInt<4>(0ha), idx_22) when _T_2871 : node _T_2872 = shl(UInt<5>(0h16), 3) node _T_2873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2872) node _T_2874 = bits(_T_2873, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2874 node _T_2875 = eq(UInt<4>(0hb), idx_22) when _T_2875 : node _T_2876 = shl(UInt<5>(0h16), 3) node _T_2877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2876) node _T_2878 = bits(_T_2877, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2878 node _T_2879 = eq(UInt<4>(0hc), idx_22) when _T_2879 : node _T_2880 = shl(UInt<5>(0h16), 3) node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880) node _T_2882 = bits(_T_2881, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2882 node _T_2883 = eq(UInt<4>(0hd), idx_22) when _T_2883 : node _T_2884 = shl(UInt<5>(0h16), 3) node _T_2885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2884) node _T_2886 = bits(_T_2885, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2886 node _T_2887 = eq(UInt<4>(0he), idx_22) when _T_2887 : node _T_2888 = shl(UInt<5>(0h16), 3) node _T_2889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2888) node _T_2890 = bits(_T_2889, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2890 node _T_2891 = eq(UInt<4>(0hf), idx_22) when _T_2891 : node _T_2892 = shl(UInt<5>(0h16), 3) node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892) node _T_2894 = bits(_T_2893, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2894 node _T_2895 = eq(UInt<5>(0h10), idx_22) when _T_2895 : node _T_2896 = shl(UInt<5>(0h16), 3) node _T_2897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2896) node _T_2898 = bits(_T_2897, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2898 node _T_2899 = eq(UInt<5>(0h11), idx_22) when _T_2899 : node _T_2900 = shl(UInt<5>(0h16), 3) node _T_2901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2900) node _T_2902 = bits(_T_2901, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2902 node _T_2903 = eq(UInt<5>(0h12), idx_22) when _T_2903 : node _T_2904 = shl(UInt<5>(0h16), 3) node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904) node _T_2906 = bits(_T_2905, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2906 node _T_2907 = eq(UInt<5>(0h13), idx_22) when _T_2907 : node _T_2908 = shl(UInt<5>(0h16), 3) node _T_2909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2908) node _T_2910 = bits(_T_2909, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2910 node _T_2911 = eq(UInt<5>(0h14), idx_22) when _T_2911 : node _T_2912 = shl(UInt<5>(0h16), 3) node _T_2913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2912) node _T_2914 = bits(_T_2913, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2914 node _T_2915 = eq(UInt<5>(0h15), idx_22) when _T_2915 : node _T_2916 = shl(UInt<5>(0h16), 3) node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916) node _T_2918 = bits(_T_2917, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2918 node _T_2919 = eq(UInt<5>(0h16), idx_22) when _T_2919 : node _T_2920 = shl(UInt<5>(0h16), 3) node _T_2921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2920) node _T_2922 = bits(_T_2921, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2922 node _T_2923 = eq(UInt<5>(0h17), idx_22) when _T_2923 : node _T_2924 = shl(UInt<5>(0h16), 3) node _T_2925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2924) node _T_2926 = bits(_T_2925, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2926 node _T_2927 = eq(UInt<5>(0h18), idx_22) when _T_2927 : node _T_2928 = shl(UInt<5>(0h16), 3) node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928) node _T_2930 = bits(_T_2929, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2930 node _T_2931 = eq(UInt<5>(0h19), idx_22) when _T_2931 : node _T_2932 = shl(UInt<5>(0h16), 3) node _T_2933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2932) node _T_2934 = bits(_T_2933, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2934 node _T_2935 = eq(UInt<5>(0h1a), idx_22) when _T_2935 : node _T_2936 = shl(UInt<5>(0h16), 3) node _T_2937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2936) node _T_2938 = bits(_T_2937, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2938 node _T_2939 = eq(UInt<5>(0h1b), idx_22) when _T_2939 : node _T_2940 = shl(UInt<5>(0h16), 3) node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940) node _T_2942 = bits(_T_2941, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2942 node _T_2943 = eq(UInt<5>(0h1c), idx_22) when _T_2943 : node _T_2944 = shl(UInt<5>(0h16), 3) node _T_2945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2944) node _T_2946 = bits(_T_2945, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2946 node _T_2947 = eq(UInt<5>(0h1d), idx_22) when _T_2947 : node _T_2948 = shl(UInt<5>(0h16), 3) node _T_2949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2948) node _T_2950 = bits(_T_2949, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2950 node _T_2951 = eq(UInt<5>(0h1e), idx_22) when _T_2951 : node _T_2952 = shl(UInt<5>(0h16), 3) node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952) node _T_2954 = bits(_T_2953, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2954 node _T_2955 = eq(UInt<5>(0h1f), idx_22) when _T_2955 : node _T_2956 = shl(UInt<5>(0h16), 3) node _T_2957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2956) node _T_2958 = bits(_T_2957, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2958 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_2959 = eq(UInt<1>(0h0), idx_23) when _T_2959 : node _T_2960 = shl(UInt<5>(0h17), 3) node _T_2961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2960) node _T_2962 = bits(_T_2961, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2962 node _T_2963 = eq(UInt<1>(0h1), idx_23) when _T_2963 : node _T_2964 = shl(UInt<5>(0h17), 3) node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964) node _T_2966 = bits(_T_2965, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2966 node _T_2967 = eq(UInt<2>(0h2), idx_23) when _T_2967 : node _T_2968 = shl(UInt<5>(0h17), 3) node _T_2969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2968) node _T_2970 = bits(_T_2969, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2970 node _T_2971 = eq(UInt<2>(0h3), idx_23) when _T_2971 : node _T_2972 = shl(UInt<5>(0h17), 3) node _T_2973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2972) node _T_2974 = bits(_T_2973, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2974 node _T_2975 = eq(UInt<3>(0h4), idx_23) when _T_2975 : node _T_2976 = shl(UInt<5>(0h17), 3) node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976) node _T_2978 = bits(_T_2977, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2978 node _T_2979 = eq(UInt<3>(0h5), idx_23) when _T_2979 : node _T_2980 = shl(UInt<5>(0h17), 3) node _T_2981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2980) node _T_2982 = bits(_T_2981, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2982 node _T_2983 = eq(UInt<3>(0h6), idx_23) when _T_2983 : node _T_2984 = shl(UInt<5>(0h17), 3) node _T_2985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2984) node _T_2986 = bits(_T_2985, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2986 node _T_2987 = eq(UInt<3>(0h7), idx_23) when _T_2987 : node _T_2988 = shl(UInt<5>(0h17), 3) node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988) node _T_2990 = bits(_T_2989, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2990 node _T_2991 = eq(UInt<4>(0h8), idx_23) when _T_2991 : node _T_2992 = shl(UInt<5>(0h17), 3) node _T_2993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2992) node _T_2994 = bits(_T_2993, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2994 node _T_2995 = eq(UInt<4>(0h9), idx_23) when _T_2995 : node _T_2996 = shl(UInt<5>(0h17), 3) node _T_2997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2996) node _T_2998 = bits(_T_2997, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2998 node _T_2999 = eq(UInt<4>(0ha), idx_23) when _T_2999 : node _T_3000 = shl(UInt<5>(0h17), 3) node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000) node _T_3002 = bits(_T_3001, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3002 node _T_3003 = eq(UInt<4>(0hb), idx_23) when _T_3003 : node _T_3004 = shl(UInt<5>(0h17), 3) node _T_3005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3004) node _T_3006 = bits(_T_3005, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3006 node _T_3007 = eq(UInt<4>(0hc), idx_23) when _T_3007 : node _T_3008 = shl(UInt<5>(0h17), 3) node _T_3009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3008) node _T_3010 = bits(_T_3009, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3010 node _T_3011 = eq(UInt<4>(0hd), idx_23) when _T_3011 : node _T_3012 = shl(UInt<5>(0h17), 3) node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012) node _T_3014 = bits(_T_3013, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3014 node _T_3015 = eq(UInt<4>(0he), idx_23) when _T_3015 : node _T_3016 = shl(UInt<5>(0h17), 3) node _T_3017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3016) node _T_3018 = bits(_T_3017, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3018 node _T_3019 = eq(UInt<4>(0hf), idx_23) when _T_3019 : node _T_3020 = shl(UInt<5>(0h17), 3) node _T_3021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3020) node _T_3022 = bits(_T_3021, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3022 node _T_3023 = eq(UInt<5>(0h10), idx_23) when _T_3023 : node _T_3024 = shl(UInt<5>(0h17), 3) node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024) node _T_3026 = bits(_T_3025, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3026 node _T_3027 = eq(UInt<5>(0h11), idx_23) when _T_3027 : node _T_3028 = shl(UInt<5>(0h17), 3) node _T_3029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3028) node _T_3030 = bits(_T_3029, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3030 node _T_3031 = eq(UInt<5>(0h12), idx_23) when _T_3031 : node _T_3032 = shl(UInt<5>(0h17), 3) node _T_3033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3032) node _T_3034 = bits(_T_3033, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3034 node _T_3035 = eq(UInt<5>(0h13), idx_23) when _T_3035 : node _T_3036 = shl(UInt<5>(0h17), 3) node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036) node _T_3038 = bits(_T_3037, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3038 node _T_3039 = eq(UInt<5>(0h14), idx_23) when _T_3039 : node _T_3040 = shl(UInt<5>(0h17), 3) node _T_3041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3040) node _T_3042 = bits(_T_3041, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3042 node _T_3043 = eq(UInt<5>(0h15), idx_23) when _T_3043 : node _T_3044 = shl(UInt<5>(0h17), 3) node _T_3045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3044) node _T_3046 = bits(_T_3045, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3046 node _T_3047 = eq(UInt<5>(0h16), idx_23) when _T_3047 : node _T_3048 = shl(UInt<5>(0h17), 3) node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048) node _T_3050 = bits(_T_3049, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3050 node _T_3051 = eq(UInt<5>(0h17), idx_23) when _T_3051 : node _T_3052 = shl(UInt<5>(0h17), 3) node _T_3053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3052) node _T_3054 = bits(_T_3053, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3054 node _T_3055 = eq(UInt<5>(0h18), idx_23) when _T_3055 : node _T_3056 = shl(UInt<5>(0h17), 3) node _T_3057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3056) node _T_3058 = bits(_T_3057, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3058 node _T_3059 = eq(UInt<5>(0h19), idx_23) when _T_3059 : node _T_3060 = shl(UInt<5>(0h17), 3) node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060) node _T_3062 = bits(_T_3061, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3062 node _T_3063 = eq(UInt<5>(0h1a), idx_23) when _T_3063 : node _T_3064 = shl(UInt<5>(0h17), 3) node _T_3065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3064) node _T_3066 = bits(_T_3065, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3066 node _T_3067 = eq(UInt<5>(0h1b), idx_23) when _T_3067 : node _T_3068 = shl(UInt<5>(0h17), 3) node _T_3069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3068) node _T_3070 = bits(_T_3069, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3070 node _T_3071 = eq(UInt<5>(0h1c), idx_23) when _T_3071 : node _T_3072 = shl(UInt<5>(0h17), 3) node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072) node _T_3074 = bits(_T_3073, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3074 node _T_3075 = eq(UInt<5>(0h1d), idx_23) when _T_3075 : node _T_3076 = shl(UInt<5>(0h17), 3) node _T_3077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3076) node _T_3078 = bits(_T_3077, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3078 node _T_3079 = eq(UInt<5>(0h1e), idx_23) when _T_3079 : node _T_3080 = shl(UInt<5>(0h17), 3) node _T_3081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3080) node _T_3082 = bits(_T_3081, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3082 node _T_3083 = eq(UInt<5>(0h1f), idx_23) when _T_3083 : node _T_3084 = shl(UInt<5>(0h17), 3) node _T_3085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3084) node _T_3086 = bits(_T_3085, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3086 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_3087 = eq(UInt<1>(0h0), idx_24) when _T_3087 : node _T_3088 = shl(UInt<5>(0h18), 3) node _T_3089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3088) node _T_3090 = bits(_T_3089, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3090 node _T_3091 = eq(UInt<1>(0h1), idx_24) when _T_3091 : node _T_3092 = shl(UInt<5>(0h18), 3) node _T_3093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3092) node _T_3094 = bits(_T_3093, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3094 node _T_3095 = eq(UInt<2>(0h2), idx_24) when _T_3095 : node _T_3096 = shl(UInt<5>(0h18), 3) node _T_3097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3096) node _T_3098 = bits(_T_3097, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3098 node _T_3099 = eq(UInt<2>(0h3), idx_24) when _T_3099 : node _T_3100 = shl(UInt<5>(0h18), 3) node _T_3101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3100) node _T_3102 = bits(_T_3101, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3102 node _T_3103 = eq(UInt<3>(0h4), idx_24) when _T_3103 : node _T_3104 = shl(UInt<5>(0h18), 3) node _T_3105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3104) node _T_3106 = bits(_T_3105, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3106 node _T_3107 = eq(UInt<3>(0h5), idx_24) when _T_3107 : node _T_3108 = shl(UInt<5>(0h18), 3) node _T_3109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3108) node _T_3110 = bits(_T_3109, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3110 node _T_3111 = eq(UInt<3>(0h6), idx_24) when _T_3111 : node _T_3112 = shl(UInt<5>(0h18), 3) node _T_3113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3112) node _T_3114 = bits(_T_3113, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3114 node _T_3115 = eq(UInt<3>(0h7), idx_24) when _T_3115 : node _T_3116 = shl(UInt<5>(0h18), 3) node _T_3117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3116) node _T_3118 = bits(_T_3117, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3118 node _T_3119 = eq(UInt<4>(0h8), idx_24) when _T_3119 : node _T_3120 = shl(UInt<5>(0h18), 3) node _T_3121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3120) node _T_3122 = bits(_T_3121, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3122 node _T_3123 = eq(UInt<4>(0h9), idx_24) when _T_3123 : node _T_3124 = shl(UInt<5>(0h18), 3) node _T_3125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3124) node _T_3126 = bits(_T_3125, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3126 node _T_3127 = eq(UInt<4>(0ha), idx_24) when _T_3127 : node _T_3128 = shl(UInt<5>(0h18), 3) node _T_3129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3128) node _T_3130 = bits(_T_3129, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3130 node _T_3131 = eq(UInt<4>(0hb), idx_24) when _T_3131 : node _T_3132 = shl(UInt<5>(0h18), 3) node _T_3133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3132) node _T_3134 = bits(_T_3133, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3134 node _T_3135 = eq(UInt<4>(0hc), idx_24) when _T_3135 : node _T_3136 = shl(UInt<5>(0h18), 3) node _T_3137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3136) node _T_3138 = bits(_T_3137, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3138 node _T_3139 = eq(UInt<4>(0hd), idx_24) when _T_3139 : node _T_3140 = shl(UInt<5>(0h18), 3) node _T_3141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3140) node _T_3142 = bits(_T_3141, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3142 node _T_3143 = eq(UInt<4>(0he), idx_24) when _T_3143 : node _T_3144 = shl(UInt<5>(0h18), 3) node _T_3145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3144) node _T_3146 = bits(_T_3145, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3146 node _T_3147 = eq(UInt<4>(0hf), idx_24) when _T_3147 : node _T_3148 = shl(UInt<5>(0h18), 3) node _T_3149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3148) node _T_3150 = bits(_T_3149, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3150 node _T_3151 = eq(UInt<5>(0h10), idx_24) when _T_3151 : node _T_3152 = shl(UInt<5>(0h18), 3) node _T_3153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3152) node _T_3154 = bits(_T_3153, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3154 node _T_3155 = eq(UInt<5>(0h11), idx_24) when _T_3155 : node _T_3156 = shl(UInt<5>(0h18), 3) node _T_3157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3156) node _T_3158 = bits(_T_3157, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3158 node _T_3159 = eq(UInt<5>(0h12), idx_24) when _T_3159 : node _T_3160 = shl(UInt<5>(0h18), 3) node _T_3161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3160) node _T_3162 = bits(_T_3161, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3162 node _T_3163 = eq(UInt<5>(0h13), idx_24) when _T_3163 : node _T_3164 = shl(UInt<5>(0h18), 3) node _T_3165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3164) node _T_3166 = bits(_T_3165, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3166 node _T_3167 = eq(UInt<5>(0h14), idx_24) when _T_3167 : node _T_3168 = shl(UInt<5>(0h18), 3) node _T_3169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3168) node _T_3170 = bits(_T_3169, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3170 node _T_3171 = eq(UInt<5>(0h15), idx_24) when _T_3171 : node _T_3172 = shl(UInt<5>(0h18), 3) node _T_3173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3172) node _T_3174 = bits(_T_3173, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3174 node _T_3175 = eq(UInt<5>(0h16), idx_24) when _T_3175 : node _T_3176 = shl(UInt<5>(0h18), 3) node _T_3177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3176) node _T_3178 = bits(_T_3177, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3178 node _T_3179 = eq(UInt<5>(0h17), idx_24) when _T_3179 : node _T_3180 = shl(UInt<5>(0h18), 3) node _T_3181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3180) node _T_3182 = bits(_T_3181, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3182 node _T_3183 = eq(UInt<5>(0h18), idx_24) when _T_3183 : node _T_3184 = shl(UInt<5>(0h18), 3) node _T_3185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3184) node _T_3186 = bits(_T_3185, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3186 node _T_3187 = eq(UInt<5>(0h19), idx_24) when _T_3187 : node _T_3188 = shl(UInt<5>(0h18), 3) node _T_3189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3188) node _T_3190 = bits(_T_3189, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3190 node _T_3191 = eq(UInt<5>(0h1a), idx_24) when _T_3191 : node _T_3192 = shl(UInt<5>(0h18), 3) node _T_3193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3192) node _T_3194 = bits(_T_3193, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3194 node _T_3195 = eq(UInt<5>(0h1b), idx_24) when _T_3195 : node _T_3196 = shl(UInt<5>(0h18), 3) node _T_3197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3196) node _T_3198 = bits(_T_3197, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3198 node _T_3199 = eq(UInt<5>(0h1c), idx_24) when _T_3199 : node _T_3200 = shl(UInt<5>(0h18), 3) node _T_3201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3200) node _T_3202 = bits(_T_3201, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3202 node _T_3203 = eq(UInt<5>(0h1d), idx_24) when _T_3203 : node _T_3204 = shl(UInt<5>(0h18), 3) node _T_3205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3204) node _T_3206 = bits(_T_3205, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3206 node _T_3207 = eq(UInt<5>(0h1e), idx_24) when _T_3207 : node _T_3208 = shl(UInt<5>(0h18), 3) node _T_3209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3208) node _T_3210 = bits(_T_3209, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3210 node _T_3211 = eq(UInt<5>(0h1f), idx_24) when _T_3211 : node _T_3212 = shl(UInt<5>(0h18), 3) node _T_3213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3212) node _T_3214 = bits(_T_3213, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3214 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_3215 = eq(UInt<1>(0h0), idx_25) when _T_3215 : node _T_3216 = shl(UInt<5>(0h19), 3) node _T_3217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3216) node _T_3218 = bits(_T_3217, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3218 node _T_3219 = eq(UInt<1>(0h1), idx_25) when _T_3219 : node _T_3220 = shl(UInt<5>(0h19), 3) node _T_3221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3220) node _T_3222 = bits(_T_3221, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3222 node _T_3223 = eq(UInt<2>(0h2), idx_25) when _T_3223 : node _T_3224 = shl(UInt<5>(0h19), 3) node _T_3225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3224) node _T_3226 = bits(_T_3225, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3226 node _T_3227 = eq(UInt<2>(0h3), idx_25) when _T_3227 : node _T_3228 = shl(UInt<5>(0h19), 3) node _T_3229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3228) node _T_3230 = bits(_T_3229, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3230 node _T_3231 = eq(UInt<3>(0h4), idx_25) when _T_3231 : node _T_3232 = shl(UInt<5>(0h19), 3) node _T_3233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3232) node _T_3234 = bits(_T_3233, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3234 node _T_3235 = eq(UInt<3>(0h5), idx_25) when _T_3235 : node _T_3236 = shl(UInt<5>(0h19), 3) node _T_3237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3236) node _T_3238 = bits(_T_3237, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3238 node _T_3239 = eq(UInt<3>(0h6), idx_25) when _T_3239 : node _T_3240 = shl(UInt<5>(0h19), 3) node _T_3241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3240) node _T_3242 = bits(_T_3241, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3242 node _T_3243 = eq(UInt<3>(0h7), idx_25) when _T_3243 : node _T_3244 = shl(UInt<5>(0h19), 3) node _T_3245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3244) node _T_3246 = bits(_T_3245, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3246 node _T_3247 = eq(UInt<4>(0h8), idx_25) when _T_3247 : node _T_3248 = shl(UInt<5>(0h19), 3) node _T_3249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3248) node _T_3250 = bits(_T_3249, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3250 node _T_3251 = eq(UInt<4>(0h9), idx_25) when _T_3251 : node _T_3252 = shl(UInt<5>(0h19), 3) node _T_3253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3252) node _T_3254 = bits(_T_3253, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3254 node _T_3255 = eq(UInt<4>(0ha), idx_25) when _T_3255 : node _T_3256 = shl(UInt<5>(0h19), 3) node _T_3257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3256) node _T_3258 = bits(_T_3257, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3258 node _T_3259 = eq(UInt<4>(0hb), idx_25) when _T_3259 : node _T_3260 = shl(UInt<5>(0h19), 3) node _T_3261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3260) node _T_3262 = bits(_T_3261, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3262 node _T_3263 = eq(UInt<4>(0hc), idx_25) when _T_3263 : node _T_3264 = shl(UInt<5>(0h19), 3) node _T_3265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3264) node _T_3266 = bits(_T_3265, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3266 node _T_3267 = eq(UInt<4>(0hd), idx_25) when _T_3267 : node _T_3268 = shl(UInt<5>(0h19), 3) node _T_3269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3268) node _T_3270 = bits(_T_3269, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3270 node _T_3271 = eq(UInt<4>(0he), idx_25) when _T_3271 : node _T_3272 = shl(UInt<5>(0h19), 3) node _T_3273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3272) node _T_3274 = bits(_T_3273, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3274 node _T_3275 = eq(UInt<4>(0hf), idx_25) when _T_3275 : node _T_3276 = shl(UInt<5>(0h19), 3) node _T_3277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3276) node _T_3278 = bits(_T_3277, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3278 node _T_3279 = eq(UInt<5>(0h10), idx_25) when _T_3279 : node _T_3280 = shl(UInt<5>(0h19), 3) node _T_3281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3280) node _T_3282 = bits(_T_3281, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3282 node _T_3283 = eq(UInt<5>(0h11), idx_25) when _T_3283 : node _T_3284 = shl(UInt<5>(0h19), 3) node _T_3285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3284) node _T_3286 = bits(_T_3285, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3286 node _T_3287 = eq(UInt<5>(0h12), idx_25) when _T_3287 : node _T_3288 = shl(UInt<5>(0h19), 3) node _T_3289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3288) node _T_3290 = bits(_T_3289, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3290 node _T_3291 = eq(UInt<5>(0h13), idx_25) when _T_3291 : node _T_3292 = shl(UInt<5>(0h19), 3) node _T_3293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3292) node _T_3294 = bits(_T_3293, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3294 node _T_3295 = eq(UInt<5>(0h14), idx_25) when _T_3295 : node _T_3296 = shl(UInt<5>(0h19), 3) node _T_3297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3296) node _T_3298 = bits(_T_3297, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3298 node _T_3299 = eq(UInt<5>(0h15), idx_25) when _T_3299 : node _T_3300 = shl(UInt<5>(0h19), 3) node _T_3301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3300) node _T_3302 = bits(_T_3301, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3302 node _T_3303 = eq(UInt<5>(0h16), idx_25) when _T_3303 : node _T_3304 = shl(UInt<5>(0h19), 3) node _T_3305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3304) node _T_3306 = bits(_T_3305, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3306 node _T_3307 = eq(UInt<5>(0h17), idx_25) when _T_3307 : node _T_3308 = shl(UInt<5>(0h19), 3) node _T_3309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3308) node _T_3310 = bits(_T_3309, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3310 node _T_3311 = eq(UInt<5>(0h18), idx_25) when _T_3311 : node _T_3312 = shl(UInt<5>(0h19), 3) node _T_3313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3312) node _T_3314 = bits(_T_3313, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3314 node _T_3315 = eq(UInt<5>(0h19), idx_25) when _T_3315 : node _T_3316 = shl(UInt<5>(0h19), 3) node _T_3317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3316) node _T_3318 = bits(_T_3317, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3318 node _T_3319 = eq(UInt<5>(0h1a), idx_25) when _T_3319 : node _T_3320 = shl(UInt<5>(0h19), 3) node _T_3321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3320) node _T_3322 = bits(_T_3321, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3322 node _T_3323 = eq(UInt<5>(0h1b), idx_25) when _T_3323 : node _T_3324 = shl(UInt<5>(0h19), 3) node _T_3325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3324) node _T_3326 = bits(_T_3325, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3326 node _T_3327 = eq(UInt<5>(0h1c), idx_25) when _T_3327 : node _T_3328 = shl(UInt<5>(0h19), 3) node _T_3329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3328) node _T_3330 = bits(_T_3329, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3330 node _T_3331 = eq(UInt<5>(0h1d), idx_25) when _T_3331 : node _T_3332 = shl(UInt<5>(0h19), 3) node _T_3333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3332) node _T_3334 = bits(_T_3333, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3334 node _T_3335 = eq(UInt<5>(0h1e), idx_25) when _T_3335 : node _T_3336 = shl(UInt<5>(0h19), 3) node _T_3337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3336) node _T_3338 = bits(_T_3337, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3338 node _T_3339 = eq(UInt<5>(0h1f), idx_25) when _T_3339 : node _T_3340 = shl(UInt<5>(0h19), 3) node _T_3341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3340) node _T_3342 = bits(_T_3341, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3342 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_3343 = eq(UInt<1>(0h0), idx_26) when _T_3343 : node _T_3344 = shl(UInt<5>(0h1a), 3) node _T_3345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3344) node _T_3346 = bits(_T_3345, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3346 node _T_3347 = eq(UInt<1>(0h1), idx_26) when _T_3347 : node _T_3348 = shl(UInt<5>(0h1a), 3) node _T_3349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3348) node _T_3350 = bits(_T_3349, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3350 node _T_3351 = eq(UInt<2>(0h2), idx_26) when _T_3351 : node _T_3352 = shl(UInt<5>(0h1a), 3) node _T_3353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3352) node _T_3354 = bits(_T_3353, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3354 node _T_3355 = eq(UInt<2>(0h3), idx_26) when _T_3355 : node _T_3356 = shl(UInt<5>(0h1a), 3) node _T_3357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3356) node _T_3358 = bits(_T_3357, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3358 node _T_3359 = eq(UInt<3>(0h4), idx_26) when _T_3359 : node _T_3360 = shl(UInt<5>(0h1a), 3) node _T_3361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3360) node _T_3362 = bits(_T_3361, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3362 node _T_3363 = eq(UInt<3>(0h5), idx_26) when _T_3363 : node _T_3364 = shl(UInt<5>(0h1a), 3) node _T_3365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3364) node _T_3366 = bits(_T_3365, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3366 node _T_3367 = eq(UInt<3>(0h6), idx_26) when _T_3367 : node _T_3368 = shl(UInt<5>(0h1a), 3) node _T_3369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3368) node _T_3370 = bits(_T_3369, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3370 node _T_3371 = eq(UInt<3>(0h7), idx_26) when _T_3371 : node _T_3372 = shl(UInt<5>(0h1a), 3) node _T_3373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3372) node _T_3374 = bits(_T_3373, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3374 node _T_3375 = eq(UInt<4>(0h8), idx_26) when _T_3375 : node _T_3376 = shl(UInt<5>(0h1a), 3) node _T_3377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3376) node _T_3378 = bits(_T_3377, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3378 node _T_3379 = eq(UInt<4>(0h9), idx_26) when _T_3379 : node _T_3380 = shl(UInt<5>(0h1a), 3) node _T_3381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3380) node _T_3382 = bits(_T_3381, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3382 node _T_3383 = eq(UInt<4>(0ha), idx_26) when _T_3383 : node _T_3384 = shl(UInt<5>(0h1a), 3) node _T_3385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3384) node _T_3386 = bits(_T_3385, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3386 node _T_3387 = eq(UInt<4>(0hb), idx_26) when _T_3387 : node _T_3388 = shl(UInt<5>(0h1a), 3) node _T_3389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3388) node _T_3390 = bits(_T_3389, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3390 node _T_3391 = eq(UInt<4>(0hc), idx_26) when _T_3391 : node _T_3392 = shl(UInt<5>(0h1a), 3) node _T_3393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3392) node _T_3394 = bits(_T_3393, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3394 node _T_3395 = eq(UInt<4>(0hd), idx_26) when _T_3395 : node _T_3396 = shl(UInt<5>(0h1a), 3) node _T_3397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3396) node _T_3398 = bits(_T_3397, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3398 node _T_3399 = eq(UInt<4>(0he), idx_26) when _T_3399 : node _T_3400 = shl(UInt<5>(0h1a), 3) node _T_3401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3400) node _T_3402 = bits(_T_3401, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3402 node _T_3403 = eq(UInt<4>(0hf), idx_26) when _T_3403 : node _T_3404 = shl(UInt<5>(0h1a), 3) node _T_3405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3404) node _T_3406 = bits(_T_3405, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3406 node _T_3407 = eq(UInt<5>(0h10), idx_26) when _T_3407 : node _T_3408 = shl(UInt<5>(0h1a), 3) node _T_3409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3408) node _T_3410 = bits(_T_3409, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3410 node _T_3411 = eq(UInt<5>(0h11), idx_26) when _T_3411 : node _T_3412 = shl(UInt<5>(0h1a), 3) node _T_3413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3412) node _T_3414 = bits(_T_3413, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3414 node _T_3415 = eq(UInt<5>(0h12), idx_26) when _T_3415 : node _T_3416 = shl(UInt<5>(0h1a), 3) node _T_3417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3416) node _T_3418 = bits(_T_3417, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3418 node _T_3419 = eq(UInt<5>(0h13), idx_26) when _T_3419 : node _T_3420 = shl(UInt<5>(0h1a), 3) node _T_3421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3420) node _T_3422 = bits(_T_3421, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3422 node _T_3423 = eq(UInt<5>(0h14), idx_26) when _T_3423 : node _T_3424 = shl(UInt<5>(0h1a), 3) node _T_3425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3424) node _T_3426 = bits(_T_3425, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3426 node _T_3427 = eq(UInt<5>(0h15), idx_26) when _T_3427 : node _T_3428 = shl(UInt<5>(0h1a), 3) node _T_3429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3428) node _T_3430 = bits(_T_3429, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3430 node _T_3431 = eq(UInt<5>(0h16), idx_26) when _T_3431 : node _T_3432 = shl(UInt<5>(0h1a), 3) node _T_3433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3432) node _T_3434 = bits(_T_3433, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3434 node _T_3435 = eq(UInt<5>(0h17), idx_26) when _T_3435 : node _T_3436 = shl(UInt<5>(0h1a), 3) node _T_3437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3436) node _T_3438 = bits(_T_3437, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3438 node _T_3439 = eq(UInt<5>(0h18), idx_26) when _T_3439 : node _T_3440 = shl(UInt<5>(0h1a), 3) node _T_3441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3440) node _T_3442 = bits(_T_3441, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3442 node _T_3443 = eq(UInt<5>(0h19), idx_26) when _T_3443 : node _T_3444 = shl(UInt<5>(0h1a), 3) node _T_3445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3444) node _T_3446 = bits(_T_3445, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3446 node _T_3447 = eq(UInt<5>(0h1a), idx_26) when _T_3447 : node _T_3448 = shl(UInt<5>(0h1a), 3) node _T_3449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3448) node _T_3450 = bits(_T_3449, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3450 node _T_3451 = eq(UInt<5>(0h1b), idx_26) when _T_3451 : node _T_3452 = shl(UInt<5>(0h1a), 3) node _T_3453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3452) node _T_3454 = bits(_T_3453, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3454 node _T_3455 = eq(UInt<5>(0h1c), idx_26) when _T_3455 : node _T_3456 = shl(UInt<5>(0h1a), 3) node _T_3457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3456) node _T_3458 = bits(_T_3457, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3458 node _T_3459 = eq(UInt<5>(0h1d), idx_26) when _T_3459 : node _T_3460 = shl(UInt<5>(0h1a), 3) node _T_3461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3460) node _T_3462 = bits(_T_3461, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3462 node _T_3463 = eq(UInt<5>(0h1e), idx_26) when _T_3463 : node _T_3464 = shl(UInt<5>(0h1a), 3) node _T_3465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3464) node _T_3466 = bits(_T_3465, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3466 node _T_3467 = eq(UInt<5>(0h1f), idx_26) when _T_3467 : node _T_3468 = shl(UInt<5>(0h1a), 3) node _T_3469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3468) node _T_3470 = bits(_T_3469, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3470 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_3471 = eq(UInt<1>(0h0), idx_27) when _T_3471 : node _T_3472 = shl(UInt<5>(0h1b), 3) node _T_3473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3472) node _T_3474 = bits(_T_3473, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3474 node _T_3475 = eq(UInt<1>(0h1), idx_27) when _T_3475 : node _T_3476 = shl(UInt<5>(0h1b), 3) node _T_3477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3476) node _T_3478 = bits(_T_3477, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3478 node _T_3479 = eq(UInt<2>(0h2), idx_27) when _T_3479 : node _T_3480 = shl(UInt<5>(0h1b), 3) node _T_3481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3480) node _T_3482 = bits(_T_3481, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3482 node _T_3483 = eq(UInt<2>(0h3), idx_27) when _T_3483 : node _T_3484 = shl(UInt<5>(0h1b), 3) node _T_3485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3484) node _T_3486 = bits(_T_3485, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3486 node _T_3487 = eq(UInt<3>(0h4), idx_27) when _T_3487 : node _T_3488 = shl(UInt<5>(0h1b), 3) node _T_3489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3488) node _T_3490 = bits(_T_3489, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3490 node _T_3491 = eq(UInt<3>(0h5), idx_27) when _T_3491 : node _T_3492 = shl(UInt<5>(0h1b), 3) node _T_3493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3492) node _T_3494 = bits(_T_3493, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3494 node _T_3495 = eq(UInt<3>(0h6), idx_27) when _T_3495 : node _T_3496 = shl(UInt<5>(0h1b), 3) node _T_3497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3496) node _T_3498 = bits(_T_3497, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3498 node _T_3499 = eq(UInt<3>(0h7), idx_27) when _T_3499 : node _T_3500 = shl(UInt<5>(0h1b), 3) node _T_3501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3500) node _T_3502 = bits(_T_3501, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3502 node _T_3503 = eq(UInt<4>(0h8), idx_27) when _T_3503 : node _T_3504 = shl(UInt<5>(0h1b), 3) node _T_3505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3504) node _T_3506 = bits(_T_3505, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3506 node _T_3507 = eq(UInt<4>(0h9), idx_27) when _T_3507 : node _T_3508 = shl(UInt<5>(0h1b), 3) node _T_3509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3508) node _T_3510 = bits(_T_3509, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3510 node _T_3511 = eq(UInt<4>(0ha), idx_27) when _T_3511 : node _T_3512 = shl(UInt<5>(0h1b), 3) node _T_3513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3512) node _T_3514 = bits(_T_3513, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3514 node _T_3515 = eq(UInt<4>(0hb), idx_27) when _T_3515 : node _T_3516 = shl(UInt<5>(0h1b), 3) node _T_3517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3516) node _T_3518 = bits(_T_3517, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3518 node _T_3519 = eq(UInt<4>(0hc), idx_27) when _T_3519 : node _T_3520 = shl(UInt<5>(0h1b), 3) node _T_3521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3520) node _T_3522 = bits(_T_3521, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3522 node _T_3523 = eq(UInt<4>(0hd), idx_27) when _T_3523 : node _T_3524 = shl(UInt<5>(0h1b), 3) node _T_3525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3524) node _T_3526 = bits(_T_3525, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3526 node _T_3527 = eq(UInt<4>(0he), idx_27) when _T_3527 : node _T_3528 = shl(UInt<5>(0h1b), 3) node _T_3529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3528) node _T_3530 = bits(_T_3529, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3530 node _T_3531 = eq(UInt<4>(0hf), idx_27) when _T_3531 : node _T_3532 = shl(UInt<5>(0h1b), 3) node _T_3533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3532) node _T_3534 = bits(_T_3533, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3534 node _T_3535 = eq(UInt<5>(0h10), idx_27) when _T_3535 : node _T_3536 = shl(UInt<5>(0h1b), 3) node _T_3537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3536) node _T_3538 = bits(_T_3537, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3538 node _T_3539 = eq(UInt<5>(0h11), idx_27) when _T_3539 : node _T_3540 = shl(UInt<5>(0h1b), 3) node _T_3541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3540) node _T_3542 = bits(_T_3541, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3542 node _T_3543 = eq(UInt<5>(0h12), idx_27) when _T_3543 : node _T_3544 = shl(UInt<5>(0h1b), 3) node _T_3545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3544) node _T_3546 = bits(_T_3545, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3546 node _T_3547 = eq(UInt<5>(0h13), idx_27) when _T_3547 : node _T_3548 = shl(UInt<5>(0h1b), 3) node _T_3549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3548) node _T_3550 = bits(_T_3549, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3550 node _T_3551 = eq(UInt<5>(0h14), idx_27) when _T_3551 : node _T_3552 = shl(UInt<5>(0h1b), 3) node _T_3553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3552) node _T_3554 = bits(_T_3553, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3554 node _T_3555 = eq(UInt<5>(0h15), idx_27) when _T_3555 : node _T_3556 = shl(UInt<5>(0h1b), 3) node _T_3557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3556) node _T_3558 = bits(_T_3557, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3558 node _T_3559 = eq(UInt<5>(0h16), idx_27) when _T_3559 : node _T_3560 = shl(UInt<5>(0h1b), 3) node _T_3561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3560) node _T_3562 = bits(_T_3561, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3562 node _T_3563 = eq(UInt<5>(0h17), idx_27) when _T_3563 : node _T_3564 = shl(UInt<5>(0h1b), 3) node _T_3565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3564) node _T_3566 = bits(_T_3565, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3566 node _T_3567 = eq(UInt<5>(0h18), idx_27) when _T_3567 : node _T_3568 = shl(UInt<5>(0h1b), 3) node _T_3569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3568) node _T_3570 = bits(_T_3569, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3570 node _T_3571 = eq(UInt<5>(0h19), idx_27) when _T_3571 : node _T_3572 = shl(UInt<5>(0h1b), 3) node _T_3573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3572) node _T_3574 = bits(_T_3573, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3574 node _T_3575 = eq(UInt<5>(0h1a), idx_27) when _T_3575 : node _T_3576 = shl(UInt<5>(0h1b), 3) node _T_3577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3576) node _T_3578 = bits(_T_3577, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3578 node _T_3579 = eq(UInt<5>(0h1b), idx_27) when _T_3579 : node _T_3580 = shl(UInt<5>(0h1b), 3) node _T_3581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3580) node _T_3582 = bits(_T_3581, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3582 node _T_3583 = eq(UInt<5>(0h1c), idx_27) when _T_3583 : node _T_3584 = shl(UInt<5>(0h1b), 3) node _T_3585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3584) node _T_3586 = bits(_T_3585, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3586 node _T_3587 = eq(UInt<5>(0h1d), idx_27) when _T_3587 : node _T_3588 = shl(UInt<5>(0h1b), 3) node _T_3589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3588) node _T_3590 = bits(_T_3589, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3590 node _T_3591 = eq(UInt<5>(0h1e), idx_27) when _T_3591 : node _T_3592 = shl(UInt<5>(0h1b), 3) node _T_3593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3592) node _T_3594 = bits(_T_3593, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3594 node _T_3595 = eq(UInt<5>(0h1f), idx_27) when _T_3595 : node _T_3596 = shl(UInt<5>(0h1b), 3) node _T_3597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3596) node _T_3598 = bits(_T_3597, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3598 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_3599 = eq(UInt<1>(0h0), idx_28) when _T_3599 : node _T_3600 = shl(UInt<5>(0h1c), 3) node _T_3601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3600) node _T_3602 = bits(_T_3601, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3602 node _T_3603 = eq(UInt<1>(0h1), idx_28) when _T_3603 : node _T_3604 = shl(UInt<5>(0h1c), 3) node _T_3605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3604) node _T_3606 = bits(_T_3605, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3606 node _T_3607 = eq(UInt<2>(0h2), idx_28) when _T_3607 : node _T_3608 = shl(UInt<5>(0h1c), 3) node _T_3609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3608) node _T_3610 = bits(_T_3609, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3610 node _T_3611 = eq(UInt<2>(0h3), idx_28) when _T_3611 : node _T_3612 = shl(UInt<5>(0h1c), 3) node _T_3613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3612) node _T_3614 = bits(_T_3613, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3614 node _T_3615 = eq(UInt<3>(0h4), idx_28) when _T_3615 : node _T_3616 = shl(UInt<5>(0h1c), 3) node _T_3617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3616) node _T_3618 = bits(_T_3617, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3618 node _T_3619 = eq(UInt<3>(0h5), idx_28) when _T_3619 : node _T_3620 = shl(UInt<5>(0h1c), 3) node _T_3621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3620) node _T_3622 = bits(_T_3621, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3622 node _T_3623 = eq(UInt<3>(0h6), idx_28) when _T_3623 : node _T_3624 = shl(UInt<5>(0h1c), 3) node _T_3625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3624) node _T_3626 = bits(_T_3625, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3626 node _T_3627 = eq(UInt<3>(0h7), idx_28) when _T_3627 : node _T_3628 = shl(UInt<5>(0h1c), 3) node _T_3629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3628) node _T_3630 = bits(_T_3629, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3630 node _T_3631 = eq(UInt<4>(0h8), idx_28) when _T_3631 : node _T_3632 = shl(UInt<5>(0h1c), 3) node _T_3633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3632) node _T_3634 = bits(_T_3633, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3634 node _T_3635 = eq(UInt<4>(0h9), idx_28) when _T_3635 : node _T_3636 = shl(UInt<5>(0h1c), 3) node _T_3637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3636) node _T_3638 = bits(_T_3637, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3638 node _T_3639 = eq(UInt<4>(0ha), idx_28) when _T_3639 : node _T_3640 = shl(UInt<5>(0h1c), 3) node _T_3641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3640) node _T_3642 = bits(_T_3641, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3642 node _T_3643 = eq(UInt<4>(0hb), idx_28) when _T_3643 : node _T_3644 = shl(UInt<5>(0h1c), 3) node _T_3645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3644) node _T_3646 = bits(_T_3645, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3646 node _T_3647 = eq(UInt<4>(0hc), idx_28) when _T_3647 : node _T_3648 = shl(UInt<5>(0h1c), 3) node _T_3649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3648) node _T_3650 = bits(_T_3649, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3650 node _T_3651 = eq(UInt<4>(0hd), idx_28) when _T_3651 : node _T_3652 = shl(UInt<5>(0h1c), 3) node _T_3653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3652) node _T_3654 = bits(_T_3653, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3654 node _T_3655 = eq(UInt<4>(0he), idx_28) when _T_3655 : node _T_3656 = shl(UInt<5>(0h1c), 3) node _T_3657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3656) node _T_3658 = bits(_T_3657, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3658 node _T_3659 = eq(UInt<4>(0hf), idx_28) when _T_3659 : node _T_3660 = shl(UInt<5>(0h1c), 3) node _T_3661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3660) node _T_3662 = bits(_T_3661, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3662 node _T_3663 = eq(UInt<5>(0h10), idx_28) when _T_3663 : node _T_3664 = shl(UInt<5>(0h1c), 3) node _T_3665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3664) node _T_3666 = bits(_T_3665, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3666 node _T_3667 = eq(UInt<5>(0h11), idx_28) when _T_3667 : node _T_3668 = shl(UInt<5>(0h1c), 3) node _T_3669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3668) node _T_3670 = bits(_T_3669, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3670 node _T_3671 = eq(UInt<5>(0h12), idx_28) when _T_3671 : node _T_3672 = shl(UInt<5>(0h1c), 3) node _T_3673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3672) node _T_3674 = bits(_T_3673, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3674 node _T_3675 = eq(UInt<5>(0h13), idx_28) when _T_3675 : node _T_3676 = shl(UInt<5>(0h1c), 3) node _T_3677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3676) node _T_3678 = bits(_T_3677, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3678 node _T_3679 = eq(UInt<5>(0h14), idx_28) when _T_3679 : node _T_3680 = shl(UInt<5>(0h1c), 3) node _T_3681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3680) node _T_3682 = bits(_T_3681, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3682 node _T_3683 = eq(UInt<5>(0h15), idx_28) when _T_3683 : node _T_3684 = shl(UInt<5>(0h1c), 3) node _T_3685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3684) node _T_3686 = bits(_T_3685, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3686 node _T_3687 = eq(UInt<5>(0h16), idx_28) when _T_3687 : node _T_3688 = shl(UInt<5>(0h1c), 3) node _T_3689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3688) node _T_3690 = bits(_T_3689, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3690 node _T_3691 = eq(UInt<5>(0h17), idx_28) when _T_3691 : node _T_3692 = shl(UInt<5>(0h1c), 3) node _T_3693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3692) node _T_3694 = bits(_T_3693, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3694 node _T_3695 = eq(UInt<5>(0h18), idx_28) when _T_3695 : node _T_3696 = shl(UInt<5>(0h1c), 3) node _T_3697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3696) node _T_3698 = bits(_T_3697, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3698 node _T_3699 = eq(UInt<5>(0h19), idx_28) when _T_3699 : node _T_3700 = shl(UInt<5>(0h1c), 3) node _T_3701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3700) node _T_3702 = bits(_T_3701, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3702 node _T_3703 = eq(UInt<5>(0h1a), idx_28) when _T_3703 : node _T_3704 = shl(UInt<5>(0h1c), 3) node _T_3705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3704) node _T_3706 = bits(_T_3705, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3706 node _T_3707 = eq(UInt<5>(0h1b), idx_28) when _T_3707 : node _T_3708 = shl(UInt<5>(0h1c), 3) node _T_3709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3708) node _T_3710 = bits(_T_3709, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3710 node _T_3711 = eq(UInt<5>(0h1c), idx_28) when _T_3711 : node _T_3712 = shl(UInt<5>(0h1c), 3) node _T_3713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3712) node _T_3714 = bits(_T_3713, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3714 node _T_3715 = eq(UInt<5>(0h1d), idx_28) when _T_3715 : node _T_3716 = shl(UInt<5>(0h1c), 3) node _T_3717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3716) node _T_3718 = bits(_T_3717, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3718 node _T_3719 = eq(UInt<5>(0h1e), idx_28) when _T_3719 : node _T_3720 = shl(UInt<5>(0h1c), 3) node _T_3721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3720) node _T_3722 = bits(_T_3721, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3722 node _T_3723 = eq(UInt<5>(0h1f), idx_28) when _T_3723 : node _T_3724 = shl(UInt<5>(0h1c), 3) node _T_3725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3724) node _T_3726 = bits(_T_3725, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3726 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_3727 = eq(UInt<1>(0h0), idx_29) when _T_3727 : node _T_3728 = shl(UInt<5>(0h1d), 3) node _T_3729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3728) node _T_3730 = bits(_T_3729, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3730 node _T_3731 = eq(UInt<1>(0h1), idx_29) when _T_3731 : node _T_3732 = shl(UInt<5>(0h1d), 3) node _T_3733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3732) node _T_3734 = bits(_T_3733, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3734 node _T_3735 = eq(UInt<2>(0h2), idx_29) when _T_3735 : node _T_3736 = shl(UInt<5>(0h1d), 3) node _T_3737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3736) node _T_3738 = bits(_T_3737, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3738 node _T_3739 = eq(UInt<2>(0h3), idx_29) when _T_3739 : node _T_3740 = shl(UInt<5>(0h1d), 3) node _T_3741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3740) node _T_3742 = bits(_T_3741, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3742 node _T_3743 = eq(UInt<3>(0h4), idx_29) when _T_3743 : node _T_3744 = shl(UInt<5>(0h1d), 3) node _T_3745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3744) node _T_3746 = bits(_T_3745, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3746 node _T_3747 = eq(UInt<3>(0h5), idx_29) when _T_3747 : node _T_3748 = shl(UInt<5>(0h1d), 3) node _T_3749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3748) node _T_3750 = bits(_T_3749, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3750 node _T_3751 = eq(UInt<3>(0h6), idx_29) when _T_3751 : node _T_3752 = shl(UInt<5>(0h1d), 3) node _T_3753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3752) node _T_3754 = bits(_T_3753, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3754 node _T_3755 = eq(UInt<3>(0h7), idx_29) when _T_3755 : node _T_3756 = shl(UInt<5>(0h1d), 3) node _T_3757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3756) node _T_3758 = bits(_T_3757, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3758 node _T_3759 = eq(UInt<4>(0h8), idx_29) when _T_3759 : node _T_3760 = shl(UInt<5>(0h1d), 3) node _T_3761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3760) node _T_3762 = bits(_T_3761, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3762 node _T_3763 = eq(UInt<4>(0h9), idx_29) when _T_3763 : node _T_3764 = shl(UInt<5>(0h1d), 3) node _T_3765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3764) node _T_3766 = bits(_T_3765, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3766 node _T_3767 = eq(UInt<4>(0ha), idx_29) when _T_3767 : node _T_3768 = shl(UInt<5>(0h1d), 3) node _T_3769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3768) node _T_3770 = bits(_T_3769, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3770 node _T_3771 = eq(UInt<4>(0hb), idx_29) when _T_3771 : node _T_3772 = shl(UInt<5>(0h1d), 3) node _T_3773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3772) node _T_3774 = bits(_T_3773, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3774 node _T_3775 = eq(UInt<4>(0hc), idx_29) when _T_3775 : node _T_3776 = shl(UInt<5>(0h1d), 3) node _T_3777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3776) node _T_3778 = bits(_T_3777, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3778 node _T_3779 = eq(UInt<4>(0hd), idx_29) when _T_3779 : node _T_3780 = shl(UInt<5>(0h1d), 3) node _T_3781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3780) node _T_3782 = bits(_T_3781, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3782 node _T_3783 = eq(UInt<4>(0he), idx_29) when _T_3783 : node _T_3784 = shl(UInt<5>(0h1d), 3) node _T_3785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3784) node _T_3786 = bits(_T_3785, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3786 node _T_3787 = eq(UInt<4>(0hf), idx_29) when _T_3787 : node _T_3788 = shl(UInt<5>(0h1d), 3) node _T_3789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3788) node _T_3790 = bits(_T_3789, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3790 node _T_3791 = eq(UInt<5>(0h10), idx_29) when _T_3791 : node _T_3792 = shl(UInt<5>(0h1d), 3) node _T_3793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3792) node _T_3794 = bits(_T_3793, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3794 node _T_3795 = eq(UInt<5>(0h11), idx_29) when _T_3795 : node _T_3796 = shl(UInt<5>(0h1d), 3) node _T_3797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3796) node _T_3798 = bits(_T_3797, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3798 node _T_3799 = eq(UInt<5>(0h12), idx_29) when _T_3799 : node _T_3800 = shl(UInt<5>(0h1d), 3) node _T_3801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3800) node _T_3802 = bits(_T_3801, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3802 node _T_3803 = eq(UInt<5>(0h13), idx_29) when _T_3803 : node _T_3804 = shl(UInt<5>(0h1d), 3) node _T_3805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3804) node _T_3806 = bits(_T_3805, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3806 node _T_3807 = eq(UInt<5>(0h14), idx_29) when _T_3807 : node _T_3808 = shl(UInt<5>(0h1d), 3) node _T_3809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3808) node _T_3810 = bits(_T_3809, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3810 node _T_3811 = eq(UInt<5>(0h15), idx_29) when _T_3811 : node _T_3812 = shl(UInt<5>(0h1d), 3) node _T_3813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3812) node _T_3814 = bits(_T_3813, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3814 node _T_3815 = eq(UInt<5>(0h16), idx_29) when _T_3815 : node _T_3816 = shl(UInt<5>(0h1d), 3) node _T_3817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3816) node _T_3818 = bits(_T_3817, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3818 node _T_3819 = eq(UInt<5>(0h17), idx_29) when _T_3819 : node _T_3820 = shl(UInt<5>(0h1d), 3) node _T_3821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3820) node _T_3822 = bits(_T_3821, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3822 node _T_3823 = eq(UInt<5>(0h18), idx_29) when _T_3823 : node _T_3824 = shl(UInt<5>(0h1d), 3) node _T_3825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3824) node _T_3826 = bits(_T_3825, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3826 node _T_3827 = eq(UInt<5>(0h19), idx_29) when _T_3827 : node _T_3828 = shl(UInt<5>(0h1d), 3) node _T_3829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3828) node _T_3830 = bits(_T_3829, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3830 node _T_3831 = eq(UInt<5>(0h1a), idx_29) when _T_3831 : node _T_3832 = shl(UInt<5>(0h1d), 3) node _T_3833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3832) node _T_3834 = bits(_T_3833, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3834 node _T_3835 = eq(UInt<5>(0h1b), idx_29) when _T_3835 : node _T_3836 = shl(UInt<5>(0h1d), 3) node _T_3837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3836) node _T_3838 = bits(_T_3837, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3838 node _T_3839 = eq(UInt<5>(0h1c), idx_29) when _T_3839 : node _T_3840 = shl(UInt<5>(0h1d), 3) node _T_3841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3840) node _T_3842 = bits(_T_3841, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3842 node _T_3843 = eq(UInt<5>(0h1d), idx_29) when _T_3843 : node _T_3844 = shl(UInt<5>(0h1d), 3) node _T_3845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3844) node _T_3846 = bits(_T_3845, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3846 node _T_3847 = eq(UInt<5>(0h1e), idx_29) when _T_3847 : node _T_3848 = shl(UInt<5>(0h1d), 3) node _T_3849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3848) node _T_3850 = bits(_T_3849, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3850 node _T_3851 = eq(UInt<5>(0h1f), idx_29) when _T_3851 : node _T_3852 = shl(UInt<5>(0h1d), 3) node _T_3853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3852) node _T_3854 = bits(_T_3853, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3854 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_3855 = eq(UInt<1>(0h0), idx_30) when _T_3855 : node _T_3856 = shl(UInt<5>(0h1e), 3) node _T_3857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3856) node _T_3858 = bits(_T_3857, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3858 node _T_3859 = eq(UInt<1>(0h1), idx_30) when _T_3859 : node _T_3860 = shl(UInt<5>(0h1e), 3) node _T_3861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3860) node _T_3862 = bits(_T_3861, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3862 node _T_3863 = eq(UInt<2>(0h2), idx_30) when _T_3863 : node _T_3864 = shl(UInt<5>(0h1e), 3) node _T_3865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3864) node _T_3866 = bits(_T_3865, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3866 node _T_3867 = eq(UInt<2>(0h3), idx_30) when _T_3867 : node _T_3868 = shl(UInt<5>(0h1e), 3) node _T_3869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3868) node _T_3870 = bits(_T_3869, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3870 node _T_3871 = eq(UInt<3>(0h4), idx_30) when _T_3871 : node _T_3872 = shl(UInt<5>(0h1e), 3) node _T_3873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3872) node _T_3874 = bits(_T_3873, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3874 node _T_3875 = eq(UInt<3>(0h5), idx_30) when _T_3875 : node _T_3876 = shl(UInt<5>(0h1e), 3) node _T_3877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3876) node _T_3878 = bits(_T_3877, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3878 node _T_3879 = eq(UInt<3>(0h6), idx_30) when _T_3879 : node _T_3880 = shl(UInt<5>(0h1e), 3) node _T_3881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3880) node _T_3882 = bits(_T_3881, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3882 node _T_3883 = eq(UInt<3>(0h7), idx_30) when _T_3883 : node _T_3884 = shl(UInt<5>(0h1e), 3) node _T_3885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3884) node _T_3886 = bits(_T_3885, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3886 node _T_3887 = eq(UInt<4>(0h8), idx_30) when _T_3887 : node _T_3888 = shl(UInt<5>(0h1e), 3) node _T_3889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3888) node _T_3890 = bits(_T_3889, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3890 node _T_3891 = eq(UInt<4>(0h9), idx_30) when _T_3891 : node _T_3892 = shl(UInt<5>(0h1e), 3) node _T_3893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3892) node _T_3894 = bits(_T_3893, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3894 node _T_3895 = eq(UInt<4>(0ha), idx_30) when _T_3895 : node _T_3896 = shl(UInt<5>(0h1e), 3) node _T_3897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3896) node _T_3898 = bits(_T_3897, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3898 node _T_3899 = eq(UInt<4>(0hb), idx_30) when _T_3899 : node _T_3900 = shl(UInt<5>(0h1e), 3) node _T_3901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3900) node _T_3902 = bits(_T_3901, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3902 node _T_3903 = eq(UInt<4>(0hc), idx_30) when _T_3903 : node _T_3904 = shl(UInt<5>(0h1e), 3) node _T_3905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3904) node _T_3906 = bits(_T_3905, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3906 node _T_3907 = eq(UInt<4>(0hd), idx_30) when _T_3907 : node _T_3908 = shl(UInt<5>(0h1e), 3) node _T_3909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3908) node _T_3910 = bits(_T_3909, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3910 node _T_3911 = eq(UInt<4>(0he), idx_30) when _T_3911 : node _T_3912 = shl(UInt<5>(0h1e), 3) node _T_3913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3912) node _T_3914 = bits(_T_3913, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3914 node _T_3915 = eq(UInt<4>(0hf), idx_30) when _T_3915 : node _T_3916 = shl(UInt<5>(0h1e), 3) node _T_3917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3916) node _T_3918 = bits(_T_3917, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3918 node _T_3919 = eq(UInt<5>(0h10), idx_30) when _T_3919 : node _T_3920 = shl(UInt<5>(0h1e), 3) node _T_3921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3920) node _T_3922 = bits(_T_3921, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3922 node _T_3923 = eq(UInt<5>(0h11), idx_30) when _T_3923 : node _T_3924 = shl(UInt<5>(0h1e), 3) node _T_3925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3924) node _T_3926 = bits(_T_3925, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3926 node _T_3927 = eq(UInt<5>(0h12), idx_30) when _T_3927 : node _T_3928 = shl(UInt<5>(0h1e), 3) node _T_3929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3928) node _T_3930 = bits(_T_3929, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3930 node _T_3931 = eq(UInt<5>(0h13), idx_30) when _T_3931 : node _T_3932 = shl(UInt<5>(0h1e), 3) node _T_3933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3932) node _T_3934 = bits(_T_3933, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3934 node _T_3935 = eq(UInt<5>(0h14), idx_30) when _T_3935 : node _T_3936 = shl(UInt<5>(0h1e), 3) node _T_3937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3936) node _T_3938 = bits(_T_3937, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3938 node _T_3939 = eq(UInt<5>(0h15), idx_30) when _T_3939 : node _T_3940 = shl(UInt<5>(0h1e), 3) node _T_3941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3940) node _T_3942 = bits(_T_3941, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3942 node _T_3943 = eq(UInt<5>(0h16), idx_30) when _T_3943 : node _T_3944 = shl(UInt<5>(0h1e), 3) node _T_3945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3944) node _T_3946 = bits(_T_3945, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3946 node _T_3947 = eq(UInt<5>(0h17), idx_30) when _T_3947 : node _T_3948 = shl(UInt<5>(0h1e), 3) node _T_3949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3948) node _T_3950 = bits(_T_3949, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3950 node _T_3951 = eq(UInt<5>(0h18), idx_30) when _T_3951 : node _T_3952 = shl(UInt<5>(0h1e), 3) node _T_3953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3952) node _T_3954 = bits(_T_3953, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3954 node _T_3955 = eq(UInt<5>(0h19), idx_30) when _T_3955 : node _T_3956 = shl(UInt<5>(0h1e), 3) node _T_3957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3956) node _T_3958 = bits(_T_3957, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3958 node _T_3959 = eq(UInt<5>(0h1a), idx_30) when _T_3959 : node _T_3960 = shl(UInt<5>(0h1e), 3) node _T_3961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3960) node _T_3962 = bits(_T_3961, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3962 node _T_3963 = eq(UInt<5>(0h1b), idx_30) when _T_3963 : node _T_3964 = shl(UInt<5>(0h1e), 3) node _T_3965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3964) node _T_3966 = bits(_T_3965, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3966 node _T_3967 = eq(UInt<5>(0h1c), idx_30) when _T_3967 : node _T_3968 = shl(UInt<5>(0h1e), 3) node _T_3969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3968) node _T_3970 = bits(_T_3969, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3970 node _T_3971 = eq(UInt<5>(0h1d), idx_30) when _T_3971 : node _T_3972 = shl(UInt<5>(0h1e), 3) node _T_3973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3972) node _T_3974 = bits(_T_3973, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3974 node _T_3975 = eq(UInt<5>(0h1e), idx_30) when _T_3975 : node _T_3976 = shl(UInt<5>(0h1e), 3) node _T_3977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3976) node _T_3978 = bits(_T_3977, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3978 node _T_3979 = eq(UInt<5>(0h1f), idx_30) when _T_3979 : node _T_3980 = shl(UInt<5>(0h1e), 3) node _T_3981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3980) node _T_3982 = bits(_T_3981, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3982 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_3983 = eq(UInt<1>(0h0), idx_31) when _T_3983 : node _T_3984 = shl(UInt<5>(0h1f), 3) node _T_3985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3984) node _T_3986 = bits(_T_3985, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3986 node _T_3987 = eq(UInt<1>(0h1), idx_31) when _T_3987 : node _T_3988 = shl(UInt<5>(0h1f), 3) node _T_3989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3988) node _T_3990 = bits(_T_3989, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3990 node _T_3991 = eq(UInt<2>(0h2), idx_31) when _T_3991 : node _T_3992 = shl(UInt<5>(0h1f), 3) node _T_3993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3992) node _T_3994 = bits(_T_3993, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3994 node _T_3995 = eq(UInt<2>(0h3), idx_31) when _T_3995 : node _T_3996 = shl(UInt<5>(0h1f), 3) node _T_3997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3996) node _T_3998 = bits(_T_3997, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3998 node _T_3999 = eq(UInt<3>(0h4), idx_31) when _T_3999 : node _T_4000 = shl(UInt<5>(0h1f), 3) node _T_4001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4000) node _T_4002 = bits(_T_4001, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_4002 node _T_4003 = eq(UInt<3>(0h5), idx_31) when _T_4003 : node _T_4004 = shl(UInt<5>(0h1f), 3) node _T_4005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4004) node _T_4006 = bits(_T_4005, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_4006 node _T_4007 = eq(UInt<3>(0h6), idx_31) when _T_4007 : node _T_4008 = shl(UInt<5>(0h1f), 3) node _T_4009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4008) node _T_4010 = bits(_T_4009, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_4010 node _T_4011 = eq(UInt<3>(0h7), idx_31) when _T_4011 : node _T_4012 = shl(UInt<5>(0h1f), 3) node _T_4013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4012) node _T_4014 = bits(_T_4013, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_4014 node _T_4015 = eq(UInt<4>(0h8), idx_31) when _T_4015 : node _T_4016 = shl(UInt<5>(0h1f), 3) node _T_4017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4016) node _T_4018 = bits(_T_4017, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_4018 node _T_4019 = eq(UInt<4>(0h9), idx_31) when _T_4019 : node _T_4020 = shl(UInt<5>(0h1f), 3) node _T_4021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4020) node _T_4022 = bits(_T_4021, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_4022 node _T_4023 = eq(UInt<4>(0ha), idx_31) when _T_4023 : node _T_4024 = shl(UInt<5>(0h1f), 3) node _T_4025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4024) node _T_4026 = bits(_T_4025, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_4026 node _T_4027 = eq(UInt<4>(0hb), idx_31) when _T_4027 : node _T_4028 = shl(UInt<5>(0h1f), 3) node _T_4029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4028) node _T_4030 = bits(_T_4029, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_4030 node _T_4031 = eq(UInt<4>(0hc), idx_31) when _T_4031 : node _T_4032 = shl(UInt<5>(0h1f), 3) node _T_4033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4032) node _T_4034 = bits(_T_4033, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_4034 node _T_4035 = eq(UInt<4>(0hd), idx_31) when _T_4035 : node _T_4036 = shl(UInt<5>(0h1f), 3) node _T_4037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4036) node _T_4038 = bits(_T_4037, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_4038 node _T_4039 = eq(UInt<4>(0he), idx_31) when _T_4039 : node _T_4040 = shl(UInt<5>(0h1f), 3) node _T_4041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4040) node _T_4042 = bits(_T_4041, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_4042 node _T_4043 = eq(UInt<4>(0hf), idx_31) when _T_4043 : node _T_4044 = shl(UInt<5>(0h1f), 3) node _T_4045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4044) node _T_4046 = bits(_T_4045, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_4046 node _T_4047 = eq(UInt<5>(0h10), idx_31) when _T_4047 : node _T_4048 = shl(UInt<5>(0h1f), 3) node _T_4049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4048) node _T_4050 = bits(_T_4049, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_4050 node _T_4051 = eq(UInt<5>(0h11), idx_31) when _T_4051 : node _T_4052 = shl(UInt<5>(0h1f), 3) node _T_4053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4052) node _T_4054 = bits(_T_4053, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_4054 node _T_4055 = eq(UInt<5>(0h12), idx_31) when _T_4055 : node _T_4056 = shl(UInt<5>(0h1f), 3) node _T_4057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4056) node _T_4058 = bits(_T_4057, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_4058 node _T_4059 = eq(UInt<5>(0h13), idx_31) when _T_4059 : node _T_4060 = shl(UInt<5>(0h1f), 3) node _T_4061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4060) node _T_4062 = bits(_T_4061, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_4062 node _T_4063 = eq(UInt<5>(0h14), idx_31) when _T_4063 : node _T_4064 = shl(UInt<5>(0h1f), 3) node _T_4065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4064) node _T_4066 = bits(_T_4065, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_4066 node _T_4067 = eq(UInt<5>(0h15), idx_31) when _T_4067 : node _T_4068 = shl(UInt<5>(0h1f), 3) node _T_4069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4068) node _T_4070 = bits(_T_4069, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_4070 node _T_4071 = eq(UInt<5>(0h16), idx_31) when _T_4071 : node _T_4072 = shl(UInt<5>(0h1f), 3) node _T_4073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4072) node _T_4074 = bits(_T_4073, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_4074 node _T_4075 = eq(UInt<5>(0h17), idx_31) when _T_4075 : node _T_4076 = shl(UInt<5>(0h1f), 3) node _T_4077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4076) node _T_4078 = bits(_T_4077, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_4078 node _T_4079 = eq(UInt<5>(0h18), idx_31) when _T_4079 : node _T_4080 = shl(UInt<5>(0h1f), 3) node _T_4081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4080) node _T_4082 = bits(_T_4081, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_4082 node _T_4083 = eq(UInt<5>(0h19), idx_31) when _T_4083 : node _T_4084 = shl(UInt<5>(0h1f), 3) node _T_4085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4084) node _T_4086 = bits(_T_4085, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_4086 node _T_4087 = eq(UInt<5>(0h1a), idx_31) when _T_4087 : node _T_4088 = shl(UInt<5>(0h1f), 3) node _T_4089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4088) node _T_4090 = bits(_T_4089, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_4090 node _T_4091 = eq(UInt<5>(0h1b), idx_31) when _T_4091 : node _T_4092 = shl(UInt<5>(0h1f), 3) node _T_4093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4092) node _T_4094 = bits(_T_4093, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_4094 node _T_4095 = eq(UInt<5>(0h1c), idx_31) when _T_4095 : node _T_4096 = shl(UInt<5>(0h1f), 3) node _T_4097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4096) node _T_4098 = bits(_T_4097, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_4098 node _T_4099 = eq(UInt<5>(0h1d), idx_31) when _T_4099 : node _T_4100 = shl(UInt<5>(0h1f), 3) node _T_4101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4100) node _T_4102 = bits(_T_4101, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_4102 node _T_4103 = eq(UInt<5>(0h1e), idx_31) when _T_4103 : node _T_4104 = shl(UInt<5>(0h1f), 3) node _T_4105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4104) node _T_4106 = bits(_T_4105, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_4106 node _T_4107 = eq(UInt<5>(0h1f), idx_31) when _T_4107 : node _T_4108 = shl(UInt<5>(0h1f), 3) node _T_4109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4108) node _T_4110 = bits(_T_4109, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_4110 node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) node _all_queues_ready_T = and(Queue16_UInt8.io.enq.ready, Queue16_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue16_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue16_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue16_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue16_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue16_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue16_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue16_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue16_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue16_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue16_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue16_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue16_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue16_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue16_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue16_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue16_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue16_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue16_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue16_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue16_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue16_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue16_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue16_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue16_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue16_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue16_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue16_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue16_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue16_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue16_UInt8_31.io.enq.ready) node _account_for_buf_lens_Q_T = eq(incoming_writes_Q.io.deq.bits.end_of_message, UInt<1>(0h0)) node _account_for_buf_lens_Q_T_1 = and(incoming_writes_Q.io.deq.bits.end_of_message, buf_lens_Q.io.enq.ready) node account_for_buf_lens_Q = or(_account_for_buf_lens_Q_T, _account_for_buf_lens_Q_T_1) node _buf_lens_Q_io_enq_valid_T = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _buf_lens_Q_io_enq_valid_T_1 = and(_buf_lens_Q_io_enq_valid_T, incoming_writes_Q.io.deq.bits.end_of_message) connect buf_lens_Q.io.enq.valid, _buf_lens_Q_io_enq_valid_T_1 node _buf_lens_Q_io_enq_bits_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_lens_Q.io.enq.bits, _buf_lens_Q_io_enq_bits_T node _incoming_writes_Q_io_deq_ready_T = and(all_queues_ready, account_for_buf_lens_Q) connect incoming_writes_Q.io.deq.ready, _incoming_writes_Q_io_deq_ready_T node _T_4111 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4112 = and(_T_4111, account_for_buf_lens_Q) when _T_4112 : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_4113 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4114 = and(_T_4113, account_for_buf_lens_Q) node _T_4115 = and(_T_4114, use_this_queue) connect Queue16_UInt8.io.enq.valid, _T_4115 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_4116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4117 = and(_T_4116, account_for_buf_lens_Q) node _T_4118 = and(_T_4117, use_this_queue_1) connect Queue16_UInt8_1.io.enq.valid, _T_4118 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_4119 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4120 = and(_T_4119, account_for_buf_lens_Q) node _T_4121 = and(_T_4120, use_this_queue_2) connect Queue16_UInt8_2.io.enq.valid, _T_4121 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_4122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4123 = and(_T_4122, account_for_buf_lens_Q) node _T_4124 = and(_T_4123, use_this_queue_3) connect Queue16_UInt8_3.io.enq.valid, _T_4124 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_4125 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4126 = and(_T_4125, account_for_buf_lens_Q) node _T_4127 = and(_T_4126, use_this_queue_4) connect Queue16_UInt8_4.io.enq.valid, _T_4127 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_4128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4129 = and(_T_4128, account_for_buf_lens_Q) node _T_4130 = and(_T_4129, use_this_queue_5) connect Queue16_UInt8_5.io.enq.valid, _T_4130 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_4131 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4132 = and(_T_4131, account_for_buf_lens_Q) node _T_4133 = and(_T_4132, use_this_queue_6) connect Queue16_UInt8_6.io.enq.valid, _T_4133 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_4134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4135 = and(_T_4134, account_for_buf_lens_Q) node _T_4136 = and(_T_4135, use_this_queue_7) connect Queue16_UInt8_7.io.enq.valid, _T_4136 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_4137 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4138 = and(_T_4137, account_for_buf_lens_Q) node _T_4139 = and(_T_4138, use_this_queue_8) connect Queue16_UInt8_8.io.enq.valid, _T_4139 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_4140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4141 = and(_T_4140, account_for_buf_lens_Q) node _T_4142 = and(_T_4141, use_this_queue_9) connect Queue16_UInt8_9.io.enq.valid, _T_4142 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_4143 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4144 = and(_T_4143, account_for_buf_lens_Q) node _T_4145 = and(_T_4144, use_this_queue_10) connect Queue16_UInt8_10.io.enq.valid, _T_4145 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_4146 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4147 = and(_T_4146, account_for_buf_lens_Q) node _T_4148 = and(_T_4147, use_this_queue_11) connect Queue16_UInt8_11.io.enq.valid, _T_4148 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_4149 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4150 = and(_T_4149, account_for_buf_lens_Q) node _T_4151 = and(_T_4150, use_this_queue_12) connect Queue16_UInt8_12.io.enq.valid, _T_4151 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_4152 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4153 = and(_T_4152, account_for_buf_lens_Q) node _T_4154 = and(_T_4153, use_this_queue_13) connect Queue16_UInt8_13.io.enq.valid, _T_4154 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_4155 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4156 = and(_T_4155, account_for_buf_lens_Q) node _T_4157 = and(_T_4156, use_this_queue_14) connect Queue16_UInt8_14.io.enq.valid, _T_4157 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_4158 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4159 = and(_T_4158, account_for_buf_lens_Q) node _T_4160 = and(_T_4159, use_this_queue_15) connect Queue16_UInt8_15.io.enq.valid, _T_4160 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_4161 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4162 = and(_T_4161, account_for_buf_lens_Q) node _T_4163 = and(_T_4162, use_this_queue_16) connect Queue16_UInt8_16.io.enq.valid, _T_4163 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_4164 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4165 = and(_T_4164, account_for_buf_lens_Q) node _T_4166 = and(_T_4165, use_this_queue_17) connect Queue16_UInt8_17.io.enq.valid, _T_4166 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_4167 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4168 = and(_T_4167, account_for_buf_lens_Q) node _T_4169 = and(_T_4168, use_this_queue_18) connect Queue16_UInt8_18.io.enq.valid, _T_4169 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_4170 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4171 = and(_T_4170, account_for_buf_lens_Q) node _T_4172 = and(_T_4171, use_this_queue_19) connect Queue16_UInt8_19.io.enq.valid, _T_4172 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_4173 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4174 = and(_T_4173, account_for_buf_lens_Q) node _T_4175 = and(_T_4174, use_this_queue_20) connect Queue16_UInt8_20.io.enq.valid, _T_4175 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_4176 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4177 = and(_T_4176, account_for_buf_lens_Q) node _T_4178 = and(_T_4177, use_this_queue_21) connect Queue16_UInt8_21.io.enq.valid, _T_4178 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_4179 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4180 = and(_T_4179, account_for_buf_lens_Q) node _T_4181 = and(_T_4180, use_this_queue_22) connect Queue16_UInt8_22.io.enq.valid, _T_4181 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_4182 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4183 = and(_T_4182, account_for_buf_lens_Q) node _T_4184 = and(_T_4183, use_this_queue_23) connect Queue16_UInt8_23.io.enq.valid, _T_4184 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_4185 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4186 = and(_T_4185, account_for_buf_lens_Q) node _T_4187 = and(_T_4186, use_this_queue_24) connect Queue16_UInt8_24.io.enq.valid, _T_4187 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_4188 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4189 = and(_T_4188, account_for_buf_lens_Q) node _T_4190 = and(_T_4189, use_this_queue_25) connect Queue16_UInt8_25.io.enq.valid, _T_4190 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_4191 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4192 = and(_T_4191, account_for_buf_lens_Q) node _T_4193 = and(_T_4192, use_this_queue_26) connect Queue16_UInt8_26.io.enq.valid, _T_4193 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_4194 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4195 = and(_T_4194, account_for_buf_lens_Q) node _T_4196 = and(_T_4195, use_this_queue_27) connect Queue16_UInt8_27.io.enq.valid, _T_4196 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_4197 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4198 = and(_T_4197, account_for_buf_lens_Q) node _T_4199 = and(_T_4198, use_this_queue_28) connect Queue16_UInt8_28.io.enq.valid, _T_4199 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_4200 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4201 = and(_T_4200, account_for_buf_lens_Q) node _T_4202 = and(_T_4201, use_this_queue_29) connect Queue16_UInt8_29.io.enq.valid, _T_4202 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_4203 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4204 = and(_T_4203, account_for_buf_lens_Q) node _T_4205 = and(_T_4204, use_this_queue_30) connect Queue16_UInt8_30.io.enq.valid, _T_4205 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_4206 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4207 = and(_T_4206, account_for_buf_lens_Q) node _T_4208 = and(_T_4207, use_this_queue_31) connect Queue16_UInt8_31.io.enq.valid, _T_4208 when Queue16_UInt8.io.deq.valid : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_4209 = asUInt(reset) node _T_4210 = eq(_T_4209, UInt<1>(0h0)) when _T_4210 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_4211 = asUInt(reset) node _T_4212 = eq(_T_4211, UInt<1>(0h0)) when _T_4212 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h0), Queue16_UInt8.io.deq.bits) : printf_7 when Queue16_UInt8_1.io.deq.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_4213 = asUInt(reset) node _T_4214 = eq(_T_4213, UInt<1>(0h0)) when _T_4214 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_4215 = asUInt(reset) node _T_4216 = eq(_T_4215, UInt<1>(0h0)) when _T_4216 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h1), Queue16_UInt8_1.io.deq.bits) : printf_9 when Queue16_UInt8_2.io.deq.valid : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_4217 = asUInt(reset) node _T_4218 = eq(_T_4217, UInt<1>(0h0)) when _T_4218 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_4219 = asUInt(reset) node _T_4220 = eq(_T_4219, UInt<1>(0h0)) when _T_4220 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h2), Queue16_UInt8_2.io.deq.bits) : printf_11 when Queue16_UInt8_3.io.deq.valid : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_4221 = asUInt(reset) node _T_4222 = eq(_T_4221, UInt<1>(0h0)) when _T_4222 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_4223 = asUInt(reset) node _T_4224 = eq(_T_4223, UInt<1>(0h0)) when _T_4224 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h3), Queue16_UInt8_3.io.deq.bits) : printf_13 when Queue16_UInt8_4.io.deq.valid : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_4225 = asUInt(reset) node _T_4226 = eq(_T_4225, UInt<1>(0h0)) when _T_4226 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_4227 = asUInt(reset) node _T_4228 = eq(_T_4227, UInt<1>(0h0)) when _T_4228 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h4), Queue16_UInt8_4.io.deq.bits) : printf_15 when Queue16_UInt8_5.io.deq.valid : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_4229 = asUInt(reset) node _T_4230 = eq(_T_4229, UInt<1>(0h0)) when _T_4230 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_4231 = asUInt(reset) node _T_4232 = eq(_T_4231, UInt<1>(0h0)) when _T_4232 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h5), Queue16_UInt8_5.io.deq.bits) : printf_17 when Queue16_UInt8_6.io.deq.valid : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_4233 = asUInt(reset) node _T_4234 = eq(_T_4233, UInt<1>(0h0)) when _T_4234 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_4235 = asUInt(reset) node _T_4236 = eq(_T_4235, UInt<1>(0h0)) when _T_4236 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h6), Queue16_UInt8_6.io.deq.bits) : printf_19 when Queue16_UInt8_7.io.deq.valid : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_4237 = asUInt(reset) node _T_4238 = eq(_T_4237, UInt<1>(0h0)) when _T_4238 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_4239 = asUInt(reset) node _T_4240 = eq(_T_4239, UInt<1>(0h0)) when _T_4240 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h7), Queue16_UInt8_7.io.deq.bits) : printf_21 when Queue16_UInt8_8.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_4241 = asUInt(reset) node _T_4242 = eq(_T_4241, UInt<1>(0h0)) when _T_4242 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_4243 = asUInt(reset) node _T_4244 = eq(_T_4243, UInt<1>(0h0)) when _T_4244 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h8), Queue16_UInt8_8.io.deq.bits) : printf_23 when Queue16_UInt8_9.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_4245 = asUInt(reset) node _T_4246 = eq(_T_4245, UInt<1>(0h0)) when _T_4246 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_4247 = asUInt(reset) node _T_4248 = eq(_T_4247, UInt<1>(0h0)) when _T_4248 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h9), Queue16_UInt8_9.io.deq.bits) : printf_25 when Queue16_UInt8_10.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_4249 = asUInt(reset) node _T_4250 = eq(_T_4249, UInt<1>(0h0)) when _T_4250 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_4251 = asUInt(reset) node _T_4252 = eq(_T_4251, UInt<1>(0h0)) when _T_4252 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0ha), Queue16_UInt8_10.io.deq.bits) : printf_27 when Queue16_UInt8_11.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_4253 = asUInt(reset) node _T_4254 = eq(_T_4253, UInt<1>(0h0)) when _T_4254 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_4255 = asUInt(reset) node _T_4256 = eq(_T_4255, UInt<1>(0h0)) when _T_4256 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hb), Queue16_UInt8_11.io.deq.bits) : printf_29 when Queue16_UInt8_12.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_4257 = asUInt(reset) node _T_4258 = eq(_T_4257, UInt<1>(0h0)) when _T_4258 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_4259 = asUInt(reset) node _T_4260 = eq(_T_4259, UInt<1>(0h0)) when _T_4260 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hc), Queue16_UInt8_12.io.deq.bits) : printf_31 when Queue16_UInt8_13.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_4261 = asUInt(reset) node _T_4262 = eq(_T_4261, UInt<1>(0h0)) when _T_4262 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_4263 = asUInt(reset) node _T_4264 = eq(_T_4263, UInt<1>(0h0)) when _T_4264 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hd), Queue16_UInt8_13.io.deq.bits) : printf_33 when Queue16_UInt8_14.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_4265 = asUInt(reset) node _T_4266 = eq(_T_4265, UInt<1>(0h0)) when _T_4266 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_4267 = asUInt(reset) node _T_4268 = eq(_T_4267, UInt<1>(0h0)) when _T_4268 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0he), Queue16_UInt8_14.io.deq.bits) : printf_35 when Queue16_UInt8_15.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_4269 = asUInt(reset) node _T_4270 = eq(_T_4269, UInt<1>(0h0)) when _T_4270 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_4271 = asUInt(reset) node _T_4272 = eq(_T_4271, UInt<1>(0h0)) when _T_4272 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hf), Queue16_UInt8_15.io.deq.bits) : printf_37 when Queue16_UInt8_16.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_4273 = asUInt(reset) node _T_4274 = eq(_T_4273, UInt<1>(0h0)) when _T_4274 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_4275 = asUInt(reset) node _T_4276 = eq(_T_4275, UInt<1>(0h0)) when _T_4276 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h10), Queue16_UInt8_16.io.deq.bits) : printf_39 when Queue16_UInt8_17.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_4277 = asUInt(reset) node _T_4278 = eq(_T_4277, UInt<1>(0h0)) when _T_4278 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_4279 = asUInt(reset) node _T_4280 = eq(_T_4279, UInt<1>(0h0)) when _T_4280 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h11), Queue16_UInt8_17.io.deq.bits) : printf_41 when Queue16_UInt8_18.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_4281 = asUInt(reset) node _T_4282 = eq(_T_4281, UInt<1>(0h0)) when _T_4282 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_4283 = asUInt(reset) node _T_4284 = eq(_T_4283, UInt<1>(0h0)) when _T_4284 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h12), Queue16_UInt8_18.io.deq.bits) : printf_43 when Queue16_UInt8_19.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_4285 = asUInt(reset) node _T_4286 = eq(_T_4285, UInt<1>(0h0)) when _T_4286 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_4287 = asUInt(reset) node _T_4288 = eq(_T_4287, UInt<1>(0h0)) when _T_4288 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h13), Queue16_UInt8_19.io.deq.bits) : printf_45 when Queue16_UInt8_20.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_4289 = asUInt(reset) node _T_4290 = eq(_T_4289, UInt<1>(0h0)) when _T_4290 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_4291 = asUInt(reset) node _T_4292 = eq(_T_4291, UInt<1>(0h0)) when _T_4292 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h14), Queue16_UInt8_20.io.deq.bits) : printf_47 when Queue16_UInt8_21.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_4293 = asUInt(reset) node _T_4294 = eq(_T_4293, UInt<1>(0h0)) when _T_4294 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h15), Queue16_UInt8_21.io.deq.bits) : printf_49 when Queue16_UInt8_22.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_4297 = asUInt(reset) node _T_4298 = eq(_T_4297, UInt<1>(0h0)) when _T_4298 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_4299 = asUInt(reset) node _T_4300 = eq(_T_4299, UInt<1>(0h0)) when _T_4300 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h16), Queue16_UInt8_22.io.deq.bits) : printf_51 when Queue16_UInt8_23.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_4301 = asUInt(reset) node _T_4302 = eq(_T_4301, UInt<1>(0h0)) when _T_4302 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_4303 = asUInt(reset) node _T_4304 = eq(_T_4303, UInt<1>(0h0)) when _T_4304 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h17), Queue16_UInt8_23.io.deq.bits) : printf_53 when Queue16_UInt8_24.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_4305 = asUInt(reset) node _T_4306 = eq(_T_4305, UInt<1>(0h0)) when _T_4306 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_4307 = asUInt(reset) node _T_4308 = eq(_T_4307, UInt<1>(0h0)) when _T_4308 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h18), Queue16_UInt8_24.io.deq.bits) : printf_55 when Queue16_UInt8_25.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_4309 = asUInt(reset) node _T_4310 = eq(_T_4309, UInt<1>(0h0)) when _T_4310 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_4311 = asUInt(reset) node _T_4312 = eq(_T_4311, UInt<1>(0h0)) when _T_4312 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h19), Queue16_UInt8_25.io.deq.bits) : printf_57 when Queue16_UInt8_26.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_4313 = asUInt(reset) node _T_4314 = eq(_T_4313, UInt<1>(0h0)) when _T_4314 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_4315 = asUInt(reset) node _T_4316 = eq(_T_4315, UInt<1>(0h0)) when _T_4316 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1a), Queue16_UInt8_26.io.deq.bits) : printf_59 when Queue16_UInt8_27.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_4317 = asUInt(reset) node _T_4318 = eq(_T_4317, UInt<1>(0h0)) when _T_4318 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_4319 = asUInt(reset) node _T_4320 = eq(_T_4319, UInt<1>(0h0)) when _T_4320 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1b), Queue16_UInt8_27.io.deq.bits) : printf_61 when Queue16_UInt8_28.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_4321 = asUInt(reset) node _T_4322 = eq(_T_4321, UInt<1>(0h0)) when _T_4322 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_4323 = asUInt(reset) node _T_4324 = eq(_T_4323, UInt<1>(0h0)) when _T_4324 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1c), Queue16_UInt8_28.io.deq.bits) : printf_63 when Queue16_UInt8_29.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_4325 = asUInt(reset) node _T_4326 = eq(_T_4325, UInt<1>(0h0)) when _T_4326 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_4327 = asUInt(reset) node _T_4328 = eq(_T_4327, UInt<1>(0h0)) when _T_4328 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1d), Queue16_UInt8_29.io.deq.bits) : printf_65 when Queue16_UInt8_30.io.deq.valid : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_4329 = asUInt(reset) node _T_4330 = eq(_T_4329, UInt<1>(0h0)) when _T_4330 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_4331 = asUInt(reset) node _T_4332 = eq(_T_4331, UInt<1>(0h0)) when _T_4332 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1e), Queue16_UInt8_30.io.deq.bits) : printf_67 when Queue16_UInt8_31.io.deq.valid : regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_4333 = asUInt(reset) node _T_4334 = eq(_T_4333, UInt<1>(0h0)) when _T_4334 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_4335 = asUInt(reset) node _T_4336 = eq(_T_4335, UInt<1>(0h0)) when _T_4336 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1f), Queue16_UInt8_31.io.deq.bits) : printf_69 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue16_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue16_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue16_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue16_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue16_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue16_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue16_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue16_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue16_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue16_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue16_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue16_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue16_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue16_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue16_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue16_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue16_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue16_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue16_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue16_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue16_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue16_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue16_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue16_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue16_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue16_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue16_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue16_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue16_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue16_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue16_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue16_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_4337 = eq(UInt<1>(0h0), remapindex) when _T_4337 : connect remapVecData[0], Queue16_UInt8.io.deq.bits connect remapVecValids[0], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[0] node _T_4338 = eq(UInt<1>(0h1), remapindex) when _T_4338 : connect remapVecData[0], Queue16_UInt8_1.io.deq.bits connect remapVecValids[0], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_4339 = eq(UInt<2>(0h2), remapindex) when _T_4339 : connect remapVecData[0], Queue16_UInt8_2.io.deq.bits connect remapVecValids[0], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_4340 = eq(UInt<2>(0h3), remapindex) when _T_4340 : connect remapVecData[0], Queue16_UInt8_3.io.deq.bits connect remapVecValids[0], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_4341 = eq(UInt<3>(0h4), remapindex) when _T_4341 : connect remapVecData[0], Queue16_UInt8_4.io.deq.bits connect remapVecValids[0], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_4342 = eq(UInt<3>(0h5), remapindex) when _T_4342 : connect remapVecData[0], Queue16_UInt8_5.io.deq.bits connect remapVecValids[0], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_4343 = eq(UInt<3>(0h6), remapindex) when _T_4343 : connect remapVecData[0], Queue16_UInt8_6.io.deq.bits connect remapVecValids[0], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_4344 = eq(UInt<3>(0h7), remapindex) when _T_4344 : connect remapVecData[0], Queue16_UInt8_7.io.deq.bits connect remapVecValids[0], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_4345 = eq(UInt<4>(0h8), remapindex) when _T_4345 : connect remapVecData[0], Queue16_UInt8_8.io.deq.bits connect remapVecValids[0], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_4346 = eq(UInt<4>(0h9), remapindex) when _T_4346 : connect remapVecData[0], Queue16_UInt8_9.io.deq.bits connect remapVecValids[0], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_4347 = eq(UInt<4>(0ha), remapindex) when _T_4347 : connect remapVecData[0], Queue16_UInt8_10.io.deq.bits connect remapVecValids[0], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_4348 = eq(UInt<4>(0hb), remapindex) when _T_4348 : connect remapVecData[0], Queue16_UInt8_11.io.deq.bits connect remapVecValids[0], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_4349 = eq(UInt<4>(0hc), remapindex) when _T_4349 : connect remapVecData[0], Queue16_UInt8_12.io.deq.bits connect remapVecValids[0], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_4350 = eq(UInt<4>(0hd), remapindex) when _T_4350 : connect remapVecData[0], Queue16_UInt8_13.io.deq.bits connect remapVecValids[0], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_4351 = eq(UInt<4>(0he), remapindex) when _T_4351 : connect remapVecData[0], Queue16_UInt8_14.io.deq.bits connect remapVecValids[0], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_4352 = eq(UInt<4>(0hf), remapindex) when _T_4352 : connect remapVecData[0], Queue16_UInt8_15.io.deq.bits connect remapVecValids[0], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_4353 = eq(UInt<5>(0h10), remapindex) when _T_4353 : connect remapVecData[0], Queue16_UInt8_16.io.deq.bits connect remapVecValids[0], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_4354 = eq(UInt<5>(0h11), remapindex) when _T_4354 : connect remapVecData[0], Queue16_UInt8_17.io.deq.bits connect remapVecValids[0], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_4355 = eq(UInt<5>(0h12), remapindex) when _T_4355 : connect remapVecData[0], Queue16_UInt8_18.io.deq.bits connect remapVecValids[0], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_4356 = eq(UInt<5>(0h13), remapindex) when _T_4356 : connect remapVecData[0], Queue16_UInt8_19.io.deq.bits connect remapVecValids[0], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_4357 = eq(UInt<5>(0h14), remapindex) when _T_4357 : connect remapVecData[0], Queue16_UInt8_20.io.deq.bits connect remapVecValids[0], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_4358 = eq(UInt<5>(0h15), remapindex) when _T_4358 : connect remapVecData[0], Queue16_UInt8_21.io.deq.bits connect remapVecValids[0], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_4359 = eq(UInt<5>(0h16), remapindex) when _T_4359 : connect remapVecData[0], Queue16_UInt8_22.io.deq.bits connect remapVecValids[0], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_4360 = eq(UInt<5>(0h17), remapindex) when _T_4360 : connect remapVecData[0], Queue16_UInt8_23.io.deq.bits connect remapVecValids[0], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_4361 = eq(UInt<5>(0h18), remapindex) when _T_4361 : connect remapVecData[0], Queue16_UInt8_24.io.deq.bits connect remapVecValids[0], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_4362 = eq(UInt<5>(0h19), remapindex) when _T_4362 : connect remapVecData[0], Queue16_UInt8_25.io.deq.bits connect remapVecValids[0], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_4363 = eq(UInt<5>(0h1a), remapindex) when _T_4363 : connect remapVecData[0], Queue16_UInt8_26.io.deq.bits connect remapVecValids[0], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_4364 = eq(UInt<5>(0h1b), remapindex) when _T_4364 : connect remapVecData[0], Queue16_UInt8_27.io.deq.bits connect remapVecValids[0], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_4365 = eq(UInt<5>(0h1c), remapindex) when _T_4365 : connect remapVecData[0], Queue16_UInt8_28.io.deq.bits connect remapVecValids[0], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_4366 = eq(UInt<5>(0h1d), remapindex) when _T_4366 : connect remapVecData[0], Queue16_UInt8_29.io.deq.bits connect remapVecValids[0], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_4367 = eq(UInt<5>(0h1e), remapindex) when _T_4367 : connect remapVecData[0], Queue16_UInt8_30.io.deq.bits connect remapVecValids[0], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_4368 = eq(UInt<5>(0h1f), remapindex) when _T_4368 : connect remapVecData[0], Queue16_UInt8_31.io.deq.bits connect remapVecValids[0], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_4369 = eq(UInt<1>(0h0), remapindex_1) when _T_4369 : connect remapVecData[1], Queue16_UInt8.io.deq.bits connect remapVecValids[1], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[1] node _T_4370 = eq(UInt<1>(0h1), remapindex_1) when _T_4370 : connect remapVecData[1], Queue16_UInt8_1.io.deq.bits connect remapVecValids[1], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_4371 = eq(UInt<2>(0h2), remapindex_1) when _T_4371 : connect remapVecData[1], Queue16_UInt8_2.io.deq.bits connect remapVecValids[1], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_4372 = eq(UInt<2>(0h3), remapindex_1) when _T_4372 : connect remapVecData[1], Queue16_UInt8_3.io.deq.bits connect remapVecValids[1], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_4373 = eq(UInt<3>(0h4), remapindex_1) when _T_4373 : connect remapVecData[1], Queue16_UInt8_4.io.deq.bits connect remapVecValids[1], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_4374 = eq(UInt<3>(0h5), remapindex_1) when _T_4374 : connect remapVecData[1], Queue16_UInt8_5.io.deq.bits connect remapVecValids[1], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_4375 = eq(UInt<3>(0h6), remapindex_1) when _T_4375 : connect remapVecData[1], Queue16_UInt8_6.io.deq.bits connect remapVecValids[1], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_4376 = eq(UInt<3>(0h7), remapindex_1) when _T_4376 : connect remapVecData[1], Queue16_UInt8_7.io.deq.bits connect remapVecValids[1], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_4377 = eq(UInt<4>(0h8), remapindex_1) when _T_4377 : connect remapVecData[1], Queue16_UInt8_8.io.deq.bits connect remapVecValids[1], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_4378 = eq(UInt<4>(0h9), remapindex_1) when _T_4378 : connect remapVecData[1], Queue16_UInt8_9.io.deq.bits connect remapVecValids[1], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_4379 = eq(UInt<4>(0ha), remapindex_1) when _T_4379 : connect remapVecData[1], Queue16_UInt8_10.io.deq.bits connect remapVecValids[1], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_4380 = eq(UInt<4>(0hb), remapindex_1) when _T_4380 : connect remapVecData[1], Queue16_UInt8_11.io.deq.bits connect remapVecValids[1], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_4381 = eq(UInt<4>(0hc), remapindex_1) when _T_4381 : connect remapVecData[1], Queue16_UInt8_12.io.deq.bits connect remapVecValids[1], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_4382 = eq(UInt<4>(0hd), remapindex_1) when _T_4382 : connect remapVecData[1], Queue16_UInt8_13.io.deq.bits connect remapVecValids[1], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_4383 = eq(UInt<4>(0he), remapindex_1) when _T_4383 : connect remapVecData[1], Queue16_UInt8_14.io.deq.bits connect remapVecValids[1], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_4384 = eq(UInt<4>(0hf), remapindex_1) when _T_4384 : connect remapVecData[1], Queue16_UInt8_15.io.deq.bits connect remapVecValids[1], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_4385 = eq(UInt<5>(0h10), remapindex_1) when _T_4385 : connect remapVecData[1], Queue16_UInt8_16.io.deq.bits connect remapVecValids[1], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_4386 = eq(UInt<5>(0h11), remapindex_1) when _T_4386 : connect remapVecData[1], Queue16_UInt8_17.io.deq.bits connect remapVecValids[1], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_4387 = eq(UInt<5>(0h12), remapindex_1) when _T_4387 : connect remapVecData[1], Queue16_UInt8_18.io.deq.bits connect remapVecValids[1], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_4388 = eq(UInt<5>(0h13), remapindex_1) when _T_4388 : connect remapVecData[1], Queue16_UInt8_19.io.deq.bits connect remapVecValids[1], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_4389 = eq(UInt<5>(0h14), remapindex_1) when _T_4389 : connect remapVecData[1], Queue16_UInt8_20.io.deq.bits connect remapVecValids[1], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_4390 = eq(UInt<5>(0h15), remapindex_1) when _T_4390 : connect remapVecData[1], Queue16_UInt8_21.io.deq.bits connect remapVecValids[1], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_4391 = eq(UInt<5>(0h16), remapindex_1) when _T_4391 : connect remapVecData[1], Queue16_UInt8_22.io.deq.bits connect remapVecValids[1], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_4392 = eq(UInt<5>(0h17), remapindex_1) when _T_4392 : connect remapVecData[1], Queue16_UInt8_23.io.deq.bits connect remapVecValids[1], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_4393 = eq(UInt<5>(0h18), remapindex_1) when _T_4393 : connect remapVecData[1], Queue16_UInt8_24.io.deq.bits connect remapVecValids[1], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_4394 = eq(UInt<5>(0h19), remapindex_1) when _T_4394 : connect remapVecData[1], Queue16_UInt8_25.io.deq.bits connect remapVecValids[1], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_4395 = eq(UInt<5>(0h1a), remapindex_1) when _T_4395 : connect remapVecData[1], Queue16_UInt8_26.io.deq.bits connect remapVecValids[1], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_4396 = eq(UInt<5>(0h1b), remapindex_1) when _T_4396 : connect remapVecData[1], Queue16_UInt8_27.io.deq.bits connect remapVecValids[1], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_4397 = eq(UInt<5>(0h1c), remapindex_1) when _T_4397 : connect remapVecData[1], Queue16_UInt8_28.io.deq.bits connect remapVecValids[1], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_4398 = eq(UInt<5>(0h1d), remapindex_1) when _T_4398 : connect remapVecData[1], Queue16_UInt8_29.io.deq.bits connect remapVecValids[1], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_4399 = eq(UInt<5>(0h1e), remapindex_1) when _T_4399 : connect remapVecData[1], Queue16_UInt8_30.io.deq.bits connect remapVecValids[1], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_4400 = eq(UInt<5>(0h1f), remapindex_1) when _T_4400 : connect remapVecData[1], Queue16_UInt8_31.io.deq.bits connect remapVecValids[1], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_4401 = eq(UInt<1>(0h0), remapindex_2) when _T_4401 : connect remapVecData[2], Queue16_UInt8.io.deq.bits connect remapVecValids[2], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[2] node _T_4402 = eq(UInt<1>(0h1), remapindex_2) when _T_4402 : connect remapVecData[2], Queue16_UInt8_1.io.deq.bits connect remapVecValids[2], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_4403 = eq(UInt<2>(0h2), remapindex_2) when _T_4403 : connect remapVecData[2], Queue16_UInt8_2.io.deq.bits connect remapVecValids[2], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_4404 = eq(UInt<2>(0h3), remapindex_2) when _T_4404 : connect remapVecData[2], Queue16_UInt8_3.io.deq.bits connect remapVecValids[2], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_4405 = eq(UInt<3>(0h4), remapindex_2) when _T_4405 : connect remapVecData[2], Queue16_UInt8_4.io.deq.bits connect remapVecValids[2], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_4406 = eq(UInt<3>(0h5), remapindex_2) when _T_4406 : connect remapVecData[2], Queue16_UInt8_5.io.deq.bits connect remapVecValids[2], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_4407 = eq(UInt<3>(0h6), remapindex_2) when _T_4407 : connect remapVecData[2], Queue16_UInt8_6.io.deq.bits connect remapVecValids[2], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_4408 = eq(UInt<3>(0h7), remapindex_2) when _T_4408 : connect remapVecData[2], Queue16_UInt8_7.io.deq.bits connect remapVecValids[2], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_4409 = eq(UInt<4>(0h8), remapindex_2) when _T_4409 : connect remapVecData[2], Queue16_UInt8_8.io.deq.bits connect remapVecValids[2], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_4410 = eq(UInt<4>(0h9), remapindex_2) when _T_4410 : connect remapVecData[2], Queue16_UInt8_9.io.deq.bits connect remapVecValids[2], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_4411 = eq(UInt<4>(0ha), remapindex_2) when _T_4411 : connect remapVecData[2], Queue16_UInt8_10.io.deq.bits connect remapVecValids[2], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_4412 = eq(UInt<4>(0hb), remapindex_2) when _T_4412 : connect remapVecData[2], Queue16_UInt8_11.io.deq.bits connect remapVecValids[2], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_4413 = eq(UInt<4>(0hc), remapindex_2) when _T_4413 : connect remapVecData[2], Queue16_UInt8_12.io.deq.bits connect remapVecValids[2], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_4414 = eq(UInt<4>(0hd), remapindex_2) when _T_4414 : connect remapVecData[2], Queue16_UInt8_13.io.deq.bits connect remapVecValids[2], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_4415 = eq(UInt<4>(0he), remapindex_2) when _T_4415 : connect remapVecData[2], Queue16_UInt8_14.io.deq.bits connect remapVecValids[2], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_4416 = eq(UInt<4>(0hf), remapindex_2) when _T_4416 : connect remapVecData[2], Queue16_UInt8_15.io.deq.bits connect remapVecValids[2], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_4417 = eq(UInt<5>(0h10), remapindex_2) when _T_4417 : connect remapVecData[2], Queue16_UInt8_16.io.deq.bits connect remapVecValids[2], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_4418 = eq(UInt<5>(0h11), remapindex_2) when _T_4418 : connect remapVecData[2], Queue16_UInt8_17.io.deq.bits connect remapVecValids[2], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_4419 = eq(UInt<5>(0h12), remapindex_2) when _T_4419 : connect remapVecData[2], Queue16_UInt8_18.io.deq.bits connect remapVecValids[2], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_4420 = eq(UInt<5>(0h13), remapindex_2) when _T_4420 : connect remapVecData[2], Queue16_UInt8_19.io.deq.bits connect remapVecValids[2], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_4421 = eq(UInt<5>(0h14), remapindex_2) when _T_4421 : connect remapVecData[2], Queue16_UInt8_20.io.deq.bits connect remapVecValids[2], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_4422 = eq(UInt<5>(0h15), remapindex_2) when _T_4422 : connect remapVecData[2], Queue16_UInt8_21.io.deq.bits connect remapVecValids[2], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_4423 = eq(UInt<5>(0h16), remapindex_2) when _T_4423 : connect remapVecData[2], Queue16_UInt8_22.io.deq.bits connect remapVecValids[2], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_4424 = eq(UInt<5>(0h17), remapindex_2) when _T_4424 : connect remapVecData[2], Queue16_UInt8_23.io.deq.bits connect remapVecValids[2], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_4425 = eq(UInt<5>(0h18), remapindex_2) when _T_4425 : connect remapVecData[2], Queue16_UInt8_24.io.deq.bits connect remapVecValids[2], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_4426 = eq(UInt<5>(0h19), remapindex_2) when _T_4426 : connect remapVecData[2], Queue16_UInt8_25.io.deq.bits connect remapVecValids[2], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_4427 = eq(UInt<5>(0h1a), remapindex_2) when _T_4427 : connect remapVecData[2], Queue16_UInt8_26.io.deq.bits connect remapVecValids[2], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_4428 = eq(UInt<5>(0h1b), remapindex_2) when _T_4428 : connect remapVecData[2], Queue16_UInt8_27.io.deq.bits connect remapVecValids[2], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_4429 = eq(UInt<5>(0h1c), remapindex_2) when _T_4429 : connect remapVecData[2], Queue16_UInt8_28.io.deq.bits connect remapVecValids[2], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_4430 = eq(UInt<5>(0h1d), remapindex_2) when _T_4430 : connect remapVecData[2], Queue16_UInt8_29.io.deq.bits connect remapVecValids[2], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_4431 = eq(UInt<5>(0h1e), remapindex_2) when _T_4431 : connect remapVecData[2], Queue16_UInt8_30.io.deq.bits connect remapVecValids[2], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_4432 = eq(UInt<5>(0h1f), remapindex_2) when _T_4432 : connect remapVecData[2], Queue16_UInt8_31.io.deq.bits connect remapVecValids[2], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_4433 = eq(UInt<1>(0h0), remapindex_3) when _T_4433 : connect remapVecData[3], Queue16_UInt8.io.deq.bits connect remapVecValids[3], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[3] node _T_4434 = eq(UInt<1>(0h1), remapindex_3) when _T_4434 : connect remapVecData[3], Queue16_UInt8_1.io.deq.bits connect remapVecValids[3], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_4435 = eq(UInt<2>(0h2), remapindex_3) when _T_4435 : connect remapVecData[3], Queue16_UInt8_2.io.deq.bits connect remapVecValids[3], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_4436 = eq(UInt<2>(0h3), remapindex_3) when _T_4436 : connect remapVecData[3], Queue16_UInt8_3.io.deq.bits connect remapVecValids[3], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_4437 = eq(UInt<3>(0h4), remapindex_3) when _T_4437 : connect remapVecData[3], Queue16_UInt8_4.io.deq.bits connect remapVecValids[3], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_4438 = eq(UInt<3>(0h5), remapindex_3) when _T_4438 : connect remapVecData[3], Queue16_UInt8_5.io.deq.bits connect remapVecValids[3], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_4439 = eq(UInt<3>(0h6), remapindex_3) when _T_4439 : connect remapVecData[3], Queue16_UInt8_6.io.deq.bits connect remapVecValids[3], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_4440 = eq(UInt<3>(0h7), remapindex_3) when _T_4440 : connect remapVecData[3], Queue16_UInt8_7.io.deq.bits connect remapVecValids[3], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_4441 = eq(UInt<4>(0h8), remapindex_3) when _T_4441 : connect remapVecData[3], Queue16_UInt8_8.io.deq.bits connect remapVecValids[3], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_4442 = eq(UInt<4>(0h9), remapindex_3) when _T_4442 : connect remapVecData[3], Queue16_UInt8_9.io.deq.bits connect remapVecValids[3], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_4443 = eq(UInt<4>(0ha), remapindex_3) when _T_4443 : connect remapVecData[3], Queue16_UInt8_10.io.deq.bits connect remapVecValids[3], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_4444 = eq(UInt<4>(0hb), remapindex_3) when _T_4444 : connect remapVecData[3], Queue16_UInt8_11.io.deq.bits connect remapVecValids[3], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_4445 = eq(UInt<4>(0hc), remapindex_3) when _T_4445 : connect remapVecData[3], Queue16_UInt8_12.io.deq.bits connect remapVecValids[3], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_4446 = eq(UInt<4>(0hd), remapindex_3) when _T_4446 : connect remapVecData[3], Queue16_UInt8_13.io.deq.bits connect remapVecValids[3], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_4447 = eq(UInt<4>(0he), remapindex_3) when _T_4447 : connect remapVecData[3], Queue16_UInt8_14.io.deq.bits connect remapVecValids[3], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_4448 = eq(UInt<4>(0hf), remapindex_3) when _T_4448 : connect remapVecData[3], Queue16_UInt8_15.io.deq.bits connect remapVecValids[3], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_4449 = eq(UInt<5>(0h10), remapindex_3) when _T_4449 : connect remapVecData[3], Queue16_UInt8_16.io.deq.bits connect remapVecValids[3], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_4450 = eq(UInt<5>(0h11), remapindex_3) when _T_4450 : connect remapVecData[3], Queue16_UInt8_17.io.deq.bits connect remapVecValids[3], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_4451 = eq(UInt<5>(0h12), remapindex_3) when _T_4451 : connect remapVecData[3], Queue16_UInt8_18.io.deq.bits connect remapVecValids[3], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_4452 = eq(UInt<5>(0h13), remapindex_3) when _T_4452 : connect remapVecData[3], Queue16_UInt8_19.io.deq.bits connect remapVecValids[3], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_4453 = eq(UInt<5>(0h14), remapindex_3) when _T_4453 : connect remapVecData[3], Queue16_UInt8_20.io.deq.bits connect remapVecValids[3], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_4454 = eq(UInt<5>(0h15), remapindex_3) when _T_4454 : connect remapVecData[3], Queue16_UInt8_21.io.deq.bits connect remapVecValids[3], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_4455 = eq(UInt<5>(0h16), remapindex_3) when _T_4455 : connect remapVecData[3], Queue16_UInt8_22.io.deq.bits connect remapVecValids[3], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_4456 = eq(UInt<5>(0h17), remapindex_3) when _T_4456 : connect remapVecData[3], Queue16_UInt8_23.io.deq.bits connect remapVecValids[3], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_4457 = eq(UInt<5>(0h18), remapindex_3) when _T_4457 : connect remapVecData[3], Queue16_UInt8_24.io.deq.bits connect remapVecValids[3], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_4458 = eq(UInt<5>(0h19), remapindex_3) when _T_4458 : connect remapVecData[3], Queue16_UInt8_25.io.deq.bits connect remapVecValids[3], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_4459 = eq(UInt<5>(0h1a), remapindex_3) when _T_4459 : connect remapVecData[3], Queue16_UInt8_26.io.deq.bits connect remapVecValids[3], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_4460 = eq(UInt<5>(0h1b), remapindex_3) when _T_4460 : connect remapVecData[3], Queue16_UInt8_27.io.deq.bits connect remapVecValids[3], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_4461 = eq(UInt<5>(0h1c), remapindex_3) when _T_4461 : connect remapVecData[3], Queue16_UInt8_28.io.deq.bits connect remapVecValids[3], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_4462 = eq(UInt<5>(0h1d), remapindex_3) when _T_4462 : connect remapVecData[3], Queue16_UInt8_29.io.deq.bits connect remapVecValids[3], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_4463 = eq(UInt<5>(0h1e), remapindex_3) when _T_4463 : connect remapVecData[3], Queue16_UInt8_30.io.deq.bits connect remapVecValids[3], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_4464 = eq(UInt<5>(0h1f), remapindex_3) when _T_4464 : connect remapVecData[3], Queue16_UInt8_31.io.deq.bits connect remapVecValids[3], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_4465 = eq(UInt<1>(0h0), remapindex_4) when _T_4465 : connect remapVecData[4], Queue16_UInt8.io.deq.bits connect remapVecValids[4], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[4] node _T_4466 = eq(UInt<1>(0h1), remapindex_4) when _T_4466 : connect remapVecData[4], Queue16_UInt8_1.io.deq.bits connect remapVecValids[4], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_4467 = eq(UInt<2>(0h2), remapindex_4) when _T_4467 : connect remapVecData[4], Queue16_UInt8_2.io.deq.bits connect remapVecValids[4], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_4468 = eq(UInt<2>(0h3), remapindex_4) when _T_4468 : connect remapVecData[4], Queue16_UInt8_3.io.deq.bits connect remapVecValids[4], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_4469 = eq(UInt<3>(0h4), remapindex_4) when _T_4469 : connect remapVecData[4], Queue16_UInt8_4.io.deq.bits connect remapVecValids[4], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_4470 = eq(UInt<3>(0h5), remapindex_4) when _T_4470 : connect remapVecData[4], Queue16_UInt8_5.io.deq.bits connect remapVecValids[4], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_4471 = eq(UInt<3>(0h6), remapindex_4) when _T_4471 : connect remapVecData[4], Queue16_UInt8_6.io.deq.bits connect remapVecValids[4], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_4472 = eq(UInt<3>(0h7), remapindex_4) when _T_4472 : connect remapVecData[4], Queue16_UInt8_7.io.deq.bits connect remapVecValids[4], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_4473 = eq(UInt<4>(0h8), remapindex_4) when _T_4473 : connect remapVecData[4], Queue16_UInt8_8.io.deq.bits connect remapVecValids[4], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_4474 = eq(UInt<4>(0h9), remapindex_4) when _T_4474 : connect remapVecData[4], Queue16_UInt8_9.io.deq.bits connect remapVecValids[4], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_4475 = eq(UInt<4>(0ha), remapindex_4) when _T_4475 : connect remapVecData[4], Queue16_UInt8_10.io.deq.bits connect remapVecValids[4], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_4476 = eq(UInt<4>(0hb), remapindex_4) when _T_4476 : connect remapVecData[4], Queue16_UInt8_11.io.deq.bits connect remapVecValids[4], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_4477 = eq(UInt<4>(0hc), remapindex_4) when _T_4477 : connect remapVecData[4], Queue16_UInt8_12.io.deq.bits connect remapVecValids[4], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_4478 = eq(UInt<4>(0hd), remapindex_4) when _T_4478 : connect remapVecData[4], Queue16_UInt8_13.io.deq.bits connect remapVecValids[4], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_4479 = eq(UInt<4>(0he), remapindex_4) when _T_4479 : connect remapVecData[4], Queue16_UInt8_14.io.deq.bits connect remapVecValids[4], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_4480 = eq(UInt<4>(0hf), remapindex_4) when _T_4480 : connect remapVecData[4], Queue16_UInt8_15.io.deq.bits connect remapVecValids[4], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_4481 = eq(UInt<5>(0h10), remapindex_4) when _T_4481 : connect remapVecData[4], Queue16_UInt8_16.io.deq.bits connect remapVecValids[4], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_4482 = eq(UInt<5>(0h11), remapindex_4) when _T_4482 : connect remapVecData[4], Queue16_UInt8_17.io.deq.bits connect remapVecValids[4], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_4483 = eq(UInt<5>(0h12), remapindex_4) when _T_4483 : connect remapVecData[4], Queue16_UInt8_18.io.deq.bits connect remapVecValids[4], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_4484 = eq(UInt<5>(0h13), remapindex_4) when _T_4484 : connect remapVecData[4], Queue16_UInt8_19.io.deq.bits connect remapVecValids[4], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_4485 = eq(UInt<5>(0h14), remapindex_4) when _T_4485 : connect remapVecData[4], Queue16_UInt8_20.io.deq.bits connect remapVecValids[4], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_4486 = eq(UInt<5>(0h15), remapindex_4) when _T_4486 : connect remapVecData[4], Queue16_UInt8_21.io.deq.bits connect remapVecValids[4], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_4487 = eq(UInt<5>(0h16), remapindex_4) when _T_4487 : connect remapVecData[4], Queue16_UInt8_22.io.deq.bits connect remapVecValids[4], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_4488 = eq(UInt<5>(0h17), remapindex_4) when _T_4488 : connect remapVecData[4], Queue16_UInt8_23.io.deq.bits connect remapVecValids[4], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_4489 = eq(UInt<5>(0h18), remapindex_4) when _T_4489 : connect remapVecData[4], Queue16_UInt8_24.io.deq.bits connect remapVecValids[4], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_4490 = eq(UInt<5>(0h19), remapindex_4) when _T_4490 : connect remapVecData[4], Queue16_UInt8_25.io.deq.bits connect remapVecValids[4], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_4491 = eq(UInt<5>(0h1a), remapindex_4) when _T_4491 : connect remapVecData[4], Queue16_UInt8_26.io.deq.bits connect remapVecValids[4], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_4492 = eq(UInt<5>(0h1b), remapindex_4) when _T_4492 : connect remapVecData[4], Queue16_UInt8_27.io.deq.bits connect remapVecValids[4], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_4493 = eq(UInt<5>(0h1c), remapindex_4) when _T_4493 : connect remapVecData[4], Queue16_UInt8_28.io.deq.bits connect remapVecValids[4], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_4494 = eq(UInt<5>(0h1d), remapindex_4) when _T_4494 : connect remapVecData[4], Queue16_UInt8_29.io.deq.bits connect remapVecValids[4], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_4495 = eq(UInt<5>(0h1e), remapindex_4) when _T_4495 : connect remapVecData[4], Queue16_UInt8_30.io.deq.bits connect remapVecValids[4], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_4496 = eq(UInt<5>(0h1f), remapindex_4) when _T_4496 : connect remapVecData[4], Queue16_UInt8_31.io.deq.bits connect remapVecValids[4], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_4497 = eq(UInt<1>(0h0), remapindex_5) when _T_4497 : connect remapVecData[5], Queue16_UInt8.io.deq.bits connect remapVecValids[5], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[5] node _T_4498 = eq(UInt<1>(0h1), remapindex_5) when _T_4498 : connect remapVecData[5], Queue16_UInt8_1.io.deq.bits connect remapVecValids[5], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_4499 = eq(UInt<2>(0h2), remapindex_5) when _T_4499 : connect remapVecData[5], Queue16_UInt8_2.io.deq.bits connect remapVecValids[5], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_4500 = eq(UInt<2>(0h3), remapindex_5) when _T_4500 : connect remapVecData[5], Queue16_UInt8_3.io.deq.bits connect remapVecValids[5], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_4501 = eq(UInt<3>(0h4), remapindex_5) when _T_4501 : connect remapVecData[5], Queue16_UInt8_4.io.deq.bits connect remapVecValids[5], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_4502 = eq(UInt<3>(0h5), remapindex_5) when _T_4502 : connect remapVecData[5], Queue16_UInt8_5.io.deq.bits connect remapVecValids[5], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_4503 = eq(UInt<3>(0h6), remapindex_5) when _T_4503 : connect remapVecData[5], Queue16_UInt8_6.io.deq.bits connect remapVecValids[5], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_4504 = eq(UInt<3>(0h7), remapindex_5) when _T_4504 : connect remapVecData[5], Queue16_UInt8_7.io.deq.bits connect remapVecValids[5], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_4505 = eq(UInt<4>(0h8), remapindex_5) when _T_4505 : connect remapVecData[5], Queue16_UInt8_8.io.deq.bits connect remapVecValids[5], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_4506 = eq(UInt<4>(0h9), remapindex_5) when _T_4506 : connect remapVecData[5], Queue16_UInt8_9.io.deq.bits connect remapVecValids[5], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_4507 = eq(UInt<4>(0ha), remapindex_5) when _T_4507 : connect remapVecData[5], Queue16_UInt8_10.io.deq.bits connect remapVecValids[5], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_4508 = eq(UInt<4>(0hb), remapindex_5) when _T_4508 : connect remapVecData[5], Queue16_UInt8_11.io.deq.bits connect remapVecValids[5], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_4509 = eq(UInt<4>(0hc), remapindex_5) when _T_4509 : connect remapVecData[5], Queue16_UInt8_12.io.deq.bits connect remapVecValids[5], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_4510 = eq(UInt<4>(0hd), remapindex_5) when _T_4510 : connect remapVecData[5], Queue16_UInt8_13.io.deq.bits connect remapVecValids[5], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_4511 = eq(UInt<4>(0he), remapindex_5) when _T_4511 : connect remapVecData[5], Queue16_UInt8_14.io.deq.bits connect remapVecValids[5], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_4512 = eq(UInt<4>(0hf), remapindex_5) when _T_4512 : connect remapVecData[5], Queue16_UInt8_15.io.deq.bits connect remapVecValids[5], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_4513 = eq(UInt<5>(0h10), remapindex_5) when _T_4513 : connect remapVecData[5], Queue16_UInt8_16.io.deq.bits connect remapVecValids[5], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_4514 = eq(UInt<5>(0h11), remapindex_5) when _T_4514 : connect remapVecData[5], Queue16_UInt8_17.io.deq.bits connect remapVecValids[5], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_4515 = eq(UInt<5>(0h12), remapindex_5) when _T_4515 : connect remapVecData[5], Queue16_UInt8_18.io.deq.bits connect remapVecValids[5], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_4516 = eq(UInt<5>(0h13), remapindex_5) when _T_4516 : connect remapVecData[5], Queue16_UInt8_19.io.deq.bits connect remapVecValids[5], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_4517 = eq(UInt<5>(0h14), remapindex_5) when _T_4517 : connect remapVecData[5], Queue16_UInt8_20.io.deq.bits connect remapVecValids[5], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_4518 = eq(UInt<5>(0h15), remapindex_5) when _T_4518 : connect remapVecData[5], Queue16_UInt8_21.io.deq.bits connect remapVecValids[5], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_4519 = eq(UInt<5>(0h16), remapindex_5) when _T_4519 : connect remapVecData[5], Queue16_UInt8_22.io.deq.bits connect remapVecValids[5], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_4520 = eq(UInt<5>(0h17), remapindex_5) when _T_4520 : connect remapVecData[5], Queue16_UInt8_23.io.deq.bits connect remapVecValids[5], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_4521 = eq(UInt<5>(0h18), remapindex_5) when _T_4521 : connect remapVecData[5], Queue16_UInt8_24.io.deq.bits connect remapVecValids[5], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_4522 = eq(UInt<5>(0h19), remapindex_5) when _T_4522 : connect remapVecData[5], Queue16_UInt8_25.io.deq.bits connect remapVecValids[5], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_4523 = eq(UInt<5>(0h1a), remapindex_5) when _T_4523 : connect remapVecData[5], Queue16_UInt8_26.io.deq.bits connect remapVecValids[5], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_4524 = eq(UInt<5>(0h1b), remapindex_5) when _T_4524 : connect remapVecData[5], Queue16_UInt8_27.io.deq.bits connect remapVecValids[5], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_4525 = eq(UInt<5>(0h1c), remapindex_5) when _T_4525 : connect remapVecData[5], Queue16_UInt8_28.io.deq.bits connect remapVecValids[5], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_4526 = eq(UInt<5>(0h1d), remapindex_5) when _T_4526 : connect remapVecData[5], Queue16_UInt8_29.io.deq.bits connect remapVecValids[5], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_4527 = eq(UInt<5>(0h1e), remapindex_5) when _T_4527 : connect remapVecData[5], Queue16_UInt8_30.io.deq.bits connect remapVecValids[5], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_4528 = eq(UInt<5>(0h1f), remapindex_5) when _T_4528 : connect remapVecData[5], Queue16_UInt8_31.io.deq.bits connect remapVecValids[5], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_4529 = eq(UInt<1>(0h0), remapindex_6) when _T_4529 : connect remapVecData[6], Queue16_UInt8.io.deq.bits connect remapVecValids[6], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[6] node _T_4530 = eq(UInt<1>(0h1), remapindex_6) when _T_4530 : connect remapVecData[6], Queue16_UInt8_1.io.deq.bits connect remapVecValids[6], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_4531 = eq(UInt<2>(0h2), remapindex_6) when _T_4531 : connect remapVecData[6], Queue16_UInt8_2.io.deq.bits connect remapVecValids[6], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_4532 = eq(UInt<2>(0h3), remapindex_6) when _T_4532 : connect remapVecData[6], Queue16_UInt8_3.io.deq.bits connect remapVecValids[6], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_4533 = eq(UInt<3>(0h4), remapindex_6) when _T_4533 : connect remapVecData[6], Queue16_UInt8_4.io.deq.bits connect remapVecValids[6], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_4534 = eq(UInt<3>(0h5), remapindex_6) when _T_4534 : connect remapVecData[6], Queue16_UInt8_5.io.deq.bits connect remapVecValids[6], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_4535 = eq(UInt<3>(0h6), remapindex_6) when _T_4535 : connect remapVecData[6], Queue16_UInt8_6.io.deq.bits connect remapVecValids[6], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_4536 = eq(UInt<3>(0h7), remapindex_6) when _T_4536 : connect remapVecData[6], Queue16_UInt8_7.io.deq.bits connect remapVecValids[6], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_4537 = eq(UInt<4>(0h8), remapindex_6) when _T_4537 : connect remapVecData[6], Queue16_UInt8_8.io.deq.bits connect remapVecValids[6], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_4538 = eq(UInt<4>(0h9), remapindex_6) when _T_4538 : connect remapVecData[6], Queue16_UInt8_9.io.deq.bits connect remapVecValids[6], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_4539 = eq(UInt<4>(0ha), remapindex_6) when _T_4539 : connect remapVecData[6], Queue16_UInt8_10.io.deq.bits connect remapVecValids[6], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_4540 = eq(UInt<4>(0hb), remapindex_6) when _T_4540 : connect remapVecData[6], Queue16_UInt8_11.io.deq.bits connect remapVecValids[6], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_4541 = eq(UInt<4>(0hc), remapindex_6) when _T_4541 : connect remapVecData[6], Queue16_UInt8_12.io.deq.bits connect remapVecValids[6], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_4542 = eq(UInt<4>(0hd), remapindex_6) when _T_4542 : connect remapVecData[6], Queue16_UInt8_13.io.deq.bits connect remapVecValids[6], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_4543 = eq(UInt<4>(0he), remapindex_6) when _T_4543 : connect remapVecData[6], Queue16_UInt8_14.io.deq.bits connect remapVecValids[6], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_4544 = eq(UInt<4>(0hf), remapindex_6) when _T_4544 : connect remapVecData[6], Queue16_UInt8_15.io.deq.bits connect remapVecValids[6], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_4545 = eq(UInt<5>(0h10), remapindex_6) when _T_4545 : connect remapVecData[6], Queue16_UInt8_16.io.deq.bits connect remapVecValids[6], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_4546 = eq(UInt<5>(0h11), remapindex_6) when _T_4546 : connect remapVecData[6], Queue16_UInt8_17.io.deq.bits connect remapVecValids[6], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_4547 = eq(UInt<5>(0h12), remapindex_6) when _T_4547 : connect remapVecData[6], Queue16_UInt8_18.io.deq.bits connect remapVecValids[6], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_4548 = eq(UInt<5>(0h13), remapindex_6) when _T_4548 : connect remapVecData[6], Queue16_UInt8_19.io.deq.bits connect remapVecValids[6], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_4549 = eq(UInt<5>(0h14), remapindex_6) when _T_4549 : connect remapVecData[6], Queue16_UInt8_20.io.deq.bits connect remapVecValids[6], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_4550 = eq(UInt<5>(0h15), remapindex_6) when _T_4550 : connect remapVecData[6], Queue16_UInt8_21.io.deq.bits connect remapVecValids[6], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_4551 = eq(UInt<5>(0h16), remapindex_6) when _T_4551 : connect remapVecData[6], Queue16_UInt8_22.io.deq.bits connect remapVecValids[6], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_4552 = eq(UInt<5>(0h17), remapindex_6) when _T_4552 : connect remapVecData[6], Queue16_UInt8_23.io.deq.bits connect remapVecValids[6], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_4553 = eq(UInt<5>(0h18), remapindex_6) when _T_4553 : connect remapVecData[6], Queue16_UInt8_24.io.deq.bits connect remapVecValids[6], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_4554 = eq(UInt<5>(0h19), remapindex_6) when _T_4554 : connect remapVecData[6], Queue16_UInt8_25.io.deq.bits connect remapVecValids[6], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_4555 = eq(UInt<5>(0h1a), remapindex_6) when _T_4555 : connect remapVecData[6], Queue16_UInt8_26.io.deq.bits connect remapVecValids[6], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_4556 = eq(UInt<5>(0h1b), remapindex_6) when _T_4556 : connect remapVecData[6], Queue16_UInt8_27.io.deq.bits connect remapVecValids[6], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_4557 = eq(UInt<5>(0h1c), remapindex_6) when _T_4557 : connect remapVecData[6], Queue16_UInt8_28.io.deq.bits connect remapVecValids[6], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_4558 = eq(UInt<5>(0h1d), remapindex_6) when _T_4558 : connect remapVecData[6], Queue16_UInt8_29.io.deq.bits connect remapVecValids[6], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_4559 = eq(UInt<5>(0h1e), remapindex_6) when _T_4559 : connect remapVecData[6], Queue16_UInt8_30.io.deq.bits connect remapVecValids[6], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_4560 = eq(UInt<5>(0h1f), remapindex_6) when _T_4560 : connect remapVecData[6], Queue16_UInt8_31.io.deq.bits connect remapVecValids[6], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_4561 = eq(UInt<1>(0h0), remapindex_7) when _T_4561 : connect remapVecData[7], Queue16_UInt8.io.deq.bits connect remapVecValids[7], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[7] node _T_4562 = eq(UInt<1>(0h1), remapindex_7) when _T_4562 : connect remapVecData[7], Queue16_UInt8_1.io.deq.bits connect remapVecValids[7], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_4563 = eq(UInt<2>(0h2), remapindex_7) when _T_4563 : connect remapVecData[7], Queue16_UInt8_2.io.deq.bits connect remapVecValids[7], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_4564 = eq(UInt<2>(0h3), remapindex_7) when _T_4564 : connect remapVecData[7], Queue16_UInt8_3.io.deq.bits connect remapVecValids[7], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_4565 = eq(UInt<3>(0h4), remapindex_7) when _T_4565 : connect remapVecData[7], Queue16_UInt8_4.io.deq.bits connect remapVecValids[7], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_4566 = eq(UInt<3>(0h5), remapindex_7) when _T_4566 : connect remapVecData[7], Queue16_UInt8_5.io.deq.bits connect remapVecValids[7], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_4567 = eq(UInt<3>(0h6), remapindex_7) when _T_4567 : connect remapVecData[7], Queue16_UInt8_6.io.deq.bits connect remapVecValids[7], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_4568 = eq(UInt<3>(0h7), remapindex_7) when _T_4568 : connect remapVecData[7], Queue16_UInt8_7.io.deq.bits connect remapVecValids[7], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_4569 = eq(UInt<4>(0h8), remapindex_7) when _T_4569 : connect remapVecData[7], Queue16_UInt8_8.io.deq.bits connect remapVecValids[7], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_4570 = eq(UInt<4>(0h9), remapindex_7) when _T_4570 : connect remapVecData[7], Queue16_UInt8_9.io.deq.bits connect remapVecValids[7], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_4571 = eq(UInt<4>(0ha), remapindex_7) when _T_4571 : connect remapVecData[7], Queue16_UInt8_10.io.deq.bits connect remapVecValids[7], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_4572 = eq(UInt<4>(0hb), remapindex_7) when _T_4572 : connect remapVecData[7], Queue16_UInt8_11.io.deq.bits connect remapVecValids[7], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_4573 = eq(UInt<4>(0hc), remapindex_7) when _T_4573 : connect remapVecData[7], Queue16_UInt8_12.io.deq.bits connect remapVecValids[7], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_4574 = eq(UInt<4>(0hd), remapindex_7) when _T_4574 : connect remapVecData[7], Queue16_UInt8_13.io.deq.bits connect remapVecValids[7], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_4575 = eq(UInt<4>(0he), remapindex_7) when _T_4575 : connect remapVecData[7], Queue16_UInt8_14.io.deq.bits connect remapVecValids[7], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_4576 = eq(UInt<4>(0hf), remapindex_7) when _T_4576 : connect remapVecData[7], Queue16_UInt8_15.io.deq.bits connect remapVecValids[7], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_4577 = eq(UInt<5>(0h10), remapindex_7) when _T_4577 : connect remapVecData[7], Queue16_UInt8_16.io.deq.bits connect remapVecValids[7], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_4578 = eq(UInt<5>(0h11), remapindex_7) when _T_4578 : connect remapVecData[7], Queue16_UInt8_17.io.deq.bits connect remapVecValids[7], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_4579 = eq(UInt<5>(0h12), remapindex_7) when _T_4579 : connect remapVecData[7], Queue16_UInt8_18.io.deq.bits connect remapVecValids[7], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_4580 = eq(UInt<5>(0h13), remapindex_7) when _T_4580 : connect remapVecData[7], Queue16_UInt8_19.io.deq.bits connect remapVecValids[7], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_4581 = eq(UInt<5>(0h14), remapindex_7) when _T_4581 : connect remapVecData[7], Queue16_UInt8_20.io.deq.bits connect remapVecValids[7], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_4582 = eq(UInt<5>(0h15), remapindex_7) when _T_4582 : connect remapVecData[7], Queue16_UInt8_21.io.deq.bits connect remapVecValids[7], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_4583 = eq(UInt<5>(0h16), remapindex_7) when _T_4583 : connect remapVecData[7], Queue16_UInt8_22.io.deq.bits connect remapVecValids[7], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_4584 = eq(UInt<5>(0h17), remapindex_7) when _T_4584 : connect remapVecData[7], Queue16_UInt8_23.io.deq.bits connect remapVecValids[7], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_4585 = eq(UInt<5>(0h18), remapindex_7) when _T_4585 : connect remapVecData[7], Queue16_UInt8_24.io.deq.bits connect remapVecValids[7], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_4586 = eq(UInt<5>(0h19), remapindex_7) when _T_4586 : connect remapVecData[7], Queue16_UInt8_25.io.deq.bits connect remapVecValids[7], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_4587 = eq(UInt<5>(0h1a), remapindex_7) when _T_4587 : connect remapVecData[7], Queue16_UInt8_26.io.deq.bits connect remapVecValids[7], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_4588 = eq(UInt<5>(0h1b), remapindex_7) when _T_4588 : connect remapVecData[7], Queue16_UInt8_27.io.deq.bits connect remapVecValids[7], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_4589 = eq(UInt<5>(0h1c), remapindex_7) when _T_4589 : connect remapVecData[7], Queue16_UInt8_28.io.deq.bits connect remapVecValids[7], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_4590 = eq(UInt<5>(0h1d), remapindex_7) when _T_4590 : connect remapVecData[7], Queue16_UInt8_29.io.deq.bits connect remapVecValids[7], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_4591 = eq(UInt<5>(0h1e), remapindex_7) when _T_4591 : connect remapVecData[7], Queue16_UInt8_30.io.deq.bits connect remapVecValids[7], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_4592 = eq(UInt<5>(0h1f), remapindex_7) when _T_4592 : connect remapVecData[7], Queue16_UInt8_31.io.deq.bits connect remapVecValids[7], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_4593 = eq(UInt<1>(0h0), remapindex_8) when _T_4593 : connect remapVecData[8], Queue16_UInt8.io.deq.bits connect remapVecValids[8], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[8] node _T_4594 = eq(UInt<1>(0h1), remapindex_8) when _T_4594 : connect remapVecData[8], Queue16_UInt8_1.io.deq.bits connect remapVecValids[8], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_4595 = eq(UInt<2>(0h2), remapindex_8) when _T_4595 : connect remapVecData[8], Queue16_UInt8_2.io.deq.bits connect remapVecValids[8], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_4596 = eq(UInt<2>(0h3), remapindex_8) when _T_4596 : connect remapVecData[8], Queue16_UInt8_3.io.deq.bits connect remapVecValids[8], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_4597 = eq(UInt<3>(0h4), remapindex_8) when _T_4597 : connect remapVecData[8], Queue16_UInt8_4.io.deq.bits connect remapVecValids[8], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_4598 = eq(UInt<3>(0h5), remapindex_8) when _T_4598 : connect remapVecData[8], Queue16_UInt8_5.io.deq.bits connect remapVecValids[8], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_4599 = eq(UInt<3>(0h6), remapindex_8) when _T_4599 : connect remapVecData[8], Queue16_UInt8_6.io.deq.bits connect remapVecValids[8], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_4600 = eq(UInt<3>(0h7), remapindex_8) when _T_4600 : connect remapVecData[8], Queue16_UInt8_7.io.deq.bits connect remapVecValids[8], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_4601 = eq(UInt<4>(0h8), remapindex_8) when _T_4601 : connect remapVecData[8], Queue16_UInt8_8.io.deq.bits connect remapVecValids[8], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_4602 = eq(UInt<4>(0h9), remapindex_8) when _T_4602 : connect remapVecData[8], Queue16_UInt8_9.io.deq.bits connect remapVecValids[8], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_4603 = eq(UInt<4>(0ha), remapindex_8) when _T_4603 : connect remapVecData[8], Queue16_UInt8_10.io.deq.bits connect remapVecValids[8], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_4604 = eq(UInt<4>(0hb), remapindex_8) when _T_4604 : connect remapVecData[8], Queue16_UInt8_11.io.deq.bits connect remapVecValids[8], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_4605 = eq(UInt<4>(0hc), remapindex_8) when _T_4605 : connect remapVecData[8], Queue16_UInt8_12.io.deq.bits connect remapVecValids[8], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_4606 = eq(UInt<4>(0hd), remapindex_8) when _T_4606 : connect remapVecData[8], Queue16_UInt8_13.io.deq.bits connect remapVecValids[8], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_4607 = eq(UInt<4>(0he), remapindex_8) when _T_4607 : connect remapVecData[8], Queue16_UInt8_14.io.deq.bits connect remapVecValids[8], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_4608 = eq(UInt<4>(0hf), remapindex_8) when _T_4608 : connect remapVecData[8], Queue16_UInt8_15.io.deq.bits connect remapVecValids[8], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_4609 = eq(UInt<5>(0h10), remapindex_8) when _T_4609 : connect remapVecData[8], Queue16_UInt8_16.io.deq.bits connect remapVecValids[8], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_4610 = eq(UInt<5>(0h11), remapindex_8) when _T_4610 : connect remapVecData[8], Queue16_UInt8_17.io.deq.bits connect remapVecValids[8], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_4611 = eq(UInt<5>(0h12), remapindex_8) when _T_4611 : connect remapVecData[8], Queue16_UInt8_18.io.deq.bits connect remapVecValids[8], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_4612 = eq(UInt<5>(0h13), remapindex_8) when _T_4612 : connect remapVecData[8], Queue16_UInt8_19.io.deq.bits connect remapVecValids[8], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_4613 = eq(UInt<5>(0h14), remapindex_8) when _T_4613 : connect remapVecData[8], Queue16_UInt8_20.io.deq.bits connect remapVecValids[8], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_4614 = eq(UInt<5>(0h15), remapindex_8) when _T_4614 : connect remapVecData[8], Queue16_UInt8_21.io.deq.bits connect remapVecValids[8], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_4615 = eq(UInt<5>(0h16), remapindex_8) when _T_4615 : connect remapVecData[8], Queue16_UInt8_22.io.deq.bits connect remapVecValids[8], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_4616 = eq(UInt<5>(0h17), remapindex_8) when _T_4616 : connect remapVecData[8], Queue16_UInt8_23.io.deq.bits connect remapVecValids[8], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_4617 = eq(UInt<5>(0h18), remapindex_8) when _T_4617 : connect remapVecData[8], Queue16_UInt8_24.io.deq.bits connect remapVecValids[8], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_4618 = eq(UInt<5>(0h19), remapindex_8) when _T_4618 : connect remapVecData[8], Queue16_UInt8_25.io.deq.bits connect remapVecValids[8], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_4619 = eq(UInt<5>(0h1a), remapindex_8) when _T_4619 : connect remapVecData[8], Queue16_UInt8_26.io.deq.bits connect remapVecValids[8], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_4620 = eq(UInt<5>(0h1b), remapindex_8) when _T_4620 : connect remapVecData[8], Queue16_UInt8_27.io.deq.bits connect remapVecValids[8], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_4621 = eq(UInt<5>(0h1c), remapindex_8) when _T_4621 : connect remapVecData[8], Queue16_UInt8_28.io.deq.bits connect remapVecValids[8], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_4622 = eq(UInt<5>(0h1d), remapindex_8) when _T_4622 : connect remapVecData[8], Queue16_UInt8_29.io.deq.bits connect remapVecValids[8], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_4623 = eq(UInt<5>(0h1e), remapindex_8) when _T_4623 : connect remapVecData[8], Queue16_UInt8_30.io.deq.bits connect remapVecValids[8], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_4624 = eq(UInt<5>(0h1f), remapindex_8) when _T_4624 : connect remapVecData[8], Queue16_UInt8_31.io.deq.bits connect remapVecValids[8], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_4625 = eq(UInt<1>(0h0), remapindex_9) when _T_4625 : connect remapVecData[9], Queue16_UInt8.io.deq.bits connect remapVecValids[9], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[9] node _T_4626 = eq(UInt<1>(0h1), remapindex_9) when _T_4626 : connect remapVecData[9], Queue16_UInt8_1.io.deq.bits connect remapVecValids[9], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_4627 = eq(UInt<2>(0h2), remapindex_9) when _T_4627 : connect remapVecData[9], Queue16_UInt8_2.io.deq.bits connect remapVecValids[9], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_4628 = eq(UInt<2>(0h3), remapindex_9) when _T_4628 : connect remapVecData[9], Queue16_UInt8_3.io.deq.bits connect remapVecValids[9], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_4629 = eq(UInt<3>(0h4), remapindex_9) when _T_4629 : connect remapVecData[9], Queue16_UInt8_4.io.deq.bits connect remapVecValids[9], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_4630 = eq(UInt<3>(0h5), remapindex_9) when _T_4630 : connect remapVecData[9], Queue16_UInt8_5.io.deq.bits connect remapVecValids[9], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_4631 = eq(UInt<3>(0h6), remapindex_9) when _T_4631 : connect remapVecData[9], Queue16_UInt8_6.io.deq.bits connect remapVecValids[9], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_4632 = eq(UInt<3>(0h7), remapindex_9) when _T_4632 : connect remapVecData[9], Queue16_UInt8_7.io.deq.bits connect remapVecValids[9], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_4633 = eq(UInt<4>(0h8), remapindex_9) when _T_4633 : connect remapVecData[9], Queue16_UInt8_8.io.deq.bits connect remapVecValids[9], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_4634 = eq(UInt<4>(0h9), remapindex_9) when _T_4634 : connect remapVecData[9], Queue16_UInt8_9.io.deq.bits connect remapVecValids[9], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_4635 = eq(UInt<4>(0ha), remapindex_9) when _T_4635 : connect remapVecData[9], Queue16_UInt8_10.io.deq.bits connect remapVecValids[9], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_4636 = eq(UInt<4>(0hb), remapindex_9) when _T_4636 : connect remapVecData[9], Queue16_UInt8_11.io.deq.bits connect remapVecValids[9], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_4637 = eq(UInt<4>(0hc), remapindex_9) when _T_4637 : connect remapVecData[9], Queue16_UInt8_12.io.deq.bits connect remapVecValids[9], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_4638 = eq(UInt<4>(0hd), remapindex_9) when _T_4638 : connect remapVecData[9], Queue16_UInt8_13.io.deq.bits connect remapVecValids[9], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_4639 = eq(UInt<4>(0he), remapindex_9) when _T_4639 : connect remapVecData[9], Queue16_UInt8_14.io.deq.bits connect remapVecValids[9], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_4640 = eq(UInt<4>(0hf), remapindex_9) when _T_4640 : connect remapVecData[9], Queue16_UInt8_15.io.deq.bits connect remapVecValids[9], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_4641 = eq(UInt<5>(0h10), remapindex_9) when _T_4641 : connect remapVecData[9], Queue16_UInt8_16.io.deq.bits connect remapVecValids[9], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_4642 = eq(UInt<5>(0h11), remapindex_9) when _T_4642 : connect remapVecData[9], Queue16_UInt8_17.io.deq.bits connect remapVecValids[9], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_4643 = eq(UInt<5>(0h12), remapindex_9) when _T_4643 : connect remapVecData[9], Queue16_UInt8_18.io.deq.bits connect remapVecValids[9], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_4644 = eq(UInt<5>(0h13), remapindex_9) when _T_4644 : connect remapVecData[9], Queue16_UInt8_19.io.deq.bits connect remapVecValids[9], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_4645 = eq(UInt<5>(0h14), remapindex_9) when _T_4645 : connect remapVecData[9], Queue16_UInt8_20.io.deq.bits connect remapVecValids[9], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_4646 = eq(UInt<5>(0h15), remapindex_9) when _T_4646 : connect remapVecData[9], Queue16_UInt8_21.io.deq.bits connect remapVecValids[9], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_4647 = eq(UInt<5>(0h16), remapindex_9) when _T_4647 : connect remapVecData[9], Queue16_UInt8_22.io.deq.bits connect remapVecValids[9], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_4648 = eq(UInt<5>(0h17), remapindex_9) when _T_4648 : connect remapVecData[9], Queue16_UInt8_23.io.deq.bits connect remapVecValids[9], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_4649 = eq(UInt<5>(0h18), remapindex_9) when _T_4649 : connect remapVecData[9], Queue16_UInt8_24.io.deq.bits connect remapVecValids[9], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_4650 = eq(UInt<5>(0h19), remapindex_9) when _T_4650 : connect remapVecData[9], Queue16_UInt8_25.io.deq.bits connect remapVecValids[9], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_4651 = eq(UInt<5>(0h1a), remapindex_9) when _T_4651 : connect remapVecData[9], Queue16_UInt8_26.io.deq.bits connect remapVecValids[9], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_4652 = eq(UInt<5>(0h1b), remapindex_9) when _T_4652 : connect remapVecData[9], Queue16_UInt8_27.io.deq.bits connect remapVecValids[9], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_4653 = eq(UInt<5>(0h1c), remapindex_9) when _T_4653 : connect remapVecData[9], Queue16_UInt8_28.io.deq.bits connect remapVecValids[9], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_4654 = eq(UInt<5>(0h1d), remapindex_9) when _T_4654 : connect remapVecData[9], Queue16_UInt8_29.io.deq.bits connect remapVecValids[9], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_4655 = eq(UInt<5>(0h1e), remapindex_9) when _T_4655 : connect remapVecData[9], Queue16_UInt8_30.io.deq.bits connect remapVecValids[9], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_4656 = eq(UInt<5>(0h1f), remapindex_9) when _T_4656 : connect remapVecData[9], Queue16_UInt8_31.io.deq.bits connect remapVecValids[9], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_4657 = eq(UInt<1>(0h0), remapindex_10) when _T_4657 : connect remapVecData[10], Queue16_UInt8.io.deq.bits connect remapVecValids[10], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[10] node _T_4658 = eq(UInt<1>(0h1), remapindex_10) when _T_4658 : connect remapVecData[10], Queue16_UInt8_1.io.deq.bits connect remapVecValids[10], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_4659 = eq(UInt<2>(0h2), remapindex_10) when _T_4659 : connect remapVecData[10], Queue16_UInt8_2.io.deq.bits connect remapVecValids[10], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_4660 = eq(UInt<2>(0h3), remapindex_10) when _T_4660 : connect remapVecData[10], Queue16_UInt8_3.io.deq.bits connect remapVecValids[10], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_4661 = eq(UInt<3>(0h4), remapindex_10) when _T_4661 : connect remapVecData[10], Queue16_UInt8_4.io.deq.bits connect remapVecValids[10], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_4662 = eq(UInt<3>(0h5), remapindex_10) when _T_4662 : connect remapVecData[10], Queue16_UInt8_5.io.deq.bits connect remapVecValids[10], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_4663 = eq(UInt<3>(0h6), remapindex_10) when _T_4663 : connect remapVecData[10], Queue16_UInt8_6.io.deq.bits connect remapVecValids[10], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_4664 = eq(UInt<3>(0h7), remapindex_10) when _T_4664 : connect remapVecData[10], Queue16_UInt8_7.io.deq.bits connect remapVecValids[10], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_4665 = eq(UInt<4>(0h8), remapindex_10) when _T_4665 : connect remapVecData[10], Queue16_UInt8_8.io.deq.bits connect remapVecValids[10], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_4666 = eq(UInt<4>(0h9), remapindex_10) when _T_4666 : connect remapVecData[10], Queue16_UInt8_9.io.deq.bits connect remapVecValids[10], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_4667 = eq(UInt<4>(0ha), remapindex_10) when _T_4667 : connect remapVecData[10], Queue16_UInt8_10.io.deq.bits connect remapVecValids[10], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_4668 = eq(UInt<4>(0hb), remapindex_10) when _T_4668 : connect remapVecData[10], Queue16_UInt8_11.io.deq.bits connect remapVecValids[10], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_4669 = eq(UInt<4>(0hc), remapindex_10) when _T_4669 : connect remapVecData[10], Queue16_UInt8_12.io.deq.bits connect remapVecValids[10], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_4670 = eq(UInt<4>(0hd), remapindex_10) when _T_4670 : connect remapVecData[10], Queue16_UInt8_13.io.deq.bits connect remapVecValids[10], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_4671 = eq(UInt<4>(0he), remapindex_10) when _T_4671 : connect remapVecData[10], Queue16_UInt8_14.io.deq.bits connect remapVecValids[10], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_4672 = eq(UInt<4>(0hf), remapindex_10) when _T_4672 : connect remapVecData[10], Queue16_UInt8_15.io.deq.bits connect remapVecValids[10], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_4673 = eq(UInt<5>(0h10), remapindex_10) when _T_4673 : connect remapVecData[10], Queue16_UInt8_16.io.deq.bits connect remapVecValids[10], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_4674 = eq(UInt<5>(0h11), remapindex_10) when _T_4674 : connect remapVecData[10], Queue16_UInt8_17.io.deq.bits connect remapVecValids[10], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_4675 = eq(UInt<5>(0h12), remapindex_10) when _T_4675 : connect remapVecData[10], Queue16_UInt8_18.io.deq.bits connect remapVecValids[10], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_4676 = eq(UInt<5>(0h13), remapindex_10) when _T_4676 : connect remapVecData[10], Queue16_UInt8_19.io.deq.bits connect remapVecValids[10], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_4677 = eq(UInt<5>(0h14), remapindex_10) when _T_4677 : connect remapVecData[10], Queue16_UInt8_20.io.deq.bits connect remapVecValids[10], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_4678 = eq(UInt<5>(0h15), remapindex_10) when _T_4678 : connect remapVecData[10], Queue16_UInt8_21.io.deq.bits connect remapVecValids[10], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_4679 = eq(UInt<5>(0h16), remapindex_10) when _T_4679 : connect remapVecData[10], Queue16_UInt8_22.io.deq.bits connect remapVecValids[10], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_4680 = eq(UInt<5>(0h17), remapindex_10) when _T_4680 : connect remapVecData[10], Queue16_UInt8_23.io.deq.bits connect remapVecValids[10], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_4681 = eq(UInt<5>(0h18), remapindex_10) when _T_4681 : connect remapVecData[10], Queue16_UInt8_24.io.deq.bits connect remapVecValids[10], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_4682 = eq(UInt<5>(0h19), remapindex_10) when _T_4682 : connect remapVecData[10], Queue16_UInt8_25.io.deq.bits connect remapVecValids[10], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_4683 = eq(UInt<5>(0h1a), remapindex_10) when _T_4683 : connect remapVecData[10], Queue16_UInt8_26.io.deq.bits connect remapVecValids[10], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_4684 = eq(UInt<5>(0h1b), remapindex_10) when _T_4684 : connect remapVecData[10], Queue16_UInt8_27.io.deq.bits connect remapVecValids[10], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_4685 = eq(UInt<5>(0h1c), remapindex_10) when _T_4685 : connect remapVecData[10], Queue16_UInt8_28.io.deq.bits connect remapVecValids[10], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_4686 = eq(UInt<5>(0h1d), remapindex_10) when _T_4686 : connect remapVecData[10], Queue16_UInt8_29.io.deq.bits connect remapVecValids[10], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_4687 = eq(UInt<5>(0h1e), remapindex_10) when _T_4687 : connect remapVecData[10], Queue16_UInt8_30.io.deq.bits connect remapVecValids[10], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_4688 = eq(UInt<5>(0h1f), remapindex_10) when _T_4688 : connect remapVecData[10], Queue16_UInt8_31.io.deq.bits connect remapVecValids[10], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_4689 = eq(UInt<1>(0h0), remapindex_11) when _T_4689 : connect remapVecData[11], Queue16_UInt8.io.deq.bits connect remapVecValids[11], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[11] node _T_4690 = eq(UInt<1>(0h1), remapindex_11) when _T_4690 : connect remapVecData[11], Queue16_UInt8_1.io.deq.bits connect remapVecValids[11], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_4691 = eq(UInt<2>(0h2), remapindex_11) when _T_4691 : connect remapVecData[11], Queue16_UInt8_2.io.deq.bits connect remapVecValids[11], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_4692 = eq(UInt<2>(0h3), remapindex_11) when _T_4692 : connect remapVecData[11], Queue16_UInt8_3.io.deq.bits connect remapVecValids[11], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_4693 = eq(UInt<3>(0h4), remapindex_11) when _T_4693 : connect remapVecData[11], Queue16_UInt8_4.io.deq.bits connect remapVecValids[11], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_4694 = eq(UInt<3>(0h5), remapindex_11) when _T_4694 : connect remapVecData[11], Queue16_UInt8_5.io.deq.bits connect remapVecValids[11], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_4695 = eq(UInt<3>(0h6), remapindex_11) when _T_4695 : connect remapVecData[11], Queue16_UInt8_6.io.deq.bits connect remapVecValids[11], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_4696 = eq(UInt<3>(0h7), remapindex_11) when _T_4696 : connect remapVecData[11], Queue16_UInt8_7.io.deq.bits connect remapVecValids[11], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_4697 = eq(UInt<4>(0h8), remapindex_11) when _T_4697 : connect remapVecData[11], Queue16_UInt8_8.io.deq.bits connect remapVecValids[11], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_4698 = eq(UInt<4>(0h9), remapindex_11) when _T_4698 : connect remapVecData[11], Queue16_UInt8_9.io.deq.bits connect remapVecValids[11], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_4699 = eq(UInt<4>(0ha), remapindex_11) when _T_4699 : connect remapVecData[11], Queue16_UInt8_10.io.deq.bits connect remapVecValids[11], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_4700 = eq(UInt<4>(0hb), remapindex_11) when _T_4700 : connect remapVecData[11], Queue16_UInt8_11.io.deq.bits connect remapVecValids[11], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_4701 = eq(UInt<4>(0hc), remapindex_11) when _T_4701 : connect remapVecData[11], Queue16_UInt8_12.io.deq.bits connect remapVecValids[11], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_4702 = eq(UInt<4>(0hd), remapindex_11) when _T_4702 : connect remapVecData[11], Queue16_UInt8_13.io.deq.bits connect remapVecValids[11], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_4703 = eq(UInt<4>(0he), remapindex_11) when _T_4703 : connect remapVecData[11], Queue16_UInt8_14.io.deq.bits connect remapVecValids[11], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_4704 = eq(UInt<4>(0hf), remapindex_11) when _T_4704 : connect remapVecData[11], Queue16_UInt8_15.io.deq.bits connect remapVecValids[11], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_4705 = eq(UInt<5>(0h10), remapindex_11) when _T_4705 : connect remapVecData[11], Queue16_UInt8_16.io.deq.bits connect remapVecValids[11], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_4706 = eq(UInt<5>(0h11), remapindex_11) when _T_4706 : connect remapVecData[11], Queue16_UInt8_17.io.deq.bits connect remapVecValids[11], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_4707 = eq(UInt<5>(0h12), remapindex_11) when _T_4707 : connect remapVecData[11], Queue16_UInt8_18.io.deq.bits connect remapVecValids[11], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_4708 = eq(UInt<5>(0h13), remapindex_11) when _T_4708 : connect remapVecData[11], Queue16_UInt8_19.io.deq.bits connect remapVecValids[11], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_4709 = eq(UInt<5>(0h14), remapindex_11) when _T_4709 : connect remapVecData[11], Queue16_UInt8_20.io.deq.bits connect remapVecValids[11], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_4710 = eq(UInt<5>(0h15), remapindex_11) when _T_4710 : connect remapVecData[11], Queue16_UInt8_21.io.deq.bits connect remapVecValids[11], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_4711 = eq(UInt<5>(0h16), remapindex_11) when _T_4711 : connect remapVecData[11], Queue16_UInt8_22.io.deq.bits connect remapVecValids[11], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_4712 = eq(UInt<5>(0h17), remapindex_11) when _T_4712 : connect remapVecData[11], Queue16_UInt8_23.io.deq.bits connect remapVecValids[11], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_4713 = eq(UInt<5>(0h18), remapindex_11) when _T_4713 : connect remapVecData[11], Queue16_UInt8_24.io.deq.bits connect remapVecValids[11], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_4714 = eq(UInt<5>(0h19), remapindex_11) when _T_4714 : connect remapVecData[11], Queue16_UInt8_25.io.deq.bits connect remapVecValids[11], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_4715 = eq(UInt<5>(0h1a), remapindex_11) when _T_4715 : connect remapVecData[11], Queue16_UInt8_26.io.deq.bits connect remapVecValids[11], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_4716 = eq(UInt<5>(0h1b), remapindex_11) when _T_4716 : connect remapVecData[11], Queue16_UInt8_27.io.deq.bits connect remapVecValids[11], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_4717 = eq(UInt<5>(0h1c), remapindex_11) when _T_4717 : connect remapVecData[11], Queue16_UInt8_28.io.deq.bits connect remapVecValids[11], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_4718 = eq(UInt<5>(0h1d), remapindex_11) when _T_4718 : connect remapVecData[11], Queue16_UInt8_29.io.deq.bits connect remapVecValids[11], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_4719 = eq(UInt<5>(0h1e), remapindex_11) when _T_4719 : connect remapVecData[11], Queue16_UInt8_30.io.deq.bits connect remapVecValids[11], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_4720 = eq(UInt<5>(0h1f), remapindex_11) when _T_4720 : connect remapVecData[11], Queue16_UInt8_31.io.deq.bits connect remapVecValids[11], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_4721 = eq(UInt<1>(0h0), remapindex_12) when _T_4721 : connect remapVecData[12], Queue16_UInt8.io.deq.bits connect remapVecValids[12], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[12] node _T_4722 = eq(UInt<1>(0h1), remapindex_12) when _T_4722 : connect remapVecData[12], Queue16_UInt8_1.io.deq.bits connect remapVecValids[12], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_4723 = eq(UInt<2>(0h2), remapindex_12) when _T_4723 : connect remapVecData[12], Queue16_UInt8_2.io.deq.bits connect remapVecValids[12], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_4724 = eq(UInt<2>(0h3), remapindex_12) when _T_4724 : connect remapVecData[12], Queue16_UInt8_3.io.deq.bits connect remapVecValids[12], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_4725 = eq(UInt<3>(0h4), remapindex_12) when _T_4725 : connect remapVecData[12], Queue16_UInt8_4.io.deq.bits connect remapVecValids[12], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_4726 = eq(UInt<3>(0h5), remapindex_12) when _T_4726 : connect remapVecData[12], Queue16_UInt8_5.io.deq.bits connect remapVecValids[12], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_4727 = eq(UInt<3>(0h6), remapindex_12) when _T_4727 : connect remapVecData[12], Queue16_UInt8_6.io.deq.bits connect remapVecValids[12], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_4728 = eq(UInt<3>(0h7), remapindex_12) when _T_4728 : connect remapVecData[12], Queue16_UInt8_7.io.deq.bits connect remapVecValids[12], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_4729 = eq(UInt<4>(0h8), remapindex_12) when _T_4729 : connect remapVecData[12], Queue16_UInt8_8.io.deq.bits connect remapVecValids[12], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_4730 = eq(UInt<4>(0h9), remapindex_12) when _T_4730 : connect remapVecData[12], Queue16_UInt8_9.io.deq.bits connect remapVecValids[12], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_4731 = eq(UInt<4>(0ha), remapindex_12) when _T_4731 : connect remapVecData[12], Queue16_UInt8_10.io.deq.bits connect remapVecValids[12], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_4732 = eq(UInt<4>(0hb), remapindex_12) when _T_4732 : connect remapVecData[12], Queue16_UInt8_11.io.deq.bits connect remapVecValids[12], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_4733 = eq(UInt<4>(0hc), remapindex_12) when _T_4733 : connect remapVecData[12], Queue16_UInt8_12.io.deq.bits connect remapVecValids[12], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_4734 = eq(UInt<4>(0hd), remapindex_12) when _T_4734 : connect remapVecData[12], Queue16_UInt8_13.io.deq.bits connect remapVecValids[12], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_4735 = eq(UInt<4>(0he), remapindex_12) when _T_4735 : connect remapVecData[12], Queue16_UInt8_14.io.deq.bits connect remapVecValids[12], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_4736 = eq(UInt<4>(0hf), remapindex_12) when _T_4736 : connect remapVecData[12], Queue16_UInt8_15.io.deq.bits connect remapVecValids[12], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_4737 = eq(UInt<5>(0h10), remapindex_12) when _T_4737 : connect remapVecData[12], Queue16_UInt8_16.io.deq.bits connect remapVecValids[12], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_4738 = eq(UInt<5>(0h11), remapindex_12) when _T_4738 : connect remapVecData[12], Queue16_UInt8_17.io.deq.bits connect remapVecValids[12], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_4739 = eq(UInt<5>(0h12), remapindex_12) when _T_4739 : connect remapVecData[12], Queue16_UInt8_18.io.deq.bits connect remapVecValids[12], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_4740 = eq(UInt<5>(0h13), remapindex_12) when _T_4740 : connect remapVecData[12], Queue16_UInt8_19.io.deq.bits connect remapVecValids[12], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_4741 = eq(UInt<5>(0h14), remapindex_12) when _T_4741 : connect remapVecData[12], Queue16_UInt8_20.io.deq.bits connect remapVecValids[12], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_4742 = eq(UInt<5>(0h15), remapindex_12) when _T_4742 : connect remapVecData[12], Queue16_UInt8_21.io.deq.bits connect remapVecValids[12], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_4743 = eq(UInt<5>(0h16), remapindex_12) when _T_4743 : connect remapVecData[12], Queue16_UInt8_22.io.deq.bits connect remapVecValids[12], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_4744 = eq(UInt<5>(0h17), remapindex_12) when _T_4744 : connect remapVecData[12], Queue16_UInt8_23.io.deq.bits connect remapVecValids[12], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_4745 = eq(UInt<5>(0h18), remapindex_12) when _T_4745 : connect remapVecData[12], Queue16_UInt8_24.io.deq.bits connect remapVecValids[12], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_4746 = eq(UInt<5>(0h19), remapindex_12) when _T_4746 : connect remapVecData[12], Queue16_UInt8_25.io.deq.bits connect remapVecValids[12], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_4747 = eq(UInt<5>(0h1a), remapindex_12) when _T_4747 : connect remapVecData[12], Queue16_UInt8_26.io.deq.bits connect remapVecValids[12], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_4748 = eq(UInt<5>(0h1b), remapindex_12) when _T_4748 : connect remapVecData[12], Queue16_UInt8_27.io.deq.bits connect remapVecValids[12], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_4749 = eq(UInt<5>(0h1c), remapindex_12) when _T_4749 : connect remapVecData[12], Queue16_UInt8_28.io.deq.bits connect remapVecValids[12], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_4750 = eq(UInt<5>(0h1d), remapindex_12) when _T_4750 : connect remapVecData[12], Queue16_UInt8_29.io.deq.bits connect remapVecValids[12], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_4751 = eq(UInt<5>(0h1e), remapindex_12) when _T_4751 : connect remapVecData[12], Queue16_UInt8_30.io.deq.bits connect remapVecValids[12], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_4752 = eq(UInt<5>(0h1f), remapindex_12) when _T_4752 : connect remapVecData[12], Queue16_UInt8_31.io.deq.bits connect remapVecValids[12], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_4753 = eq(UInt<1>(0h0), remapindex_13) when _T_4753 : connect remapVecData[13], Queue16_UInt8.io.deq.bits connect remapVecValids[13], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[13] node _T_4754 = eq(UInt<1>(0h1), remapindex_13) when _T_4754 : connect remapVecData[13], Queue16_UInt8_1.io.deq.bits connect remapVecValids[13], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_4755 = eq(UInt<2>(0h2), remapindex_13) when _T_4755 : connect remapVecData[13], Queue16_UInt8_2.io.deq.bits connect remapVecValids[13], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_4756 = eq(UInt<2>(0h3), remapindex_13) when _T_4756 : connect remapVecData[13], Queue16_UInt8_3.io.deq.bits connect remapVecValids[13], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_4757 = eq(UInt<3>(0h4), remapindex_13) when _T_4757 : connect remapVecData[13], Queue16_UInt8_4.io.deq.bits connect remapVecValids[13], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_4758 = eq(UInt<3>(0h5), remapindex_13) when _T_4758 : connect remapVecData[13], Queue16_UInt8_5.io.deq.bits connect remapVecValids[13], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_4759 = eq(UInt<3>(0h6), remapindex_13) when _T_4759 : connect remapVecData[13], Queue16_UInt8_6.io.deq.bits connect remapVecValids[13], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_4760 = eq(UInt<3>(0h7), remapindex_13) when _T_4760 : connect remapVecData[13], Queue16_UInt8_7.io.deq.bits connect remapVecValids[13], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_4761 = eq(UInt<4>(0h8), remapindex_13) when _T_4761 : connect remapVecData[13], Queue16_UInt8_8.io.deq.bits connect remapVecValids[13], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_4762 = eq(UInt<4>(0h9), remapindex_13) when _T_4762 : connect remapVecData[13], Queue16_UInt8_9.io.deq.bits connect remapVecValids[13], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_4763 = eq(UInt<4>(0ha), remapindex_13) when _T_4763 : connect remapVecData[13], Queue16_UInt8_10.io.deq.bits connect remapVecValids[13], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_4764 = eq(UInt<4>(0hb), remapindex_13) when _T_4764 : connect remapVecData[13], Queue16_UInt8_11.io.deq.bits connect remapVecValids[13], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_4765 = eq(UInt<4>(0hc), remapindex_13) when _T_4765 : connect remapVecData[13], Queue16_UInt8_12.io.deq.bits connect remapVecValids[13], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_4766 = eq(UInt<4>(0hd), remapindex_13) when _T_4766 : connect remapVecData[13], Queue16_UInt8_13.io.deq.bits connect remapVecValids[13], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_4767 = eq(UInt<4>(0he), remapindex_13) when _T_4767 : connect remapVecData[13], Queue16_UInt8_14.io.deq.bits connect remapVecValids[13], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_4768 = eq(UInt<4>(0hf), remapindex_13) when _T_4768 : connect remapVecData[13], Queue16_UInt8_15.io.deq.bits connect remapVecValids[13], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_4769 = eq(UInt<5>(0h10), remapindex_13) when _T_4769 : connect remapVecData[13], Queue16_UInt8_16.io.deq.bits connect remapVecValids[13], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_4770 = eq(UInt<5>(0h11), remapindex_13) when _T_4770 : connect remapVecData[13], Queue16_UInt8_17.io.deq.bits connect remapVecValids[13], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_4771 = eq(UInt<5>(0h12), remapindex_13) when _T_4771 : connect remapVecData[13], Queue16_UInt8_18.io.deq.bits connect remapVecValids[13], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_4772 = eq(UInt<5>(0h13), remapindex_13) when _T_4772 : connect remapVecData[13], Queue16_UInt8_19.io.deq.bits connect remapVecValids[13], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_4773 = eq(UInt<5>(0h14), remapindex_13) when _T_4773 : connect remapVecData[13], Queue16_UInt8_20.io.deq.bits connect remapVecValids[13], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_4774 = eq(UInt<5>(0h15), remapindex_13) when _T_4774 : connect remapVecData[13], Queue16_UInt8_21.io.deq.bits connect remapVecValids[13], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_4775 = eq(UInt<5>(0h16), remapindex_13) when _T_4775 : connect remapVecData[13], Queue16_UInt8_22.io.deq.bits connect remapVecValids[13], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_4776 = eq(UInt<5>(0h17), remapindex_13) when _T_4776 : connect remapVecData[13], Queue16_UInt8_23.io.deq.bits connect remapVecValids[13], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_4777 = eq(UInt<5>(0h18), remapindex_13) when _T_4777 : connect remapVecData[13], Queue16_UInt8_24.io.deq.bits connect remapVecValids[13], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_4778 = eq(UInt<5>(0h19), remapindex_13) when _T_4778 : connect remapVecData[13], Queue16_UInt8_25.io.deq.bits connect remapVecValids[13], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_4779 = eq(UInt<5>(0h1a), remapindex_13) when _T_4779 : connect remapVecData[13], Queue16_UInt8_26.io.deq.bits connect remapVecValids[13], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_4780 = eq(UInt<5>(0h1b), remapindex_13) when _T_4780 : connect remapVecData[13], Queue16_UInt8_27.io.deq.bits connect remapVecValids[13], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_4781 = eq(UInt<5>(0h1c), remapindex_13) when _T_4781 : connect remapVecData[13], Queue16_UInt8_28.io.deq.bits connect remapVecValids[13], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_4782 = eq(UInt<5>(0h1d), remapindex_13) when _T_4782 : connect remapVecData[13], Queue16_UInt8_29.io.deq.bits connect remapVecValids[13], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_4783 = eq(UInt<5>(0h1e), remapindex_13) when _T_4783 : connect remapVecData[13], Queue16_UInt8_30.io.deq.bits connect remapVecValids[13], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_4784 = eq(UInt<5>(0h1f), remapindex_13) when _T_4784 : connect remapVecData[13], Queue16_UInt8_31.io.deq.bits connect remapVecValids[13], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_4785 = eq(UInt<1>(0h0), remapindex_14) when _T_4785 : connect remapVecData[14], Queue16_UInt8.io.deq.bits connect remapVecValids[14], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[14] node _T_4786 = eq(UInt<1>(0h1), remapindex_14) when _T_4786 : connect remapVecData[14], Queue16_UInt8_1.io.deq.bits connect remapVecValids[14], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_4787 = eq(UInt<2>(0h2), remapindex_14) when _T_4787 : connect remapVecData[14], Queue16_UInt8_2.io.deq.bits connect remapVecValids[14], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_4788 = eq(UInt<2>(0h3), remapindex_14) when _T_4788 : connect remapVecData[14], Queue16_UInt8_3.io.deq.bits connect remapVecValids[14], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_4789 = eq(UInt<3>(0h4), remapindex_14) when _T_4789 : connect remapVecData[14], Queue16_UInt8_4.io.deq.bits connect remapVecValids[14], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_4790 = eq(UInt<3>(0h5), remapindex_14) when _T_4790 : connect remapVecData[14], Queue16_UInt8_5.io.deq.bits connect remapVecValids[14], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_4791 = eq(UInt<3>(0h6), remapindex_14) when _T_4791 : connect remapVecData[14], Queue16_UInt8_6.io.deq.bits connect remapVecValids[14], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_4792 = eq(UInt<3>(0h7), remapindex_14) when _T_4792 : connect remapVecData[14], Queue16_UInt8_7.io.deq.bits connect remapVecValids[14], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_4793 = eq(UInt<4>(0h8), remapindex_14) when _T_4793 : connect remapVecData[14], Queue16_UInt8_8.io.deq.bits connect remapVecValids[14], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_4794 = eq(UInt<4>(0h9), remapindex_14) when _T_4794 : connect remapVecData[14], Queue16_UInt8_9.io.deq.bits connect remapVecValids[14], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_4795 = eq(UInt<4>(0ha), remapindex_14) when _T_4795 : connect remapVecData[14], Queue16_UInt8_10.io.deq.bits connect remapVecValids[14], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_4796 = eq(UInt<4>(0hb), remapindex_14) when _T_4796 : connect remapVecData[14], Queue16_UInt8_11.io.deq.bits connect remapVecValids[14], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_4797 = eq(UInt<4>(0hc), remapindex_14) when _T_4797 : connect remapVecData[14], Queue16_UInt8_12.io.deq.bits connect remapVecValids[14], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_4798 = eq(UInt<4>(0hd), remapindex_14) when _T_4798 : connect remapVecData[14], Queue16_UInt8_13.io.deq.bits connect remapVecValids[14], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_4799 = eq(UInt<4>(0he), remapindex_14) when _T_4799 : connect remapVecData[14], Queue16_UInt8_14.io.deq.bits connect remapVecValids[14], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_4800 = eq(UInt<4>(0hf), remapindex_14) when _T_4800 : connect remapVecData[14], Queue16_UInt8_15.io.deq.bits connect remapVecValids[14], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_4801 = eq(UInt<5>(0h10), remapindex_14) when _T_4801 : connect remapVecData[14], Queue16_UInt8_16.io.deq.bits connect remapVecValids[14], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_4802 = eq(UInt<5>(0h11), remapindex_14) when _T_4802 : connect remapVecData[14], Queue16_UInt8_17.io.deq.bits connect remapVecValids[14], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_4803 = eq(UInt<5>(0h12), remapindex_14) when _T_4803 : connect remapVecData[14], Queue16_UInt8_18.io.deq.bits connect remapVecValids[14], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_4804 = eq(UInt<5>(0h13), remapindex_14) when _T_4804 : connect remapVecData[14], Queue16_UInt8_19.io.deq.bits connect remapVecValids[14], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_4805 = eq(UInt<5>(0h14), remapindex_14) when _T_4805 : connect remapVecData[14], Queue16_UInt8_20.io.deq.bits connect remapVecValids[14], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_4806 = eq(UInt<5>(0h15), remapindex_14) when _T_4806 : connect remapVecData[14], Queue16_UInt8_21.io.deq.bits connect remapVecValids[14], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_4807 = eq(UInt<5>(0h16), remapindex_14) when _T_4807 : connect remapVecData[14], Queue16_UInt8_22.io.deq.bits connect remapVecValids[14], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_4808 = eq(UInt<5>(0h17), remapindex_14) when _T_4808 : connect remapVecData[14], Queue16_UInt8_23.io.deq.bits connect remapVecValids[14], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_4809 = eq(UInt<5>(0h18), remapindex_14) when _T_4809 : connect remapVecData[14], Queue16_UInt8_24.io.deq.bits connect remapVecValids[14], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_4810 = eq(UInt<5>(0h19), remapindex_14) when _T_4810 : connect remapVecData[14], Queue16_UInt8_25.io.deq.bits connect remapVecValids[14], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_4811 = eq(UInt<5>(0h1a), remapindex_14) when _T_4811 : connect remapVecData[14], Queue16_UInt8_26.io.deq.bits connect remapVecValids[14], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_4812 = eq(UInt<5>(0h1b), remapindex_14) when _T_4812 : connect remapVecData[14], Queue16_UInt8_27.io.deq.bits connect remapVecValids[14], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_4813 = eq(UInt<5>(0h1c), remapindex_14) when _T_4813 : connect remapVecData[14], Queue16_UInt8_28.io.deq.bits connect remapVecValids[14], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_4814 = eq(UInt<5>(0h1d), remapindex_14) when _T_4814 : connect remapVecData[14], Queue16_UInt8_29.io.deq.bits connect remapVecValids[14], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_4815 = eq(UInt<5>(0h1e), remapindex_14) when _T_4815 : connect remapVecData[14], Queue16_UInt8_30.io.deq.bits connect remapVecValids[14], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_4816 = eq(UInt<5>(0h1f), remapindex_14) when _T_4816 : connect remapVecData[14], Queue16_UInt8_31.io.deq.bits connect remapVecValids[14], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_4817 = eq(UInt<1>(0h0), remapindex_15) when _T_4817 : connect remapVecData[15], Queue16_UInt8.io.deq.bits connect remapVecValids[15], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[15] node _T_4818 = eq(UInt<1>(0h1), remapindex_15) when _T_4818 : connect remapVecData[15], Queue16_UInt8_1.io.deq.bits connect remapVecValids[15], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_4819 = eq(UInt<2>(0h2), remapindex_15) when _T_4819 : connect remapVecData[15], Queue16_UInt8_2.io.deq.bits connect remapVecValids[15], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_4820 = eq(UInt<2>(0h3), remapindex_15) when _T_4820 : connect remapVecData[15], Queue16_UInt8_3.io.deq.bits connect remapVecValids[15], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_4821 = eq(UInt<3>(0h4), remapindex_15) when _T_4821 : connect remapVecData[15], Queue16_UInt8_4.io.deq.bits connect remapVecValids[15], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_4822 = eq(UInt<3>(0h5), remapindex_15) when _T_4822 : connect remapVecData[15], Queue16_UInt8_5.io.deq.bits connect remapVecValids[15], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_4823 = eq(UInt<3>(0h6), remapindex_15) when _T_4823 : connect remapVecData[15], Queue16_UInt8_6.io.deq.bits connect remapVecValids[15], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_4824 = eq(UInt<3>(0h7), remapindex_15) when _T_4824 : connect remapVecData[15], Queue16_UInt8_7.io.deq.bits connect remapVecValids[15], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_4825 = eq(UInt<4>(0h8), remapindex_15) when _T_4825 : connect remapVecData[15], Queue16_UInt8_8.io.deq.bits connect remapVecValids[15], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_4826 = eq(UInt<4>(0h9), remapindex_15) when _T_4826 : connect remapVecData[15], Queue16_UInt8_9.io.deq.bits connect remapVecValids[15], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_4827 = eq(UInt<4>(0ha), remapindex_15) when _T_4827 : connect remapVecData[15], Queue16_UInt8_10.io.deq.bits connect remapVecValids[15], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_4828 = eq(UInt<4>(0hb), remapindex_15) when _T_4828 : connect remapVecData[15], Queue16_UInt8_11.io.deq.bits connect remapVecValids[15], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_4829 = eq(UInt<4>(0hc), remapindex_15) when _T_4829 : connect remapVecData[15], Queue16_UInt8_12.io.deq.bits connect remapVecValids[15], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_4830 = eq(UInt<4>(0hd), remapindex_15) when _T_4830 : connect remapVecData[15], Queue16_UInt8_13.io.deq.bits connect remapVecValids[15], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_4831 = eq(UInt<4>(0he), remapindex_15) when _T_4831 : connect remapVecData[15], Queue16_UInt8_14.io.deq.bits connect remapVecValids[15], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_4832 = eq(UInt<4>(0hf), remapindex_15) when _T_4832 : connect remapVecData[15], Queue16_UInt8_15.io.deq.bits connect remapVecValids[15], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_4833 = eq(UInt<5>(0h10), remapindex_15) when _T_4833 : connect remapVecData[15], Queue16_UInt8_16.io.deq.bits connect remapVecValids[15], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_4834 = eq(UInt<5>(0h11), remapindex_15) when _T_4834 : connect remapVecData[15], Queue16_UInt8_17.io.deq.bits connect remapVecValids[15], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_4835 = eq(UInt<5>(0h12), remapindex_15) when _T_4835 : connect remapVecData[15], Queue16_UInt8_18.io.deq.bits connect remapVecValids[15], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_4836 = eq(UInt<5>(0h13), remapindex_15) when _T_4836 : connect remapVecData[15], Queue16_UInt8_19.io.deq.bits connect remapVecValids[15], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_4837 = eq(UInt<5>(0h14), remapindex_15) when _T_4837 : connect remapVecData[15], Queue16_UInt8_20.io.deq.bits connect remapVecValids[15], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_4838 = eq(UInt<5>(0h15), remapindex_15) when _T_4838 : connect remapVecData[15], Queue16_UInt8_21.io.deq.bits connect remapVecValids[15], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_4839 = eq(UInt<5>(0h16), remapindex_15) when _T_4839 : connect remapVecData[15], Queue16_UInt8_22.io.deq.bits connect remapVecValids[15], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_4840 = eq(UInt<5>(0h17), remapindex_15) when _T_4840 : connect remapVecData[15], Queue16_UInt8_23.io.deq.bits connect remapVecValids[15], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_4841 = eq(UInt<5>(0h18), remapindex_15) when _T_4841 : connect remapVecData[15], Queue16_UInt8_24.io.deq.bits connect remapVecValids[15], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_4842 = eq(UInt<5>(0h19), remapindex_15) when _T_4842 : connect remapVecData[15], Queue16_UInt8_25.io.deq.bits connect remapVecValids[15], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_4843 = eq(UInt<5>(0h1a), remapindex_15) when _T_4843 : connect remapVecData[15], Queue16_UInt8_26.io.deq.bits connect remapVecValids[15], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_4844 = eq(UInt<5>(0h1b), remapindex_15) when _T_4844 : connect remapVecData[15], Queue16_UInt8_27.io.deq.bits connect remapVecValids[15], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_4845 = eq(UInt<5>(0h1c), remapindex_15) when _T_4845 : connect remapVecData[15], Queue16_UInt8_28.io.deq.bits connect remapVecValids[15], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_4846 = eq(UInt<5>(0h1d), remapindex_15) when _T_4846 : connect remapVecData[15], Queue16_UInt8_29.io.deq.bits connect remapVecValids[15], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_4847 = eq(UInt<5>(0h1e), remapindex_15) when _T_4847 : connect remapVecData[15], Queue16_UInt8_30.io.deq.bits connect remapVecValids[15], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_4848 = eq(UInt<5>(0h1f), remapindex_15) when _T_4848 : connect remapVecData[15], Queue16_UInt8_31.io.deq.bits connect remapVecValids[15], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_4849 = eq(UInt<1>(0h0), remapindex_16) when _T_4849 : connect remapVecData[16], Queue16_UInt8.io.deq.bits connect remapVecValids[16], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[16] node _T_4850 = eq(UInt<1>(0h1), remapindex_16) when _T_4850 : connect remapVecData[16], Queue16_UInt8_1.io.deq.bits connect remapVecValids[16], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_4851 = eq(UInt<2>(0h2), remapindex_16) when _T_4851 : connect remapVecData[16], Queue16_UInt8_2.io.deq.bits connect remapVecValids[16], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_4852 = eq(UInt<2>(0h3), remapindex_16) when _T_4852 : connect remapVecData[16], Queue16_UInt8_3.io.deq.bits connect remapVecValids[16], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_4853 = eq(UInt<3>(0h4), remapindex_16) when _T_4853 : connect remapVecData[16], Queue16_UInt8_4.io.deq.bits connect remapVecValids[16], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_4854 = eq(UInt<3>(0h5), remapindex_16) when _T_4854 : connect remapVecData[16], Queue16_UInt8_5.io.deq.bits connect remapVecValids[16], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_4855 = eq(UInt<3>(0h6), remapindex_16) when _T_4855 : connect remapVecData[16], Queue16_UInt8_6.io.deq.bits connect remapVecValids[16], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_4856 = eq(UInt<3>(0h7), remapindex_16) when _T_4856 : connect remapVecData[16], Queue16_UInt8_7.io.deq.bits connect remapVecValids[16], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_4857 = eq(UInt<4>(0h8), remapindex_16) when _T_4857 : connect remapVecData[16], Queue16_UInt8_8.io.deq.bits connect remapVecValids[16], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_4858 = eq(UInt<4>(0h9), remapindex_16) when _T_4858 : connect remapVecData[16], Queue16_UInt8_9.io.deq.bits connect remapVecValids[16], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_4859 = eq(UInt<4>(0ha), remapindex_16) when _T_4859 : connect remapVecData[16], Queue16_UInt8_10.io.deq.bits connect remapVecValids[16], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_4860 = eq(UInt<4>(0hb), remapindex_16) when _T_4860 : connect remapVecData[16], Queue16_UInt8_11.io.deq.bits connect remapVecValids[16], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_4861 = eq(UInt<4>(0hc), remapindex_16) when _T_4861 : connect remapVecData[16], Queue16_UInt8_12.io.deq.bits connect remapVecValids[16], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_4862 = eq(UInt<4>(0hd), remapindex_16) when _T_4862 : connect remapVecData[16], Queue16_UInt8_13.io.deq.bits connect remapVecValids[16], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_4863 = eq(UInt<4>(0he), remapindex_16) when _T_4863 : connect remapVecData[16], Queue16_UInt8_14.io.deq.bits connect remapVecValids[16], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_4864 = eq(UInt<4>(0hf), remapindex_16) when _T_4864 : connect remapVecData[16], Queue16_UInt8_15.io.deq.bits connect remapVecValids[16], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_4865 = eq(UInt<5>(0h10), remapindex_16) when _T_4865 : connect remapVecData[16], Queue16_UInt8_16.io.deq.bits connect remapVecValids[16], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_4866 = eq(UInt<5>(0h11), remapindex_16) when _T_4866 : connect remapVecData[16], Queue16_UInt8_17.io.deq.bits connect remapVecValids[16], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_4867 = eq(UInt<5>(0h12), remapindex_16) when _T_4867 : connect remapVecData[16], Queue16_UInt8_18.io.deq.bits connect remapVecValids[16], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_4868 = eq(UInt<5>(0h13), remapindex_16) when _T_4868 : connect remapVecData[16], Queue16_UInt8_19.io.deq.bits connect remapVecValids[16], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_4869 = eq(UInt<5>(0h14), remapindex_16) when _T_4869 : connect remapVecData[16], Queue16_UInt8_20.io.deq.bits connect remapVecValids[16], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_4870 = eq(UInt<5>(0h15), remapindex_16) when _T_4870 : connect remapVecData[16], Queue16_UInt8_21.io.deq.bits connect remapVecValids[16], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_4871 = eq(UInt<5>(0h16), remapindex_16) when _T_4871 : connect remapVecData[16], Queue16_UInt8_22.io.deq.bits connect remapVecValids[16], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_4872 = eq(UInt<5>(0h17), remapindex_16) when _T_4872 : connect remapVecData[16], Queue16_UInt8_23.io.deq.bits connect remapVecValids[16], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_4873 = eq(UInt<5>(0h18), remapindex_16) when _T_4873 : connect remapVecData[16], Queue16_UInt8_24.io.deq.bits connect remapVecValids[16], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_4874 = eq(UInt<5>(0h19), remapindex_16) when _T_4874 : connect remapVecData[16], Queue16_UInt8_25.io.deq.bits connect remapVecValids[16], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_4875 = eq(UInt<5>(0h1a), remapindex_16) when _T_4875 : connect remapVecData[16], Queue16_UInt8_26.io.deq.bits connect remapVecValids[16], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_4876 = eq(UInt<5>(0h1b), remapindex_16) when _T_4876 : connect remapVecData[16], Queue16_UInt8_27.io.deq.bits connect remapVecValids[16], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_4877 = eq(UInt<5>(0h1c), remapindex_16) when _T_4877 : connect remapVecData[16], Queue16_UInt8_28.io.deq.bits connect remapVecValids[16], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_4878 = eq(UInt<5>(0h1d), remapindex_16) when _T_4878 : connect remapVecData[16], Queue16_UInt8_29.io.deq.bits connect remapVecValids[16], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_4879 = eq(UInt<5>(0h1e), remapindex_16) when _T_4879 : connect remapVecData[16], Queue16_UInt8_30.io.deq.bits connect remapVecValids[16], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_4880 = eq(UInt<5>(0h1f), remapindex_16) when _T_4880 : connect remapVecData[16], Queue16_UInt8_31.io.deq.bits connect remapVecValids[16], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_4881 = eq(UInt<1>(0h0), remapindex_17) when _T_4881 : connect remapVecData[17], Queue16_UInt8.io.deq.bits connect remapVecValids[17], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[17] node _T_4882 = eq(UInt<1>(0h1), remapindex_17) when _T_4882 : connect remapVecData[17], Queue16_UInt8_1.io.deq.bits connect remapVecValids[17], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_4883 = eq(UInt<2>(0h2), remapindex_17) when _T_4883 : connect remapVecData[17], Queue16_UInt8_2.io.deq.bits connect remapVecValids[17], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_4884 = eq(UInt<2>(0h3), remapindex_17) when _T_4884 : connect remapVecData[17], Queue16_UInt8_3.io.deq.bits connect remapVecValids[17], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_4885 = eq(UInt<3>(0h4), remapindex_17) when _T_4885 : connect remapVecData[17], Queue16_UInt8_4.io.deq.bits connect remapVecValids[17], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_4886 = eq(UInt<3>(0h5), remapindex_17) when _T_4886 : connect remapVecData[17], Queue16_UInt8_5.io.deq.bits connect remapVecValids[17], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_4887 = eq(UInt<3>(0h6), remapindex_17) when _T_4887 : connect remapVecData[17], Queue16_UInt8_6.io.deq.bits connect remapVecValids[17], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_4888 = eq(UInt<3>(0h7), remapindex_17) when _T_4888 : connect remapVecData[17], Queue16_UInt8_7.io.deq.bits connect remapVecValids[17], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_4889 = eq(UInt<4>(0h8), remapindex_17) when _T_4889 : connect remapVecData[17], Queue16_UInt8_8.io.deq.bits connect remapVecValids[17], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_4890 = eq(UInt<4>(0h9), remapindex_17) when _T_4890 : connect remapVecData[17], Queue16_UInt8_9.io.deq.bits connect remapVecValids[17], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_4891 = eq(UInt<4>(0ha), remapindex_17) when _T_4891 : connect remapVecData[17], Queue16_UInt8_10.io.deq.bits connect remapVecValids[17], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_4892 = eq(UInt<4>(0hb), remapindex_17) when _T_4892 : connect remapVecData[17], Queue16_UInt8_11.io.deq.bits connect remapVecValids[17], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_4893 = eq(UInt<4>(0hc), remapindex_17) when _T_4893 : connect remapVecData[17], Queue16_UInt8_12.io.deq.bits connect remapVecValids[17], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_4894 = eq(UInt<4>(0hd), remapindex_17) when _T_4894 : connect remapVecData[17], Queue16_UInt8_13.io.deq.bits connect remapVecValids[17], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_4895 = eq(UInt<4>(0he), remapindex_17) when _T_4895 : connect remapVecData[17], Queue16_UInt8_14.io.deq.bits connect remapVecValids[17], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_4896 = eq(UInt<4>(0hf), remapindex_17) when _T_4896 : connect remapVecData[17], Queue16_UInt8_15.io.deq.bits connect remapVecValids[17], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_4897 = eq(UInt<5>(0h10), remapindex_17) when _T_4897 : connect remapVecData[17], Queue16_UInt8_16.io.deq.bits connect remapVecValids[17], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_4898 = eq(UInt<5>(0h11), remapindex_17) when _T_4898 : connect remapVecData[17], Queue16_UInt8_17.io.deq.bits connect remapVecValids[17], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_4899 = eq(UInt<5>(0h12), remapindex_17) when _T_4899 : connect remapVecData[17], Queue16_UInt8_18.io.deq.bits connect remapVecValids[17], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_4900 = eq(UInt<5>(0h13), remapindex_17) when _T_4900 : connect remapVecData[17], Queue16_UInt8_19.io.deq.bits connect remapVecValids[17], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_4901 = eq(UInt<5>(0h14), remapindex_17) when _T_4901 : connect remapVecData[17], Queue16_UInt8_20.io.deq.bits connect remapVecValids[17], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_4902 = eq(UInt<5>(0h15), remapindex_17) when _T_4902 : connect remapVecData[17], Queue16_UInt8_21.io.deq.bits connect remapVecValids[17], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_4903 = eq(UInt<5>(0h16), remapindex_17) when _T_4903 : connect remapVecData[17], Queue16_UInt8_22.io.deq.bits connect remapVecValids[17], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_4904 = eq(UInt<5>(0h17), remapindex_17) when _T_4904 : connect remapVecData[17], Queue16_UInt8_23.io.deq.bits connect remapVecValids[17], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_4905 = eq(UInt<5>(0h18), remapindex_17) when _T_4905 : connect remapVecData[17], Queue16_UInt8_24.io.deq.bits connect remapVecValids[17], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_4906 = eq(UInt<5>(0h19), remapindex_17) when _T_4906 : connect remapVecData[17], Queue16_UInt8_25.io.deq.bits connect remapVecValids[17], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_4907 = eq(UInt<5>(0h1a), remapindex_17) when _T_4907 : connect remapVecData[17], Queue16_UInt8_26.io.deq.bits connect remapVecValids[17], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_4908 = eq(UInt<5>(0h1b), remapindex_17) when _T_4908 : connect remapVecData[17], Queue16_UInt8_27.io.deq.bits connect remapVecValids[17], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_4909 = eq(UInt<5>(0h1c), remapindex_17) when _T_4909 : connect remapVecData[17], Queue16_UInt8_28.io.deq.bits connect remapVecValids[17], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_4910 = eq(UInt<5>(0h1d), remapindex_17) when _T_4910 : connect remapVecData[17], Queue16_UInt8_29.io.deq.bits connect remapVecValids[17], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_4911 = eq(UInt<5>(0h1e), remapindex_17) when _T_4911 : connect remapVecData[17], Queue16_UInt8_30.io.deq.bits connect remapVecValids[17], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_4912 = eq(UInt<5>(0h1f), remapindex_17) when _T_4912 : connect remapVecData[17], Queue16_UInt8_31.io.deq.bits connect remapVecValids[17], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_4913 = eq(UInt<1>(0h0), remapindex_18) when _T_4913 : connect remapVecData[18], Queue16_UInt8.io.deq.bits connect remapVecValids[18], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[18] node _T_4914 = eq(UInt<1>(0h1), remapindex_18) when _T_4914 : connect remapVecData[18], Queue16_UInt8_1.io.deq.bits connect remapVecValids[18], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_4915 = eq(UInt<2>(0h2), remapindex_18) when _T_4915 : connect remapVecData[18], Queue16_UInt8_2.io.deq.bits connect remapVecValids[18], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_4916 = eq(UInt<2>(0h3), remapindex_18) when _T_4916 : connect remapVecData[18], Queue16_UInt8_3.io.deq.bits connect remapVecValids[18], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_4917 = eq(UInt<3>(0h4), remapindex_18) when _T_4917 : connect remapVecData[18], Queue16_UInt8_4.io.deq.bits connect remapVecValids[18], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_4918 = eq(UInt<3>(0h5), remapindex_18) when _T_4918 : connect remapVecData[18], Queue16_UInt8_5.io.deq.bits connect remapVecValids[18], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_4919 = eq(UInt<3>(0h6), remapindex_18) when _T_4919 : connect remapVecData[18], Queue16_UInt8_6.io.deq.bits connect remapVecValids[18], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_4920 = eq(UInt<3>(0h7), remapindex_18) when _T_4920 : connect remapVecData[18], Queue16_UInt8_7.io.deq.bits connect remapVecValids[18], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_4921 = eq(UInt<4>(0h8), remapindex_18) when _T_4921 : connect remapVecData[18], Queue16_UInt8_8.io.deq.bits connect remapVecValids[18], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_4922 = eq(UInt<4>(0h9), remapindex_18) when _T_4922 : connect remapVecData[18], Queue16_UInt8_9.io.deq.bits connect remapVecValids[18], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_4923 = eq(UInt<4>(0ha), remapindex_18) when _T_4923 : connect remapVecData[18], Queue16_UInt8_10.io.deq.bits connect remapVecValids[18], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_4924 = eq(UInt<4>(0hb), remapindex_18) when _T_4924 : connect remapVecData[18], Queue16_UInt8_11.io.deq.bits connect remapVecValids[18], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_4925 = eq(UInt<4>(0hc), remapindex_18) when _T_4925 : connect remapVecData[18], Queue16_UInt8_12.io.deq.bits connect remapVecValids[18], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_4926 = eq(UInt<4>(0hd), remapindex_18) when _T_4926 : connect remapVecData[18], Queue16_UInt8_13.io.deq.bits connect remapVecValids[18], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_4927 = eq(UInt<4>(0he), remapindex_18) when _T_4927 : connect remapVecData[18], Queue16_UInt8_14.io.deq.bits connect remapVecValids[18], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_4928 = eq(UInt<4>(0hf), remapindex_18) when _T_4928 : connect remapVecData[18], Queue16_UInt8_15.io.deq.bits connect remapVecValids[18], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_4929 = eq(UInt<5>(0h10), remapindex_18) when _T_4929 : connect remapVecData[18], Queue16_UInt8_16.io.deq.bits connect remapVecValids[18], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_4930 = eq(UInt<5>(0h11), remapindex_18) when _T_4930 : connect remapVecData[18], Queue16_UInt8_17.io.deq.bits connect remapVecValids[18], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_4931 = eq(UInt<5>(0h12), remapindex_18) when _T_4931 : connect remapVecData[18], Queue16_UInt8_18.io.deq.bits connect remapVecValids[18], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_4932 = eq(UInt<5>(0h13), remapindex_18) when _T_4932 : connect remapVecData[18], Queue16_UInt8_19.io.deq.bits connect remapVecValids[18], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_4933 = eq(UInt<5>(0h14), remapindex_18) when _T_4933 : connect remapVecData[18], Queue16_UInt8_20.io.deq.bits connect remapVecValids[18], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_4934 = eq(UInt<5>(0h15), remapindex_18) when _T_4934 : connect remapVecData[18], Queue16_UInt8_21.io.deq.bits connect remapVecValids[18], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_4935 = eq(UInt<5>(0h16), remapindex_18) when _T_4935 : connect remapVecData[18], Queue16_UInt8_22.io.deq.bits connect remapVecValids[18], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_4936 = eq(UInt<5>(0h17), remapindex_18) when _T_4936 : connect remapVecData[18], Queue16_UInt8_23.io.deq.bits connect remapVecValids[18], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_4937 = eq(UInt<5>(0h18), remapindex_18) when _T_4937 : connect remapVecData[18], Queue16_UInt8_24.io.deq.bits connect remapVecValids[18], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_4938 = eq(UInt<5>(0h19), remapindex_18) when _T_4938 : connect remapVecData[18], Queue16_UInt8_25.io.deq.bits connect remapVecValids[18], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_4939 = eq(UInt<5>(0h1a), remapindex_18) when _T_4939 : connect remapVecData[18], Queue16_UInt8_26.io.deq.bits connect remapVecValids[18], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_4940 = eq(UInt<5>(0h1b), remapindex_18) when _T_4940 : connect remapVecData[18], Queue16_UInt8_27.io.deq.bits connect remapVecValids[18], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_4941 = eq(UInt<5>(0h1c), remapindex_18) when _T_4941 : connect remapVecData[18], Queue16_UInt8_28.io.deq.bits connect remapVecValids[18], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_4942 = eq(UInt<5>(0h1d), remapindex_18) when _T_4942 : connect remapVecData[18], Queue16_UInt8_29.io.deq.bits connect remapVecValids[18], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_4943 = eq(UInt<5>(0h1e), remapindex_18) when _T_4943 : connect remapVecData[18], Queue16_UInt8_30.io.deq.bits connect remapVecValids[18], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_4944 = eq(UInt<5>(0h1f), remapindex_18) when _T_4944 : connect remapVecData[18], Queue16_UInt8_31.io.deq.bits connect remapVecValids[18], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_4945 = eq(UInt<1>(0h0), remapindex_19) when _T_4945 : connect remapVecData[19], Queue16_UInt8.io.deq.bits connect remapVecValids[19], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[19] node _T_4946 = eq(UInt<1>(0h1), remapindex_19) when _T_4946 : connect remapVecData[19], Queue16_UInt8_1.io.deq.bits connect remapVecValids[19], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_4947 = eq(UInt<2>(0h2), remapindex_19) when _T_4947 : connect remapVecData[19], Queue16_UInt8_2.io.deq.bits connect remapVecValids[19], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_4948 = eq(UInt<2>(0h3), remapindex_19) when _T_4948 : connect remapVecData[19], Queue16_UInt8_3.io.deq.bits connect remapVecValids[19], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_4949 = eq(UInt<3>(0h4), remapindex_19) when _T_4949 : connect remapVecData[19], Queue16_UInt8_4.io.deq.bits connect remapVecValids[19], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_4950 = eq(UInt<3>(0h5), remapindex_19) when _T_4950 : connect remapVecData[19], Queue16_UInt8_5.io.deq.bits connect remapVecValids[19], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_4951 = eq(UInt<3>(0h6), remapindex_19) when _T_4951 : connect remapVecData[19], Queue16_UInt8_6.io.deq.bits connect remapVecValids[19], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_4952 = eq(UInt<3>(0h7), remapindex_19) when _T_4952 : connect remapVecData[19], Queue16_UInt8_7.io.deq.bits connect remapVecValids[19], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_4953 = eq(UInt<4>(0h8), remapindex_19) when _T_4953 : connect remapVecData[19], Queue16_UInt8_8.io.deq.bits connect remapVecValids[19], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_4954 = eq(UInt<4>(0h9), remapindex_19) when _T_4954 : connect remapVecData[19], Queue16_UInt8_9.io.deq.bits connect remapVecValids[19], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_4955 = eq(UInt<4>(0ha), remapindex_19) when _T_4955 : connect remapVecData[19], Queue16_UInt8_10.io.deq.bits connect remapVecValids[19], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_4956 = eq(UInt<4>(0hb), remapindex_19) when _T_4956 : connect remapVecData[19], Queue16_UInt8_11.io.deq.bits connect remapVecValids[19], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_4957 = eq(UInt<4>(0hc), remapindex_19) when _T_4957 : connect remapVecData[19], Queue16_UInt8_12.io.deq.bits connect remapVecValids[19], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_4958 = eq(UInt<4>(0hd), remapindex_19) when _T_4958 : connect remapVecData[19], Queue16_UInt8_13.io.deq.bits connect remapVecValids[19], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_4959 = eq(UInt<4>(0he), remapindex_19) when _T_4959 : connect remapVecData[19], Queue16_UInt8_14.io.deq.bits connect remapVecValids[19], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_4960 = eq(UInt<4>(0hf), remapindex_19) when _T_4960 : connect remapVecData[19], Queue16_UInt8_15.io.deq.bits connect remapVecValids[19], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_4961 = eq(UInt<5>(0h10), remapindex_19) when _T_4961 : connect remapVecData[19], Queue16_UInt8_16.io.deq.bits connect remapVecValids[19], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_4962 = eq(UInt<5>(0h11), remapindex_19) when _T_4962 : connect remapVecData[19], Queue16_UInt8_17.io.deq.bits connect remapVecValids[19], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_4963 = eq(UInt<5>(0h12), remapindex_19) when _T_4963 : connect remapVecData[19], Queue16_UInt8_18.io.deq.bits connect remapVecValids[19], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_4964 = eq(UInt<5>(0h13), remapindex_19) when _T_4964 : connect remapVecData[19], Queue16_UInt8_19.io.deq.bits connect remapVecValids[19], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_4965 = eq(UInt<5>(0h14), remapindex_19) when _T_4965 : connect remapVecData[19], Queue16_UInt8_20.io.deq.bits connect remapVecValids[19], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_4966 = eq(UInt<5>(0h15), remapindex_19) when _T_4966 : connect remapVecData[19], Queue16_UInt8_21.io.deq.bits connect remapVecValids[19], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_4967 = eq(UInt<5>(0h16), remapindex_19) when _T_4967 : connect remapVecData[19], Queue16_UInt8_22.io.deq.bits connect remapVecValids[19], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_4968 = eq(UInt<5>(0h17), remapindex_19) when _T_4968 : connect remapVecData[19], Queue16_UInt8_23.io.deq.bits connect remapVecValids[19], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_4969 = eq(UInt<5>(0h18), remapindex_19) when _T_4969 : connect remapVecData[19], Queue16_UInt8_24.io.deq.bits connect remapVecValids[19], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_4970 = eq(UInt<5>(0h19), remapindex_19) when _T_4970 : connect remapVecData[19], Queue16_UInt8_25.io.deq.bits connect remapVecValids[19], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_4971 = eq(UInt<5>(0h1a), remapindex_19) when _T_4971 : connect remapVecData[19], Queue16_UInt8_26.io.deq.bits connect remapVecValids[19], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_4972 = eq(UInt<5>(0h1b), remapindex_19) when _T_4972 : connect remapVecData[19], Queue16_UInt8_27.io.deq.bits connect remapVecValids[19], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_4973 = eq(UInt<5>(0h1c), remapindex_19) when _T_4973 : connect remapVecData[19], Queue16_UInt8_28.io.deq.bits connect remapVecValids[19], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_4974 = eq(UInt<5>(0h1d), remapindex_19) when _T_4974 : connect remapVecData[19], Queue16_UInt8_29.io.deq.bits connect remapVecValids[19], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_4975 = eq(UInt<5>(0h1e), remapindex_19) when _T_4975 : connect remapVecData[19], Queue16_UInt8_30.io.deq.bits connect remapVecValids[19], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_4976 = eq(UInt<5>(0h1f), remapindex_19) when _T_4976 : connect remapVecData[19], Queue16_UInt8_31.io.deq.bits connect remapVecValids[19], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_4977 = eq(UInt<1>(0h0), remapindex_20) when _T_4977 : connect remapVecData[20], Queue16_UInt8.io.deq.bits connect remapVecValids[20], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[20] node _T_4978 = eq(UInt<1>(0h1), remapindex_20) when _T_4978 : connect remapVecData[20], Queue16_UInt8_1.io.deq.bits connect remapVecValids[20], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_4979 = eq(UInt<2>(0h2), remapindex_20) when _T_4979 : connect remapVecData[20], Queue16_UInt8_2.io.deq.bits connect remapVecValids[20], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_4980 = eq(UInt<2>(0h3), remapindex_20) when _T_4980 : connect remapVecData[20], Queue16_UInt8_3.io.deq.bits connect remapVecValids[20], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_4981 = eq(UInt<3>(0h4), remapindex_20) when _T_4981 : connect remapVecData[20], Queue16_UInt8_4.io.deq.bits connect remapVecValids[20], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_4982 = eq(UInt<3>(0h5), remapindex_20) when _T_4982 : connect remapVecData[20], Queue16_UInt8_5.io.deq.bits connect remapVecValids[20], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_4983 = eq(UInt<3>(0h6), remapindex_20) when _T_4983 : connect remapVecData[20], Queue16_UInt8_6.io.deq.bits connect remapVecValids[20], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_4984 = eq(UInt<3>(0h7), remapindex_20) when _T_4984 : connect remapVecData[20], Queue16_UInt8_7.io.deq.bits connect remapVecValids[20], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_4985 = eq(UInt<4>(0h8), remapindex_20) when _T_4985 : connect remapVecData[20], Queue16_UInt8_8.io.deq.bits connect remapVecValids[20], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_4986 = eq(UInt<4>(0h9), remapindex_20) when _T_4986 : connect remapVecData[20], Queue16_UInt8_9.io.deq.bits connect remapVecValids[20], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_4987 = eq(UInt<4>(0ha), remapindex_20) when _T_4987 : connect remapVecData[20], Queue16_UInt8_10.io.deq.bits connect remapVecValids[20], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_4988 = eq(UInt<4>(0hb), remapindex_20) when _T_4988 : connect remapVecData[20], Queue16_UInt8_11.io.deq.bits connect remapVecValids[20], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_4989 = eq(UInt<4>(0hc), remapindex_20) when _T_4989 : connect remapVecData[20], Queue16_UInt8_12.io.deq.bits connect remapVecValids[20], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_4990 = eq(UInt<4>(0hd), remapindex_20) when _T_4990 : connect remapVecData[20], Queue16_UInt8_13.io.deq.bits connect remapVecValids[20], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_4991 = eq(UInt<4>(0he), remapindex_20) when _T_4991 : connect remapVecData[20], Queue16_UInt8_14.io.deq.bits connect remapVecValids[20], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_4992 = eq(UInt<4>(0hf), remapindex_20) when _T_4992 : connect remapVecData[20], Queue16_UInt8_15.io.deq.bits connect remapVecValids[20], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_4993 = eq(UInt<5>(0h10), remapindex_20) when _T_4993 : connect remapVecData[20], Queue16_UInt8_16.io.deq.bits connect remapVecValids[20], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_4994 = eq(UInt<5>(0h11), remapindex_20) when _T_4994 : connect remapVecData[20], Queue16_UInt8_17.io.deq.bits connect remapVecValids[20], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_4995 = eq(UInt<5>(0h12), remapindex_20) when _T_4995 : connect remapVecData[20], Queue16_UInt8_18.io.deq.bits connect remapVecValids[20], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_4996 = eq(UInt<5>(0h13), remapindex_20) when _T_4996 : connect remapVecData[20], Queue16_UInt8_19.io.deq.bits connect remapVecValids[20], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_4997 = eq(UInt<5>(0h14), remapindex_20) when _T_4997 : connect remapVecData[20], Queue16_UInt8_20.io.deq.bits connect remapVecValids[20], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_4998 = eq(UInt<5>(0h15), remapindex_20) when _T_4998 : connect remapVecData[20], Queue16_UInt8_21.io.deq.bits connect remapVecValids[20], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_4999 = eq(UInt<5>(0h16), remapindex_20) when _T_4999 : connect remapVecData[20], Queue16_UInt8_22.io.deq.bits connect remapVecValids[20], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_5000 = eq(UInt<5>(0h17), remapindex_20) when _T_5000 : connect remapVecData[20], Queue16_UInt8_23.io.deq.bits connect remapVecValids[20], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_5001 = eq(UInt<5>(0h18), remapindex_20) when _T_5001 : connect remapVecData[20], Queue16_UInt8_24.io.deq.bits connect remapVecValids[20], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_5002 = eq(UInt<5>(0h19), remapindex_20) when _T_5002 : connect remapVecData[20], Queue16_UInt8_25.io.deq.bits connect remapVecValids[20], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_5003 = eq(UInt<5>(0h1a), remapindex_20) when _T_5003 : connect remapVecData[20], Queue16_UInt8_26.io.deq.bits connect remapVecValids[20], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_5004 = eq(UInt<5>(0h1b), remapindex_20) when _T_5004 : connect remapVecData[20], Queue16_UInt8_27.io.deq.bits connect remapVecValids[20], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_5005 = eq(UInt<5>(0h1c), remapindex_20) when _T_5005 : connect remapVecData[20], Queue16_UInt8_28.io.deq.bits connect remapVecValids[20], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_5006 = eq(UInt<5>(0h1d), remapindex_20) when _T_5006 : connect remapVecData[20], Queue16_UInt8_29.io.deq.bits connect remapVecValids[20], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_5007 = eq(UInt<5>(0h1e), remapindex_20) when _T_5007 : connect remapVecData[20], Queue16_UInt8_30.io.deq.bits connect remapVecValids[20], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_5008 = eq(UInt<5>(0h1f), remapindex_20) when _T_5008 : connect remapVecData[20], Queue16_UInt8_31.io.deq.bits connect remapVecValids[20], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_5009 = eq(UInt<1>(0h0), remapindex_21) when _T_5009 : connect remapVecData[21], Queue16_UInt8.io.deq.bits connect remapVecValids[21], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[21] node _T_5010 = eq(UInt<1>(0h1), remapindex_21) when _T_5010 : connect remapVecData[21], Queue16_UInt8_1.io.deq.bits connect remapVecValids[21], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_5011 = eq(UInt<2>(0h2), remapindex_21) when _T_5011 : connect remapVecData[21], Queue16_UInt8_2.io.deq.bits connect remapVecValids[21], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_5012 = eq(UInt<2>(0h3), remapindex_21) when _T_5012 : connect remapVecData[21], Queue16_UInt8_3.io.deq.bits connect remapVecValids[21], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_5013 = eq(UInt<3>(0h4), remapindex_21) when _T_5013 : connect remapVecData[21], Queue16_UInt8_4.io.deq.bits connect remapVecValids[21], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_5014 = eq(UInt<3>(0h5), remapindex_21) when _T_5014 : connect remapVecData[21], Queue16_UInt8_5.io.deq.bits connect remapVecValids[21], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_5015 = eq(UInt<3>(0h6), remapindex_21) when _T_5015 : connect remapVecData[21], Queue16_UInt8_6.io.deq.bits connect remapVecValids[21], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_5016 = eq(UInt<3>(0h7), remapindex_21) when _T_5016 : connect remapVecData[21], Queue16_UInt8_7.io.deq.bits connect remapVecValids[21], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_5017 = eq(UInt<4>(0h8), remapindex_21) when _T_5017 : connect remapVecData[21], Queue16_UInt8_8.io.deq.bits connect remapVecValids[21], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_5018 = eq(UInt<4>(0h9), remapindex_21) when _T_5018 : connect remapVecData[21], Queue16_UInt8_9.io.deq.bits connect remapVecValids[21], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_5019 = eq(UInt<4>(0ha), remapindex_21) when _T_5019 : connect remapVecData[21], Queue16_UInt8_10.io.deq.bits connect remapVecValids[21], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_5020 = eq(UInt<4>(0hb), remapindex_21) when _T_5020 : connect remapVecData[21], Queue16_UInt8_11.io.deq.bits connect remapVecValids[21], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_5021 = eq(UInt<4>(0hc), remapindex_21) when _T_5021 : connect remapVecData[21], Queue16_UInt8_12.io.deq.bits connect remapVecValids[21], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_5022 = eq(UInt<4>(0hd), remapindex_21) when _T_5022 : connect remapVecData[21], Queue16_UInt8_13.io.deq.bits connect remapVecValids[21], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_5023 = eq(UInt<4>(0he), remapindex_21) when _T_5023 : connect remapVecData[21], Queue16_UInt8_14.io.deq.bits connect remapVecValids[21], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_5024 = eq(UInt<4>(0hf), remapindex_21) when _T_5024 : connect remapVecData[21], Queue16_UInt8_15.io.deq.bits connect remapVecValids[21], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_5025 = eq(UInt<5>(0h10), remapindex_21) when _T_5025 : connect remapVecData[21], Queue16_UInt8_16.io.deq.bits connect remapVecValids[21], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_5026 = eq(UInt<5>(0h11), remapindex_21) when _T_5026 : connect remapVecData[21], Queue16_UInt8_17.io.deq.bits connect remapVecValids[21], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_5027 = eq(UInt<5>(0h12), remapindex_21) when _T_5027 : connect remapVecData[21], Queue16_UInt8_18.io.deq.bits connect remapVecValids[21], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_5028 = eq(UInt<5>(0h13), remapindex_21) when _T_5028 : connect remapVecData[21], Queue16_UInt8_19.io.deq.bits connect remapVecValids[21], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_5029 = eq(UInt<5>(0h14), remapindex_21) when _T_5029 : connect remapVecData[21], Queue16_UInt8_20.io.deq.bits connect remapVecValids[21], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_5030 = eq(UInt<5>(0h15), remapindex_21) when _T_5030 : connect remapVecData[21], Queue16_UInt8_21.io.deq.bits connect remapVecValids[21], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_5031 = eq(UInt<5>(0h16), remapindex_21) when _T_5031 : connect remapVecData[21], Queue16_UInt8_22.io.deq.bits connect remapVecValids[21], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_5032 = eq(UInt<5>(0h17), remapindex_21) when _T_5032 : connect remapVecData[21], Queue16_UInt8_23.io.deq.bits connect remapVecValids[21], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_5033 = eq(UInt<5>(0h18), remapindex_21) when _T_5033 : connect remapVecData[21], Queue16_UInt8_24.io.deq.bits connect remapVecValids[21], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_5034 = eq(UInt<5>(0h19), remapindex_21) when _T_5034 : connect remapVecData[21], Queue16_UInt8_25.io.deq.bits connect remapVecValids[21], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_5035 = eq(UInt<5>(0h1a), remapindex_21) when _T_5035 : connect remapVecData[21], Queue16_UInt8_26.io.deq.bits connect remapVecValids[21], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_5036 = eq(UInt<5>(0h1b), remapindex_21) when _T_5036 : connect remapVecData[21], Queue16_UInt8_27.io.deq.bits connect remapVecValids[21], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_5037 = eq(UInt<5>(0h1c), remapindex_21) when _T_5037 : connect remapVecData[21], Queue16_UInt8_28.io.deq.bits connect remapVecValids[21], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_5038 = eq(UInt<5>(0h1d), remapindex_21) when _T_5038 : connect remapVecData[21], Queue16_UInt8_29.io.deq.bits connect remapVecValids[21], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_5039 = eq(UInt<5>(0h1e), remapindex_21) when _T_5039 : connect remapVecData[21], Queue16_UInt8_30.io.deq.bits connect remapVecValids[21], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_5040 = eq(UInt<5>(0h1f), remapindex_21) when _T_5040 : connect remapVecData[21], Queue16_UInt8_31.io.deq.bits connect remapVecValids[21], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_5041 = eq(UInt<1>(0h0), remapindex_22) when _T_5041 : connect remapVecData[22], Queue16_UInt8.io.deq.bits connect remapVecValids[22], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[22] node _T_5042 = eq(UInt<1>(0h1), remapindex_22) when _T_5042 : connect remapVecData[22], Queue16_UInt8_1.io.deq.bits connect remapVecValids[22], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_5043 = eq(UInt<2>(0h2), remapindex_22) when _T_5043 : connect remapVecData[22], Queue16_UInt8_2.io.deq.bits connect remapVecValids[22], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_5044 = eq(UInt<2>(0h3), remapindex_22) when _T_5044 : connect remapVecData[22], Queue16_UInt8_3.io.deq.bits connect remapVecValids[22], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_5045 = eq(UInt<3>(0h4), remapindex_22) when _T_5045 : connect remapVecData[22], Queue16_UInt8_4.io.deq.bits connect remapVecValids[22], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_5046 = eq(UInt<3>(0h5), remapindex_22) when _T_5046 : connect remapVecData[22], Queue16_UInt8_5.io.deq.bits connect remapVecValids[22], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_5047 = eq(UInt<3>(0h6), remapindex_22) when _T_5047 : connect remapVecData[22], Queue16_UInt8_6.io.deq.bits connect remapVecValids[22], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_5048 = eq(UInt<3>(0h7), remapindex_22) when _T_5048 : connect remapVecData[22], Queue16_UInt8_7.io.deq.bits connect remapVecValids[22], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_5049 = eq(UInt<4>(0h8), remapindex_22) when _T_5049 : connect remapVecData[22], Queue16_UInt8_8.io.deq.bits connect remapVecValids[22], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_5050 = eq(UInt<4>(0h9), remapindex_22) when _T_5050 : connect remapVecData[22], Queue16_UInt8_9.io.deq.bits connect remapVecValids[22], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_5051 = eq(UInt<4>(0ha), remapindex_22) when _T_5051 : connect remapVecData[22], Queue16_UInt8_10.io.deq.bits connect remapVecValids[22], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_5052 = eq(UInt<4>(0hb), remapindex_22) when _T_5052 : connect remapVecData[22], Queue16_UInt8_11.io.deq.bits connect remapVecValids[22], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_5053 = eq(UInt<4>(0hc), remapindex_22) when _T_5053 : connect remapVecData[22], Queue16_UInt8_12.io.deq.bits connect remapVecValids[22], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_5054 = eq(UInt<4>(0hd), remapindex_22) when _T_5054 : connect remapVecData[22], Queue16_UInt8_13.io.deq.bits connect remapVecValids[22], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_5055 = eq(UInt<4>(0he), remapindex_22) when _T_5055 : connect remapVecData[22], Queue16_UInt8_14.io.deq.bits connect remapVecValids[22], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_5056 = eq(UInt<4>(0hf), remapindex_22) when _T_5056 : connect remapVecData[22], Queue16_UInt8_15.io.deq.bits connect remapVecValids[22], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_5057 = eq(UInt<5>(0h10), remapindex_22) when _T_5057 : connect remapVecData[22], Queue16_UInt8_16.io.deq.bits connect remapVecValids[22], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_5058 = eq(UInt<5>(0h11), remapindex_22) when _T_5058 : connect remapVecData[22], Queue16_UInt8_17.io.deq.bits connect remapVecValids[22], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_5059 = eq(UInt<5>(0h12), remapindex_22) when _T_5059 : connect remapVecData[22], Queue16_UInt8_18.io.deq.bits connect remapVecValids[22], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_5060 = eq(UInt<5>(0h13), remapindex_22) when _T_5060 : connect remapVecData[22], Queue16_UInt8_19.io.deq.bits connect remapVecValids[22], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_5061 = eq(UInt<5>(0h14), remapindex_22) when _T_5061 : connect remapVecData[22], Queue16_UInt8_20.io.deq.bits connect remapVecValids[22], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_5062 = eq(UInt<5>(0h15), remapindex_22) when _T_5062 : connect remapVecData[22], Queue16_UInt8_21.io.deq.bits connect remapVecValids[22], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_5063 = eq(UInt<5>(0h16), remapindex_22) when _T_5063 : connect remapVecData[22], Queue16_UInt8_22.io.deq.bits connect remapVecValids[22], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_5064 = eq(UInt<5>(0h17), remapindex_22) when _T_5064 : connect remapVecData[22], Queue16_UInt8_23.io.deq.bits connect remapVecValids[22], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_5065 = eq(UInt<5>(0h18), remapindex_22) when _T_5065 : connect remapVecData[22], Queue16_UInt8_24.io.deq.bits connect remapVecValids[22], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_5066 = eq(UInt<5>(0h19), remapindex_22) when _T_5066 : connect remapVecData[22], Queue16_UInt8_25.io.deq.bits connect remapVecValids[22], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_5067 = eq(UInt<5>(0h1a), remapindex_22) when _T_5067 : connect remapVecData[22], Queue16_UInt8_26.io.deq.bits connect remapVecValids[22], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_5068 = eq(UInt<5>(0h1b), remapindex_22) when _T_5068 : connect remapVecData[22], Queue16_UInt8_27.io.deq.bits connect remapVecValids[22], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_5069 = eq(UInt<5>(0h1c), remapindex_22) when _T_5069 : connect remapVecData[22], Queue16_UInt8_28.io.deq.bits connect remapVecValids[22], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_5070 = eq(UInt<5>(0h1d), remapindex_22) when _T_5070 : connect remapVecData[22], Queue16_UInt8_29.io.deq.bits connect remapVecValids[22], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_5071 = eq(UInt<5>(0h1e), remapindex_22) when _T_5071 : connect remapVecData[22], Queue16_UInt8_30.io.deq.bits connect remapVecValids[22], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_5072 = eq(UInt<5>(0h1f), remapindex_22) when _T_5072 : connect remapVecData[22], Queue16_UInt8_31.io.deq.bits connect remapVecValids[22], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_5073 = eq(UInt<1>(0h0), remapindex_23) when _T_5073 : connect remapVecData[23], Queue16_UInt8.io.deq.bits connect remapVecValids[23], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[23] node _T_5074 = eq(UInt<1>(0h1), remapindex_23) when _T_5074 : connect remapVecData[23], Queue16_UInt8_1.io.deq.bits connect remapVecValids[23], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_5075 = eq(UInt<2>(0h2), remapindex_23) when _T_5075 : connect remapVecData[23], Queue16_UInt8_2.io.deq.bits connect remapVecValids[23], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_5076 = eq(UInt<2>(0h3), remapindex_23) when _T_5076 : connect remapVecData[23], Queue16_UInt8_3.io.deq.bits connect remapVecValids[23], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_5077 = eq(UInt<3>(0h4), remapindex_23) when _T_5077 : connect remapVecData[23], Queue16_UInt8_4.io.deq.bits connect remapVecValids[23], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_5078 = eq(UInt<3>(0h5), remapindex_23) when _T_5078 : connect remapVecData[23], Queue16_UInt8_5.io.deq.bits connect remapVecValids[23], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_5079 = eq(UInt<3>(0h6), remapindex_23) when _T_5079 : connect remapVecData[23], Queue16_UInt8_6.io.deq.bits connect remapVecValids[23], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_5080 = eq(UInt<3>(0h7), remapindex_23) when _T_5080 : connect remapVecData[23], Queue16_UInt8_7.io.deq.bits connect remapVecValids[23], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_5081 = eq(UInt<4>(0h8), remapindex_23) when _T_5081 : connect remapVecData[23], Queue16_UInt8_8.io.deq.bits connect remapVecValids[23], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_5082 = eq(UInt<4>(0h9), remapindex_23) when _T_5082 : connect remapVecData[23], Queue16_UInt8_9.io.deq.bits connect remapVecValids[23], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_5083 = eq(UInt<4>(0ha), remapindex_23) when _T_5083 : connect remapVecData[23], Queue16_UInt8_10.io.deq.bits connect remapVecValids[23], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_5084 = eq(UInt<4>(0hb), remapindex_23) when _T_5084 : connect remapVecData[23], Queue16_UInt8_11.io.deq.bits connect remapVecValids[23], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_5085 = eq(UInt<4>(0hc), remapindex_23) when _T_5085 : connect remapVecData[23], Queue16_UInt8_12.io.deq.bits connect remapVecValids[23], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_5086 = eq(UInt<4>(0hd), remapindex_23) when _T_5086 : connect remapVecData[23], Queue16_UInt8_13.io.deq.bits connect remapVecValids[23], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_5087 = eq(UInt<4>(0he), remapindex_23) when _T_5087 : connect remapVecData[23], Queue16_UInt8_14.io.deq.bits connect remapVecValids[23], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_5088 = eq(UInt<4>(0hf), remapindex_23) when _T_5088 : connect remapVecData[23], Queue16_UInt8_15.io.deq.bits connect remapVecValids[23], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_5089 = eq(UInt<5>(0h10), remapindex_23) when _T_5089 : connect remapVecData[23], Queue16_UInt8_16.io.deq.bits connect remapVecValids[23], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_5090 = eq(UInt<5>(0h11), remapindex_23) when _T_5090 : connect remapVecData[23], Queue16_UInt8_17.io.deq.bits connect remapVecValids[23], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_5091 = eq(UInt<5>(0h12), remapindex_23) when _T_5091 : connect remapVecData[23], Queue16_UInt8_18.io.deq.bits connect remapVecValids[23], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_5092 = eq(UInt<5>(0h13), remapindex_23) when _T_5092 : connect remapVecData[23], Queue16_UInt8_19.io.deq.bits connect remapVecValids[23], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_5093 = eq(UInt<5>(0h14), remapindex_23) when _T_5093 : connect remapVecData[23], Queue16_UInt8_20.io.deq.bits connect remapVecValids[23], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_5094 = eq(UInt<5>(0h15), remapindex_23) when _T_5094 : connect remapVecData[23], Queue16_UInt8_21.io.deq.bits connect remapVecValids[23], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_5095 = eq(UInt<5>(0h16), remapindex_23) when _T_5095 : connect remapVecData[23], Queue16_UInt8_22.io.deq.bits connect remapVecValids[23], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_5096 = eq(UInt<5>(0h17), remapindex_23) when _T_5096 : connect remapVecData[23], Queue16_UInt8_23.io.deq.bits connect remapVecValids[23], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_5097 = eq(UInt<5>(0h18), remapindex_23) when _T_5097 : connect remapVecData[23], Queue16_UInt8_24.io.deq.bits connect remapVecValids[23], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_5098 = eq(UInt<5>(0h19), remapindex_23) when _T_5098 : connect remapVecData[23], Queue16_UInt8_25.io.deq.bits connect remapVecValids[23], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_5099 = eq(UInt<5>(0h1a), remapindex_23) when _T_5099 : connect remapVecData[23], Queue16_UInt8_26.io.deq.bits connect remapVecValids[23], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_5100 = eq(UInt<5>(0h1b), remapindex_23) when _T_5100 : connect remapVecData[23], Queue16_UInt8_27.io.deq.bits connect remapVecValids[23], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_5101 = eq(UInt<5>(0h1c), remapindex_23) when _T_5101 : connect remapVecData[23], Queue16_UInt8_28.io.deq.bits connect remapVecValids[23], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_5102 = eq(UInt<5>(0h1d), remapindex_23) when _T_5102 : connect remapVecData[23], Queue16_UInt8_29.io.deq.bits connect remapVecValids[23], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_5103 = eq(UInt<5>(0h1e), remapindex_23) when _T_5103 : connect remapVecData[23], Queue16_UInt8_30.io.deq.bits connect remapVecValids[23], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_5104 = eq(UInt<5>(0h1f), remapindex_23) when _T_5104 : connect remapVecData[23], Queue16_UInt8_31.io.deq.bits connect remapVecValids[23], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_5105 = eq(UInt<1>(0h0), remapindex_24) when _T_5105 : connect remapVecData[24], Queue16_UInt8.io.deq.bits connect remapVecValids[24], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[24] node _T_5106 = eq(UInt<1>(0h1), remapindex_24) when _T_5106 : connect remapVecData[24], Queue16_UInt8_1.io.deq.bits connect remapVecValids[24], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_5107 = eq(UInt<2>(0h2), remapindex_24) when _T_5107 : connect remapVecData[24], Queue16_UInt8_2.io.deq.bits connect remapVecValids[24], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_5108 = eq(UInt<2>(0h3), remapindex_24) when _T_5108 : connect remapVecData[24], Queue16_UInt8_3.io.deq.bits connect remapVecValids[24], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_5109 = eq(UInt<3>(0h4), remapindex_24) when _T_5109 : connect remapVecData[24], Queue16_UInt8_4.io.deq.bits connect remapVecValids[24], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_5110 = eq(UInt<3>(0h5), remapindex_24) when _T_5110 : connect remapVecData[24], Queue16_UInt8_5.io.deq.bits connect remapVecValids[24], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_5111 = eq(UInt<3>(0h6), remapindex_24) when _T_5111 : connect remapVecData[24], Queue16_UInt8_6.io.deq.bits connect remapVecValids[24], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_5112 = eq(UInt<3>(0h7), remapindex_24) when _T_5112 : connect remapVecData[24], Queue16_UInt8_7.io.deq.bits connect remapVecValids[24], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_5113 = eq(UInt<4>(0h8), remapindex_24) when _T_5113 : connect remapVecData[24], Queue16_UInt8_8.io.deq.bits connect remapVecValids[24], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_5114 = eq(UInt<4>(0h9), remapindex_24) when _T_5114 : connect remapVecData[24], Queue16_UInt8_9.io.deq.bits connect remapVecValids[24], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_5115 = eq(UInt<4>(0ha), remapindex_24) when _T_5115 : connect remapVecData[24], Queue16_UInt8_10.io.deq.bits connect remapVecValids[24], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_5116 = eq(UInt<4>(0hb), remapindex_24) when _T_5116 : connect remapVecData[24], Queue16_UInt8_11.io.deq.bits connect remapVecValids[24], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_5117 = eq(UInt<4>(0hc), remapindex_24) when _T_5117 : connect remapVecData[24], Queue16_UInt8_12.io.deq.bits connect remapVecValids[24], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_5118 = eq(UInt<4>(0hd), remapindex_24) when _T_5118 : connect remapVecData[24], Queue16_UInt8_13.io.deq.bits connect remapVecValids[24], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_5119 = eq(UInt<4>(0he), remapindex_24) when _T_5119 : connect remapVecData[24], Queue16_UInt8_14.io.deq.bits connect remapVecValids[24], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_5120 = eq(UInt<4>(0hf), remapindex_24) when _T_5120 : connect remapVecData[24], Queue16_UInt8_15.io.deq.bits connect remapVecValids[24], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_5121 = eq(UInt<5>(0h10), remapindex_24) when _T_5121 : connect remapVecData[24], Queue16_UInt8_16.io.deq.bits connect remapVecValids[24], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_5122 = eq(UInt<5>(0h11), remapindex_24) when _T_5122 : connect remapVecData[24], Queue16_UInt8_17.io.deq.bits connect remapVecValids[24], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_5123 = eq(UInt<5>(0h12), remapindex_24) when _T_5123 : connect remapVecData[24], Queue16_UInt8_18.io.deq.bits connect remapVecValids[24], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_5124 = eq(UInt<5>(0h13), remapindex_24) when _T_5124 : connect remapVecData[24], Queue16_UInt8_19.io.deq.bits connect remapVecValids[24], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_5125 = eq(UInt<5>(0h14), remapindex_24) when _T_5125 : connect remapVecData[24], Queue16_UInt8_20.io.deq.bits connect remapVecValids[24], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_5126 = eq(UInt<5>(0h15), remapindex_24) when _T_5126 : connect remapVecData[24], Queue16_UInt8_21.io.deq.bits connect remapVecValids[24], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_5127 = eq(UInt<5>(0h16), remapindex_24) when _T_5127 : connect remapVecData[24], Queue16_UInt8_22.io.deq.bits connect remapVecValids[24], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_5128 = eq(UInt<5>(0h17), remapindex_24) when _T_5128 : connect remapVecData[24], Queue16_UInt8_23.io.deq.bits connect remapVecValids[24], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_5129 = eq(UInt<5>(0h18), remapindex_24) when _T_5129 : connect remapVecData[24], Queue16_UInt8_24.io.deq.bits connect remapVecValids[24], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_5130 = eq(UInt<5>(0h19), remapindex_24) when _T_5130 : connect remapVecData[24], Queue16_UInt8_25.io.deq.bits connect remapVecValids[24], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_5131 = eq(UInt<5>(0h1a), remapindex_24) when _T_5131 : connect remapVecData[24], Queue16_UInt8_26.io.deq.bits connect remapVecValids[24], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_5132 = eq(UInt<5>(0h1b), remapindex_24) when _T_5132 : connect remapVecData[24], Queue16_UInt8_27.io.deq.bits connect remapVecValids[24], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_5133 = eq(UInt<5>(0h1c), remapindex_24) when _T_5133 : connect remapVecData[24], Queue16_UInt8_28.io.deq.bits connect remapVecValids[24], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_5134 = eq(UInt<5>(0h1d), remapindex_24) when _T_5134 : connect remapVecData[24], Queue16_UInt8_29.io.deq.bits connect remapVecValids[24], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_5135 = eq(UInt<5>(0h1e), remapindex_24) when _T_5135 : connect remapVecData[24], Queue16_UInt8_30.io.deq.bits connect remapVecValids[24], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_5136 = eq(UInt<5>(0h1f), remapindex_24) when _T_5136 : connect remapVecData[24], Queue16_UInt8_31.io.deq.bits connect remapVecValids[24], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_5137 = eq(UInt<1>(0h0), remapindex_25) when _T_5137 : connect remapVecData[25], Queue16_UInt8.io.deq.bits connect remapVecValids[25], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[25] node _T_5138 = eq(UInt<1>(0h1), remapindex_25) when _T_5138 : connect remapVecData[25], Queue16_UInt8_1.io.deq.bits connect remapVecValids[25], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_5139 = eq(UInt<2>(0h2), remapindex_25) when _T_5139 : connect remapVecData[25], Queue16_UInt8_2.io.deq.bits connect remapVecValids[25], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_5140 = eq(UInt<2>(0h3), remapindex_25) when _T_5140 : connect remapVecData[25], Queue16_UInt8_3.io.deq.bits connect remapVecValids[25], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_5141 = eq(UInt<3>(0h4), remapindex_25) when _T_5141 : connect remapVecData[25], Queue16_UInt8_4.io.deq.bits connect remapVecValids[25], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_5142 = eq(UInt<3>(0h5), remapindex_25) when _T_5142 : connect remapVecData[25], Queue16_UInt8_5.io.deq.bits connect remapVecValids[25], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_5143 = eq(UInt<3>(0h6), remapindex_25) when _T_5143 : connect remapVecData[25], Queue16_UInt8_6.io.deq.bits connect remapVecValids[25], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_5144 = eq(UInt<3>(0h7), remapindex_25) when _T_5144 : connect remapVecData[25], Queue16_UInt8_7.io.deq.bits connect remapVecValids[25], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_5145 = eq(UInt<4>(0h8), remapindex_25) when _T_5145 : connect remapVecData[25], Queue16_UInt8_8.io.deq.bits connect remapVecValids[25], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_5146 = eq(UInt<4>(0h9), remapindex_25) when _T_5146 : connect remapVecData[25], Queue16_UInt8_9.io.deq.bits connect remapVecValids[25], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_5147 = eq(UInt<4>(0ha), remapindex_25) when _T_5147 : connect remapVecData[25], Queue16_UInt8_10.io.deq.bits connect remapVecValids[25], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_5148 = eq(UInt<4>(0hb), remapindex_25) when _T_5148 : connect remapVecData[25], Queue16_UInt8_11.io.deq.bits connect remapVecValids[25], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_5149 = eq(UInt<4>(0hc), remapindex_25) when _T_5149 : connect remapVecData[25], Queue16_UInt8_12.io.deq.bits connect remapVecValids[25], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_5150 = eq(UInt<4>(0hd), remapindex_25) when _T_5150 : connect remapVecData[25], Queue16_UInt8_13.io.deq.bits connect remapVecValids[25], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_5151 = eq(UInt<4>(0he), remapindex_25) when _T_5151 : connect remapVecData[25], Queue16_UInt8_14.io.deq.bits connect remapVecValids[25], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_5152 = eq(UInt<4>(0hf), remapindex_25) when _T_5152 : connect remapVecData[25], Queue16_UInt8_15.io.deq.bits connect remapVecValids[25], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_5153 = eq(UInt<5>(0h10), remapindex_25) when _T_5153 : connect remapVecData[25], Queue16_UInt8_16.io.deq.bits connect remapVecValids[25], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_5154 = eq(UInt<5>(0h11), remapindex_25) when _T_5154 : connect remapVecData[25], Queue16_UInt8_17.io.deq.bits connect remapVecValids[25], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_5155 = eq(UInt<5>(0h12), remapindex_25) when _T_5155 : connect remapVecData[25], Queue16_UInt8_18.io.deq.bits connect remapVecValids[25], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_5156 = eq(UInt<5>(0h13), remapindex_25) when _T_5156 : connect remapVecData[25], Queue16_UInt8_19.io.deq.bits connect remapVecValids[25], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_5157 = eq(UInt<5>(0h14), remapindex_25) when _T_5157 : connect remapVecData[25], Queue16_UInt8_20.io.deq.bits connect remapVecValids[25], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_5158 = eq(UInt<5>(0h15), remapindex_25) when _T_5158 : connect remapVecData[25], Queue16_UInt8_21.io.deq.bits connect remapVecValids[25], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_5159 = eq(UInt<5>(0h16), remapindex_25) when _T_5159 : connect remapVecData[25], Queue16_UInt8_22.io.deq.bits connect remapVecValids[25], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_5160 = eq(UInt<5>(0h17), remapindex_25) when _T_5160 : connect remapVecData[25], Queue16_UInt8_23.io.deq.bits connect remapVecValids[25], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_5161 = eq(UInt<5>(0h18), remapindex_25) when _T_5161 : connect remapVecData[25], Queue16_UInt8_24.io.deq.bits connect remapVecValids[25], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_5162 = eq(UInt<5>(0h19), remapindex_25) when _T_5162 : connect remapVecData[25], Queue16_UInt8_25.io.deq.bits connect remapVecValids[25], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_5163 = eq(UInt<5>(0h1a), remapindex_25) when _T_5163 : connect remapVecData[25], Queue16_UInt8_26.io.deq.bits connect remapVecValids[25], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_5164 = eq(UInt<5>(0h1b), remapindex_25) when _T_5164 : connect remapVecData[25], Queue16_UInt8_27.io.deq.bits connect remapVecValids[25], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_5165 = eq(UInt<5>(0h1c), remapindex_25) when _T_5165 : connect remapVecData[25], Queue16_UInt8_28.io.deq.bits connect remapVecValids[25], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_5166 = eq(UInt<5>(0h1d), remapindex_25) when _T_5166 : connect remapVecData[25], Queue16_UInt8_29.io.deq.bits connect remapVecValids[25], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_5167 = eq(UInt<5>(0h1e), remapindex_25) when _T_5167 : connect remapVecData[25], Queue16_UInt8_30.io.deq.bits connect remapVecValids[25], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_5168 = eq(UInt<5>(0h1f), remapindex_25) when _T_5168 : connect remapVecData[25], Queue16_UInt8_31.io.deq.bits connect remapVecValids[25], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_5169 = eq(UInt<1>(0h0), remapindex_26) when _T_5169 : connect remapVecData[26], Queue16_UInt8.io.deq.bits connect remapVecValids[26], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[26] node _T_5170 = eq(UInt<1>(0h1), remapindex_26) when _T_5170 : connect remapVecData[26], Queue16_UInt8_1.io.deq.bits connect remapVecValids[26], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_5171 = eq(UInt<2>(0h2), remapindex_26) when _T_5171 : connect remapVecData[26], Queue16_UInt8_2.io.deq.bits connect remapVecValids[26], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_5172 = eq(UInt<2>(0h3), remapindex_26) when _T_5172 : connect remapVecData[26], Queue16_UInt8_3.io.deq.bits connect remapVecValids[26], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_5173 = eq(UInt<3>(0h4), remapindex_26) when _T_5173 : connect remapVecData[26], Queue16_UInt8_4.io.deq.bits connect remapVecValids[26], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_5174 = eq(UInt<3>(0h5), remapindex_26) when _T_5174 : connect remapVecData[26], Queue16_UInt8_5.io.deq.bits connect remapVecValids[26], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_5175 = eq(UInt<3>(0h6), remapindex_26) when _T_5175 : connect remapVecData[26], Queue16_UInt8_6.io.deq.bits connect remapVecValids[26], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_5176 = eq(UInt<3>(0h7), remapindex_26) when _T_5176 : connect remapVecData[26], Queue16_UInt8_7.io.deq.bits connect remapVecValids[26], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_5177 = eq(UInt<4>(0h8), remapindex_26) when _T_5177 : connect remapVecData[26], Queue16_UInt8_8.io.deq.bits connect remapVecValids[26], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_5178 = eq(UInt<4>(0h9), remapindex_26) when _T_5178 : connect remapVecData[26], Queue16_UInt8_9.io.deq.bits connect remapVecValids[26], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_5179 = eq(UInt<4>(0ha), remapindex_26) when _T_5179 : connect remapVecData[26], Queue16_UInt8_10.io.deq.bits connect remapVecValids[26], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_5180 = eq(UInt<4>(0hb), remapindex_26) when _T_5180 : connect remapVecData[26], Queue16_UInt8_11.io.deq.bits connect remapVecValids[26], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_5181 = eq(UInt<4>(0hc), remapindex_26) when _T_5181 : connect remapVecData[26], Queue16_UInt8_12.io.deq.bits connect remapVecValids[26], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_5182 = eq(UInt<4>(0hd), remapindex_26) when _T_5182 : connect remapVecData[26], Queue16_UInt8_13.io.deq.bits connect remapVecValids[26], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_5183 = eq(UInt<4>(0he), remapindex_26) when _T_5183 : connect remapVecData[26], Queue16_UInt8_14.io.deq.bits connect remapVecValids[26], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_5184 = eq(UInt<4>(0hf), remapindex_26) when _T_5184 : connect remapVecData[26], Queue16_UInt8_15.io.deq.bits connect remapVecValids[26], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_5185 = eq(UInt<5>(0h10), remapindex_26) when _T_5185 : connect remapVecData[26], Queue16_UInt8_16.io.deq.bits connect remapVecValids[26], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_5186 = eq(UInt<5>(0h11), remapindex_26) when _T_5186 : connect remapVecData[26], Queue16_UInt8_17.io.deq.bits connect remapVecValids[26], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_5187 = eq(UInt<5>(0h12), remapindex_26) when _T_5187 : connect remapVecData[26], Queue16_UInt8_18.io.deq.bits connect remapVecValids[26], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_5188 = eq(UInt<5>(0h13), remapindex_26) when _T_5188 : connect remapVecData[26], Queue16_UInt8_19.io.deq.bits connect remapVecValids[26], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_5189 = eq(UInt<5>(0h14), remapindex_26) when _T_5189 : connect remapVecData[26], Queue16_UInt8_20.io.deq.bits connect remapVecValids[26], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_5190 = eq(UInt<5>(0h15), remapindex_26) when _T_5190 : connect remapVecData[26], Queue16_UInt8_21.io.deq.bits connect remapVecValids[26], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_5191 = eq(UInt<5>(0h16), remapindex_26) when _T_5191 : connect remapVecData[26], Queue16_UInt8_22.io.deq.bits connect remapVecValids[26], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_5192 = eq(UInt<5>(0h17), remapindex_26) when _T_5192 : connect remapVecData[26], Queue16_UInt8_23.io.deq.bits connect remapVecValids[26], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_5193 = eq(UInt<5>(0h18), remapindex_26) when _T_5193 : connect remapVecData[26], Queue16_UInt8_24.io.deq.bits connect remapVecValids[26], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_5194 = eq(UInt<5>(0h19), remapindex_26) when _T_5194 : connect remapVecData[26], Queue16_UInt8_25.io.deq.bits connect remapVecValids[26], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_5195 = eq(UInt<5>(0h1a), remapindex_26) when _T_5195 : connect remapVecData[26], Queue16_UInt8_26.io.deq.bits connect remapVecValids[26], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_5196 = eq(UInt<5>(0h1b), remapindex_26) when _T_5196 : connect remapVecData[26], Queue16_UInt8_27.io.deq.bits connect remapVecValids[26], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_5197 = eq(UInt<5>(0h1c), remapindex_26) when _T_5197 : connect remapVecData[26], Queue16_UInt8_28.io.deq.bits connect remapVecValids[26], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_5198 = eq(UInt<5>(0h1d), remapindex_26) when _T_5198 : connect remapVecData[26], Queue16_UInt8_29.io.deq.bits connect remapVecValids[26], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_5199 = eq(UInt<5>(0h1e), remapindex_26) when _T_5199 : connect remapVecData[26], Queue16_UInt8_30.io.deq.bits connect remapVecValids[26], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_5200 = eq(UInt<5>(0h1f), remapindex_26) when _T_5200 : connect remapVecData[26], Queue16_UInt8_31.io.deq.bits connect remapVecValids[26], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_5201 = eq(UInt<1>(0h0), remapindex_27) when _T_5201 : connect remapVecData[27], Queue16_UInt8.io.deq.bits connect remapVecValids[27], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[27] node _T_5202 = eq(UInt<1>(0h1), remapindex_27) when _T_5202 : connect remapVecData[27], Queue16_UInt8_1.io.deq.bits connect remapVecValids[27], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_5203 = eq(UInt<2>(0h2), remapindex_27) when _T_5203 : connect remapVecData[27], Queue16_UInt8_2.io.deq.bits connect remapVecValids[27], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_5204 = eq(UInt<2>(0h3), remapindex_27) when _T_5204 : connect remapVecData[27], Queue16_UInt8_3.io.deq.bits connect remapVecValids[27], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_5205 = eq(UInt<3>(0h4), remapindex_27) when _T_5205 : connect remapVecData[27], Queue16_UInt8_4.io.deq.bits connect remapVecValids[27], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_5206 = eq(UInt<3>(0h5), remapindex_27) when _T_5206 : connect remapVecData[27], Queue16_UInt8_5.io.deq.bits connect remapVecValids[27], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_5207 = eq(UInt<3>(0h6), remapindex_27) when _T_5207 : connect remapVecData[27], Queue16_UInt8_6.io.deq.bits connect remapVecValids[27], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_5208 = eq(UInt<3>(0h7), remapindex_27) when _T_5208 : connect remapVecData[27], Queue16_UInt8_7.io.deq.bits connect remapVecValids[27], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_5209 = eq(UInt<4>(0h8), remapindex_27) when _T_5209 : connect remapVecData[27], Queue16_UInt8_8.io.deq.bits connect remapVecValids[27], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_5210 = eq(UInt<4>(0h9), remapindex_27) when _T_5210 : connect remapVecData[27], Queue16_UInt8_9.io.deq.bits connect remapVecValids[27], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_5211 = eq(UInt<4>(0ha), remapindex_27) when _T_5211 : connect remapVecData[27], Queue16_UInt8_10.io.deq.bits connect remapVecValids[27], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_5212 = eq(UInt<4>(0hb), remapindex_27) when _T_5212 : connect remapVecData[27], Queue16_UInt8_11.io.deq.bits connect remapVecValids[27], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_5213 = eq(UInt<4>(0hc), remapindex_27) when _T_5213 : connect remapVecData[27], Queue16_UInt8_12.io.deq.bits connect remapVecValids[27], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_5214 = eq(UInt<4>(0hd), remapindex_27) when _T_5214 : connect remapVecData[27], Queue16_UInt8_13.io.deq.bits connect remapVecValids[27], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_5215 = eq(UInt<4>(0he), remapindex_27) when _T_5215 : connect remapVecData[27], Queue16_UInt8_14.io.deq.bits connect remapVecValids[27], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_5216 = eq(UInt<4>(0hf), remapindex_27) when _T_5216 : connect remapVecData[27], Queue16_UInt8_15.io.deq.bits connect remapVecValids[27], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_5217 = eq(UInt<5>(0h10), remapindex_27) when _T_5217 : connect remapVecData[27], Queue16_UInt8_16.io.deq.bits connect remapVecValids[27], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_5218 = eq(UInt<5>(0h11), remapindex_27) when _T_5218 : connect remapVecData[27], Queue16_UInt8_17.io.deq.bits connect remapVecValids[27], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_5219 = eq(UInt<5>(0h12), remapindex_27) when _T_5219 : connect remapVecData[27], Queue16_UInt8_18.io.deq.bits connect remapVecValids[27], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_5220 = eq(UInt<5>(0h13), remapindex_27) when _T_5220 : connect remapVecData[27], Queue16_UInt8_19.io.deq.bits connect remapVecValids[27], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_5221 = eq(UInt<5>(0h14), remapindex_27) when _T_5221 : connect remapVecData[27], Queue16_UInt8_20.io.deq.bits connect remapVecValids[27], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_5222 = eq(UInt<5>(0h15), remapindex_27) when _T_5222 : connect remapVecData[27], Queue16_UInt8_21.io.deq.bits connect remapVecValids[27], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_5223 = eq(UInt<5>(0h16), remapindex_27) when _T_5223 : connect remapVecData[27], Queue16_UInt8_22.io.deq.bits connect remapVecValids[27], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_5224 = eq(UInt<5>(0h17), remapindex_27) when _T_5224 : connect remapVecData[27], Queue16_UInt8_23.io.deq.bits connect remapVecValids[27], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_5225 = eq(UInt<5>(0h18), remapindex_27) when _T_5225 : connect remapVecData[27], Queue16_UInt8_24.io.deq.bits connect remapVecValids[27], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_5226 = eq(UInt<5>(0h19), remapindex_27) when _T_5226 : connect remapVecData[27], Queue16_UInt8_25.io.deq.bits connect remapVecValids[27], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_5227 = eq(UInt<5>(0h1a), remapindex_27) when _T_5227 : connect remapVecData[27], Queue16_UInt8_26.io.deq.bits connect remapVecValids[27], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_5228 = eq(UInt<5>(0h1b), remapindex_27) when _T_5228 : connect remapVecData[27], Queue16_UInt8_27.io.deq.bits connect remapVecValids[27], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_5229 = eq(UInt<5>(0h1c), remapindex_27) when _T_5229 : connect remapVecData[27], Queue16_UInt8_28.io.deq.bits connect remapVecValids[27], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_5230 = eq(UInt<5>(0h1d), remapindex_27) when _T_5230 : connect remapVecData[27], Queue16_UInt8_29.io.deq.bits connect remapVecValids[27], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_5231 = eq(UInt<5>(0h1e), remapindex_27) when _T_5231 : connect remapVecData[27], Queue16_UInt8_30.io.deq.bits connect remapVecValids[27], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_5232 = eq(UInt<5>(0h1f), remapindex_27) when _T_5232 : connect remapVecData[27], Queue16_UInt8_31.io.deq.bits connect remapVecValids[27], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_5233 = eq(UInt<1>(0h0), remapindex_28) when _T_5233 : connect remapVecData[28], Queue16_UInt8.io.deq.bits connect remapVecValids[28], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[28] node _T_5234 = eq(UInt<1>(0h1), remapindex_28) when _T_5234 : connect remapVecData[28], Queue16_UInt8_1.io.deq.bits connect remapVecValids[28], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_5235 = eq(UInt<2>(0h2), remapindex_28) when _T_5235 : connect remapVecData[28], Queue16_UInt8_2.io.deq.bits connect remapVecValids[28], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_5236 = eq(UInt<2>(0h3), remapindex_28) when _T_5236 : connect remapVecData[28], Queue16_UInt8_3.io.deq.bits connect remapVecValids[28], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_5237 = eq(UInt<3>(0h4), remapindex_28) when _T_5237 : connect remapVecData[28], Queue16_UInt8_4.io.deq.bits connect remapVecValids[28], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_5238 = eq(UInt<3>(0h5), remapindex_28) when _T_5238 : connect remapVecData[28], Queue16_UInt8_5.io.deq.bits connect remapVecValids[28], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_5239 = eq(UInt<3>(0h6), remapindex_28) when _T_5239 : connect remapVecData[28], Queue16_UInt8_6.io.deq.bits connect remapVecValids[28], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_5240 = eq(UInt<3>(0h7), remapindex_28) when _T_5240 : connect remapVecData[28], Queue16_UInt8_7.io.deq.bits connect remapVecValids[28], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_5241 = eq(UInt<4>(0h8), remapindex_28) when _T_5241 : connect remapVecData[28], Queue16_UInt8_8.io.deq.bits connect remapVecValids[28], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_5242 = eq(UInt<4>(0h9), remapindex_28) when _T_5242 : connect remapVecData[28], Queue16_UInt8_9.io.deq.bits connect remapVecValids[28], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_5243 = eq(UInt<4>(0ha), remapindex_28) when _T_5243 : connect remapVecData[28], Queue16_UInt8_10.io.deq.bits connect remapVecValids[28], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_5244 = eq(UInt<4>(0hb), remapindex_28) when _T_5244 : connect remapVecData[28], Queue16_UInt8_11.io.deq.bits connect remapVecValids[28], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_5245 = eq(UInt<4>(0hc), remapindex_28) when _T_5245 : connect remapVecData[28], Queue16_UInt8_12.io.deq.bits connect remapVecValids[28], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_5246 = eq(UInt<4>(0hd), remapindex_28) when _T_5246 : connect remapVecData[28], Queue16_UInt8_13.io.deq.bits connect remapVecValids[28], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_5247 = eq(UInt<4>(0he), remapindex_28) when _T_5247 : connect remapVecData[28], Queue16_UInt8_14.io.deq.bits connect remapVecValids[28], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_5248 = eq(UInt<4>(0hf), remapindex_28) when _T_5248 : connect remapVecData[28], Queue16_UInt8_15.io.deq.bits connect remapVecValids[28], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_5249 = eq(UInt<5>(0h10), remapindex_28) when _T_5249 : connect remapVecData[28], Queue16_UInt8_16.io.deq.bits connect remapVecValids[28], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_5250 = eq(UInt<5>(0h11), remapindex_28) when _T_5250 : connect remapVecData[28], Queue16_UInt8_17.io.deq.bits connect remapVecValids[28], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_5251 = eq(UInt<5>(0h12), remapindex_28) when _T_5251 : connect remapVecData[28], Queue16_UInt8_18.io.deq.bits connect remapVecValids[28], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_5252 = eq(UInt<5>(0h13), remapindex_28) when _T_5252 : connect remapVecData[28], Queue16_UInt8_19.io.deq.bits connect remapVecValids[28], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_5253 = eq(UInt<5>(0h14), remapindex_28) when _T_5253 : connect remapVecData[28], Queue16_UInt8_20.io.deq.bits connect remapVecValids[28], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_5254 = eq(UInt<5>(0h15), remapindex_28) when _T_5254 : connect remapVecData[28], Queue16_UInt8_21.io.deq.bits connect remapVecValids[28], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_5255 = eq(UInt<5>(0h16), remapindex_28) when _T_5255 : connect remapVecData[28], Queue16_UInt8_22.io.deq.bits connect remapVecValids[28], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_5256 = eq(UInt<5>(0h17), remapindex_28) when _T_5256 : connect remapVecData[28], Queue16_UInt8_23.io.deq.bits connect remapVecValids[28], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_5257 = eq(UInt<5>(0h18), remapindex_28) when _T_5257 : connect remapVecData[28], Queue16_UInt8_24.io.deq.bits connect remapVecValids[28], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_5258 = eq(UInt<5>(0h19), remapindex_28) when _T_5258 : connect remapVecData[28], Queue16_UInt8_25.io.deq.bits connect remapVecValids[28], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_5259 = eq(UInt<5>(0h1a), remapindex_28) when _T_5259 : connect remapVecData[28], Queue16_UInt8_26.io.deq.bits connect remapVecValids[28], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_5260 = eq(UInt<5>(0h1b), remapindex_28) when _T_5260 : connect remapVecData[28], Queue16_UInt8_27.io.deq.bits connect remapVecValids[28], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_5261 = eq(UInt<5>(0h1c), remapindex_28) when _T_5261 : connect remapVecData[28], Queue16_UInt8_28.io.deq.bits connect remapVecValids[28], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_5262 = eq(UInt<5>(0h1d), remapindex_28) when _T_5262 : connect remapVecData[28], Queue16_UInt8_29.io.deq.bits connect remapVecValids[28], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_5263 = eq(UInt<5>(0h1e), remapindex_28) when _T_5263 : connect remapVecData[28], Queue16_UInt8_30.io.deq.bits connect remapVecValids[28], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_5264 = eq(UInt<5>(0h1f), remapindex_28) when _T_5264 : connect remapVecData[28], Queue16_UInt8_31.io.deq.bits connect remapVecValids[28], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_5265 = eq(UInt<1>(0h0), remapindex_29) when _T_5265 : connect remapVecData[29], Queue16_UInt8.io.deq.bits connect remapVecValids[29], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[29] node _T_5266 = eq(UInt<1>(0h1), remapindex_29) when _T_5266 : connect remapVecData[29], Queue16_UInt8_1.io.deq.bits connect remapVecValids[29], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_5267 = eq(UInt<2>(0h2), remapindex_29) when _T_5267 : connect remapVecData[29], Queue16_UInt8_2.io.deq.bits connect remapVecValids[29], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_5268 = eq(UInt<2>(0h3), remapindex_29) when _T_5268 : connect remapVecData[29], Queue16_UInt8_3.io.deq.bits connect remapVecValids[29], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_5269 = eq(UInt<3>(0h4), remapindex_29) when _T_5269 : connect remapVecData[29], Queue16_UInt8_4.io.deq.bits connect remapVecValids[29], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_5270 = eq(UInt<3>(0h5), remapindex_29) when _T_5270 : connect remapVecData[29], Queue16_UInt8_5.io.deq.bits connect remapVecValids[29], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_5271 = eq(UInt<3>(0h6), remapindex_29) when _T_5271 : connect remapVecData[29], Queue16_UInt8_6.io.deq.bits connect remapVecValids[29], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_5272 = eq(UInt<3>(0h7), remapindex_29) when _T_5272 : connect remapVecData[29], Queue16_UInt8_7.io.deq.bits connect remapVecValids[29], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_5273 = eq(UInt<4>(0h8), remapindex_29) when _T_5273 : connect remapVecData[29], Queue16_UInt8_8.io.deq.bits connect remapVecValids[29], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_5274 = eq(UInt<4>(0h9), remapindex_29) when _T_5274 : connect remapVecData[29], Queue16_UInt8_9.io.deq.bits connect remapVecValids[29], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_5275 = eq(UInt<4>(0ha), remapindex_29) when _T_5275 : connect remapVecData[29], Queue16_UInt8_10.io.deq.bits connect remapVecValids[29], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_5276 = eq(UInt<4>(0hb), remapindex_29) when _T_5276 : connect remapVecData[29], Queue16_UInt8_11.io.deq.bits connect remapVecValids[29], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_5277 = eq(UInt<4>(0hc), remapindex_29) when _T_5277 : connect remapVecData[29], Queue16_UInt8_12.io.deq.bits connect remapVecValids[29], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_5278 = eq(UInt<4>(0hd), remapindex_29) when _T_5278 : connect remapVecData[29], Queue16_UInt8_13.io.deq.bits connect remapVecValids[29], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_5279 = eq(UInt<4>(0he), remapindex_29) when _T_5279 : connect remapVecData[29], Queue16_UInt8_14.io.deq.bits connect remapVecValids[29], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_5280 = eq(UInt<4>(0hf), remapindex_29) when _T_5280 : connect remapVecData[29], Queue16_UInt8_15.io.deq.bits connect remapVecValids[29], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_5281 = eq(UInt<5>(0h10), remapindex_29) when _T_5281 : connect remapVecData[29], Queue16_UInt8_16.io.deq.bits connect remapVecValids[29], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_5282 = eq(UInt<5>(0h11), remapindex_29) when _T_5282 : connect remapVecData[29], Queue16_UInt8_17.io.deq.bits connect remapVecValids[29], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_5283 = eq(UInt<5>(0h12), remapindex_29) when _T_5283 : connect remapVecData[29], Queue16_UInt8_18.io.deq.bits connect remapVecValids[29], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_5284 = eq(UInt<5>(0h13), remapindex_29) when _T_5284 : connect remapVecData[29], Queue16_UInt8_19.io.deq.bits connect remapVecValids[29], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_5285 = eq(UInt<5>(0h14), remapindex_29) when _T_5285 : connect remapVecData[29], Queue16_UInt8_20.io.deq.bits connect remapVecValids[29], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_5286 = eq(UInt<5>(0h15), remapindex_29) when _T_5286 : connect remapVecData[29], Queue16_UInt8_21.io.deq.bits connect remapVecValids[29], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_5287 = eq(UInt<5>(0h16), remapindex_29) when _T_5287 : connect remapVecData[29], Queue16_UInt8_22.io.deq.bits connect remapVecValids[29], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_5288 = eq(UInt<5>(0h17), remapindex_29) when _T_5288 : connect remapVecData[29], Queue16_UInt8_23.io.deq.bits connect remapVecValids[29], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_5289 = eq(UInt<5>(0h18), remapindex_29) when _T_5289 : connect remapVecData[29], Queue16_UInt8_24.io.deq.bits connect remapVecValids[29], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_5290 = eq(UInt<5>(0h19), remapindex_29) when _T_5290 : connect remapVecData[29], Queue16_UInt8_25.io.deq.bits connect remapVecValids[29], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_5291 = eq(UInt<5>(0h1a), remapindex_29) when _T_5291 : connect remapVecData[29], Queue16_UInt8_26.io.deq.bits connect remapVecValids[29], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_5292 = eq(UInt<5>(0h1b), remapindex_29) when _T_5292 : connect remapVecData[29], Queue16_UInt8_27.io.deq.bits connect remapVecValids[29], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_5293 = eq(UInt<5>(0h1c), remapindex_29) when _T_5293 : connect remapVecData[29], Queue16_UInt8_28.io.deq.bits connect remapVecValids[29], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_5294 = eq(UInt<5>(0h1d), remapindex_29) when _T_5294 : connect remapVecData[29], Queue16_UInt8_29.io.deq.bits connect remapVecValids[29], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_5295 = eq(UInt<5>(0h1e), remapindex_29) when _T_5295 : connect remapVecData[29], Queue16_UInt8_30.io.deq.bits connect remapVecValids[29], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_5296 = eq(UInt<5>(0h1f), remapindex_29) when _T_5296 : connect remapVecData[29], Queue16_UInt8_31.io.deq.bits connect remapVecValids[29], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_5297 = eq(UInt<1>(0h0), remapindex_30) when _T_5297 : connect remapVecData[30], Queue16_UInt8.io.deq.bits connect remapVecValids[30], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[30] node _T_5298 = eq(UInt<1>(0h1), remapindex_30) when _T_5298 : connect remapVecData[30], Queue16_UInt8_1.io.deq.bits connect remapVecValids[30], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_5299 = eq(UInt<2>(0h2), remapindex_30) when _T_5299 : connect remapVecData[30], Queue16_UInt8_2.io.deq.bits connect remapVecValids[30], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_5300 = eq(UInt<2>(0h3), remapindex_30) when _T_5300 : connect remapVecData[30], Queue16_UInt8_3.io.deq.bits connect remapVecValids[30], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_5301 = eq(UInt<3>(0h4), remapindex_30) when _T_5301 : connect remapVecData[30], Queue16_UInt8_4.io.deq.bits connect remapVecValids[30], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_5302 = eq(UInt<3>(0h5), remapindex_30) when _T_5302 : connect remapVecData[30], Queue16_UInt8_5.io.deq.bits connect remapVecValids[30], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_5303 = eq(UInt<3>(0h6), remapindex_30) when _T_5303 : connect remapVecData[30], Queue16_UInt8_6.io.deq.bits connect remapVecValids[30], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_5304 = eq(UInt<3>(0h7), remapindex_30) when _T_5304 : connect remapVecData[30], Queue16_UInt8_7.io.deq.bits connect remapVecValids[30], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_5305 = eq(UInt<4>(0h8), remapindex_30) when _T_5305 : connect remapVecData[30], Queue16_UInt8_8.io.deq.bits connect remapVecValids[30], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_5306 = eq(UInt<4>(0h9), remapindex_30) when _T_5306 : connect remapVecData[30], Queue16_UInt8_9.io.deq.bits connect remapVecValids[30], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_5307 = eq(UInt<4>(0ha), remapindex_30) when _T_5307 : connect remapVecData[30], Queue16_UInt8_10.io.deq.bits connect remapVecValids[30], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_5308 = eq(UInt<4>(0hb), remapindex_30) when _T_5308 : connect remapVecData[30], Queue16_UInt8_11.io.deq.bits connect remapVecValids[30], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_5309 = eq(UInt<4>(0hc), remapindex_30) when _T_5309 : connect remapVecData[30], Queue16_UInt8_12.io.deq.bits connect remapVecValids[30], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_5310 = eq(UInt<4>(0hd), remapindex_30) when _T_5310 : connect remapVecData[30], Queue16_UInt8_13.io.deq.bits connect remapVecValids[30], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_5311 = eq(UInt<4>(0he), remapindex_30) when _T_5311 : connect remapVecData[30], Queue16_UInt8_14.io.deq.bits connect remapVecValids[30], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_5312 = eq(UInt<4>(0hf), remapindex_30) when _T_5312 : connect remapVecData[30], Queue16_UInt8_15.io.deq.bits connect remapVecValids[30], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_5313 = eq(UInt<5>(0h10), remapindex_30) when _T_5313 : connect remapVecData[30], Queue16_UInt8_16.io.deq.bits connect remapVecValids[30], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_5314 = eq(UInt<5>(0h11), remapindex_30) when _T_5314 : connect remapVecData[30], Queue16_UInt8_17.io.deq.bits connect remapVecValids[30], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_5315 = eq(UInt<5>(0h12), remapindex_30) when _T_5315 : connect remapVecData[30], Queue16_UInt8_18.io.deq.bits connect remapVecValids[30], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_5316 = eq(UInt<5>(0h13), remapindex_30) when _T_5316 : connect remapVecData[30], Queue16_UInt8_19.io.deq.bits connect remapVecValids[30], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_5317 = eq(UInt<5>(0h14), remapindex_30) when _T_5317 : connect remapVecData[30], Queue16_UInt8_20.io.deq.bits connect remapVecValids[30], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_5318 = eq(UInt<5>(0h15), remapindex_30) when _T_5318 : connect remapVecData[30], Queue16_UInt8_21.io.deq.bits connect remapVecValids[30], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_5319 = eq(UInt<5>(0h16), remapindex_30) when _T_5319 : connect remapVecData[30], Queue16_UInt8_22.io.deq.bits connect remapVecValids[30], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_5320 = eq(UInt<5>(0h17), remapindex_30) when _T_5320 : connect remapVecData[30], Queue16_UInt8_23.io.deq.bits connect remapVecValids[30], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_5321 = eq(UInt<5>(0h18), remapindex_30) when _T_5321 : connect remapVecData[30], Queue16_UInt8_24.io.deq.bits connect remapVecValids[30], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_5322 = eq(UInt<5>(0h19), remapindex_30) when _T_5322 : connect remapVecData[30], Queue16_UInt8_25.io.deq.bits connect remapVecValids[30], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_5323 = eq(UInt<5>(0h1a), remapindex_30) when _T_5323 : connect remapVecData[30], Queue16_UInt8_26.io.deq.bits connect remapVecValids[30], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_5324 = eq(UInt<5>(0h1b), remapindex_30) when _T_5324 : connect remapVecData[30], Queue16_UInt8_27.io.deq.bits connect remapVecValids[30], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_5325 = eq(UInt<5>(0h1c), remapindex_30) when _T_5325 : connect remapVecData[30], Queue16_UInt8_28.io.deq.bits connect remapVecValids[30], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_5326 = eq(UInt<5>(0h1d), remapindex_30) when _T_5326 : connect remapVecData[30], Queue16_UInt8_29.io.deq.bits connect remapVecValids[30], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_5327 = eq(UInt<5>(0h1e), remapindex_30) when _T_5327 : connect remapVecData[30], Queue16_UInt8_30.io.deq.bits connect remapVecValids[30], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_5328 = eq(UInt<5>(0h1f), remapindex_30) when _T_5328 : connect remapVecData[30], Queue16_UInt8_31.io.deq.bits connect remapVecValids[30], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_5329 = eq(UInt<1>(0h0), remapindex_31) when _T_5329 : connect remapVecData[31], Queue16_UInt8.io.deq.bits connect remapVecValids[31], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[31] node _T_5330 = eq(UInt<1>(0h1), remapindex_31) when _T_5330 : connect remapVecData[31], Queue16_UInt8_1.io.deq.bits connect remapVecValids[31], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_5331 = eq(UInt<2>(0h2), remapindex_31) when _T_5331 : connect remapVecData[31], Queue16_UInt8_2.io.deq.bits connect remapVecValids[31], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_5332 = eq(UInt<2>(0h3), remapindex_31) when _T_5332 : connect remapVecData[31], Queue16_UInt8_3.io.deq.bits connect remapVecValids[31], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_5333 = eq(UInt<3>(0h4), remapindex_31) when _T_5333 : connect remapVecData[31], Queue16_UInt8_4.io.deq.bits connect remapVecValids[31], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_5334 = eq(UInt<3>(0h5), remapindex_31) when _T_5334 : connect remapVecData[31], Queue16_UInt8_5.io.deq.bits connect remapVecValids[31], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_5335 = eq(UInt<3>(0h6), remapindex_31) when _T_5335 : connect remapVecData[31], Queue16_UInt8_6.io.deq.bits connect remapVecValids[31], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_5336 = eq(UInt<3>(0h7), remapindex_31) when _T_5336 : connect remapVecData[31], Queue16_UInt8_7.io.deq.bits connect remapVecValids[31], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_5337 = eq(UInt<4>(0h8), remapindex_31) when _T_5337 : connect remapVecData[31], Queue16_UInt8_8.io.deq.bits connect remapVecValids[31], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_5338 = eq(UInt<4>(0h9), remapindex_31) when _T_5338 : connect remapVecData[31], Queue16_UInt8_9.io.deq.bits connect remapVecValids[31], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_5339 = eq(UInt<4>(0ha), remapindex_31) when _T_5339 : connect remapVecData[31], Queue16_UInt8_10.io.deq.bits connect remapVecValids[31], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_5340 = eq(UInt<4>(0hb), remapindex_31) when _T_5340 : connect remapVecData[31], Queue16_UInt8_11.io.deq.bits connect remapVecValids[31], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_5341 = eq(UInt<4>(0hc), remapindex_31) when _T_5341 : connect remapVecData[31], Queue16_UInt8_12.io.deq.bits connect remapVecValids[31], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_5342 = eq(UInt<4>(0hd), remapindex_31) when _T_5342 : connect remapVecData[31], Queue16_UInt8_13.io.deq.bits connect remapVecValids[31], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_5343 = eq(UInt<4>(0he), remapindex_31) when _T_5343 : connect remapVecData[31], Queue16_UInt8_14.io.deq.bits connect remapVecValids[31], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_5344 = eq(UInt<4>(0hf), remapindex_31) when _T_5344 : connect remapVecData[31], Queue16_UInt8_15.io.deq.bits connect remapVecValids[31], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_5345 = eq(UInt<5>(0h10), remapindex_31) when _T_5345 : connect remapVecData[31], Queue16_UInt8_16.io.deq.bits connect remapVecValids[31], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_5346 = eq(UInt<5>(0h11), remapindex_31) when _T_5346 : connect remapVecData[31], Queue16_UInt8_17.io.deq.bits connect remapVecValids[31], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_5347 = eq(UInt<5>(0h12), remapindex_31) when _T_5347 : connect remapVecData[31], Queue16_UInt8_18.io.deq.bits connect remapVecValids[31], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_5348 = eq(UInt<5>(0h13), remapindex_31) when _T_5348 : connect remapVecData[31], Queue16_UInt8_19.io.deq.bits connect remapVecValids[31], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_5349 = eq(UInt<5>(0h14), remapindex_31) when _T_5349 : connect remapVecData[31], Queue16_UInt8_20.io.deq.bits connect remapVecValids[31], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_5350 = eq(UInt<5>(0h15), remapindex_31) when _T_5350 : connect remapVecData[31], Queue16_UInt8_21.io.deq.bits connect remapVecValids[31], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_5351 = eq(UInt<5>(0h16), remapindex_31) when _T_5351 : connect remapVecData[31], Queue16_UInt8_22.io.deq.bits connect remapVecValids[31], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_5352 = eq(UInt<5>(0h17), remapindex_31) when _T_5352 : connect remapVecData[31], Queue16_UInt8_23.io.deq.bits connect remapVecValids[31], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_5353 = eq(UInt<5>(0h18), remapindex_31) when _T_5353 : connect remapVecData[31], Queue16_UInt8_24.io.deq.bits connect remapVecValids[31], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_5354 = eq(UInt<5>(0h19), remapindex_31) when _T_5354 : connect remapVecData[31], Queue16_UInt8_25.io.deq.bits connect remapVecValids[31], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_5355 = eq(UInt<5>(0h1a), remapindex_31) when _T_5355 : connect remapVecData[31], Queue16_UInt8_26.io.deq.bits connect remapVecValids[31], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_5356 = eq(UInt<5>(0h1b), remapindex_31) when _T_5356 : connect remapVecData[31], Queue16_UInt8_27.io.deq.bits connect remapVecValids[31], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_5357 = eq(UInt<5>(0h1c), remapindex_31) when _T_5357 : connect remapVecData[31], Queue16_UInt8_28.io.deq.bits connect remapVecValids[31], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_5358 = eq(UInt<5>(0h1d), remapindex_31) when _T_5358 : connect remapVecData[31], Queue16_UInt8_29.io.deq.bits connect remapVecValids[31], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_5359 = eq(UInt<5>(0h1e), remapindex_31) when _T_5359 : connect remapVecData[31], Queue16_UInt8_30.io.deq.bits connect remapVecValids[31], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_5360 = eq(UInt<5>(0h1f), remapindex_31) when _T_5360 : connect remapVecData[31], Queue16_UInt8_31.io.deq.bits connect remapVecValids[31], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[31] node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) regreset backend_bytes_written : UInt<64>, clock, reset, UInt<64>(0h0) node _backend_next_write_addr_T = add(decompress_dest_info_Q.io.deq.bits.op, backend_bytes_written) node backend_next_write_addr = tail(_backend_next_write_addr_T, 1) node _throttle_end_T = sub(buf_lens_Q.io.deq.bits, backend_bytes_written) node _throttle_end_T_1 = tail(_throttle_end_T, 1) node throttle_end = mux(buf_lens_Q.io.deq.valid, _throttle_end_T_1, UInt<6>(0h20)) node _throttle_end_writeable_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_T_6 = mux(_throttle_end_writeable_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _throttle_end_writeable_T_7 = mux(_throttle_end_writeable_T_4, UInt<2>(0h2), _throttle_end_writeable_T_6) node _throttle_end_writeable_T_8 = mux(_throttle_end_writeable_T_3, UInt<3>(0h4), _throttle_end_writeable_T_7) node _throttle_end_writeable_T_9 = mux(_throttle_end_writeable_T_2, UInt<4>(0h8), _throttle_end_writeable_T_8) node _throttle_end_writeable_T_10 = mux(_throttle_end_writeable_T_1, UInt<5>(0h10), _throttle_end_writeable_T_9) node throttle_end_writeable = mux(_throttle_end_writeable_T, UInt<6>(0h20), _throttle_end_writeable_T_10) node _throttle_end_writeable_log2_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_log2_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_log2_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_log2_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_log2_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_log2_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_log2_T_6 = mux(_throttle_end_writeable_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _throttle_end_writeable_log2_T_7 = mux(_throttle_end_writeable_log2_T_4, UInt<1>(0h1), _throttle_end_writeable_log2_T_6) node _throttle_end_writeable_log2_T_8 = mux(_throttle_end_writeable_log2_T_3, UInt<2>(0h2), _throttle_end_writeable_log2_T_7) node _throttle_end_writeable_log2_T_9 = mux(_throttle_end_writeable_log2_T_2, UInt<2>(0h3), _throttle_end_writeable_log2_T_8) node _throttle_end_writeable_log2_T_10 = mux(_throttle_end_writeable_log2_T_1, UInt<3>(0h4), _throttle_end_writeable_log2_T_9) node throttle_end_writeable_log2 = mux(_throttle_end_writeable_log2_T, UInt<3>(0h5), _throttle_end_writeable_log2_T_10) node _ptr_align_max_bytes_writeable_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_T_5 = mux(_ptr_align_max_bytes_writeable_T_4, UInt<5>(0h10), UInt<6>(0h20)) node _ptr_align_max_bytes_writeable_T_6 = mux(_ptr_align_max_bytes_writeable_T_3, UInt<4>(0h8), _ptr_align_max_bytes_writeable_T_5) node _ptr_align_max_bytes_writeable_T_7 = mux(_ptr_align_max_bytes_writeable_T_2, UInt<3>(0h4), _ptr_align_max_bytes_writeable_T_6) node _ptr_align_max_bytes_writeable_T_8 = mux(_ptr_align_max_bytes_writeable_T_1, UInt<2>(0h2), _ptr_align_max_bytes_writeable_T_7) node ptr_align_max_bytes_writeable = mux(_ptr_align_max_bytes_writeable_T, UInt<1>(0h1), _ptr_align_max_bytes_writeable_T_8) node _ptr_align_max_bytes_writeable_log2_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_log2_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_log2_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_log2_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_log2_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_log2_T_5 = mux(_ptr_align_max_bytes_writeable_log2_T_4, UInt<3>(0h4), UInt<3>(0h5)) node _ptr_align_max_bytes_writeable_log2_T_6 = mux(_ptr_align_max_bytes_writeable_log2_T_3, UInt<2>(0h3), _ptr_align_max_bytes_writeable_log2_T_5) node _ptr_align_max_bytes_writeable_log2_T_7 = mux(_ptr_align_max_bytes_writeable_log2_T_2, UInt<2>(0h2), _ptr_align_max_bytes_writeable_log2_T_6) node _ptr_align_max_bytes_writeable_log2_T_8 = mux(_ptr_align_max_bytes_writeable_log2_T_1, UInt<1>(0h1), _ptr_align_max_bytes_writeable_log2_T_7) node ptr_align_max_bytes_writeable_log2 = mux(_ptr_align_max_bytes_writeable_log2_T, UInt<1>(0h0), _ptr_align_max_bytes_writeable_log2_T_8) node _count_valids_largest_aligned_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_T_6 = mux(_count_valids_largest_aligned_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _count_valids_largest_aligned_T_7 = mux(_count_valids_largest_aligned_T_4, UInt<2>(0h2), _count_valids_largest_aligned_T_6) node _count_valids_largest_aligned_T_8 = mux(_count_valids_largest_aligned_T_3, UInt<3>(0h4), _count_valids_largest_aligned_T_7) node _count_valids_largest_aligned_T_9 = mux(_count_valids_largest_aligned_T_2, UInt<4>(0h8), _count_valids_largest_aligned_T_8) node _count_valids_largest_aligned_T_10 = mux(_count_valids_largest_aligned_T_1, UInt<5>(0h10), _count_valids_largest_aligned_T_9) node count_valids_largest_aligned = mux(_count_valids_largest_aligned_T, UInt<6>(0h20), _count_valids_largest_aligned_T_10) node _count_valids_largest_aligned_log2_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_log2_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_log2_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_log2_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_log2_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_log2_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_log2_T_6 = mux(_count_valids_largest_aligned_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _count_valids_largest_aligned_log2_T_7 = mux(_count_valids_largest_aligned_log2_T_4, UInt<1>(0h1), _count_valids_largest_aligned_log2_T_6) node _count_valids_largest_aligned_log2_T_8 = mux(_count_valids_largest_aligned_log2_T_3, UInt<2>(0h2), _count_valids_largest_aligned_log2_T_7) node _count_valids_largest_aligned_log2_T_9 = mux(_count_valids_largest_aligned_log2_T_2, UInt<2>(0h3), _count_valids_largest_aligned_log2_T_8) node _count_valids_largest_aligned_log2_T_10 = mux(_count_valids_largest_aligned_log2_T_1, UInt<3>(0h4), _count_valids_largest_aligned_log2_T_9) node count_valids_largest_aligned_log2 = mux(_count_valids_largest_aligned_log2_T, UInt<3>(0h5), _count_valids_largest_aligned_log2_T_10) node _bytes_to_write_T = lt(ptr_align_max_bytes_writeable, count_valids_largest_aligned) node _bytes_to_write_T_1 = lt(ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_2 = mux(_bytes_to_write_T_1, ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_3 = lt(count_valids_largest_aligned, throttle_end_writeable) node _bytes_to_write_T_4 = mux(_bytes_to_write_T_3, count_valids_largest_aligned, throttle_end_writeable) node bytes_to_write = mux(_bytes_to_write_T, _bytes_to_write_T_2, _bytes_to_write_T_4) node remapped_write_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node remapped_write_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node remapped_write_data_lo_lo_lo = cat(remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo) node remapped_write_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node remapped_write_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node remapped_write_data_lo_lo_hi = cat(remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo) node remapped_write_data_lo_lo = cat(remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo) node remapped_write_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node remapped_write_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node remapped_write_data_lo_hi_lo = cat(remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo) node remapped_write_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node remapped_write_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node remapped_write_data_lo_hi_hi = cat(remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo) node remapped_write_data_lo_hi = cat(remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo) node remapped_write_data_lo = cat(remapped_write_data_lo_hi, remapped_write_data_lo_lo) node remapped_write_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node remapped_write_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node remapped_write_data_hi_lo_lo = cat(remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo) node remapped_write_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node remapped_write_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node remapped_write_data_hi_lo_hi = cat(remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo) node remapped_write_data_hi_lo = cat(remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo) node remapped_write_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node remapped_write_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node remapped_write_data_hi_hi_lo = cat(remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo) node remapped_write_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node remapped_write_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node remapped_write_data_hi_hi_hi = cat(remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo) node remapped_write_data_hi_hi = cat(remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo) node remapped_write_data_hi = cat(remapped_write_data_hi_hi, remapped_write_data_hi_lo) node remapped_write_data = cat(remapped_write_data_hi, remapped_write_data_lo) node enough_data = neq(bytes_to_write, UInt<1>(0h0)) node _bytes_to_write_log2_T = lt(ptr_align_max_bytes_writeable_log2, count_valids_largest_aligned_log2) node _bytes_to_write_log2_T_1 = lt(ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_2 = mux(_bytes_to_write_log2_T_1, ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_3 = lt(count_valids_largest_aligned_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_4 = mux(_bytes_to_write_log2_T_3, count_valids_largest_aligned_log2, throttle_end_writeable_log2) node bytes_to_write_log2 = mux(_bytes_to_write_log2_T, _bytes_to_write_log2_T_2, _bytes_to_write_log2_T_4) node _write_ptr_override_T = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node write_ptr_override = and(buf_lens_Q.io.deq.valid, _write_ptr_override_T) node _T_5361 = eq(write_ptr_override, UInt<1>(0h0)) node _T_5362 = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node _remapVecReadys_0_T = lt(UInt<1>(0h0), bytes_to_write) node _remapVecReadys_0_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, _T_5361) node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_0_T_4 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_3) connect remapVecReadys[0], _remapVecReadys_0_T_4 node _remapVecReadys_1_T = lt(UInt<1>(0h1), bytes_to_write) node _remapVecReadys_1_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, _T_5361) node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_1_T_4 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_3) connect remapVecReadys[1], _remapVecReadys_1_T_4 node _remapVecReadys_2_T = lt(UInt<2>(0h2), bytes_to_write) node _remapVecReadys_2_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, _T_5361) node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_2_T_4 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_3) connect remapVecReadys[2], _remapVecReadys_2_T_4 node _remapVecReadys_3_T = lt(UInt<2>(0h3), bytes_to_write) node _remapVecReadys_3_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, _T_5361) node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_3_T_4 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_3) connect remapVecReadys[3], _remapVecReadys_3_T_4 node _remapVecReadys_4_T = lt(UInt<3>(0h4), bytes_to_write) node _remapVecReadys_4_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, _T_5361) node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_4_T_4 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_3) connect remapVecReadys[4], _remapVecReadys_4_T_4 node _remapVecReadys_5_T = lt(UInt<3>(0h5), bytes_to_write) node _remapVecReadys_5_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, _T_5361) node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_5_T_4 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_3) connect remapVecReadys[5], _remapVecReadys_5_T_4 node _remapVecReadys_6_T = lt(UInt<3>(0h6), bytes_to_write) node _remapVecReadys_6_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, _T_5361) node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_6_T_4 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_3) connect remapVecReadys[6], _remapVecReadys_6_T_4 node _remapVecReadys_7_T = lt(UInt<3>(0h7), bytes_to_write) node _remapVecReadys_7_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, _T_5361) node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_7_T_4 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_3) connect remapVecReadys[7], _remapVecReadys_7_T_4 node _remapVecReadys_8_T = lt(UInt<4>(0h8), bytes_to_write) node _remapVecReadys_8_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, _T_5361) node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_8_T_4 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_3) connect remapVecReadys[8], _remapVecReadys_8_T_4 node _remapVecReadys_9_T = lt(UInt<4>(0h9), bytes_to_write) node _remapVecReadys_9_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, _T_5361) node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_9_T_4 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_3) connect remapVecReadys[9], _remapVecReadys_9_T_4 node _remapVecReadys_10_T = lt(UInt<4>(0ha), bytes_to_write) node _remapVecReadys_10_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, _T_5361) node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_10_T_4 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_3) connect remapVecReadys[10], _remapVecReadys_10_T_4 node _remapVecReadys_11_T = lt(UInt<4>(0hb), bytes_to_write) node _remapVecReadys_11_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, _T_5361) node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_11_T_4 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_3) connect remapVecReadys[11], _remapVecReadys_11_T_4 node _remapVecReadys_12_T = lt(UInt<4>(0hc), bytes_to_write) node _remapVecReadys_12_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, _T_5361) node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_12_T_4 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_3) connect remapVecReadys[12], _remapVecReadys_12_T_4 node _remapVecReadys_13_T = lt(UInt<4>(0hd), bytes_to_write) node _remapVecReadys_13_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, _T_5361) node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_13_T_4 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_3) connect remapVecReadys[13], _remapVecReadys_13_T_4 node _remapVecReadys_14_T = lt(UInt<4>(0he), bytes_to_write) node _remapVecReadys_14_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, _T_5361) node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_14_T_4 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_3) connect remapVecReadys[14], _remapVecReadys_14_T_4 node _remapVecReadys_15_T = lt(UInt<4>(0hf), bytes_to_write) node _remapVecReadys_15_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, _T_5361) node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_15_T_4 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_3) connect remapVecReadys[15], _remapVecReadys_15_T_4 node _remapVecReadys_16_T = lt(UInt<5>(0h10), bytes_to_write) node _remapVecReadys_16_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, _T_5361) node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_16_T_4 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_3) connect remapVecReadys[16], _remapVecReadys_16_T_4 node _remapVecReadys_17_T = lt(UInt<5>(0h11), bytes_to_write) node _remapVecReadys_17_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, _T_5361) node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_17_T_4 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_3) connect remapVecReadys[17], _remapVecReadys_17_T_4 node _remapVecReadys_18_T = lt(UInt<5>(0h12), bytes_to_write) node _remapVecReadys_18_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, _T_5361) node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_18_T_4 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_3) connect remapVecReadys[18], _remapVecReadys_18_T_4 node _remapVecReadys_19_T = lt(UInt<5>(0h13), bytes_to_write) node _remapVecReadys_19_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, _T_5361) node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_19_T_4 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_3) connect remapVecReadys[19], _remapVecReadys_19_T_4 node _remapVecReadys_20_T = lt(UInt<5>(0h14), bytes_to_write) node _remapVecReadys_20_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, _T_5361) node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_20_T_4 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_3) connect remapVecReadys[20], _remapVecReadys_20_T_4 node _remapVecReadys_21_T = lt(UInt<5>(0h15), bytes_to_write) node _remapVecReadys_21_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, _T_5361) node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_21_T_4 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_3) connect remapVecReadys[21], _remapVecReadys_21_T_4 node _remapVecReadys_22_T = lt(UInt<5>(0h16), bytes_to_write) node _remapVecReadys_22_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, _T_5361) node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_22_T_4 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_3) connect remapVecReadys[22], _remapVecReadys_22_T_4 node _remapVecReadys_23_T = lt(UInt<5>(0h17), bytes_to_write) node _remapVecReadys_23_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, _T_5361) node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_23_T_4 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_3) connect remapVecReadys[23], _remapVecReadys_23_T_4 node _remapVecReadys_24_T = lt(UInt<5>(0h18), bytes_to_write) node _remapVecReadys_24_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, _T_5361) node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_24_T_4 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_3) connect remapVecReadys[24], _remapVecReadys_24_T_4 node _remapVecReadys_25_T = lt(UInt<5>(0h19), bytes_to_write) node _remapVecReadys_25_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, _T_5361) node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_25_T_4 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_3) connect remapVecReadys[25], _remapVecReadys_25_T_4 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), bytes_to_write) node _remapVecReadys_26_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, _T_5361) node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_26_T_4 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_3) connect remapVecReadys[26], _remapVecReadys_26_T_4 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), bytes_to_write) node _remapVecReadys_27_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, _T_5361) node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_27_T_4 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_3) connect remapVecReadys[27], _remapVecReadys_27_T_4 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), bytes_to_write) node _remapVecReadys_28_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, _T_5361) node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_28_T_4 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_3) connect remapVecReadys[28], _remapVecReadys_28_T_4 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), bytes_to_write) node _remapVecReadys_29_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, _T_5361) node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_29_T_4 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_3) connect remapVecReadys[29], _remapVecReadys_29_T_4 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), bytes_to_write) node _remapVecReadys_30_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, _T_5361) node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_30_T_4 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_3) connect remapVecReadys[30], _remapVecReadys_30_T_4 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), bytes_to_write) node _remapVecReadys_31_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, _T_5361) node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_31_T_4 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_3) connect remapVecReadys[31], _remapVecReadys_31_T_4 node _T_5363 = and(io.l2io.req.ready, enough_data) node _T_5364 = and(_T_5363, _T_5361) node _T_5365 = and(_T_5364, decompress_dest_info_Q.io.deq.valid) when _T_5365 : node _read_start_index_T = add(read_start_index, bytes_to_write) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1 node _backend_bytes_written_T = add(backend_bytes_written, bytes_to_write) node _backend_bytes_written_T_1 = tail(_backend_bytes_written_T, 1) connect backend_bytes_written, _backend_bytes_written_T_1 regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_5366 = asUInt(reset) node _T_5367 = eq(_T_5366, UInt<1>(0h0)) when _T_5367 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70 node _T_5368 = asUInt(reset) node _T_5369 = eq(_T_5368, UInt<1>(0h0)) when _T_5369 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] writefire: addr: 0x%x, data 0x%x, size %d\n", io.l2io.req.bits.addr, io.l2io.req.bits.data, io.l2io.req.bits.size) : printf_71 node _io_l2io_req_valid_T = and(enough_data, _T_5361) node _io_l2io_req_valid_T_1 = and(_io_l2io_req_valid_T, decompress_dest_info_Q.io.deq.valid) connect io.l2io.req.valid, _io_l2io_req_valid_T_1 node _io_l2io_req_bits_size_T = mux(write_ptr_override, UInt<2>(0h2), bytes_to_write_log2) connect io.l2io.req.bits.size, _io_l2io_req_bits_size_T node _io_l2io_req_bits_addr_T = mux(write_ptr_override, decompress_dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr) connect io.l2io.req.bits.addr, _io_l2io_req_bits_addr_T node _io_l2io_req_bits_data_T = mux(write_ptr_override, buf_lens_Q.io.deq.bits, remapped_write_data) connect io.l2io.req.bits.data, _io_l2io_req_bits_data_T connect io.l2io.req.bits.cmd, UInt<1>(0h1) node _buf_lens_Q_io_deq_ready_T = and(io.l2io.req.ready, _T_5362) node _buf_lens_Q_io_deq_ready_T_1 = and(_buf_lens_Q_io_deq_ready_T, decompress_dest_info_Q.io.deq.valid) connect buf_lens_Q.io.deq.ready, _buf_lens_Q_io_deq_ready_T_1 node _decompress_dest_info_Q_io_deq_ready_T = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _decompress_dest_info_Q_io_deq_ready_T_1 = and(_decompress_dest_info_Q_io_deq_ready_T, _T_5362) connect decompress_dest_info_Q.io.deq.ready, _decompress_dest_info_Q_io_deq_ready_T_1 regreset bufs_completed : UInt<64>, clock, reset, UInt<64>(0h0) connect io.bufs_completed, bufs_completed connect io.l2io.resp.ready, UInt<1>(0h1) connect io.no_writes_inflight, io.l2io.no_memops_inflight node _T_5370 = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _T_5371 = and(_T_5370, _T_5362) node _T_5372 = and(_T_5371, decompress_dest_info_Q.io.deq.valid) when _T_5372 : node _bufs_completed_T = add(bufs_completed, UInt<1>(0h1)) node _bufs_completed_T_1 = tail(_bufs_completed_T, 1) connect bufs_completed, _bufs_completed_T_1 connect backend_bytes_written, UInt<1>(0h0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_5373 = asUInt(reset) node _T_5374 = eq(_T_5373, UInt<1>(0h0)) when _T_5374 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72 node _T_5375 = asUInt(reset) node _T_5376 = eq(_T_5375, UInt<1>(0h0)) when _T_5376 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] write cmpflag addr: 0x%x, final_bytes_written: %d\n", decompress_dest_info_Q.io.deq.bits.cmpflag, buf_lens_Q.io.deq.bits) : printf_73 node _T_5377 = neq(count_valids, UInt<1>(0h0)) when _T_5377 : node _T_5378 = eq(write_ptr_override, UInt<1>(0h0)) regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_5379 = asUInt(reset) node _T_5380 = eq(_T_5379, UInt<1>(0h0)) when _T_5380 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74 node _T_5381 = asUInt(reset) node _T_5382 = eq(_T_5381, UInt<1>(0h0)) when _T_5382 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d, l2io.req.ready: %d, enough_data: %d, write_ptr_override: %d, decompress_dest_info_Q.io.deq.valid: %d\n", read_start_index, backend_bytes_written, count_valids, ptr_align_max_bytes_writeable, bytes_to_write, bytes_to_write_log2, io.l2io.req.ready, enough_data, _T_5378, decompress_dest_info_Q.io.deq.valid) : printf_75	module EntropyCompressorMemwriter_2( // @[EntropyCompressorMemWriter.scala:21:7] input clock, // @[EntropyCompressorMemWriter.scala:21:7] input reset, // @[EntropyCompressorMemWriter.scala:21:7] output io_memwrites_in_ready, // @[EntropyCompressorMemWriter.scala:24:14] input io_memwrites_in_valid, // @[EntropyCompressorMemWriter.scala:24:14] input [255:0] io_memwrites_in_bits_data, // @[EntropyCompressorMemWriter.scala:24:14] input [5:0] io_memwrites_in_bits_validbytes, // @[EntropyCompressorMemWriter.scala:24:14] input io_memwrites_in_bits_end_of_message, // @[EntropyCompressorMemWriter.scala:24:14] input io_l2io_req_ready, // @[EntropyCompressorMemWriter.scala:24:14] output io_l2io_req_valid, // @[EntropyCompressorMemWriter.scala:24:14] output [63:0] io_l2io_req_bits_addr, // @[EntropyCompressorMemWriter.scala:24:14] output [2:0] io_l2io_req_bits_size, // @[EntropyCompressorMemWriter.scala:24:14] output [255:0] io_l2io_req_bits_data, // @[EntropyCompressorMemWriter.scala:24:14] input io_l2io_resp_valid, // @[EntropyCompressorMemWriter.scala:24:14] input [255:0] io_l2io_resp_bits_data, // @[EntropyCompressorMemWriter.scala:24:14] input io_l2io_no_memops_inflight, // @[EntropyCompressorMemWriter.scala:24:14] output io_decompress_dest_info_ready, // @[EntropyCompressorMemWriter.scala:24:14] input io_decompress_dest_info_valid, // @[EntropyCompressorMemWriter.scala:24:14] input [63:0] io_decompress_dest_info_bits_op, // @[EntropyCompressorMemWriter.scala:24:14] input [63:0] io_decompress_dest_info_bits_cmpflag // @[EntropyCompressorMemWriter.scala:24:14] ); wire _Queue16_UInt8_31_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_31_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_31_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_30_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_30_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_30_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_29_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_29_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_29_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_28_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_28_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_28_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_27_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_27_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_27_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_26_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_26_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_26_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_25_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_25_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_25_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_24_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_24_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_24_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_23_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_23_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_23_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_22_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_22_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_22_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_21_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_21_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_21_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_20_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_20_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_20_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_19_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_19_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_19_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_18_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_18_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_18_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_17_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_17_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_17_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_16_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_16_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_16_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_15_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_15_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_15_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_14_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_14_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_14_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_13_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_13_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_13_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_12_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_12_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_12_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_11_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_11_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_11_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_10_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_10_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_10_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_9_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_9_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_9_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_8_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_8_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_7_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_7_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_7_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_6_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_6_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_6_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_5_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_5_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_5_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_4_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_4_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_4_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_3_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_3_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_3_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_2_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_2_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_2_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_1_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_1_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_1_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _buf_lens_Q_io_enq_ready; // @[EntropyCompressorMemWriter.scala:50:26] wire _buf_lens_Q_io_deq_valid; // @[EntropyCompressorMemWriter.scala:50:26] wire [63:0] _buf_lens_Q_io_deq_bits; // @[EntropyCompressorMemWriter.scala:50:26] wire _decompress_dest_info_Q_io_deq_valid; // @[EntropyCompressorMemWriter.scala:37:38] wire [63:0] _decompress_dest_info_Q_io_deq_bits_op; // @[EntropyCompressorMemWriter.scala:37:38] wire [63:0] _decompress_dest_info_Q_io_deq_bits_cmpflag; // @[EntropyCompressorMemWriter.scala:37:38] wire _incoming_writes_Q_io_deq_valid; // @[EntropyCompressorMemWriter.scala:33:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[EntropyCompressorMemWriter.scala:33:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[EntropyCompressorMemWriter.scala:33:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[EntropyCompressorMemWriter.scala:33:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[EntropyCompressorMemWriter.scala:21:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[EntropyCompressorMemWriter.scala:21:7] wire [5:0] io_memwrites_in_bits_validbytes_0 = io_memwrites_in_bits_validbytes; // @[EntropyCompressorMemWriter.scala:21:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[EntropyCompressorMemWriter.scala:21:7] wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[EntropyCompressorMemWriter.scala:21:7] wire io_decompress_dest_info_valid_0 = io_decompress_dest_info_valid; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_decompress_dest_info_bits_op_0 = io_decompress_dest_info_bits_op; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_decompress_dest_info_bits_cmpflag_0 = io_decompress_dest_info_bits_cmpflag; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_req_bits_cmd = 1'h1; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_resp_ready = 1'h1; // @[EntropyCompressorMemWriter.scala:21:7] wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[EntropyCompressorMemWriter.scala:182:50] wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[EntropyCompressorMemWriter.scala:213:56] wire _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] wire [63:0] _io_l2io_req_bits_addr_T; // @[EntropyCompressorMemWriter.scala:280:31] wire [2:0] _io_l2io_req_bits_size_T; // @[EntropyCompressorMemWriter.scala:279:31] wire [255:0] _io_l2io_req_bits_data_T; // @[EntropyCompressorMemWriter.scala:281:31] wire io_no_writes_inflight = io_l2io_no_memops_inflight_0; // @[EntropyCompressorMemWriter.scala:21:7] wire io_memwrites_in_ready_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_l2io_req_bits_addr_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [2:0] io_l2io_req_bits_size_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [255:0] io_l2io_req_bits_data_0; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_req_valid_0; // @[EntropyCompressorMemWriter.scala:21:7] wire io_decompress_dest_info_ready_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_bufs_completed; // @[EntropyCompressorMemWriter.scala:21:7] wire _decompress_dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53] wire _decompress_dest_last_fire_T = _decompress_dest_info_Q_io_deq_ready_T_1 & _decompress_dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35] reg decompress_dest_last_fire; // @[EntropyCompressorMemWriter.scala:40:42] reg decompress_dest_last_valid; // @[EntropyCompressorMemWriter.scala:41:43] wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[EntropyCompressorMemWriter.scala:41:43, :42:105] wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire \| _decompress_dest_printhelp_T; // @[EntropyCompressorMemWriter.scala:40:42, :42:{101,105}] wire decompress_dest_printhelp = _decompress_dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[EntropyCompressorMemWriter.scala:37:38, :42:{71,101}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] buf_len_tracker; // @[EntropyCompressorMemWriter.scala:55:32] wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53] wire _T_10 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35] wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[EntropyCompressorMemWriter.scala:33:33, :55:32, :60:42] wire [64:0] _buf_len_tracker_T; // @[EntropyCompressorMemWriter.scala:60:42] assign _buf_len_tracker_T = _GEN; // @[EntropyCompressorMemWriter.scala:60:42] wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[EntropyCompressorMemWriter.scala:110:45] assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[EntropyCompressorMemWriter.scala:60:42, :110:45] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[EntropyCompressorMemWriter.scala:74:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[EntropyCompressorMemWriter.scala:74:34, :84:34] wire [6:0] _GEN_0 = _idx_T % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx = _GEN_0[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_1 = _idx_T_1 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_1 = _GEN_1[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_2 = _idx_T_2 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_2 = _GEN_2[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_3 = _idx_T_3 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_3 = _GEN_3[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_4 = _idx_T_4 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_4 = _GEN_4[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_5 = _idx_T_5 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_5 = _GEN_5[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_6 = _idx_T_6 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_6 = _GEN_6[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_7 = _idx_T_7 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_7 = _GEN_7[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_8 = _idx_T_8 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_8 = _GEN_8[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_9 = _idx_T_9 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_9 = _GEN_9[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_10 = _idx_T_10 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_10 = _GEN_10[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_11 = _idx_T_11 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_11 = _GEN_11[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_12 = _idx_T_12 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_12 = _GEN_12[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_13 = _idx_T_13 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_13 = _GEN_13[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_14 = _idx_T_14 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_14 = _GEN_14[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_15 = _idx_T_15 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_15 = _GEN_15[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_16 = _idx_T_16 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_16 = _GEN_16[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_17 = _idx_T_17 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_17 = _GEN_17[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_18 = _idx_T_18 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_18 = _GEN_18[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_19 = _idx_T_19 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_19 = _GEN_19[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_20 = _idx_T_20 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_20 = _GEN_20[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_21 = _idx_T_21 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_21 = _GEN_21[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_22 = _idx_T_22 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_22 = _GEN_22[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_23 = _idx_T_23 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_23 = _GEN_23[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_24 = _idx_T_24 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_24 = _GEN_24[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_25 = _idx_T_25 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_25 = _GEN_25[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_26 = _idx_T_26 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_26 = _GEN_26[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_27 = _idx_T_27 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_27 = _GEN_27[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_28 = _idx_T_28 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_28 = _GEN_28[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_29 = _idx_T_29 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_29 = _GEN_29[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_30 = _idx_T_30 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_30 = _GEN_30[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_31 = _idx_T_31 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_31 = _GEN_31[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[EntropyCompressorMemWriter.scala:33:33, :84:34, :93:47] wire [6:0] _GEN_32 = wrap_len_index_wide % 7'h20; // @[EntropyCompressorMemWriter.scala:93:47, :94:48] wire [5:0] wrap_len_index_end = _GEN_32[5:0]; // @[EntropyCompressorMemWriter.scala:94:48] wire wrapped = \|(wrap_len_index_wide[6:5]); // @[EntropyCompressorMemWriter.scala:93:47, :95:37] wire _all_queues_ready_T = _Queue16_UInt8_io_enq_ready & _Queue16_UInt8_1_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue16_UInt8_2_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue16_UInt8_3_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue16_UInt8_4_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue16_UInt8_5_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue16_UInt8_6_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue16_UInt8_7_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue16_UInt8_8_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue16_UInt8_9_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue16_UInt8_10_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue16_UInt8_11_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue16_UInt8_12_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue16_UInt8_13_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue16_UInt8_14_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue16_UInt8_15_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue16_UInt8_16_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue16_UInt8_17_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue16_UInt8_18_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue16_UInt8_19_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue16_UInt8_20_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue16_UInt8_21_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue16_UInt8_22_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue16_UInt8_23_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue16_UInt8_24_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue16_UInt8_25_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue16_UInt8_26_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue16_UInt8_27_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue16_UInt8_28_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue16_UInt8_29_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue16_UInt8_30_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue16_UInt8_31_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[EntropyCompressorMemWriter.scala:33:33, :101:33] wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[EntropyCompressorMemWriter.scala:33:33, :50:26, :101:61] wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T \| _account_for_buf_lens_Q_T_1; // @[EntropyCompressorMemWriter.scala:101:{33,46,61}] wire _buf_lens_Q_io_enq_valid_T = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53] assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53] wire _GEN_33 = write_start_index == 6'h0; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T = _GEN_33; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_3; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_3 = _GEN_33; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_1 = \|wrap_len_index_end; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_2 = _use_this_queue_T \| _use_this_queue_T_1; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_4 = \|wrap_len_index_end; // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_34 = write_start_index < 6'h2; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_6; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_6 = _GEN_34; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_9; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_9 = _GEN_34; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_7 = \|(wrap_len_index_end[5:1]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 \| _use_this_queue_T_7; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_10 = \|(wrap_len_index_end[5:1]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_35 = write_start_index < 6'h3; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_12; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_12 = _GEN_35; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_15; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_15 = _GEN_35; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_36 = wrap_len_index_end > 6'h2; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_13; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_13 = _GEN_36; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_16; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_16 = _GEN_36; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 \| _use_this_queue_T_13; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_37 = write_start_index < 6'h4; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_18; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_18 = _GEN_37; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_21; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_21 = _GEN_37; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_19 = \|(wrap_len_index_end[5:2]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 \| _use_this_queue_T_19; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_22 = \|(wrap_len_index_end[5:2]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_38 = write_start_index < 6'h5; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_24; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_24 = _GEN_38; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_27; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_27 = _GEN_38; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_39 = wrap_len_index_end > 6'h4; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_25; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_25 = _GEN_39; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_28; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_28 = _GEN_39; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 \| _use_this_queue_T_25; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_40 = write_start_index < 6'h6; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_30; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_30 = _GEN_40; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_33; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_33 = _GEN_40; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_41 = wrap_len_index_end > 6'h5; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_31; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_31 = _GEN_41; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_34; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_34 = _GEN_41; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 \| _use_this_queue_T_31; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_42 = write_start_index < 6'h7; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_36; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_36 = _GEN_42; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_39; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_39 = _GEN_42; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_43 = wrap_len_index_end > 6'h6; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_37; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_37 = _GEN_43; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_40; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_40 = _GEN_43; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 \| _use_this_queue_T_37; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_44 = write_start_index < 6'h8; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_42; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_42 = _GEN_44; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_45; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_45 = _GEN_44; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_43 = \|(wrap_len_index_end[5:3]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 \| _use_this_queue_T_43; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_46 = \|(wrap_len_index_end[5:3]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_45 = write_start_index < 6'h9; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_48; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_48 = _GEN_45; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_51; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_51 = _GEN_45; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_46 = wrap_len_index_end > 6'h8; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_49; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_49 = _GEN_46; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_52; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_52 = _GEN_46; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 \| _use_this_queue_T_49; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_47 = write_start_index < 6'hA; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_54; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_54 = _GEN_47; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_57; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_57 = _GEN_47; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_48 = wrap_len_index_end > 6'h9; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_55; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_55 = _GEN_48; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_58; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_58 = _GEN_48; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 \| _use_this_queue_T_55; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_49 = write_start_index < 6'hB; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_60; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_60 = _GEN_49; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_63; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_63 = _GEN_49; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_50 = wrap_len_index_end > 6'hA; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_61; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_61 = _GEN_50; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_64; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_64 = _GEN_50; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 \| _use_this_queue_T_61; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_51 = write_start_index < 6'hC; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_66; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_66 = _GEN_51; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_69; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_69 = _GEN_51; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_52 = wrap_len_index_end > 6'hB; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_67; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_67 = _GEN_52; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_70; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_70 = _GEN_52; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 \| _use_this_queue_T_67; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_53 = write_start_index < 6'hD; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_72; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_72 = _GEN_53; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_75; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_75 = _GEN_53; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_54 = wrap_len_index_end > 6'hC; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_73; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_73 = _GEN_54; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_76; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_76 = _GEN_54; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 \| _use_this_queue_T_73; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_55 = write_start_index < 6'hE; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_78; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_78 = _GEN_55; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_81; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_81 = _GEN_55; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_56 = wrap_len_index_end > 6'hD; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_79; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_79 = _GEN_56; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_82; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_82 = _GEN_56; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 \| _use_this_queue_T_79; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_57 = write_start_index < 6'hF; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_84; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_84 = _GEN_57; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_87; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_87 = _GEN_57; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_58 = wrap_len_index_end > 6'hE; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_85; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_85 = _GEN_58; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_88; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_88 = _GEN_58; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 \| _use_this_queue_T_85; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_59 = write_start_index < 6'h10; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_90; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_90 = _GEN_59; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_93; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_93 = _GEN_59; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_91 = \|(wrap_len_index_end[5:4]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 \| _use_this_queue_T_91; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_94 = \|(wrap_len_index_end[5:4]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_60 = write_start_index < 6'h11; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_96; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_96 = _GEN_60; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_99; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_99 = _GEN_60; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_61 = wrap_len_index_end > 6'h10; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_97; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_97 = _GEN_61; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_100; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_100 = _GEN_61; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 \| _use_this_queue_T_97; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_62 = write_start_index < 6'h12; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_102; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_102 = _GEN_62; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_105; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_105 = _GEN_62; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_63 = wrap_len_index_end > 6'h11; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_103; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_103 = _GEN_63; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_106; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_106 = _GEN_63; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 \| _use_this_queue_T_103; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_64 = write_start_index < 6'h13; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_108; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_108 = _GEN_64; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_111; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_111 = _GEN_64; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_65 = wrap_len_index_end > 6'h12; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_109; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_109 = _GEN_65; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_112; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_112 = _GEN_65; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 \| _use_this_queue_T_109; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_66 = write_start_index < 6'h14; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_114; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_114 = _GEN_66; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_117; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_117 = _GEN_66; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_67 = wrap_len_index_end > 6'h13; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_115; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_115 = _GEN_67; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_118; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_118 = _GEN_67; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 \| _use_this_queue_T_115; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_68 = write_start_index < 6'h15; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_120; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_120 = _GEN_68; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_123; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_123 = _GEN_68; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_69 = wrap_len_index_end > 6'h14; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_121; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_121 = _GEN_69; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_124; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_124 = _GEN_69; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 \| _use_this_queue_T_121; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_70 = write_start_index < 6'h16; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_126; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_126 = _GEN_70; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_129; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_129 = _GEN_70; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_71 = wrap_len_index_end > 6'h15; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_127; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_127 = _GEN_71; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_130; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_130 = _GEN_71; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 \| _use_this_queue_T_127; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_72 = write_start_index < 6'h17; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_132; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_132 = _GEN_72; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_135; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_135 = _GEN_72; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_73 = wrap_len_index_end > 6'h16; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_133; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_133 = _GEN_73; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_136; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_136 = _GEN_73; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 \| _use_this_queue_T_133; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_74 = write_start_index < 6'h18; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_138; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_138 = _GEN_74; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_141; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_141 = _GEN_74; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_75 = wrap_len_index_end > 6'h17; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_139; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_139 = _GEN_75; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_142; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_142 = _GEN_75; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 \| _use_this_queue_T_139; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_76 = write_start_index < 6'h19; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_144; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_144 = _GEN_76; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_147; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_147 = _GEN_76; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_77 = wrap_len_index_end > 6'h18; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_145; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_145 = _GEN_77; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_148; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_148 = _GEN_77; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 \| _use_this_queue_T_145; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_78 = write_start_index < 6'h1A; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_150; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_150 = _GEN_78; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_153; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_153 = _GEN_78; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_79 = wrap_len_index_end > 6'h19; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_151; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_151 = _GEN_79; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_154; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_154 = _GEN_79; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 \| _use_this_queue_T_151; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_80 = write_start_index < 6'h1B; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_156; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_156 = _GEN_80; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_159; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_159 = _GEN_80; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_81 = wrap_len_index_end > 6'h1A; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_157; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_157 = _GEN_81; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_160; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_160 = _GEN_81; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 \| _use_this_queue_T_157; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_82 = write_start_index < 6'h1C; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_162; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_162 = _GEN_82; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_165; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_165 = _GEN_82; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_83 = wrap_len_index_end > 6'h1B; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_163; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_163 = _GEN_83; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_166; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_166 = _GEN_83; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 \| _use_this_queue_T_163; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_84 = write_start_index < 6'h1D; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_168; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_168 = _GEN_84; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_171; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_171 = _GEN_84; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_85 = wrap_len_index_end > 6'h1C; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_169; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_169 = _GEN_85; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_172; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_172 = _GEN_85; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 \| _use_this_queue_T_169; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_86 = write_start_index < 6'h1E; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_174; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_174 = _GEN_86; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_177; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_177 = _GEN_86; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_87 = wrap_len_index_end > 6'h1D; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_175; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_175 = _GEN_87; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_178; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_178 = _GEN_87; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 \| _use_this_queue_T_175; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_88 = write_start_index < 6'h1F; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_180; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_180 = _GEN_88; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_183; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_183 = _GEN_88; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_89 = wrap_len_index_end > 6'h1E; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_181; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_181 = _GEN_89; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_184; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_184 = _GEN_89; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 \| _use_this_queue_T_181; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 \| _use_this_queue_T_187; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[EntropyCompressorMemWriter.scala:74:34, :121:41, :122:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[EntropyCompressorMemWriter.scala:134:33] wire [7:0] remapVecData_0; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_1; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_2; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_3; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_4; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_5; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_6; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_7; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_8; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_9; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_10; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_11; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_12; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_13; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_14; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_15; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_16; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_17; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_18; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_19; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_20; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_21; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_22; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_23; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_24; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_25; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_26; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_27; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_28; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_29; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_30; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_31; // @[EntropyCompressorMemWriter.scala:136:26] wire remapVecValids_0; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_1; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_2; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_3; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_4; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_5; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_6; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_7; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_8; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_9; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_10; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_11; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_12; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_13; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_14; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_15; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_16; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_17; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_18; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_19; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_20; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_21; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_22; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_23; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_24; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_25; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_26; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_27; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_28; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_29; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_30; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_31; // @[EntropyCompressorMemWriter.scala:137:28] wire _remapVecReadys_0_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_1_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_2_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_3_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_4_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_5_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_6_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_7_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_8_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_9_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_10_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_11_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_12_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_13_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_14_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_15_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_16_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_17_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_18_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_19_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_20_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_21_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_22_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_23_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_24_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_25_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_26_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_27_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_28_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_29_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_30_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_31_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire remapVecReadys_0; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_1; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_2; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_3; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_4; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_5; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_6; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_7; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_8; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_9; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_10; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_11; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_12; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_13; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_14; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_15; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_16; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_17; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_18; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_19; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_20; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_21; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_22; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_23; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_24; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_25; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_26; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_27; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_28; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_29; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_30; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_31; // @[EntropyCompressorMemWriter.scala:138:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[EntropyCompressorMemWriter.scala:134:33, :148:33] wire [6:0] _GEN_90 = _remapindex_T % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex = _GEN_90[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4337 = remapindex == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4338 = remapindex == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4339 = remapindex == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4340 = remapindex == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4341 = remapindex == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4342 = remapindex == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4343 = remapindex == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4344 = remapindex == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4345 = remapindex == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4346 = remapindex == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4347 = remapindex == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4348 = remapindex == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4349 = remapindex == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4350 = remapindex == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4351 = remapindex == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4352 = remapindex == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4353 = remapindex == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4354 = remapindex == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4355 = remapindex == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4356 = remapindex == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4357 = remapindex == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4358 = remapindex == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4359 = remapindex == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4360 = remapindex == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4361 = remapindex == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4362 = remapindex == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4363 = remapindex == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4364 = remapindex == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4365 = remapindex == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4366 = remapindex == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4367 = remapindex == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4368 = remapindex == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_bits : _T_4367 ? _Queue16_UInt8_30_io_deq_bits : _T_4366 ? _Queue16_UInt8_29_io_deq_bits : _T_4365 ? _Queue16_UInt8_28_io_deq_bits : _T_4364 ? _Queue16_UInt8_27_io_deq_bits : _T_4363 ? _Queue16_UInt8_26_io_deq_bits : _T_4362 ? _Queue16_UInt8_25_io_deq_bits : _T_4361 ? _Queue16_UInt8_24_io_deq_bits : _T_4360 ? _Queue16_UInt8_23_io_deq_bits : _T_4359 ? _Queue16_UInt8_22_io_deq_bits : _T_4358 ? _Queue16_UInt8_21_io_deq_bits : _T_4357 ? _Queue16_UInt8_20_io_deq_bits : _T_4356 ? _Queue16_UInt8_19_io_deq_bits : _T_4355 ? _Queue16_UInt8_18_io_deq_bits : _T_4354 ? _Queue16_UInt8_17_io_deq_bits : _T_4353 ? _Queue16_UInt8_16_io_deq_bits : _T_4352 ? _Queue16_UInt8_15_io_deq_bits : _T_4351 ? _Queue16_UInt8_14_io_deq_bits : _T_4350 ? _Queue16_UInt8_13_io_deq_bits : _T_4349 ? _Queue16_UInt8_12_io_deq_bits : _T_4348 ? _Queue16_UInt8_11_io_deq_bits : _T_4347 ? _Queue16_UInt8_10_io_deq_bits : _T_4346 ? _Queue16_UInt8_9_io_deq_bits : _T_4345 ? _Queue16_UInt8_8_io_deq_bits : _T_4344 ? _Queue16_UInt8_7_io_deq_bits : _T_4343 ? _Queue16_UInt8_6_io_deq_bits : _T_4342 ? _Queue16_UInt8_5_io_deq_bits : _T_4341 ? _Queue16_UInt8_4_io_deq_bits : _T_4340 ? _Queue16_UInt8_3_io_deq_bits : _T_4339 ? _Queue16_UInt8_2_io_deq_bits : _T_4338 ? _Queue16_UInt8_1_io_deq_bits : _T_4337 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_valid : _T_4367 ? _Queue16_UInt8_30_io_deq_valid : _T_4366 ? _Queue16_UInt8_29_io_deq_valid : _T_4365 ? _Queue16_UInt8_28_io_deq_valid : _T_4364 ? _Queue16_UInt8_27_io_deq_valid : _T_4363 ? _Queue16_UInt8_26_io_deq_valid : _T_4362 ? _Queue16_UInt8_25_io_deq_valid : _T_4361 ? _Queue16_UInt8_24_io_deq_valid : _T_4360 ? _Queue16_UInt8_23_io_deq_valid : _T_4359 ? _Queue16_UInt8_22_io_deq_valid : _T_4358 ? _Queue16_UInt8_21_io_deq_valid : _T_4357 ? _Queue16_UInt8_20_io_deq_valid : _T_4356 ? _Queue16_UInt8_19_io_deq_valid : _T_4355 ? _Queue16_UInt8_18_io_deq_valid : _T_4354 ? _Queue16_UInt8_17_io_deq_valid : _T_4353 ? _Queue16_UInt8_16_io_deq_valid : _T_4352 ? _Queue16_UInt8_15_io_deq_valid : _T_4351 ? _Queue16_UInt8_14_io_deq_valid : _T_4350 ? _Queue16_UInt8_13_io_deq_valid : _T_4349 ? _Queue16_UInt8_12_io_deq_valid : _T_4348 ? _Queue16_UInt8_11_io_deq_valid : _T_4347 ? _Queue16_UInt8_10_io_deq_valid : _T_4346 ? _Queue16_UInt8_9_io_deq_valid : _T_4345 ? _Queue16_UInt8_8_io_deq_valid : _T_4344 ? _Queue16_UInt8_7_io_deq_valid : _T_4343 ? _Queue16_UInt8_6_io_deq_valid : _T_4342 ? _Queue16_UInt8_5_io_deq_valid : _T_4341 ? _Queue16_UInt8_4_io_deq_valid : _T_4340 ? _Queue16_UInt8_3_io_deq_valid : _T_4339 ? _Queue16_UInt8_2_io_deq_valid : _T_4338 ? _Queue16_UInt8_1_io_deq_valid : _T_4337 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_91 = _remapindex_T_1 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_1 = _GEN_91[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4369 = remapindex_1 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4370 = remapindex_1 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4371 = remapindex_1 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4372 = remapindex_1 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4373 = remapindex_1 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4374 = remapindex_1 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4375 = remapindex_1 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4376 = remapindex_1 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4377 = remapindex_1 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4378 = remapindex_1 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4379 = remapindex_1 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4380 = remapindex_1 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4381 = remapindex_1 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4382 = remapindex_1 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4383 = remapindex_1 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4384 = remapindex_1 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4385 = remapindex_1 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4386 = remapindex_1 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4387 = remapindex_1 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4388 = remapindex_1 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4389 = remapindex_1 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4390 = remapindex_1 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4391 = remapindex_1 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4392 = remapindex_1 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4393 = remapindex_1 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4394 = remapindex_1 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4395 = remapindex_1 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4396 = remapindex_1 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4397 = remapindex_1 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4398 = remapindex_1 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4399 = remapindex_1 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4400 = remapindex_1 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_bits : _T_4399 ? _Queue16_UInt8_30_io_deq_bits : _T_4398 ? _Queue16_UInt8_29_io_deq_bits : _T_4397 ? _Queue16_UInt8_28_io_deq_bits : _T_4396 ? _Queue16_UInt8_27_io_deq_bits : _T_4395 ? _Queue16_UInt8_26_io_deq_bits : _T_4394 ? _Queue16_UInt8_25_io_deq_bits : _T_4393 ? _Queue16_UInt8_24_io_deq_bits : _T_4392 ? _Queue16_UInt8_23_io_deq_bits : _T_4391 ? _Queue16_UInt8_22_io_deq_bits : _T_4390 ? _Queue16_UInt8_21_io_deq_bits : _T_4389 ? _Queue16_UInt8_20_io_deq_bits : _T_4388 ? _Queue16_UInt8_19_io_deq_bits : _T_4387 ? _Queue16_UInt8_18_io_deq_bits : _T_4386 ? _Queue16_UInt8_17_io_deq_bits : _T_4385 ? _Queue16_UInt8_16_io_deq_bits : _T_4384 ? _Queue16_UInt8_15_io_deq_bits : _T_4383 ? _Queue16_UInt8_14_io_deq_bits : _T_4382 ? _Queue16_UInt8_13_io_deq_bits : _T_4381 ? _Queue16_UInt8_12_io_deq_bits : _T_4380 ? _Queue16_UInt8_11_io_deq_bits : _T_4379 ? _Queue16_UInt8_10_io_deq_bits : _T_4378 ? _Queue16_UInt8_9_io_deq_bits : _T_4377 ? _Queue16_UInt8_8_io_deq_bits : _T_4376 ? _Queue16_UInt8_7_io_deq_bits : _T_4375 ? _Queue16_UInt8_6_io_deq_bits : _T_4374 ? _Queue16_UInt8_5_io_deq_bits : _T_4373 ? _Queue16_UInt8_4_io_deq_bits : _T_4372 ? _Queue16_UInt8_3_io_deq_bits : _T_4371 ? _Queue16_UInt8_2_io_deq_bits : _T_4370 ? _Queue16_UInt8_1_io_deq_bits : _T_4369 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_valid : _T_4399 ? _Queue16_UInt8_30_io_deq_valid : _T_4398 ? _Queue16_UInt8_29_io_deq_valid : _T_4397 ? _Queue16_UInt8_28_io_deq_valid : _T_4396 ? _Queue16_UInt8_27_io_deq_valid : _T_4395 ? _Queue16_UInt8_26_io_deq_valid : _T_4394 ? _Queue16_UInt8_25_io_deq_valid : _T_4393 ? _Queue16_UInt8_24_io_deq_valid : _T_4392 ? _Queue16_UInt8_23_io_deq_valid : _T_4391 ? _Queue16_UInt8_22_io_deq_valid : _T_4390 ? _Queue16_UInt8_21_io_deq_valid : _T_4389 ? _Queue16_UInt8_20_io_deq_valid : _T_4388 ? _Queue16_UInt8_19_io_deq_valid : _T_4387 ? _Queue16_UInt8_18_io_deq_valid : _T_4386 ? _Queue16_UInt8_17_io_deq_valid : _T_4385 ? _Queue16_UInt8_16_io_deq_valid : _T_4384 ? _Queue16_UInt8_15_io_deq_valid : _T_4383 ? _Queue16_UInt8_14_io_deq_valid : _T_4382 ? _Queue16_UInt8_13_io_deq_valid : _T_4381 ? _Queue16_UInt8_12_io_deq_valid : _T_4380 ? _Queue16_UInt8_11_io_deq_valid : _T_4379 ? _Queue16_UInt8_10_io_deq_valid : _T_4378 ? _Queue16_UInt8_9_io_deq_valid : _T_4377 ? _Queue16_UInt8_8_io_deq_valid : _T_4376 ? _Queue16_UInt8_7_io_deq_valid : _T_4375 ? _Queue16_UInt8_6_io_deq_valid : _T_4374 ? _Queue16_UInt8_5_io_deq_valid : _T_4373 ? _Queue16_UInt8_4_io_deq_valid : _T_4372 ? _Queue16_UInt8_3_io_deq_valid : _T_4371 ? _Queue16_UInt8_2_io_deq_valid : _T_4370 ? _Queue16_UInt8_1_io_deq_valid : _T_4369 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_92 = _remapindex_T_2 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_2 = _GEN_92[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4401 = remapindex_2 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4402 = remapindex_2 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4403 = remapindex_2 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4404 = remapindex_2 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4405 = remapindex_2 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4406 = remapindex_2 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4407 = remapindex_2 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4408 = remapindex_2 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4409 = remapindex_2 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4410 = remapindex_2 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4411 = remapindex_2 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4412 = remapindex_2 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4413 = remapindex_2 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4414 = remapindex_2 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4415 = remapindex_2 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4416 = remapindex_2 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4417 = remapindex_2 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4418 = remapindex_2 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4419 = remapindex_2 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4420 = remapindex_2 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4421 = remapindex_2 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4422 = remapindex_2 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4423 = remapindex_2 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4424 = remapindex_2 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4425 = remapindex_2 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4426 = remapindex_2 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4427 = remapindex_2 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4428 = remapindex_2 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4429 = remapindex_2 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4430 = remapindex_2 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4431 = remapindex_2 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4432 = remapindex_2 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_bits : _T_4431 ? _Queue16_UInt8_30_io_deq_bits : _T_4430 ? _Queue16_UInt8_29_io_deq_bits : _T_4429 ? _Queue16_UInt8_28_io_deq_bits : _T_4428 ? _Queue16_UInt8_27_io_deq_bits : _T_4427 ? _Queue16_UInt8_26_io_deq_bits : _T_4426 ? _Queue16_UInt8_25_io_deq_bits : _T_4425 ? _Queue16_UInt8_24_io_deq_bits : _T_4424 ? _Queue16_UInt8_23_io_deq_bits : _T_4423 ? _Queue16_UInt8_22_io_deq_bits : _T_4422 ? _Queue16_UInt8_21_io_deq_bits : _T_4421 ? _Queue16_UInt8_20_io_deq_bits : _T_4420 ? _Queue16_UInt8_19_io_deq_bits : _T_4419 ? _Queue16_UInt8_18_io_deq_bits : _T_4418 ? _Queue16_UInt8_17_io_deq_bits : _T_4417 ? _Queue16_UInt8_16_io_deq_bits : _T_4416 ? _Queue16_UInt8_15_io_deq_bits : _T_4415 ? _Queue16_UInt8_14_io_deq_bits : _T_4414 ? _Queue16_UInt8_13_io_deq_bits : _T_4413 ? _Queue16_UInt8_12_io_deq_bits : _T_4412 ? _Queue16_UInt8_11_io_deq_bits : _T_4411 ? _Queue16_UInt8_10_io_deq_bits : _T_4410 ? _Queue16_UInt8_9_io_deq_bits : _T_4409 ? _Queue16_UInt8_8_io_deq_bits : _T_4408 ? _Queue16_UInt8_7_io_deq_bits : _T_4407 ? _Queue16_UInt8_6_io_deq_bits : _T_4406 ? _Queue16_UInt8_5_io_deq_bits : _T_4405 ? _Queue16_UInt8_4_io_deq_bits : _T_4404 ? _Queue16_UInt8_3_io_deq_bits : _T_4403 ? _Queue16_UInt8_2_io_deq_bits : _T_4402 ? _Queue16_UInt8_1_io_deq_bits : _T_4401 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_valid : _T_4431 ? _Queue16_UInt8_30_io_deq_valid : _T_4430 ? _Queue16_UInt8_29_io_deq_valid : _T_4429 ? _Queue16_UInt8_28_io_deq_valid : _T_4428 ? _Queue16_UInt8_27_io_deq_valid : _T_4427 ? _Queue16_UInt8_26_io_deq_valid : _T_4426 ? _Queue16_UInt8_25_io_deq_valid : _T_4425 ? _Queue16_UInt8_24_io_deq_valid : _T_4424 ? _Queue16_UInt8_23_io_deq_valid : _T_4423 ? _Queue16_UInt8_22_io_deq_valid : _T_4422 ? _Queue16_UInt8_21_io_deq_valid : _T_4421 ? _Queue16_UInt8_20_io_deq_valid : _T_4420 ? _Queue16_UInt8_19_io_deq_valid : _T_4419 ? _Queue16_UInt8_18_io_deq_valid : _T_4418 ? _Queue16_UInt8_17_io_deq_valid : _T_4417 ? _Queue16_UInt8_16_io_deq_valid : _T_4416 ? _Queue16_UInt8_15_io_deq_valid : _T_4415 ? _Queue16_UInt8_14_io_deq_valid : _T_4414 ? _Queue16_UInt8_13_io_deq_valid : _T_4413 ? _Queue16_UInt8_12_io_deq_valid : _T_4412 ? _Queue16_UInt8_11_io_deq_valid : _T_4411 ? _Queue16_UInt8_10_io_deq_valid : _T_4410 ? _Queue16_UInt8_9_io_deq_valid : _T_4409 ? _Queue16_UInt8_8_io_deq_valid : _T_4408 ? _Queue16_UInt8_7_io_deq_valid : _T_4407 ? _Queue16_UInt8_6_io_deq_valid : _T_4406 ? _Queue16_UInt8_5_io_deq_valid : _T_4405 ? _Queue16_UInt8_4_io_deq_valid : _T_4404 ? _Queue16_UInt8_3_io_deq_valid : _T_4403 ? _Queue16_UInt8_2_io_deq_valid : _T_4402 ? _Queue16_UInt8_1_io_deq_valid : _T_4401 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_93 = _remapindex_T_3 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_3 = _GEN_93[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4433 = remapindex_3 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4434 = remapindex_3 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4435 = remapindex_3 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4436 = remapindex_3 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4437 = remapindex_3 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4438 = remapindex_3 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4439 = remapindex_3 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4440 = remapindex_3 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4441 = remapindex_3 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4442 = remapindex_3 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4443 = remapindex_3 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4444 = remapindex_3 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4445 = remapindex_3 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4446 = remapindex_3 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4447 = remapindex_3 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4448 = remapindex_3 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4449 = remapindex_3 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4450 = remapindex_3 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4451 = remapindex_3 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4452 = remapindex_3 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4453 = remapindex_3 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4454 = remapindex_3 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4455 = remapindex_3 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4456 = remapindex_3 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4457 = remapindex_3 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4458 = remapindex_3 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4459 = remapindex_3 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4460 = remapindex_3 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4461 = remapindex_3 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4462 = remapindex_3 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4463 = remapindex_3 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4464 = remapindex_3 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_bits : _T_4463 ? _Queue16_UInt8_30_io_deq_bits : _T_4462 ? _Queue16_UInt8_29_io_deq_bits : _T_4461 ? _Queue16_UInt8_28_io_deq_bits : _T_4460 ? _Queue16_UInt8_27_io_deq_bits : _T_4459 ? _Queue16_UInt8_26_io_deq_bits : _T_4458 ? _Queue16_UInt8_25_io_deq_bits : _T_4457 ? _Queue16_UInt8_24_io_deq_bits : _T_4456 ? _Queue16_UInt8_23_io_deq_bits : _T_4455 ? _Queue16_UInt8_22_io_deq_bits : _T_4454 ? _Queue16_UInt8_21_io_deq_bits : _T_4453 ? _Queue16_UInt8_20_io_deq_bits : _T_4452 ? _Queue16_UInt8_19_io_deq_bits : _T_4451 ? _Queue16_UInt8_18_io_deq_bits : _T_4450 ? _Queue16_UInt8_17_io_deq_bits : _T_4449 ? _Queue16_UInt8_16_io_deq_bits : _T_4448 ? _Queue16_UInt8_15_io_deq_bits : _T_4447 ? _Queue16_UInt8_14_io_deq_bits : _T_4446 ? _Queue16_UInt8_13_io_deq_bits : _T_4445 ? _Queue16_UInt8_12_io_deq_bits : _T_4444 ? _Queue16_UInt8_11_io_deq_bits : _T_4443 ? _Queue16_UInt8_10_io_deq_bits : _T_4442 ? _Queue16_UInt8_9_io_deq_bits : _T_4441 ? _Queue16_UInt8_8_io_deq_bits : _T_4440 ? _Queue16_UInt8_7_io_deq_bits : _T_4439 ? _Queue16_UInt8_6_io_deq_bits : _T_4438 ? _Queue16_UInt8_5_io_deq_bits : _T_4437 ? _Queue16_UInt8_4_io_deq_bits : _T_4436 ? _Queue16_UInt8_3_io_deq_bits : _T_4435 ? _Queue16_UInt8_2_io_deq_bits : _T_4434 ? _Queue16_UInt8_1_io_deq_bits : _T_4433 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_valid : _T_4463 ? _Queue16_UInt8_30_io_deq_valid : _T_4462 ? _Queue16_UInt8_29_io_deq_valid : _T_4461 ? _Queue16_UInt8_28_io_deq_valid : _T_4460 ? _Queue16_UInt8_27_io_deq_valid : _T_4459 ? _Queue16_UInt8_26_io_deq_valid : _T_4458 ? _Queue16_UInt8_25_io_deq_valid : _T_4457 ? _Queue16_UInt8_24_io_deq_valid : _T_4456 ? _Queue16_UInt8_23_io_deq_valid : _T_4455 ? _Queue16_UInt8_22_io_deq_valid : _T_4454 ? _Queue16_UInt8_21_io_deq_valid : _T_4453 ? _Queue16_UInt8_20_io_deq_valid : _T_4452 ? _Queue16_UInt8_19_io_deq_valid : _T_4451 ? _Queue16_UInt8_18_io_deq_valid : _T_4450 ? _Queue16_UInt8_17_io_deq_valid : _T_4449 ? _Queue16_UInt8_16_io_deq_valid : _T_4448 ? _Queue16_UInt8_15_io_deq_valid : _T_4447 ? _Queue16_UInt8_14_io_deq_valid : _T_4446 ? _Queue16_UInt8_13_io_deq_valid : _T_4445 ? _Queue16_UInt8_12_io_deq_valid : _T_4444 ? _Queue16_UInt8_11_io_deq_valid : _T_4443 ? _Queue16_UInt8_10_io_deq_valid : _T_4442 ? _Queue16_UInt8_9_io_deq_valid : _T_4441 ? _Queue16_UInt8_8_io_deq_valid : _T_4440 ? _Queue16_UInt8_7_io_deq_valid : _T_4439 ? _Queue16_UInt8_6_io_deq_valid : _T_4438 ? _Queue16_UInt8_5_io_deq_valid : _T_4437 ? _Queue16_UInt8_4_io_deq_valid : _T_4436 ? _Queue16_UInt8_3_io_deq_valid : _T_4435 ? _Queue16_UInt8_2_io_deq_valid : _T_4434 ? _Queue16_UInt8_1_io_deq_valid : _T_4433 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_94 = _remapindex_T_4 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_4 = _GEN_94[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4465 = remapindex_4 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4466 = remapindex_4 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4467 = remapindex_4 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4468 = remapindex_4 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4469 = remapindex_4 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4470 = remapindex_4 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4471 = remapindex_4 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4472 = remapindex_4 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4473 = remapindex_4 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4474 = remapindex_4 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4475 = remapindex_4 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4476 = remapindex_4 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4477 = remapindex_4 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4478 = remapindex_4 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4479 = remapindex_4 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4480 = remapindex_4 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4481 = remapindex_4 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4482 = remapindex_4 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4483 = remapindex_4 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4484 = remapindex_4 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4485 = remapindex_4 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4486 = remapindex_4 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4487 = remapindex_4 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4488 = remapindex_4 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4489 = remapindex_4 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4490 = remapindex_4 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4491 = remapindex_4 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4492 = remapindex_4 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4493 = remapindex_4 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4494 = remapindex_4 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4495 = remapindex_4 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4496 = remapindex_4 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_bits : _T_4495 ? _Queue16_UInt8_30_io_deq_bits : _T_4494 ? _Queue16_UInt8_29_io_deq_bits : _T_4493 ? _Queue16_UInt8_28_io_deq_bits : _T_4492 ? _Queue16_UInt8_27_io_deq_bits : _T_4491 ? _Queue16_UInt8_26_io_deq_bits : _T_4490 ? _Queue16_UInt8_25_io_deq_bits : _T_4489 ? _Queue16_UInt8_24_io_deq_bits : _T_4488 ? _Queue16_UInt8_23_io_deq_bits : _T_4487 ? _Queue16_UInt8_22_io_deq_bits : _T_4486 ? _Queue16_UInt8_21_io_deq_bits : _T_4485 ? _Queue16_UInt8_20_io_deq_bits : _T_4484 ? _Queue16_UInt8_19_io_deq_bits : _T_4483 ? _Queue16_UInt8_18_io_deq_bits : _T_4482 ? _Queue16_UInt8_17_io_deq_bits : _T_4481 ? _Queue16_UInt8_16_io_deq_bits : _T_4480 ? _Queue16_UInt8_15_io_deq_bits : _T_4479 ? _Queue16_UInt8_14_io_deq_bits : _T_4478 ? _Queue16_UInt8_13_io_deq_bits : _T_4477 ? _Queue16_UInt8_12_io_deq_bits : _T_4476 ? _Queue16_UInt8_11_io_deq_bits : _T_4475 ? _Queue16_UInt8_10_io_deq_bits : _T_4474 ? _Queue16_UInt8_9_io_deq_bits : _T_4473 ? _Queue16_UInt8_8_io_deq_bits : _T_4472 ? _Queue16_UInt8_7_io_deq_bits : _T_4471 ? _Queue16_UInt8_6_io_deq_bits : _T_4470 ? _Queue16_UInt8_5_io_deq_bits : _T_4469 ? _Queue16_UInt8_4_io_deq_bits : _T_4468 ? _Queue16_UInt8_3_io_deq_bits : _T_4467 ? _Queue16_UInt8_2_io_deq_bits : _T_4466 ? _Queue16_UInt8_1_io_deq_bits : _T_4465 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_valid : _T_4495 ? _Queue16_UInt8_30_io_deq_valid : _T_4494 ? _Queue16_UInt8_29_io_deq_valid : _T_4493 ? _Queue16_UInt8_28_io_deq_valid : _T_4492 ? _Queue16_UInt8_27_io_deq_valid : _T_4491 ? _Queue16_UInt8_26_io_deq_valid : _T_4490 ? _Queue16_UInt8_25_io_deq_valid : _T_4489 ? _Queue16_UInt8_24_io_deq_valid : _T_4488 ? _Queue16_UInt8_23_io_deq_valid : _T_4487 ? _Queue16_UInt8_22_io_deq_valid : _T_4486 ? _Queue16_UInt8_21_io_deq_valid : _T_4485 ? _Queue16_UInt8_20_io_deq_valid : _T_4484 ? _Queue16_UInt8_19_io_deq_valid : _T_4483 ? _Queue16_UInt8_18_io_deq_valid : _T_4482 ? _Queue16_UInt8_17_io_deq_valid : _T_4481 ? _Queue16_UInt8_16_io_deq_valid : _T_4480 ? _Queue16_UInt8_15_io_deq_valid : _T_4479 ? _Queue16_UInt8_14_io_deq_valid : _T_4478 ? _Queue16_UInt8_13_io_deq_valid : _T_4477 ? _Queue16_UInt8_12_io_deq_valid : _T_4476 ? _Queue16_UInt8_11_io_deq_valid : _T_4475 ? _Queue16_UInt8_10_io_deq_valid : _T_4474 ? _Queue16_UInt8_9_io_deq_valid : _T_4473 ? _Queue16_UInt8_8_io_deq_valid : _T_4472 ? _Queue16_UInt8_7_io_deq_valid : _T_4471 ? _Queue16_UInt8_6_io_deq_valid : _T_4470 ? _Queue16_UInt8_5_io_deq_valid : _T_4469 ? _Queue16_UInt8_4_io_deq_valid : _T_4468 ? _Queue16_UInt8_3_io_deq_valid : _T_4467 ? _Queue16_UInt8_2_io_deq_valid : _T_4466 ? _Queue16_UInt8_1_io_deq_valid : _T_4465 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_95 = _remapindex_T_5 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_5 = _GEN_95[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4497 = remapindex_5 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4498 = remapindex_5 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4499 = remapindex_5 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4500 = remapindex_5 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4501 = remapindex_5 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4502 = remapindex_5 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4503 = remapindex_5 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4504 = remapindex_5 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4505 = remapindex_5 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4506 = remapindex_5 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4507 = remapindex_5 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4508 = remapindex_5 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4509 = remapindex_5 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4510 = remapindex_5 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4511 = remapindex_5 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4512 = remapindex_5 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4513 = remapindex_5 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4514 = remapindex_5 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4515 = remapindex_5 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4516 = remapindex_5 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4517 = remapindex_5 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4518 = remapindex_5 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4519 = remapindex_5 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4520 = remapindex_5 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4521 = remapindex_5 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4522 = remapindex_5 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4523 = remapindex_5 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4524 = remapindex_5 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4525 = remapindex_5 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4526 = remapindex_5 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4527 = remapindex_5 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4528 = remapindex_5 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_bits : _T_4527 ? _Queue16_UInt8_30_io_deq_bits : _T_4526 ? _Queue16_UInt8_29_io_deq_bits : _T_4525 ? _Queue16_UInt8_28_io_deq_bits : _T_4524 ? _Queue16_UInt8_27_io_deq_bits : _T_4523 ? _Queue16_UInt8_26_io_deq_bits : _T_4522 ? _Queue16_UInt8_25_io_deq_bits : _T_4521 ? _Queue16_UInt8_24_io_deq_bits : _T_4520 ? _Queue16_UInt8_23_io_deq_bits : _T_4519 ? _Queue16_UInt8_22_io_deq_bits : _T_4518 ? _Queue16_UInt8_21_io_deq_bits : _T_4517 ? _Queue16_UInt8_20_io_deq_bits : _T_4516 ? _Queue16_UInt8_19_io_deq_bits : _T_4515 ? _Queue16_UInt8_18_io_deq_bits : _T_4514 ? _Queue16_UInt8_17_io_deq_bits : _T_4513 ? _Queue16_UInt8_16_io_deq_bits : _T_4512 ? _Queue16_UInt8_15_io_deq_bits : _T_4511 ? _Queue16_UInt8_14_io_deq_bits : _T_4510 ? _Queue16_UInt8_13_io_deq_bits : _T_4509 ? _Queue16_UInt8_12_io_deq_bits : _T_4508 ? _Queue16_UInt8_11_io_deq_bits : _T_4507 ? _Queue16_UInt8_10_io_deq_bits : _T_4506 ? _Queue16_UInt8_9_io_deq_bits : _T_4505 ? _Queue16_UInt8_8_io_deq_bits : _T_4504 ? _Queue16_UInt8_7_io_deq_bits : _T_4503 ? _Queue16_UInt8_6_io_deq_bits : _T_4502 ? _Queue16_UInt8_5_io_deq_bits : _T_4501 ? _Queue16_UInt8_4_io_deq_bits : _T_4500 ? _Queue16_UInt8_3_io_deq_bits : _T_4499 ? _Queue16_UInt8_2_io_deq_bits : _T_4498 ? _Queue16_UInt8_1_io_deq_bits : _T_4497 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_valid : _T_4527 ? _Queue16_UInt8_30_io_deq_valid : _T_4526 ? _Queue16_UInt8_29_io_deq_valid : _T_4525 ? _Queue16_UInt8_28_io_deq_valid : _T_4524 ? _Queue16_UInt8_27_io_deq_valid : _T_4523 ? _Queue16_UInt8_26_io_deq_valid : _T_4522 ? _Queue16_UInt8_25_io_deq_valid : _T_4521 ? _Queue16_UInt8_24_io_deq_valid : _T_4520 ? _Queue16_UInt8_23_io_deq_valid : _T_4519 ? _Queue16_UInt8_22_io_deq_valid : _T_4518 ? _Queue16_UInt8_21_io_deq_valid : _T_4517 ? _Queue16_UInt8_20_io_deq_valid : _T_4516 ? _Queue16_UInt8_19_io_deq_valid : _T_4515 ? _Queue16_UInt8_18_io_deq_valid : _T_4514 ? _Queue16_UInt8_17_io_deq_valid : _T_4513 ? _Queue16_UInt8_16_io_deq_valid : _T_4512 ? _Queue16_UInt8_15_io_deq_valid : _T_4511 ? _Queue16_UInt8_14_io_deq_valid : _T_4510 ? _Queue16_UInt8_13_io_deq_valid : _T_4509 ? _Queue16_UInt8_12_io_deq_valid : _T_4508 ? _Queue16_UInt8_11_io_deq_valid : _T_4507 ? _Queue16_UInt8_10_io_deq_valid : _T_4506 ? _Queue16_UInt8_9_io_deq_valid : _T_4505 ? _Queue16_UInt8_8_io_deq_valid : _T_4504 ? _Queue16_UInt8_7_io_deq_valid : _T_4503 ? _Queue16_UInt8_6_io_deq_valid : _T_4502 ? _Queue16_UInt8_5_io_deq_valid : _T_4501 ? _Queue16_UInt8_4_io_deq_valid : _T_4500 ? _Queue16_UInt8_3_io_deq_valid : _T_4499 ? _Queue16_UInt8_2_io_deq_valid : _T_4498 ? _Queue16_UInt8_1_io_deq_valid : _T_4497 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_96 = _remapindex_T_6 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_6 = _GEN_96[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4529 = remapindex_6 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4530 = remapindex_6 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4531 = remapindex_6 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4532 = remapindex_6 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4533 = remapindex_6 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4534 = remapindex_6 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4535 = remapindex_6 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4536 = remapindex_6 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4537 = remapindex_6 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4538 = remapindex_6 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4539 = remapindex_6 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4540 = remapindex_6 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4541 = remapindex_6 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4542 = remapindex_6 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4543 = remapindex_6 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4544 = remapindex_6 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4545 = remapindex_6 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4546 = remapindex_6 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4547 = remapindex_6 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4548 = remapindex_6 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4549 = remapindex_6 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4550 = remapindex_6 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4551 = remapindex_6 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4552 = remapindex_6 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4553 = remapindex_6 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4554 = remapindex_6 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4555 = remapindex_6 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4556 = remapindex_6 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4557 = remapindex_6 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4558 = remapindex_6 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4559 = remapindex_6 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4560 = remapindex_6 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_bits : _T_4559 ? _Queue16_UInt8_30_io_deq_bits : _T_4558 ? _Queue16_UInt8_29_io_deq_bits : _T_4557 ? _Queue16_UInt8_28_io_deq_bits : _T_4556 ? _Queue16_UInt8_27_io_deq_bits : _T_4555 ? _Queue16_UInt8_26_io_deq_bits : _T_4554 ? _Queue16_UInt8_25_io_deq_bits : _T_4553 ? _Queue16_UInt8_24_io_deq_bits : _T_4552 ? _Queue16_UInt8_23_io_deq_bits : _T_4551 ? _Queue16_UInt8_22_io_deq_bits : _T_4550 ? _Queue16_UInt8_21_io_deq_bits : _T_4549 ? _Queue16_UInt8_20_io_deq_bits : _T_4548 ? _Queue16_UInt8_19_io_deq_bits : _T_4547 ? _Queue16_UInt8_18_io_deq_bits : _T_4546 ? _Queue16_UInt8_17_io_deq_bits : _T_4545 ? _Queue16_UInt8_16_io_deq_bits : _T_4544 ? _Queue16_UInt8_15_io_deq_bits : _T_4543 ? _Queue16_UInt8_14_io_deq_bits : _T_4542 ? _Queue16_UInt8_13_io_deq_bits : _T_4541 ? _Queue16_UInt8_12_io_deq_bits : _T_4540 ? _Queue16_UInt8_11_io_deq_bits : _T_4539 ? _Queue16_UInt8_10_io_deq_bits : _T_4538 ? _Queue16_UInt8_9_io_deq_bits : _T_4537 ? _Queue16_UInt8_8_io_deq_bits : _T_4536 ? _Queue16_UInt8_7_io_deq_bits : _T_4535 ? _Queue16_UInt8_6_io_deq_bits : _T_4534 ? _Queue16_UInt8_5_io_deq_bits : _T_4533 ? _Queue16_UInt8_4_io_deq_bits : _T_4532 ? _Queue16_UInt8_3_io_deq_bits : _T_4531 ? _Queue16_UInt8_2_io_deq_bits : _T_4530 ? _Queue16_UInt8_1_io_deq_bits : _T_4529 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_valid : _T_4559 ? _Queue16_UInt8_30_io_deq_valid : _T_4558 ? _Queue16_UInt8_29_io_deq_valid : _T_4557 ? _Queue16_UInt8_28_io_deq_valid : _T_4556 ? _Queue16_UInt8_27_io_deq_valid : _T_4555 ? _Queue16_UInt8_26_io_deq_valid : _T_4554 ? _Queue16_UInt8_25_io_deq_valid : _T_4553 ? _Queue16_UInt8_24_io_deq_valid : _T_4552 ? _Queue16_UInt8_23_io_deq_valid : _T_4551 ? _Queue16_UInt8_22_io_deq_valid : _T_4550 ? _Queue16_UInt8_21_io_deq_valid : _T_4549 ? _Queue16_UInt8_20_io_deq_valid : _T_4548 ? _Queue16_UInt8_19_io_deq_valid : _T_4547 ? _Queue16_UInt8_18_io_deq_valid : _T_4546 ? _Queue16_UInt8_17_io_deq_valid : _T_4545 ? _Queue16_UInt8_16_io_deq_valid : _T_4544 ? _Queue16_UInt8_15_io_deq_valid : _T_4543 ? _Queue16_UInt8_14_io_deq_valid : _T_4542 ? _Queue16_UInt8_13_io_deq_valid : _T_4541 ? _Queue16_UInt8_12_io_deq_valid : _T_4540 ? _Queue16_UInt8_11_io_deq_valid : _T_4539 ? _Queue16_UInt8_10_io_deq_valid : _T_4538 ? _Queue16_UInt8_9_io_deq_valid : _T_4537 ? _Queue16_UInt8_8_io_deq_valid : _T_4536 ? _Queue16_UInt8_7_io_deq_valid : _T_4535 ? _Queue16_UInt8_6_io_deq_valid : _T_4534 ? _Queue16_UInt8_5_io_deq_valid : _T_4533 ? _Queue16_UInt8_4_io_deq_valid : _T_4532 ? _Queue16_UInt8_3_io_deq_valid : _T_4531 ? _Queue16_UInt8_2_io_deq_valid : _T_4530 ? _Queue16_UInt8_1_io_deq_valid : _T_4529 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_97 = _remapindex_T_7 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_7 = _GEN_97[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4561 = remapindex_7 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4562 = remapindex_7 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4563 = remapindex_7 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4564 = remapindex_7 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4565 = remapindex_7 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4566 = remapindex_7 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4567 = remapindex_7 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4568 = remapindex_7 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4569 = remapindex_7 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4570 = remapindex_7 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4571 = remapindex_7 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4572 = remapindex_7 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4573 = remapindex_7 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4574 = remapindex_7 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4575 = remapindex_7 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4576 = remapindex_7 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4577 = remapindex_7 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4578 = remapindex_7 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4579 = remapindex_7 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4580 = remapindex_7 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4581 = remapindex_7 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4582 = remapindex_7 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4583 = remapindex_7 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4584 = remapindex_7 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4585 = remapindex_7 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4586 = remapindex_7 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4587 = remapindex_7 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4588 = remapindex_7 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4589 = remapindex_7 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4590 = remapindex_7 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4591 = remapindex_7 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4592 = remapindex_7 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_bits : _T_4591 ? _Queue16_UInt8_30_io_deq_bits : _T_4590 ? _Queue16_UInt8_29_io_deq_bits : _T_4589 ? _Queue16_UInt8_28_io_deq_bits : _T_4588 ? _Queue16_UInt8_27_io_deq_bits : _T_4587 ? _Queue16_UInt8_26_io_deq_bits : _T_4586 ? _Queue16_UInt8_25_io_deq_bits : _T_4585 ? _Queue16_UInt8_24_io_deq_bits : _T_4584 ? _Queue16_UInt8_23_io_deq_bits : _T_4583 ? _Queue16_UInt8_22_io_deq_bits : _T_4582 ? _Queue16_UInt8_21_io_deq_bits : _T_4581 ? _Queue16_UInt8_20_io_deq_bits : _T_4580 ? _Queue16_UInt8_19_io_deq_bits : _T_4579 ? _Queue16_UInt8_18_io_deq_bits : _T_4578 ? _Queue16_UInt8_17_io_deq_bits : _T_4577 ? _Queue16_UInt8_16_io_deq_bits : _T_4576 ? _Queue16_UInt8_15_io_deq_bits : _T_4575 ? _Queue16_UInt8_14_io_deq_bits : _T_4574 ? _Queue16_UInt8_13_io_deq_bits : _T_4573 ? _Queue16_UInt8_12_io_deq_bits : _T_4572 ? _Queue16_UInt8_11_io_deq_bits : _T_4571 ? _Queue16_UInt8_10_io_deq_bits : _T_4570 ? _Queue16_UInt8_9_io_deq_bits : _T_4569 ? _Queue16_UInt8_8_io_deq_bits : _T_4568 ? _Queue16_UInt8_7_io_deq_bits : _T_4567 ? _Queue16_UInt8_6_io_deq_bits : _T_4566 ? _Queue16_UInt8_5_io_deq_bits : _T_4565 ? _Queue16_UInt8_4_io_deq_bits : _T_4564 ? _Queue16_UInt8_3_io_deq_bits : _T_4563 ? _Queue16_UInt8_2_io_deq_bits : _T_4562 ? _Queue16_UInt8_1_io_deq_bits : _T_4561 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_valid : _T_4591 ? _Queue16_UInt8_30_io_deq_valid : _T_4590 ? _Queue16_UInt8_29_io_deq_valid : _T_4589 ? _Queue16_UInt8_28_io_deq_valid : _T_4588 ? _Queue16_UInt8_27_io_deq_valid : _T_4587 ? _Queue16_UInt8_26_io_deq_valid : _T_4586 ? _Queue16_UInt8_25_io_deq_valid : _T_4585 ? _Queue16_UInt8_24_io_deq_valid : _T_4584 ? _Queue16_UInt8_23_io_deq_valid : _T_4583 ? _Queue16_UInt8_22_io_deq_valid : _T_4582 ? _Queue16_UInt8_21_io_deq_valid : _T_4581 ? _Queue16_UInt8_20_io_deq_valid : _T_4580 ? _Queue16_UInt8_19_io_deq_valid : _T_4579 ? _Queue16_UInt8_18_io_deq_valid : _T_4578 ? _Queue16_UInt8_17_io_deq_valid : _T_4577 ? _Queue16_UInt8_16_io_deq_valid : _T_4576 ? _Queue16_UInt8_15_io_deq_valid : _T_4575 ? _Queue16_UInt8_14_io_deq_valid : _T_4574 ? _Queue16_UInt8_13_io_deq_valid : _T_4573 ? _Queue16_UInt8_12_io_deq_valid : _T_4572 ? _Queue16_UInt8_11_io_deq_valid : _T_4571 ? _Queue16_UInt8_10_io_deq_valid : _T_4570 ? _Queue16_UInt8_9_io_deq_valid : _T_4569 ? _Queue16_UInt8_8_io_deq_valid : _T_4568 ? _Queue16_UInt8_7_io_deq_valid : _T_4567 ? _Queue16_UInt8_6_io_deq_valid : _T_4566 ? _Queue16_UInt8_5_io_deq_valid : _T_4565 ? _Queue16_UInt8_4_io_deq_valid : _T_4564 ? _Queue16_UInt8_3_io_deq_valid : _T_4563 ? _Queue16_UInt8_2_io_deq_valid : _T_4562 ? _Queue16_UInt8_1_io_deq_valid : _T_4561 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_98 = _remapindex_T_8 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_8 = _GEN_98[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4593 = remapindex_8 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4594 = remapindex_8 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4595 = remapindex_8 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4596 = remapindex_8 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4597 = remapindex_8 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4598 = remapindex_8 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4599 = remapindex_8 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4600 = remapindex_8 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4601 = remapindex_8 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4602 = remapindex_8 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4603 = remapindex_8 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4604 = remapindex_8 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4605 = remapindex_8 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4606 = remapindex_8 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4607 = remapindex_8 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4608 = remapindex_8 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4609 = remapindex_8 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4610 = remapindex_8 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4611 = remapindex_8 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4612 = remapindex_8 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4613 = remapindex_8 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4614 = remapindex_8 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4615 = remapindex_8 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4616 = remapindex_8 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4617 = remapindex_8 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4618 = remapindex_8 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4619 = remapindex_8 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4620 = remapindex_8 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4621 = remapindex_8 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4622 = remapindex_8 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4623 = remapindex_8 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4624 = remapindex_8 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_bits : _T_4623 ? _Queue16_UInt8_30_io_deq_bits : _T_4622 ? _Queue16_UInt8_29_io_deq_bits : _T_4621 ? _Queue16_UInt8_28_io_deq_bits : _T_4620 ? _Queue16_UInt8_27_io_deq_bits : _T_4619 ? _Queue16_UInt8_26_io_deq_bits : _T_4618 ? _Queue16_UInt8_25_io_deq_bits : _T_4617 ? _Queue16_UInt8_24_io_deq_bits : _T_4616 ? _Queue16_UInt8_23_io_deq_bits : _T_4615 ? _Queue16_UInt8_22_io_deq_bits : _T_4614 ? _Queue16_UInt8_21_io_deq_bits : _T_4613 ? _Queue16_UInt8_20_io_deq_bits : _T_4612 ? _Queue16_UInt8_19_io_deq_bits : _T_4611 ? _Queue16_UInt8_18_io_deq_bits : _T_4610 ? _Queue16_UInt8_17_io_deq_bits : _T_4609 ? _Queue16_UInt8_16_io_deq_bits : _T_4608 ? _Queue16_UInt8_15_io_deq_bits : _T_4607 ? _Queue16_UInt8_14_io_deq_bits : _T_4606 ? _Queue16_UInt8_13_io_deq_bits : _T_4605 ? _Queue16_UInt8_12_io_deq_bits : _T_4604 ? _Queue16_UInt8_11_io_deq_bits : _T_4603 ? _Queue16_UInt8_10_io_deq_bits : _T_4602 ? _Queue16_UInt8_9_io_deq_bits : _T_4601 ? _Queue16_UInt8_8_io_deq_bits : _T_4600 ? _Queue16_UInt8_7_io_deq_bits : _T_4599 ? _Queue16_UInt8_6_io_deq_bits : _T_4598 ? _Queue16_UInt8_5_io_deq_bits : _T_4597 ? _Queue16_UInt8_4_io_deq_bits : _T_4596 ? _Queue16_UInt8_3_io_deq_bits : _T_4595 ? _Queue16_UInt8_2_io_deq_bits : _T_4594 ? _Queue16_UInt8_1_io_deq_bits : _T_4593 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_valid : _T_4623 ? _Queue16_UInt8_30_io_deq_valid : _T_4622 ? _Queue16_UInt8_29_io_deq_valid : _T_4621 ? _Queue16_UInt8_28_io_deq_valid : _T_4620 ? _Queue16_UInt8_27_io_deq_valid : _T_4619 ? _Queue16_UInt8_26_io_deq_valid : _T_4618 ? _Queue16_UInt8_25_io_deq_valid : _T_4617 ? _Queue16_UInt8_24_io_deq_valid : _T_4616 ? _Queue16_UInt8_23_io_deq_valid : _T_4615 ? _Queue16_UInt8_22_io_deq_valid : _T_4614 ? _Queue16_UInt8_21_io_deq_valid : _T_4613 ? _Queue16_UInt8_20_io_deq_valid : _T_4612 ? _Queue16_UInt8_19_io_deq_valid : _T_4611 ? _Queue16_UInt8_18_io_deq_valid : _T_4610 ? _Queue16_UInt8_17_io_deq_valid : _T_4609 ? _Queue16_UInt8_16_io_deq_valid : _T_4608 ? _Queue16_UInt8_15_io_deq_valid : _T_4607 ? _Queue16_UInt8_14_io_deq_valid : _T_4606 ? _Queue16_UInt8_13_io_deq_valid : _T_4605 ? _Queue16_UInt8_12_io_deq_valid : _T_4604 ? _Queue16_UInt8_11_io_deq_valid : _T_4603 ? _Queue16_UInt8_10_io_deq_valid : _T_4602 ? _Queue16_UInt8_9_io_deq_valid : _T_4601 ? _Queue16_UInt8_8_io_deq_valid : _T_4600 ? _Queue16_UInt8_7_io_deq_valid : _T_4599 ? _Queue16_UInt8_6_io_deq_valid : _T_4598 ? _Queue16_UInt8_5_io_deq_valid : _T_4597 ? _Queue16_UInt8_4_io_deq_valid : _T_4596 ? _Queue16_UInt8_3_io_deq_valid : _T_4595 ? _Queue16_UInt8_2_io_deq_valid : _T_4594 ? _Queue16_UInt8_1_io_deq_valid : _T_4593 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_99 = _remapindex_T_9 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_9 = _GEN_99[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4625 = remapindex_9 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4626 = remapindex_9 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4627 = remapindex_9 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4628 = remapindex_9 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4629 = remapindex_9 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4630 = remapindex_9 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4631 = remapindex_9 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4632 = remapindex_9 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4633 = remapindex_9 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4634 = remapindex_9 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4635 = remapindex_9 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4636 = remapindex_9 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4637 = remapindex_9 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4638 = remapindex_9 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4639 = remapindex_9 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4640 = remapindex_9 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4641 = remapindex_9 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4642 = remapindex_9 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4643 = remapindex_9 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4644 = remapindex_9 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4645 = remapindex_9 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4646 = remapindex_9 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4647 = remapindex_9 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4648 = remapindex_9 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4649 = remapindex_9 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4650 = remapindex_9 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4651 = remapindex_9 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4652 = remapindex_9 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4653 = remapindex_9 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4654 = remapindex_9 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4655 = remapindex_9 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4656 = remapindex_9 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_bits : _T_4655 ? _Queue16_UInt8_30_io_deq_bits : _T_4654 ? _Queue16_UInt8_29_io_deq_bits : _T_4653 ? _Queue16_UInt8_28_io_deq_bits : _T_4652 ? _Queue16_UInt8_27_io_deq_bits : _T_4651 ? _Queue16_UInt8_26_io_deq_bits : _T_4650 ? _Queue16_UInt8_25_io_deq_bits : _T_4649 ? _Queue16_UInt8_24_io_deq_bits : _T_4648 ? _Queue16_UInt8_23_io_deq_bits : _T_4647 ? _Queue16_UInt8_22_io_deq_bits : _T_4646 ? _Queue16_UInt8_21_io_deq_bits : _T_4645 ? _Queue16_UInt8_20_io_deq_bits : _T_4644 ? _Queue16_UInt8_19_io_deq_bits : _T_4643 ? _Queue16_UInt8_18_io_deq_bits : _T_4642 ? _Queue16_UInt8_17_io_deq_bits : _T_4641 ? _Queue16_UInt8_16_io_deq_bits : _T_4640 ? _Queue16_UInt8_15_io_deq_bits : _T_4639 ? _Queue16_UInt8_14_io_deq_bits : _T_4638 ? _Queue16_UInt8_13_io_deq_bits : _T_4637 ? _Queue16_UInt8_12_io_deq_bits : _T_4636 ? _Queue16_UInt8_11_io_deq_bits : _T_4635 ? _Queue16_UInt8_10_io_deq_bits : _T_4634 ? _Queue16_UInt8_9_io_deq_bits : _T_4633 ? _Queue16_UInt8_8_io_deq_bits : _T_4632 ? _Queue16_UInt8_7_io_deq_bits : _T_4631 ? _Queue16_UInt8_6_io_deq_bits : _T_4630 ? _Queue16_UInt8_5_io_deq_bits : _T_4629 ? _Queue16_UInt8_4_io_deq_bits : _T_4628 ? _Queue16_UInt8_3_io_deq_bits : _T_4627 ? _Queue16_UInt8_2_io_deq_bits : _T_4626 ? _Queue16_UInt8_1_io_deq_bits : _T_4625 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_valid : _T_4655 ? _Queue16_UInt8_30_io_deq_valid : _T_4654 ? _Queue16_UInt8_29_io_deq_valid : _T_4653 ? _Queue16_UInt8_28_io_deq_valid : _T_4652 ? _Queue16_UInt8_27_io_deq_valid : _T_4651 ? _Queue16_UInt8_26_io_deq_valid : _T_4650 ? _Queue16_UInt8_25_io_deq_valid : _T_4649 ? _Queue16_UInt8_24_io_deq_valid : _T_4648 ? _Queue16_UInt8_23_io_deq_valid : _T_4647 ? _Queue16_UInt8_22_io_deq_valid : _T_4646 ? _Queue16_UInt8_21_io_deq_valid : _T_4645 ? _Queue16_UInt8_20_io_deq_valid : _T_4644 ? _Queue16_UInt8_19_io_deq_valid : _T_4643 ? _Queue16_UInt8_18_io_deq_valid : _T_4642 ? _Queue16_UInt8_17_io_deq_valid : _T_4641 ? _Queue16_UInt8_16_io_deq_valid : _T_4640 ? _Queue16_UInt8_15_io_deq_valid : _T_4639 ? _Queue16_UInt8_14_io_deq_valid : _T_4638 ? _Queue16_UInt8_13_io_deq_valid : _T_4637 ? _Queue16_UInt8_12_io_deq_valid : _T_4636 ? _Queue16_UInt8_11_io_deq_valid : _T_4635 ? _Queue16_UInt8_10_io_deq_valid : _T_4634 ? _Queue16_UInt8_9_io_deq_valid : _T_4633 ? _Queue16_UInt8_8_io_deq_valid : _T_4632 ? _Queue16_UInt8_7_io_deq_valid : _T_4631 ? _Queue16_UInt8_6_io_deq_valid : _T_4630 ? _Queue16_UInt8_5_io_deq_valid : _T_4629 ? _Queue16_UInt8_4_io_deq_valid : _T_4628 ? _Queue16_UInt8_3_io_deq_valid : _T_4627 ? _Queue16_UInt8_2_io_deq_valid : _T_4626 ? _Queue16_UInt8_1_io_deq_valid : _T_4625 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_100 = _remapindex_T_10 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_10 = _GEN_100[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4657 = remapindex_10 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4658 = remapindex_10 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4659 = remapindex_10 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4660 = remapindex_10 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4661 = remapindex_10 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4662 = remapindex_10 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4663 = remapindex_10 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4664 = remapindex_10 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4665 = remapindex_10 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4666 = remapindex_10 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4667 = remapindex_10 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4668 = remapindex_10 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4669 = remapindex_10 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4670 = remapindex_10 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4671 = remapindex_10 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4672 = remapindex_10 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4673 = remapindex_10 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4674 = remapindex_10 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4675 = remapindex_10 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4676 = remapindex_10 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4677 = remapindex_10 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4678 = remapindex_10 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4679 = remapindex_10 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4680 = remapindex_10 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4681 = remapindex_10 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4682 = remapindex_10 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4683 = remapindex_10 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4684 = remapindex_10 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4685 = remapindex_10 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4686 = remapindex_10 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4687 = remapindex_10 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4688 = remapindex_10 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_bits : _T_4687 ? _Queue16_UInt8_30_io_deq_bits : _T_4686 ? _Queue16_UInt8_29_io_deq_bits : _T_4685 ? _Queue16_UInt8_28_io_deq_bits : _T_4684 ? _Queue16_UInt8_27_io_deq_bits : _T_4683 ? _Queue16_UInt8_26_io_deq_bits : _T_4682 ? _Queue16_UInt8_25_io_deq_bits : _T_4681 ? _Queue16_UInt8_24_io_deq_bits : _T_4680 ? _Queue16_UInt8_23_io_deq_bits : _T_4679 ? _Queue16_UInt8_22_io_deq_bits : _T_4678 ? _Queue16_UInt8_21_io_deq_bits : _T_4677 ? _Queue16_UInt8_20_io_deq_bits : _T_4676 ? _Queue16_UInt8_19_io_deq_bits : _T_4675 ? _Queue16_UInt8_18_io_deq_bits : _T_4674 ? _Queue16_UInt8_17_io_deq_bits : _T_4673 ? _Queue16_UInt8_16_io_deq_bits : _T_4672 ? _Queue16_UInt8_15_io_deq_bits : _T_4671 ? _Queue16_UInt8_14_io_deq_bits : _T_4670 ? _Queue16_UInt8_13_io_deq_bits : _T_4669 ? _Queue16_UInt8_12_io_deq_bits : _T_4668 ? _Queue16_UInt8_11_io_deq_bits : _T_4667 ? _Queue16_UInt8_10_io_deq_bits : _T_4666 ? _Queue16_UInt8_9_io_deq_bits : _T_4665 ? _Queue16_UInt8_8_io_deq_bits : _T_4664 ? _Queue16_UInt8_7_io_deq_bits : _T_4663 ? _Queue16_UInt8_6_io_deq_bits : _T_4662 ? _Queue16_UInt8_5_io_deq_bits : _T_4661 ? _Queue16_UInt8_4_io_deq_bits : _T_4660 ? _Queue16_UInt8_3_io_deq_bits : _T_4659 ? _Queue16_UInt8_2_io_deq_bits : _T_4658 ? _Queue16_UInt8_1_io_deq_bits : _T_4657 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_valid : _T_4687 ? _Queue16_UInt8_30_io_deq_valid : _T_4686 ? _Queue16_UInt8_29_io_deq_valid : _T_4685 ? _Queue16_UInt8_28_io_deq_valid : _T_4684 ? _Queue16_UInt8_27_io_deq_valid : _T_4683 ? _Queue16_UInt8_26_io_deq_valid : _T_4682 ? _Queue16_UInt8_25_io_deq_valid : _T_4681 ? _Queue16_UInt8_24_io_deq_valid : _T_4680 ? _Queue16_UInt8_23_io_deq_valid : _T_4679 ? _Queue16_UInt8_22_io_deq_valid : _T_4678 ? _Queue16_UInt8_21_io_deq_valid : _T_4677 ? _Queue16_UInt8_20_io_deq_valid : _T_4676 ? _Queue16_UInt8_19_io_deq_valid : _T_4675 ? _Queue16_UInt8_18_io_deq_valid : _T_4674 ? _Queue16_UInt8_17_io_deq_valid : _T_4673 ? _Queue16_UInt8_16_io_deq_valid : _T_4672 ? _Queue16_UInt8_15_io_deq_valid : _T_4671 ? _Queue16_UInt8_14_io_deq_valid : _T_4670 ? _Queue16_UInt8_13_io_deq_valid : _T_4669 ? _Queue16_UInt8_12_io_deq_valid : _T_4668 ? _Queue16_UInt8_11_io_deq_valid : _T_4667 ? _Queue16_UInt8_10_io_deq_valid : _T_4666 ? _Queue16_UInt8_9_io_deq_valid : _T_4665 ? _Queue16_UInt8_8_io_deq_valid : _T_4664 ? _Queue16_UInt8_7_io_deq_valid : _T_4663 ? _Queue16_UInt8_6_io_deq_valid : _T_4662 ? _Queue16_UInt8_5_io_deq_valid : _T_4661 ? _Queue16_UInt8_4_io_deq_valid : _T_4660 ? _Queue16_UInt8_3_io_deq_valid : _T_4659 ? _Queue16_UInt8_2_io_deq_valid : _T_4658 ? _Queue16_UInt8_1_io_deq_valid : _T_4657 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_101 = _remapindex_T_11 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_11 = _GEN_101[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4689 = remapindex_11 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4690 = remapindex_11 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4691 = remapindex_11 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4692 = remapindex_11 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4693 = remapindex_11 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4694 = remapindex_11 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4695 = remapindex_11 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4696 = remapindex_11 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4697 = remapindex_11 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4698 = remapindex_11 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4699 = remapindex_11 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4700 = remapindex_11 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4701 = remapindex_11 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4702 = remapindex_11 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4703 = remapindex_11 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4704 = remapindex_11 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4705 = remapindex_11 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4706 = remapindex_11 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4707 = remapindex_11 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4708 = remapindex_11 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4709 = remapindex_11 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4710 = remapindex_11 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4711 = remapindex_11 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4712 = remapindex_11 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4713 = remapindex_11 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4714 = remapindex_11 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4715 = remapindex_11 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4716 = remapindex_11 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4717 = remapindex_11 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4718 = remapindex_11 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4719 = remapindex_11 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4720 = remapindex_11 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_bits : _T_4719 ? _Queue16_UInt8_30_io_deq_bits : _T_4718 ? _Queue16_UInt8_29_io_deq_bits : _T_4717 ? _Queue16_UInt8_28_io_deq_bits : _T_4716 ? _Queue16_UInt8_27_io_deq_bits : _T_4715 ? _Queue16_UInt8_26_io_deq_bits : _T_4714 ? _Queue16_UInt8_25_io_deq_bits : _T_4713 ? _Queue16_UInt8_24_io_deq_bits : _T_4712 ? _Queue16_UInt8_23_io_deq_bits : _T_4711 ? _Queue16_UInt8_22_io_deq_bits : _T_4710 ? _Queue16_UInt8_21_io_deq_bits : _T_4709 ? _Queue16_UInt8_20_io_deq_bits : _T_4708 ? _Queue16_UInt8_19_io_deq_bits : _T_4707 ? _Queue16_UInt8_18_io_deq_bits : _T_4706 ? _Queue16_UInt8_17_io_deq_bits : _T_4705 ? _Queue16_UInt8_16_io_deq_bits : _T_4704 ? _Queue16_UInt8_15_io_deq_bits : _T_4703 ? _Queue16_UInt8_14_io_deq_bits : _T_4702 ? _Queue16_UInt8_13_io_deq_bits : _T_4701 ? _Queue16_UInt8_12_io_deq_bits : _T_4700 ? _Queue16_UInt8_11_io_deq_bits : _T_4699 ? _Queue16_UInt8_10_io_deq_bits : _T_4698 ? _Queue16_UInt8_9_io_deq_bits : _T_4697 ? _Queue16_UInt8_8_io_deq_bits : _T_4696 ? _Queue16_UInt8_7_io_deq_bits : _T_4695 ? _Queue16_UInt8_6_io_deq_bits : _T_4694 ? _Queue16_UInt8_5_io_deq_bits : _T_4693 ? _Queue16_UInt8_4_io_deq_bits : _T_4692 ? _Queue16_UInt8_3_io_deq_bits : _T_4691 ? _Queue16_UInt8_2_io_deq_bits : _T_4690 ? _Queue16_UInt8_1_io_deq_bits : _T_4689 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_valid : _T_4719 ? _Queue16_UInt8_30_io_deq_valid : _T_4718 ? _Queue16_UInt8_29_io_deq_valid : _T_4717 ? _Queue16_UInt8_28_io_deq_valid : _T_4716 ? _Queue16_UInt8_27_io_deq_valid : _T_4715 ? _Queue16_UInt8_26_io_deq_valid : _T_4714 ? _Queue16_UInt8_25_io_deq_valid : _T_4713 ? _Queue16_UInt8_24_io_deq_valid : _T_4712 ? _Queue16_UInt8_23_io_deq_valid : _T_4711 ? _Queue16_UInt8_22_io_deq_valid : _T_4710 ? _Queue16_UInt8_21_io_deq_valid : _T_4709 ? _Queue16_UInt8_20_io_deq_valid : _T_4708 ? _Queue16_UInt8_19_io_deq_valid : _T_4707 ? _Queue16_UInt8_18_io_deq_valid : _T_4706 ? _Queue16_UInt8_17_io_deq_valid : _T_4705 ? _Queue16_UInt8_16_io_deq_valid : _T_4704 ? _Queue16_UInt8_15_io_deq_valid : _T_4703 ? _Queue16_UInt8_14_io_deq_valid : _T_4702 ? _Queue16_UInt8_13_io_deq_valid : _T_4701 ? _Queue16_UInt8_12_io_deq_valid : _T_4700 ? _Queue16_UInt8_11_io_deq_valid : _T_4699 ? _Queue16_UInt8_10_io_deq_valid : _T_4698 ? _Queue16_UInt8_9_io_deq_valid : _T_4697 ? _Queue16_UInt8_8_io_deq_valid : _T_4696 ? _Queue16_UInt8_7_io_deq_valid : _T_4695 ? _Queue16_UInt8_6_io_deq_valid : _T_4694 ? _Queue16_UInt8_5_io_deq_valid : _T_4693 ? _Queue16_UInt8_4_io_deq_valid : _T_4692 ? _Queue16_UInt8_3_io_deq_valid : _T_4691 ? _Queue16_UInt8_2_io_deq_valid : _T_4690 ? _Queue16_UInt8_1_io_deq_valid : _T_4689 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_102 = _remapindex_T_12 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_12 = _GEN_102[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4721 = remapindex_12 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4722 = remapindex_12 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4723 = remapindex_12 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4724 = remapindex_12 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4725 = remapindex_12 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4726 = remapindex_12 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4727 = remapindex_12 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4728 = remapindex_12 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4729 = remapindex_12 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4730 = remapindex_12 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4731 = remapindex_12 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4732 = remapindex_12 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4733 = remapindex_12 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4734 = remapindex_12 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4735 = remapindex_12 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4736 = remapindex_12 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4737 = remapindex_12 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4738 = remapindex_12 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4739 = remapindex_12 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4740 = remapindex_12 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4741 = remapindex_12 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4742 = remapindex_12 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4743 = remapindex_12 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4744 = remapindex_12 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4745 = remapindex_12 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4746 = remapindex_12 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4747 = remapindex_12 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4748 = remapindex_12 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4749 = remapindex_12 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4750 = remapindex_12 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4751 = remapindex_12 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4752 = remapindex_12 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_bits : _T_4751 ? _Queue16_UInt8_30_io_deq_bits : _T_4750 ? _Queue16_UInt8_29_io_deq_bits : _T_4749 ? _Queue16_UInt8_28_io_deq_bits : _T_4748 ? _Queue16_UInt8_27_io_deq_bits : _T_4747 ? _Queue16_UInt8_26_io_deq_bits : _T_4746 ? _Queue16_UInt8_25_io_deq_bits : _T_4745 ? _Queue16_UInt8_24_io_deq_bits : _T_4744 ? _Queue16_UInt8_23_io_deq_bits : _T_4743 ? _Queue16_UInt8_22_io_deq_bits : _T_4742 ? _Queue16_UInt8_21_io_deq_bits : _T_4741 ? _Queue16_UInt8_20_io_deq_bits : _T_4740 ? _Queue16_UInt8_19_io_deq_bits : _T_4739 ? _Queue16_UInt8_18_io_deq_bits : _T_4738 ? _Queue16_UInt8_17_io_deq_bits : _T_4737 ? _Queue16_UInt8_16_io_deq_bits : _T_4736 ? _Queue16_UInt8_15_io_deq_bits : _T_4735 ? _Queue16_UInt8_14_io_deq_bits : _T_4734 ? _Queue16_UInt8_13_io_deq_bits : _T_4733 ? _Queue16_UInt8_12_io_deq_bits : _T_4732 ? _Queue16_UInt8_11_io_deq_bits : _T_4731 ? _Queue16_UInt8_10_io_deq_bits : _T_4730 ? _Queue16_UInt8_9_io_deq_bits : _T_4729 ? _Queue16_UInt8_8_io_deq_bits : _T_4728 ? _Queue16_UInt8_7_io_deq_bits : _T_4727 ? _Queue16_UInt8_6_io_deq_bits : _T_4726 ? _Queue16_UInt8_5_io_deq_bits : _T_4725 ? _Queue16_UInt8_4_io_deq_bits : _T_4724 ? _Queue16_UInt8_3_io_deq_bits : _T_4723 ? _Queue16_UInt8_2_io_deq_bits : _T_4722 ? _Queue16_UInt8_1_io_deq_bits : _T_4721 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_valid : _T_4751 ? _Queue16_UInt8_30_io_deq_valid : _T_4750 ? _Queue16_UInt8_29_io_deq_valid : _T_4749 ? _Queue16_UInt8_28_io_deq_valid : _T_4748 ? _Queue16_UInt8_27_io_deq_valid : _T_4747 ? _Queue16_UInt8_26_io_deq_valid : _T_4746 ? _Queue16_UInt8_25_io_deq_valid : _T_4745 ? _Queue16_UInt8_24_io_deq_valid : _T_4744 ? _Queue16_UInt8_23_io_deq_valid : _T_4743 ? _Queue16_UInt8_22_io_deq_valid : _T_4742 ? _Queue16_UInt8_21_io_deq_valid : _T_4741 ? _Queue16_UInt8_20_io_deq_valid : _T_4740 ? _Queue16_UInt8_19_io_deq_valid : _T_4739 ? _Queue16_UInt8_18_io_deq_valid : _T_4738 ? _Queue16_UInt8_17_io_deq_valid : _T_4737 ? _Queue16_UInt8_16_io_deq_valid : _T_4736 ? _Queue16_UInt8_15_io_deq_valid : _T_4735 ? _Queue16_UInt8_14_io_deq_valid : _T_4734 ? _Queue16_UInt8_13_io_deq_valid : _T_4733 ? _Queue16_UInt8_12_io_deq_valid : _T_4732 ? _Queue16_UInt8_11_io_deq_valid : _T_4731 ? _Queue16_UInt8_10_io_deq_valid : _T_4730 ? _Queue16_UInt8_9_io_deq_valid : _T_4729 ? _Queue16_UInt8_8_io_deq_valid : _T_4728 ? _Queue16_UInt8_7_io_deq_valid : _T_4727 ? _Queue16_UInt8_6_io_deq_valid : _T_4726 ? _Queue16_UInt8_5_io_deq_valid : _T_4725 ? _Queue16_UInt8_4_io_deq_valid : _T_4724 ? _Queue16_UInt8_3_io_deq_valid : _T_4723 ? _Queue16_UInt8_2_io_deq_valid : _T_4722 ? _Queue16_UInt8_1_io_deq_valid : _T_4721 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_103 = _remapindex_T_13 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_13 = _GEN_103[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4753 = remapindex_13 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4754 = remapindex_13 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4755 = remapindex_13 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4756 = remapindex_13 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4757 = remapindex_13 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4758 = remapindex_13 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4759 = remapindex_13 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4760 = remapindex_13 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4761 = remapindex_13 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4762 = remapindex_13 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4763 = remapindex_13 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4764 = remapindex_13 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4765 = remapindex_13 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4766 = remapindex_13 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4767 = remapindex_13 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4768 = remapindex_13 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4769 = remapindex_13 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4770 = remapindex_13 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4771 = remapindex_13 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4772 = remapindex_13 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4773 = remapindex_13 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4774 = remapindex_13 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4775 = remapindex_13 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4776 = remapindex_13 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4777 = remapindex_13 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4778 = remapindex_13 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4779 = remapindex_13 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4780 = remapindex_13 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4781 = remapindex_13 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4782 = remapindex_13 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4783 = remapindex_13 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4784 = remapindex_13 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_bits : _T_4783 ? _Queue16_UInt8_30_io_deq_bits : _T_4782 ? _Queue16_UInt8_29_io_deq_bits : _T_4781 ? _Queue16_UInt8_28_io_deq_bits : _T_4780 ? _Queue16_UInt8_27_io_deq_bits : _T_4779 ? _Queue16_UInt8_26_io_deq_bits : _T_4778 ? _Queue16_UInt8_25_io_deq_bits : _T_4777 ? _Queue16_UInt8_24_io_deq_bits : _T_4776 ? _Queue16_UInt8_23_io_deq_bits : _T_4775 ? _Queue16_UInt8_22_io_deq_bits : _T_4774 ? _Queue16_UInt8_21_io_deq_bits : _T_4773 ? _Queue16_UInt8_20_io_deq_bits : _T_4772 ? _Queue16_UInt8_19_io_deq_bits : _T_4771 ? _Queue16_UInt8_18_io_deq_bits : _T_4770 ? _Queue16_UInt8_17_io_deq_bits : _T_4769 ? _Queue16_UInt8_16_io_deq_bits : _T_4768 ? _Queue16_UInt8_15_io_deq_bits : _T_4767 ? _Queue16_UInt8_14_io_deq_bits : _T_4766 ? _Queue16_UInt8_13_io_deq_bits : _T_4765 ? _Queue16_UInt8_12_io_deq_bits : _T_4764 ? _Queue16_UInt8_11_io_deq_bits : _T_4763 ? _Queue16_UInt8_10_io_deq_bits : _T_4762 ? _Queue16_UInt8_9_io_deq_bits : _T_4761 ? _Queue16_UInt8_8_io_deq_bits : _T_4760 ? _Queue16_UInt8_7_io_deq_bits : _T_4759 ? _Queue16_UInt8_6_io_deq_bits : _T_4758 ? _Queue16_UInt8_5_io_deq_bits : _T_4757 ? _Queue16_UInt8_4_io_deq_bits : _T_4756 ? _Queue16_UInt8_3_io_deq_bits : _T_4755 ? _Queue16_UInt8_2_io_deq_bits : _T_4754 ? _Queue16_UInt8_1_io_deq_bits : _T_4753 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_valid : _T_4783 ? _Queue16_UInt8_30_io_deq_valid : _T_4782 ? _Queue16_UInt8_29_io_deq_valid : _T_4781 ? _Queue16_UInt8_28_io_deq_valid : _T_4780 ? _Queue16_UInt8_27_io_deq_valid : _T_4779 ? _Queue16_UInt8_26_io_deq_valid : _T_4778 ? _Queue16_UInt8_25_io_deq_valid : _T_4777 ? _Queue16_UInt8_24_io_deq_valid : _T_4776 ? _Queue16_UInt8_23_io_deq_valid : _T_4775 ? _Queue16_UInt8_22_io_deq_valid : _T_4774 ? _Queue16_UInt8_21_io_deq_valid : _T_4773 ? _Queue16_UInt8_20_io_deq_valid : _T_4772 ? _Queue16_UInt8_19_io_deq_valid : _T_4771 ? _Queue16_UInt8_18_io_deq_valid : _T_4770 ? _Queue16_UInt8_17_io_deq_valid : _T_4769 ? _Queue16_UInt8_16_io_deq_valid : _T_4768 ? _Queue16_UInt8_15_io_deq_valid : _T_4767 ? _Queue16_UInt8_14_io_deq_valid : _T_4766 ? _Queue16_UInt8_13_io_deq_valid : _T_4765 ? _Queue16_UInt8_12_io_deq_valid : _T_4764 ? _Queue16_UInt8_11_io_deq_valid : _T_4763 ? _Queue16_UInt8_10_io_deq_valid : _T_4762 ? _Queue16_UInt8_9_io_deq_valid : _T_4761 ? _Queue16_UInt8_8_io_deq_valid : _T_4760 ? _Queue16_UInt8_7_io_deq_valid : _T_4759 ? _Queue16_UInt8_6_io_deq_valid : _T_4758 ? _Queue16_UInt8_5_io_deq_valid : _T_4757 ? _Queue16_UInt8_4_io_deq_valid : _T_4756 ? _Queue16_UInt8_3_io_deq_valid : _T_4755 ? _Queue16_UInt8_2_io_deq_valid : _T_4754 ? _Queue16_UInt8_1_io_deq_valid : _T_4753 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_104 = _remapindex_T_14 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_14 = _GEN_104[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4785 = remapindex_14 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4786 = remapindex_14 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4787 = remapindex_14 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4788 = remapindex_14 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4789 = remapindex_14 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4790 = remapindex_14 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4791 = remapindex_14 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4792 = remapindex_14 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4793 = remapindex_14 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4794 = remapindex_14 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4795 = remapindex_14 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4796 = remapindex_14 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4797 = remapindex_14 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4798 = remapindex_14 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4799 = remapindex_14 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4800 = remapindex_14 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4801 = remapindex_14 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4802 = remapindex_14 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4803 = remapindex_14 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4804 = remapindex_14 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4805 = remapindex_14 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4806 = remapindex_14 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4807 = remapindex_14 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4808 = remapindex_14 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4809 = remapindex_14 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4810 = remapindex_14 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4811 = remapindex_14 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4812 = remapindex_14 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4813 = remapindex_14 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4814 = remapindex_14 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4815 = remapindex_14 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4816 = remapindex_14 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_bits : _T_4815 ? _Queue16_UInt8_30_io_deq_bits : _T_4814 ? _Queue16_UInt8_29_io_deq_bits : _T_4813 ? _Queue16_UInt8_28_io_deq_bits : _T_4812 ? _Queue16_UInt8_27_io_deq_bits : _T_4811 ? _Queue16_UInt8_26_io_deq_bits : _T_4810 ? _Queue16_UInt8_25_io_deq_bits : _T_4809 ? _Queue16_UInt8_24_io_deq_bits : _T_4808 ? _Queue16_UInt8_23_io_deq_bits : _T_4807 ? _Queue16_UInt8_22_io_deq_bits : _T_4806 ? _Queue16_UInt8_21_io_deq_bits : _T_4805 ? _Queue16_UInt8_20_io_deq_bits : _T_4804 ? _Queue16_UInt8_19_io_deq_bits : _T_4803 ? _Queue16_UInt8_18_io_deq_bits : _T_4802 ? _Queue16_UInt8_17_io_deq_bits : _T_4801 ? _Queue16_UInt8_16_io_deq_bits : _T_4800 ? _Queue16_UInt8_15_io_deq_bits : _T_4799 ? _Queue16_UInt8_14_io_deq_bits : _T_4798 ? _Queue16_UInt8_13_io_deq_bits : _T_4797 ? _Queue16_UInt8_12_io_deq_bits : _T_4796 ? _Queue16_UInt8_11_io_deq_bits : _T_4795 ? _Queue16_UInt8_10_io_deq_bits : _T_4794 ? _Queue16_UInt8_9_io_deq_bits : _T_4793 ? _Queue16_UInt8_8_io_deq_bits : _T_4792 ? _Queue16_UInt8_7_io_deq_bits : _T_4791 ? _Queue16_UInt8_6_io_deq_bits : _T_4790 ? _Queue16_UInt8_5_io_deq_bits : _T_4789 ? _Queue16_UInt8_4_io_deq_bits : _T_4788 ? _Queue16_UInt8_3_io_deq_bits : _T_4787 ? _Queue16_UInt8_2_io_deq_bits : _T_4786 ? _Queue16_UInt8_1_io_deq_bits : _T_4785 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_valid : _T_4815 ? _Queue16_UInt8_30_io_deq_valid : _T_4814 ? _Queue16_UInt8_29_io_deq_valid : _T_4813 ? _Queue16_UInt8_28_io_deq_valid : _T_4812 ? _Queue16_UInt8_27_io_deq_valid : _T_4811 ? _Queue16_UInt8_26_io_deq_valid : _T_4810 ? _Queue16_UInt8_25_io_deq_valid : _T_4809 ? _Queue16_UInt8_24_io_deq_valid : _T_4808 ? _Queue16_UInt8_23_io_deq_valid : _T_4807 ? _Queue16_UInt8_22_io_deq_valid : _T_4806 ? _Queue16_UInt8_21_io_deq_valid : _T_4805 ? _Queue16_UInt8_20_io_deq_valid : _T_4804 ? _Queue16_UInt8_19_io_deq_valid : _T_4803 ? _Queue16_UInt8_18_io_deq_valid : _T_4802 ? _Queue16_UInt8_17_io_deq_valid : _T_4801 ? _Queue16_UInt8_16_io_deq_valid : _T_4800 ? _Queue16_UInt8_15_io_deq_valid : _T_4799 ? _Queue16_UInt8_14_io_deq_valid : _T_4798 ? _Queue16_UInt8_13_io_deq_valid : _T_4797 ? _Queue16_UInt8_12_io_deq_valid : _T_4796 ? _Queue16_UInt8_11_io_deq_valid : _T_4795 ? _Queue16_UInt8_10_io_deq_valid : _T_4794 ? _Queue16_UInt8_9_io_deq_valid : _T_4793 ? _Queue16_UInt8_8_io_deq_valid : _T_4792 ? _Queue16_UInt8_7_io_deq_valid : _T_4791 ? _Queue16_UInt8_6_io_deq_valid : _T_4790 ? _Queue16_UInt8_5_io_deq_valid : _T_4789 ? _Queue16_UInt8_4_io_deq_valid : _T_4788 ? _Queue16_UInt8_3_io_deq_valid : _T_4787 ? _Queue16_UInt8_2_io_deq_valid : _T_4786 ? _Queue16_UInt8_1_io_deq_valid : _T_4785 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_105 = _remapindex_T_15 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_15 = _GEN_105[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4817 = remapindex_15 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4818 = remapindex_15 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4819 = remapindex_15 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4820 = remapindex_15 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4821 = remapindex_15 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4822 = remapindex_15 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4823 = remapindex_15 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4824 = remapindex_15 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4825 = remapindex_15 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4826 = remapindex_15 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4827 = remapindex_15 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4828 = remapindex_15 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4829 = remapindex_15 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4830 = remapindex_15 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4831 = remapindex_15 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4832 = remapindex_15 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4833 = remapindex_15 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4834 = remapindex_15 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4835 = remapindex_15 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4836 = remapindex_15 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4837 = remapindex_15 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4838 = remapindex_15 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4839 = remapindex_15 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4840 = remapindex_15 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4841 = remapindex_15 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4842 = remapindex_15 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4843 = remapindex_15 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4844 = remapindex_15 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4845 = remapindex_15 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4846 = remapindex_15 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4847 = remapindex_15 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4848 = remapindex_15 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_bits : _T_4847 ? _Queue16_UInt8_30_io_deq_bits : _T_4846 ? _Queue16_UInt8_29_io_deq_bits : _T_4845 ? _Queue16_UInt8_28_io_deq_bits : _T_4844 ? _Queue16_UInt8_27_io_deq_bits : _T_4843 ? _Queue16_UInt8_26_io_deq_bits : _T_4842 ? _Queue16_UInt8_25_io_deq_bits : _T_4841 ? _Queue16_UInt8_24_io_deq_bits : _T_4840 ? _Queue16_UInt8_23_io_deq_bits : _T_4839 ? _Queue16_UInt8_22_io_deq_bits : _T_4838 ? _Queue16_UInt8_21_io_deq_bits : _T_4837 ? _Queue16_UInt8_20_io_deq_bits : _T_4836 ? _Queue16_UInt8_19_io_deq_bits : _T_4835 ? _Queue16_UInt8_18_io_deq_bits : _T_4834 ? _Queue16_UInt8_17_io_deq_bits : _T_4833 ? _Queue16_UInt8_16_io_deq_bits : _T_4832 ? _Queue16_UInt8_15_io_deq_bits : _T_4831 ? _Queue16_UInt8_14_io_deq_bits : _T_4830 ? _Queue16_UInt8_13_io_deq_bits : _T_4829 ? _Queue16_UInt8_12_io_deq_bits : _T_4828 ? _Queue16_UInt8_11_io_deq_bits : _T_4827 ? _Queue16_UInt8_10_io_deq_bits : _T_4826 ? _Queue16_UInt8_9_io_deq_bits : _T_4825 ? _Queue16_UInt8_8_io_deq_bits : _T_4824 ? _Queue16_UInt8_7_io_deq_bits : _T_4823 ? _Queue16_UInt8_6_io_deq_bits : _T_4822 ? _Queue16_UInt8_5_io_deq_bits : _T_4821 ? _Queue16_UInt8_4_io_deq_bits : _T_4820 ? _Queue16_UInt8_3_io_deq_bits : _T_4819 ? _Queue16_UInt8_2_io_deq_bits : _T_4818 ? _Queue16_UInt8_1_io_deq_bits : _T_4817 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_valid : _T_4847 ? _Queue16_UInt8_30_io_deq_valid : _T_4846 ? _Queue16_UInt8_29_io_deq_valid : _T_4845 ? _Queue16_UInt8_28_io_deq_valid : _T_4844 ? _Queue16_UInt8_27_io_deq_valid : _T_4843 ? _Queue16_UInt8_26_io_deq_valid : _T_4842 ? _Queue16_UInt8_25_io_deq_valid : _T_4841 ? _Queue16_UInt8_24_io_deq_valid : _T_4840 ? _Queue16_UInt8_23_io_deq_valid : _T_4839 ? _Queue16_UInt8_22_io_deq_valid : _T_4838 ? _Queue16_UInt8_21_io_deq_valid : _T_4837 ? _Queue16_UInt8_20_io_deq_valid : _T_4836 ? _Queue16_UInt8_19_io_deq_valid : _T_4835 ? _Queue16_UInt8_18_io_deq_valid : _T_4834 ? _Queue16_UInt8_17_io_deq_valid : _T_4833 ? _Queue16_UInt8_16_io_deq_valid : _T_4832 ? _Queue16_UInt8_15_io_deq_valid : _T_4831 ? _Queue16_UInt8_14_io_deq_valid : _T_4830 ? _Queue16_UInt8_13_io_deq_valid : _T_4829 ? _Queue16_UInt8_12_io_deq_valid : _T_4828 ? _Queue16_UInt8_11_io_deq_valid : _T_4827 ? _Queue16_UInt8_10_io_deq_valid : _T_4826 ? _Queue16_UInt8_9_io_deq_valid : _T_4825 ? _Queue16_UInt8_8_io_deq_valid : _T_4824 ? _Queue16_UInt8_7_io_deq_valid : _T_4823 ? _Queue16_UInt8_6_io_deq_valid : _T_4822 ? _Queue16_UInt8_5_io_deq_valid : _T_4821 ? _Queue16_UInt8_4_io_deq_valid : _T_4820 ? _Queue16_UInt8_3_io_deq_valid : _T_4819 ? _Queue16_UInt8_2_io_deq_valid : _T_4818 ? _Queue16_UInt8_1_io_deq_valid : _T_4817 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_106 = _remapindex_T_16 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_16 = _GEN_106[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4849 = remapindex_16 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4850 = remapindex_16 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4851 = remapindex_16 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4852 = remapindex_16 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4853 = remapindex_16 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4854 = remapindex_16 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4855 = remapindex_16 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4856 = remapindex_16 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4857 = remapindex_16 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4858 = remapindex_16 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4859 = remapindex_16 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4860 = remapindex_16 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4861 = remapindex_16 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4862 = remapindex_16 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4863 = remapindex_16 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4864 = remapindex_16 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4865 = remapindex_16 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4866 = remapindex_16 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4867 = remapindex_16 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4868 = remapindex_16 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4869 = remapindex_16 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4870 = remapindex_16 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4871 = remapindex_16 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4872 = remapindex_16 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4873 = remapindex_16 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4874 = remapindex_16 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4875 = remapindex_16 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4876 = remapindex_16 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4877 = remapindex_16 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4878 = remapindex_16 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4879 = remapindex_16 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4880 = remapindex_16 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_bits : _T_4879 ? _Queue16_UInt8_30_io_deq_bits : _T_4878 ? _Queue16_UInt8_29_io_deq_bits : _T_4877 ? _Queue16_UInt8_28_io_deq_bits : _T_4876 ? _Queue16_UInt8_27_io_deq_bits : _T_4875 ? _Queue16_UInt8_26_io_deq_bits : _T_4874 ? _Queue16_UInt8_25_io_deq_bits : _T_4873 ? _Queue16_UInt8_24_io_deq_bits : _T_4872 ? _Queue16_UInt8_23_io_deq_bits : _T_4871 ? _Queue16_UInt8_22_io_deq_bits : _T_4870 ? _Queue16_UInt8_21_io_deq_bits : _T_4869 ? _Queue16_UInt8_20_io_deq_bits : _T_4868 ? _Queue16_UInt8_19_io_deq_bits : _T_4867 ? _Queue16_UInt8_18_io_deq_bits : _T_4866 ? _Queue16_UInt8_17_io_deq_bits : _T_4865 ? _Queue16_UInt8_16_io_deq_bits : _T_4864 ? _Queue16_UInt8_15_io_deq_bits : _T_4863 ? _Queue16_UInt8_14_io_deq_bits : _T_4862 ? _Queue16_UInt8_13_io_deq_bits : _T_4861 ? _Queue16_UInt8_12_io_deq_bits : _T_4860 ? _Queue16_UInt8_11_io_deq_bits : _T_4859 ? _Queue16_UInt8_10_io_deq_bits : _T_4858 ? _Queue16_UInt8_9_io_deq_bits : _T_4857 ? _Queue16_UInt8_8_io_deq_bits : _T_4856 ? _Queue16_UInt8_7_io_deq_bits : _T_4855 ? _Queue16_UInt8_6_io_deq_bits : _T_4854 ? _Queue16_UInt8_5_io_deq_bits : _T_4853 ? _Queue16_UInt8_4_io_deq_bits : _T_4852 ? _Queue16_UInt8_3_io_deq_bits : _T_4851 ? _Queue16_UInt8_2_io_deq_bits : _T_4850 ? _Queue16_UInt8_1_io_deq_bits : _T_4849 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_valid : _T_4879 ? _Queue16_UInt8_30_io_deq_valid : _T_4878 ? _Queue16_UInt8_29_io_deq_valid : _T_4877 ? _Queue16_UInt8_28_io_deq_valid : _T_4876 ? _Queue16_UInt8_27_io_deq_valid : _T_4875 ? _Queue16_UInt8_26_io_deq_valid : _T_4874 ? _Queue16_UInt8_25_io_deq_valid : _T_4873 ? _Queue16_UInt8_24_io_deq_valid : _T_4872 ? _Queue16_UInt8_23_io_deq_valid : _T_4871 ? _Queue16_UInt8_22_io_deq_valid : _T_4870 ? _Queue16_UInt8_21_io_deq_valid : _T_4869 ? _Queue16_UInt8_20_io_deq_valid : _T_4868 ? _Queue16_UInt8_19_io_deq_valid : _T_4867 ? _Queue16_UInt8_18_io_deq_valid : _T_4866 ? _Queue16_UInt8_17_io_deq_valid : _T_4865 ? _Queue16_UInt8_16_io_deq_valid : _T_4864 ? _Queue16_UInt8_15_io_deq_valid : _T_4863 ? _Queue16_UInt8_14_io_deq_valid : _T_4862 ? _Queue16_UInt8_13_io_deq_valid : _T_4861 ? _Queue16_UInt8_12_io_deq_valid : _T_4860 ? _Queue16_UInt8_11_io_deq_valid : _T_4859 ? _Queue16_UInt8_10_io_deq_valid : _T_4858 ? _Queue16_UInt8_9_io_deq_valid : _T_4857 ? _Queue16_UInt8_8_io_deq_valid : _T_4856 ? _Queue16_UInt8_7_io_deq_valid : _T_4855 ? _Queue16_UInt8_6_io_deq_valid : _T_4854 ? _Queue16_UInt8_5_io_deq_valid : _T_4853 ? _Queue16_UInt8_4_io_deq_valid : _T_4852 ? _Queue16_UInt8_3_io_deq_valid : _T_4851 ? _Queue16_UInt8_2_io_deq_valid : _T_4850 ? _Queue16_UInt8_1_io_deq_valid : _T_4849 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_107 = _remapindex_T_17 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_17 = _GEN_107[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4881 = remapindex_17 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4882 = remapindex_17 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4883 = remapindex_17 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4884 = remapindex_17 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4885 = remapindex_17 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4886 = remapindex_17 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4887 = remapindex_17 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4888 = remapindex_17 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4889 = remapindex_17 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4890 = remapindex_17 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4891 = remapindex_17 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4892 = remapindex_17 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4893 = remapindex_17 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4894 = remapindex_17 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4895 = remapindex_17 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4896 = remapindex_17 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4897 = remapindex_17 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4898 = remapindex_17 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4899 = remapindex_17 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4900 = remapindex_17 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4901 = remapindex_17 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4902 = remapindex_17 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4903 = remapindex_17 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4904 = remapindex_17 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4905 = remapindex_17 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4906 = remapindex_17 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4907 = remapindex_17 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4908 = remapindex_17 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4909 = remapindex_17 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4910 = remapindex_17 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4911 = remapindex_17 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4912 = remapindex_17 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_bits : _T_4911 ? _Queue16_UInt8_30_io_deq_bits : _T_4910 ? _Queue16_UInt8_29_io_deq_bits : _T_4909 ? _Queue16_UInt8_28_io_deq_bits : _T_4908 ? _Queue16_UInt8_27_io_deq_bits : _T_4907 ? _Queue16_UInt8_26_io_deq_bits : _T_4906 ? _Queue16_UInt8_25_io_deq_bits : _T_4905 ? _Queue16_UInt8_24_io_deq_bits : _T_4904 ? _Queue16_UInt8_23_io_deq_bits : _T_4903 ? _Queue16_UInt8_22_io_deq_bits : _T_4902 ? _Queue16_UInt8_21_io_deq_bits : _T_4901 ? _Queue16_UInt8_20_io_deq_bits : _T_4900 ? _Queue16_UInt8_19_io_deq_bits : _T_4899 ? _Queue16_UInt8_18_io_deq_bits : _T_4898 ? _Queue16_UInt8_17_io_deq_bits : _T_4897 ? _Queue16_UInt8_16_io_deq_bits : _T_4896 ? _Queue16_UInt8_15_io_deq_bits : _T_4895 ? _Queue16_UInt8_14_io_deq_bits : _T_4894 ? _Queue16_UInt8_13_io_deq_bits : _T_4893 ? _Queue16_UInt8_12_io_deq_bits : _T_4892 ? _Queue16_UInt8_11_io_deq_bits : _T_4891 ? _Queue16_UInt8_10_io_deq_bits : _T_4890 ? _Queue16_UInt8_9_io_deq_bits : _T_4889 ? _Queue16_UInt8_8_io_deq_bits : _T_4888 ? _Queue16_UInt8_7_io_deq_bits : _T_4887 ? _Queue16_UInt8_6_io_deq_bits : _T_4886 ? _Queue16_UInt8_5_io_deq_bits : _T_4885 ? _Queue16_UInt8_4_io_deq_bits : _T_4884 ? _Queue16_UInt8_3_io_deq_bits : _T_4883 ? _Queue16_UInt8_2_io_deq_bits : _T_4882 ? _Queue16_UInt8_1_io_deq_bits : _T_4881 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_valid : _T_4911 ? _Queue16_UInt8_30_io_deq_valid : _T_4910 ? _Queue16_UInt8_29_io_deq_valid : _T_4909 ? _Queue16_UInt8_28_io_deq_valid : _T_4908 ? _Queue16_UInt8_27_io_deq_valid : _T_4907 ? _Queue16_UInt8_26_io_deq_valid : _T_4906 ? _Queue16_UInt8_25_io_deq_valid : _T_4905 ? _Queue16_UInt8_24_io_deq_valid : _T_4904 ? _Queue16_UInt8_23_io_deq_valid : _T_4903 ? _Queue16_UInt8_22_io_deq_valid : _T_4902 ? _Queue16_UInt8_21_io_deq_valid : _T_4901 ? _Queue16_UInt8_20_io_deq_valid : _T_4900 ? _Queue16_UInt8_19_io_deq_valid : _T_4899 ? _Queue16_UInt8_18_io_deq_valid : _T_4898 ? _Queue16_UInt8_17_io_deq_valid : _T_4897 ? _Queue16_UInt8_16_io_deq_valid : _T_4896 ? _Queue16_UInt8_15_io_deq_valid : _T_4895 ? _Queue16_UInt8_14_io_deq_valid : _T_4894 ? _Queue16_UInt8_13_io_deq_valid : _T_4893 ? _Queue16_UInt8_12_io_deq_valid : _T_4892 ? _Queue16_UInt8_11_io_deq_valid : _T_4891 ? _Queue16_UInt8_10_io_deq_valid : _T_4890 ? _Queue16_UInt8_9_io_deq_valid : _T_4889 ? _Queue16_UInt8_8_io_deq_valid : _T_4888 ? _Queue16_UInt8_7_io_deq_valid : _T_4887 ? _Queue16_UInt8_6_io_deq_valid : _T_4886 ? _Queue16_UInt8_5_io_deq_valid : _T_4885 ? _Queue16_UInt8_4_io_deq_valid : _T_4884 ? _Queue16_UInt8_3_io_deq_valid : _T_4883 ? _Queue16_UInt8_2_io_deq_valid : _T_4882 ? _Queue16_UInt8_1_io_deq_valid : _T_4881 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_108 = _remapindex_T_18 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_18 = _GEN_108[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4913 = remapindex_18 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4914 = remapindex_18 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4915 = remapindex_18 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4916 = remapindex_18 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4917 = remapindex_18 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4918 = remapindex_18 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4919 = remapindex_18 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4920 = remapindex_18 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4921 = remapindex_18 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4922 = remapindex_18 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4923 = remapindex_18 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4924 = remapindex_18 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4925 = remapindex_18 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4926 = remapindex_18 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4927 = remapindex_18 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4928 = remapindex_18 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4929 = remapindex_18 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4930 = remapindex_18 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4931 = remapindex_18 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4932 = remapindex_18 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4933 = remapindex_18 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4934 = remapindex_18 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4935 = remapindex_18 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4936 = remapindex_18 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4937 = remapindex_18 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4938 = remapindex_18 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4939 = remapindex_18 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4940 = remapindex_18 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4941 = remapindex_18 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4942 = remapindex_18 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4943 = remapindex_18 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4944 = remapindex_18 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_bits : _T_4943 ? _Queue16_UInt8_30_io_deq_bits : _T_4942 ? _Queue16_UInt8_29_io_deq_bits : _T_4941 ? _Queue16_UInt8_28_io_deq_bits : _T_4940 ? _Queue16_UInt8_27_io_deq_bits : _T_4939 ? _Queue16_UInt8_26_io_deq_bits : _T_4938 ? _Queue16_UInt8_25_io_deq_bits : _T_4937 ? _Queue16_UInt8_24_io_deq_bits : _T_4936 ? _Queue16_UInt8_23_io_deq_bits : _T_4935 ? _Queue16_UInt8_22_io_deq_bits : _T_4934 ? _Queue16_UInt8_21_io_deq_bits : _T_4933 ? _Queue16_UInt8_20_io_deq_bits : _T_4932 ? _Queue16_UInt8_19_io_deq_bits : _T_4931 ? _Queue16_UInt8_18_io_deq_bits : _T_4930 ? _Queue16_UInt8_17_io_deq_bits : _T_4929 ? _Queue16_UInt8_16_io_deq_bits : _T_4928 ? _Queue16_UInt8_15_io_deq_bits : _T_4927 ? _Queue16_UInt8_14_io_deq_bits : _T_4926 ? _Queue16_UInt8_13_io_deq_bits : _T_4925 ? _Queue16_UInt8_12_io_deq_bits : _T_4924 ? _Queue16_UInt8_11_io_deq_bits : _T_4923 ? _Queue16_UInt8_10_io_deq_bits : _T_4922 ? _Queue16_UInt8_9_io_deq_bits : _T_4921 ? _Queue16_UInt8_8_io_deq_bits : _T_4920 ? _Queue16_UInt8_7_io_deq_bits : _T_4919 ? _Queue16_UInt8_6_io_deq_bits : _T_4918 ? _Queue16_UInt8_5_io_deq_bits : _T_4917 ? _Queue16_UInt8_4_io_deq_bits : _T_4916 ? _Queue16_UInt8_3_io_deq_bits : _T_4915 ? _Queue16_UInt8_2_io_deq_bits : _T_4914 ? _Queue16_UInt8_1_io_deq_bits : _T_4913 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_valid : _T_4943 ? _Queue16_UInt8_30_io_deq_valid : _T_4942 ? _Queue16_UInt8_29_io_deq_valid : _T_4941 ? _Queue16_UInt8_28_io_deq_valid : _T_4940 ? _Queue16_UInt8_27_io_deq_valid : _T_4939 ? _Queue16_UInt8_26_io_deq_valid : _T_4938 ? _Queue16_UInt8_25_io_deq_valid : _T_4937 ? _Queue16_UInt8_24_io_deq_valid : _T_4936 ? _Queue16_UInt8_23_io_deq_valid : _T_4935 ? _Queue16_UInt8_22_io_deq_valid : _T_4934 ? _Queue16_UInt8_21_io_deq_valid : _T_4933 ? _Queue16_UInt8_20_io_deq_valid : _T_4932 ? _Queue16_UInt8_19_io_deq_valid : _T_4931 ? _Queue16_UInt8_18_io_deq_valid : _T_4930 ? _Queue16_UInt8_17_io_deq_valid : _T_4929 ? _Queue16_UInt8_16_io_deq_valid : _T_4928 ? _Queue16_UInt8_15_io_deq_valid : _T_4927 ? _Queue16_UInt8_14_io_deq_valid : _T_4926 ? _Queue16_UInt8_13_io_deq_valid : _T_4925 ? _Queue16_UInt8_12_io_deq_valid : _T_4924 ? _Queue16_UInt8_11_io_deq_valid : _T_4923 ? _Queue16_UInt8_10_io_deq_valid : _T_4922 ? _Queue16_UInt8_9_io_deq_valid : _T_4921 ? _Queue16_UInt8_8_io_deq_valid : _T_4920 ? _Queue16_UInt8_7_io_deq_valid : _T_4919 ? _Queue16_UInt8_6_io_deq_valid : _T_4918 ? _Queue16_UInt8_5_io_deq_valid : _T_4917 ? _Queue16_UInt8_4_io_deq_valid : _T_4916 ? _Queue16_UInt8_3_io_deq_valid : _T_4915 ? _Queue16_UInt8_2_io_deq_valid : _T_4914 ? _Queue16_UInt8_1_io_deq_valid : _T_4913 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_109 = _remapindex_T_19 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_19 = _GEN_109[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4945 = remapindex_19 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4946 = remapindex_19 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4947 = remapindex_19 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4948 = remapindex_19 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4949 = remapindex_19 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4950 = remapindex_19 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4951 = remapindex_19 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4952 = remapindex_19 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4953 = remapindex_19 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4954 = remapindex_19 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4955 = remapindex_19 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4956 = remapindex_19 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4957 = remapindex_19 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4958 = remapindex_19 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4959 = remapindex_19 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4960 = remapindex_19 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4961 = remapindex_19 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4962 = remapindex_19 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4963 = remapindex_19 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4964 = remapindex_19 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4965 = remapindex_19 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4966 = remapindex_19 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4967 = remapindex_19 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4968 = remapindex_19 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4969 = remapindex_19 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4970 = remapindex_19 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4971 = remapindex_19 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4972 = remapindex_19 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4973 = remapindex_19 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4974 = remapindex_19 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4975 = remapindex_19 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4976 = remapindex_19 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_bits : _T_4975 ? _Queue16_UInt8_30_io_deq_bits : _T_4974 ? _Queue16_UInt8_29_io_deq_bits : _T_4973 ? _Queue16_UInt8_28_io_deq_bits : _T_4972 ? _Queue16_UInt8_27_io_deq_bits : _T_4971 ? _Queue16_UInt8_26_io_deq_bits : _T_4970 ? _Queue16_UInt8_25_io_deq_bits : _T_4969 ? _Queue16_UInt8_24_io_deq_bits : _T_4968 ? _Queue16_UInt8_23_io_deq_bits : _T_4967 ? _Queue16_UInt8_22_io_deq_bits : _T_4966 ? _Queue16_UInt8_21_io_deq_bits : _T_4965 ? _Queue16_UInt8_20_io_deq_bits : _T_4964 ? _Queue16_UInt8_19_io_deq_bits : _T_4963 ? _Queue16_UInt8_18_io_deq_bits : _T_4962 ? _Queue16_UInt8_17_io_deq_bits : _T_4961 ? _Queue16_UInt8_16_io_deq_bits : _T_4960 ? _Queue16_UInt8_15_io_deq_bits : _T_4959 ? _Queue16_UInt8_14_io_deq_bits : _T_4958 ? _Queue16_UInt8_13_io_deq_bits : _T_4957 ? _Queue16_UInt8_12_io_deq_bits : _T_4956 ? _Queue16_UInt8_11_io_deq_bits : _T_4955 ? _Queue16_UInt8_10_io_deq_bits : _T_4954 ? _Queue16_UInt8_9_io_deq_bits : _T_4953 ? _Queue16_UInt8_8_io_deq_bits : _T_4952 ? _Queue16_UInt8_7_io_deq_bits : _T_4951 ? _Queue16_UInt8_6_io_deq_bits : _T_4950 ? _Queue16_UInt8_5_io_deq_bits : _T_4949 ? _Queue16_UInt8_4_io_deq_bits : _T_4948 ? _Queue16_UInt8_3_io_deq_bits : _T_4947 ? _Queue16_UInt8_2_io_deq_bits : _T_4946 ? _Queue16_UInt8_1_io_deq_bits : _T_4945 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_valid : _T_4975 ? _Queue16_UInt8_30_io_deq_valid : _T_4974 ? _Queue16_UInt8_29_io_deq_valid : _T_4973 ? _Queue16_UInt8_28_io_deq_valid : _T_4972 ? _Queue16_UInt8_27_io_deq_valid : _T_4971 ? _Queue16_UInt8_26_io_deq_valid : _T_4970 ? _Queue16_UInt8_25_io_deq_valid : _T_4969 ? _Queue16_UInt8_24_io_deq_valid : _T_4968 ? _Queue16_UInt8_23_io_deq_valid : _T_4967 ? _Queue16_UInt8_22_io_deq_valid : _T_4966 ? _Queue16_UInt8_21_io_deq_valid : _T_4965 ? _Queue16_UInt8_20_io_deq_valid : _T_4964 ? _Queue16_UInt8_19_io_deq_valid : _T_4963 ? _Queue16_UInt8_18_io_deq_valid : _T_4962 ? _Queue16_UInt8_17_io_deq_valid : _T_4961 ? _Queue16_UInt8_16_io_deq_valid : _T_4960 ? _Queue16_UInt8_15_io_deq_valid : _T_4959 ? _Queue16_UInt8_14_io_deq_valid : _T_4958 ? _Queue16_UInt8_13_io_deq_valid : _T_4957 ? _Queue16_UInt8_12_io_deq_valid : _T_4956 ? _Queue16_UInt8_11_io_deq_valid : _T_4955 ? _Queue16_UInt8_10_io_deq_valid : _T_4954 ? _Queue16_UInt8_9_io_deq_valid : _T_4953 ? _Queue16_UInt8_8_io_deq_valid : _T_4952 ? _Queue16_UInt8_7_io_deq_valid : _T_4951 ? _Queue16_UInt8_6_io_deq_valid : _T_4950 ? _Queue16_UInt8_5_io_deq_valid : _T_4949 ? _Queue16_UInt8_4_io_deq_valid : _T_4948 ? _Queue16_UInt8_3_io_deq_valid : _T_4947 ? _Queue16_UInt8_2_io_deq_valid : _T_4946 ? _Queue16_UInt8_1_io_deq_valid : _T_4945 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_110 = _remapindex_T_20 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_20 = _GEN_110[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4977 = remapindex_20 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4978 = remapindex_20 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4979 = remapindex_20 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4980 = remapindex_20 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4981 = remapindex_20 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4982 = remapindex_20 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4983 = remapindex_20 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4984 = remapindex_20 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4985 = remapindex_20 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4986 = remapindex_20 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4987 = remapindex_20 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4988 = remapindex_20 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4989 = remapindex_20 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4990 = remapindex_20 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4991 = remapindex_20 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4992 = remapindex_20 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4993 = remapindex_20 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4994 = remapindex_20 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4995 = remapindex_20 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4996 = remapindex_20 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4997 = remapindex_20 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4998 = remapindex_20 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4999 = remapindex_20 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5000 = remapindex_20 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5001 = remapindex_20 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5002 = remapindex_20 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5003 = remapindex_20 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5004 = remapindex_20 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5005 = remapindex_20 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5006 = remapindex_20 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5007 = remapindex_20 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5008 = remapindex_20 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_bits : _T_5007 ? _Queue16_UInt8_30_io_deq_bits : _T_5006 ? _Queue16_UInt8_29_io_deq_bits : _T_5005 ? _Queue16_UInt8_28_io_deq_bits : _T_5004 ? _Queue16_UInt8_27_io_deq_bits : _T_5003 ? _Queue16_UInt8_26_io_deq_bits : _T_5002 ? _Queue16_UInt8_25_io_deq_bits : _T_5001 ? _Queue16_UInt8_24_io_deq_bits : _T_5000 ? _Queue16_UInt8_23_io_deq_bits : _T_4999 ? _Queue16_UInt8_22_io_deq_bits : _T_4998 ? _Queue16_UInt8_21_io_deq_bits : _T_4997 ? _Queue16_UInt8_20_io_deq_bits : _T_4996 ? _Queue16_UInt8_19_io_deq_bits : _T_4995 ? _Queue16_UInt8_18_io_deq_bits : _T_4994 ? _Queue16_UInt8_17_io_deq_bits : _T_4993 ? _Queue16_UInt8_16_io_deq_bits : _T_4992 ? _Queue16_UInt8_15_io_deq_bits : _T_4991 ? _Queue16_UInt8_14_io_deq_bits : _T_4990 ? _Queue16_UInt8_13_io_deq_bits : _T_4989 ? _Queue16_UInt8_12_io_deq_bits : _T_4988 ? _Queue16_UInt8_11_io_deq_bits : _T_4987 ? _Queue16_UInt8_10_io_deq_bits : _T_4986 ? _Queue16_UInt8_9_io_deq_bits : _T_4985 ? _Queue16_UInt8_8_io_deq_bits : _T_4984 ? _Queue16_UInt8_7_io_deq_bits : _T_4983 ? _Queue16_UInt8_6_io_deq_bits : _T_4982 ? _Queue16_UInt8_5_io_deq_bits : _T_4981 ? _Queue16_UInt8_4_io_deq_bits : _T_4980 ? _Queue16_UInt8_3_io_deq_bits : _T_4979 ? _Queue16_UInt8_2_io_deq_bits : _T_4978 ? _Queue16_UInt8_1_io_deq_bits : _T_4977 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_valid : _T_5007 ? _Queue16_UInt8_30_io_deq_valid : _T_5006 ? _Queue16_UInt8_29_io_deq_valid : _T_5005 ? _Queue16_UInt8_28_io_deq_valid : _T_5004 ? _Queue16_UInt8_27_io_deq_valid : _T_5003 ? _Queue16_UInt8_26_io_deq_valid : _T_5002 ? _Queue16_UInt8_25_io_deq_valid : _T_5001 ? _Queue16_UInt8_24_io_deq_valid : _T_5000 ? _Queue16_UInt8_23_io_deq_valid : _T_4999 ? _Queue16_UInt8_22_io_deq_valid : _T_4998 ? _Queue16_UInt8_21_io_deq_valid : _T_4997 ? _Queue16_UInt8_20_io_deq_valid : _T_4996 ? _Queue16_UInt8_19_io_deq_valid : _T_4995 ? _Queue16_UInt8_18_io_deq_valid : _T_4994 ? _Queue16_UInt8_17_io_deq_valid : _T_4993 ? _Queue16_UInt8_16_io_deq_valid : _T_4992 ? _Queue16_UInt8_15_io_deq_valid : _T_4991 ? _Queue16_UInt8_14_io_deq_valid : _T_4990 ? _Queue16_UInt8_13_io_deq_valid : _T_4989 ? _Queue16_UInt8_12_io_deq_valid : _T_4988 ? _Queue16_UInt8_11_io_deq_valid : _T_4987 ? _Queue16_UInt8_10_io_deq_valid : _T_4986 ? _Queue16_UInt8_9_io_deq_valid : _T_4985 ? _Queue16_UInt8_8_io_deq_valid : _T_4984 ? _Queue16_UInt8_7_io_deq_valid : _T_4983 ? _Queue16_UInt8_6_io_deq_valid : _T_4982 ? _Queue16_UInt8_5_io_deq_valid : _T_4981 ? _Queue16_UInt8_4_io_deq_valid : _T_4980 ? _Queue16_UInt8_3_io_deq_valid : _T_4979 ? _Queue16_UInt8_2_io_deq_valid : _T_4978 ? _Queue16_UInt8_1_io_deq_valid : _T_4977 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_111 = _remapindex_T_21 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_21 = _GEN_111[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5009 = remapindex_21 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5010 = remapindex_21 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5011 = remapindex_21 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5012 = remapindex_21 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5013 = remapindex_21 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5014 = remapindex_21 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5015 = remapindex_21 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5016 = remapindex_21 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5017 = remapindex_21 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5018 = remapindex_21 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5019 = remapindex_21 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5020 = remapindex_21 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5021 = remapindex_21 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5022 = remapindex_21 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5023 = remapindex_21 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5024 = remapindex_21 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5025 = remapindex_21 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5026 = remapindex_21 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5027 = remapindex_21 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5028 = remapindex_21 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5029 = remapindex_21 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5030 = remapindex_21 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5031 = remapindex_21 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5032 = remapindex_21 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5033 = remapindex_21 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5034 = remapindex_21 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5035 = remapindex_21 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5036 = remapindex_21 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5037 = remapindex_21 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5038 = remapindex_21 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5039 = remapindex_21 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5040 = remapindex_21 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_bits : _T_5039 ? _Queue16_UInt8_30_io_deq_bits : _T_5038 ? _Queue16_UInt8_29_io_deq_bits : _T_5037 ? _Queue16_UInt8_28_io_deq_bits : _T_5036 ? _Queue16_UInt8_27_io_deq_bits : _T_5035 ? _Queue16_UInt8_26_io_deq_bits : _T_5034 ? _Queue16_UInt8_25_io_deq_bits : _T_5033 ? _Queue16_UInt8_24_io_deq_bits : _T_5032 ? _Queue16_UInt8_23_io_deq_bits : _T_5031 ? _Queue16_UInt8_22_io_deq_bits : _T_5030 ? _Queue16_UInt8_21_io_deq_bits : _T_5029 ? _Queue16_UInt8_20_io_deq_bits : _T_5028 ? _Queue16_UInt8_19_io_deq_bits : _T_5027 ? _Queue16_UInt8_18_io_deq_bits : _T_5026 ? _Queue16_UInt8_17_io_deq_bits : _T_5025 ? _Queue16_UInt8_16_io_deq_bits : _T_5024 ? _Queue16_UInt8_15_io_deq_bits : _T_5023 ? _Queue16_UInt8_14_io_deq_bits : _T_5022 ? _Queue16_UInt8_13_io_deq_bits : _T_5021 ? _Queue16_UInt8_12_io_deq_bits : _T_5020 ? _Queue16_UInt8_11_io_deq_bits : _T_5019 ? _Queue16_UInt8_10_io_deq_bits : _T_5018 ? _Queue16_UInt8_9_io_deq_bits : _T_5017 ? _Queue16_UInt8_8_io_deq_bits : _T_5016 ? _Queue16_UInt8_7_io_deq_bits : _T_5015 ? _Queue16_UInt8_6_io_deq_bits : _T_5014 ? _Queue16_UInt8_5_io_deq_bits : _T_5013 ? _Queue16_UInt8_4_io_deq_bits : _T_5012 ? _Queue16_UInt8_3_io_deq_bits : _T_5011 ? _Queue16_UInt8_2_io_deq_bits : _T_5010 ? _Queue16_UInt8_1_io_deq_bits : _T_5009 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_valid : _T_5039 ? _Queue16_UInt8_30_io_deq_valid : _T_5038 ? _Queue16_UInt8_29_io_deq_valid : _T_5037 ? _Queue16_UInt8_28_io_deq_valid : _T_5036 ? _Queue16_UInt8_27_io_deq_valid : _T_5035 ? _Queue16_UInt8_26_io_deq_valid : _T_5034 ? _Queue16_UInt8_25_io_deq_valid : _T_5033 ? _Queue16_UInt8_24_io_deq_valid : _T_5032 ? _Queue16_UInt8_23_io_deq_valid : _T_5031 ? _Queue16_UInt8_22_io_deq_valid : _T_5030 ? _Queue16_UInt8_21_io_deq_valid : _T_5029 ? _Queue16_UInt8_20_io_deq_valid : _T_5028 ? _Queue16_UInt8_19_io_deq_valid : _T_5027 ? _Queue16_UInt8_18_io_deq_valid : _T_5026 ? _Queue16_UInt8_17_io_deq_valid : _T_5025 ? _Queue16_UInt8_16_io_deq_valid : _T_5024 ? _Queue16_UInt8_15_io_deq_valid : _T_5023 ? _Queue16_UInt8_14_io_deq_valid : _T_5022 ? _Queue16_UInt8_13_io_deq_valid : _T_5021 ? _Queue16_UInt8_12_io_deq_valid : _T_5020 ? _Queue16_UInt8_11_io_deq_valid : _T_5019 ? _Queue16_UInt8_10_io_deq_valid : _T_5018 ? _Queue16_UInt8_9_io_deq_valid : _T_5017 ? _Queue16_UInt8_8_io_deq_valid : _T_5016 ? _Queue16_UInt8_7_io_deq_valid : _T_5015 ? _Queue16_UInt8_6_io_deq_valid : _T_5014 ? _Queue16_UInt8_5_io_deq_valid : _T_5013 ? _Queue16_UInt8_4_io_deq_valid : _T_5012 ? _Queue16_UInt8_3_io_deq_valid : _T_5011 ? _Queue16_UInt8_2_io_deq_valid : _T_5010 ? _Queue16_UInt8_1_io_deq_valid : _T_5009 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_112 = _remapindex_T_22 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_22 = _GEN_112[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5041 = remapindex_22 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5042 = remapindex_22 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5043 = remapindex_22 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5044 = remapindex_22 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5045 = remapindex_22 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5046 = remapindex_22 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5047 = remapindex_22 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5048 = remapindex_22 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5049 = remapindex_22 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5050 = remapindex_22 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5051 = remapindex_22 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5052 = remapindex_22 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5053 = remapindex_22 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5054 = remapindex_22 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5055 = remapindex_22 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5056 = remapindex_22 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5057 = remapindex_22 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5058 = remapindex_22 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5059 = remapindex_22 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5060 = remapindex_22 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5061 = remapindex_22 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5062 = remapindex_22 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5063 = remapindex_22 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5064 = remapindex_22 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5065 = remapindex_22 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5066 = remapindex_22 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5067 = remapindex_22 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5068 = remapindex_22 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5069 = remapindex_22 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5070 = remapindex_22 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5071 = remapindex_22 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5072 = remapindex_22 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_bits : _T_5071 ? _Queue16_UInt8_30_io_deq_bits : _T_5070 ? _Queue16_UInt8_29_io_deq_bits : _T_5069 ? _Queue16_UInt8_28_io_deq_bits : _T_5068 ? _Queue16_UInt8_27_io_deq_bits : _T_5067 ? _Queue16_UInt8_26_io_deq_bits : _T_5066 ? _Queue16_UInt8_25_io_deq_bits : _T_5065 ? _Queue16_UInt8_24_io_deq_bits : _T_5064 ? _Queue16_UInt8_23_io_deq_bits : _T_5063 ? _Queue16_UInt8_22_io_deq_bits : _T_5062 ? _Queue16_UInt8_21_io_deq_bits : _T_5061 ? _Queue16_UInt8_20_io_deq_bits : _T_5060 ? _Queue16_UInt8_19_io_deq_bits : _T_5059 ? _Queue16_UInt8_18_io_deq_bits : _T_5058 ? _Queue16_UInt8_17_io_deq_bits : _T_5057 ? _Queue16_UInt8_16_io_deq_bits : _T_5056 ? _Queue16_UInt8_15_io_deq_bits : _T_5055 ? _Queue16_UInt8_14_io_deq_bits : _T_5054 ? _Queue16_UInt8_13_io_deq_bits : _T_5053 ? _Queue16_UInt8_12_io_deq_bits : _T_5052 ? _Queue16_UInt8_11_io_deq_bits : _T_5051 ? _Queue16_UInt8_10_io_deq_bits : _T_5050 ? _Queue16_UInt8_9_io_deq_bits : _T_5049 ? _Queue16_UInt8_8_io_deq_bits : _T_5048 ? _Queue16_UInt8_7_io_deq_bits : _T_5047 ? _Queue16_UInt8_6_io_deq_bits : _T_5046 ? _Queue16_UInt8_5_io_deq_bits : _T_5045 ? _Queue16_UInt8_4_io_deq_bits : _T_5044 ? _Queue16_UInt8_3_io_deq_bits : _T_5043 ? _Queue16_UInt8_2_io_deq_bits : _T_5042 ? _Queue16_UInt8_1_io_deq_bits : _T_5041 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_valid : _T_5071 ? _Queue16_UInt8_30_io_deq_valid : _T_5070 ? _Queue16_UInt8_29_io_deq_valid : _T_5069 ? _Queue16_UInt8_28_io_deq_valid : _T_5068 ? _Queue16_UInt8_27_io_deq_valid : _T_5067 ? _Queue16_UInt8_26_io_deq_valid : _T_5066 ? _Queue16_UInt8_25_io_deq_valid : _T_5065 ? _Queue16_UInt8_24_io_deq_valid : _T_5064 ? _Queue16_UInt8_23_io_deq_valid : _T_5063 ? _Queue16_UInt8_22_io_deq_valid : _T_5062 ? _Queue16_UInt8_21_io_deq_valid : _T_5061 ? _Queue16_UInt8_20_io_deq_valid : _T_5060 ? _Queue16_UInt8_19_io_deq_valid : _T_5059 ? _Queue16_UInt8_18_io_deq_valid : _T_5058 ? _Queue16_UInt8_17_io_deq_valid : _T_5057 ? _Queue16_UInt8_16_io_deq_valid : _T_5056 ? _Queue16_UInt8_15_io_deq_valid : _T_5055 ? _Queue16_UInt8_14_io_deq_valid : _T_5054 ? _Queue16_UInt8_13_io_deq_valid : _T_5053 ? _Queue16_UInt8_12_io_deq_valid : _T_5052 ? _Queue16_UInt8_11_io_deq_valid : _T_5051 ? _Queue16_UInt8_10_io_deq_valid : _T_5050 ? _Queue16_UInt8_9_io_deq_valid : _T_5049 ? _Queue16_UInt8_8_io_deq_valid : _T_5048 ? _Queue16_UInt8_7_io_deq_valid : _T_5047 ? _Queue16_UInt8_6_io_deq_valid : _T_5046 ? _Queue16_UInt8_5_io_deq_valid : _T_5045 ? _Queue16_UInt8_4_io_deq_valid : _T_5044 ? _Queue16_UInt8_3_io_deq_valid : _T_5043 ? _Queue16_UInt8_2_io_deq_valid : _T_5042 ? _Queue16_UInt8_1_io_deq_valid : _T_5041 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_113 = _remapindex_T_23 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_23 = _GEN_113[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5073 = remapindex_23 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5074 = remapindex_23 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5075 = remapindex_23 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5076 = remapindex_23 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5077 = remapindex_23 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5078 = remapindex_23 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5079 = remapindex_23 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5080 = remapindex_23 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5081 = remapindex_23 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5082 = remapindex_23 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5083 = remapindex_23 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5084 = remapindex_23 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5085 = remapindex_23 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5086 = remapindex_23 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5087 = remapindex_23 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5088 = remapindex_23 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5089 = remapindex_23 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5090 = remapindex_23 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5091 = remapindex_23 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5092 = remapindex_23 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5093 = remapindex_23 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5094 = remapindex_23 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5095 = remapindex_23 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5096 = remapindex_23 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5097 = remapindex_23 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5098 = remapindex_23 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5099 = remapindex_23 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5100 = remapindex_23 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5101 = remapindex_23 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5102 = remapindex_23 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5103 = remapindex_23 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5104 = remapindex_23 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_bits : _T_5103 ? _Queue16_UInt8_30_io_deq_bits : _T_5102 ? _Queue16_UInt8_29_io_deq_bits : _T_5101 ? _Queue16_UInt8_28_io_deq_bits : _T_5100 ? _Queue16_UInt8_27_io_deq_bits : _T_5099 ? _Queue16_UInt8_26_io_deq_bits : _T_5098 ? _Queue16_UInt8_25_io_deq_bits : _T_5097 ? _Queue16_UInt8_24_io_deq_bits : _T_5096 ? _Queue16_UInt8_23_io_deq_bits : _T_5095 ? _Queue16_UInt8_22_io_deq_bits : _T_5094 ? _Queue16_UInt8_21_io_deq_bits : _T_5093 ? _Queue16_UInt8_20_io_deq_bits : _T_5092 ? _Queue16_UInt8_19_io_deq_bits : _T_5091 ? _Queue16_UInt8_18_io_deq_bits : _T_5090 ? _Queue16_UInt8_17_io_deq_bits : _T_5089 ? _Queue16_UInt8_16_io_deq_bits : _T_5088 ? _Queue16_UInt8_15_io_deq_bits : _T_5087 ? _Queue16_UInt8_14_io_deq_bits : _T_5086 ? _Queue16_UInt8_13_io_deq_bits : _T_5085 ? _Queue16_UInt8_12_io_deq_bits : _T_5084 ? _Queue16_UInt8_11_io_deq_bits : _T_5083 ? _Queue16_UInt8_10_io_deq_bits : _T_5082 ? _Queue16_UInt8_9_io_deq_bits : _T_5081 ? _Queue16_UInt8_8_io_deq_bits : _T_5080 ? _Queue16_UInt8_7_io_deq_bits : _T_5079 ? _Queue16_UInt8_6_io_deq_bits : _T_5078 ? _Queue16_UInt8_5_io_deq_bits : _T_5077 ? _Queue16_UInt8_4_io_deq_bits : _T_5076 ? _Queue16_UInt8_3_io_deq_bits : _T_5075 ? _Queue16_UInt8_2_io_deq_bits : _T_5074 ? _Queue16_UInt8_1_io_deq_bits : _T_5073 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_valid : _T_5103 ? _Queue16_UInt8_30_io_deq_valid : _T_5102 ? _Queue16_UInt8_29_io_deq_valid : _T_5101 ? _Queue16_UInt8_28_io_deq_valid : _T_5100 ? _Queue16_UInt8_27_io_deq_valid : _T_5099 ? _Queue16_UInt8_26_io_deq_valid : _T_5098 ? _Queue16_UInt8_25_io_deq_valid : _T_5097 ? _Queue16_UInt8_24_io_deq_valid : _T_5096 ? _Queue16_UInt8_23_io_deq_valid : _T_5095 ? _Queue16_UInt8_22_io_deq_valid : _T_5094 ? _Queue16_UInt8_21_io_deq_valid : _T_5093 ? _Queue16_UInt8_20_io_deq_valid : _T_5092 ? _Queue16_UInt8_19_io_deq_valid : _T_5091 ? _Queue16_UInt8_18_io_deq_valid : _T_5090 ? _Queue16_UInt8_17_io_deq_valid : _T_5089 ? _Queue16_UInt8_16_io_deq_valid : _T_5088 ? _Queue16_UInt8_15_io_deq_valid : _T_5087 ? _Queue16_UInt8_14_io_deq_valid : _T_5086 ? _Queue16_UInt8_13_io_deq_valid : _T_5085 ? _Queue16_UInt8_12_io_deq_valid : _T_5084 ? _Queue16_UInt8_11_io_deq_valid : _T_5083 ? _Queue16_UInt8_10_io_deq_valid : _T_5082 ? _Queue16_UInt8_9_io_deq_valid : _T_5081 ? _Queue16_UInt8_8_io_deq_valid : _T_5080 ? _Queue16_UInt8_7_io_deq_valid : _T_5079 ? _Queue16_UInt8_6_io_deq_valid : _T_5078 ? _Queue16_UInt8_5_io_deq_valid : _T_5077 ? _Queue16_UInt8_4_io_deq_valid : _T_5076 ? _Queue16_UInt8_3_io_deq_valid : _T_5075 ? _Queue16_UInt8_2_io_deq_valid : _T_5074 ? _Queue16_UInt8_1_io_deq_valid : _T_5073 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_114 = _remapindex_T_24 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_24 = _GEN_114[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5105 = remapindex_24 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5106 = remapindex_24 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5107 = remapindex_24 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5108 = remapindex_24 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5109 = remapindex_24 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5110 = remapindex_24 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5111 = remapindex_24 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5112 = remapindex_24 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5113 = remapindex_24 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5114 = remapindex_24 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5115 = remapindex_24 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5116 = remapindex_24 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5117 = remapindex_24 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5118 = remapindex_24 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5119 = remapindex_24 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5120 = remapindex_24 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5121 = remapindex_24 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5122 = remapindex_24 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5123 = remapindex_24 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5124 = remapindex_24 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5125 = remapindex_24 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5126 = remapindex_24 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5127 = remapindex_24 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5128 = remapindex_24 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5129 = remapindex_24 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5130 = remapindex_24 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5131 = remapindex_24 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5132 = remapindex_24 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5133 = remapindex_24 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5134 = remapindex_24 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5135 = remapindex_24 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5136 = remapindex_24 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_bits : _T_5135 ? _Queue16_UInt8_30_io_deq_bits : _T_5134 ? _Queue16_UInt8_29_io_deq_bits : _T_5133 ? _Queue16_UInt8_28_io_deq_bits : _T_5132 ? _Queue16_UInt8_27_io_deq_bits : _T_5131 ? _Queue16_UInt8_26_io_deq_bits : _T_5130 ? _Queue16_UInt8_25_io_deq_bits : _T_5129 ? _Queue16_UInt8_24_io_deq_bits : _T_5128 ? _Queue16_UInt8_23_io_deq_bits : _T_5127 ? _Queue16_UInt8_22_io_deq_bits : _T_5126 ? _Queue16_UInt8_21_io_deq_bits : _T_5125 ? _Queue16_UInt8_20_io_deq_bits : _T_5124 ? _Queue16_UInt8_19_io_deq_bits : _T_5123 ? _Queue16_UInt8_18_io_deq_bits : _T_5122 ? _Queue16_UInt8_17_io_deq_bits : _T_5121 ? _Queue16_UInt8_16_io_deq_bits : _T_5120 ? _Queue16_UInt8_15_io_deq_bits : _T_5119 ? _Queue16_UInt8_14_io_deq_bits : _T_5118 ? _Queue16_UInt8_13_io_deq_bits : _T_5117 ? _Queue16_UInt8_12_io_deq_bits : _T_5116 ? _Queue16_UInt8_11_io_deq_bits : _T_5115 ? _Queue16_UInt8_10_io_deq_bits : _T_5114 ? _Queue16_UInt8_9_io_deq_bits : _T_5113 ? _Queue16_UInt8_8_io_deq_bits : _T_5112 ? _Queue16_UInt8_7_io_deq_bits : _T_5111 ? _Queue16_UInt8_6_io_deq_bits : _T_5110 ? _Queue16_UInt8_5_io_deq_bits : _T_5109 ? _Queue16_UInt8_4_io_deq_bits : _T_5108 ? _Queue16_UInt8_3_io_deq_bits : _T_5107 ? _Queue16_UInt8_2_io_deq_bits : _T_5106 ? _Queue16_UInt8_1_io_deq_bits : _T_5105 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_valid : _T_5135 ? _Queue16_UInt8_30_io_deq_valid : _T_5134 ? _Queue16_UInt8_29_io_deq_valid : _T_5133 ? _Queue16_UInt8_28_io_deq_valid : _T_5132 ? _Queue16_UInt8_27_io_deq_valid : _T_5131 ? _Queue16_UInt8_26_io_deq_valid : _T_5130 ? _Queue16_UInt8_25_io_deq_valid : _T_5129 ? _Queue16_UInt8_24_io_deq_valid : _T_5128 ? _Queue16_UInt8_23_io_deq_valid : _T_5127 ? _Queue16_UInt8_22_io_deq_valid : _T_5126 ? _Queue16_UInt8_21_io_deq_valid : _T_5125 ? _Queue16_UInt8_20_io_deq_valid : _T_5124 ? _Queue16_UInt8_19_io_deq_valid : _T_5123 ? _Queue16_UInt8_18_io_deq_valid : _T_5122 ? _Queue16_UInt8_17_io_deq_valid : _T_5121 ? _Queue16_UInt8_16_io_deq_valid : _T_5120 ? _Queue16_UInt8_15_io_deq_valid : _T_5119 ? _Queue16_UInt8_14_io_deq_valid : _T_5118 ? _Queue16_UInt8_13_io_deq_valid : _T_5117 ? _Queue16_UInt8_12_io_deq_valid : _T_5116 ? _Queue16_UInt8_11_io_deq_valid : _T_5115 ? _Queue16_UInt8_10_io_deq_valid : _T_5114 ? _Queue16_UInt8_9_io_deq_valid : _T_5113 ? _Queue16_UInt8_8_io_deq_valid : _T_5112 ? _Queue16_UInt8_7_io_deq_valid : _T_5111 ? _Queue16_UInt8_6_io_deq_valid : _T_5110 ? _Queue16_UInt8_5_io_deq_valid : _T_5109 ? _Queue16_UInt8_4_io_deq_valid : _T_5108 ? _Queue16_UInt8_3_io_deq_valid : _T_5107 ? _Queue16_UInt8_2_io_deq_valid : _T_5106 ? _Queue16_UInt8_1_io_deq_valid : _T_5105 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_115 = _remapindex_T_25 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_25 = _GEN_115[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5137 = remapindex_25 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5138 = remapindex_25 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5139 = remapindex_25 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5140 = remapindex_25 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5141 = remapindex_25 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5142 = remapindex_25 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5143 = remapindex_25 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5144 = remapindex_25 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5145 = remapindex_25 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5146 = remapindex_25 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5147 = remapindex_25 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5148 = remapindex_25 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5149 = remapindex_25 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5150 = remapindex_25 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5151 = remapindex_25 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5152 = remapindex_25 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5153 = remapindex_25 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5154 = remapindex_25 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5155 = remapindex_25 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5156 = remapindex_25 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5157 = remapindex_25 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5158 = remapindex_25 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5159 = remapindex_25 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5160 = remapindex_25 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5161 = remapindex_25 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5162 = remapindex_25 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5163 = remapindex_25 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5164 = remapindex_25 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5165 = remapindex_25 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5166 = remapindex_25 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5167 = remapindex_25 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5168 = remapindex_25 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_bits : _T_5167 ? _Queue16_UInt8_30_io_deq_bits : _T_5166 ? _Queue16_UInt8_29_io_deq_bits : _T_5165 ? _Queue16_UInt8_28_io_deq_bits : _T_5164 ? _Queue16_UInt8_27_io_deq_bits : _T_5163 ? _Queue16_UInt8_26_io_deq_bits : _T_5162 ? _Queue16_UInt8_25_io_deq_bits : _T_5161 ? _Queue16_UInt8_24_io_deq_bits : _T_5160 ? _Queue16_UInt8_23_io_deq_bits : _T_5159 ? _Queue16_UInt8_22_io_deq_bits : _T_5158 ? _Queue16_UInt8_21_io_deq_bits : _T_5157 ? _Queue16_UInt8_20_io_deq_bits : _T_5156 ? _Queue16_UInt8_19_io_deq_bits : _T_5155 ? _Queue16_UInt8_18_io_deq_bits : _T_5154 ? _Queue16_UInt8_17_io_deq_bits : _T_5153 ? _Queue16_UInt8_16_io_deq_bits : _T_5152 ? _Queue16_UInt8_15_io_deq_bits : _T_5151 ? _Queue16_UInt8_14_io_deq_bits : _T_5150 ? _Queue16_UInt8_13_io_deq_bits : _T_5149 ? _Queue16_UInt8_12_io_deq_bits : _T_5148 ? _Queue16_UInt8_11_io_deq_bits : _T_5147 ? _Queue16_UInt8_10_io_deq_bits : _T_5146 ? _Queue16_UInt8_9_io_deq_bits : _T_5145 ? _Queue16_UInt8_8_io_deq_bits : _T_5144 ? _Queue16_UInt8_7_io_deq_bits : _T_5143 ? _Queue16_UInt8_6_io_deq_bits : _T_5142 ? _Queue16_UInt8_5_io_deq_bits : _T_5141 ? _Queue16_UInt8_4_io_deq_bits : _T_5140 ? _Queue16_UInt8_3_io_deq_bits : _T_5139 ? _Queue16_UInt8_2_io_deq_bits : _T_5138 ? _Queue16_UInt8_1_io_deq_bits : _T_5137 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_valid : _T_5167 ? _Queue16_UInt8_30_io_deq_valid : _T_5166 ? _Queue16_UInt8_29_io_deq_valid : _T_5165 ? _Queue16_UInt8_28_io_deq_valid : _T_5164 ? _Queue16_UInt8_27_io_deq_valid : _T_5163 ? _Queue16_UInt8_26_io_deq_valid : _T_5162 ? _Queue16_UInt8_25_io_deq_valid : _T_5161 ? _Queue16_UInt8_24_io_deq_valid : _T_5160 ? _Queue16_UInt8_23_io_deq_valid : _T_5159 ? _Queue16_UInt8_22_io_deq_valid : _T_5158 ? _Queue16_UInt8_21_io_deq_valid : _T_5157 ? _Queue16_UInt8_20_io_deq_valid : _T_5156 ? _Queue16_UInt8_19_io_deq_valid : _T_5155 ? _Queue16_UInt8_18_io_deq_valid : _T_5154 ? _Queue16_UInt8_17_io_deq_valid : _T_5153 ? _Queue16_UInt8_16_io_deq_valid : _T_5152 ? _Queue16_UInt8_15_io_deq_valid : _T_5151 ? _Queue16_UInt8_14_io_deq_valid : _T_5150 ? _Queue16_UInt8_13_io_deq_valid : _T_5149 ? _Queue16_UInt8_12_io_deq_valid : _T_5148 ? _Queue16_UInt8_11_io_deq_valid : _T_5147 ? _Queue16_UInt8_10_io_deq_valid : _T_5146 ? _Queue16_UInt8_9_io_deq_valid : _T_5145 ? _Queue16_UInt8_8_io_deq_valid : _T_5144 ? _Queue16_UInt8_7_io_deq_valid : _T_5143 ? _Queue16_UInt8_6_io_deq_valid : _T_5142 ? _Queue16_UInt8_5_io_deq_valid : _T_5141 ? _Queue16_UInt8_4_io_deq_valid : _T_5140 ? _Queue16_UInt8_3_io_deq_valid : _T_5139 ? _Queue16_UInt8_2_io_deq_valid : _T_5138 ? _Queue16_UInt8_1_io_deq_valid : _T_5137 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_116 = _remapindex_T_26 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_26 = _GEN_116[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5169 = remapindex_26 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5170 = remapindex_26 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5171 = remapindex_26 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5172 = remapindex_26 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5173 = remapindex_26 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5174 = remapindex_26 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5175 = remapindex_26 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5176 = remapindex_26 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5177 = remapindex_26 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5178 = remapindex_26 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5179 = remapindex_26 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5180 = remapindex_26 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5181 = remapindex_26 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5182 = remapindex_26 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5183 = remapindex_26 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5184 = remapindex_26 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5185 = remapindex_26 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5186 = remapindex_26 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5187 = remapindex_26 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5188 = remapindex_26 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5189 = remapindex_26 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5190 = remapindex_26 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5191 = remapindex_26 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5192 = remapindex_26 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5193 = remapindex_26 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5194 = remapindex_26 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5195 = remapindex_26 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5196 = remapindex_26 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5197 = remapindex_26 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5198 = remapindex_26 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5199 = remapindex_26 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5200 = remapindex_26 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_bits : _T_5199 ? _Queue16_UInt8_30_io_deq_bits : _T_5198 ? _Queue16_UInt8_29_io_deq_bits : _T_5197 ? _Queue16_UInt8_28_io_deq_bits : _T_5196 ? _Queue16_UInt8_27_io_deq_bits : _T_5195 ? _Queue16_UInt8_26_io_deq_bits : _T_5194 ? _Queue16_UInt8_25_io_deq_bits : _T_5193 ? _Queue16_UInt8_24_io_deq_bits : _T_5192 ? _Queue16_UInt8_23_io_deq_bits : _T_5191 ? _Queue16_UInt8_22_io_deq_bits : _T_5190 ? _Queue16_UInt8_21_io_deq_bits : _T_5189 ? _Queue16_UInt8_20_io_deq_bits : _T_5188 ? _Queue16_UInt8_19_io_deq_bits : _T_5187 ? _Queue16_UInt8_18_io_deq_bits : _T_5186 ? _Queue16_UInt8_17_io_deq_bits : _T_5185 ? _Queue16_UInt8_16_io_deq_bits : _T_5184 ? _Queue16_UInt8_15_io_deq_bits : _T_5183 ? _Queue16_UInt8_14_io_deq_bits : _T_5182 ? _Queue16_UInt8_13_io_deq_bits : _T_5181 ? _Queue16_UInt8_12_io_deq_bits : _T_5180 ? _Queue16_UInt8_11_io_deq_bits : _T_5179 ? _Queue16_UInt8_10_io_deq_bits : _T_5178 ? _Queue16_UInt8_9_io_deq_bits : _T_5177 ? _Queue16_UInt8_8_io_deq_bits : _T_5176 ? _Queue16_UInt8_7_io_deq_bits : _T_5175 ? _Queue16_UInt8_6_io_deq_bits : _T_5174 ? _Queue16_UInt8_5_io_deq_bits : _T_5173 ? _Queue16_UInt8_4_io_deq_bits : _T_5172 ? _Queue16_UInt8_3_io_deq_bits : _T_5171 ? _Queue16_UInt8_2_io_deq_bits : _T_5170 ? _Queue16_UInt8_1_io_deq_bits : _T_5169 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_valid : _T_5199 ? _Queue16_UInt8_30_io_deq_valid : _T_5198 ? _Queue16_UInt8_29_io_deq_valid : _T_5197 ? _Queue16_UInt8_28_io_deq_valid : _T_5196 ? _Queue16_UInt8_27_io_deq_valid : _T_5195 ? _Queue16_UInt8_26_io_deq_valid : _T_5194 ? _Queue16_UInt8_25_io_deq_valid : _T_5193 ? _Queue16_UInt8_24_io_deq_valid : _T_5192 ? _Queue16_UInt8_23_io_deq_valid : _T_5191 ? _Queue16_UInt8_22_io_deq_valid : _T_5190 ? _Queue16_UInt8_21_io_deq_valid : _T_5189 ? _Queue16_UInt8_20_io_deq_valid : _T_5188 ? _Queue16_UInt8_19_io_deq_valid : _T_5187 ? _Queue16_UInt8_18_io_deq_valid : _T_5186 ? _Queue16_UInt8_17_io_deq_valid : _T_5185 ? _Queue16_UInt8_16_io_deq_valid : _T_5184 ? _Queue16_UInt8_15_io_deq_valid : _T_5183 ? _Queue16_UInt8_14_io_deq_valid : _T_5182 ? _Queue16_UInt8_13_io_deq_valid : _T_5181 ? _Queue16_UInt8_12_io_deq_valid : _T_5180 ? _Queue16_UInt8_11_io_deq_valid : _T_5179 ? _Queue16_UInt8_10_io_deq_valid : _T_5178 ? _Queue16_UInt8_9_io_deq_valid : _T_5177 ? _Queue16_UInt8_8_io_deq_valid : _T_5176 ? _Queue16_UInt8_7_io_deq_valid : _T_5175 ? _Queue16_UInt8_6_io_deq_valid : _T_5174 ? _Queue16_UInt8_5_io_deq_valid : _T_5173 ? _Queue16_UInt8_4_io_deq_valid : _T_5172 ? _Queue16_UInt8_3_io_deq_valid : _T_5171 ? _Queue16_UInt8_2_io_deq_valid : _T_5170 ? _Queue16_UInt8_1_io_deq_valid : _T_5169 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_117 = _remapindex_T_27 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_27 = _GEN_117[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5201 = remapindex_27 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5202 = remapindex_27 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5203 = remapindex_27 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5204 = remapindex_27 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5205 = remapindex_27 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5206 = remapindex_27 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5207 = remapindex_27 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5208 = remapindex_27 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5209 = remapindex_27 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5210 = remapindex_27 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5211 = remapindex_27 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5212 = remapindex_27 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5213 = remapindex_27 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5214 = remapindex_27 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5215 = remapindex_27 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5216 = remapindex_27 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5217 = remapindex_27 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5218 = remapindex_27 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5219 = remapindex_27 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5220 = remapindex_27 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5221 = remapindex_27 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5222 = remapindex_27 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5223 = remapindex_27 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5224 = remapindex_27 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5225 = remapindex_27 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5226 = remapindex_27 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5227 = remapindex_27 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5228 = remapindex_27 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5229 = remapindex_27 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5230 = remapindex_27 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5231 = remapindex_27 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5232 = remapindex_27 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_bits : _T_5231 ? _Queue16_UInt8_30_io_deq_bits : _T_5230 ? _Queue16_UInt8_29_io_deq_bits : _T_5229 ? _Queue16_UInt8_28_io_deq_bits : _T_5228 ? _Queue16_UInt8_27_io_deq_bits : _T_5227 ? _Queue16_UInt8_26_io_deq_bits : _T_5226 ? _Queue16_UInt8_25_io_deq_bits : _T_5225 ? _Queue16_UInt8_24_io_deq_bits : _T_5224 ? _Queue16_UInt8_23_io_deq_bits : _T_5223 ? _Queue16_UInt8_22_io_deq_bits : _T_5222 ? _Queue16_UInt8_21_io_deq_bits : _T_5221 ? _Queue16_UInt8_20_io_deq_bits : _T_5220 ? _Queue16_UInt8_19_io_deq_bits : _T_5219 ? _Queue16_UInt8_18_io_deq_bits : _T_5218 ? _Queue16_UInt8_17_io_deq_bits : _T_5217 ? _Queue16_UInt8_16_io_deq_bits : _T_5216 ? _Queue16_UInt8_15_io_deq_bits : _T_5215 ? _Queue16_UInt8_14_io_deq_bits : _T_5214 ? _Queue16_UInt8_13_io_deq_bits : _T_5213 ? _Queue16_UInt8_12_io_deq_bits : _T_5212 ? _Queue16_UInt8_11_io_deq_bits : _T_5211 ? _Queue16_UInt8_10_io_deq_bits : _T_5210 ? _Queue16_UInt8_9_io_deq_bits : _T_5209 ? _Queue16_UInt8_8_io_deq_bits : _T_5208 ? _Queue16_UInt8_7_io_deq_bits : _T_5207 ? _Queue16_UInt8_6_io_deq_bits : _T_5206 ? _Queue16_UInt8_5_io_deq_bits : _T_5205 ? _Queue16_UInt8_4_io_deq_bits : _T_5204 ? _Queue16_UInt8_3_io_deq_bits : _T_5203 ? _Queue16_UInt8_2_io_deq_bits : _T_5202 ? _Queue16_UInt8_1_io_deq_bits : _T_5201 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_valid : _T_5231 ? _Queue16_UInt8_30_io_deq_valid : _T_5230 ? _Queue16_UInt8_29_io_deq_valid : _T_5229 ? _Queue16_UInt8_28_io_deq_valid : _T_5228 ? _Queue16_UInt8_27_io_deq_valid : _T_5227 ? _Queue16_UInt8_26_io_deq_valid : _T_5226 ? _Queue16_UInt8_25_io_deq_valid : _T_5225 ? _Queue16_UInt8_24_io_deq_valid : _T_5224 ? _Queue16_UInt8_23_io_deq_valid : _T_5223 ? _Queue16_UInt8_22_io_deq_valid : _T_5222 ? _Queue16_UInt8_21_io_deq_valid : _T_5221 ? _Queue16_UInt8_20_io_deq_valid : _T_5220 ? _Queue16_UInt8_19_io_deq_valid : _T_5219 ? _Queue16_UInt8_18_io_deq_valid : _T_5218 ? _Queue16_UInt8_17_io_deq_valid : _T_5217 ? _Queue16_UInt8_16_io_deq_valid : _T_5216 ? _Queue16_UInt8_15_io_deq_valid : _T_5215 ? _Queue16_UInt8_14_io_deq_valid : _T_5214 ? _Queue16_UInt8_13_io_deq_valid : _T_5213 ? _Queue16_UInt8_12_io_deq_valid : _T_5212 ? _Queue16_UInt8_11_io_deq_valid : _T_5211 ? _Queue16_UInt8_10_io_deq_valid : _T_5210 ? _Queue16_UInt8_9_io_deq_valid : _T_5209 ? _Queue16_UInt8_8_io_deq_valid : _T_5208 ? _Queue16_UInt8_7_io_deq_valid : _T_5207 ? _Queue16_UInt8_6_io_deq_valid : _T_5206 ? _Queue16_UInt8_5_io_deq_valid : _T_5205 ? _Queue16_UInt8_4_io_deq_valid : _T_5204 ? _Queue16_UInt8_3_io_deq_valid : _T_5203 ? _Queue16_UInt8_2_io_deq_valid : _T_5202 ? _Queue16_UInt8_1_io_deq_valid : _T_5201 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_118 = _remapindex_T_28 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_28 = _GEN_118[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5233 = remapindex_28 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5234 = remapindex_28 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5235 = remapindex_28 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5236 = remapindex_28 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5237 = remapindex_28 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5238 = remapindex_28 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5239 = remapindex_28 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5240 = remapindex_28 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5241 = remapindex_28 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5242 = remapindex_28 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5243 = remapindex_28 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5244 = remapindex_28 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5245 = remapindex_28 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5246 = remapindex_28 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5247 = remapindex_28 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5248 = remapindex_28 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5249 = remapindex_28 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5250 = remapindex_28 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5251 = remapindex_28 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5252 = remapindex_28 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5253 = remapindex_28 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5254 = remapindex_28 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5255 = remapindex_28 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5256 = remapindex_28 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5257 = remapindex_28 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5258 = remapindex_28 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5259 = remapindex_28 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5260 = remapindex_28 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5261 = remapindex_28 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5262 = remapindex_28 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5263 = remapindex_28 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5264 = remapindex_28 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_bits : _T_5263 ? _Queue16_UInt8_30_io_deq_bits : _T_5262 ? _Queue16_UInt8_29_io_deq_bits : _T_5261 ? _Queue16_UInt8_28_io_deq_bits : _T_5260 ? _Queue16_UInt8_27_io_deq_bits : _T_5259 ? _Queue16_UInt8_26_io_deq_bits : _T_5258 ? _Queue16_UInt8_25_io_deq_bits : _T_5257 ? _Queue16_UInt8_24_io_deq_bits : _T_5256 ? _Queue16_UInt8_23_io_deq_bits : _T_5255 ? _Queue16_UInt8_22_io_deq_bits : _T_5254 ? _Queue16_UInt8_21_io_deq_bits : _T_5253 ? _Queue16_UInt8_20_io_deq_bits : _T_5252 ? _Queue16_UInt8_19_io_deq_bits : _T_5251 ? _Queue16_UInt8_18_io_deq_bits : _T_5250 ? _Queue16_UInt8_17_io_deq_bits : _T_5249 ? _Queue16_UInt8_16_io_deq_bits : _T_5248 ? _Queue16_UInt8_15_io_deq_bits : _T_5247 ? _Queue16_UInt8_14_io_deq_bits : _T_5246 ? _Queue16_UInt8_13_io_deq_bits : _T_5245 ? _Queue16_UInt8_12_io_deq_bits : _T_5244 ? _Queue16_UInt8_11_io_deq_bits : _T_5243 ? _Queue16_UInt8_10_io_deq_bits : _T_5242 ? _Queue16_UInt8_9_io_deq_bits : _T_5241 ? _Queue16_UInt8_8_io_deq_bits : _T_5240 ? _Queue16_UInt8_7_io_deq_bits : _T_5239 ? _Queue16_UInt8_6_io_deq_bits : _T_5238 ? _Queue16_UInt8_5_io_deq_bits : _T_5237 ? _Queue16_UInt8_4_io_deq_bits : _T_5236 ? _Queue16_UInt8_3_io_deq_bits : _T_5235 ? _Queue16_UInt8_2_io_deq_bits : _T_5234 ? _Queue16_UInt8_1_io_deq_bits : _T_5233 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_valid : _T_5263 ? _Queue16_UInt8_30_io_deq_valid : _T_5262 ? _Queue16_UInt8_29_io_deq_valid : _T_5261 ? _Queue16_UInt8_28_io_deq_valid : _T_5260 ? _Queue16_UInt8_27_io_deq_valid : _T_5259 ? _Queue16_UInt8_26_io_deq_valid : _T_5258 ? _Queue16_UInt8_25_io_deq_valid : _T_5257 ? _Queue16_UInt8_24_io_deq_valid : _T_5256 ? _Queue16_UInt8_23_io_deq_valid : _T_5255 ? _Queue16_UInt8_22_io_deq_valid : _T_5254 ? _Queue16_UInt8_21_io_deq_valid : _T_5253 ? _Queue16_UInt8_20_io_deq_valid : _T_5252 ? _Queue16_UInt8_19_io_deq_valid : _T_5251 ? _Queue16_UInt8_18_io_deq_valid : _T_5250 ? _Queue16_UInt8_17_io_deq_valid : _T_5249 ? _Queue16_UInt8_16_io_deq_valid : _T_5248 ? _Queue16_UInt8_15_io_deq_valid : _T_5247 ? _Queue16_UInt8_14_io_deq_valid : _T_5246 ? _Queue16_UInt8_13_io_deq_valid : _T_5245 ? _Queue16_UInt8_12_io_deq_valid : _T_5244 ? _Queue16_UInt8_11_io_deq_valid : _T_5243 ? _Queue16_UInt8_10_io_deq_valid : _T_5242 ? _Queue16_UInt8_9_io_deq_valid : _T_5241 ? _Queue16_UInt8_8_io_deq_valid : _T_5240 ? _Queue16_UInt8_7_io_deq_valid : _T_5239 ? _Queue16_UInt8_6_io_deq_valid : _T_5238 ? _Queue16_UInt8_5_io_deq_valid : _T_5237 ? _Queue16_UInt8_4_io_deq_valid : _T_5236 ? _Queue16_UInt8_3_io_deq_valid : _T_5235 ? _Queue16_UInt8_2_io_deq_valid : _T_5234 ? _Queue16_UInt8_1_io_deq_valid : _T_5233 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_119 = _remapindex_T_29 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_29 = _GEN_119[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5265 = remapindex_29 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5266 = remapindex_29 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5267 = remapindex_29 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5268 = remapindex_29 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5269 = remapindex_29 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5270 = remapindex_29 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5271 = remapindex_29 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5272 = remapindex_29 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5273 = remapindex_29 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5274 = remapindex_29 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5275 = remapindex_29 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5276 = remapindex_29 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5277 = remapindex_29 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5278 = remapindex_29 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5279 = remapindex_29 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5280 = remapindex_29 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5281 = remapindex_29 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5282 = remapindex_29 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5283 = remapindex_29 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5284 = remapindex_29 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5285 = remapindex_29 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5286 = remapindex_29 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5287 = remapindex_29 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5288 = remapindex_29 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5289 = remapindex_29 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5290 = remapindex_29 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5291 = remapindex_29 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5292 = remapindex_29 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5293 = remapindex_29 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5294 = remapindex_29 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5295 = remapindex_29 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5296 = remapindex_29 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_bits : _T_5295 ? _Queue16_UInt8_30_io_deq_bits : _T_5294 ? _Queue16_UInt8_29_io_deq_bits : _T_5293 ? _Queue16_UInt8_28_io_deq_bits : _T_5292 ? _Queue16_UInt8_27_io_deq_bits : _T_5291 ? _Queue16_UInt8_26_io_deq_bits : _T_5290 ? _Queue16_UInt8_25_io_deq_bits : _T_5289 ? _Queue16_UInt8_24_io_deq_bits : _T_5288 ? _Queue16_UInt8_23_io_deq_bits : _T_5287 ? _Queue16_UInt8_22_io_deq_bits : _T_5286 ? _Queue16_UInt8_21_io_deq_bits : _T_5285 ? _Queue16_UInt8_20_io_deq_bits : _T_5284 ? _Queue16_UInt8_19_io_deq_bits : _T_5283 ? _Queue16_UInt8_18_io_deq_bits : _T_5282 ? _Queue16_UInt8_17_io_deq_bits : _T_5281 ? _Queue16_UInt8_16_io_deq_bits : _T_5280 ? _Queue16_UInt8_15_io_deq_bits : _T_5279 ? _Queue16_UInt8_14_io_deq_bits : _T_5278 ? _Queue16_UInt8_13_io_deq_bits : _T_5277 ? _Queue16_UInt8_12_io_deq_bits : _T_5276 ? _Queue16_UInt8_11_io_deq_bits : _T_5275 ? _Queue16_UInt8_10_io_deq_bits : _T_5274 ? _Queue16_UInt8_9_io_deq_bits : _T_5273 ? _Queue16_UInt8_8_io_deq_bits : _T_5272 ? _Queue16_UInt8_7_io_deq_bits : _T_5271 ? _Queue16_UInt8_6_io_deq_bits : _T_5270 ? _Queue16_UInt8_5_io_deq_bits : _T_5269 ? _Queue16_UInt8_4_io_deq_bits : _T_5268 ? _Queue16_UInt8_3_io_deq_bits : _T_5267 ? _Queue16_UInt8_2_io_deq_bits : _T_5266 ? _Queue16_UInt8_1_io_deq_bits : _T_5265 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_valid : _T_5295 ? _Queue16_UInt8_30_io_deq_valid : _T_5294 ? _Queue16_UInt8_29_io_deq_valid : _T_5293 ? _Queue16_UInt8_28_io_deq_valid : _T_5292 ? _Queue16_UInt8_27_io_deq_valid : _T_5291 ? _Queue16_UInt8_26_io_deq_valid : _T_5290 ? _Queue16_UInt8_25_io_deq_valid : _T_5289 ? _Queue16_UInt8_24_io_deq_valid : _T_5288 ? _Queue16_UInt8_23_io_deq_valid : _T_5287 ? _Queue16_UInt8_22_io_deq_valid : _T_5286 ? _Queue16_UInt8_21_io_deq_valid : _T_5285 ? _Queue16_UInt8_20_io_deq_valid : _T_5284 ? _Queue16_UInt8_19_io_deq_valid : _T_5283 ? _Queue16_UInt8_18_io_deq_valid : _T_5282 ? _Queue16_UInt8_17_io_deq_valid : _T_5281 ? _Queue16_UInt8_16_io_deq_valid : _T_5280 ? _Queue16_UInt8_15_io_deq_valid : _T_5279 ? _Queue16_UInt8_14_io_deq_valid : _T_5278 ? _Queue16_UInt8_13_io_deq_valid : _T_5277 ? _Queue16_UInt8_12_io_deq_valid : _T_5276 ? _Queue16_UInt8_11_io_deq_valid : _T_5275 ? _Queue16_UInt8_10_io_deq_valid : _T_5274 ? _Queue16_UInt8_9_io_deq_valid : _T_5273 ? _Queue16_UInt8_8_io_deq_valid : _T_5272 ? _Queue16_UInt8_7_io_deq_valid : _T_5271 ? _Queue16_UInt8_6_io_deq_valid : _T_5270 ? _Queue16_UInt8_5_io_deq_valid : _T_5269 ? _Queue16_UInt8_4_io_deq_valid : _T_5268 ? _Queue16_UInt8_3_io_deq_valid : _T_5267 ? _Queue16_UInt8_2_io_deq_valid : _T_5266 ? _Queue16_UInt8_1_io_deq_valid : _T_5265 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_120 = _remapindex_T_30 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_30 = _GEN_120[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5297 = remapindex_30 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5298 = remapindex_30 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5299 = remapindex_30 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5300 = remapindex_30 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5301 = remapindex_30 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5302 = remapindex_30 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5303 = remapindex_30 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5304 = remapindex_30 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5305 = remapindex_30 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5306 = remapindex_30 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5307 = remapindex_30 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5308 = remapindex_30 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5309 = remapindex_30 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5310 = remapindex_30 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5311 = remapindex_30 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5312 = remapindex_30 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5313 = remapindex_30 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5314 = remapindex_30 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5315 = remapindex_30 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5316 = remapindex_30 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5317 = remapindex_30 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5318 = remapindex_30 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5319 = remapindex_30 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5320 = remapindex_30 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5321 = remapindex_30 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5322 = remapindex_30 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5323 = remapindex_30 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5324 = remapindex_30 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5325 = remapindex_30 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5326 = remapindex_30 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5327 = remapindex_30 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5328 = remapindex_30 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_bits : _T_5327 ? _Queue16_UInt8_30_io_deq_bits : _T_5326 ? _Queue16_UInt8_29_io_deq_bits : _T_5325 ? _Queue16_UInt8_28_io_deq_bits : _T_5324 ? _Queue16_UInt8_27_io_deq_bits : _T_5323 ? _Queue16_UInt8_26_io_deq_bits : _T_5322 ? _Queue16_UInt8_25_io_deq_bits : _T_5321 ? _Queue16_UInt8_24_io_deq_bits : _T_5320 ? _Queue16_UInt8_23_io_deq_bits : _T_5319 ? _Queue16_UInt8_22_io_deq_bits : _T_5318 ? _Queue16_UInt8_21_io_deq_bits : _T_5317 ? _Queue16_UInt8_20_io_deq_bits : _T_5316 ? _Queue16_UInt8_19_io_deq_bits : _T_5315 ? _Queue16_UInt8_18_io_deq_bits : _T_5314 ? _Queue16_UInt8_17_io_deq_bits : _T_5313 ? _Queue16_UInt8_16_io_deq_bits : _T_5312 ? _Queue16_UInt8_15_io_deq_bits : _T_5311 ? _Queue16_UInt8_14_io_deq_bits : _T_5310 ? _Queue16_UInt8_13_io_deq_bits : _T_5309 ? _Queue16_UInt8_12_io_deq_bits : _T_5308 ? _Queue16_UInt8_11_io_deq_bits : _T_5307 ? _Queue16_UInt8_10_io_deq_bits : _T_5306 ? _Queue16_UInt8_9_io_deq_bits : _T_5305 ? _Queue16_UInt8_8_io_deq_bits : _T_5304 ? _Queue16_UInt8_7_io_deq_bits : _T_5303 ? _Queue16_UInt8_6_io_deq_bits : _T_5302 ? _Queue16_UInt8_5_io_deq_bits : _T_5301 ? _Queue16_UInt8_4_io_deq_bits : _T_5300 ? _Queue16_UInt8_3_io_deq_bits : _T_5299 ? _Queue16_UInt8_2_io_deq_bits : _T_5298 ? _Queue16_UInt8_1_io_deq_bits : _T_5297 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_valid : _T_5327 ? _Queue16_UInt8_30_io_deq_valid : _T_5326 ? _Queue16_UInt8_29_io_deq_valid : _T_5325 ? _Queue16_UInt8_28_io_deq_valid : _T_5324 ? _Queue16_UInt8_27_io_deq_valid : _T_5323 ? _Queue16_UInt8_26_io_deq_valid : _T_5322 ? _Queue16_UInt8_25_io_deq_valid : _T_5321 ? _Queue16_UInt8_24_io_deq_valid : _T_5320 ? _Queue16_UInt8_23_io_deq_valid : _T_5319 ? _Queue16_UInt8_22_io_deq_valid : _T_5318 ? _Queue16_UInt8_21_io_deq_valid : _T_5317 ? _Queue16_UInt8_20_io_deq_valid : _T_5316 ? _Queue16_UInt8_19_io_deq_valid : _T_5315 ? _Queue16_UInt8_18_io_deq_valid : _T_5314 ? _Queue16_UInt8_17_io_deq_valid : _T_5313 ? _Queue16_UInt8_16_io_deq_valid : _T_5312 ? _Queue16_UInt8_15_io_deq_valid : _T_5311 ? _Queue16_UInt8_14_io_deq_valid : _T_5310 ? _Queue16_UInt8_13_io_deq_valid : _T_5309 ? _Queue16_UInt8_12_io_deq_valid : _T_5308 ? _Queue16_UInt8_11_io_deq_valid : _T_5307 ? _Queue16_UInt8_10_io_deq_valid : _T_5306 ? _Queue16_UInt8_9_io_deq_valid : _T_5305 ? _Queue16_UInt8_8_io_deq_valid : _T_5304 ? _Queue16_UInt8_7_io_deq_valid : _T_5303 ? _Queue16_UInt8_6_io_deq_valid : _T_5302 ? _Queue16_UInt8_5_io_deq_valid : _T_5301 ? _Queue16_UInt8_4_io_deq_valid : _T_5300 ? _Queue16_UInt8_3_io_deq_valid : _T_5299 ? _Queue16_UInt8_2_io_deq_valid : _T_5298 ? _Queue16_UInt8_1_io_deq_valid : _T_5297 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_121 = _remapindex_T_31 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_31 = _GEN_121[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5329 = remapindex_31 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5330 = remapindex_31 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5331 = remapindex_31 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5332 = remapindex_31 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5333 = remapindex_31 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5334 = remapindex_31 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5335 = remapindex_31 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5336 = remapindex_31 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5337 = remapindex_31 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5338 = remapindex_31 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5339 = remapindex_31 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5340 = remapindex_31 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5341 = remapindex_31 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5342 = remapindex_31 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5343 = remapindex_31 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5344 = remapindex_31 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5345 = remapindex_31 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5346 = remapindex_31 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5347 = remapindex_31 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5348 = remapindex_31 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5349 = remapindex_31 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5350 = remapindex_31 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5351 = remapindex_31 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5352 = remapindex_31 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5353 = remapindex_31 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5354 = remapindex_31 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5355 = remapindex_31 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5356 = remapindex_31 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5357 = remapindex_31 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5358 = remapindex_31 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5359 = remapindex_31 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5360 = remapindex_31 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_bits : _T_5359 ? _Queue16_UInt8_30_io_deq_bits : _T_5358 ? _Queue16_UInt8_29_io_deq_bits : _T_5357 ? _Queue16_UInt8_28_io_deq_bits : _T_5356 ? _Queue16_UInt8_27_io_deq_bits : _T_5355 ? _Queue16_UInt8_26_io_deq_bits : _T_5354 ? _Queue16_UInt8_25_io_deq_bits : _T_5353 ? _Queue16_UInt8_24_io_deq_bits : _T_5352 ? _Queue16_UInt8_23_io_deq_bits : _T_5351 ? _Queue16_UInt8_22_io_deq_bits : _T_5350 ? _Queue16_UInt8_21_io_deq_bits : _T_5349 ? _Queue16_UInt8_20_io_deq_bits : _T_5348 ? _Queue16_UInt8_19_io_deq_bits : _T_5347 ? _Queue16_UInt8_18_io_deq_bits : _T_5346 ? _Queue16_UInt8_17_io_deq_bits : _T_5345 ? _Queue16_UInt8_16_io_deq_bits : _T_5344 ? _Queue16_UInt8_15_io_deq_bits : _T_5343 ? _Queue16_UInt8_14_io_deq_bits : _T_5342 ? _Queue16_UInt8_13_io_deq_bits : _T_5341 ? _Queue16_UInt8_12_io_deq_bits : _T_5340 ? _Queue16_UInt8_11_io_deq_bits : _T_5339 ? _Queue16_UInt8_10_io_deq_bits : _T_5338 ? _Queue16_UInt8_9_io_deq_bits : _T_5337 ? _Queue16_UInt8_8_io_deq_bits : _T_5336 ? _Queue16_UInt8_7_io_deq_bits : _T_5335 ? _Queue16_UInt8_6_io_deq_bits : _T_5334 ? _Queue16_UInt8_5_io_deq_bits : _T_5333 ? _Queue16_UInt8_4_io_deq_bits : _T_5332 ? _Queue16_UInt8_3_io_deq_bits : _T_5331 ? _Queue16_UInt8_2_io_deq_bits : _T_5330 ? _Queue16_UInt8_1_io_deq_bits : _T_5329 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_valid : _T_5359 ? _Queue16_UInt8_30_io_deq_valid : _T_5358 ? _Queue16_UInt8_29_io_deq_valid : _T_5357 ? _Queue16_UInt8_28_io_deq_valid : _T_5356 ? _Queue16_UInt8_27_io_deq_valid : _T_5355 ? _Queue16_UInt8_26_io_deq_valid : _T_5354 ? _Queue16_UInt8_25_io_deq_valid : _T_5353 ? _Queue16_UInt8_24_io_deq_valid : _T_5352 ? _Queue16_UInt8_23_io_deq_valid : _T_5351 ? _Queue16_UInt8_22_io_deq_valid : _T_5350 ? _Queue16_UInt8_21_io_deq_valid : _T_5349 ? _Queue16_UInt8_20_io_deq_valid : _T_5348 ? _Queue16_UInt8_19_io_deq_valid : _T_5347 ? _Queue16_UInt8_18_io_deq_valid : _T_5346 ? _Queue16_UInt8_17_io_deq_valid : _T_5345 ? _Queue16_UInt8_16_io_deq_valid : _T_5344 ? _Queue16_UInt8_15_io_deq_valid : _T_5343 ? _Queue16_UInt8_14_io_deq_valid : _T_5342 ? _Queue16_UInt8_13_io_deq_valid : _T_5341 ? _Queue16_UInt8_12_io_deq_valid : _T_5340 ? _Queue16_UInt8_11_io_deq_valid : _T_5339 ? _Queue16_UInt8_10_io_deq_valid : _T_5338 ? _Queue16_UInt8_9_io_deq_valid : _T_5337 ? _Queue16_UInt8_8_io_deq_valid : _T_5336 ? _Queue16_UInt8_7_io_deq_valid : _T_5335 ? _Queue16_UInt8_6_io_deq_valid : _T_5334 ? _Queue16_UInt8_5_io_deq_valid : _T_5333 ? _Queue16_UInt8_4_io_deq_valid : _T_5332 ? _Queue16_UInt8_3_io_deq_valid : _T_5331 ? _Queue16_UInt8_2_io_deq_valid : _T_5330 ? _Queue16_UInt8_1_io_deq_valid : _T_5329 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[EntropyCompressorMemWriter.scala:87:{76,90}, :137:28, :158:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[EntropyCompressorMemWriter.scala:87:{76,90}, :137:28, :158:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] reg [63:0] backend_bytes_written; // @[EntropyCompressorMemWriter.scala:162:38] wire [64:0] _GEN_122 = {1'h0, backend_bytes_written}; // @[EntropyCompressorMemWriter.scala:162:38, :163:71] wire [64:0] _backend_next_write_addr_T = {1'h0, _decompress_dest_info_Q_io_deq_bits_op} + _GEN_122; // @[EntropyCompressorMemWriter.scala:37:38, :163:71] wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[EntropyCompressorMemWriter.scala:163:71] wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_122; // @[EntropyCompressorMemWriter.scala:50:26, :163:71, :166:28] wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[EntropyCompressorMemWriter.scala:166:28] wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[EntropyCompressorMemWriter.scala:50:26, :165:25, :166:28] wire _throttle_end_writeable_T = \|(throttle_end[63:5]); // @[EntropyCompressorMemWriter.scala:165:25, :169:49] wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[EntropyCompressorMemWriter.scala:165:25, :170:53] wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[EntropyCompressorMemWriter.scala:165:25, :170:53, :178:55] wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[EntropyCompressorMemWriter.scala:165:25, :171:55] wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[EntropyCompressorMemWriter.scala:165:25, :171:55, :179:57] wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[EntropyCompressorMemWriter.scala:165:25, :172:57] wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[EntropyCompressorMemWriter.scala:165:25, :172:57, :180:59] wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[EntropyCompressorMemWriter.scala:165:25, :173:59] wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[EntropyCompressorMemWriter.scala:165:25, :173:59, :181:61] wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[EntropyCompressorMemWriter.scala:165:25, :174:61] wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[EntropyCompressorMemWriter.scala:165:25, :174:61, :182:63] wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[EntropyCompressorMemWriter.scala:174:{48,61}] wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[EntropyCompressorMemWriter.scala:173:{46,59}, :174:48] wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[EntropyCompressorMemWriter.scala:172:{44,57}, :173:46] wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[EntropyCompressorMemWriter.scala:171:{42,55}, :172:44] wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[EntropyCompressorMemWriter.scala:170:{40,53}, :171:42] wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[EntropyCompressorMemWriter.scala:169:{35,49}, :170:40] wire _throttle_end_writeable_log2_T = \|(throttle_end[63:5]); // @[EntropyCompressorMemWriter.scala:165:25, :169:49, :177:54] wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[EntropyCompressorMemWriter.scala:181:{48,61}] wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[EntropyCompressorMemWriter.scala:180:{46,59}, :181:48] wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[EntropyCompressorMemWriter.scala:179:{44,57}, :180:46] wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[EntropyCompressorMemWriter.scala:178:{42,55}, :179:44] wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[EntropyCompressorMemWriter.scala:177:{40,54}, :178:42] wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[EntropyCompressorMemWriter.scala:163:71, :186:66] wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[EntropyCompressorMemWriter.scala:163:71, :186:66, :193:71] wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[EntropyCompressorMemWriter.scala:163:71, :187:68] wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[EntropyCompressorMemWriter.scala:163:71, :187:68, :194:72] wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[EntropyCompressorMemWriter.scala:163:71, :188:70] wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[EntropyCompressorMemWriter.scala:163:71, :188:70, :195:74] wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[EntropyCompressorMemWriter.scala:163:71, :189:72] wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[EntropyCompressorMemWriter.scala:163:71, :189:72, :196:76] wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[EntropyCompressorMemWriter.scala:163:71, :190:74] wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[EntropyCompressorMemWriter.scala:163:71, :190:74, :197:78] wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[EntropyCompressorMemWriter.scala:190:{50,74}] wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[EntropyCompressorMemWriter.scala:189:{48,72}, :190:50] wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[EntropyCompressorMemWriter.scala:188:{46,70}, :189:48] wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[EntropyCompressorMemWriter.scala:187:{44,68}, :188:46] wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[EntropyCompressorMemWriter.scala:186:{42,66}, :187:44] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[EntropyCompressorMemWriter.scala:197:{54,78}] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[EntropyCompressorMemWriter.scala:196:{52,76}, :197:54] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[EntropyCompressorMemWriter.scala:195:{50,74}, :196:52] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[EntropyCompressorMemWriter.scala:194:{48,72}, :195:50] wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[EntropyCompressorMemWriter.scala:193:{47,71}, :194:48] wire _count_valids_largest_aligned_T = count_valids[5]; // @[EntropyCompressorMemWriter.scala:158:60, :200:54] wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[EntropyCompressorMemWriter.scala:158:60, :200:54, :208:59] wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[EntropyCompressorMemWriter.scala:158:60, :201:55] wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[EntropyCompressorMemWriter.scala:158:60, :201:55, :209:61] wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[EntropyCompressorMemWriter.scala:158:60, :202:57] wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[EntropyCompressorMemWriter.scala:158:60, :202:57, :210:63] wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[EntropyCompressorMemWriter.scala:158:60, :203:59] wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[EntropyCompressorMemWriter.scala:158:60, :203:59, :211:65] wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[EntropyCompressorMemWriter.scala:158:60, :204:61] wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[EntropyCompressorMemWriter.scala:158:60, :204:61, :212:67] wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[EntropyCompressorMemWriter.scala:158:60, :205:63] wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[EntropyCompressorMemWriter.scala:158:60, :205:63, :213:69] wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[EntropyCompressorMemWriter.scala:205:{50,63}] wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[EntropyCompressorMemWriter.scala:204:{48,61}, :205:50] wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[EntropyCompressorMemWriter.scala:203:{46,59}, :204:48] wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[EntropyCompressorMemWriter.scala:202:{44,57}, :203:46] wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[EntropyCompressorMemWriter.scala:201:{42,55}, :202:44] wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[EntropyCompressorMemWriter.scala:200:{41,54}, :201:42] wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[EntropyCompressorMemWriter.scala:212:{54,67}] wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[EntropyCompressorMemWriter.scala:211:{52,65}, :212:54] wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[EntropyCompressorMemWriter.scala:210:{50,63}, :211:52] wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[EntropyCompressorMemWriter.scala:209:{48,61}, :210:50] wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[EntropyCompressorMemWriter.scala:208:{46,59}, :209:48] wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[EntropyCompressorMemWriter.scala:186:42, :200:41, :220:35] wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :186:42, :221:39] wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :186:42, :221:{8,39}] wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :200:41, :224:38] wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :200:41, :224:{8,38}] wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[EntropyCompressorMemWriter.scala:219:27, :220:35, :221:8, :224:8] wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire enough_data = \|bytes_to_write; // @[EntropyCompressorMemWriter.scala:219:27, :230:36] wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[EntropyCompressorMemWriter.scala:193:47, :208:46, :233:40] wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :193:47, :234:44] wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :193:47, :234:{8,44}] wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :208:46, :237:43] wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :208:46, :237:{8,43}] wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[EntropyCompressorMemWriter.scala:232:32, :233:40, :234:8, :237:8] wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[EntropyCompressorMemWriter.scala:50:26, :162:38, :242:79] wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[EntropyCompressorMemWriter.scala:50:26, :242:{52,79}] wire _remapVecReadys_0_T = \|bytes_to_write; // @[EntropyCompressorMemWriter.scala:219:27, :230:36, :259:43] wire _T_5363 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_1_T = \|(bytes_to_write[5:1]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_3_T = \|(bytes_to_write[5:2]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_7_T = \|(bytes_to_write[5:3]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_15_T = \|(bytes_to_write[5:4]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_31_T = bytes_to_write[5]; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _T_5365 = _T_5363 & ~write_ptr_override & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[EntropyCompressorMemWriter.scala:148:33, :219:27, :263:43] wire [6:0] _GEN_123 = _read_start_index_T % 7'h20; // @[EntropyCompressorMemWriter.scala:263:{43,62}] wire [5:0] _read_start_index_T_1 = _GEN_123[5:0]; // @[EntropyCompressorMemWriter.scala:263:62] wire [64:0] _backend_bytes_written_T = _GEN_122 + {59'h0, bytes_to_write}; // @[EntropyCompressorMemWriter.scala:163:71, :219:27, :264:52] wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[EntropyCompressorMemWriter.scala:264:52] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53] assign _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h2 : bytes_to_write_log2; // @[EntropyCompressorMemWriter.scala:232:32, :242:52, :279:31] assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[EntropyCompressorMemWriter.scala:21:7, :279:31] assign _io_l2io_req_bits_addr_T = write_ptr_override ? _decompress_dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[EntropyCompressorMemWriter.scala:37:38, :163:71, :242:52, :280:31] assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[EntropyCompressorMemWriter.scala:21:7, :280:31] assign _io_l2io_req_bits_data_T = write_ptr_override ? {192'h0, _buf_lens_Q_io_deq_bits} : remapped_write_data; // @[EntropyCompressorMemWriter.scala:50:26, :87:{76,90}, :228:32, :242:52, :281:31] assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[EntropyCompressorMemWriter.scala:21:7, :281:31] wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53] wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _decompress_dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53] assign _decompress_dest_info_Q_io_deq_ready_T_1 = _decompress_dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53] reg [63:0] bufs_completed; // @[EntropyCompressorMemWriter.scala:287:31] assign io_bufs_completed = bufs_completed; // @[EntropyCompressorMemWriter.scala:21:7, :287:31] wire _T_5372 = _decompress_dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18] wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[EntropyCompressorMemWriter.scala:287:31, :295:38] wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[EntropyCompressorMemWriter.scala:295:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_58 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_58( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module VectorScalarMultiplier_1 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { in : { bits : UInt<32>}[4], scale : { bits : UInt<32>}, repeats : UInt<16>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}} reg in : { valid : UInt<1>, bits : { in : { bits : UInt<32>}[4], scale : { bits : UInt<32>}, repeats : UInt<16>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, clock wire in_fire : UInt<1> connect in_fire, UInt<1>(0h0) node _io_req_ready_T = eq(in.valid, UInt<1>(0h0)) node _io_req_ready_T_1 = eq(in.bits.repeats, UInt<1>(0h0)) node _io_req_ready_T_2 = and(_io_req_ready_T_1, in_fire) node _io_req_ready_T_3 = or(_io_req_ready_T, _io_req_ready_T_2) connect io.req.ready, _io_req_ready_T_3 node _T = and(io.req.ready, io.req.valid) when _T : connect in.valid, io.req.valid connect in.bits, io.req.bits else : when in_fire : node _T_1 = eq(in.bits.repeats, UInt<1>(0h0)) when _T_1 : connect in.valid, UInt<1>(0h0) node _in_bits_repeats_T = sub(in.bits.repeats, UInt<1>(0h1)) node _in_bits_repeats_T_1 = tail(_in_bits_repeats_T, 1) connect in.bits.repeats, _in_bits_repeats_T_1 node _T_2 = asUInt(reset) when _T_2 : connect in.valid, UInt<1>(0h0) inst pipe of Pipeline_1 connect pipe.clock, clock connect pipe.reset, reset connect io.resp.bits, pipe.io.out.bits connect io.resp.valid, pipe.io.out.valid connect pipe.io.out.ready, io.resp.ready node _in_fire_T = and(pipe.io.in.ready, pipe.io.in.valid) connect in_fire, _in_fire_T connect pipe.io.in.valid, in.valid connect pipe.io.in.bits.tag.cmd_id, in.bits.tag.cmd_id connect pipe.io.in.bits.tag.bytes_read, in.bits.tag.bytes_read connect pipe.io.in.bits.tag.last, in.bits.tag.last connect pipe.io.in.bits.tag.len, in.bits.tag.len connect pipe.io.in.bits.tag.pixel_repeats, in.bits.tag.pixel_repeats connect pipe.io.in.bits.tag.repeats, in.bits.tag.repeats connect pipe.io.in.bits.tag.scale, in.bits.tag.scale connect pipe.io.in.bits.tag.has_acc_bitwidth, in.bits.tag.has_acc_bitwidth connect pipe.io.in.bits.tag.accumulate, in.bits.tag.accumulate connect pipe.io.in.bits.tag.is_acc, in.bits.tag.is_acc connect pipe.io.in.bits.tag.mask[0], in.bits.tag.mask[0] connect pipe.io.in.bits.tag.mask[1], in.bits.tag.mask[1] connect pipe.io.in.bits.tag.mask[2], in.bits.tag.mask[2] connect pipe.io.in.bits.tag.mask[3], in.bits.tag.mask[3] connect pipe.io.in.bits.tag.mask[4], in.bits.tag.mask[4] connect pipe.io.in.bits.tag.mask[5], in.bits.tag.mask[5] connect pipe.io.in.bits.tag.mask[6], in.bits.tag.mask[6] connect pipe.io.in.bits.tag.mask[7], in.bits.tag.mask[7] connect pipe.io.in.bits.tag.mask[8], in.bits.tag.mask[8] connect pipe.io.in.bits.tag.mask[9], in.bits.tag.mask[9] connect pipe.io.in.bits.tag.mask[10], in.bits.tag.mask[10] connect pipe.io.in.bits.tag.mask[11], in.bits.tag.mask[11] connect pipe.io.in.bits.tag.mask[12], in.bits.tag.mask[12] connect pipe.io.in.bits.tag.mask[13], in.bits.tag.mask[13] connect pipe.io.in.bits.tag.mask[14], in.bits.tag.mask[14] connect pipe.io.in.bits.tag.mask[15], in.bits.tag.mask[15] connect pipe.io.in.bits.tag.addr, in.bits.tag.addr connect pipe.io.in.bits.tag.data, in.bits.tag.data node _pipe_io_in_bits_last_T = eq(in.bits.repeats, UInt<1>(0h0)) node _pipe_io_in_bits_last_T_1 = and(_pipe_io_in_bits_last_T, in.bits.last) connect pipe.io.in.bits.last, _pipe_io_in_bits_last_T_1 connect pipe.io.in.bits.row, in.bits.repeats wire _WIRE : { bits : UInt<32>} wire _WIRE_1 : UInt<32> connect _WIRE_1, in.bits.scale.bits node _T_3 = bits(_WIRE_1, 31, 0) connect _WIRE.bits, _T_3 node t_rec_rawIn_sign = bits(_WIRE.bits, 31, 31) node t_rec_rawIn_expIn = bits(_WIRE.bits, 30, 23) node t_rec_rawIn_fractIn = bits(_WIRE.bits, 22, 0) node t_rec_rawIn_isZeroExpIn = eq(t_rec_rawIn_expIn, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn = eq(t_rec_rawIn_fractIn, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T = bits(t_rec_rawIn_fractIn, 0, 0) node _t_rec_rawIn_normDist_T_1 = bits(t_rec_rawIn_fractIn, 1, 1) node _t_rec_rawIn_normDist_T_2 = bits(t_rec_rawIn_fractIn, 2, 2) node _t_rec_rawIn_normDist_T_3 = bits(t_rec_rawIn_fractIn, 3, 3) node _t_rec_rawIn_normDist_T_4 = bits(t_rec_rawIn_fractIn, 4, 4) node _t_rec_rawIn_normDist_T_5 = bits(t_rec_rawIn_fractIn, 5, 5) node _t_rec_rawIn_normDist_T_6 = bits(t_rec_rawIn_fractIn, 6, 6) node _t_rec_rawIn_normDist_T_7 = bits(t_rec_rawIn_fractIn, 7, 7) node _t_rec_rawIn_normDist_T_8 = bits(t_rec_rawIn_fractIn, 8, 8) node _t_rec_rawIn_normDist_T_9 = bits(t_rec_rawIn_fractIn, 9, 9) node _t_rec_rawIn_normDist_T_10 = bits(t_rec_rawIn_fractIn, 10, 10) node _t_rec_rawIn_normDist_T_11 = bits(t_rec_rawIn_fractIn, 11, 11) node _t_rec_rawIn_normDist_T_12 = bits(t_rec_rawIn_fractIn, 12, 12) node _t_rec_rawIn_normDist_T_13 = bits(t_rec_rawIn_fractIn, 13, 13) node _t_rec_rawIn_normDist_T_14 = bits(t_rec_rawIn_fractIn, 14, 14) node _t_rec_rawIn_normDist_T_15 = bits(t_rec_rawIn_fractIn, 15, 15) node _t_rec_rawIn_normDist_T_16 = bits(t_rec_rawIn_fractIn, 16, 16) node _t_rec_rawIn_normDist_T_17 = bits(t_rec_rawIn_fractIn, 17, 17) node _t_rec_rawIn_normDist_T_18 = bits(t_rec_rawIn_fractIn, 18, 18) node _t_rec_rawIn_normDist_T_19 = bits(t_rec_rawIn_fractIn, 19, 19) node _t_rec_rawIn_normDist_T_20 = bits(t_rec_rawIn_fractIn, 20, 20) node _t_rec_rawIn_normDist_T_21 = bits(t_rec_rawIn_fractIn, 21, 21) node _t_rec_rawIn_normDist_T_22 = bits(t_rec_rawIn_fractIn, 22, 22) node _t_rec_rawIn_normDist_T_23 = mux(_t_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_24 = mux(_t_rec_rawIn_normDist_T_2, UInt<5>(0h14), _t_rec_rawIn_normDist_T_23) node _t_rec_rawIn_normDist_T_25 = mux(_t_rec_rawIn_normDist_T_3, UInt<5>(0h13), _t_rec_rawIn_normDist_T_24) node _t_rec_rawIn_normDist_T_26 = mux(_t_rec_rawIn_normDist_T_4, UInt<5>(0h12), _t_rec_rawIn_normDist_T_25) node _t_rec_rawIn_normDist_T_27 = mux(_t_rec_rawIn_normDist_T_5, UInt<5>(0h11), _t_rec_rawIn_normDist_T_26) node _t_rec_rawIn_normDist_T_28 = mux(_t_rec_rawIn_normDist_T_6, UInt<5>(0h10), _t_rec_rawIn_normDist_T_27) node _t_rec_rawIn_normDist_T_29 = mux(_t_rec_rawIn_normDist_T_7, UInt<4>(0hf), _t_rec_rawIn_normDist_T_28) node _t_rec_rawIn_normDist_T_30 = mux(_t_rec_rawIn_normDist_T_8, UInt<4>(0he), _t_rec_rawIn_normDist_T_29) node _t_rec_rawIn_normDist_T_31 = mux(_t_rec_rawIn_normDist_T_9, UInt<4>(0hd), _t_rec_rawIn_normDist_T_30) node _t_rec_rawIn_normDist_T_32 = mux(_t_rec_rawIn_normDist_T_10, UInt<4>(0hc), _t_rec_rawIn_normDist_T_31) node _t_rec_rawIn_normDist_T_33 = mux(_t_rec_rawIn_normDist_T_11, UInt<4>(0hb), _t_rec_rawIn_normDist_T_32) node _t_rec_rawIn_normDist_T_34 = mux(_t_rec_rawIn_normDist_T_12, UInt<4>(0ha), _t_rec_rawIn_normDist_T_33) node _t_rec_rawIn_normDist_T_35 = mux(_t_rec_rawIn_normDist_T_13, UInt<4>(0h9), _t_rec_rawIn_normDist_T_34) node _t_rec_rawIn_normDist_T_36 = mux(_t_rec_rawIn_normDist_T_14, UInt<4>(0h8), _t_rec_rawIn_normDist_T_35) node _t_rec_rawIn_normDist_T_37 = mux(_t_rec_rawIn_normDist_T_15, UInt<3>(0h7), _t_rec_rawIn_normDist_T_36) node _t_rec_rawIn_normDist_T_38 = mux(_t_rec_rawIn_normDist_T_16, UInt<3>(0h6), _t_rec_rawIn_normDist_T_37) node _t_rec_rawIn_normDist_T_39 = mux(_t_rec_rawIn_normDist_T_17, UInt<3>(0h5), _t_rec_rawIn_normDist_T_38) node _t_rec_rawIn_normDist_T_40 = mux(_t_rec_rawIn_normDist_T_18, UInt<3>(0h4), _t_rec_rawIn_normDist_T_39) node _t_rec_rawIn_normDist_T_41 = mux(_t_rec_rawIn_normDist_T_19, UInt<2>(0h3), _t_rec_rawIn_normDist_T_40) node _t_rec_rawIn_normDist_T_42 = mux(_t_rec_rawIn_normDist_T_20, UInt<2>(0h2), _t_rec_rawIn_normDist_T_41) node _t_rec_rawIn_normDist_T_43 = mux(_t_rec_rawIn_normDist_T_21, UInt<1>(0h1), _t_rec_rawIn_normDist_T_42) node t_rec_rawIn_normDist = mux(_t_rec_rawIn_normDist_T_22, UInt<1>(0h0), _t_rec_rawIn_normDist_T_43) node _t_rec_rawIn_subnormFract_T = dshl(t_rec_rawIn_fractIn, t_rec_rawIn_normDist) node _t_rec_rawIn_subnormFract_T_1 = bits(_t_rec_rawIn_subnormFract_T, 21, 0) node t_rec_rawIn_subnormFract = shl(_t_rec_rawIn_subnormFract_T_1, 1) node _t_rec_rawIn_adjustedExp_T = xor(t_rec_rawIn_normDist, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_1 = mux(t_rec_rawIn_isZeroExpIn, _t_rec_rawIn_adjustedExp_T, t_rec_rawIn_expIn) node _t_rec_rawIn_adjustedExp_T_2 = mux(t_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_2) node _t_rec_rawIn_adjustedExp_T_4 = add(_t_rec_rawIn_adjustedExp_T_1, _t_rec_rawIn_adjustedExp_T_3) node t_rec_rawIn_adjustedExp = tail(_t_rec_rawIn_adjustedExp_T_4, 1) node t_rec_rawIn_isZero = and(t_rec_rawIn_isZeroExpIn, t_rec_rawIn_isZeroFractIn) node _t_rec_rawIn_isSpecial_T = bits(t_rec_rawIn_adjustedExp, 8, 7) node t_rec_rawIn_isSpecial = eq(_t_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire t_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T = eq(t_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_1 = and(t_rec_rawIn_isSpecial, _t_rec_rawIn_out_isNaN_T) connect t_rec_rawIn.isNaN, _t_rec_rawIn_out_isNaN_T_1 node _t_rec_rawIn_out_isInf_T = and(t_rec_rawIn_isSpecial, t_rec_rawIn_isZeroFractIn) connect t_rec_rawIn.isInf, _t_rec_rawIn_out_isInf_T connect t_rec_rawIn.isZero, t_rec_rawIn_isZero connect t_rec_rawIn.sign, t_rec_rawIn_sign node _t_rec_rawIn_out_sExp_T = bits(t_rec_rawIn_adjustedExp, 8, 0) node _t_rec_rawIn_out_sExp_T_1 = cvt(_t_rec_rawIn_out_sExp_T) connect t_rec_rawIn.sExp, _t_rec_rawIn_out_sExp_T_1 node _t_rec_rawIn_out_sig_T = eq(t_rec_rawIn_isZero, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T) node _t_rec_rawIn_out_sig_T_2 = mux(t_rec_rawIn_isZeroExpIn, t_rec_rawIn_subnormFract, t_rec_rawIn_fractIn) node _t_rec_rawIn_out_sig_T_3 = cat(_t_rec_rawIn_out_sig_T_1, _t_rec_rawIn_out_sig_T_2) connect t_rec_rawIn.sig, _t_rec_rawIn_out_sig_T_3 node _t_rec_T = bits(t_rec_rawIn.sExp, 8, 6) node _t_rec_T_1 = mux(t_rec_rawIn.isZero, UInt<3>(0h0), _t_rec_T) node _t_rec_T_2 = mux(t_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_3 = or(_t_rec_T_1, _t_rec_T_2) node _t_rec_T_4 = cat(t_rec_rawIn.sign, _t_rec_T_3) node _t_rec_T_5 = bits(t_rec_rawIn.sExp, 5, 0) node _t_rec_T_6 = cat(_t_rec_T_4, _t_rec_T_5) node _t_rec_T_7 = bits(t_rec_rawIn.sig, 22, 0) node t_rec = cat(_t_rec_T_6, _t_rec_T_7) node self_rec_rawIn_sign = bits(in.bits.in[0].bits, 31, 31) node self_rec_rawIn_expIn = bits(in.bits.in[0].bits, 30, 23) node self_rec_rawIn_fractIn = bits(in.bits.in[0].bits, 22, 0) node self_rec_rawIn_isZeroExpIn = eq(self_rec_rawIn_expIn, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn = eq(self_rec_rawIn_fractIn, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T = bits(self_rec_rawIn_fractIn, 0, 0) node _self_rec_rawIn_normDist_T_1 = bits(self_rec_rawIn_fractIn, 1, 1) node _self_rec_rawIn_normDist_T_2 = bits(self_rec_rawIn_fractIn, 2, 2) node _self_rec_rawIn_normDist_T_3 = bits(self_rec_rawIn_fractIn, 3, 3) node _self_rec_rawIn_normDist_T_4 = bits(self_rec_rawIn_fractIn, 4, 4) node _self_rec_rawIn_normDist_T_5 = bits(self_rec_rawIn_fractIn, 5, 5) node _self_rec_rawIn_normDist_T_6 = bits(self_rec_rawIn_fractIn, 6, 6) node _self_rec_rawIn_normDist_T_7 = bits(self_rec_rawIn_fractIn, 7, 7) node _self_rec_rawIn_normDist_T_8 = bits(self_rec_rawIn_fractIn, 8, 8) node _self_rec_rawIn_normDist_T_9 = bits(self_rec_rawIn_fractIn, 9, 9) node _self_rec_rawIn_normDist_T_10 = bits(self_rec_rawIn_fractIn, 10, 10) node _self_rec_rawIn_normDist_T_11 = bits(self_rec_rawIn_fractIn, 11, 11) node _self_rec_rawIn_normDist_T_12 = bits(self_rec_rawIn_fractIn, 12, 12) node _self_rec_rawIn_normDist_T_13 = bits(self_rec_rawIn_fractIn, 13, 13) node _self_rec_rawIn_normDist_T_14 = bits(self_rec_rawIn_fractIn, 14, 14) node _self_rec_rawIn_normDist_T_15 = bits(self_rec_rawIn_fractIn, 15, 15) node _self_rec_rawIn_normDist_T_16 = bits(self_rec_rawIn_fractIn, 16, 16) node _self_rec_rawIn_normDist_T_17 = bits(self_rec_rawIn_fractIn, 17, 17) node _self_rec_rawIn_normDist_T_18 = bits(self_rec_rawIn_fractIn, 18, 18) node _self_rec_rawIn_normDist_T_19 = bits(self_rec_rawIn_fractIn, 19, 19) node _self_rec_rawIn_normDist_T_20 = bits(self_rec_rawIn_fractIn, 20, 20) node _self_rec_rawIn_normDist_T_21 = bits(self_rec_rawIn_fractIn, 21, 21) node _self_rec_rawIn_normDist_T_22 = bits(self_rec_rawIn_fractIn, 22, 22) node _self_rec_rawIn_normDist_T_23 = mux(_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_24 = mux(_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _self_rec_rawIn_normDist_T_23) node _self_rec_rawIn_normDist_T_25 = mux(_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _self_rec_rawIn_normDist_T_24) node _self_rec_rawIn_normDist_T_26 = mux(_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _self_rec_rawIn_normDist_T_25) node _self_rec_rawIn_normDist_T_27 = mux(_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _self_rec_rawIn_normDist_T_26) node _self_rec_rawIn_normDist_T_28 = mux(_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _self_rec_rawIn_normDist_T_27) node _self_rec_rawIn_normDist_T_29 = mux(_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _self_rec_rawIn_normDist_T_28) node _self_rec_rawIn_normDist_T_30 = mux(_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _self_rec_rawIn_normDist_T_29) node _self_rec_rawIn_normDist_T_31 = mux(_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _self_rec_rawIn_normDist_T_30) node _self_rec_rawIn_normDist_T_32 = mux(_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _self_rec_rawIn_normDist_T_31) node _self_rec_rawIn_normDist_T_33 = mux(_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _self_rec_rawIn_normDist_T_32) node _self_rec_rawIn_normDist_T_34 = mux(_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _self_rec_rawIn_normDist_T_33) node _self_rec_rawIn_normDist_T_35 = mux(_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _self_rec_rawIn_normDist_T_34) node _self_rec_rawIn_normDist_T_36 = mux(_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _self_rec_rawIn_normDist_T_35) node _self_rec_rawIn_normDist_T_37 = mux(_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _self_rec_rawIn_normDist_T_36) node _self_rec_rawIn_normDist_T_38 = mux(_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _self_rec_rawIn_normDist_T_37) node _self_rec_rawIn_normDist_T_39 = mux(_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _self_rec_rawIn_normDist_T_38) node _self_rec_rawIn_normDist_T_40 = mux(_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _self_rec_rawIn_normDist_T_39) node _self_rec_rawIn_normDist_T_41 = mux(_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _self_rec_rawIn_normDist_T_40) node _self_rec_rawIn_normDist_T_42 = mux(_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _self_rec_rawIn_normDist_T_41) node _self_rec_rawIn_normDist_T_43 = mux(_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _self_rec_rawIn_normDist_T_42) node self_rec_rawIn_normDist = mux(_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _self_rec_rawIn_normDist_T_43) node _self_rec_rawIn_subnormFract_T = dshl(self_rec_rawIn_fractIn, self_rec_rawIn_normDist) node _self_rec_rawIn_subnormFract_T_1 = bits(_self_rec_rawIn_subnormFract_T, 21, 0) node self_rec_rawIn_subnormFract = shl(_self_rec_rawIn_subnormFract_T_1, 1) node _self_rec_rawIn_adjustedExp_T = xor(self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_1 = mux(self_rec_rawIn_isZeroExpIn, _self_rec_rawIn_adjustedExp_T, self_rec_rawIn_expIn) node _self_rec_rawIn_adjustedExp_T_2 = mux(self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_2) node _self_rec_rawIn_adjustedExp_T_4 = add(_self_rec_rawIn_adjustedExp_T_1, _self_rec_rawIn_adjustedExp_T_3) node self_rec_rawIn_adjustedExp = tail(_self_rec_rawIn_adjustedExp_T_4, 1) node self_rec_rawIn_isZero = and(self_rec_rawIn_isZeroExpIn, self_rec_rawIn_isZeroFractIn) node _self_rec_rawIn_isSpecial_T = bits(self_rec_rawIn_adjustedExp, 8, 7) node self_rec_rawIn_isSpecial = eq(_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T = eq(self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_1 = and(self_rec_rawIn_isSpecial, _self_rec_rawIn_out_isNaN_T) connect self_rec_rawIn.isNaN, _self_rec_rawIn_out_isNaN_T_1 node _self_rec_rawIn_out_isInf_T = and(self_rec_rawIn_isSpecial, self_rec_rawIn_isZeroFractIn) connect self_rec_rawIn.isInf, _self_rec_rawIn_out_isInf_T connect self_rec_rawIn.isZero, self_rec_rawIn_isZero connect self_rec_rawIn.sign, self_rec_rawIn_sign node _self_rec_rawIn_out_sExp_T = bits(self_rec_rawIn_adjustedExp, 8, 0) node _self_rec_rawIn_out_sExp_T_1 = cvt(_self_rec_rawIn_out_sExp_T) connect self_rec_rawIn.sExp, _self_rec_rawIn_out_sExp_T_1 node _self_rec_rawIn_out_sig_T = eq(self_rec_rawIn_isZero, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T) node _self_rec_rawIn_out_sig_T_2 = mux(self_rec_rawIn_isZeroExpIn, self_rec_rawIn_subnormFract, self_rec_rawIn_fractIn) node _self_rec_rawIn_out_sig_T_3 = cat(_self_rec_rawIn_out_sig_T_1, _self_rec_rawIn_out_sig_T_2) connect self_rec_rawIn.sig, _self_rec_rawIn_out_sig_T_3 node _self_rec_T = bits(self_rec_rawIn.sExp, 8, 6) node _self_rec_T_1 = mux(self_rec_rawIn.isZero, UInt<3>(0h0), _self_rec_T) node _self_rec_T_2 = mux(self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_3 = or(_self_rec_T_1, _self_rec_T_2) node _self_rec_T_4 = cat(self_rec_rawIn.sign, _self_rec_T_3) node _self_rec_T_5 = bits(self_rec_rawIn.sExp, 5, 0) node _self_rec_T_6 = cat(_self_rec_T_4, _self_rec_T_5) node _self_rec_T_7 = bits(self_rec_rawIn.sig, 22, 0) node self_rec = cat(_self_rec_T_6, _self_rec_T_7) inst t_resizer of RecFNToRecFN_8 connect t_resizer.io.in, t_rec connect t_resizer.io.roundingMode, UInt<3>(0h0) connect t_resizer.io.detectTininess, UInt<1>(0h1) inst muladder of MulRecFN_4 connect muladder.io.roundingMode, UInt<3>(0h0) connect muladder.io.detectTininess, UInt<1>(0h1) connect muladder.io.a, self_rec connect muladder.io.b, t_resizer.io.out wire out : { bits : UInt<32>} node out_bits_rawIn_exp = bits(muladder.io.out, 31, 23) node _out_bits_rawIn_isZero_T = bits(out_bits_rawIn_exp, 8, 6) node out_bits_rawIn_isZero = eq(_out_bits_rawIn_isZero_T, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T = bits(out_bits_rawIn_exp, 8, 7) node out_bits_rawIn_isSpecial = eq(_out_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T = bits(out_bits_rawIn_exp, 6, 6) node _out_bits_rawIn_out_isNaN_T_1 = and(out_bits_rawIn_isSpecial, _out_bits_rawIn_out_isNaN_T) connect out_bits_rawIn.isNaN, _out_bits_rawIn_out_isNaN_T_1 node _out_bits_rawIn_out_isInf_T = bits(out_bits_rawIn_exp, 6, 6) node _out_bits_rawIn_out_isInf_T_1 = eq(_out_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_2 = and(out_bits_rawIn_isSpecial, _out_bits_rawIn_out_isInf_T_1) connect out_bits_rawIn.isInf, _out_bits_rawIn_out_isInf_T_2 connect out_bits_rawIn.isZero, out_bits_rawIn_isZero node _out_bits_rawIn_out_sign_T = bits(muladder.io.out, 32, 32) connect out_bits_rawIn.sign, _out_bits_rawIn_out_sign_T node _out_bits_rawIn_out_sExp_T = cvt(out_bits_rawIn_exp) connect out_bits_rawIn.sExp, _out_bits_rawIn_out_sExp_T node _out_bits_rawIn_out_sig_T = eq(out_bits_rawIn_isZero, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T) node _out_bits_rawIn_out_sig_T_2 = bits(muladder.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_3 = cat(_out_bits_rawIn_out_sig_T_1, _out_bits_rawIn_out_sig_T_2) connect out_bits_rawIn.sig, _out_bits_rawIn_out_sig_T_3 node out_bits_isSubnormal = lt(out_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T = bits(out_bits_rawIn.sExp, 4, 0) node _out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T) node out_bits_denormShiftDist = tail(_out_bits_denormShiftDist_T_1, 1) node _out_bits_denormFract_T = shr(out_bits_rawIn.sig, 1) node _out_bits_denormFract_T_1 = dshr(_out_bits_denormFract_T, out_bits_denormShiftDist) node out_bits_denormFract = bits(_out_bits_denormFract_T_1, 22, 0) node _out_bits_expOut_T = bits(out_bits_rawIn.sExp, 7, 0) node _out_bits_expOut_T_1 = sub(_out_bits_expOut_T, UInt<8>(0h81)) node _out_bits_expOut_T_2 = tail(_out_bits_expOut_T_1, 1) node _out_bits_expOut_T_3 = mux(out_bits_isSubnormal, UInt<1>(0h0), _out_bits_expOut_T_2) node _out_bits_expOut_T_4 = or(out_bits_rawIn.isNaN, out_bits_rawIn.isInf) node _out_bits_expOut_T_5 = mux(_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut = or(_out_bits_expOut_T_3, _out_bits_expOut_T_5) node _out_bits_fractOut_T = bits(out_bits_rawIn.sig, 22, 0) node _out_bits_fractOut_T_1 = mux(out_bits_rawIn.isInf, UInt<1>(0h0), _out_bits_fractOut_T) node out_bits_fractOut = mux(out_bits_isSubnormal, out_bits_denormFract, _out_bits_fractOut_T_1) node out_bits_hi = cat(out_bits_rawIn.sign, out_bits_expOut) node _out_bits_T = cat(out_bits_hi, out_bits_fractOut) connect out.bits, _out_bits_T wire _WIRE_2 : { bits : UInt<32>} wire _WIRE_3 : UInt<32> connect _WIRE_3, in.bits.scale.bits node _T_4 = bits(_WIRE_3, 31, 0) connect _WIRE_2.bits, _T_4 node t_rec_rawIn_sign_1 = bits(_WIRE_2.bits, 31, 31) node t_rec_rawIn_expIn_1 = bits(_WIRE_2.bits, 30, 23) node t_rec_rawIn_fractIn_1 = bits(_WIRE_2.bits, 22, 0) node t_rec_rawIn_isZeroExpIn_1 = eq(t_rec_rawIn_expIn_1, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn_1 = eq(t_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T_44 = bits(t_rec_rawIn_fractIn_1, 0, 0) node _t_rec_rawIn_normDist_T_45 = bits(t_rec_rawIn_fractIn_1, 1, 1) node _t_rec_rawIn_normDist_T_46 = bits(t_rec_rawIn_fractIn_1, 2, 2) node _t_rec_rawIn_normDist_T_47 = bits(t_rec_rawIn_fractIn_1, 3, 3) node _t_rec_rawIn_normDist_T_48 = bits(t_rec_rawIn_fractIn_1, 4, 4) node _t_rec_rawIn_normDist_T_49 = bits(t_rec_rawIn_fractIn_1, 5, 5) node _t_rec_rawIn_normDist_T_50 = bits(t_rec_rawIn_fractIn_1, 6, 6) node _t_rec_rawIn_normDist_T_51 = bits(t_rec_rawIn_fractIn_1, 7, 7) node _t_rec_rawIn_normDist_T_52 = bits(t_rec_rawIn_fractIn_1, 8, 8) node _t_rec_rawIn_normDist_T_53 = bits(t_rec_rawIn_fractIn_1, 9, 9) node _t_rec_rawIn_normDist_T_54 = bits(t_rec_rawIn_fractIn_1, 10, 10) node _t_rec_rawIn_normDist_T_55 = bits(t_rec_rawIn_fractIn_1, 11, 11) node _t_rec_rawIn_normDist_T_56 = bits(t_rec_rawIn_fractIn_1, 12, 12) node _t_rec_rawIn_normDist_T_57 = bits(t_rec_rawIn_fractIn_1, 13, 13) node _t_rec_rawIn_normDist_T_58 = bits(t_rec_rawIn_fractIn_1, 14, 14) node _t_rec_rawIn_normDist_T_59 = bits(t_rec_rawIn_fractIn_1, 15, 15) node _t_rec_rawIn_normDist_T_60 = bits(t_rec_rawIn_fractIn_1, 16, 16) node _t_rec_rawIn_normDist_T_61 = bits(t_rec_rawIn_fractIn_1, 17, 17) node _t_rec_rawIn_normDist_T_62 = bits(t_rec_rawIn_fractIn_1, 18, 18) node _t_rec_rawIn_normDist_T_63 = bits(t_rec_rawIn_fractIn_1, 19, 19) node _t_rec_rawIn_normDist_T_64 = bits(t_rec_rawIn_fractIn_1, 20, 20) node _t_rec_rawIn_normDist_T_65 = bits(t_rec_rawIn_fractIn_1, 21, 21) node _t_rec_rawIn_normDist_T_66 = bits(t_rec_rawIn_fractIn_1, 22, 22) node _t_rec_rawIn_normDist_T_67 = mux(_t_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_68 = mux(_t_rec_rawIn_normDist_T_46, UInt<5>(0h14), _t_rec_rawIn_normDist_T_67) node _t_rec_rawIn_normDist_T_69 = mux(_t_rec_rawIn_normDist_T_47, UInt<5>(0h13), _t_rec_rawIn_normDist_T_68) node _t_rec_rawIn_normDist_T_70 = mux(_t_rec_rawIn_normDist_T_48, UInt<5>(0h12), _t_rec_rawIn_normDist_T_69) node _t_rec_rawIn_normDist_T_71 = mux(_t_rec_rawIn_normDist_T_49, UInt<5>(0h11), _t_rec_rawIn_normDist_T_70) node _t_rec_rawIn_normDist_T_72 = mux(_t_rec_rawIn_normDist_T_50, UInt<5>(0h10), _t_rec_rawIn_normDist_T_71) node _t_rec_rawIn_normDist_T_73 = mux(_t_rec_rawIn_normDist_T_51, UInt<4>(0hf), _t_rec_rawIn_normDist_T_72) node _t_rec_rawIn_normDist_T_74 = mux(_t_rec_rawIn_normDist_T_52, UInt<4>(0he), _t_rec_rawIn_normDist_T_73) node _t_rec_rawIn_normDist_T_75 = mux(_t_rec_rawIn_normDist_T_53, UInt<4>(0hd), _t_rec_rawIn_normDist_T_74) node _t_rec_rawIn_normDist_T_76 = mux(_t_rec_rawIn_normDist_T_54, UInt<4>(0hc), _t_rec_rawIn_normDist_T_75) node _t_rec_rawIn_normDist_T_77 = mux(_t_rec_rawIn_normDist_T_55, UInt<4>(0hb), _t_rec_rawIn_normDist_T_76) node _t_rec_rawIn_normDist_T_78 = mux(_t_rec_rawIn_normDist_T_56, UInt<4>(0ha), _t_rec_rawIn_normDist_T_77) node _t_rec_rawIn_normDist_T_79 = mux(_t_rec_rawIn_normDist_T_57, UInt<4>(0h9), _t_rec_rawIn_normDist_T_78) node _t_rec_rawIn_normDist_T_80 = mux(_t_rec_rawIn_normDist_T_58, UInt<4>(0h8), _t_rec_rawIn_normDist_T_79) node _t_rec_rawIn_normDist_T_81 = mux(_t_rec_rawIn_normDist_T_59, UInt<3>(0h7), _t_rec_rawIn_normDist_T_80) node _t_rec_rawIn_normDist_T_82 = mux(_t_rec_rawIn_normDist_T_60, UInt<3>(0h6), _t_rec_rawIn_normDist_T_81) node _t_rec_rawIn_normDist_T_83 = mux(_t_rec_rawIn_normDist_T_61, UInt<3>(0h5), _t_rec_rawIn_normDist_T_82) node _t_rec_rawIn_normDist_T_84 = mux(_t_rec_rawIn_normDist_T_62, UInt<3>(0h4), _t_rec_rawIn_normDist_T_83) node _t_rec_rawIn_normDist_T_85 = mux(_t_rec_rawIn_normDist_T_63, UInt<2>(0h3), _t_rec_rawIn_normDist_T_84) node _t_rec_rawIn_normDist_T_86 = mux(_t_rec_rawIn_normDist_T_64, UInt<2>(0h2), _t_rec_rawIn_normDist_T_85) node _t_rec_rawIn_normDist_T_87 = mux(_t_rec_rawIn_normDist_T_65, UInt<1>(0h1), _t_rec_rawIn_normDist_T_86) node t_rec_rawIn_normDist_1 = mux(_t_rec_rawIn_normDist_T_66, UInt<1>(0h0), _t_rec_rawIn_normDist_T_87) node _t_rec_rawIn_subnormFract_T_2 = dshl(t_rec_rawIn_fractIn_1, t_rec_rawIn_normDist_1) node _t_rec_rawIn_subnormFract_T_3 = bits(_t_rec_rawIn_subnormFract_T_2, 21, 0) node t_rec_rawIn_subnormFract_1 = shl(_t_rec_rawIn_subnormFract_T_3, 1) node _t_rec_rawIn_adjustedExp_T_5 = xor(t_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_6 = mux(t_rec_rawIn_isZeroExpIn_1, _t_rec_rawIn_adjustedExp_T_5, t_rec_rawIn_expIn_1) node _t_rec_rawIn_adjustedExp_T_7 = mux(t_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_7) node _t_rec_rawIn_adjustedExp_T_9 = add(_t_rec_rawIn_adjustedExp_T_6, _t_rec_rawIn_adjustedExp_T_8) node t_rec_rawIn_adjustedExp_1 = tail(_t_rec_rawIn_adjustedExp_T_9, 1) node t_rec_rawIn_isZero_1 = and(t_rec_rawIn_isZeroExpIn_1, t_rec_rawIn_isZeroFractIn_1) node _t_rec_rawIn_isSpecial_T_1 = bits(t_rec_rawIn_adjustedExp_1, 8, 7) node t_rec_rawIn_isSpecial_1 = eq(_t_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire t_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T_2 = eq(t_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_3 = and(t_rec_rawIn_isSpecial_1, _t_rec_rawIn_out_isNaN_T_2) connect t_rec_rawIn_1.isNaN, _t_rec_rawIn_out_isNaN_T_3 node _t_rec_rawIn_out_isInf_T_1 = and(t_rec_rawIn_isSpecial_1, t_rec_rawIn_isZeroFractIn_1) connect t_rec_rawIn_1.isInf, _t_rec_rawIn_out_isInf_T_1 connect t_rec_rawIn_1.isZero, t_rec_rawIn_isZero_1 connect t_rec_rawIn_1.sign, t_rec_rawIn_sign_1 node _t_rec_rawIn_out_sExp_T_2 = bits(t_rec_rawIn_adjustedExp_1, 8, 0) node _t_rec_rawIn_out_sExp_T_3 = cvt(_t_rec_rawIn_out_sExp_T_2) connect t_rec_rawIn_1.sExp, _t_rec_rawIn_out_sExp_T_3 node _t_rec_rawIn_out_sig_T_4 = eq(t_rec_rawIn_isZero_1, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T_4) node _t_rec_rawIn_out_sig_T_6 = mux(t_rec_rawIn_isZeroExpIn_1, t_rec_rawIn_subnormFract_1, t_rec_rawIn_fractIn_1) node _t_rec_rawIn_out_sig_T_7 = cat(_t_rec_rawIn_out_sig_T_5, _t_rec_rawIn_out_sig_T_6) connect t_rec_rawIn_1.sig, _t_rec_rawIn_out_sig_T_7 node _t_rec_T_8 = bits(t_rec_rawIn_1.sExp, 8, 6) node _t_rec_T_9 = mux(t_rec_rawIn_1.isZero, UInt<3>(0h0), _t_rec_T_8) node _t_rec_T_10 = mux(t_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_11 = or(_t_rec_T_9, _t_rec_T_10) node _t_rec_T_12 = cat(t_rec_rawIn_1.sign, _t_rec_T_11) node _t_rec_T_13 = bits(t_rec_rawIn_1.sExp, 5, 0) node _t_rec_T_14 = cat(_t_rec_T_12, _t_rec_T_13) node _t_rec_T_15 = bits(t_rec_rawIn_1.sig, 22, 0) node t_rec_1 = cat(_t_rec_T_14, _t_rec_T_15) node self_rec_rawIn_sign_1 = bits(in.bits.in[1].bits, 31, 31) node self_rec_rawIn_expIn_1 = bits(in.bits.in[1].bits, 30, 23) node self_rec_rawIn_fractIn_1 = bits(in.bits.in[1].bits, 22, 0) node self_rec_rawIn_isZeroExpIn_1 = eq(self_rec_rawIn_expIn_1, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn_1 = eq(self_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T_44 = bits(self_rec_rawIn_fractIn_1, 0, 0) node _self_rec_rawIn_normDist_T_45 = bits(self_rec_rawIn_fractIn_1, 1, 1) node _self_rec_rawIn_normDist_T_46 = bits(self_rec_rawIn_fractIn_1, 2, 2) node _self_rec_rawIn_normDist_T_47 = bits(self_rec_rawIn_fractIn_1, 3, 3) node _self_rec_rawIn_normDist_T_48 = bits(self_rec_rawIn_fractIn_1, 4, 4) node _self_rec_rawIn_normDist_T_49 = bits(self_rec_rawIn_fractIn_1, 5, 5) node _self_rec_rawIn_normDist_T_50 = bits(self_rec_rawIn_fractIn_1, 6, 6) node _self_rec_rawIn_normDist_T_51 = bits(self_rec_rawIn_fractIn_1, 7, 7) node _self_rec_rawIn_normDist_T_52 = bits(self_rec_rawIn_fractIn_1, 8, 8) node _self_rec_rawIn_normDist_T_53 = bits(self_rec_rawIn_fractIn_1, 9, 9) node _self_rec_rawIn_normDist_T_54 = bits(self_rec_rawIn_fractIn_1, 10, 10) node _self_rec_rawIn_normDist_T_55 = bits(self_rec_rawIn_fractIn_1, 11, 11) node _self_rec_rawIn_normDist_T_56 = bits(self_rec_rawIn_fractIn_1, 12, 12) node _self_rec_rawIn_normDist_T_57 = bits(self_rec_rawIn_fractIn_1, 13, 13) node _self_rec_rawIn_normDist_T_58 = bits(self_rec_rawIn_fractIn_1, 14, 14) node _self_rec_rawIn_normDist_T_59 = bits(self_rec_rawIn_fractIn_1, 15, 15) node _self_rec_rawIn_normDist_T_60 = bits(self_rec_rawIn_fractIn_1, 16, 16) node _self_rec_rawIn_normDist_T_61 = bits(self_rec_rawIn_fractIn_1, 17, 17) node _self_rec_rawIn_normDist_T_62 = bits(self_rec_rawIn_fractIn_1, 18, 18) node _self_rec_rawIn_normDist_T_63 = bits(self_rec_rawIn_fractIn_1, 19, 19) node _self_rec_rawIn_normDist_T_64 = bits(self_rec_rawIn_fractIn_1, 20, 20) node _self_rec_rawIn_normDist_T_65 = bits(self_rec_rawIn_fractIn_1, 21, 21) node _self_rec_rawIn_normDist_T_66 = bits(self_rec_rawIn_fractIn_1, 22, 22) node _self_rec_rawIn_normDist_T_67 = mux(_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_68 = mux(_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _self_rec_rawIn_normDist_T_67) node _self_rec_rawIn_normDist_T_69 = mux(_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _self_rec_rawIn_normDist_T_68) node _self_rec_rawIn_normDist_T_70 = mux(_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _self_rec_rawIn_normDist_T_69) node _self_rec_rawIn_normDist_T_71 = mux(_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _self_rec_rawIn_normDist_T_70) node _self_rec_rawIn_normDist_T_72 = mux(_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _self_rec_rawIn_normDist_T_71) node _self_rec_rawIn_normDist_T_73 = mux(_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _self_rec_rawIn_normDist_T_72) node _self_rec_rawIn_normDist_T_74 = mux(_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _self_rec_rawIn_normDist_T_73) node _self_rec_rawIn_normDist_T_75 = mux(_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _self_rec_rawIn_normDist_T_74) node _self_rec_rawIn_normDist_T_76 = mux(_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _self_rec_rawIn_normDist_T_75) node _self_rec_rawIn_normDist_T_77 = mux(_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _self_rec_rawIn_normDist_T_76) node _self_rec_rawIn_normDist_T_78 = mux(_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _self_rec_rawIn_normDist_T_77) node _self_rec_rawIn_normDist_T_79 = mux(_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _self_rec_rawIn_normDist_T_78) node _self_rec_rawIn_normDist_T_80 = mux(_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _self_rec_rawIn_normDist_T_79) node _self_rec_rawIn_normDist_T_81 = mux(_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _self_rec_rawIn_normDist_T_80) node _self_rec_rawIn_normDist_T_82 = mux(_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _self_rec_rawIn_normDist_T_81) node _self_rec_rawIn_normDist_T_83 = mux(_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _self_rec_rawIn_normDist_T_82) node _self_rec_rawIn_normDist_T_84 = mux(_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _self_rec_rawIn_normDist_T_83) node _self_rec_rawIn_normDist_T_85 = mux(_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _self_rec_rawIn_normDist_T_84) node _self_rec_rawIn_normDist_T_86 = mux(_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _self_rec_rawIn_normDist_T_85) node _self_rec_rawIn_normDist_T_87 = mux(_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _self_rec_rawIn_normDist_T_86) node self_rec_rawIn_normDist_1 = mux(_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _self_rec_rawIn_normDist_T_87) node _self_rec_rawIn_subnormFract_T_2 = dshl(self_rec_rawIn_fractIn_1, self_rec_rawIn_normDist_1) node _self_rec_rawIn_subnormFract_T_3 = bits(_self_rec_rawIn_subnormFract_T_2, 21, 0) node self_rec_rawIn_subnormFract_1 = shl(_self_rec_rawIn_subnormFract_T_3, 1) node _self_rec_rawIn_adjustedExp_T_5 = xor(self_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_6 = mux(self_rec_rawIn_isZeroExpIn_1, _self_rec_rawIn_adjustedExp_T_5, self_rec_rawIn_expIn_1) node _self_rec_rawIn_adjustedExp_T_7 = mux(self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_7) node _self_rec_rawIn_adjustedExp_T_9 = add(_self_rec_rawIn_adjustedExp_T_6, _self_rec_rawIn_adjustedExp_T_8) node self_rec_rawIn_adjustedExp_1 = tail(_self_rec_rawIn_adjustedExp_T_9, 1) node self_rec_rawIn_isZero_1 = and(self_rec_rawIn_isZeroExpIn_1, self_rec_rawIn_isZeroFractIn_1) node _self_rec_rawIn_isSpecial_T_1 = bits(self_rec_rawIn_adjustedExp_1, 8, 7) node self_rec_rawIn_isSpecial_1 = eq(_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T_2 = eq(self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_3 = and(self_rec_rawIn_isSpecial_1, _self_rec_rawIn_out_isNaN_T_2) connect self_rec_rawIn_1.isNaN, _self_rec_rawIn_out_isNaN_T_3 node _self_rec_rawIn_out_isInf_T_1 = and(self_rec_rawIn_isSpecial_1, self_rec_rawIn_isZeroFractIn_1) connect self_rec_rawIn_1.isInf, _self_rec_rawIn_out_isInf_T_1 connect self_rec_rawIn_1.isZero, self_rec_rawIn_isZero_1 connect self_rec_rawIn_1.sign, self_rec_rawIn_sign_1 node _self_rec_rawIn_out_sExp_T_2 = bits(self_rec_rawIn_adjustedExp_1, 8, 0) node _self_rec_rawIn_out_sExp_T_3 = cvt(_self_rec_rawIn_out_sExp_T_2) connect self_rec_rawIn_1.sExp, _self_rec_rawIn_out_sExp_T_3 node _self_rec_rawIn_out_sig_T_4 = eq(self_rec_rawIn_isZero_1, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_4) node _self_rec_rawIn_out_sig_T_6 = mux(self_rec_rawIn_isZeroExpIn_1, self_rec_rawIn_subnormFract_1, self_rec_rawIn_fractIn_1) node _self_rec_rawIn_out_sig_T_7 = cat(_self_rec_rawIn_out_sig_T_5, _self_rec_rawIn_out_sig_T_6) connect self_rec_rawIn_1.sig, _self_rec_rawIn_out_sig_T_7 node _self_rec_T_8 = bits(self_rec_rawIn_1.sExp, 8, 6) node _self_rec_T_9 = mux(self_rec_rawIn_1.isZero, UInt<3>(0h0), _self_rec_T_8) node _self_rec_T_10 = mux(self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_11 = or(_self_rec_T_9, _self_rec_T_10) node _self_rec_T_12 = cat(self_rec_rawIn_1.sign, _self_rec_T_11) node _self_rec_T_13 = bits(self_rec_rawIn_1.sExp, 5, 0) node _self_rec_T_14 = cat(_self_rec_T_12, _self_rec_T_13) node _self_rec_T_15 = bits(self_rec_rawIn_1.sig, 22, 0) node self_rec_1 = cat(_self_rec_T_14, _self_rec_T_15) inst t_resizer_1 of RecFNToRecFN_9 connect t_resizer_1.io.in, t_rec_1 connect t_resizer_1.io.roundingMode, UInt<3>(0h0) connect t_resizer_1.io.detectTininess, UInt<1>(0h1) inst muladder_1 of MulRecFN_5 connect muladder_1.io.roundingMode, UInt<3>(0h0) connect muladder_1.io.detectTininess, UInt<1>(0h1) connect muladder_1.io.a, self_rec_1 connect muladder_1.io.b, t_resizer_1.io.out wire out_1 : { bits : UInt<32>} node out_bits_rawIn_exp_1 = bits(muladder_1.io.out, 31, 23) node _out_bits_rawIn_isZero_T_1 = bits(out_bits_rawIn_exp_1, 8, 6) node out_bits_rawIn_isZero_1 = eq(_out_bits_rawIn_isZero_T_1, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T_1 = bits(out_bits_rawIn_exp_1, 8, 7) node out_bits_rawIn_isSpecial_1 = eq(_out_bits_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire out_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T_2 = bits(out_bits_rawIn_exp_1, 6, 6) node _out_bits_rawIn_out_isNaN_T_3 = and(out_bits_rawIn_isSpecial_1, _out_bits_rawIn_out_isNaN_T_2) connect out_bits_rawIn_1.isNaN, _out_bits_rawIn_out_isNaN_T_3 node _out_bits_rawIn_out_isInf_T_3 = bits(out_bits_rawIn_exp_1, 6, 6) node _out_bits_rawIn_out_isInf_T_4 = eq(_out_bits_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_5 = and(out_bits_rawIn_isSpecial_1, _out_bits_rawIn_out_isInf_T_4) connect out_bits_rawIn_1.isInf, _out_bits_rawIn_out_isInf_T_5 connect out_bits_rawIn_1.isZero, out_bits_rawIn_isZero_1 node _out_bits_rawIn_out_sign_T_1 = bits(muladder_1.io.out, 32, 32) connect out_bits_rawIn_1.sign, _out_bits_rawIn_out_sign_T_1 node _out_bits_rawIn_out_sExp_T_1 = cvt(out_bits_rawIn_exp_1) connect out_bits_rawIn_1.sExp, _out_bits_rawIn_out_sExp_T_1 node _out_bits_rawIn_out_sig_T_4 = eq(out_bits_rawIn_isZero_1, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T_4) node _out_bits_rawIn_out_sig_T_6 = bits(muladder_1.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_7 = cat(_out_bits_rawIn_out_sig_T_5, _out_bits_rawIn_out_sig_T_6) connect out_bits_rawIn_1.sig, _out_bits_rawIn_out_sig_T_7 node out_bits_isSubnormal_1 = lt(out_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T_2 = bits(out_bits_rawIn_1.sExp, 4, 0) node _out_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T_2) node out_bits_denormShiftDist_1 = tail(_out_bits_denormShiftDist_T_3, 1) node _out_bits_denormFract_T_2 = shr(out_bits_rawIn_1.sig, 1) node _out_bits_denormFract_T_3 = dshr(_out_bits_denormFract_T_2, out_bits_denormShiftDist_1) node out_bits_denormFract_1 = bits(_out_bits_denormFract_T_3, 22, 0) node _out_bits_expOut_T_6 = bits(out_bits_rawIn_1.sExp, 7, 0) node _out_bits_expOut_T_7 = sub(_out_bits_expOut_T_6, UInt<8>(0h81)) node _out_bits_expOut_T_8 = tail(_out_bits_expOut_T_7, 1) node _out_bits_expOut_T_9 = mux(out_bits_isSubnormal_1, UInt<1>(0h0), _out_bits_expOut_T_8) node _out_bits_expOut_T_10 = or(out_bits_rawIn_1.isNaN, out_bits_rawIn_1.isInf) node _out_bits_expOut_T_11 = mux(_out_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut_1 = or(_out_bits_expOut_T_9, _out_bits_expOut_T_11) node _out_bits_fractOut_T_2 = bits(out_bits_rawIn_1.sig, 22, 0) node _out_bits_fractOut_T_3 = mux(out_bits_rawIn_1.isInf, UInt<1>(0h0), _out_bits_fractOut_T_2) node out_bits_fractOut_1 = mux(out_bits_isSubnormal_1, out_bits_denormFract_1, _out_bits_fractOut_T_3) node out_bits_hi_1 = cat(out_bits_rawIn_1.sign, out_bits_expOut_1) node _out_bits_T_1 = cat(out_bits_hi_1, out_bits_fractOut_1) connect out_1.bits, _out_bits_T_1 wire _WIRE_4 : { bits : UInt<32>} wire _WIRE_5 : UInt<32> connect _WIRE_5, in.bits.scale.bits node _T_5 = bits(_WIRE_5, 31, 0) connect _WIRE_4.bits, _T_5 node t_rec_rawIn_sign_2 = bits(_WIRE_4.bits, 31, 31) node t_rec_rawIn_expIn_2 = bits(_WIRE_4.bits, 30, 23) node t_rec_rawIn_fractIn_2 = bits(_WIRE_4.bits, 22, 0) node t_rec_rawIn_isZeroExpIn_2 = eq(t_rec_rawIn_expIn_2, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn_2 = eq(t_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T_88 = bits(t_rec_rawIn_fractIn_2, 0, 0) node _t_rec_rawIn_normDist_T_89 = bits(t_rec_rawIn_fractIn_2, 1, 1) node _t_rec_rawIn_normDist_T_90 = bits(t_rec_rawIn_fractIn_2, 2, 2) node _t_rec_rawIn_normDist_T_91 = bits(t_rec_rawIn_fractIn_2, 3, 3) node _t_rec_rawIn_normDist_T_92 = bits(t_rec_rawIn_fractIn_2, 4, 4) node _t_rec_rawIn_normDist_T_93 = bits(t_rec_rawIn_fractIn_2, 5, 5) node _t_rec_rawIn_normDist_T_94 = bits(t_rec_rawIn_fractIn_2, 6, 6) node _t_rec_rawIn_normDist_T_95 = bits(t_rec_rawIn_fractIn_2, 7, 7) node _t_rec_rawIn_normDist_T_96 = bits(t_rec_rawIn_fractIn_2, 8, 8) node _t_rec_rawIn_normDist_T_97 = bits(t_rec_rawIn_fractIn_2, 9, 9) node _t_rec_rawIn_normDist_T_98 = bits(t_rec_rawIn_fractIn_2, 10, 10) node _t_rec_rawIn_normDist_T_99 = bits(t_rec_rawIn_fractIn_2, 11, 11) node _t_rec_rawIn_normDist_T_100 = bits(t_rec_rawIn_fractIn_2, 12, 12) node _t_rec_rawIn_normDist_T_101 = bits(t_rec_rawIn_fractIn_2, 13, 13) node _t_rec_rawIn_normDist_T_102 = bits(t_rec_rawIn_fractIn_2, 14, 14) node _t_rec_rawIn_normDist_T_103 = bits(t_rec_rawIn_fractIn_2, 15, 15) node _t_rec_rawIn_normDist_T_104 = bits(t_rec_rawIn_fractIn_2, 16, 16) node _t_rec_rawIn_normDist_T_105 = bits(t_rec_rawIn_fractIn_2, 17, 17) node _t_rec_rawIn_normDist_T_106 = bits(t_rec_rawIn_fractIn_2, 18, 18) node _t_rec_rawIn_normDist_T_107 = bits(t_rec_rawIn_fractIn_2, 19, 19) node _t_rec_rawIn_normDist_T_108 = bits(t_rec_rawIn_fractIn_2, 20, 20) node _t_rec_rawIn_normDist_T_109 = bits(t_rec_rawIn_fractIn_2, 21, 21) node _t_rec_rawIn_normDist_T_110 = bits(t_rec_rawIn_fractIn_2, 22, 22) node _t_rec_rawIn_normDist_T_111 = mux(_t_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_112 = mux(_t_rec_rawIn_normDist_T_90, UInt<5>(0h14), _t_rec_rawIn_normDist_T_111) node _t_rec_rawIn_normDist_T_113 = mux(_t_rec_rawIn_normDist_T_91, UInt<5>(0h13), _t_rec_rawIn_normDist_T_112) node _t_rec_rawIn_normDist_T_114 = mux(_t_rec_rawIn_normDist_T_92, UInt<5>(0h12), _t_rec_rawIn_normDist_T_113) node _t_rec_rawIn_normDist_T_115 = mux(_t_rec_rawIn_normDist_T_93, UInt<5>(0h11), _t_rec_rawIn_normDist_T_114) node _t_rec_rawIn_normDist_T_116 = mux(_t_rec_rawIn_normDist_T_94, UInt<5>(0h10), _t_rec_rawIn_normDist_T_115) node _t_rec_rawIn_normDist_T_117 = mux(_t_rec_rawIn_normDist_T_95, UInt<4>(0hf), _t_rec_rawIn_normDist_T_116) node _t_rec_rawIn_normDist_T_118 = mux(_t_rec_rawIn_normDist_T_96, UInt<4>(0he), _t_rec_rawIn_normDist_T_117) node _t_rec_rawIn_normDist_T_119 = mux(_t_rec_rawIn_normDist_T_97, UInt<4>(0hd), _t_rec_rawIn_normDist_T_118) node _t_rec_rawIn_normDist_T_120 = mux(_t_rec_rawIn_normDist_T_98, UInt<4>(0hc), _t_rec_rawIn_normDist_T_119) node _t_rec_rawIn_normDist_T_121 = mux(_t_rec_rawIn_normDist_T_99, UInt<4>(0hb), _t_rec_rawIn_normDist_T_120) node _t_rec_rawIn_normDist_T_122 = mux(_t_rec_rawIn_normDist_T_100, UInt<4>(0ha), _t_rec_rawIn_normDist_T_121) node _t_rec_rawIn_normDist_T_123 = mux(_t_rec_rawIn_normDist_T_101, UInt<4>(0h9), _t_rec_rawIn_normDist_T_122) node _t_rec_rawIn_normDist_T_124 = mux(_t_rec_rawIn_normDist_T_102, UInt<4>(0h8), _t_rec_rawIn_normDist_T_123) node _t_rec_rawIn_normDist_T_125 = mux(_t_rec_rawIn_normDist_T_103, UInt<3>(0h7), _t_rec_rawIn_normDist_T_124) node _t_rec_rawIn_normDist_T_126 = mux(_t_rec_rawIn_normDist_T_104, UInt<3>(0h6), _t_rec_rawIn_normDist_T_125) node _t_rec_rawIn_normDist_T_127 = mux(_t_rec_rawIn_normDist_T_105, UInt<3>(0h5), _t_rec_rawIn_normDist_T_126) node _t_rec_rawIn_normDist_T_128 = mux(_t_rec_rawIn_normDist_T_106, UInt<3>(0h4), _t_rec_rawIn_normDist_T_127) node _t_rec_rawIn_normDist_T_129 = mux(_t_rec_rawIn_normDist_T_107, UInt<2>(0h3), _t_rec_rawIn_normDist_T_128) node _t_rec_rawIn_normDist_T_130 = mux(_t_rec_rawIn_normDist_T_108, UInt<2>(0h2), _t_rec_rawIn_normDist_T_129) node _t_rec_rawIn_normDist_T_131 = mux(_t_rec_rawIn_normDist_T_109, UInt<1>(0h1), _t_rec_rawIn_normDist_T_130) node t_rec_rawIn_normDist_2 = mux(_t_rec_rawIn_normDist_T_110, UInt<1>(0h0), _t_rec_rawIn_normDist_T_131) node _t_rec_rawIn_subnormFract_T_4 = dshl(t_rec_rawIn_fractIn_2, t_rec_rawIn_normDist_2) node _t_rec_rawIn_subnormFract_T_5 = bits(_t_rec_rawIn_subnormFract_T_4, 21, 0) node t_rec_rawIn_subnormFract_2 = shl(_t_rec_rawIn_subnormFract_T_5, 1) node _t_rec_rawIn_adjustedExp_T_10 = xor(t_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_11 = mux(t_rec_rawIn_isZeroExpIn_2, _t_rec_rawIn_adjustedExp_T_10, t_rec_rawIn_expIn_2) node _t_rec_rawIn_adjustedExp_T_12 = mux(t_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_12) node _t_rec_rawIn_adjustedExp_T_14 = add(_t_rec_rawIn_adjustedExp_T_11, _t_rec_rawIn_adjustedExp_T_13) node t_rec_rawIn_adjustedExp_2 = tail(_t_rec_rawIn_adjustedExp_T_14, 1) node t_rec_rawIn_isZero_2 = and(t_rec_rawIn_isZeroExpIn_2, t_rec_rawIn_isZeroFractIn_2) node _t_rec_rawIn_isSpecial_T_2 = bits(t_rec_rawIn_adjustedExp_2, 8, 7) node t_rec_rawIn_isSpecial_2 = eq(_t_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire t_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T_4 = eq(t_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_5 = and(t_rec_rawIn_isSpecial_2, _t_rec_rawIn_out_isNaN_T_4) connect t_rec_rawIn_2.isNaN, _t_rec_rawIn_out_isNaN_T_5 node _t_rec_rawIn_out_isInf_T_2 = and(t_rec_rawIn_isSpecial_2, t_rec_rawIn_isZeroFractIn_2) connect t_rec_rawIn_2.isInf, _t_rec_rawIn_out_isInf_T_2 connect t_rec_rawIn_2.isZero, t_rec_rawIn_isZero_2 connect t_rec_rawIn_2.sign, t_rec_rawIn_sign_2 node _t_rec_rawIn_out_sExp_T_4 = bits(t_rec_rawIn_adjustedExp_2, 8, 0) node _t_rec_rawIn_out_sExp_T_5 = cvt(_t_rec_rawIn_out_sExp_T_4) connect t_rec_rawIn_2.sExp, _t_rec_rawIn_out_sExp_T_5 node _t_rec_rawIn_out_sig_T_8 = eq(t_rec_rawIn_isZero_2, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T_8) node _t_rec_rawIn_out_sig_T_10 = mux(t_rec_rawIn_isZeroExpIn_2, t_rec_rawIn_subnormFract_2, t_rec_rawIn_fractIn_2) node _t_rec_rawIn_out_sig_T_11 = cat(_t_rec_rawIn_out_sig_T_9, _t_rec_rawIn_out_sig_T_10) connect t_rec_rawIn_2.sig, _t_rec_rawIn_out_sig_T_11 node _t_rec_T_16 = bits(t_rec_rawIn_2.sExp, 8, 6) node _t_rec_T_17 = mux(t_rec_rawIn_2.isZero, UInt<3>(0h0), _t_rec_T_16) node _t_rec_T_18 = mux(t_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_19 = or(_t_rec_T_17, _t_rec_T_18) node _t_rec_T_20 = cat(t_rec_rawIn_2.sign, _t_rec_T_19) node _t_rec_T_21 = bits(t_rec_rawIn_2.sExp, 5, 0) node _t_rec_T_22 = cat(_t_rec_T_20, _t_rec_T_21) node _t_rec_T_23 = bits(t_rec_rawIn_2.sig, 22, 0) node t_rec_2 = cat(_t_rec_T_22, _t_rec_T_23) node self_rec_rawIn_sign_2 = bits(in.bits.in[2].bits, 31, 31) node self_rec_rawIn_expIn_2 = bits(in.bits.in[2].bits, 30, 23) node self_rec_rawIn_fractIn_2 = bits(in.bits.in[2].bits, 22, 0) node self_rec_rawIn_isZeroExpIn_2 = eq(self_rec_rawIn_expIn_2, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn_2 = eq(self_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T_88 = bits(self_rec_rawIn_fractIn_2, 0, 0) node _self_rec_rawIn_normDist_T_89 = bits(self_rec_rawIn_fractIn_2, 1, 1) node _self_rec_rawIn_normDist_T_90 = bits(self_rec_rawIn_fractIn_2, 2, 2) node _self_rec_rawIn_normDist_T_91 = bits(self_rec_rawIn_fractIn_2, 3, 3) node _self_rec_rawIn_normDist_T_92 = bits(self_rec_rawIn_fractIn_2, 4, 4) node _self_rec_rawIn_normDist_T_93 = bits(self_rec_rawIn_fractIn_2, 5, 5) node _self_rec_rawIn_normDist_T_94 = bits(self_rec_rawIn_fractIn_2, 6, 6) node _self_rec_rawIn_normDist_T_95 = bits(self_rec_rawIn_fractIn_2, 7, 7) node _self_rec_rawIn_normDist_T_96 = bits(self_rec_rawIn_fractIn_2, 8, 8) node _self_rec_rawIn_normDist_T_97 = bits(self_rec_rawIn_fractIn_2, 9, 9) node _self_rec_rawIn_normDist_T_98 = bits(self_rec_rawIn_fractIn_2, 10, 10) node _self_rec_rawIn_normDist_T_99 = bits(self_rec_rawIn_fractIn_2, 11, 11) node _self_rec_rawIn_normDist_T_100 = bits(self_rec_rawIn_fractIn_2, 12, 12) node _self_rec_rawIn_normDist_T_101 = bits(self_rec_rawIn_fractIn_2, 13, 13) node _self_rec_rawIn_normDist_T_102 = bits(self_rec_rawIn_fractIn_2, 14, 14) node _self_rec_rawIn_normDist_T_103 = bits(self_rec_rawIn_fractIn_2, 15, 15) node _self_rec_rawIn_normDist_T_104 = bits(self_rec_rawIn_fractIn_2, 16, 16) node _self_rec_rawIn_normDist_T_105 = bits(self_rec_rawIn_fractIn_2, 17, 17) node _self_rec_rawIn_normDist_T_106 = bits(self_rec_rawIn_fractIn_2, 18, 18) node _self_rec_rawIn_normDist_T_107 = bits(self_rec_rawIn_fractIn_2, 19, 19) node _self_rec_rawIn_normDist_T_108 = bits(self_rec_rawIn_fractIn_2, 20, 20) node _self_rec_rawIn_normDist_T_109 = bits(self_rec_rawIn_fractIn_2, 21, 21) node _self_rec_rawIn_normDist_T_110 = bits(self_rec_rawIn_fractIn_2, 22, 22) node _self_rec_rawIn_normDist_T_111 = mux(_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_112 = mux(_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _self_rec_rawIn_normDist_T_111) node _self_rec_rawIn_normDist_T_113 = mux(_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _self_rec_rawIn_normDist_T_112) node _self_rec_rawIn_normDist_T_114 = mux(_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _self_rec_rawIn_normDist_T_113) node _self_rec_rawIn_normDist_T_115 = mux(_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _self_rec_rawIn_normDist_T_114) node _self_rec_rawIn_normDist_T_116 = mux(_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _self_rec_rawIn_normDist_T_115) node _self_rec_rawIn_normDist_T_117 = mux(_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _self_rec_rawIn_normDist_T_116) node _self_rec_rawIn_normDist_T_118 = mux(_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _self_rec_rawIn_normDist_T_117) node _self_rec_rawIn_normDist_T_119 = mux(_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _self_rec_rawIn_normDist_T_118) node _self_rec_rawIn_normDist_T_120 = mux(_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _self_rec_rawIn_normDist_T_119) node _self_rec_rawIn_normDist_T_121 = mux(_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _self_rec_rawIn_normDist_T_120) node _self_rec_rawIn_normDist_T_122 = mux(_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _self_rec_rawIn_normDist_T_121) node _self_rec_rawIn_normDist_T_123 = mux(_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _self_rec_rawIn_normDist_T_122) node _self_rec_rawIn_normDist_T_124 = mux(_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _self_rec_rawIn_normDist_T_123) node _self_rec_rawIn_normDist_T_125 = mux(_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _self_rec_rawIn_normDist_T_124) node _self_rec_rawIn_normDist_T_126 = mux(_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _self_rec_rawIn_normDist_T_125) node _self_rec_rawIn_normDist_T_127 = mux(_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _self_rec_rawIn_normDist_T_126) node _self_rec_rawIn_normDist_T_128 = mux(_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _self_rec_rawIn_normDist_T_127) node _self_rec_rawIn_normDist_T_129 = mux(_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _self_rec_rawIn_normDist_T_128) node _self_rec_rawIn_normDist_T_130 = mux(_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _self_rec_rawIn_normDist_T_129) node _self_rec_rawIn_normDist_T_131 = mux(_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _self_rec_rawIn_normDist_T_130) node self_rec_rawIn_normDist_2 = mux(_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _self_rec_rawIn_normDist_T_131) node _self_rec_rawIn_subnormFract_T_4 = dshl(self_rec_rawIn_fractIn_2, self_rec_rawIn_normDist_2) node _self_rec_rawIn_subnormFract_T_5 = bits(_self_rec_rawIn_subnormFract_T_4, 21, 0) node self_rec_rawIn_subnormFract_2 = shl(_self_rec_rawIn_subnormFract_T_5, 1) node _self_rec_rawIn_adjustedExp_T_10 = xor(self_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_11 = mux(self_rec_rawIn_isZeroExpIn_2, _self_rec_rawIn_adjustedExp_T_10, self_rec_rawIn_expIn_2) node _self_rec_rawIn_adjustedExp_T_12 = mux(self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_12) node _self_rec_rawIn_adjustedExp_T_14 = add(_self_rec_rawIn_adjustedExp_T_11, _self_rec_rawIn_adjustedExp_T_13) node self_rec_rawIn_adjustedExp_2 = tail(_self_rec_rawIn_adjustedExp_T_14, 1) node self_rec_rawIn_isZero_2 = and(self_rec_rawIn_isZeroExpIn_2, self_rec_rawIn_isZeroFractIn_2) node _self_rec_rawIn_isSpecial_T_2 = bits(self_rec_rawIn_adjustedExp_2, 8, 7) node self_rec_rawIn_isSpecial_2 = eq(_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T_4 = eq(self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_5 = and(self_rec_rawIn_isSpecial_2, _self_rec_rawIn_out_isNaN_T_4) connect self_rec_rawIn_2.isNaN, _self_rec_rawIn_out_isNaN_T_5 node _self_rec_rawIn_out_isInf_T_2 = and(self_rec_rawIn_isSpecial_2, self_rec_rawIn_isZeroFractIn_2) connect self_rec_rawIn_2.isInf, _self_rec_rawIn_out_isInf_T_2 connect self_rec_rawIn_2.isZero, self_rec_rawIn_isZero_2 connect self_rec_rawIn_2.sign, self_rec_rawIn_sign_2 node _self_rec_rawIn_out_sExp_T_4 = bits(self_rec_rawIn_adjustedExp_2, 8, 0) node _self_rec_rawIn_out_sExp_T_5 = cvt(_self_rec_rawIn_out_sExp_T_4) connect self_rec_rawIn_2.sExp, _self_rec_rawIn_out_sExp_T_5 node _self_rec_rawIn_out_sig_T_8 = eq(self_rec_rawIn_isZero_2, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_8) node _self_rec_rawIn_out_sig_T_10 = mux(self_rec_rawIn_isZeroExpIn_2, self_rec_rawIn_subnormFract_2, self_rec_rawIn_fractIn_2) node _self_rec_rawIn_out_sig_T_11 = cat(_self_rec_rawIn_out_sig_T_9, _self_rec_rawIn_out_sig_T_10) connect self_rec_rawIn_2.sig, _self_rec_rawIn_out_sig_T_11 node _self_rec_T_16 = bits(self_rec_rawIn_2.sExp, 8, 6) node _self_rec_T_17 = mux(self_rec_rawIn_2.isZero, UInt<3>(0h0), _self_rec_T_16) node _self_rec_T_18 = mux(self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_19 = or(_self_rec_T_17, _self_rec_T_18) node _self_rec_T_20 = cat(self_rec_rawIn_2.sign, _self_rec_T_19) node _self_rec_T_21 = bits(self_rec_rawIn_2.sExp, 5, 0) node _self_rec_T_22 = cat(_self_rec_T_20, _self_rec_T_21) node _self_rec_T_23 = bits(self_rec_rawIn_2.sig, 22, 0) node self_rec_2 = cat(_self_rec_T_22, _self_rec_T_23) inst t_resizer_2 of RecFNToRecFN_10 connect t_resizer_2.io.in, t_rec_2 connect t_resizer_2.io.roundingMode, UInt<3>(0h0) connect t_resizer_2.io.detectTininess, UInt<1>(0h1) inst muladder_2 of MulRecFN_6 connect muladder_2.io.roundingMode, UInt<3>(0h0) connect muladder_2.io.detectTininess, UInt<1>(0h1) connect muladder_2.io.a, self_rec_2 connect muladder_2.io.b, t_resizer_2.io.out wire out_2 : { bits : UInt<32>} node out_bits_rawIn_exp_2 = bits(muladder_2.io.out, 31, 23) node _out_bits_rawIn_isZero_T_2 = bits(out_bits_rawIn_exp_2, 8, 6) node out_bits_rawIn_isZero_2 = eq(_out_bits_rawIn_isZero_T_2, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T_2 = bits(out_bits_rawIn_exp_2, 8, 7) node out_bits_rawIn_isSpecial_2 = eq(_out_bits_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire out_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T_4 = bits(out_bits_rawIn_exp_2, 6, 6) node _out_bits_rawIn_out_isNaN_T_5 = and(out_bits_rawIn_isSpecial_2, _out_bits_rawIn_out_isNaN_T_4) connect out_bits_rawIn_2.isNaN, _out_bits_rawIn_out_isNaN_T_5 node _out_bits_rawIn_out_isInf_T_6 = bits(out_bits_rawIn_exp_2, 6, 6) node _out_bits_rawIn_out_isInf_T_7 = eq(_out_bits_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_8 = and(out_bits_rawIn_isSpecial_2, _out_bits_rawIn_out_isInf_T_7) connect out_bits_rawIn_2.isInf, _out_bits_rawIn_out_isInf_T_8 connect out_bits_rawIn_2.isZero, out_bits_rawIn_isZero_2 node _out_bits_rawIn_out_sign_T_2 = bits(muladder_2.io.out, 32, 32) connect out_bits_rawIn_2.sign, _out_bits_rawIn_out_sign_T_2 node _out_bits_rawIn_out_sExp_T_2 = cvt(out_bits_rawIn_exp_2) connect out_bits_rawIn_2.sExp, _out_bits_rawIn_out_sExp_T_2 node _out_bits_rawIn_out_sig_T_8 = eq(out_bits_rawIn_isZero_2, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T_8) node _out_bits_rawIn_out_sig_T_10 = bits(muladder_2.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_11 = cat(_out_bits_rawIn_out_sig_T_9, _out_bits_rawIn_out_sig_T_10) connect out_bits_rawIn_2.sig, _out_bits_rawIn_out_sig_T_11 node out_bits_isSubnormal_2 = lt(out_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T_4 = bits(out_bits_rawIn_2.sExp, 4, 0) node _out_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T_4) node out_bits_denormShiftDist_2 = tail(_out_bits_denormShiftDist_T_5, 1) node _out_bits_denormFract_T_4 = shr(out_bits_rawIn_2.sig, 1) node _out_bits_denormFract_T_5 = dshr(_out_bits_denormFract_T_4, out_bits_denormShiftDist_2) node out_bits_denormFract_2 = bits(_out_bits_denormFract_T_5, 22, 0) node _out_bits_expOut_T_12 = bits(out_bits_rawIn_2.sExp, 7, 0) node _out_bits_expOut_T_13 = sub(_out_bits_expOut_T_12, UInt<8>(0h81)) node _out_bits_expOut_T_14 = tail(_out_bits_expOut_T_13, 1) node _out_bits_expOut_T_15 = mux(out_bits_isSubnormal_2, UInt<1>(0h0), _out_bits_expOut_T_14) node _out_bits_expOut_T_16 = or(out_bits_rawIn_2.isNaN, out_bits_rawIn_2.isInf) node _out_bits_expOut_T_17 = mux(_out_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut_2 = or(_out_bits_expOut_T_15, _out_bits_expOut_T_17) node _out_bits_fractOut_T_4 = bits(out_bits_rawIn_2.sig, 22, 0) node _out_bits_fractOut_T_5 = mux(out_bits_rawIn_2.isInf, UInt<1>(0h0), _out_bits_fractOut_T_4) node out_bits_fractOut_2 = mux(out_bits_isSubnormal_2, out_bits_denormFract_2, _out_bits_fractOut_T_5) node out_bits_hi_2 = cat(out_bits_rawIn_2.sign, out_bits_expOut_2) node _out_bits_T_2 = cat(out_bits_hi_2, out_bits_fractOut_2) connect out_2.bits, _out_bits_T_2 wire _WIRE_6 : { bits : UInt<32>} wire _WIRE_7 : UInt<32> connect _WIRE_7, in.bits.scale.bits node _T_6 = bits(_WIRE_7, 31, 0) connect _WIRE_6.bits, _T_6 node t_rec_rawIn_sign_3 = bits(_WIRE_6.bits, 31, 31) node t_rec_rawIn_expIn_3 = bits(_WIRE_6.bits, 30, 23) node t_rec_rawIn_fractIn_3 = bits(_WIRE_6.bits, 22, 0) node t_rec_rawIn_isZeroExpIn_3 = eq(t_rec_rawIn_expIn_3, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn_3 = eq(t_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T_132 = bits(t_rec_rawIn_fractIn_3, 0, 0) node _t_rec_rawIn_normDist_T_133 = bits(t_rec_rawIn_fractIn_3, 1, 1) node _t_rec_rawIn_normDist_T_134 = bits(t_rec_rawIn_fractIn_3, 2, 2) node _t_rec_rawIn_normDist_T_135 = bits(t_rec_rawIn_fractIn_3, 3, 3) node _t_rec_rawIn_normDist_T_136 = bits(t_rec_rawIn_fractIn_3, 4, 4) node _t_rec_rawIn_normDist_T_137 = bits(t_rec_rawIn_fractIn_3, 5, 5) node _t_rec_rawIn_normDist_T_138 = bits(t_rec_rawIn_fractIn_3, 6, 6) node _t_rec_rawIn_normDist_T_139 = bits(t_rec_rawIn_fractIn_3, 7, 7) node _t_rec_rawIn_normDist_T_140 = bits(t_rec_rawIn_fractIn_3, 8, 8) node _t_rec_rawIn_normDist_T_141 = bits(t_rec_rawIn_fractIn_3, 9, 9) node _t_rec_rawIn_normDist_T_142 = bits(t_rec_rawIn_fractIn_3, 10, 10) node _t_rec_rawIn_normDist_T_143 = bits(t_rec_rawIn_fractIn_3, 11, 11) node _t_rec_rawIn_normDist_T_144 = bits(t_rec_rawIn_fractIn_3, 12, 12) node _t_rec_rawIn_normDist_T_145 = bits(t_rec_rawIn_fractIn_3, 13, 13) node _t_rec_rawIn_normDist_T_146 = bits(t_rec_rawIn_fractIn_3, 14, 14) node _t_rec_rawIn_normDist_T_147 = bits(t_rec_rawIn_fractIn_3, 15, 15) node _t_rec_rawIn_normDist_T_148 = bits(t_rec_rawIn_fractIn_3, 16, 16) node _t_rec_rawIn_normDist_T_149 = bits(t_rec_rawIn_fractIn_3, 17, 17) node _t_rec_rawIn_normDist_T_150 = bits(t_rec_rawIn_fractIn_3, 18, 18) node _t_rec_rawIn_normDist_T_151 = bits(t_rec_rawIn_fractIn_3, 19, 19) node _t_rec_rawIn_normDist_T_152 = bits(t_rec_rawIn_fractIn_3, 20, 20) node _t_rec_rawIn_normDist_T_153 = bits(t_rec_rawIn_fractIn_3, 21, 21) node _t_rec_rawIn_normDist_T_154 = bits(t_rec_rawIn_fractIn_3, 22, 22) node _t_rec_rawIn_normDist_T_155 = mux(_t_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_156 = mux(_t_rec_rawIn_normDist_T_134, UInt<5>(0h14), _t_rec_rawIn_normDist_T_155) node _t_rec_rawIn_normDist_T_157 = mux(_t_rec_rawIn_normDist_T_135, UInt<5>(0h13), _t_rec_rawIn_normDist_T_156) node _t_rec_rawIn_normDist_T_158 = mux(_t_rec_rawIn_normDist_T_136, UInt<5>(0h12), _t_rec_rawIn_normDist_T_157) node _t_rec_rawIn_normDist_T_159 = mux(_t_rec_rawIn_normDist_T_137, UInt<5>(0h11), _t_rec_rawIn_normDist_T_158) node _t_rec_rawIn_normDist_T_160 = mux(_t_rec_rawIn_normDist_T_138, UInt<5>(0h10), _t_rec_rawIn_normDist_T_159) node _t_rec_rawIn_normDist_T_161 = mux(_t_rec_rawIn_normDist_T_139, UInt<4>(0hf), _t_rec_rawIn_normDist_T_160) node _t_rec_rawIn_normDist_T_162 = mux(_t_rec_rawIn_normDist_T_140, UInt<4>(0he), _t_rec_rawIn_normDist_T_161) node _t_rec_rawIn_normDist_T_163 = mux(_t_rec_rawIn_normDist_T_141, UInt<4>(0hd), _t_rec_rawIn_normDist_T_162) node _t_rec_rawIn_normDist_T_164 = mux(_t_rec_rawIn_normDist_T_142, UInt<4>(0hc), _t_rec_rawIn_normDist_T_163) node _t_rec_rawIn_normDist_T_165 = mux(_t_rec_rawIn_normDist_T_143, UInt<4>(0hb), _t_rec_rawIn_normDist_T_164) node _t_rec_rawIn_normDist_T_166 = mux(_t_rec_rawIn_normDist_T_144, UInt<4>(0ha), _t_rec_rawIn_normDist_T_165) node _t_rec_rawIn_normDist_T_167 = mux(_t_rec_rawIn_normDist_T_145, UInt<4>(0h9), _t_rec_rawIn_normDist_T_166) node _t_rec_rawIn_normDist_T_168 = mux(_t_rec_rawIn_normDist_T_146, UInt<4>(0h8), _t_rec_rawIn_normDist_T_167) node _t_rec_rawIn_normDist_T_169 = mux(_t_rec_rawIn_normDist_T_147, UInt<3>(0h7), _t_rec_rawIn_normDist_T_168) node _t_rec_rawIn_normDist_T_170 = mux(_t_rec_rawIn_normDist_T_148, UInt<3>(0h6), _t_rec_rawIn_normDist_T_169) node _t_rec_rawIn_normDist_T_171 = mux(_t_rec_rawIn_normDist_T_149, UInt<3>(0h5), _t_rec_rawIn_normDist_T_170) node _t_rec_rawIn_normDist_T_172 = mux(_t_rec_rawIn_normDist_T_150, UInt<3>(0h4), _t_rec_rawIn_normDist_T_171) node _t_rec_rawIn_normDist_T_173 = mux(_t_rec_rawIn_normDist_T_151, UInt<2>(0h3), _t_rec_rawIn_normDist_T_172) node _t_rec_rawIn_normDist_T_174 = mux(_t_rec_rawIn_normDist_T_152, UInt<2>(0h2), _t_rec_rawIn_normDist_T_173) node _t_rec_rawIn_normDist_T_175 = mux(_t_rec_rawIn_normDist_T_153, UInt<1>(0h1), _t_rec_rawIn_normDist_T_174) node t_rec_rawIn_normDist_3 = mux(_t_rec_rawIn_normDist_T_154, UInt<1>(0h0), _t_rec_rawIn_normDist_T_175) node _t_rec_rawIn_subnormFract_T_6 = dshl(t_rec_rawIn_fractIn_3, t_rec_rawIn_normDist_3) node _t_rec_rawIn_subnormFract_T_7 = bits(_t_rec_rawIn_subnormFract_T_6, 21, 0) node t_rec_rawIn_subnormFract_3 = shl(_t_rec_rawIn_subnormFract_T_7, 1) node _t_rec_rawIn_adjustedExp_T_15 = xor(t_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_16 = mux(t_rec_rawIn_isZeroExpIn_3, _t_rec_rawIn_adjustedExp_T_15, t_rec_rawIn_expIn_3) node _t_rec_rawIn_adjustedExp_T_17 = mux(t_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_17) node _t_rec_rawIn_adjustedExp_T_19 = add(_t_rec_rawIn_adjustedExp_T_16, _t_rec_rawIn_adjustedExp_T_18) node t_rec_rawIn_adjustedExp_3 = tail(_t_rec_rawIn_adjustedExp_T_19, 1) node t_rec_rawIn_isZero_3 = and(t_rec_rawIn_isZeroExpIn_3, t_rec_rawIn_isZeroFractIn_3) node _t_rec_rawIn_isSpecial_T_3 = bits(t_rec_rawIn_adjustedExp_3, 8, 7) node t_rec_rawIn_isSpecial_3 = eq(_t_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire t_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T_6 = eq(t_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_7 = and(t_rec_rawIn_isSpecial_3, _t_rec_rawIn_out_isNaN_T_6) connect t_rec_rawIn_3.isNaN, _t_rec_rawIn_out_isNaN_T_7 node _t_rec_rawIn_out_isInf_T_3 = and(t_rec_rawIn_isSpecial_3, t_rec_rawIn_isZeroFractIn_3) connect t_rec_rawIn_3.isInf, _t_rec_rawIn_out_isInf_T_3 connect t_rec_rawIn_3.isZero, t_rec_rawIn_isZero_3 connect t_rec_rawIn_3.sign, t_rec_rawIn_sign_3 node _t_rec_rawIn_out_sExp_T_6 = bits(t_rec_rawIn_adjustedExp_3, 8, 0) node _t_rec_rawIn_out_sExp_T_7 = cvt(_t_rec_rawIn_out_sExp_T_6) connect t_rec_rawIn_3.sExp, _t_rec_rawIn_out_sExp_T_7 node _t_rec_rawIn_out_sig_T_12 = eq(t_rec_rawIn_isZero_3, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T_12) node _t_rec_rawIn_out_sig_T_14 = mux(t_rec_rawIn_isZeroExpIn_3, t_rec_rawIn_subnormFract_3, t_rec_rawIn_fractIn_3) node _t_rec_rawIn_out_sig_T_15 = cat(_t_rec_rawIn_out_sig_T_13, _t_rec_rawIn_out_sig_T_14) connect t_rec_rawIn_3.sig, _t_rec_rawIn_out_sig_T_15 node _t_rec_T_24 = bits(t_rec_rawIn_3.sExp, 8, 6) node _t_rec_T_25 = mux(t_rec_rawIn_3.isZero, UInt<3>(0h0), _t_rec_T_24) node _t_rec_T_26 = mux(t_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_27 = or(_t_rec_T_25, _t_rec_T_26) node _t_rec_T_28 = cat(t_rec_rawIn_3.sign, _t_rec_T_27) node _t_rec_T_29 = bits(t_rec_rawIn_3.sExp, 5, 0) node _t_rec_T_30 = cat(_t_rec_T_28, _t_rec_T_29) node _t_rec_T_31 = bits(t_rec_rawIn_3.sig, 22, 0) node t_rec_3 = cat(_t_rec_T_30, _t_rec_T_31) node self_rec_rawIn_sign_3 = bits(in.bits.in[3].bits, 31, 31) node self_rec_rawIn_expIn_3 = bits(in.bits.in[3].bits, 30, 23) node self_rec_rawIn_fractIn_3 = bits(in.bits.in[3].bits, 22, 0) node self_rec_rawIn_isZeroExpIn_3 = eq(self_rec_rawIn_expIn_3, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn_3 = eq(self_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T_132 = bits(self_rec_rawIn_fractIn_3, 0, 0) node _self_rec_rawIn_normDist_T_133 = bits(self_rec_rawIn_fractIn_3, 1, 1) node _self_rec_rawIn_normDist_T_134 = bits(self_rec_rawIn_fractIn_3, 2, 2) node _self_rec_rawIn_normDist_T_135 = bits(self_rec_rawIn_fractIn_3, 3, 3) node _self_rec_rawIn_normDist_T_136 = bits(self_rec_rawIn_fractIn_3, 4, 4) node _self_rec_rawIn_normDist_T_137 = bits(self_rec_rawIn_fractIn_3, 5, 5) node _self_rec_rawIn_normDist_T_138 = bits(self_rec_rawIn_fractIn_3, 6, 6) node _self_rec_rawIn_normDist_T_139 = bits(self_rec_rawIn_fractIn_3, 7, 7) node _self_rec_rawIn_normDist_T_140 = bits(self_rec_rawIn_fractIn_3, 8, 8) node _self_rec_rawIn_normDist_T_141 = bits(self_rec_rawIn_fractIn_3, 9, 9) node _self_rec_rawIn_normDist_T_142 = bits(self_rec_rawIn_fractIn_3, 10, 10) node _self_rec_rawIn_normDist_T_143 = bits(self_rec_rawIn_fractIn_3, 11, 11) node _self_rec_rawIn_normDist_T_144 = bits(self_rec_rawIn_fractIn_3, 12, 12) node _self_rec_rawIn_normDist_T_145 = bits(self_rec_rawIn_fractIn_3, 13, 13) node _self_rec_rawIn_normDist_T_146 = bits(self_rec_rawIn_fractIn_3, 14, 14) node _self_rec_rawIn_normDist_T_147 = bits(self_rec_rawIn_fractIn_3, 15, 15) node _self_rec_rawIn_normDist_T_148 = bits(self_rec_rawIn_fractIn_3, 16, 16) node _self_rec_rawIn_normDist_T_149 = bits(self_rec_rawIn_fractIn_3, 17, 17) node _self_rec_rawIn_normDist_T_150 = bits(self_rec_rawIn_fractIn_3, 18, 18) node _self_rec_rawIn_normDist_T_151 = bits(self_rec_rawIn_fractIn_3, 19, 19) node _self_rec_rawIn_normDist_T_152 = bits(self_rec_rawIn_fractIn_3, 20, 20) node _self_rec_rawIn_normDist_T_153 = bits(self_rec_rawIn_fractIn_3, 21, 21) node _self_rec_rawIn_normDist_T_154 = bits(self_rec_rawIn_fractIn_3, 22, 22) node _self_rec_rawIn_normDist_T_155 = mux(_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_156 = mux(_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _self_rec_rawIn_normDist_T_155) node _self_rec_rawIn_normDist_T_157 = mux(_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _self_rec_rawIn_normDist_T_156) node _self_rec_rawIn_normDist_T_158 = mux(_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _self_rec_rawIn_normDist_T_157) node _self_rec_rawIn_normDist_T_159 = mux(_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _self_rec_rawIn_normDist_T_158) node _self_rec_rawIn_normDist_T_160 = mux(_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _self_rec_rawIn_normDist_T_159) node _self_rec_rawIn_normDist_T_161 = mux(_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _self_rec_rawIn_normDist_T_160) node _self_rec_rawIn_normDist_T_162 = mux(_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _self_rec_rawIn_normDist_T_161) node _self_rec_rawIn_normDist_T_163 = mux(_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _self_rec_rawIn_normDist_T_162) node _self_rec_rawIn_normDist_T_164 = mux(_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _self_rec_rawIn_normDist_T_163) node _self_rec_rawIn_normDist_T_165 = mux(_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _self_rec_rawIn_normDist_T_164) node _self_rec_rawIn_normDist_T_166 = mux(_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _self_rec_rawIn_normDist_T_165) node _self_rec_rawIn_normDist_T_167 = mux(_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _self_rec_rawIn_normDist_T_166) node _self_rec_rawIn_normDist_T_168 = mux(_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _self_rec_rawIn_normDist_T_167) node _self_rec_rawIn_normDist_T_169 = mux(_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _self_rec_rawIn_normDist_T_168) node _self_rec_rawIn_normDist_T_170 = mux(_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _self_rec_rawIn_normDist_T_169) node _self_rec_rawIn_normDist_T_171 = mux(_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _self_rec_rawIn_normDist_T_170) node _self_rec_rawIn_normDist_T_172 = mux(_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _self_rec_rawIn_normDist_T_171) node _self_rec_rawIn_normDist_T_173 = mux(_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _self_rec_rawIn_normDist_T_172) node _self_rec_rawIn_normDist_T_174 = mux(_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _self_rec_rawIn_normDist_T_173) node _self_rec_rawIn_normDist_T_175 = mux(_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _self_rec_rawIn_normDist_T_174) node self_rec_rawIn_normDist_3 = mux(_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _self_rec_rawIn_normDist_T_175) node _self_rec_rawIn_subnormFract_T_6 = dshl(self_rec_rawIn_fractIn_3, self_rec_rawIn_normDist_3) node _self_rec_rawIn_subnormFract_T_7 = bits(_self_rec_rawIn_subnormFract_T_6, 21, 0) node self_rec_rawIn_subnormFract_3 = shl(_self_rec_rawIn_subnormFract_T_7, 1) node _self_rec_rawIn_adjustedExp_T_15 = xor(self_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_16 = mux(self_rec_rawIn_isZeroExpIn_3, _self_rec_rawIn_adjustedExp_T_15, self_rec_rawIn_expIn_3) node _self_rec_rawIn_adjustedExp_T_17 = mux(self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_17) node _self_rec_rawIn_adjustedExp_T_19 = add(_self_rec_rawIn_adjustedExp_T_16, _self_rec_rawIn_adjustedExp_T_18) node self_rec_rawIn_adjustedExp_3 = tail(_self_rec_rawIn_adjustedExp_T_19, 1) node self_rec_rawIn_isZero_3 = and(self_rec_rawIn_isZeroExpIn_3, self_rec_rawIn_isZeroFractIn_3) node _self_rec_rawIn_isSpecial_T_3 = bits(self_rec_rawIn_adjustedExp_3, 8, 7) node self_rec_rawIn_isSpecial_3 = eq(_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T_6 = eq(self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_7 = and(self_rec_rawIn_isSpecial_3, _self_rec_rawIn_out_isNaN_T_6) connect self_rec_rawIn_3.isNaN, _self_rec_rawIn_out_isNaN_T_7 node _self_rec_rawIn_out_isInf_T_3 = and(self_rec_rawIn_isSpecial_3, self_rec_rawIn_isZeroFractIn_3) connect self_rec_rawIn_3.isInf, _self_rec_rawIn_out_isInf_T_3 connect self_rec_rawIn_3.isZero, self_rec_rawIn_isZero_3 connect self_rec_rawIn_3.sign, self_rec_rawIn_sign_3 node _self_rec_rawIn_out_sExp_T_6 = bits(self_rec_rawIn_adjustedExp_3, 8, 0) node _self_rec_rawIn_out_sExp_T_7 = cvt(_self_rec_rawIn_out_sExp_T_6) connect self_rec_rawIn_3.sExp, _self_rec_rawIn_out_sExp_T_7 node _self_rec_rawIn_out_sig_T_12 = eq(self_rec_rawIn_isZero_3, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_12) node _self_rec_rawIn_out_sig_T_14 = mux(self_rec_rawIn_isZeroExpIn_3, self_rec_rawIn_subnormFract_3, self_rec_rawIn_fractIn_3) node _self_rec_rawIn_out_sig_T_15 = cat(_self_rec_rawIn_out_sig_T_13, _self_rec_rawIn_out_sig_T_14) connect self_rec_rawIn_3.sig, _self_rec_rawIn_out_sig_T_15 node _self_rec_T_24 = bits(self_rec_rawIn_3.sExp, 8, 6) node _self_rec_T_25 = mux(self_rec_rawIn_3.isZero, UInt<3>(0h0), _self_rec_T_24) node _self_rec_T_26 = mux(self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_27 = or(_self_rec_T_25, _self_rec_T_26) node _self_rec_T_28 = cat(self_rec_rawIn_3.sign, _self_rec_T_27) node _self_rec_T_29 = bits(self_rec_rawIn_3.sExp, 5, 0) node _self_rec_T_30 = cat(_self_rec_T_28, _self_rec_T_29) node _self_rec_T_31 = bits(self_rec_rawIn_3.sig, 22, 0) node self_rec_3 = cat(_self_rec_T_30, _self_rec_T_31) inst t_resizer_3 of RecFNToRecFN_11 connect t_resizer_3.io.in, t_rec_3 connect t_resizer_3.io.roundingMode, UInt<3>(0h0) connect t_resizer_3.io.detectTininess, UInt<1>(0h1) inst muladder_3 of MulRecFN_7 connect muladder_3.io.roundingMode, UInt<3>(0h0) connect muladder_3.io.detectTininess, UInt<1>(0h1) connect muladder_3.io.a, self_rec_3 connect muladder_3.io.b, t_resizer_3.io.out wire out_3 : { bits : UInt<32>} node out_bits_rawIn_exp_3 = bits(muladder_3.io.out, 31, 23) node _out_bits_rawIn_isZero_T_3 = bits(out_bits_rawIn_exp_3, 8, 6) node out_bits_rawIn_isZero_3 = eq(_out_bits_rawIn_isZero_T_3, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T_3 = bits(out_bits_rawIn_exp_3, 8, 7) node out_bits_rawIn_isSpecial_3 = eq(_out_bits_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire out_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T_6 = bits(out_bits_rawIn_exp_3, 6, 6) node _out_bits_rawIn_out_isNaN_T_7 = and(out_bits_rawIn_isSpecial_3, _out_bits_rawIn_out_isNaN_T_6) connect out_bits_rawIn_3.isNaN, _out_bits_rawIn_out_isNaN_T_7 node _out_bits_rawIn_out_isInf_T_9 = bits(out_bits_rawIn_exp_3, 6, 6) node _out_bits_rawIn_out_isInf_T_10 = eq(_out_bits_rawIn_out_isInf_T_9, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_11 = and(out_bits_rawIn_isSpecial_3, _out_bits_rawIn_out_isInf_T_10) connect out_bits_rawIn_3.isInf, _out_bits_rawIn_out_isInf_T_11 connect out_bits_rawIn_3.isZero, out_bits_rawIn_isZero_3 node _out_bits_rawIn_out_sign_T_3 = bits(muladder_3.io.out, 32, 32) connect out_bits_rawIn_3.sign, _out_bits_rawIn_out_sign_T_3 node _out_bits_rawIn_out_sExp_T_3 = cvt(out_bits_rawIn_exp_3) connect out_bits_rawIn_3.sExp, _out_bits_rawIn_out_sExp_T_3 node _out_bits_rawIn_out_sig_T_12 = eq(out_bits_rawIn_isZero_3, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T_12) node _out_bits_rawIn_out_sig_T_14 = bits(muladder_3.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_15 = cat(_out_bits_rawIn_out_sig_T_13, _out_bits_rawIn_out_sig_T_14) connect out_bits_rawIn_3.sig, _out_bits_rawIn_out_sig_T_15 node out_bits_isSubnormal_3 = lt(out_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T_6 = bits(out_bits_rawIn_3.sExp, 4, 0) node _out_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T_6) node out_bits_denormShiftDist_3 = tail(_out_bits_denormShiftDist_T_7, 1) node _out_bits_denormFract_T_6 = shr(out_bits_rawIn_3.sig, 1) node _out_bits_denormFract_T_7 = dshr(_out_bits_denormFract_T_6, out_bits_denormShiftDist_3) node out_bits_denormFract_3 = bits(_out_bits_denormFract_T_7, 22, 0) node _out_bits_expOut_T_18 = bits(out_bits_rawIn_3.sExp, 7, 0) node _out_bits_expOut_T_19 = sub(_out_bits_expOut_T_18, UInt<8>(0h81)) node _out_bits_expOut_T_20 = tail(_out_bits_expOut_T_19, 1) node _out_bits_expOut_T_21 = mux(out_bits_isSubnormal_3, UInt<1>(0h0), _out_bits_expOut_T_20) node _out_bits_expOut_T_22 = or(out_bits_rawIn_3.isNaN, out_bits_rawIn_3.isInf) node _out_bits_expOut_T_23 = mux(_out_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut_3 = or(_out_bits_expOut_T_21, _out_bits_expOut_T_23) node _out_bits_fractOut_T_6 = bits(out_bits_rawIn_3.sig, 22, 0) node _out_bits_fractOut_T_7 = mux(out_bits_rawIn_3.isInf, UInt<1>(0h0), _out_bits_fractOut_T_6) node out_bits_fractOut_3 = mux(out_bits_isSubnormal_3, out_bits_denormFract_3, _out_bits_fractOut_T_7) node out_bits_hi_3 = cat(out_bits_rawIn_3.sign, out_bits_expOut_3) node _out_bits_T_3 = cat(out_bits_hi_3, out_bits_fractOut_3) connect out_3.bits, _out_bits_T_3 connect pipe.io.in.bits.out[0].bits, out.bits connect pipe.io.in.bits.out[1].bits, out_1.bits connect pipe.io.in.bits.out[2].bits, out_2.bits connect pipe.io.in.bits.out[3].bits, out_3.bits	module VectorScalarMultiplier_1( // @[VectorScalarMultiplier.scala:45:7] input clock, // @[VectorScalarMultiplier.scala:45:7] input reset, // @[VectorScalarMultiplier.scala:45:7] output io_req_ready, // @[VectorScalarMultiplier.scala:54:14] input io_req_valid, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_0_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_1_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_2_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_3_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_scale_bits, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_repeats, // @[VectorScalarMultiplier.scala:54:14] input [7:0] io_req_bits_pixel_repeats, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_last, // @[VectorScalarMultiplier.scala:54:14] input [127:0] io_req_bits_tag_data, // @[VectorScalarMultiplier.scala:54:14] input [13:0] io_req_bits_tag_addr, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_0, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_1, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_2, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_3, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_4, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_5, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_6, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_7, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_8, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_9, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_10, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_11, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_12, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_13, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_14, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_15, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_is_acc, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_accumulate, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_has_acc_bitwidth, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_tag_scale, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_tag_repeats, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_tag_pixel_repeats, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_tag_len, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_last, // @[VectorScalarMultiplier.scala:54:14] input [7:0] io_req_bits_tag_bytes_read, // @[VectorScalarMultiplier.scala:54:14] input [7:0] io_req_bits_tag_cmd_id, // @[VectorScalarMultiplier.scala:54:14] input io_resp_ready, // @[VectorScalarMultiplier.scala:54:14] output io_resp_valid, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_0_bits, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_1_bits, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_2_bits, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_3_bits, // @[VectorScalarMultiplier.scala:54:14] output [15:0] io_resp_bits_row, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_last, // @[VectorScalarMultiplier.scala:54:14] output [13:0] io_resp_bits_tag_addr, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_0, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_1, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_2, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_3, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_4, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_5, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_6, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_7, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_8, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_9, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_10, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_11, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_12, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_13, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_14, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_15, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_is_acc, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_accumulate, // @[VectorScalarMultiplier.scala:54:14] output [7:0] io_resp_bits_tag_bytes_read, // @[VectorScalarMultiplier.scala:54:14] output [7:0] io_resp_bits_tag_cmd_id // @[VectorScalarMultiplier.scala:54:14] ); wire self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _muladder_3_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_3_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _muladder_2_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_2_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _muladder_1_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_1_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _muladder_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_io_out; // @[Arithmetic.scala:336:32] wire _pipe_io_in_ready; // @[VectorScalarMultiplier.scala:83:22] wire io_req_valid_0 = io_req_valid; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_0_bits_0 = io_req_bits_in_0_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_1_bits_0 = io_req_bits_in_1_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_2_bits_0 = io_req_bits_in_2_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_3_bits_0 = io_req_bits_in_3_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_scale_bits_0 = io_req_bits_scale_bits; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_last_0 = io_req_bits_last; // @[VectorScalarMultiplier.scala:45:7] wire [127:0] io_req_bits_tag_data_0 = io_req_bits_tag_data; // @[VectorScalarMultiplier.scala:45:7] wire [13:0] io_req_bits_tag_addr_0 = io_req_bits_tag_addr; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_0_0 = io_req_bits_tag_mask_0; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_1_0 = io_req_bits_tag_mask_1; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_2_0 = io_req_bits_tag_mask_2; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_3_0 = io_req_bits_tag_mask_3; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_4_0 = io_req_bits_tag_mask_4; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_5_0 = io_req_bits_tag_mask_5; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_6_0 = io_req_bits_tag_mask_6; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_7_0 = io_req_bits_tag_mask_7; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_8_0 = io_req_bits_tag_mask_8; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_9_0 = io_req_bits_tag_mask_9; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_10_0 = io_req_bits_tag_mask_10; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_11_0 = io_req_bits_tag_mask_11; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_12_0 = io_req_bits_tag_mask_12; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_13_0 = io_req_bits_tag_mask_13; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_14_0 = io_req_bits_tag_mask_14; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_15_0 = io_req_bits_tag_mask_15; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_is_acc_0 = io_req_bits_tag_is_acc; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_accumulate_0 = io_req_bits_tag_accumulate; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_has_acc_bitwidth_0 = io_req_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_tag_scale_0 = io_req_bits_tag_scale; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_tag_repeats_0 = io_req_bits_tag_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_tag_pixel_repeats_0 = io_req_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_tag_len_0 = io_req_bits_tag_len; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_last_0 = io_req_bits_tag_last; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_req_bits_tag_bytes_read_0 = io_req_bits_tag_bytes_read; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_req_bits_tag_cmd_id_0 = io_req_bits_tag_cmd_id; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_ready_0 = io_resp_ready; // @[VectorScalarMultiplier.scala:45:7] wire _io_req_ready_T_3; // @[VectorScalarMultiplier.scala:67:29] wire io_req_ready_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_0_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_1_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_2_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_3_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7] wire [127:0] io_resp_bits_tag_data; // @[VectorScalarMultiplier.scala:45:7] wire [13:0] io_resp_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_tag_scale; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_tag_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_tag_len; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_last; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_resp_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_resp_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_row_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_last_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_valid_0; // @[VectorScalarMultiplier.scala:45:7] reg in_valid; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_0_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_1_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_2_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_3_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_scale_bits; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_repeats; // @[VectorScalarMultiplier.scala:65:15] reg [7:0] in_bits_pixel_repeats; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_last; // @[VectorScalarMultiplier.scala:65:15] reg [127:0] in_bits_tag_data; // @[VectorScalarMultiplier.scala:65:15] reg [13:0] in_bits_tag_addr; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_0; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_1; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_2; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_3; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_4; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_5; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_6; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_7; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_8; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_9; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_10; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_11; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_12; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_13; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_14; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_15; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_is_acc; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_accumulate; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_tag_scale; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_tag_repeats; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_tag_len; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_last; // @[VectorScalarMultiplier.scala:65:15] reg [7:0] in_bits_tag_bytes_read; // @[VectorScalarMultiplier.scala:65:15] reg [7:0] in_bits_tag_cmd_id; // @[VectorScalarMultiplier.scala:65:15] wire _in_fire_T; // @[Decoupled.scala:51:35] wire in_fire; // @[VectorScalarMultiplier.scala:66:25] wire _io_req_ready_T = ~in_valid; // @[VectorScalarMultiplier.scala:65:15, :67:19] wire _T_1 = in_bits_repeats == 16'h0; // @[VectorScalarMultiplier.scala:65:15, :67:49] wire _io_req_ready_T_1; // @[VectorScalarMultiplier.scala:67:49] assign _io_req_ready_T_1 = _T_1; // @[VectorScalarMultiplier.scala:67:49] wire _pipe_io_in_bits_last_T; // @[VectorScalarMultiplier.scala:92:45] assign _pipe_io_in_bits_last_T = _T_1; // @[VectorScalarMultiplier.scala:67:49, :92:45] wire _io_req_ready_T_2 = _io_req_ready_T_1 & in_fire; // @[VectorScalarMultiplier.scala:66:25, :67:{49,57}] assign _io_req_ready_T_3 = _io_req_ready_T \| _io_req_ready_T_2; // @[VectorScalarMultiplier.scala:67:{19,29,57}] assign io_req_ready_0 = _io_req_ready_T_3; // @[VectorScalarMultiplier.scala:45:7, :67:29] wire [16:0] _in_bits_repeats_T = {1'h0, in_bits_repeats} - 17'h1; // @[VectorScalarMultiplier.scala:65:15, :76:40] wire [15:0] _in_bits_repeats_T_1 = _in_bits_repeats_T[15:0]; // @[VectorScalarMultiplier.scala:76:40] assign _in_fire_T = _pipe_io_in_ready & in_valid; // @[Decoupled.scala:51:35] assign in_fire = _in_fire_T; // @[Decoupled.scala:51:35] wire _pipe_io_in_bits_last_T_1 = _pipe_io_in_bits_last_T & in_bits_last; // @[VectorScalarMultiplier.scala:65:15, :92:{45,53}] wire t_rec_rawIn_sign = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_1 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_2 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_3 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_0 = t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] t_rec_rawIn_expIn = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] t_rec_rawIn_expIn_1 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] t_rec_rawIn_expIn_2 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] t_rec_rawIn_expIn_3 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] t_rec_rawIn_fractIn = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] t_rec_rawIn_fractIn_1 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] t_rec_rawIn_fractIn_2 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] t_rec_rawIn_fractIn_3 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire t_rec_rawIn_isZeroExpIn = t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn = t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T = t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_1 = t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_2 = t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_3 = t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_4 = t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_5 = t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_6 = t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_7 = t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_8 = t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_9 = t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_10 = t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_11 = t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_12 = t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_13 = t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_14 = t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_15 = t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_16 = t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_17 = t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_18 = t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_19 = t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_20 = t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_21 = t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_22 = t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_23 = _t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_24 = _t_rec_rawIn_normDist_T_2 ? 5'h14 : _t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_25 = _t_rec_rawIn_normDist_T_3 ? 5'h13 : _t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_26 = _t_rec_rawIn_normDist_T_4 ? 5'h12 : _t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_27 = _t_rec_rawIn_normDist_T_5 ? 5'h11 : _t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_28 = _t_rec_rawIn_normDist_T_6 ? 5'h10 : _t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_29 = _t_rec_rawIn_normDist_T_7 ? 5'hF : _t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_30 = _t_rec_rawIn_normDist_T_8 ? 5'hE : _t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_31 = _t_rec_rawIn_normDist_T_9 ? 5'hD : _t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_32 = _t_rec_rawIn_normDist_T_10 ? 5'hC : _t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_33 = _t_rec_rawIn_normDist_T_11 ? 5'hB : _t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_34 = _t_rec_rawIn_normDist_T_12 ? 5'hA : _t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_35 = _t_rec_rawIn_normDist_T_13 ? 5'h9 : _t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_36 = _t_rec_rawIn_normDist_T_14 ? 5'h8 : _t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_37 = _t_rec_rawIn_normDist_T_15 ? 5'h7 : _t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_38 = _t_rec_rawIn_normDist_T_16 ? 5'h6 : _t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_39 = _t_rec_rawIn_normDist_T_17 ? 5'h5 : _t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_40 = _t_rec_rawIn_normDist_T_18 ? 5'h4 : _t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_41 = _t_rec_rawIn_normDist_T_19 ? 5'h3 : _t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_42 = _t_rec_rawIn_normDist_T_20 ? 5'h2 : _t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_43 = _t_rec_rawIn_normDist_T_21 ? 5'h1 : _t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist = _t_rec_rawIn_normDist_T_22 ? 5'h0 : _t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T = {31'h0, t_rec_rawIn_fractIn} << t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_1 = _t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract = {_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T = {4'hF, ~t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_1 = t_rec_rawIn_isZeroExpIn ? _t_rec_rawIn_adjustedExp_T : {1'h0, t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_2 = t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_3 = {6'h20, _t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_4 = {1'h0, _t_rec_rawIn_adjustedExp_T_1} + {2'h0, _t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp = _t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T = t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero = t_rec_rawIn_isZeroExpIn & t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_isZero_0 = t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T = t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial = &_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_2 = t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T = ~t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_1 = t_rec_rawIn_isSpecial & _t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_isNaN = _t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T = t_rec_rawIn_isSpecial & t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_isInf = _t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_1 = {1'h0, _t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_sExp = _t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T = ~t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_1 = {1'h0, _t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_2 = t_rec_rawIn_isZeroExpIn ? t_rec_rawIn_subnormFract : t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_3 = {_t_rec_rawIn_out_sig_T_1, _t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_sig = _t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T = t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_1 = t_rec_rawIn_isZero_0 ? 3'h0 : _t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_3 = {_t_rec_T_1[2:1], _t_rec_T_1[0] \| _t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_4 = {t_rec_rawIn_sign_0, _t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_5 = t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_6 = {_t_rec_T_4, _t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_7 = t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec = {_t_rec_T_6, _t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign = in_bits_in_0_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_sign_0 = self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn = in_bits_in_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn = in_bits_in_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn = self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn = self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T = self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_1 = self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_2 = self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_3 = self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_4 = self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_5 = self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_6 = self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_7 = self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_8 = self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_9 = self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_10 = self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_11 = self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_12 = self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_13 = self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_14 = self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_15 = self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_16 = self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_17 = self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_18 = self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_19 = self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_20 = self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_21 = self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_22 = self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_23 = _self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_24 = _self_rec_rawIn_normDist_T_2 ? 5'h14 : _self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_25 = _self_rec_rawIn_normDist_T_3 ? 5'h13 : _self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_26 = _self_rec_rawIn_normDist_T_4 ? 5'h12 : _self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_27 = _self_rec_rawIn_normDist_T_5 ? 5'h11 : _self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_28 = _self_rec_rawIn_normDist_T_6 ? 5'h10 : _self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_29 = _self_rec_rawIn_normDist_T_7 ? 5'hF : _self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_30 = _self_rec_rawIn_normDist_T_8 ? 5'hE : _self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_31 = _self_rec_rawIn_normDist_T_9 ? 5'hD : _self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_32 = _self_rec_rawIn_normDist_T_10 ? 5'hC : _self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_33 = _self_rec_rawIn_normDist_T_11 ? 5'hB : _self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_34 = _self_rec_rawIn_normDist_T_12 ? 5'hA : _self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_35 = _self_rec_rawIn_normDist_T_13 ? 5'h9 : _self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_36 = _self_rec_rawIn_normDist_T_14 ? 5'h8 : _self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_37 = _self_rec_rawIn_normDist_T_15 ? 5'h7 : _self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_38 = _self_rec_rawIn_normDist_T_16 ? 5'h6 : _self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_39 = _self_rec_rawIn_normDist_T_17 ? 5'h5 : _self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_40 = _self_rec_rawIn_normDist_T_18 ? 5'h4 : _self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_41 = _self_rec_rawIn_normDist_T_19 ? 5'h3 : _self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_42 = _self_rec_rawIn_normDist_T_20 ? 5'h2 : _self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_43 = _self_rec_rawIn_normDist_T_21 ? 5'h1 : _self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist = _self_rec_rawIn_normDist_T_22 ? 5'h0 : _self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T = {31'h0, self_rec_rawIn_fractIn} << self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_1 = _self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract = {_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T = {4'hF, ~self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_1 = self_rec_rawIn_isZeroExpIn ? _self_rec_rawIn_adjustedExp_T : {1'h0, self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_2 = self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_3 = {6'h20, _self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_4 = {1'h0, _self_rec_rawIn_adjustedExp_T_1} + {2'h0, _self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp = _self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T = self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero = self_rec_rawIn_isZeroExpIn & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_isZero_0 = self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T = self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial = &_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_2 = self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T = ~self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_1 = self_rec_rawIn_isSpecial & _self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_isNaN = _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T = self_rec_rawIn_isSpecial & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_isInf = _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_1 = {1'h0, _self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_sExp = _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T = ~self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_1 = {1'h0, _self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_2 = self_rec_rawIn_isZeroExpIn ? self_rec_rawIn_subnormFract : self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_3 = {_self_rec_rawIn_out_sig_T_1, _self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_sig = _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T = self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_1 = self_rec_rawIn_isZero_0 ? 3'h0 : _self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_3 = {_self_rec_T_1[2:1], _self_rec_T_1[0] \| _self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_4 = {self_rec_rawIn_sign_0, _self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_5 = self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_6 = {_self_rec_T_4, _self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_7 = self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec = {_self_rec_T_6, _self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] out_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp = _muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T = out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero = _out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_isZero_0 = out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T = out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial = &_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T = out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T = out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_1 = out_bits_rawIn_isSpecial & _out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_isNaN = _out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_1 = ~_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_2 = out_bits_rawIn_isSpecial & _out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_isInf = _out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T = _muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_sign = _out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T = {1'h0, out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_sExp = _out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T = ~out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_1 = {1'h0, _out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_2 = _muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_3 = {_out_bits_rawIn_out_sig_T_1, _out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_sig = _out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal = $signed(out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T = out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist = _out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T = out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_1 = _out_bits_denormFract_T >> out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract = _out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T = out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_1 = {1'h0, _out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_2 = _out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_3 = out_bits_isSubnormal ? 8'h0 : _out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_4 = out_bits_rawIn_isNaN \| out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_5 = {8{_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut = _out_bits_expOut_T_3 \| _out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T = out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_1 = out_bits_rawIn_isInf ? 23'h0 : _out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut = out_bits_isSubnormal ? out_bits_denormFract : _out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi = {out_bits_rawIn_sign, out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T = {out_bits_hi, out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_bits = _out_bits_T; // @[fNFromRecFN.scala:66:12] wire t_rec_rawIn_1_sign = t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire t_rec_rawIn_isZeroExpIn_1 = t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn_1 = t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T_44 = t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_45 = t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_46 = t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_47 = t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_48 = t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_49 = t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_50 = t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_51 = t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_52 = t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_53 = t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_54 = t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_55 = t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_56 = t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_57 = t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_58 = t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_59 = t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_60 = t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_61 = t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_62 = t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_63 = t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_64 = t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_65 = t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_66 = t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_67 = _t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_68 = _t_rec_rawIn_normDist_T_46 ? 5'h14 : _t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_69 = _t_rec_rawIn_normDist_T_47 ? 5'h13 : _t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_70 = _t_rec_rawIn_normDist_T_48 ? 5'h12 : _t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_71 = _t_rec_rawIn_normDist_T_49 ? 5'h11 : _t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_72 = _t_rec_rawIn_normDist_T_50 ? 5'h10 : _t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_73 = _t_rec_rawIn_normDist_T_51 ? 5'hF : _t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_74 = _t_rec_rawIn_normDist_T_52 ? 5'hE : _t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_75 = _t_rec_rawIn_normDist_T_53 ? 5'hD : _t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_76 = _t_rec_rawIn_normDist_T_54 ? 5'hC : _t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_77 = _t_rec_rawIn_normDist_T_55 ? 5'hB : _t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_78 = _t_rec_rawIn_normDist_T_56 ? 5'hA : _t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_79 = _t_rec_rawIn_normDist_T_57 ? 5'h9 : _t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_80 = _t_rec_rawIn_normDist_T_58 ? 5'h8 : _t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_81 = _t_rec_rawIn_normDist_T_59 ? 5'h7 : _t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_82 = _t_rec_rawIn_normDist_T_60 ? 5'h6 : _t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_83 = _t_rec_rawIn_normDist_T_61 ? 5'h5 : _t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_84 = _t_rec_rawIn_normDist_T_62 ? 5'h4 : _t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_85 = _t_rec_rawIn_normDist_T_63 ? 5'h3 : _t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_86 = _t_rec_rawIn_normDist_T_64 ? 5'h2 : _t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_87 = _t_rec_rawIn_normDist_T_65 ? 5'h1 : _t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist_1 = _t_rec_rawIn_normDist_T_66 ? 5'h0 : _t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T_2 = {31'h0, t_rec_rawIn_fractIn_1} << t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_3 = _t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract_1 = {_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_6 = t_rec_rawIn_isZeroExpIn_1 ? _t_rec_rawIn_adjustedExp_T_5 : {1'h0, t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_7 = t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_8 = {6'h20, _t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_9 = {1'h0, _t_rec_rawIn_adjustedExp_T_6} + {2'h0, _t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp_1 = _t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T_2 = t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero_1 = t_rec_rawIn_isZeroExpIn_1 & t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_1_isZero = t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T_1 = t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial_1 = &_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_10 = t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T_2 = ~t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_3 = t_rec_rawIn_isSpecial_1 & _t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_1_isNaN = _t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T_1 = t_rec_rawIn_isSpecial_1 & t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_1_isInf = _t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_3 = {1'h0, _t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_1_sExp = _t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T_4 = ~t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_5 = {1'h0, _t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_6 = t_rec_rawIn_isZeroExpIn_1 ? t_rec_rawIn_subnormFract_1 : t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_7 = {_t_rec_rawIn_out_sig_T_5, _t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_1_sig = _t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T_8 = t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_9 = t_rec_rawIn_1_isZero ? 3'h0 : _t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_11 = {_t_rec_T_9[2:1], _t_rec_T_9[0] \| _t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_12 = {t_rec_rawIn_1_sign, _t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_13 = t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_14 = {_t_rec_T_12, _t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_15 = t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec_1 = {_t_rec_T_14, _t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign_1 = in_bits_in_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_1_sign = self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn_1 = in_bits_in_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn_1 = in_bits_in_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn_1 = self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn_1 = self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T_44 = self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_45 = self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_46 = self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_47 = self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_48 = self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_49 = self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_50 = self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_51 = self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_52 = self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_53 = self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_54 = self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_55 = self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_56 = self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_57 = self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_58 = self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_59 = self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_60 = self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_61 = self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_62 = self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_63 = self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_64 = self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_65 = self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_66 = self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_67 = _self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_68 = _self_rec_rawIn_normDist_T_46 ? 5'h14 : _self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_69 = _self_rec_rawIn_normDist_T_47 ? 5'h13 : _self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_70 = _self_rec_rawIn_normDist_T_48 ? 5'h12 : _self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_71 = _self_rec_rawIn_normDist_T_49 ? 5'h11 : _self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_72 = _self_rec_rawIn_normDist_T_50 ? 5'h10 : _self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_73 = _self_rec_rawIn_normDist_T_51 ? 5'hF : _self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_74 = _self_rec_rawIn_normDist_T_52 ? 5'hE : _self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_75 = _self_rec_rawIn_normDist_T_53 ? 5'hD : _self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_76 = _self_rec_rawIn_normDist_T_54 ? 5'hC : _self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_77 = _self_rec_rawIn_normDist_T_55 ? 5'hB : _self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_78 = _self_rec_rawIn_normDist_T_56 ? 5'hA : _self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_79 = _self_rec_rawIn_normDist_T_57 ? 5'h9 : _self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_80 = _self_rec_rawIn_normDist_T_58 ? 5'h8 : _self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_81 = _self_rec_rawIn_normDist_T_59 ? 5'h7 : _self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_82 = _self_rec_rawIn_normDist_T_60 ? 5'h6 : _self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_83 = _self_rec_rawIn_normDist_T_61 ? 5'h5 : _self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_84 = _self_rec_rawIn_normDist_T_62 ? 5'h4 : _self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_85 = _self_rec_rawIn_normDist_T_63 ? 5'h3 : _self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_86 = _self_rec_rawIn_normDist_T_64 ? 5'h2 : _self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_87 = _self_rec_rawIn_normDist_T_65 ? 5'h1 : _self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist_1 = _self_rec_rawIn_normDist_T_66 ? 5'h0 : _self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T_2 = {31'h0, self_rec_rawIn_fractIn_1} << self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_3 = _self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract_1 = {_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_6 = self_rec_rawIn_isZeroExpIn_1 ? _self_rec_rawIn_adjustedExp_T_5 : {1'h0, self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_7 = self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_8 = {6'h20, _self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_9 = {1'h0, _self_rec_rawIn_adjustedExp_T_6} + {2'h0, _self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp_1 = _self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T_2 = self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero_1 = self_rec_rawIn_isZeroExpIn_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_1_isZero = self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T_1 = self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial_1 = &_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_10 = self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T_2 = ~self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_3 = self_rec_rawIn_isSpecial_1 & _self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_1_isNaN = _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T_1 = self_rec_rawIn_isSpecial_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_1_isInf = _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_3 = {1'h0, _self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_1_sExp = _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T_4 = ~self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_5 = {1'h0, _self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_6 = self_rec_rawIn_isZeroExpIn_1 ? self_rec_rawIn_subnormFract_1 : self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_7 = {_self_rec_rawIn_out_sig_T_5, _self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_1_sig = _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T_8 = self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_9 = self_rec_rawIn_1_isZero ? 3'h0 : _self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_11 = {_self_rec_T_9[2:1], _self_rec_T_9[0] \| _self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_12 = {self_rec_rawIn_1_sign, _self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_13 = self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_14 = {_self_rec_T_12, _self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_15 = self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec_1 = {_self_rec_T_14, _self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] out_1_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp_1 = _muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T_1 = out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero_1 = _out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_1_isZero = out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T_1 = out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial_1 = &_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T_2 = out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T_3 = out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_3 = out_bits_rawIn_isSpecial_1 & _out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_1_isNaN = _out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_4 = ~_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_5 = out_bits_rawIn_isSpecial_1 & _out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_1_isInf = _out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T_1 = _muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_1_sign = _out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T_1 = {1'h0, out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_1_sExp = _out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T_4 = ~out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_5 = {1'h0, _out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_6 = _muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_7 = {_out_bits_rawIn_out_sig_T_5, _out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_1_sig = _out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal_1 = $signed(out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T_2 = out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist_1 = _out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T_2 = out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_3 = _out_bits_denormFract_T_2 >> out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract_1 = _out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T_6 = out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_7 = {1'h0, _out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_8 = _out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_9 = out_bits_isSubnormal_1 ? 8'h0 : _out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_10 = out_bits_rawIn_1_isNaN \| out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_11 = {8{_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut_1 = _out_bits_expOut_T_9 \| _out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T_2 = out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_3 = out_bits_rawIn_1_isInf ? 23'h0 : _out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut_1 = out_bits_isSubnormal_1 ? out_bits_denormFract_1 : _out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi_1 = {out_bits_rawIn_1_sign, out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T_1 = {out_bits_hi_1, out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_1_bits = _out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire t_rec_rawIn_2_sign = t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire t_rec_rawIn_isZeroExpIn_2 = t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn_2 = t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T_88 = t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_89 = t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_90 = t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_91 = t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_92 = t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_93 = t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_94 = t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_95 = t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_96 = t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_97 = t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_98 = t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_99 = t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_100 = t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_101 = t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_102 = t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_103 = t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_104 = t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_105 = t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_106 = t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_107 = t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_108 = t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_109 = t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_110 = t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_111 = _t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_112 = _t_rec_rawIn_normDist_T_90 ? 5'h14 : _t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_113 = _t_rec_rawIn_normDist_T_91 ? 5'h13 : _t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_114 = _t_rec_rawIn_normDist_T_92 ? 5'h12 : _t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_115 = _t_rec_rawIn_normDist_T_93 ? 5'h11 : _t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_116 = _t_rec_rawIn_normDist_T_94 ? 5'h10 : _t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_117 = _t_rec_rawIn_normDist_T_95 ? 5'hF : _t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_118 = _t_rec_rawIn_normDist_T_96 ? 5'hE : _t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_119 = _t_rec_rawIn_normDist_T_97 ? 5'hD : _t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_120 = _t_rec_rawIn_normDist_T_98 ? 5'hC : _t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_121 = _t_rec_rawIn_normDist_T_99 ? 5'hB : _t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_122 = _t_rec_rawIn_normDist_T_100 ? 5'hA : _t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_123 = _t_rec_rawIn_normDist_T_101 ? 5'h9 : _t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_124 = _t_rec_rawIn_normDist_T_102 ? 5'h8 : _t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_125 = _t_rec_rawIn_normDist_T_103 ? 5'h7 : _t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_126 = _t_rec_rawIn_normDist_T_104 ? 5'h6 : _t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_127 = _t_rec_rawIn_normDist_T_105 ? 5'h5 : _t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_128 = _t_rec_rawIn_normDist_T_106 ? 5'h4 : _t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_129 = _t_rec_rawIn_normDist_T_107 ? 5'h3 : _t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_130 = _t_rec_rawIn_normDist_T_108 ? 5'h2 : _t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_131 = _t_rec_rawIn_normDist_T_109 ? 5'h1 : _t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist_2 = _t_rec_rawIn_normDist_T_110 ? 5'h0 : _t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T_4 = {31'h0, t_rec_rawIn_fractIn_2} << t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_5 = _t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract_2 = {_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_11 = t_rec_rawIn_isZeroExpIn_2 ? _t_rec_rawIn_adjustedExp_T_10 : {1'h0, t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_12 = t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_13 = {6'h20, _t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_14 = {1'h0, _t_rec_rawIn_adjustedExp_T_11} + {2'h0, _t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp_2 = _t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T_4 = t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero_2 = t_rec_rawIn_isZeroExpIn_2 & t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_2_isZero = t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T_2 = t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial_2 = &_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_18 = t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T_4 = ~t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_5 = t_rec_rawIn_isSpecial_2 & _t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_2_isNaN = _t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T_2 = t_rec_rawIn_isSpecial_2 & t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_2_isInf = _t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_5 = {1'h0, _t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_2_sExp = _t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T_8 = ~t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_9 = {1'h0, _t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_10 = t_rec_rawIn_isZeroExpIn_2 ? t_rec_rawIn_subnormFract_2 : t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_11 = {_t_rec_rawIn_out_sig_T_9, _t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_2_sig = _t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T_16 = t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_17 = t_rec_rawIn_2_isZero ? 3'h0 : _t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_19 = {_t_rec_T_17[2:1], _t_rec_T_17[0] \| _t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_20 = {t_rec_rawIn_2_sign, _t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_21 = t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_22 = {_t_rec_T_20, _t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_23 = t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec_2 = {_t_rec_T_22, _t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign_2 = in_bits_in_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_2_sign = self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn_2 = in_bits_in_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn_2 = in_bits_in_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn_2 = self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn_2 = self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T_88 = self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_89 = self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_90 = self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_91 = self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_92 = self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_93 = self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_94 = self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_95 = self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_96 = self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_97 = self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_98 = self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_99 = self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_100 = self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_101 = self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_102 = self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_103 = self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_104 = self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_105 = self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_106 = self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_107 = self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_108 = self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_109 = self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_110 = self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_111 = _self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_112 = _self_rec_rawIn_normDist_T_90 ? 5'h14 : _self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_113 = _self_rec_rawIn_normDist_T_91 ? 5'h13 : _self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_114 = _self_rec_rawIn_normDist_T_92 ? 5'h12 : _self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_115 = _self_rec_rawIn_normDist_T_93 ? 5'h11 : _self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_116 = _self_rec_rawIn_normDist_T_94 ? 5'h10 : _self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_117 = _self_rec_rawIn_normDist_T_95 ? 5'hF : _self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_118 = _self_rec_rawIn_normDist_T_96 ? 5'hE : _self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_119 = _self_rec_rawIn_normDist_T_97 ? 5'hD : _self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_120 = _self_rec_rawIn_normDist_T_98 ? 5'hC : _self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_121 = _self_rec_rawIn_normDist_T_99 ? 5'hB : _self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_122 = _self_rec_rawIn_normDist_T_100 ? 5'hA : _self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_123 = _self_rec_rawIn_normDist_T_101 ? 5'h9 : _self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_124 = _self_rec_rawIn_normDist_T_102 ? 5'h8 : _self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_125 = _self_rec_rawIn_normDist_T_103 ? 5'h7 : _self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_126 = _self_rec_rawIn_normDist_T_104 ? 5'h6 : _self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_127 = _self_rec_rawIn_normDist_T_105 ? 5'h5 : _self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_128 = _self_rec_rawIn_normDist_T_106 ? 5'h4 : _self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_129 = _self_rec_rawIn_normDist_T_107 ? 5'h3 : _self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_130 = _self_rec_rawIn_normDist_T_108 ? 5'h2 : _self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_131 = _self_rec_rawIn_normDist_T_109 ? 5'h1 : _self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist_2 = _self_rec_rawIn_normDist_T_110 ? 5'h0 : _self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T_4 = {31'h0, self_rec_rawIn_fractIn_2} << self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_5 = _self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract_2 = {_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_11 = self_rec_rawIn_isZeroExpIn_2 ? _self_rec_rawIn_adjustedExp_T_10 : {1'h0, self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_12 = self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_13 = {6'h20, _self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_14 = {1'h0, _self_rec_rawIn_adjustedExp_T_11} + {2'h0, _self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp_2 = _self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T_4 = self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero_2 = self_rec_rawIn_isZeroExpIn_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_2_isZero = self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T_2 = self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial_2 = &_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_18 = self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T_4 = ~self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_5 = self_rec_rawIn_isSpecial_2 & _self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_2_isNaN = _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T_2 = self_rec_rawIn_isSpecial_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_2_isInf = _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_5 = {1'h0, _self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_2_sExp = _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T_8 = ~self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_9 = {1'h0, _self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_10 = self_rec_rawIn_isZeroExpIn_2 ? self_rec_rawIn_subnormFract_2 : self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_11 = {_self_rec_rawIn_out_sig_T_9, _self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_2_sig = _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T_16 = self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_17 = self_rec_rawIn_2_isZero ? 3'h0 : _self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_19 = {_self_rec_T_17[2:1], _self_rec_T_17[0] \| _self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_20 = {self_rec_rawIn_2_sign, _self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_21 = self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_22 = {_self_rec_T_20, _self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_23 = self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec_2 = {_self_rec_T_22, _self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] out_2_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp_2 = _muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T_2 = out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero_2 = _out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_2_isZero = out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T_2 = out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial_2 = &_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T_4 = out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T_6 = out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_5 = out_bits_rawIn_isSpecial_2 & _out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_2_isNaN = _out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_7 = ~_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_8 = out_bits_rawIn_isSpecial_2 & _out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_2_isInf = _out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T_2 = _muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_2_sign = _out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T_2 = {1'h0, out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_2_sExp = _out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T_8 = ~out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_9 = {1'h0, _out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_10 = _muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_11 = {_out_bits_rawIn_out_sig_T_9, _out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_2_sig = _out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal_2 = $signed(out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T_4 = out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist_2 = _out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T_4 = out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_5 = _out_bits_denormFract_T_4 >> out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract_2 = _out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T_12 = out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_13 = {1'h0, _out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_14 = _out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_15 = out_bits_isSubnormal_2 ? 8'h0 : _out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_16 = out_bits_rawIn_2_isNaN \| out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_17 = {8{_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut_2 = _out_bits_expOut_T_15 \| _out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T_4 = out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_5 = out_bits_rawIn_2_isInf ? 23'h0 : _out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut_2 = out_bits_isSubnormal_2 ? out_bits_denormFract_2 : _out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi_2 = {out_bits_rawIn_2_sign, out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T_2 = {out_bits_hi_2, out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_2_bits = _out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire t_rec_rawIn_3_sign = t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire t_rec_rawIn_isZeroExpIn_3 = t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn_3 = t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T_132 = t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_133 = t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_134 = t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_135 = t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_136 = t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_137 = t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_138 = t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_139 = t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_140 = t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_141 = t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_142 = t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_143 = t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_144 = t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_145 = t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_146 = t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_147 = t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_148 = t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_149 = t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_150 = t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_151 = t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_152 = t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_153 = t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_154 = t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_155 = _t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_156 = _t_rec_rawIn_normDist_T_134 ? 5'h14 : _t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_157 = _t_rec_rawIn_normDist_T_135 ? 5'h13 : _t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_158 = _t_rec_rawIn_normDist_T_136 ? 5'h12 : _t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_159 = _t_rec_rawIn_normDist_T_137 ? 5'h11 : _t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_160 = _t_rec_rawIn_normDist_T_138 ? 5'h10 : _t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_161 = _t_rec_rawIn_normDist_T_139 ? 5'hF : _t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_162 = _t_rec_rawIn_normDist_T_140 ? 5'hE : _t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_163 = _t_rec_rawIn_normDist_T_141 ? 5'hD : _t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_164 = _t_rec_rawIn_normDist_T_142 ? 5'hC : _t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_165 = _t_rec_rawIn_normDist_T_143 ? 5'hB : _t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_166 = _t_rec_rawIn_normDist_T_144 ? 5'hA : _t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_167 = _t_rec_rawIn_normDist_T_145 ? 5'h9 : _t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_168 = _t_rec_rawIn_normDist_T_146 ? 5'h8 : _t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_169 = _t_rec_rawIn_normDist_T_147 ? 5'h7 : _t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_170 = _t_rec_rawIn_normDist_T_148 ? 5'h6 : _t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_171 = _t_rec_rawIn_normDist_T_149 ? 5'h5 : _t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_172 = _t_rec_rawIn_normDist_T_150 ? 5'h4 : _t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_173 = _t_rec_rawIn_normDist_T_151 ? 5'h3 : _t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_174 = _t_rec_rawIn_normDist_T_152 ? 5'h2 : _t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_175 = _t_rec_rawIn_normDist_T_153 ? 5'h1 : _t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist_3 = _t_rec_rawIn_normDist_T_154 ? 5'h0 : _t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T_6 = {31'h0, t_rec_rawIn_fractIn_3} << t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_7 = _t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract_3 = {_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_16 = t_rec_rawIn_isZeroExpIn_3 ? _t_rec_rawIn_adjustedExp_T_15 : {1'h0, t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_17 = t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_18 = {6'h20, _t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_19 = {1'h0, _t_rec_rawIn_adjustedExp_T_16} + {2'h0, _t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp_3 = _t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T_6 = t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero_3 = t_rec_rawIn_isZeroExpIn_3 & t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_3_isZero = t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T_3 = t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial_3 = &_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_26 = t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T_6 = ~t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_7 = t_rec_rawIn_isSpecial_3 & _t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_3_isNaN = _t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T_3 = t_rec_rawIn_isSpecial_3 & t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_3_isInf = _t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_7 = {1'h0, _t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_3_sExp = _t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T_12 = ~t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_13 = {1'h0, _t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_14 = t_rec_rawIn_isZeroExpIn_3 ? t_rec_rawIn_subnormFract_3 : t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_15 = {_t_rec_rawIn_out_sig_T_13, _t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_3_sig = _t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T_24 = t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_25 = t_rec_rawIn_3_isZero ? 3'h0 : _t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_27 = {_t_rec_T_25[2:1], _t_rec_T_25[0] \| _t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_28 = {t_rec_rawIn_3_sign, _t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_29 = t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_30 = {_t_rec_T_28, _t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_31 = t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec_3 = {_t_rec_T_30, _t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign_3 = in_bits_in_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_3_sign = self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn_3 = in_bits_in_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn_3 = in_bits_in_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn_3 = self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn_3 = self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T_132 = self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_133 = self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_134 = self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_135 = self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_136 = self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_137 = self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_138 = self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_139 = self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_140 = self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_141 = self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_142 = self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_143 = self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_144 = self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_145 = self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_146 = self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_147 = self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_148 = self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_149 = self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_150 = self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_151 = self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_152 = self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_153 = self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_154 = self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_155 = _self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_156 = _self_rec_rawIn_normDist_T_134 ? 5'h14 : _self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_157 = _self_rec_rawIn_normDist_T_135 ? 5'h13 : _self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_158 = _self_rec_rawIn_normDist_T_136 ? 5'h12 : _self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_159 = _self_rec_rawIn_normDist_T_137 ? 5'h11 : _self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_160 = _self_rec_rawIn_normDist_T_138 ? 5'h10 : _self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_161 = _self_rec_rawIn_normDist_T_139 ? 5'hF : _self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_162 = _self_rec_rawIn_normDist_T_140 ? 5'hE : _self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_163 = _self_rec_rawIn_normDist_T_141 ? 5'hD : _self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_164 = _self_rec_rawIn_normDist_T_142 ? 5'hC : _self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_165 = _self_rec_rawIn_normDist_T_143 ? 5'hB : _self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_166 = _self_rec_rawIn_normDist_T_144 ? 5'hA : _self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_167 = _self_rec_rawIn_normDist_T_145 ? 5'h9 : _self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_168 = _self_rec_rawIn_normDist_T_146 ? 5'h8 : _self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_169 = _self_rec_rawIn_normDist_T_147 ? 5'h7 : _self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_170 = _self_rec_rawIn_normDist_T_148 ? 5'h6 : _self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_171 = _self_rec_rawIn_normDist_T_149 ? 5'h5 : _self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_172 = _self_rec_rawIn_normDist_T_150 ? 5'h4 : _self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_173 = _self_rec_rawIn_normDist_T_151 ? 5'h3 : _self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_174 = _self_rec_rawIn_normDist_T_152 ? 5'h2 : _self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_175 = _self_rec_rawIn_normDist_T_153 ? 5'h1 : _self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist_3 = _self_rec_rawIn_normDist_T_154 ? 5'h0 : _self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T_6 = {31'h0, self_rec_rawIn_fractIn_3} << self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_7 = _self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract_3 = {_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_16 = self_rec_rawIn_isZeroExpIn_3 ? _self_rec_rawIn_adjustedExp_T_15 : {1'h0, self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_17 = self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_18 = {6'h20, _self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_19 = {1'h0, _self_rec_rawIn_adjustedExp_T_16} + {2'h0, _self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp_3 = _self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T_6 = self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero_3 = self_rec_rawIn_isZeroExpIn_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_3_isZero = self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T_3 = self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial_3 = &_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_26 = self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T_6 = ~self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_7 = self_rec_rawIn_isSpecial_3 & _self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_3_isNaN = _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T_3 = self_rec_rawIn_isSpecial_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_3_isInf = _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_7 = {1'h0, _self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_3_sExp = _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T_12 = ~self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_13 = {1'h0, _self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_14 = self_rec_rawIn_isZeroExpIn_3 ? self_rec_rawIn_subnormFract_3 : self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_15 = {_self_rec_rawIn_out_sig_T_13, _self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_3_sig = _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T_24 = self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_25 = self_rec_rawIn_3_isZero ? 3'h0 : _self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_27 = {_self_rec_T_25[2:1], _self_rec_T_25[0] \| _self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_28 = {self_rec_rawIn_3_sign, _self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_29 = self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_30 = {_self_rec_T_28, _self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_31 = self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec_3 = {_self_rec_T_30, _self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] out_3_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp_3 = _muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T_3 = out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero_3 = _out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_3_isZero = out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T_3 = out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial_3 = &_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T_6 = out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T_9 = out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_7 = out_bits_rawIn_isSpecial_3 & _out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_3_isNaN = _out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_10 = ~_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_11 = out_bits_rawIn_isSpecial_3 & _out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_3_isInf = _out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T_3 = _muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_3_sign = _out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T_3 = {1'h0, out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_3_sExp = _out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T_12 = ~out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_13 = {1'h0, _out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_14 = _muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_15 = {_out_bits_rawIn_out_sig_T_13, _out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_3_sig = _out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal_3 = $signed(out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T_6 = out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist_3 = _out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T_6 = out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_7 = _out_bits_denormFract_T_6 >> out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract_3 = _out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T_18 = out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_19 = {1'h0, _out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_20 = _out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_21 = out_bits_isSubnormal_3 ? 8'h0 : _out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_22 = out_bits_rawIn_3_isNaN \| out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_23 = {8{_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut_3 = _out_bits_expOut_T_21 \| _out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T_6 = out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_7 = out_bits_rawIn_3_isInf ? 23'h0 : _out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut_3 = out_bits_isSubnormal_3 ? out_bits_denormFract_3 : _out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi_3 = {out_bits_rawIn_3_sign, out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T_3 = {out_bits_hi_3, out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_3_bits = _out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[VectorScalarMultiplier.scala:45:7] if (reset) // @[VectorScalarMultiplier.scala:45:7] in_valid <= 1'h0; // @[VectorScalarMultiplier.scala:65:15] else // @[VectorScalarMultiplier.scala:45:7] in_valid <= _T ? io_req_valid_0 : ~(in_fire & _T_1) & in_valid; // @[Decoupled.scala:51:35] if (_T) begin // @[Decoupled.scala:51:35] in_bits_in_0_bits <= io_req_bits_in_0_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_in_1_bits <= io_req_bits_in_1_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_in_2_bits <= io_req_bits_in_2_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_in_3_bits <= io_req_bits_in_3_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_scale_bits <= io_req_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_repeats <= io_req_bits_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_pixel_repeats <= io_req_bits_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_last <= io_req_bits_last_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_data <= io_req_bits_tag_data_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_addr <= io_req_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_0 <= io_req_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_1 <= io_req_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_2 <= io_req_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_3 <= io_req_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_4 <= io_req_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_5 <= io_req_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_6 <= io_req_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_7 <= io_req_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_8 <= io_req_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_9 <= io_req_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_10 <= io_req_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_11 <= io_req_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_12 <= io_req_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_13 <= io_req_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_14 <= io_req_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_15 <= io_req_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_is_acc <= io_req_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_accumulate <= io_req_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_has_acc_bitwidth <= io_req_bits_tag_has_acc_bitwidth_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_scale <= io_req_bits_tag_scale_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_repeats <= io_req_bits_tag_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_pixel_repeats <= io_req_bits_tag_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_len <= io_req_bits_tag_len_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_last <= io_req_bits_tag_last_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_bytes_read <= io_req_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_cmd_id <= io_req_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] end else if (in_fire) // @[VectorScalarMultiplier.scala:66:25] in_bits_repeats <= _in_bits_repeats_T_1; // @[VectorScalarMultiplier.scala:65:15, :76:40] always @(posedge) Pipeline_1 pipe ( // @[VectorScalarMultiplier.scala:83:22] .clock (clock), .reset (reset), .io_in_ready (_pipe_io_in_ready), .io_in_valid (in_valid), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_out_0_bits (out_bits), // @[Arithmetic.scala:350:23] .io_in_bits_out_1_bits (out_1_bits), // @[Arithmetic.scala:350:23] .io_in_bits_out_2_bits (out_2_bits), // @[Arithmetic.scala:350:23] .io_in_bits_out_3_bits (out_3_bits), // @[Arithmetic.scala:350:23] .io_in_bits_row (in_bits_repeats), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_last (_pipe_io_in_bits_last_T_1), // @[VectorScalarMultiplier.scala:92:53] .io_in_bits_tag_data (in_bits_tag_data), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_addr (in_bits_tag_addr), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_0 (in_bits_tag_mask_0), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_1 (in_bits_tag_mask_1), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_2 (in_bits_tag_mask_2), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_3 (in_bits_tag_mask_3), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_4 (in_bits_tag_mask_4), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_5 (in_bits_tag_mask_5), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_6 (in_bits_tag_mask_6), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_7 (in_bits_tag_mask_7), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_8 (in_bits_tag_mask_8), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_9 (in_bits_tag_mask_9), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_10 (in_bits_tag_mask_10), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_11 (in_bits_tag_mask_11), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_12 (in_bits_tag_mask_12), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_13 (in_bits_tag_mask_13), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_14 (in_bits_tag_mask_14), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_15 (in_bits_tag_mask_15), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_is_acc (in_bits_tag_is_acc), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_accumulate (in_bits_tag_accumulate), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_has_acc_bitwidth (in_bits_tag_has_acc_bitwidth), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_scale (in_bits_tag_scale), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_repeats (in_bits_tag_repeats), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_pixel_repeats (in_bits_tag_pixel_repeats), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_len (in_bits_tag_len), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_last (in_bits_tag_last), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_bytes_read (in_bits_tag_bytes_read), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_cmd_id (in_bits_tag_cmd_id), // @[VectorScalarMultiplier.scala:65:15] .io_out_ready (io_resp_ready_0), // @[VectorScalarMultiplier.scala:45:7] .io_out_valid (io_resp_valid_0), .io_out_bits_out_0_bits (io_resp_bits_out_0_bits_0), .io_out_bits_out_1_bits (io_resp_bits_out_1_bits_0), .io_out_bits_out_2_bits (io_resp_bits_out_2_bits_0), .io_out_bits_out_3_bits (io_resp_bits_out_3_bits_0), .io_out_bits_row (io_resp_bits_row_0), .io_out_bits_last (io_resp_bits_last_0), .io_out_bits_tag_data (io_resp_bits_tag_data), .io_out_bits_tag_addr (io_resp_bits_tag_addr_0), .io_out_bits_tag_mask_0 (io_resp_bits_tag_mask_0_0), .io_out_bits_tag_mask_1 (io_resp_bits_tag_mask_1_0), .io_out_bits_tag_mask_2 (io_resp_bits_tag_mask_2_0), .io_out_bits_tag_mask_3 (io_resp_bits_tag_mask_3_0), .io_out_bits_tag_mask_4 (io_resp_bits_tag_mask_4_0), .io_out_bits_tag_mask_5 (io_resp_bits_tag_mask_5_0), .io_out_bits_tag_mask_6 (io_resp_bits_tag_mask_6_0), .io_out_bits_tag_mask_7 (io_resp_bits_tag_mask_7_0), .io_out_bits_tag_mask_8 (io_resp_bits_tag_mask_8_0), .io_out_bits_tag_mask_9 (io_resp_bits_tag_mask_9_0), .io_out_bits_tag_mask_10 (io_resp_bits_tag_mask_10_0), .io_out_bits_tag_mask_11 (io_resp_bits_tag_mask_11_0), .io_out_bits_tag_mask_12 (io_resp_bits_tag_mask_12_0), .io_out_bits_tag_mask_13 (io_resp_bits_tag_mask_13_0), .io_out_bits_tag_mask_14 (io_resp_bits_tag_mask_14_0), .io_out_bits_tag_mask_15 (io_resp_bits_tag_mask_15_0), .io_out_bits_tag_is_acc (io_resp_bits_tag_is_acc_0), .io_out_bits_tag_accumulate (io_resp_bits_tag_accumulate_0), .io_out_bits_tag_has_acc_bitwidth (io_resp_bits_tag_has_acc_bitwidth), .io_out_bits_tag_scale (io_resp_bits_tag_scale), .io_out_bits_tag_repeats (io_resp_bits_tag_repeats), .io_out_bits_tag_pixel_repeats (io_resp_bits_tag_pixel_repeats), .io_out_bits_tag_len (io_resp_bits_tag_len), .io_out_bits_tag_last (io_resp_bits_tag_last), .io_out_bits_tag_bytes_read (io_resp_bits_tag_bytes_read_0), .io_out_bits_tag_cmd_id (io_resp_bits_tag_cmd_id_0) ); // @[VectorScalarMultiplier.scala:83:22] RecFNToRecFN_8 t_resizer ( // @[Arithmetic.scala:336:32] .io_in (t_rec), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_4 muladder ( // @[Arithmetic.scala:342:30] .io_a (self_rec), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_9 t_resizer_1 ( // @[Arithmetic.scala:336:32] .io_in (t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_1_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_5 muladder_1 ( // @[Arithmetic.scala:342:30] .io_a (self_rec_1), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_1_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_1_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_10 t_resizer_2 ( // @[Arithmetic.scala:336:32] .io_in (t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_2_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_6 muladder_2 ( // @[Arithmetic.scala:342:30] .io_a (self_rec_2), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_2_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_2_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_11 t_resizer_3 ( // @[Arithmetic.scala:336:32] .io_in (t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_3_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_7 muladder_3 ( // @[Arithmetic.scala:342:30] .io_a (self_rec_3), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_3_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_3_io_out) ); // @[Arithmetic.scala:342:30] assign io_req_ready = io_req_ready_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_valid = io_resp_valid_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_0_bits = io_resp_bits_out_0_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_1_bits = io_resp_bits_out_1_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_2_bits = io_resp_bits_out_2_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_3_bits = io_resp_bits_out_3_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_row = io_resp_bits_row_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_last = io_resp_bits_last_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_addr = io_resp_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_0 = io_resp_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_1 = io_resp_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_2 = io_resp_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_3 = io_resp_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_4 = io_resp_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_5 = io_resp_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_6 = io_resp_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_7 = io_resp_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_8 = io_resp_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_9 = io_resp_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_10 = io_resp_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_11 = io_resp_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_12 = io_resp_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_13 = io_resp_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_14 = io_resp_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_15 = io_resp_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_is_acc = io_resp_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_accumulate = io_resp_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_bytes_read = io_resp_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_cmd_id = io_resp_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_111 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h70)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h71)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h72)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h73)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<7>(0h7c)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 2) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<7>(0h7b)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 5) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0hd)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_43 = shr(io.in.a.bits.source, 5) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<4>(0hc)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_49 = shr(io.in.a.bits.source, 5) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<4>(0hb)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_55 = shr(io.in.a.bits.source, 5) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<4>(0ha)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_61 = shr(io.in.a.bits.source, 5) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<4>(0h9)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_67 = shr(io.in.a.bits.source, 5) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<4>(0h8)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_73 = shr(io.in.a.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<7>(0h7a)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_79 = shr(io.in.a.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<7>(0h79)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_85 = shr(io.in.a.bits.source, 5) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<3>(0h7)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_91 = shr(io.in.a.bits.source, 5) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<3>(0h6)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_97 = shr(io.in.a.bits.source, 5) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<3>(0h5)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_103 = shr(io.in.a.bits.source, 5) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_109 = shr(io.in.a.bits.source, 5) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<2>(0h3)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_115 = shr(io.in.a.bits.source, 5) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_121 = shr(io.in.a.bits.source, 5) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h1)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_127 = shr(io.in.a.bits.source, 5) node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h0)) node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129) node _source_ok_T_131 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131) node _source_ok_T_133 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _source_ok_T_134 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _source_ok_T_135 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _source_ok_T_136 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[27] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_48 connect _source_ok_WIRE[9], _source_ok_T_54 connect _source_ok_WIRE[10], _source_ok_T_60 connect _source_ok_WIRE[11], _source_ok_T_66 connect _source_ok_WIRE[12], _source_ok_T_72 connect _source_ok_WIRE[13], _source_ok_T_78 connect _source_ok_WIRE[14], _source_ok_T_84 connect _source_ok_WIRE[15], _source_ok_T_90 connect _source_ok_WIRE[16], _source_ok_T_96 connect _source_ok_WIRE[17], _source_ok_T_102 connect _source_ok_WIRE[18], _source_ok_T_108 connect _source_ok_WIRE[19], _source_ok_T_114 connect _source_ok_WIRE[20], _source_ok_T_120 connect _source_ok_WIRE[21], _source_ok_T_126 connect _source_ok_WIRE[22], _source_ok_T_132 connect _source_ok_WIRE[23], _source_ok_T_133 connect _source_ok_WIRE[24], _source_ok_T_134 connect _source_ok_WIRE[25], _source_ok_T_135 connect _source_ok_WIRE[26], _source_ok_T_136 node _source_ok_T_137 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE[2]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE[3]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE[4]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE[5]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE[6]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE[7]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE[8]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE[9]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE[10]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE[11]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE[12]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE[13]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE[14]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE[15]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE[16]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE[17]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE[18]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE[19]) node _source_ok_T_156 = or(_source_ok_T_155, _source_ok_WIRE[20]) node _source_ok_T_157 = or(_source_ok_T_156, _source_ok_WIRE[21]) node _source_ok_T_158 = or(_source_ok_T_157, _source_ok_WIRE[22]) node _source_ok_T_159 = or(_source_ok_T_158, _source_ok_WIRE[23]) node _source_ok_T_160 = or(_source_ok_T_159, _source_ok_WIRE[24]) node _source_ok_T_161 = or(_source_ok_T_160, _source_ok_WIRE[25]) node source_ok = or(_source_ok_T_161, _source_ok_WIRE[26]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h70)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h71)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h72)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h73)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<7>(0h7c)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_77 = shr(io.in.a.bits.source, 2) node _T_78 = eq(_T_77, UInt<7>(0h7b)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_90 = shr(io.in.a.bits.source, 5) node _T_91 = eq(_T_90, UInt<4>(0hd)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_103 = shr(io.in.a.bits.source, 5) node _T_104 = eq(_T_103, UInt<4>(0hc)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_7) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_116 = shr(io.in.a.bits.source, 5) node _T_117 = eq(_T_116, UInt<4>(0hb)) node _T_118 = leq(UInt<1>(0h0), uncommonBits_8) node _T_119 = and(_T_117, _T_118) node _T_120 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_124 = cvt(_T_123) node _T_125 = and(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = asSInt(_T_125) node _T_127 = eq(_T_126, asSInt(UInt<1>(0h0))) node _T_128 = or(_T_122, _T_127) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_129 = shr(io.in.a.bits.source, 5) node _T_130 = eq(_T_129, UInt<4>(0ha)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_9) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(_T_134, UInt<1>(0h0)) node _T_136 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = or(_T_135, _T_140) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_142 = shr(io.in.a.bits.source, 5) node _T_143 = eq(_T_142, UInt<4>(0h9)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_10) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = or(_T_148, _T_153) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_155 = shr(io.in.a.bits.source, 5) node _T_156 = eq(_T_155, UInt<4>(0h8)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_11) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_160 = and(_T_158, _T_159) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_168 = shr(io.in.a.bits.source, 2) node _T_169 = eq(_T_168, UInt<7>(0h7a)) node _T_170 = leq(UInt<1>(0h0), uncommonBits_12) node _T_171 = and(_T_169, _T_170) node _T_172 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_174, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<7>(0h79)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = or(_T_187, _T_192) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_194 = shr(io.in.a.bits.source, 5) node _T_195 = eq(_T_194, UInt<3>(0h7)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_14) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_207 = shr(io.in.a.bits.source, 5) node _T_208 = eq(_T_207, UInt<3>(0h6)) node _T_209 = leq(UInt<1>(0h0), uncommonBits_15) node _T_210 = and(_T_208, _T_209) node _T_211 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(_T_212, UInt<1>(0h0)) node _T_214 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = or(_T_213, _T_218) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_220 = shr(io.in.a.bits.source, 5) node _T_221 = eq(_T_220, UInt<3>(0h5)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_16) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = or(_T_226, _T_231) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_233 = shr(io.in.a.bits.source, 5) node _T_234 = eq(_T_233, UInt<3>(0h4)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_17) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = or(_T_239, _T_244) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_246 = shr(io.in.a.bits.source, 5) node _T_247 = eq(_T_246, UInt<2>(0h3)) node _T_248 = leq(UInt<1>(0h0), uncommonBits_18) node _T_249 = and(_T_247, _T_248) node _T_250 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_254 = cvt(_T_253) node _T_255 = and(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = asSInt(_T_255) node _T_257 = eq(_T_256, asSInt(UInt<1>(0h0))) node _T_258 = or(_T_252, _T_257) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_259 = shr(io.in.a.bits.source, 5) node _T_260 = eq(_T_259, UInt<2>(0h2)) node _T_261 = leq(UInt<1>(0h0), uncommonBits_19) node _T_262 = and(_T_260, _T_261) node _T_263 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_272 = shr(io.in.a.bits.source, 5) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_20) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_278, _T_283) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_285 = shr(io.in.a.bits.source, 5) node _T_286 = eq(_T_285, UInt<1>(0h0)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_21) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(_T_290, UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = or(_T_291, _T_296) node _T_298 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = or(_T_299, _T_304) node _T_306 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_307 = eq(_T_306, UInt<1>(0h0)) node _T_308 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_307, _T_312) node _T_314 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = or(_T_315, _T_320) node _T_322 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_323 = eq(_T_322, UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_11, _T_24) node _T_331 = and(_T_330, _T_37) node _T_332 = and(_T_331, _T_50) node _T_333 = and(_T_332, _T_63) node _T_334 = and(_T_333, _T_76) node _T_335 = and(_T_334, _T_89) node _T_336 = and(_T_335, _T_102) node _T_337 = and(_T_336, _T_115) node _T_338 = and(_T_337, _T_128) node _T_339 = and(_T_338, _T_141) node _T_340 = and(_T_339, _T_154) node _T_341 = and(_T_340, _T_167) node _T_342 = and(_T_341, _T_180) node _T_343 = and(_T_342, _T_193) node _T_344 = and(_T_343, _T_206) node _T_345 = and(_T_344, _T_219) node _T_346 = and(_T_345, _T_232) node _T_347 = and(_T_346, _T_245) node _T_348 = and(_T_347, _T_258) node _T_349 = and(_T_348, _T_271) node _T_350 = and(_T_349, _T_284) node _T_351 = and(_T_350, _T_297) node _T_352 = and(_T_351, _T_305) node _T_353 = and(_T_352, _T_313) node _T_354 = and(_T_353, _T_321) node _T_355 = and(_T_354, _T_329) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_355, UInt<1>(0h1), "") : assert_1 node _T_359 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_359 : node _T_360 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_361 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_362 = and(_T_360, _T_361) node _T_363 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<7>(0h70)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_22) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<7>(0h71)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_23) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_376 = shr(io.in.a.bits.source, 2) node _T_377 = eq(_T_376, UInt<7>(0h72)) node _T_378 = leq(UInt<1>(0h0), uncommonBits_24) node _T_379 = and(_T_377, _T_378) node _T_380 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_381 = and(_T_379, _T_380) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_382 = shr(io.in.a.bits.source, 2) node _T_383 = eq(_T_382, UInt<7>(0h73)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_25) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_387 = and(_T_385, _T_386) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_388 = shr(io.in.a.bits.source, 2) node _T_389 = eq(_T_388, UInt<7>(0h7c)) node _T_390 = leq(UInt<1>(0h0), uncommonBits_26) node _T_391 = and(_T_389, _T_390) node _T_392 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_393 = and(_T_391, _T_392) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<7>(0h7b)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_27) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_400 = shr(io.in.a.bits.source, 5) node _T_401 = eq(_T_400, UInt<4>(0hd)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_28) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<4>(0hc)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_29) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<4>(0hb)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_30) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_418 = shr(io.in.a.bits.source, 5) node _T_419 = eq(_T_418, UInt<4>(0ha)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_31) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_424 = shr(io.in.a.bits.source, 5) node _T_425 = eq(_T_424, UInt<4>(0h9)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_32) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<4>(0h8)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_33) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<7>(0h7a)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_34) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_442 = shr(io.in.a.bits.source, 2) node _T_443 = eq(_T_442, UInt<7>(0h79)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_35) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h7)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_36) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_454 = shr(io.in.a.bits.source, 5) node _T_455 = eq(_T_454, UInt<3>(0h6)) node _T_456 = leq(UInt<1>(0h0), uncommonBits_37) node _T_457 = and(_T_455, _T_456) node _T_458 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_459 = and(_T_457, _T_458) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_460 = shr(io.in.a.bits.source, 5) node _T_461 = eq(_T_460, UInt<3>(0h5)) node _T_462 = leq(UInt<1>(0h0), uncommonBits_38) node _T_463 = and(_T_461, _T_462) node _T_464 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_465 = and(_T_463, _T_464) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_466 = shr(io.in.a.bits.source, 5) node _T_467 = eq(_T_466, UInt<3>(0h4)) node _T_468 = leq(UInt<1>(0h0), uncommonBits_39) node _T_469 = and(_T_467, _T_468) node _T_470 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_471 = and(_T_469, _T_470) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_472 = shr(io.in.a.bits.source, 5) node _T_473 = eq(_T_472, UInt<2>(0h3)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_40) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_478 = shr(io.in.a.bits.source, 5) node _T_479 = eq(_T_478, UInt<2>(0h2)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_41) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_484 = shr(io.in.a.bits.source, 5) node _T_485 = eq(_T_484, UInt<1>(0h1)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_42) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_490 = shr(io.in.a.bits.source, 5) node _T_491 = eq(_T_490, UInt<1>(0h0)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_43) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_495 = and(_T_493, _T_494) node _T_496 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_497 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_498 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_499 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_500 = or(_T_363, _T_369) node _T_501 = or(_T_500, _T_375) node _T_502 = or(_T_501, _T_381) node _T_503 = or(_T_502, _T_387) node _T_504 = or(_T_503, _T_393) node _T_505 = or(_T_504, _T_399) node _T_506 = or(_T_505, _T_405) node _T_507 = or(_T_506, _T_411) node _T_508 = or(_T_507, _T_417) node _T_509 = or(_T_508, _T_423) node _T_510 = or(_T_509, _T_429) node _T_511 = or(_T_510, _T_435) node _T_512 = or(_T_511, _T_441) node _T_513 = or(_T_512, _T_447) node _T_514 = or(_T_513, _T_453) node _T_515 = or(_T_514, _T_459) node _T_516 = or(_T_515, _T_465) node _T_517 = or(_T_516, _T_471) node _T_518 = or(_T_517, _T_477) node _T_519 = or(_T_518, _T_483) node _T_520 = or(_T_519, _T_489) node _T_521 = or(_T_520, _T_495) node _T_522 = or(_T_521, _T_496) node _T_523 = or(_T_522, _T_497) node _T_524 = or(_T_523, _T_498) node _T_525 = or(_T_524, _T_499) node _T_526 = and(_T_362, _T_525) node _T_527 = or(UInt<1>(0h0), _T_526) node _T_528 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<13>(0h1000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = and(_T_528, _T_533) node _T_535 = or(UInt<1>(0h0), _T_534) node _T_536 = and(_T_527, _T_535) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_536, UInt<1>(0h1), "") : assert_2 node _T_540 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_541 = shr(io.in.a.bits.source, 2) node _T_542 = eq(_T_541, UInt<7>(0h70)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_44) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_547 = shr(io.in.a.bits.source, 2) node _T_548 = eq(_T_547, UInt<7>(0h71)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_45) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<7>(0h72)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_46) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<7>(0h73)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_47) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<7>(0h7c)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_48) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<7>(0h7b)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_49) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_577 = shr(io.in.a.bits.source, 5) node _T_578 = eq(_T_577, UInt<4>(0hd)) node _T_579 = leq(UInt<1>(0h0), uncommonBits_50) node _T_580 = and(_T_578, _T_579) node _T_581 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_582 = and(_T_580, _T_581) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_583 = shr(io.in.a.bits.source, 5) node _T_584 = eq(_T_583, UInt<4>(0hc)) node _T_585 = leq(UInt<1>(0h0), uncommonBits_51) node _T_586 = and(_T_584, _T_585) node _T_587 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_588 = and(_T_586, _T_587) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_589 = shr(io.in.a.bits.source, 5) node _T_590 = eq(_T_589, UInt<4>(0hb)) node _T_591 = leq(UInt<1>(0h0), uncommonBits_52) node _T_592 = and(_T_590, _T_591) node _T_593 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_594 = and(_T_592, _T_593) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_595 = shr(io.in.a.bits.source, 5) node _T_596 = eq(_T_595, UInt<4>(0ha)) node _T_597 = leq(UInt<1>(0h0), uncommonBits_53) node _T_598 = and(_T_596, _T_597) node _T_599 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_600 = and(_T_598, _T_599) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_601 = shr(io.in.a.bits.source, 5) node _T_602 = eq(_T_601, UInt<4>(0h9)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_54) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_607 = shr(io.in.a.bits.source, 5) node _T_608 = eq(_T_607, UInt<4>(0h8)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_55) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_613 = shr(io.in.a.bits.source, 2) node _T_614 = eq(_T_613, UInt<7>(0h7a)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_56) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_619 = shr(io.in.a.bits.source, 2) node _T_620 = eq(_T_619, UInt<7>(0h79)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_57) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_624 = and(_T_622, _T_623) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_625 = shr(io.in.a.bits.source, 5) node _T_626 = eq(_T_625, UInt<3>(0h7)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_58) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_631 = shr(io.in.a.bits.source, 5) node _T_632 = eq(_T_631, UInt<3>(0h6)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_59) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_637 = shr(io.in.a.bits.source, 5) node _T_638 = eq(_T_637, UInt<3>(0h5)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_60) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_643 = shr(io.in.a.bits.source, 5) node _T_644 = eq(_T_643, UInt<3>(0h4)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_61) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_649 = shr(io.in.a.bits.source, 5) node _T_650 = eq(_T_649, UInt<2>(0h3)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_62) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_654 = and(_T_652, _T_653) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_655 = shr(io.in.a.bits.source, 5) node _T_656 = eq(_T_655, UInt<2>(0h2)) node _T_657 = leq(UInt<1>(0h0), uncommonBits_63) node _T_658 = and(_T_656, _T_657) node _T_659 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_660 = and(_T_658, _T_659) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_661 = shr(io.in.a.bits.source, 5) node _T_662 = eq(_T_661, UInt<1>(0h1)) node _T_663 = leq(UInt<1>(0h0), uncommonBits_64) node _T_664 = and(_T_662, _T_663) node _T_665 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_666 = and(_T_664, _T_665) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_667 = shr(io.in.a.bits.source, 5) node _T_668 = eq(_T_667, UInt<1>(0h0)) node _T_669 = leq(UInt<1>(0h0), uncommonBits_65) node _T_670 = and(_T_668, _T_669) node _T_671 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_672 = and(_T_670, _T_671) node _T_673 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_674 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_675 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_676 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[27] connect _WIRE[0], _T_540 connect _WIRE[1], _T_546 connect _WIRE[2], _T_552 connect _WIRE[3], _T_558 connect _WIRE[4], _T_564 connect _WIRE[5], _T_570 connect _WIRE[6], _T_576 connect _WIRE[7], _T_582 connect _WIRE[8], _T_588 connect _WIRE[9], _T_594 connect _WIRE[10], _T_600 connect _WIRE[11], _T_606 connect _WIRE[12], _T_612 connect _WIRE[13], _T_618 connect _WIRE[14], _T_624 connect _WIRE[15], _T_630 connect _WIRE[16], _T_636 connect _WIRE[17], _T_642 connect _WIRE[18], _T_648 connect _WIRE[19], _T_654 connect _WIRE[20], _T_660 connect _WIRE[21], _T_666 connect _WIRE[22], _T_672 connect _WIRE[23], _T_673 connect _WIRE[24], _T_674 connect _WIRE[25], _T_675 connect _WIRE[26], _T_676 node _T_677 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_678 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_682 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_685 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_686 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_687 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_688 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_689 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_690 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_691 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_692 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_693 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_695 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_697 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_698 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_699 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_700 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_701 = mux(_WIRE[23], _T_677, UInt<1>(0h0)) node _T_702 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_703 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = mux(_WIRE[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = or(_T_678, _T_679) node _T_706 = or(_T_705, _T_680) node _T_707 = or(_T_706, _T_681) node _T_708 = or(_T_707, _T_682) node _T_709 = or(_T_708, _T_683) node _T_710 = or(_T_709, _T_684) node _T_711 = or(_T_710, _T_685) node _T_712 = or(_T_711, _T_686) node _T_713 = or(_T_712, _T_687) node _T_714 = or(_T_713, _T_688) node _T_715 = or(_T_714, _T_689) node _T_716 = or(_T_715, _T_690) node _T_717 = or(_T_716, _T_691) node _T_718 = or(_T_717, _T_692) node _T_719 = or(_T_718, _T_693) node _T_720 = or(_T_719, _T_694) node _T_721 = or(_T_720, _T_695) node _T_722 = or(_T_721, _T_696) node _T_723 = or(_T_722, _T_697) node _T_724 = or(_T_723, _T_698) node _T_725 = or(_T_724, _T_699) node _T_726 = or(_T_725, _T_700) node _T_727 = or(_T_726, _T_701) node _T_728 = or(_T_727, _T_702) node _T_729 = or(_T_728, _T_703) node _T_730 = or(_T_729, _T_704) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_730 node _T_731 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_732 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_733 = and(_T_731, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<13>(0h1000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = and(_T_734, _T_739) node _T_741 = or(UInt<1>(0h0), _T_740) node _T_742 = and(_WIRE_1, _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_742, UInt<1>(0h1), "") : assert_3 node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(source_ok, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_749 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_749, UInt<1>(0h1), "") : assert_5 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(is_aligned, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_756 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(_T_756, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_756, UInt<1>(0h1), "") : assert_7 node _T_760 = not(io.in.a.bits.mask) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_761, UInt<1>(0h1), "") : assert_8 node _T_765 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_765, UInt<1>(0h1), "") : assert_9 node _T_769 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_769 : node _T_770 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_771 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_772 = and(_T_770, _T_771) node _T_773 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_774 = shr(io.in.a.bits.source, 2) node _T_775 = eq(_T_774, UInt<7>(0h70)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_66) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_780 = shr(io.in.a.bits.source, 2) node _T_781 = eq(_T_780, UInt<7>(0h71)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_67) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_786 = shr(io.in.a.bits.source, 2) node _T_787 = eq(_T_786, UInt<7>(0h72)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_68) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_792 = shr(io.in.a.bits.source, 2) node _T_793 = eq(_T_792, UInt<7>(0h73)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_69) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_797 = and(_T_795, _T_796) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_798 = shr(io.in.a.bits.source, 2) node _T_799 = eq(_T_798, UInt<7>(0h7c)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_70) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_803 = and(_T_801, _T_802) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_804 = shr(io.in.a.bits.source, 2) node _T_805 = eq(_T_804, UInt<7>(0h7b)) node _T_806 = leq(UInt<1>(0h0), uncommonBits_71) node _T_807 = and(_T_805, _T_806) node _T_808 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_809 = and(_T_807, _T_808) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 4, 0) node _T_810 = shr(io.in.a.bits.source, 5) node _T_811 = eq(_T_810, UInt<4>(0hd)) node _T_812 = leq(UInt<1>(0h0), uncommonBits_72) node _T_813 = and(_T_811, _T_812) node _T_814 = leq(uncommonBits_72, UInt<5>(0h1f)) node _T_815 = and(_T_813, _T_814) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 4, 0) node _T_816 = shr(io.in.a.bits.source, 5) node _T_817 = eq(_T_816, UInt<4>(0hc)) node _T_818 = leq(UInt<1>(0h0), uncommonBits_73) node _T_819 = and(_T_817, _T_818) node _T_820 = leq(uncommonBits_73, UInt<5>(0h1f)) node _T_821 = and(_T_819, _T_820) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 4, 0) node _T_822 = shr(io.in.a.bits.source, 5) node _T_823 = eq(_T_822, UInt<4>(0hb)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_74) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_74, UInt<5>(0h1f)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 4, 0) node _T_828 = shr(io.in.a.bits.source, 5) node _T_829 = eq(_T_828, UInt<4>(0ha)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_75) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_75, UInt<5>(0h1f)) node _T_833 = and(_T_831, _T_832) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_834 = shr(io.in.a.bits.source, 5) node _T_835 = eq(_T_834, UInt<4>(0h9)) node _T_836 = leq(UInt<1>(0h0), uncommonBits_76) node _T_837 = and(_T_835, _T_836) node _T_838 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_839 = and(_T_837, _T_838) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_840 = shr(io.in.a.bits.source, 5) node _T_841 = eq(_T_840, UInt<4>(0h8)) node _T_842 = leq(UInt<1>(0h0), uncommonBits_77) node _T_843 = and(_T_841, _T_842) node _T_844 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_845 = and(_T_843, _T_844) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_846 = shr(io.in.a.bits.source, 2) node _T_847 = eq(_T_846, UInt<7>(0h7a)) node _T_848 = leq(UInt<1>(0h0), uncommonBits_78) node _T_849 = and(_T_847, _T_848) node _T_850 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_851 = and(_T_849, _T_850) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0) node _T_852 = shr(io.in.a.bits.source, 2) node _T_853 = eq(_T_852, UInt<7>(0h79)) node _T_854 = leq(UInt<1>(0h0), uncommonBits_79) node _T_855 = and(_T_853, _T_854) node _T_856 = leq(uncommonBits_79, UInt<2>(0h3)) node _T_857 = and(_T_855, _T_856) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_858 = shr(io.in.a.bits.source, 5) node _T_859 = eq(_T_858, UInt<3>(0h7)) node _T_860 = leq(UInt<1>(0h0), uncommonBits_80) node _T_861 = and(_T_859, _T_860) node _T_862 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_863 = and(_T_861, _T_862) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_864 = shr(io.in.a.bits.source, 5) node _T_865 = eq(_T_864, UInt<3>(0h6)) node _T_866 = leq(UInt<1>(0h0), uncommonBits_81) node _T_867 = and(_T_865, _T_866) node _T_868 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_869 = and(_T_867, _T_868) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_870 = shr(io.in.a.bits.source, 5) node _T_871 = eq(_T_870, UInt<3>(0h5)) node _T_872 = leq(UInt<1>(0h0), uncommonBits_82) node _T_873 = and(_T_871, _T_872) node _T_874 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_875 = and(_T_873, _T_874) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_876 = shr(io.in.a.bits.source, 5) node _T_877 = eq(_T_876, UInt<3>(0h4)) node _T_878 = leq(UInt<1>(0h0), uncommonBits_83) node _T_879 = and(_T_877, _T_878) node _T_880 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_881 = and(_T_879, _T_880) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 4, 0) node _T_882 = shr(io.in.a.bits.source, 5) node _T_883 = eq(_T_882, UInt<2>(0h3)) node _T_884 = leq(UInt<1>(0h0), uncommonBits_84) node _T_885 = and(_T_883, _T_884) node _T_886 = leq(uncommonBits_84, UInt<5>(0h1f)) node _T_887 = and(_T_885, _T_886) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 4, 0) node _T_888 = shr(io.in.a.bits.source, 5) node _T_889 = eq(_T_888, UInt<2>(0h2)) node _T_890 = leq(UInt<1>(0h0), uncommonBits_85) node _T_891 = and(_T_889, _T_890) node _T_892 = leq(uncommonBits_85, UInt<5>(0h1f)) node _T_893 = and(_T_891, _T_892) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 4, 0) node _T_894 = shr(io.in.a.bits.source, 5) node _T_895 = eq(_T_894, UInt<1>(0h1)) node _T_896 = leq(UInt<1>(0h0), uncommonBits_86) node _T_897 = and(_T_895, _T_896) node _T_898 = leq(uncommonBits_86, UInt<5>(0h1f)) node _T_899 = and(_T_897, _T_898) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 4, 0) node _T_900 = shr(io.in.a.bits.source, 5) node _T_901 = eq(_T_900, UInt<1>(0h0)) node _T_902 = leq(UInt<1>(0h0), uncommonBits_87) node _T_903 = and(_T_901, _T_902) node _T_904 = leq(uncommonBits_87, UInt<5>(0h1f)) node _T_905 = and(_T_903, _T_904) node _T_906 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_907 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_908 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_909 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_910 = or(_T_773, _T_779) node _T_911 = or(_T_910, _T_785) node _T_912 = or(_T_911, _T_791) node _T_913 = or(_T_912, _T_797) node _T_914 = or(_T_913, _T_803) node _T_915 = or(_T_914, _T_809) node _T_916 = or(_T_915, _T_815) node _T_917 = or(_T_916, _T_821) node _T_918 = or(_T_917, _T_827) node _T_919 = or(_T_918, _T_833) node _T_920 = or(_T_919, _T_839) node _T_921 = or(_T_920, _T_845) node _T_922 = or(_T_921, _T_851) node _T_923 = or(_T_922, _T_857) node _T_924 = or(_T_923, _T_863) node _T_925 = or(_T_924, _T_869) node _T_926 = or(_T_925, _T_875) node _T_927 = or(_T_926, _T_881) node _T_928 = or(_T_927, _T_887) node _T_929 = or(_T_928, _T_893) node _T_930 = or(_T_929, _T_899) node _T_931 = or(_T_930, _T_905) node _T_932 = or(_T_931, _T_906) node _T_933 = or(_T_932, _T_907) node _T_934 = or(_T_933, _T_908) node _T_935 = or(_T_934, _T_909) node _T_936 = and(_T_772, _T_935) node _T_937 = or(UInt<1>(0h0), _T_936) node _T_938 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_939 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = and(_T_938, _T_943) node _T_945 = or(UInt<1>(0h0), _T_944) node _T_946 = and(_T_937, _T_945) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_946, UInt<1>(0h1), "") : assert_10 node _T_950 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<7>(0h70)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_88) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 1, 0) node _T_957 = shr(io.in.a.bits.source, 2) node _T_958 = eq(_T_957, UInt<7>(0h71)) node _T_959 = leq(UInt<1>(0h0), uncommonBits_89) node _T_960 = and(_T_958, _T_959) node _T_961 = leq(uncommonBits_89, UInt<2>(0h3)) node _T_962 = and(_T_960, _T_961) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 1, 0) node _T_963 = shr(io.in.a.bits.source, 2) node _T_964 = eq(_T_963, UInt<7>(0h72)) node _T_965 = leq(UInt<1>(0h0), uncommonBits_90) node _T_966 = and(_T_964, _T_965) node _T_967 = leq(uncommonBits_90, UInt<2>(0h3)) node _T_968 = and(_T_966, _T_967) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0) node _T_969 = shr(io.in.a.bits.source, 2) node _T_970 = eq(_T_969, UInt<7>(0h73)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_91) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_91, UInt<2>(0h3)) node _T_974 = and(_T_972, _T_973) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0) node _T_975 = shr(io.in.a.bits.source, 2) node _T_976 = eq(_T_975, UInt<7>(0h7c)) node _T_977 = leq(UInt<1>(0h0), uncommonBits_92) node _T_978 = and(_T_976, _T_977) node _T_979 = leq(uncommonBits_92, UInt<2>(0h3)) node _T_980 = and(_T_978, _T_979) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0) node _T_981 = shr(io.in.a.bits.source, 2) node _T_982 = eq(_T_981, UInt<7>(0h7b)) node _T_983 = leq(UInt<1>(0h0), uncommonBits_93) node _T_984 = and(_T_982, _T_983) node _T_985 = leq(uncommonBits_93, UInt<2>(0h3)) node _T_986 = and(_T_984, _T_985) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_987 = shr(io.in.a.bits.source, 5) node _T_988 = eq(_T_987, UInt<4>(0hd)) node _T_989 = leq(UInt<1>(0h0), uncommonBits_94) node _T_990 = and(_T_988, _T_989) node _T_991 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_992 = and(_T_990, _T_991) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_993 = shr(io.in.a.bits.source, 5) node _T_994 = eq(_T_993, UInt<4>(0hc)) node _T_995 = leq(UInt<1>(0h0), uncommonBits_95) node _T_996 = and(_T_994, _T_995) node _T_997 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_998 = and(_T_996, _T_997) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 4, 0) node _T_999 = shr(io.in.a.bits.source, 5) node _T_1000 = eq(_T_999, UInt<4>(0hb)) node _T_1001 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1002 = and(_T_1000, _T_1001) node _T_1003 = leq(uncommonBits_96, UInt<5>(0h1f)) node _T_1004 = and(_T_1002, _T_1003) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 4, 0) node _T_1005 = shr(io.in.a.bits.source, 5) node _T_1006 = eq(_T_1005, UInt<4>(0ha)) node _T_1007 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = leq(uncommonBits_97, UInt<5>(0h1f)) node _T_1010 = and(_T_1008, _T_1009) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 4, 0) node _T_1011 = shr(io.in.a.bits.source, 5) node _T_1012 = eq(_T_1011, UInt<4>(0h9)) node _T_1013 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = leq(uncommonBits_98, UInt<5>(0h1f)) node _T_1016 = and(_T_1014, _T_1015) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 4, 0) node _T_1017 = shr(io.in.a.bits.source, 5) node _T_1018 = eq(_T_1017, UInt<4>(0h8)) node _T_1019 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1020 = and(_T_1018, _T_1019) node _T_1021 = leq(uncommonBits_99, UInt<5>(0h1f)) node _T_1022 = and(_T_1020, _T_1021) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 1, 0) node _T_1023 = shr(io.in.a.bits.source, 2) node _T_1024 = eq(_T_1023, UInt<7>(0h7a)) node _T_1025 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = leq(uncommonBits_100, UInt<2>(0h3)) node _T_1028 = and(_T_1026, _T_1027) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 1, 0) node _T_1029 = shr(io.in.a.bits.source, 2) node _T_1030 = eq(_T_1029, UInt<7>(0h79)) node _T_1031 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = leq(uncommonBits_101, UInt<2>(0h3)) node _T_1034 = and(_T_1032, _T_1033) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1035 = shr(io.in.a.bits.source, 5) node _T_1036 = eq(_T_1035, UInt<3>(0h7)) node _T_1037 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1040 = and(_T_1038, _T_1039) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1041 = shr(io.in.a.bits.source, 5) node _T_1042 = eq(_T_1041, UInt<3>(0h6)) node _T_1043 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1046 = and(_T_1044, _T_1045) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1047 = shr(io.in.a.bits.source, 5) node _T_1048 = eq(_T_1047, UInt<3>(0h5)) node _T_1049 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1050 = and(_T_1048, _T_1049) node _T_1051 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1052 = and(_T_1050, _T_1051) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1053 = shr(io.in.a.bits.source, 5) node _T_1054 = eq(_T_1053, UInt<3>(0h4)) node _T_1055 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1056 = and(_T_1054, _T_1055) node _T_1057 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1058 = and(_T_1056, _T_1057) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1059 = shr(io.in.a.bits.source, 5) node _T_1060 = eq(_T_1059, UInt<2>(0h3)) node _T_1061 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1064 = and(_T_1062, _T_1063) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1065 = shr(io.in.a.bits.source, 5) node _T_1066 = eq(_T_1065, UInt<2>(0h2)) node _T_1067 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1070 = and(_T_1068, _T_1069) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 4, 0) node _T_1071 = shr(io.in.a.bits.source, 5) node _T_1072 = eq(_T_1071, UInt<1>(0h1)) node _T_1073 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1074 = and(_T_1072, _T_1073) node _T_1075 = leq(uncommonBits_108, UInt<5>(0h1f)) node _T_1076 = and(_T_1074, _T_1075) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 4, 0) node _T_1077 = shr(io.in.a.bits.source, 5) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) node _T_1079 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1080 = and(_T_1078, _T_1079) node _T_1081 = leq(uncommonBits_109, UInt<5>(0h1f)) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1084 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1085 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1086 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[27] connect _WIRE_2[0], _T_950 connect _WIRE_2[1], _T_956 connect _WIRE_2[2], _T_962 connect _WIRE_2[3], _T_968 connect _WIRE_2[4], _T_974 connect _WIRE_2[5], _T_980 connect _WIRE_2[6], _T_986 connect _WIRE_2[7], _T_992 connect _WIRE_2[8], _T_998 connect _WIRE_2[9], _T_1004 connect _WIRE_2[10], _T_1010 connect _WIRE_2[11], _T_1016 connect _WIRE_2[12], _T_1022 connect _WIRE_2[13], _T_1028 connect _WIRE_2[14], _T_1034 connect _WIRE_2[15], _T_1040 connect _WIRE_2[16], _T_1046 connect _WIRE_2[17], _T_1052 connect _WIRE_2[18], _T_1058 connect _WIRE_2[19], _T_1064 connect _WIRE_2[20], _T_1070 connect _WIRE_2[21], _T_1076 connect _WIRE_2[22], _T_1082 connect _WIRE_2[23], _T_1083 connect _WIRE_2[24], _T_1084 connect _WIRE_2[25], _T_1085 connect _WIRE_2[26], _T_1086 node _T_1087 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1088 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1089 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1090 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1091 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1092 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1094 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1096 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1097 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_1098 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1099 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1100 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1101 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_1102 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_1103 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_1104 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1105 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_1106 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1107 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_1108 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_1109 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_1110 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_1111 = mux(_WIRE_2[23], _T_1087, UInt<1>(0h0)) node _T_1112 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_1113 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_1114 = mux(_WIRE_2[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_1115 = or(_T_1088, _T_1089) node _T_1116 = or(_T_1115, _T_1090) node _T_1117 = or(_T_1116, _T_1091) node _T_1118 = or(_T_1117, _T_1092) node _T_1119 = or(_T_1118, _T_1093) node _T_1120 = or(_T_1119, _T_1094) node _T_1121 = or(_T_1120, _T_1095) node _T_1122 = or(_T_1121, _T_1096) node _T_1123 = or(_T_1122, _T_1097) node _T_1124 = or(_T_1123, _T_1098) node _T_1125 = or(_T_1124, _T_1099) node _T_1126 = or(_T_1125, _T_1100) node _T_1127 = or(_T_1126, _T_1101) node _T_1128 = or(_T_1127, _T_1102) node _T_1129 = or(_T_1128, _T_1103) node _T_1130 = or(_T_1129, _T_1104) node _T_1131 = or(_T_1130, _T_1105) node _T_1132 = or(_T_1131, _T_1106) node _T_1133 = or(_T_1132, _T_1107) node _T_1134 = or(_T_1133, _T_1108) node _T_1135 = or(_T_1134, _T_1109) node _T_1136 = or(_T_1135, _T_1110) node _T_1137 = or(_T_1136, _T_1111) node _T_1138 = or(_T_1137, _T_1112) node _T_1139 = or(_T_1138, _T_1113) node _T_1140 = or(_T_1139, _T_1114) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1140 node _T_1141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1142 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = or(UInt<1>(0h0), _T_1143) node _T_1145 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1146 = cvt(_T_1145) node _T_1147 = and(_T_1146, asSInt(UInt<13>(0h1000))) node _T_1148 = asSInt(_T_1147) node _T_1149 = eq(_T_1148, asSInt(UInt<1>(0h0))) node _T_1150 = and(_T_1144, _T_1149) node _T_1151 = or(UInt<1>(0h0), _T_1150) node _T_1152 = and(_WIRE_3, _T_1151) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_11 node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(source_ok, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1159 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_13 node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(is_aligned, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1166 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_15 node _T_1170 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_16 node _T_1174 = not(io.in.a.bits.mask) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_17 node _T_1179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_18 node _T_1183 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1183 : node _T_1184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1188 = shr(io.in.a.bits.source, 2) node _T_1189 = eq(_T_1188, UInt<7>(0h70)) node _T_1190 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1193 = and(_T_1191, _T_1192) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<7>(0h71)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<7>(0h72)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_112, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 1, 0) node _T_1206 = shr(io.in.a.bits.source, 2) node _T_1207 = eq(_T_1206, UInt<7>(0h73)) node _T_1208 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = leq(uncommonBits_113, UInt<2>(0h3)) node _T_1211 = and(_T_1209, _T_1210) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 1, 0) node _T_1212 = shr(io.in.a.bits.source, 2) node _T_1213 = eq(_T_1212, UInt<7>(0h7c)) node _T_1214 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = leq(uncommonBits_114, UInt<2>(0h3)) node _T_1217 = and(_T_1215, _T_1216) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 1, 0) node _T_1218 = shr(io.in.a.bits.source, 2) node _T_1219 = eq(_T_1218, UInt<7>(0h7b)) node _T_1220 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1221 = and(_T_1219, _T_1220) node _T_1222 = leq(uncommonBits_115, UInt<2>(0h3)) node _T_1223 = and(_T_1221, _T_1222) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1224 = shr(io.in.a.bits.source, 5) node _T_1225 = eq(_T_1224, UInt<4>(0hd)) node _T_1226 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1229 = and(_T_1227, _T_1228) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1230 = shr(io.in.a.bits.source, 5) node _T_1231 = eq(_T_1230, UInt<4>(0hc)) node _T_1232 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1235 = and(_T_1233, _T_1234) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1236 = shr(io.in.a.bits.source, 5) node _T_1237 = eq(_T_1236, UInt<4>(0hb)) node _T_1238 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1241 = and(_T_1239, _T_1240) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1242 = shr(io.in.a.bits.source, 5) node _T_1243 = eq(_T_1242, UInt<4>(0ha)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1247 = and(_T_1245, _T_1246) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 4, 0) node _T_1248 = shr(io.in.a.bits.source, 5) node _T_1249 = eq(_T_1248, UInt<4>(0h9)) node _T_1250 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = leq(uncommonBits_120, UInt<5>(0h1f)) node _T_1253 = and(_T_1251, _T_1252) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 4, 0) node _T_1254 = shr(io.in.a.bits.source, 5) node _T_1255 = eq(_T_1254, UInt<4>(0h8)) node _T_1256 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = leq(uncommonBits_121, UInt<5>(0h1f)) node _T_1259 = and(_T_1257, _T_1258) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1260 = shr(io.in.a.bits.source, 2) node _T_1261 = eq(_T_1260, UInt<7>(0h7a)) node _T_1262 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1265 = and(_T_1263, _T_1264) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1266 = shr(io.in.a.bits.source, 2) node _T_1267 = eq(_T_1266, UInt<7>(0h79)) node _T_1268 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1271 = and(_T_1269, _T_1270) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1272 = shr(io.in.a.bits.source, 5) node _T_1273 = eq(_T_1272, UInt<3>(0h7)) node _T_1274 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1277 = and(_T_1275, _T_1276) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1278 = shr(io.in.a.bits.source, 5) node _T_1279 = eq(_T_1278, UInt<3>(0h6)) node _T_1280 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1281 = and(_T_1279, _T_1280) node _T_1282 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1283 = and(_T_1281, _T_1282) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1284 = shr(io.in.a.bits.source, 5) node _T_1285 = eq(_T_1284, UInt<3>(0h5)) node _T_1286 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1289 = and(_T_1287, _T_1288) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1290 = shr(io.in.a.bits.source, 5) node _T_1291 = eq(_T_1290, UInt<3>(0h4)) node _T_1292 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1293 = and(_T_1291, _T_1292) node _T_1294 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1295 = and(_T_1293, _T_1294) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1296 = shr(io.in.a.bits.source, 5) node _T_1297 = eq(_T_1296, UInt<2>(0h3)) node _T_1298 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1301 = and(_T_1299, _T_1300) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1302 = shr(io.in.a.bits.source, 5) node _T_1303 = eq(_T_1302, UInt<2>(0h2)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1307 = and(_T_1305, _T_1306) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1308 = shr(io.in.a.bits.source, 5) node _T_1309 = eq(_T_1308, UInt<1>(0h1)) node _T_1310 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1313 = and(_T_1311, _T_1312) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1314 = shr(io.in.a.bits.source, 5) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) node _T_1316 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1317 = and(_T_1315, _T_1316) node _T_1318 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1321 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1322 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1323 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1324 = or(_T_1187, _T_1193) node _T_1325 = or(_T_1324, _T_1199) node _T_1326 = or(_T_1325, _T_1205) node _T_1327 = or(_T_1326, _T_1211) node _T_1328 = or(_T_1327, _T_1217) node _T_1329 = or(_T_1328, _T_1223) node _T_1330 = or(_T_1329, _T_1229) node _T_1331 = or(_T_1330, _T_1235) node _T_1332 = or(_T_1331, _T_1241) node _T_1333 = or(_T_1332, _T_1247) node _T_1334 = or(_T_1333, _T_1253) node _T_1335 = or(_T_1334, _T_1259) node _T_1336 = or(_T_1335, _T_1265) node _T_1337 = or(_T_1336, _T_1271) node _T_1338 = or(_T_1337, _T_1277) node _T_1339 = or(_T_1338, _T_1283) node _T_1340 = or(_T_1339, _T_1289) node _T_1341 = or(_T_1340, _T_1295) node _T_1342 = or(_T_1341, _T_1301) node _T_1343 = or(_T_1342, _T_1307) node _T_1344 = or(_T_1343, _T_1313) node _T_1345 = or(_T_1344, _T_1319) node _T_1346 = or(_T_1345, _T_1320) node _T_1347 = or(_T_1346, _T_1321) node _T_1348 = or(_T_1347, _T_1322) node _T_1349 = or(_T_1348, _T_1323) node _T_1350 = and(_T_1186, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1350) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_19 node _T_1355 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1356 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1357 = and(_T_1355, _T_1356) node _T_1358 = or(UInt<1>(0h0), _T_1357) node _T_1359 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1360 = cvt(_T_1359) node _T_1361 = and(_T_1360, asSInt(UInt<13>(0h1000))) node _T_1362 = asSInt(_T_1361) node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0))) node _T_1364 = and(_T_1358, _T_1363) node _T_1365 = or(UInt<1>(0h0), _T_1364) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_20 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(source_ok, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(is_aligned, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1375 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_23 node _T_1379 = eq(io.in.a.bits.mask, mask) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_24 node _T_1383 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_25 node _T_1387 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1387 : node _T_1388 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1389 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_132 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_132 = bits(_uncommonBits_T_132, 1, 0) node _T_1392 = shr(io.in.a.bits.source, 2) node _T_1393 = eq(_T_1392, UInt<7>(0h70)) node _T_1394 = leq(UInt<1>(0h0), uncommonBits_132) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = leq(uncommonBits_132, UInt<2>(0h3)) node _T_1397 = and(_T_1395, _T_1396) node _uncommonBits_T_133 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_133 = bits(_uncommonBits_T_133, 1, 0) node _T_1398 = shr(io.in.a.bits.source, 2) node _T_1399 = eq(_T_1398, UInt<7>(0h71)) node _T_1400 = leq(UInt<1>(0h0), uncommonBits_133) node _T_1401 = and(_T_1399, _T_1400) node _T_1402 = leq(uncommonBits_133, UInt<2>(0h3)) node _T_1403 = and(_T_1401, _T_1402) node _uncommonBits_T_134 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_134 = bits(_uncommonBits_T_134, 1, 0) node _T_1404 = shr(io.in.a.bits.source, 2) node _T_1405 = eq(_T_1404, UInt<7>(0h72)) node _T_1406 = leq(UInt<1>(0h0), uncommonBits_134) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = leq(uncommonBits_134, UInt<2>(0h3)) node _T_1409 = and(_T_1407, _T_1408) node _uncommonBits_T_135 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_135 = bits(_uncommonBits_T_135, 1, 0) node _T_1410 = shr(io.in.a.bits.source, 2) node _T_1411 = eq(_T_1410, UInt<7>(0h73)) node _T_1412 = leq(UInt<1>(0h0), uncommonBits_135) node _T_1413 = and(_T_1411, _T_1412) node _T_1414 = leq(uncommonBits_135, UInt<2>(0h3)) node _T_1415 = and(_T_1413, _T_1414) node _uncommonBits_T_136 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_136 = bits(_uncommonBits_T_136, 1, 0) node _T_1416 = shr(io.in.a.bits.source, 2) node _T_1417 = eq(_T_1416, UInt<7>(0h7c)) node _T_1418 = leq(UInt<1>(0h0), uncommonBits_136) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = leq(uncommonBits_136, UInt<2>(0h3)) node _T_1421 = and(_T_1419, _T_1420) node _uncommonBits_T_137 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_137 = bits(_uncommonBits_T_137, 1, 0) node _T_1422 = shr(io.in.a.bits.source, 2) node _T_1423 = eq(_T_1422, UInt<7>(0h7b)) node _T_1424 = leq(UInt<1>(0h0), uncommonBits_137) node _T_1425 = and(_T_1423, _T_1424) node _T_1426 = leq(uncommonBits_137, UInt<2>(0h3)) node _T_1427 = and(_T_1425, _T_1426) node _uncommonBits_T_138 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_138 = bits(_uncommonBits_T_138, 4, 0) node _T_1428 = shr(io.in.a.bits.source, 5) node _T_1429 = eq(_T_1428, UInt<4>(0hd)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_138) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_138, UInt<5>(0h1f)) node _T_1433 = and(_T_1431, _T_1432) node _uncommonBits_T_139 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_139 = bits(_uncommonBits_T_139, 4, 0) node _T_1434 = shr(io.in.a.bits.source, 5) node _T_1435 = eq(_T_1434, UInt<4>(0hc)) node _T_1436 = leq(UInt<1>(0h0), uncommonBits_139) node _T_1437 = and(_T_1435, _T_1436) node _T_1438 = leq(uncommonBits_139, UInt<5>(0h1f)) node _T_1439 = and(_T_1437, _T_1438) node _uncommonBits_T_140 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_140 = bits(_uncommonBits_T_140, 4, 0) node _T_1440 = shr(io.in.a.bits.source, 5) node _T_1441 = eq(_T_1440, UInt<4>(0hb)) node _T_1442 = leq(UInt<1>(0h0), uncommonBits_140) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = leq(uncommonBits_140, UInt<5>(0h1f)) node _T_1445 = and(_T_1443, _T_1444) node _uncommonBits_T_141 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_141 = bits(_uncommonBits_T_141, 4, 0) node _T_1446 = shr(io.in.a.bits.source, 5) node _T_1447 = eq(_T_1446, UInt<4>(0ha)) node _T_1448 = leq(UInt<1>(0h0), uncommonBits_141) node _T_1449 = and(_T_1447, _T_1448) node _T_1450 = leq(uncommonBits_141, UInt<5>(0h1f)) node _T_1451 = and(_T_1449, _T_1450) node _uncommonBits_T_142 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_142 = bits(_uncommonBits_T_142, 4, 0) node _T_1452 = shr(io.in.a.bits.source, 5) node _T_1453 = eq(_T_1452, UInt<4>(0h9)) node _T_1454 = leq(UInt<1>(0h0), uncommonBits_142) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = leq(uncommonBits_142, UInt<5>(0h1f)) node _T_1457 = and(_T_1455, _T_1456) node _uncommonBits_T_143 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_143 = bits(_uncommonBits_T_143, 4, 0) node _T_1458 = shr(io.in.a.bits.source, 5) node _T_1459 = eq(_T_1458, UInt<4>(0h8)) node _T_1460 = leq(UInt<1>(0h0), uncommonBits_143) node _T_1461 = and(_T_1459, _T_1460) node _T_1462 = leq(uncommonBits_143, UInt<5>(0h1f)) node _T_1463 = and(_T_1461, _T_1462) node _uncommonBits_T_144 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_144 = bits(_uncommonBits_T_144, 1, 0) node _T_1464 = shr(io.in.a.bits.source, 2) node _T_1465 = eq(_T_1464, UInt<7>(0h7a)) node _T_1466 = leq(UInt<1>(0h0), uncommonBits_144) node _T_1467 = and(_T_1465, _T_1466) node _T_1468 = leq(uncommonBits_144, UInt<2>(0h3)) node _T_1469 = and(_T_1467, _T_1468) node _uncommonBits_T_145 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_145 = bits(_uncommonBits_T_145, 1, 0) node _T_1470 = shr(io.in.a.bits.source, 2) node _T_1471 = eq(_T_1470, UInt<7>(0h79)) node _T_1472 = leq(UInt<1>(0h0), uncommonBits_145) node _T_1473 = and(_T_1471, _T_1472) node _T_1474 = leq(uncommonBits_145, UInt<2>(0h3)) node _T_1475 = and(_T_1473, _T_1474) node _uncommonBits_T_146 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_146 = bits(_uncommonBits_T_146, 4, 0) node _T_1476 = shr(io.in.a.bits.source, 5) node _T_1477 = eq(_T_1476, UInt<3>(0h7)) node _T_1478 = leq(UInt<1>(0h0), uncommonBits_146) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = leq(uncommonBits_146, UInt<5>(0h1f)) node _T_1481 = and(_T_1479, _T_1480) node _uncommonBits_T_147 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_147 = bits(_uncommonBits_T_147, 4, 0) node _T_1482 = shr(io.in.a.bits.source, 5) node _T_1483 = eq(_T_1482, UInt<3>(0h6)) node _T_1484 = leq(UInt<1>(0h0), uncommonBits_147) node _T_1485 = and(_T_1483, _T_1484) node _T_1486 = leq(uncommonBits_147, UInt<5>(0h1f)) node _T_1487 = and(_T_1485, _T_1486) node _uncommonBits_T_148 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_148 = bits(_uncommonBits_T_148, 4, 0) node _T_1488 = shr(io.in.a.bits.source, 5) node _T_1489 = eq(_T_1488, UInt<3>(0h5)) node _T_1490 = leq(UInt<1>(0h0), uncommonBits_148) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = leq(uncommonBits_148, UInt<5>(0h1f)) node _T_1493 = and(_T_1491, _T_1492) node _uncommonBits_T_149 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_149 = bits(_uncommonBits_T_149, 4, 0) node _T_1494 = shr(io.in.a.bits.source, 5) node _T_1495 = eq(_T_1494, UInt<3>(0h4)) node _T_1496 = leq(UInt<1>(0h0), uncommonBits_149) node _T_1497 = and(_T_1495, _T_1496) node _T_1498 = leq(uncommonBits_149, UInt<5>(0h1f)) node _T_1499 = and(_T_1497, _T_1498) node _uncommonBits_T_150 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_150 = bits(_uncommonBits_T_150, 4, 0) node _T_1500 = shr(io.in.a.bits.source, 5) node _T_1501 = eq(_T_1500, UInt<2>(0h3)) node _T_1502 = leq(UInt<1>(0h0), uncommonBits_150) node _T_1503 = and(_T_1501, _T_1502) node _T_1504 = leq(uncommonBits_150, UInt<5>(0h1f)) node _T_1505 = and(_T_1503, _T_1504) node _uncommonBits_T_151 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_151 = bits(_uncommonBits_T_151, 4, 0) node _T_1506 = shr(io.in.a.bits.source, 5) node _T_1507 = eq(_T_1506, UInt<2>(0h2)) node _T_1508 = leq(UInt<1>(0h0), uncommonBits_151) node _T_1509 = and(_T_1507, _T_1508) node _T_1510 = leq(uncommonBits_151, UInt<5>(0h1f)) node _T_1511 = and(_T_1509, _T_1510) node _uncommonBits_T_152 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_152 = bits(_uncommonBits_T_152, 4, 0) node _T_1512 = shr(io.in.a.bits.source, 5) node _T_1513 = eq(_T_1512, UInt<1>(0h1)) node _T_1514 = leq(UInt<1>(0h0), uncommonBits_152) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = leq(uncommonBits_152, UInt<5>(0h1f)) node _T_1517 = and(_T_1515, _T_1516) node _uncommonBits_T_153 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_153 = bits(_uncommonBits_T_153, 4, 0) node _T_1518 = shr(io.in.a.bits.source, 5) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) node _T_1520 = leq(UInt<1>(0h0), uncommonBits_153) node _T_1521 = and(_T_1519, _T_1520) node _T_1522 = leq(uncommonBits_153, UInt<5>(0h1f)) node _T_1523 = and(_T_1521, _T_1522) node _T_1524 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1525 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1526 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1527 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1528 = or(_T_1391, _T_1397) node _T_1529 = or(_T_1528, _T_1403) node _T_1530 = or(_T_1529, _T_1409) node _T_1531 = or(_T_1530, _T_1415) node _T_1532 = or(_T_1531, _T_1421) node _T_1533 = or(_T_1532, _T_1427) node _T_1534 = or(_T_1533, _T_1433) node _T_1535 = or(_T_1534, _T_1439) node _T_1536 = or(_T_1535, _T_1445) node _T_1537 = or(_T_1536, _T_1451) node _T_1538 = or(_T_1537, _T_1457) node _T_1539 = or(_T_1538, _T_1463) node _T_1540 = or(_T_1539, _T_1469) node _T_1541 = or(_T_1540, _T_1475) node _T_1542 = or(_T_1541, _T_1481) node _T_1543 = or(_T_1542, _T_1487) node _T_1544 = or(_T_1543, _T_1493) node _T_1545 = or(_T_1544, _T_1499) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1511) node _T_1548 = or(_T_1547, _T_1517) node _T_1549 = or(_T_1548, _T_1523) node _T_1550 = or(_T_1549, _T_1524) node _T_1551 = or(_T_1550, _T_1525) node _T_1552 = or(_T_1551, _T_1526) node _T_1553 = or(_T_1552, _T_1527) node _T_1554 = and(_T_1390, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1557 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = or(UInt<1>(0h0), _T_1558) node _T_1560 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<13>(0h1000))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = and(_T_1559, _T_1564) node _T_1566 = or(UInt<1>(0h0), _T_1565) node _T_1567 = and(_T_1555, _T_1566) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_26 node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(source_ok, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(is_aligned, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1577 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_29 node _T_1581 = eq(io.in.a.bits.mask, mask) node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(_T_1581, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1581, UInt<1>(0h1), "") : assert_30 node _T_1585 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1585 : node _T_1586 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1587 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1588 = and(_T_1586, _T_1587) node _T_1589 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_154 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_154 = bits(_uncommonBits_T_154, 1, 0) node _T_1590 = shr(io.in.a.bits.source, 2) node _T_1591 = eq(_T_1590, UInt<7>(0h70)) node _T_1592 = leq(UInt<1>(0h0), uncommonBits_154) node _T_1593 = and(_T_1591, _T_1592) node _T_1594 = leq(uncommonBits_154, UInt<2>(0h3)) node _T_1595 = and(_T_1593, _T_1594) node _uncommonBits_T_155 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_155 = bits(_uncommonBits_T_155, 1, 0) node _T_1596 = shr(io.in.a.bits.source, 2) node _T_1597 = eq(_T_1596, UInt<7>(0h71)) node _T_1598 = leq(UInt<1>(0h0), uncommonBits_155) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = leq(uncommonBits_155, UInt<2>(0h3)) node _T_1601 = and(_T_1599, _T_1600) node _uncommonBits_T_156 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_156 = bits(_uncommonBits_T_156, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<7>(0h72)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_156) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_156, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_157 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_157 = bits(_uncommonBits_T_157, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<7>(0h73)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_157) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_157, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_158 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_158 = bits(_uncommonBits_T_158, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<7>(0h7c)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_158) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_158, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_159 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_159 = bits(_uncommonBits_T_159, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<7>(0h7b)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_159) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_159, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _uncommonBits_T_160 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_160 = bits(_uncommonBits_T_160, 4, 0) node _T_1626 = shr(io.in.a.bits.source, 5) node _T_1627 = eq(_T_1626, UInt<4>(0hd)) node _T_1628 = leq(UInt<1>(0h0), uncommonBits_160) node _T_1629 = and(_T_1627, _T_1628) node _T_1630 = leq(uncommonBits_160, UInt<5>(0h1f)) node _T_1631 = and(_T_1629, _T_1630) node _uncommonBits_T_161 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_161 = bits(_uncommonBits_T_161, 4, 0) node _T_1632 = shr(io.in.a.bits.source, 5) node _T_1633 = eq(_T_1632, UInt<4>(0hc)) node _T_1634 = leq(UInt<1>(0h0), uncommonBits_161) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = leq(uncommonBits_161, UInt<5>(0h1f)) node _T_1637 = and(_T_1635, _T_1636) node _uncommonBits_T_162 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_162 = bits(_uncommonBits_T_162, 4, 0) node _T_1638 = shr(io.in.a.bits.source, 5) node _T_1639 = eq(_T_1638, UInt<4>(0hb)) node _T_1640 = leq(UInt<1>(0h0), uncommonBits_162) node _T_1641 = and(_T_1639, _T_1640) node _T_1642 = leq(uncommonBits_162, UInt<5>(0h1f)) node _T_1643 = and(_T_1641, _T_1642) node _uncommonBits_T_163 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_163 = bits(_uncommonBits_T_163, 4, 0) node _T_1644 = shr(io.in.a.bits.source, 5) node _T_1645 = eq(_T_1644, UInt<4>(0ha)) node _T_1646 = leq(UInt<1>(0h0), uncommonBits_163) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = leq(uncommonBits_163, UInt<5>(0h1f)) node _T_1649 = and(_T_1647, _T_1648) node _uncommonBits_T_164 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_164 = bits(_uncommonBits_T_164, 4, 0) node _T_1650 = shr(io.in.a.bits.source, 5) node _T_1651 = eq(_T_1650, UInt<4>(0h9)) node _T_1652 = leq(UInt<1>(0h0), uncommonBits_164) node _T_1653 = and(_T_1651, _T_1652) node _T_1654 = leq(uncommonBits_164, UInt<5>(0h1f)) node _T_1655 = and(_T_1653, _T_1654) node _uncommonBits_T_165 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_165 = bits(_uncommonBits_T_165, 4, 0) node _T_1656 = shr(io.in.a.bits.source, 5) node _T_1657 = eq(_T_1656, UInt<4>(0h8)) node _T_1658 = leq(UInt<1>(0h0), uncommonBits_165) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = leq(uncommonBits_165, UInt<5>(0h1f)) node _T_1661 = and(_T_1659, _T_1660) node _uncommonBits_T_166 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_166 = bits(_uncommonBits_T_166, 1, 0) node _T_1662 = shr(io.in.a.bits.source, 2) node _T_1663 = eq(_T_1662, UInt<7>(0h7a)) node _T_1664 = leq(UInt<1>(0h0), uncommonBits_166) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = leq(uncommonBits_166, UInt<2>(0h3)) node _T_1667 = and(_T_1665, _T_1666) node _uncommonBits_T_167 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_167 = bits(_uncommonBits_T_167, 1, 0) node _T_1668 = shr(io.in.a.bits.source, 2) node _T_1669 = eq(_T_1668, UInt<7>(0h79)) node _T_1670 = leq(UInt<1>(0h0), uncommonBits_167) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = leq(uncommonBits_167, UInt<2>(0h3)) node _T_1673 = and(_T_1671, _T_1672) node _uncommonBits_T_168 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_168 = bits(_uncommonBits_T_168, 4, 0) node _T_1674 = shr(io.in.a.bits.source, 5) node _T_1675 = eq(_T_1674, UInt<3>(0h7)) node _T_1676 = leq(UInt<1>(0h0), uncommonBits_168) node _T_1677 = and(_T_1675, _T_1676) node _T_1678 = leq(uncommonBits_168, UInt<5>(0h1f)) node _T_1679 = and(_T_1677, _T_1678) node _uncommonBits_T_169 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_169 = bits(_uncommonBits_T_169, 4, 0) node _T_1680 = shr(io.in.a.bits.source, 5) node _T_1681 = eq(_T_1680, UInt<3>(0h6)) node _T_1682 = leq(UInt<1>(0h0), uncommonBits_169) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = leq(uncommonBits_169, UInt<5>(0h1f)) node _T_1685 = and(_T_1683, _T_1684) node _uncommonBits_T_170 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_170 = bits(_uncommonBits_T_170, 4, 0) node _T_1686 = shr(io.in.a.bits.source, 5) node _T_1687 = eq(_T_1686, UInt<3>(0h5)) node _T_1688 = leq(UInt<1>(0h0), uncommonBits_170) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = leq(uncommonBits_170, UInt<5>(0h1f)) node _T_1691 = and(_T_1689, _T_1690) node _uncommonBits_T_171 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_171 = bits(_uncommonBits_T_171, 4, 0) node _T_1692 = shr(io.in.a.bits.source, 5) node _T_1693 = eq(_T_1692, UInt<3>(0h4)) node _T_1694 = leq(UInt<1>(0h0), uncommonBits_171) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = leq(uncommonBits_171, UInt<5>(0h1f)) node _T_1697 = and(_T_1695, _T_1696) node _uncommonBits_T_172 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_172 = bits(_uncommonBits_T_172, 4, 0) node _T_1698 = shr(io.in.a.bits.source, 5) node _T_1699 = eq(_T_1698, UInt<2>(0h3)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_172) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_172, UInt<5>(0h1f)) node _T_1703 = and(_T_1701, _T_1702) node _uncommonBits_T_173 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_173 = bits(_uncommonBits_T_173, 4, 0) node _T_1704 = shr(io.in.a.bits.source, 5) node _T_1705 = eq(_T_1704, UInt<2>(0h2)) node _T_1706 = leq(UInt<1>(0h0), uncommonBits_173) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = leq(uncommonBits_173, UInt<5>(0h1f)) node _T_1709 = and(_T_1707, _T_1708) node _uncommonBits_T_174 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_174 = bits(_uncommonBits_T_174, 4, 0) node _T_1710 = shr(io.in.a.bits.source, 5) node _T_1711 = eq(_T_1710, UInt<1>(0h1)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_174) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_174, UInt<5>(0h1f)) node _T_1715 = and(_T_1713, _T_1714) node _uncommonBits_T_175 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_175 = bits(_uncommonBits_T_175, 4, 0) node _T_1716 = shr(io.in.a.bits.source, 5) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) node _T_1718 = leq(UInt<1>(0h0), uncommonBits_175) node _T_1719 = and(_T_1717, _T_1718) node _T_1720 = leq(uncommonBits_175, UInt<5>(0h1f)) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1723 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1724 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1725 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1726 = or(_T_1589, _T_1595) node _T_1727 = or(_T_1726, _T_1601) node _T_1728 = or(_T_1727, _T_1607) node _T_1729 = or(_T_1728, _T_1613) node _T_1730 = or(_T_1729, _T_1619) node _T_1731 = or(_T_1730, _T_1625) node _T_1732 = or(_T_1731, _T_1631) node _T_1733 = or(_T_1732, _T_1637) node _T_1734 = or(_T_1733, _T_1643) node _T_1735 = or(_T_1734, _T_1649) node _T_1736 = or(_T_1735, _T_1655) node _T_1737 = or(_T_1736, _T_1661) node _T_1738 = or(_T_1737, _T_1667) node _T_1739 = or(_T_1738, _T_1673) node _T_1740 = or(_T_1739, _T_1679) node _T_1741 = or(_T_1740, _T_1685) node _T_1742 = or(_T_1741, _T_1691) node _T_1743 = or(_T_1742, _T_1697) node _T_1744 = or(_T_1743, _T_1703) node _T_1745 = or(_T_1744, _T_1709) node _T_1746 = or(_T_1745, _T_1715) node _T_1747 = or(_T_1746, _T_1721) node _T_1748 = or(_T_1747, _T_1722) node _T_1749 = or(_T_1748, _T_1723) node _T_1750 = or(_T_1749, _T_1724) node _T_1751 = or(_T_1750, _T_1725) node _T_1752 = and(_T_1588, _T_1751) node _T_1753 = or(UInt<1>(0h0), _T_1752) node _T_1754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1755 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = or(UInt<1>(0h0), _T_1756) node _T_1758 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1759 = cvt(_T_1758) node _T_1760 = and(_T_1759, asSInt(UInt<13>(0h1000))) node _T_1761 = asSInt(_T_1760) node _T_1762 = eq(_T_1761, asSInt(UInt<1>(0h0))) node _T_1763 = and(_T_1757, _T_1762) node _T_1764 = or(UInt<1>(0h0), _T_1763) node _T_1765 = and(_T_1753, _T_1764) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_31 node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(source_ok, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(is_aligned, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1775 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_34 node _T_1779 = not(mask) node _T_1780 = and(io.in.a.bits.mask, _T_1779) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_35 node _T_1785 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1785 : node _T_1786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1787 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1788 = and(_T_1786, _T_1787) node _T_1789 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_176 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_176 = bits(_uncommonBits_T_176, 1, 0) node _T_1790 = shr(io.in.a.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<7>(0h70)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_176) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_176, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_177 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_177 = bits(_uncommonBits_T_177, 1, 0) node _T_1796 = shr(io.in.a.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<7>(0h71)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_177) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_177, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_178 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_178 = bits(_uncommonBits_T_178, 1, 0) node _T_1802 = shr(io.in.a.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<7>(0h72)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_178) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_178, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_179 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_179 = bits(_uncommonBits_T_179, 1, 0) node _T_1808 = shr(io.in.a.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<7>(0h73)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_179) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_179, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_180 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_180 = bits(_uncommonBits_T_180, 1, 0) node _T_1814 = shr(io.in.a.bits.source, 2) node _T_1815 = eq(_T_1814, UInt<7>(0h7c)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_180) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_180, UInt<2>(0h3)) node _T_1819 = and(_T_1817, _T_1818) node _uncommonBits_T_181 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_181 = bits(_uncommonBits_T_181, 1, 0) node _T_1820 = shr(io.in.a.bits.source, 2) node _T_1821 = eq(_T_1820, UInt<7>(0h7b)) node _T_1822 = leq(UInt<1>(0h0), uncommonBits_181) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = leq(uncommonBits_181, UInt<2>(0h3)) node _T_1825 = and(_T_1823, _T_1824) node _uncommonBits_T_182 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_182 = bits(_uncommonBits_T_182, 4, 0) node _T_1826 = shr(io.in.a.bits.source, 5) node _T_1827 = eq(_T_1826, UInt<4>(0hd)) node _T_1828 = leq(UInt<1>(0h0), uncommonBits_182) node _T_1829 = and(_T_1827, _T_1828) node _T_1830 = leq(uncommonBits_182, UInt<5>(0h1f)) node _T_1831 = and(_T_1829, _T_1830) node _uncommonBits_T_183 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_183 = bits(_uncommonBits_T_183, 4, 0) node _T_1832 = shr(io.in.a.bits.source, 5) node _T_1833 = eq(_T_1832, UInt<4>(0hc)) node _T_1834 = leq(UInt<1>(0h0), uncommonBits_183) node _T_1835 = and(_T_1833, _T_1834) node _T_1836 = leq(uncommonBits_183, UInt<5>(0h1f)) node _T_1837 = and(_T_1835, _T_1836) node _uncommonBits_T_184 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_184 = bits(_uncommonBits_T_184, 4, 0) node _T_1838 = shr(io.in.a.bits.source, 5) node _T_1839 = eq(_T_1838, UInt<4>(0hb)) node _T_1840 = leq(UInt<1>(0h0), uncommonBits_184) node _T_1841 = and(_T_1839, _T_1840) node _T_1842 = leq(uncommonBits_184, UInt<5>(0h1f)) node _T_1843 = and(_T_1841, _T_1842) node _uncommonBits_T_185 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_185 = bits(_uncommonBits_T_185, 4, 0) node _T_1844 = shr(io.in.a.bits.source, 5) node _T_1845 = eq(_T_1844, UInt<4>(0ha)) node _T_1846 = leq(UInt<1>(0h0), uncommonBits_185) node _T_1847 = and(_T_1845, _T_1846) node _T_1848 = leq(uncommonBits_185, UInt<5>(0h1f)) node _T_1849 = and(_T_1847, _T_1848) node _uncommonBits_T_186 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_186 = bits(_uncommonBits_T_186, 4, 0) node _T_1850 = shr(io.in.a.bits.source, 5) node _T_1851 = eq(_T_1850, UInt<4>(0h9)) node _T_1852 = leq(UInt<1>(0h0), uncommonBits_186) node _T_1853 = and(_T_1851, _T_1852) node _T_1854 = leq(uncommonBits_186, UInt<5>(0h1f)) node _T_1855 = and(_T_1853, _T_1854) node _uncommonBits_T_187 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_187 = bits(_uncommonBits_T_187, 4, 0) node _T_1856 = shr(io.in.a.bits.source, 5) node _T_1857 = eq(_T_1856, UInt<4>(0h8)) node _T_1858 = leq(UInt<1>(0h0), uncommonBits_187) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = leq(uncommonBits_187, UInt<5>(0h1f)) node _T_1861 = and(_T_1859, _T_1860) node _uncommonBits_T_188 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_188 = bits(_uncommonBits_T_188, 1, 0) node _T_1862 = shr(io.in.a.bits.source, 2) node _T_1863 = eq(_T_1862, UInt<7>(0h7a)) node _T_1864 = leq(UInt<1>(0h0), uncommonBits_188) node _T_1865 = and(_T_1863, _T_1864) node _T_1866 = leq(uncommonBits_188, UInt<2>(0h3)) node _T_1867 = and(_T_1865, _T_1866) node _uncommonBits_T_189 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_189 = bits(_uncommonBits_T_189, 1, 0) node _T_1868 = shr(io.in.a.bits.source, 2) node _T_1869 = eq(_T_1868, UInt<7>(0h79)) node _T_1870 = leq(UInt<1>(0h0), uncommonBits_189) node _T_1871 = and(_T_1869, _T_1870) node _T_1872 = leq(uncommonBits_189, UInt<2>(0h3)) node _T_1873 = and(_T_1871, _T_1872) node _uncommonBits_T_190 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_190 = bits(_uncommonBits_T_190, 4, 0) node _T_1874 = shr(io.in.a.bits.source, 5) node _T_1875 = eq(_T_1874, UInt<3>(0h7)) node _T_1876 = leq(UInt<1>(0h0), uncommonBits_190) node _T_1877 = and(_T_1875, _T_1876) node _T_1878 = leq(uncommonBits_190, UInt<5>(0h1f)) node _T_1879 = and(_T_1877, _T_1878) node _uncommonBits_T_191 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_191 = bits(_uncommonBits_T_191, 4, 0) node _T_1880 = shr(io.in.a.bits.source, 5) node _T_1881 = eq(_T_1880, UInt<3>(0h6)) node _T_1882 = leq(UInt<1>(0h0), uncommonBits_191) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = leq(uncommonBits_191, UInt<5>(0h1f)) node _T_1885 = and(_T_1883, _T_1884) node _uncommonBits_T_192 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_192 = bits(_uncommonBits_T_192, 4, 0) node _T_1886 = shr(io.in.a.bits.source, 5) node _T_1887 = eq(_T_1886, UInt<3>(0h5)) node _T_1888 = leq(UInt<1>(0h0), uncommonBits_192) node _T_1889 = and(_T_1887, _T_1888) node _T_1890 = leq(uncommonBits_192, UInt<5>(0h1f)) node _T_1891 = and(_T_1889, _T_1890) node _uncommonBits_T_193 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_193 = bits(_uncommonBits_T_193, 4, 0) node _T_1892 = shr(io.in.a.bits.source, 5) node _T_1893 = eq(_T_1892, UInt<3>(0h4)) node _T_1894 = leq(UInt<1>(0h0), uncommonBits_193) node _T_1895 = and(_T_1893, _T_1894) node _T_1896 = leq(uncommonBits_193, UInt<5>(0h1f)) node _T_1897 = and(_T_1895, _T_1896) node _uncommonBits_T_194 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_194 = bits(_uncommonBits_T_194, 4, 0) node _T_1898 = shr(io.in.a.bits.source, 5) node _T_1899 = eq(_T_1898, UInt<2>(0h3)) node _T_1900 = leq(UInt<1>(0h0), uncommonBits_194) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = leq(uncommonBits_194, UInt<5>(0h1f)) node _T_1903 = and(_T_1901, _T_1902) node _uncommonBits_T_195 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_195 = bits(_uncommonBits_T_195, 4, 0) node _T_1904 = shr(io.in.a.bits.source, 5) node _T_1905 = eq(_T_1904, UInt<2>(0h2)) node _T_1906 = leq(UInt<1>(0h0), uncommonBits_195) node _T_1907 = and(_T_1905, _T_1906) node _T_1908 = leq(uncommonBits_195, UInt<5>(0h1f)) node _T_1909 = and(_T_1907, _T_1908) node _uncommonBits_T_196 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_196 = bits(_uncommonBits_T_196, 4, 0) node _T_1910 = shr(io.in.a.bits.source, 5) node _T_1911 = eq(_T_1910, UInt<1>(0h1)) node _T_1912 = leq(UInt<1>(0h0), uncommonBits_196) node _T_1913 = and(_T_1911, _T_1912) node _T_1914 = leq(uncommonBits_196, UInt<5>(0h1f)) node _T_1915 = and(_T_1913, _T_1914) node _uncommonBits_T_197 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_197 = bits(_uncommonBits_T_197, 4, 0) node _T_1916 = shr(io.in.a.bits.source, 5) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) node _T_1918 = leq(UInt<1>(0h0), uncommonBits_197) node _T_1919 = and(_T_1917, _T_1918) node _T_1920 = leq(uncommonBits_197, UInt<5>(0h1f)) node _T_1921 = and(_T_1919, _T_1920) node _T_1922 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1923 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1924 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1925 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1926 = or(_T_1789, _T_1795) node _T_1927 = or(_T_1926, _T_1801) node _T_1928 = or(_T_1927, _T_1807) node _T_1929 = or(_T_1928, _T_1813) node _T_1930 = or(_T_1929, _T_1819) node _T_1931 = or(_T_1930, _T_1825) node _T_1932 = or(_T_1931, _T_1831) node _T_1933 = or(_T_1932, _T_1837) node _T_1934 = or(_T_1933, _T_1843) node _T_1935 = or(_T_1934, _T_1849) node _T_1936 = or(_T_1935, _T_1855) node _T_1937 = or(_T_1936, _T_1861) node _T_1938 = or(_T_1937, _T_1867) node _T_1939 = or(_T_1938, _T_1873) node _T_1940 = or(_T_1939, _T_1879) node _T_1941 = or(_T_1940, _T_1885) node _T_1942 = or(_T_1941, _T_1891) node _T_1943 = or(_T_1942, _T_1897) node _T_1944 = or(_T_1943, _T_1903) node _T_1945 = or(_T_1944, _T_1909) node _T_1946 = or(_T_1945, _T_1915) node _T_1947 = or(_T_1946, _T_1921) node _T_1948 = or(_T_1947, _T_1922) node _T_1949 = or(_T_1948, _T_1923) node _T_1950 = or(_T_1949, _T_1924) node _T_1951 = or(_T_1950, _T_1925) node _T_1952 = and(_T_1788, _T_1951) node _T_1953 = or(UInt<1>(0h0), _T_1952) node _T_1954 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1955 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1956 = cvt(_T_1955) node _T_1957 = and(_T_1956, asSInt(UInt<13>(0h1000))) node _T_1958 = asSInt(_T_1957) node _T_1959 = eq(_T_1958, asSInt(UInt<1>(0h0))) node _T_1960 = and(_T_1954, _T_1959) node _T_1961 = or(UInt<1>(0h0), _T_1960) node _T_1962 = and(_T_1953, _T_1961) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_36 node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(source_ok, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1969 = asUInt(reset) node _T_1970 = eq(_T_1969, UInt<1>(0h0)) when _T_1970 : node _T_1971 = eq(is_aligned, UInt<1>(0h0)) when _T_1971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1972 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(_T_1972, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1972, UInt<1>(0h1), "") : assert_39 node _T_1976 = eq(io.in.a.bits.mask, mask) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_40 node _T_1980 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1980 : node _T_1981 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1982 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1983 = and(_T_1981, _T_1982) node _T_1984 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_198 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_198 = bits(_uncommonBits_T_198, 1, 0) node _T_1985 = shr(io.in.a.bits.source, 2) node _T_1986 = eq(_T_1985, UInt<7>(0h70)) node _T_1987 = leq(UInt<1>(0h0), uncommonBits_198) node _T_1988 = and(_T_1986, _T_1987) node _T_1989 = leq(uncommonBits_198, UInt<2>(0h3)) node _T_1990 = and(_T_1988, _T_1989) node _uncommonBits_T_199 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_199 = bits(_uncommonBits_T_199, 1, 0) node _T_1991 = shr(io.in.a.bits.source, 2) node _T_1992 = eq(_T_1991, UInt<7>(0h71)) node _T_1993 = leq(UInt<1>(0h0), uncommonBits_199) node _T_1994 = and(_T_1992, _T_1993) node _T_1995 = leq(uncommonBits_199, UInt<2>(0h3)) node _T_1996 = and(_T_1994, _T_1995) node _uncommonBits_T_200 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_200 = bits(_uncommonBits_T_200, 1, 0) node _T_1997 = shr(io.in.a.bits.source, 2) node _T_1998 = eq(_T_1997, UInt<7>(0h72)) node _T_1999 = leq(UInt<1>(0h0), uncommonBits_200) node _T_2000 = and(_T_1998, _T_1999) node _T_2001 = leq(uncommonBits_200, UInt<2>(0h3)) node _T_2002 = and(_T_2000, _T_2001) node _uncommonBits_T_201 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_201 = bits(_uncommonBits_T_201, 1, 0) node _T_2003 = shr(io.in.a.bits.source, 2) node _T_2004 = eq(_T_2003, UInt<7>(0h73)) node _T_2005 = leq(UInt<1>(0h0), uncommonBits_201) node _T_2006 = and(_T_2004, _T_2005) node _T_2007 = leq(uncommonBits_201, UInt<2>(0h3)) node _T_2008 = and(_T_2006, _T_2007) node _uncommonBits_T_202 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_202 = bits(_uncommonBits_T_202, 1, 0) node _T_2009 = shr(io.in.a.bits.source, 2) node _T_2010 = eq(_T_2009, UInt<7>(0h7c)) node _T_2011 = leq(UInt<1>(0h0), uncommonBits_202) node _T_2012 = and(_T_2010, _T_2011) node _T_2013 = leq(uncommonBits_202, UInt<2>(0h3)) node _T_2014 = and(_T_2012, _T_2013) node _uncommonBits_T_203 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_203 = bits(_uncommonBits_T_203, 1, 0) node _T_2015 = shr(io.in.a.bits.source, 2) node _T_2016 = eq(_T_2015, UInt<7>(0h7b)) node _T_2017 = leq(UInt<1>(0h0), uncommonBits_203) node _T_2018 = and(_T_2016, _T_2017) node _T_2019 = leq(uncommonBits_203, UInt<2>(0h3)) node _T_2020 = and(_T_2018, _T_2019) node _uncommonBits_T_204 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_204 = bits(_uncommonBits_T_204, 4, 0) node _T_2021 = shr(io.in.a.bits.source, 5) node _T_2022 = eq(_T_2021, UInt<4>(0hd)) node _T_2023 = leq(UInt<1>(0h0), uncommonBits_204) node _T_2024 = and(_T_2022, _T_2023) node _T_2025 = leq(uncommonBits_204, UInt<5>(0h1f)) node _T_2026 = and(_T_2024, _T_2025) node _uncommonBits_T_205 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_205 = bits(_uncommonBits_T_205, 4, 0) node _T_2027 = shr(io.in.a.bits.source, 5) node _T_2028 = eq(_T_2027, UInt<4>(0hc)) node _T_2029 = leq(UInt<1>(0h0), uncommonBits_205) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = leq(uncommonBits_205, UInt<5>(0h1f)) node _T_2032 = and(_T_2030, _T_2031) node _uncommonBits_T_206 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_206 = bits(_uncommonBits_T_206, 4, 0) node _T_2033 = shr(io.in.a.bits.source, 5) node _T_2034 = eq(_T_2033, UInt<4>(0hb)) node _T_2035 = leq(UInt<1>(0h0), uncommonBits_206) node _T_2036 = and(_T_2034, _T_2035) node _T_2037 = leq(uncommonBits_206, UInt<5>(0h1f)) node _T_2038 = and(_T_2036, _T_2037) node _uncommonBits_T_207 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_207 = bits(_uncommonBits_T_207, 4, 0) node _T_2039 = shr(io.in.a.bits.source, 5) node _T_2040 = eq(_T_2039, UInt<4>(0ha)) node _T_2041 = leq(UInt<1>(0h0), uncommonBits_207) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = leq(uncommonBits_207, UInt<5>(0h1f)) node _T_2044 = and(_T_2042, _T_2043) node _uncommonBits_T_208 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_208 = bits(_uncommonBits_T_208, 4, 0) node _T_2045 = shr(io.in.a.bits.source, 5) node _T_2046 = eq(_T_2045, UInt<4>(0h9)) node _T_2047 = leq(UInt<1>(0h0), uncommonBits_208) node _T_2048 = and(_T_2046, _T_2047) node _T_2049 = leq(uncommonBits_208, UInt<5>(0h1f)) node _T_2050 = and(_T_2048, _T_2049) node _uncommonBits_T_209 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_209 = bits(_uncommonBits_T_209, 4, 0) node _T_2051 = shr(io.in.a.bits.source, 5) node _T_2052 = eq(_T_2051, UInt<4>(0h8)) node _T_2053 = leq(UInt<1>(0h0), uncommonBits_209) node _T_2054 = and(_T_2052, _T_2053) node _T_2055 = leq(uncommonBits_209, UInt<5>(0h1f)) node _T_2056 = and(_T_2054, _T_2055) node _uncommonBits_T_210 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_210 = bits(_uncommonBits_T_210, 1, 0) node _T_2057 = shr(io.in.a.bits.source, 2) node _T_2058 = eq(_T_2057, UInt<7>(0h7a)) node _T_2059 = leq(UInt<1>(0h0), uncommonBits_210) node _T_2060 = and(_T_2058, _T_2059) node _T_2061 = leq(uncommonBits_210, UInt<2>(0h3)) node _T_2062 = and(_T_2060, _T_2061) node _uncommonBits_T_211 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_211 = bits(_uncommonBits_T_211, 1, 0) node _T_2063 = shr(io.in.a.bits.source, 2) node _T_2064 = eq(_T_2063, UInt<7>(0h79)) node _T_2065 = leq(UInt<1>(0h0), uncommonBits_211) node _T_2066 = and(_T_2064, _T_2065) node _T_2067 = leq(uncommonBits_211, UInt<2>(0h3)) node _T_2068 = and(_T_2066, _T_2067) node _uncommonBits_T_212 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_212 = bits(_uncommonBits_T_212, 4, 0) node _T_2069 = shr(io.in.a.bits.source, 5) node _T_2070 = eq(_T_2069, UInt<3>(0h7)) node _T_2071 = leq(UInt<1>(0h0), uncommonBits_212) node _T_2072 = and(_T_2070, _T_2071) node _T_2073 = leq(uncommonBits_212, UInt<5>(0h1f)) node _T_2074 = and(_T_2072, _T_2073) node _uncommonBits_T_213 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_213 = bits(_uncommonBits_T_213, 4, 0) node _T_2075 = shr(io.in.a.bits.source, 5) node _T_2076 = eq(_T_2075, UInt<3>(0h6)) node _T_2077 = leq(UInt<1>(0h0), uncommonBits_213) node _T_2078 = and(_T_2076, _T_2077) node _T_2079 = leq(uncommonBits_213, UInt<5>(0h1f)) node _T_2080 = and(_T_2078, _T_2079) node _uncommonBits_T_214 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_214 = bits(_uncommonBits_T_214, 4, 0) node _T_2081 = shr(io.in.a.bits.source, 5) node _T_2082 = eq(_T_2081, UInt<3>(0h5)) node _T_2083 = leq(UInt<1>(0h0), uncommonBits_214) node _T_2084 = and(_T_2082, _T_2083) node _T_2085 = leq(uncommonBits_214, UInt<5>(0h1f)) node _T_2086 = and(_T_2084, _T_2085) node _uncommonBits_T_215 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_215 = bits(_uncommonBits_T_215, 4, 0) node _T_2087 = shr(io.in.a.bits.source, 5) node _T_2088 = eq(_T_2087, UInt<3>(0h4)) node _T_2089 = leq(UInt<1>(0h0), uncommonBits_215) node _T_2090 = and(_T_2088, _T_2089) node _T_2091 = leq(uncommonBits_215, UInt<5>(0h1f)) node _T_2092 = and(_T_2090, _T_2091) node _uncommonBits_T_216 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_216 = bits(_uncommonBits_T_216, 4, 0) node _T_2093 = shr(io.in.a.bits.source, 5) node _T_2094 = eq(_T_2093, UInt<2>(0h3)) node _T_2095 = leq(UInt<1>(0h0), uncommonBits_216) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = leq(uncommonBits_216, UInt<5>(0h1f)) node _T_2098 = and(_T_2096, _T_2097) node _uncommonBits_T_217 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_217 = bits(_uncommonBits_T_217, 4, 0) node _T_2099 = shr(io.in.a.bits.source, 5) node _T_2100 = eq(_T_2099, UInt<2>(0h2)) node _T_2101 = leq(UInt<1>(0h0), uncommonBits_217) node _T_2102 = and(_T_2100, _T_2101) node _T_2103 = leq(uncommonBits_217, UInt<5>(0h1f)) node _T_2104 = and(_T_2102, _T_2103) node _uncommonBits_T_218 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_218 = bits(_uncommonBits_T_218, 4, 0) node _T_2105 = shr(io.in.a.bits.source, 5) node _T_2106 = eq(_T_2105, UInt<1>(0h1)) node _T_2107 = leq(UInt<1>(0h0), uncommonBits_218) node _T_2108 = and(_T_2106, _T_2107) node _T_2109 = leq(uncommonBits_218, UInt<5>(0h1f)) node _T_2110 = and(_T_2108, _T_2109) node _uncommonBits_T_219 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_219 = bits(_uncommonBits_T_219, 4, 0) node _T_2111 = shr(io.in.a.bits.source, 5) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) node _T_2113 = leq(UInt<1>(0h0), uncommonBits_219) node _T_2114 = and(_T_2112, _T_2113) node _T_2115 = leq(uncommonBits_219, UInt<5>(0h1f)) node _T_2116 = and(_T_2114, _T_2115) node _T_2117 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2118 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_2119 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2120 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_2121 = or(_T_1984, _T_1990) node _T_2122 = or(_T_2121, _T_1996) node _T_2123 = or(_T_2122, _T_2002) node _T_2124 = or(_T_2123, _T_2008) node _T_2125 = or(_T_2124, _T_2014) node _T_2126 = or(_T_2125, _T_2020) node _T_2127 = or(_T_2126, _T_2026) node _T_2128 = or(_T_2127, _T_2032) node _T_2129 = or(_T_2128, _T_2038) node _T_2130 = or(_T_2129, _T_2044) node _T_2131 = or(_T_2130, _T_2050) node _T_2132 = or(_T_2131, _T_2056) node _T_2133 = or(_T_2132, _T_2062) node _T_2134 = or(_T_2133, _T_2068) node _T_2135 = or(_T_2134, _T_2074) node _T_2136 = or(_T_2135, _T_2080) node _T_2137 = or(_T_2136, _T_2086) node _T_2138 = or(_T_2137, _T_2092) node _T_2139 = or(_T_2138, _T_2098) node _T_2140 = or(_T_2139, _T_2104) node _T_2141 = or(_T_2140, _T_2110) node _T_2142 = or(_T_2141, _T_2116) node _T_2143 = or(_T_2142, _T_2117) node _T_2144 = or(_T_2143, _T_2118) node _T_2145 = or(_T_2144, _T_2119) node _T_2146 = or(_T_2145, _T_2120) node _T_2147 = and(_T_1983, _T_2146) node _T_2148 = or(UInt<1>(0h0), _T_2147) node _T_2149 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2150 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = and(_T_2149, _T_2154) node _T_2156 = or(UInt<1>(0h0), _T_2155) node _T_2157 = and(_T_2148, _T_2156) node _T_2158 = asUInt(reset) node _T_2159 = eq(_T_2158, UInt<1>(0h0)) when _T_2159 : node _T_2160 = eq(_T_2157, UInt<1>(0h0)) when _T_2160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_2157, UInt<1>(0h1), "") : assert_41 node _T_2161 = asUInt(reset) node _T_2162 = eq(_T_2161, UInt<1>(0h0)) when _T_2162 : node _T_2163 = eq(source_ok, UInt<1>(0h0)) when _T_2163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_2164 = asUInt(reset) node _T_2165 = eq(_T_2164, UInt<1>(0h0)) when _T_2165 : node _T_2166 = eq(is_aligned, UInt<1>(0h0)) when _T_2166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_2167 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_2168 = asUInt(reset) node _T_2169 = eq(_T_2168, UInt<1>(0h0)) when _T_2169 : node _T_2170 = eq(_T_2167, UInt<1>(0h0)) when _T_2170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_2167, UInt<1>(0h1), "") : assert_44 node _T_2171 = eq(io.in.a.bits.mask, mask) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_45 node _T_2175 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_2175 : node _T_2176 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2177 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2178 = and(_T_2176, _T_2177) node _T_2179 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_220 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_220 = bits(_uncommonBits_T_220, 1, 0) node _T_2180 = shr(io.in.a.bits.source, 2) node _T_2181 = eq(_T_2180, UInt<7>(0h70)) node _T_2182 = leq(UInt<1>(0h0), uncommonBits_220) node _T_2183 = and(_T_2181, _T_2182) node _T_2184 = leq(uncommonBits_220, UInt<2>(0h3)) node _T_2185 = and(_T_2183, _T_2184) node _uncommonBits_T_221 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_221 = bits(_uncommonBits_T_221, 1, 0) node _T_2186 = shr(io.in.a.bits.source, 2) node _T_2187 = eq(_T_2186, UInt<7>(0h71)) node _T_2188 = leq(UInt<1>(0h0), uncommonBits_221) node _T_2189 = and(_T_2187, _T_2188) node _T_2190 = leq(uncommonBits_221, UInt<2>(0h3)) node _T_2191 = and(_T_2189, _T_2190) node _uncommonBits_T_222 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_222 = bits(_uncommonBits_T_222, 1, 0) node _T_2192 = shr(io.in.a.bits.source, 2) node _T_2193 = eq(_T_2192, UInt<7>(0h72)) node _T_2194 = leq(UInt<1>(0h0), uncommonBits_222) node _T_2195 = and(_T_2193, _T_2194) node _T_2196 = leq(uncommonBits_222, UInt<2>(0h3)) node _T_2197 = and(_T_2195, _T_2196) node _uncommonBits_T_223 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_223 = bits(_uncommonBits_T_223, 1, 0) node _T_2198 = shr(io.in.a.bits.source, 2) node _T_2199 = eq(_T_2198, UInt<7>(0h73)) node _T_2200 = leq(UInt<1>(0h0), uncommonBits_223) node _T_2201 = and(_T_2199, _T_2200) node _T_2202 = leq(uncommonBits_223, UInt<2>(0h3)) node _T_2203 = and(_T_2201, _T_2202) node _uncommonBits_T_224 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_224 = bits(_uncommonBits_T_224, 1, 0) node _T_2204 = shr(io.in.a.bits.source, 2) node _T_2205 = eq(_T_2204, UInt<7>(0h7c)) node _T_2206 = leq(UInt<1>(0h0), uncommonBits_224) node _T_2207 = and(_T_2205, _T_2206) node _T_2208 = leq(uncommonBits_224, UInt<2>(0h3)) node _T_2209 = and(_T_2207, _T_2208) node _uncommonBits_T_225 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_225 = bits(_uncommonBits_T_225, 1, 0) node _T_2210 = shr(io.in.a.bits.source, 2) node _T_2211 = eq(_T_2210, UInt<7>(0h7b)) node _T_2212 = leq(UInt<1>(0h0), uncommonBits_225) node _T_2213 = and(_T_2211, _T_2212) node _T_2214 = leq(uncommonBits_225, UInt<2>(0h3)) node _T_2215 = and(_T_2213, _T_2214) node _uncommonBits_T_226 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_226 = bits(_uncommonBits_T_226, 4, 0) node _T_2216 = shr(io.in.a.bits.source, 5) node _T_2217 = eq(_T_2216, UInt<4>(0hd)) node _T_2218 = leq(UInt<1>(0h0), uncommonBits_226) node _T_2219 = and(_T_2217, _T_2218) node _T_2220 = leq(uncommonBits_226, UInt<5>(0h1f)) node _T_2221 = and(_T_2219, _T_2220) node _uncommonBits_T_227 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_227 = bits(_uncommonBits_T_227, 4, 0) node _T_2222 = shr(io.in.a.bits.source, 5) node _T_2223 = eq(_T_2222, UInt<4>(0hc)) node _T_2224 = leq(UInt<1>(0h0), uncommonBits_227) node _T_2225 = and(_T_2223, _T_2224) node _T_2226 = leq(uncommonBits_227, UInt<5>(0h1f)) node _T_2227 = and(_T_2225, _T_2226) node _uncommonBits_T_228 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_228 = bits(_uncommonBits_T_228, 4, 0) node _T_2228 = shr(io.in.a.bits.source, 5) node _T_2229 = eq(_T_2228, UInt<4>(0hb)) node _T_2230 = leq(UInt<1>(0h0), uncommonBits_228) node _T_2231 = and(_T_2229, _T_2230) node _T_2232 = leq(uncommonBits_228, UInt<5>(0h1f)) node _T_2233 = and(_T_2231, _T_2232) node _uncommonBits_T_229 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_229 = bits(_uncommonBits_T_229, 4, 0) node _T_2234 = shr(io.in.a.bits.source, 5) node _T_2235 = eq(_T_2234, UInt<4>(0ha)) node _T_2236 = leq(UInt<1>(0h0), uncommonBits_229) node _T_2237 = and(_T_2235, _T_2236) node _T_2238 = leq(uncommonBits_229, UInt<5>(0h1f)) node _T_2239 = and(_T_2237, _T_2238) node _uncommonBits_T_230 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_230 = bits(_uncommonBits_T_230, 4, 0) node _T_2240 = shr(io.in.a.bits.source, 5) node _T_2241 = eq(_T_2240, UInt<4>(0h9)) node _T_2242 = leq(UInt<1>(0h0), uncommonBits_230) node _T_2243 = and(_T_2241, _T_2242) node _T_2244 = leq(uncommonBits_230, UInt<5>(0h1f)) node _T_2245 = and(_T_2243, _T_2244) node _uncommonBits_T_231 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_231 = bits(_uncommonBits_T_231, 4, 0) node _T_2246 = shr(io.in.a.bits.source, 5) node _T_2247 = eq(_T_2246, UInt<4>(0h8)) node _T_2248 = leq(UInt<1>(0h0), uncommonBits_231) node _T_2249 = and(_T_2247, _T_2248) node _T_2250 = leq(uncommonBits_231, UInt<5>(0h1f)) node _T_2251 = and(_T_2249, _T_2250) node _uncommonBits_T_232 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_232 = bits(_uncommonBits_T_232, 1, 0) node _T_2252 = shr(io.in.a.bits.source, 2) node _T_2253 = eq(_T_2252, UInt<7>(0h7a)) node _T_2254 = leq(UInt<1>(0h0), uncommonBits_232) node _T_2255 = and(_T_2253, _T_2254) node _T_2256 = leq(uncommonBits_232, UInt<2>(0h3)) node _T_2257 = and(_T_2255, _T_2256) node _uncommonBits_T_233 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_233 = bits(_uncommonBits_T_233, 1, 0) node _T_2258 = shr(io.in.a.bits.source, 2) node _T_2259 = eq(_T_2258, UInt<7>(0h79)) node _T_2260 = leq(UInt<1>(0h0), uncommonBits_233) node _T_2261 = and(_T_2259, _T_2260) node _T_2262 = leq(uncommonBits_233, UInt<2>(0h3)) node _T_2263 = and(_T_2261, _T_2262) node _uncommonBits_T_234 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_234 = bits(_uncommonBits_T_234, 4, 0) node _T_2264 = shr(io.in.a.bits.source, 5) node _T_2265 = eq(_T_2264, UInt<3>(0h7)) node _T_2266 = leq(UInt<1>(0h0), uncommonBits_234) node _T_2267 = and(_T_2265, _T_2266) node _T_2268 = leq(uncommonBits_234, UInt<5>(0h1f)) node _T_2269 = and(_T_2267, _T_2268) node _uncommonBits_T_235 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_235 = bits(_uncommonBits_T_235, 4, 0) node _T_2270 = shr(io.in.a.bits.source, 5) node _T_2271 = eq(_T_2270, UInt<3>(0h6)) node _T_2272 = leq(UInt<1>(0h0), uncommonBits_235) node _T_2273 = and(_T_2271, _T_2272) node _T_2274 = leq(uncommonBits_235, UInt<5>(0h1f)) node _T_2275 = and(_T_2273, _T_2274) node _uncommonBits_T_236 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_236 = bits(_uncommonBits_T_236, 4, 0) node _T_2276 = shr(io.in.a.bits.source, 5) node _T_2277 = eq(_T_2276, UInt<3>(0h5)) node _T_2278 = leq(UInt<1>(0h0), uncommonBits_236) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = leq(uncommonBits_236, UInt<5>(0h1f)) node _T_2281 = and(_T_2279, _T_2280) node _uncommonBits_T_237 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_237 = bits(_uncommonBits_T_237, 4, 0) node _T_2282 = shr(io.in.a.bits.source, 5) node _T_2283 = eq(_T_2282, UInt<3>(0h4)) node _T_2284 = leq(UInt<1>(0h0), uncommonBits_237) node _T_2285 = and(_T_2283, _T_2284) node _T_2286 = leq(uncommonBits_237, UInt<5>(0h1f)) node _T_2287 = and(_T_2285, _T_2286) node _uncommonBits_T_238 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_238 = bits(_uncommonBits_T_238, 4, 0) node _T_2288 = shr(io.in.a.bits.source, 5) node _T_2289 = eq(_T_2288, UInt<2>(0h3)) node _T_2290 = leq(UInt<1>(0h0), uncommonBits_238) node _T_2291 = and(_T_2289, _T_2290) node _T_2292 = leq(uncommonBits_238, UInt<5>(0h1f)) node _T_2293 = and(_T_2291, _T_2292) node _uncommonBits_T_239 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_239 = bits(_uncommonBits_T_239, 4, 0) node _T_2294 = shr(io.in.a.bits.source, 5) node _T_2295 = eq(_T_2294, UInt<2>(0h2)) node _T_2296 = leq(UInt<1>(0h0), uncommonBits_239) node _T_2297 = and(_T_2295, _T_2296) node _T_2298 = leq(uncommonBits_239, UInt<5>(0h1f)) node _T_2299 = and(_T_2297, _T_2298) node _uncommonBits_T_240 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_240 = bits(_uncommonBits_T_240, 4, 0) node _T_2300 = shr(io.in.a.bits.source, 5) node _T_2301 = eq(_T_2300, UInt<1>(0h1)) node _T_2302 = leq(UInt<1>(0h0), uncommonBits_240) node _T_2303 = and(_T_2301, _T_2302) node _T_2304 = leq(uncommonBits_240, UInt<5>(0h1f)) node _T_2305 = and(_T_2303, _T_2304) node _uncommonBits_T_241 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_241 = bits(_uncommonBits_T_241, 4, 0) node _T_2306 = shr(io.in.a.bits.source, 5) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) node _T_2308 = leq(UInt<1>(0h0), uncommonBits_241) node _T_2309 = and(_T_2307, _T_2308) node _T_2310 = leq(uncommonBits_241, UInt<5>(0h1f)) node _T_2311 = and(_T_2309, _T_2310) node _T_2312 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2313 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_2314 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2315 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_2316 = or(_T_2179, _T_2185) node _T_2317 = or(_T_2316, _T_2191) node _T_2318 = or(_T_2317, _T_2197) node _T_2319 = or(_T_2318, _T_2203) node _T_2320 = or(_T_2319, _T_2209) node _T_2321 = or(_T_2320, _T_2215) node _T_2322 = or(_T_2321, _T_2221) node _T_2323 = or(_T_2322, _T_2227) node _T_2324 = or(_T_2323, _T_2233) node _T_2325 = or(_T_2324, _T_2239) node _T_2326 = or(_T_2325, _T_2245) node _T_2327 = or(_T_2326, _T_2251) node _T_2328 = or(_T_2327, _T_2257) node _T_2329 = or(_T_2328, _T_2263) node _T_2330 = or(_T_2329, _T_2269) node _T_2331 = or(_T_2330, _T_2275) node _T_2332 = or(_T_2331, _T_2281) node _T_2333 = or(_T_2332, _T_2287) node _T_2334 = or(_T_2333, _T_2293) node _T_2335 = or(_T_2334, _T_2299) node _T_2336 = or(_T_2335, _T_2305) node _T_2337 = or(_T_2336, _T_2311) node _T_2338 = or(_T_2337, _T_2312) node _T_2339 = or(_T_2338, _T_2313) node _T_2340 = or(_T_2339, _T_2314) node _T_2341 = or(_T_2340, _T_2315) node _T_2342 = and(_T_2178, _T_2341) node _T_2343 = or(UInt<1>(0h0), _T_2342) node _T_2344 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2345 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2346 = cvt(_T_2345) node _T_2347 = and(_T_2346, asSInt(UInt<13>(0h1000))) node _T_2348 = asSInt(_T_2347) node _T_2349 = eq(_T_2348, asSInt(UInt<1>(0h0))) node _T_2350 = and(_T_2344, _T_2349) node _T_2351 = or(UInt<1>(0h0), _T_2350) node _T_2352 = and(_T_2343, _T_2351) node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(_T_2352, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2352, UInt<1>(0h1), "") : assert_46 node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(source_ok, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(is_aligned, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2362 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2363 = asUInt(reset) node _T_2364 = eq(_T_2363, UInt<1>(0h0)) when _T_2364 : node _T_2365 = eq(_T_2362, UInt<1>(0h0)) when _T_2365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2362, UInt<1>(0h1), "") : assert_49 node _T_2366 = eq(io.in.a.bits.mask, mask) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_50 node _T_2370 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2371 = asUInt(reset) node _T_2372 = eq(_T_2371, UInt<1>(0h0)) when _T_2372 : node _T_2373 = eq(_T_2370, UInt<1>(0h0)) when _T_2373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2370, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2374 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2375 = asUInt(reset) node _T_2376 = eq(_T_2375, UInt<1>(0h0)) when _T_2376 : node _T_2377 = eq(_T_2374, UInt<1>(0h0)) when _T_2377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2374, UInt<1>(0h1), "") : assert_52 node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 1, 0) node _source_ok_T_163 = shr(io.in.d.bits.source, 2) node _source_ok_T_164 = eq(_source_ok_T_163, UInt<7>(0h70)) node _source_ok_T_165 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_166 = and(_source_ok_T_164, _source_ok_T_165) node _source_ok_T_167 = leq(source_ok_uncommonBits_22, UInt<2>(0h3)) node _source_ok_T_168 = and(_source_ok_T_166, _source_ok_T_167) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 1, 0) node _source_ok_T_169 = shr(io.in.d.bits.source, 2) node _source_ok_T_170 = eq(_source_ok_T_169, UInt<7>(0h71)) node _source_ok_T_171 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_172 = and(_source_ok_T_170, _source_ok_T_171) node _source_ok_T_173 = leq(source_ok_uncommonBits_23, UInt<2>(0h3)) node _source_ok_T_174 = and(_source_ok_T_172, _source_ok_T_173) node _source_ok_uncommonBits_T_24 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_24 = bits(_source_ok_uncommonBits_T_24, 1, 0) node _source_ok_T_175 = shr(io.in.d.bits.source, 2) node _source_ok_T_176 = eq(_source_ok_T_175, UInt<7>(0h72)) node _source_ok_T_177 = leq(UInt<1>(0h0), source_ok_uncommonBits_24) node _source_ok_T_178 = and(_source_ok_T_176, _source_ok_T_177) node _source_ok_T_179 = leq(source_ok_uncommonBits_24, UInt<2>(0h3)) node _source_ok_T_180 = and(_source_ok_T_178, _source_ok_T_179) node _source_ok_uncommonBits_T_25 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_25 = bits(_source_ok_uncommonBits_T_25, 1, 0) node _source_ok_T_181 = shr(io.in.d.bits.source, 2) node _source_ok_T_182 = eq(_source_ok_T_181, UInt<7>(0h73)) node _source_ok_T_183 = leq(UInt<1>(0h0), source_ok_uncommonBits_25) node _source_ok_T_184 = and(_source_ok_T_182, _source_ok_T_183) node _source_ok_T_185 = leq(source_ok_uncommonBits_25, UInt<2>(0h3)) node _source_ok_T_186 = and(_source_ok_T_184, _source_ok_T_185) node _source_ok_uncommonBits_T_26 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_26 = bits(_source_ok_uncommonBits_T_26, 1, 0) node _source_ok_T_187 = shr(io.in.d.bits.source, 2) node _source_ok_T_188 = eq(_source_ok_T_187, UInt<7>(0h7c)) node _source_ok_T_189 = leq(UInt<1>(0h0), source_ok_uncommonBits_26) node _source_ok_T_190 = and(_source_ok_T_188, _source_ok_T_189) node _source_ok_T_191 = leq(source_ok_uncommonBits_26, UInt<2>(0h3)) node _source_ok_T_192 = and(_source_ok_T_190, _source_ok_T_191) node _source_ok_uncommonBits_T_27 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_27 = bits(_source_ok_uncommonBits_T_27, 1, 0) node _source_ok_T_193 = shr(io.in.d.bits.source, 2) node _source_ok_T_194 = eq(_source_ok_T_193, UInt<7>(0h7b)) node _source_ok_T_195 = leq(UInt<1>(0h0), source_ok_uncommonBits_27) node _source_ok_T_196 = and(_source_ok_T_194, _source_ok_T_195) node _source_ok_T_197 = leq(source_ok_uncommonBits_27, UInt<2>(0h3)) node _source_ok_T_198 = and(_source_ok_T_196, _source_ok_T_197) node _source_ok_uncommonBits_T_28 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_28 = bits(_source_ok_uncommonBits_T_28, 4, 0) node _source_ok_T_199 = shr(io.in.d.bits.source, 5) node _source_ok_T_200 = eq(_source_ok_T_199, UInt<4>(0hd)) node _source_ok_T_201 = leq(UInt<1>(0h0), source_ok_uncommonBits_28) node _source_ok_T_202 = and(_source_ok_T_200, _source_ok_T_201) node _source_ok_T_203 = leq(source_ok_uncommonBits_28, UInt<5>(0h1f)) node _source_ok_T_204 = and(_source_ok_T_202, _source_ok_T_203) node _source_ok_uncommonBits_T_29 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_29 = bits(_source_ok_uncommonBits_T_29, 4, 0) node _source_ok_T_205 = shr(io.in.d.bits.source, 5) node _source_ok_T_206 = eq(_source_ok_T_205, UInt<4>(0hc)) node _source_ok_T_207 = leq(UInt<1>(0h0), source_ok_uncommonBits_29) node _source_ok_T_208 = and(_source_ok_T_206, _source_ok_T_207) node _source_ok_T_209 = leq(source_ok_uncommonBits_29, UInt<5>(0h1f)) node _source_ok_T_210 = and(_source_ok_T_208, _source_ok_T_209) node _source_ok_uncommonBits_T_30 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_30 = bits(_source_ok_uncommonBits_T_30, 4, 0) node _source_ok_T_211 = shr(io.in.d.bits.source, 5) node _source_ok_T_212 = eq(_source_ok_T_211, UInt<4>(0hb)) node _source_ok_T_213 = leq(UInt<1>(0h0), source_ok_uncommonBits_30) node _source_ok_T_214 = and(_source_ok_T_212, _source_ok_T_213) node _source_ok_T_215 = leq(source_ok_uncommonBits_30, UInt<5>(0h1f)) node _source_ok_T_216 = and(_source_ok_T_214, _source_ok_T_215) node _source_ok_uncommonBits_T_31 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_31 = bits(_source_ok_uncommonBits_T_31, 4, 0) node _source_ok_T_217 = shr(io.in.d.bits.source, 5) node _source_ok_T_218 = eq(_source_ok_T_217, UInt<4>(0ha)) node _source_ok_T_219 = leq(UInt<1>(0h0), source_ok_uncommonBits_31) node _source_ok_T_220 = and(_source_ok_T_218, _source_ok_T_219) node _source_ok_T_221 = leq(source_ok_uncommonBits_31, UInt<5>(0h1f)) node _source_ok_T_222 = and(_source_ok_T_220, _source_ok_T_221) node _source_ok_uncommonBits_T_32 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_32 = bits(_source_ok_uncommonBits_T_32, 4, 0) node _source_ok_T_223 = shr(io.in.d.bits.source, 5) node _source_ok_T_224 = eq(_source_ok_T_223, UInt<4>(0h9)) node _source_ok_T_225 = leq(UInt<1>(0h0), source_ok_uncommonBits_32) node _source_ok_T_226 = and(_source_ok_T_224, _source_ok_T_225) node _source_ok_T_227 = leq(source_ok_uncommonBits_32, UInt<5>(0h1f)) node _source_ok_T_228 = and(_source_ok_T_226, _source_ok_T_227) node _source_ok_uncommonBits_T_33 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_33 = bits(_source_ok_uncommonBits_T_33, 4, 0) node _source_ok_T_229 = shr(io.in.d.bits.source, 5) node _source_ok_T_230 = eq(_source_ok_T_229, UInt<4>(0h8)) node _source_ok_T_231 = leq(UInt<1>(0h0), source_ok_uncommonBits_33) node _source_ok_T_232 = and(_source_ok_T_230, _source_ok_T_231) node _source_ok_T_233 = leq(source_ok_uncommonBits_33, UInt<5>(0h1f)) node _source_ok_T_234 = and(_source_ok_T_232, _source_ok_T_233) node _source_ok_uncommonBits_T_34 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_34 = bits(_source_ok_uncommonBits_T_34, 1, 0) node _source_ok_T_235 = shr(io.in.d.bits.source, 2) node _source_ok_T_236 = eq(_source_ok_T_235, UInt<7>(0h7a)) node _source_ok_T_237 = leq(UInt<1>(0h0), source_ok_uncommonBits_34) node _source_ok_T_238 = and(_source_ok_T_236, _source_ok_T_237) node _source_ok_T_239 = leq(source_ok_uncommonBits_34, UInt<2>(0h3)) node _source_ok_T_240 = and(_source_ok_T_238, _source_ok_T_239) node _source_ok_uncommonBits_T_35 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_35 = bits(_source_ok_uncommonBits_T_35, 1, 0) node _source_ok_T_241 = shr(io.in.d.bits.source, 2) node _source_ok_T_242 = eq(_source_ok_T_241, UInt<7>(0h79)) node _source_ok_T_243 = leq(UInt<1>(0h0), source_ok_uncommonBits_35) node _source_ok_T_244 = and(_source_ok_T_242, _source_ok_T_243) node _source_ok_T_245 = leq(source_ok_uncommonBits_35, UInt<2>(0h3)) node _source_ok_T_246 = and(_source_ok_T_244, _source_ok_T_245) node _source_ok_uncommonBits_T_36 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_36 = bits(_source_ok_uncommonBits_T_36, 4, 0) node _source_ok_T_247 = shr(io.in.d.bits.source, 5) node _source_ok_T_248 = eq(_source_ok_T_247, UInt<3>(0h7)) node _source_ok_T_249 = leq(UInt<1>(0h0), source_ok_uncommonBits_36) node _source_ok_T_250 = and(_source_ok_T_248, _source_ok_T_249) node _source_ok_T_251 = leq(source_ok_uncommonBits_36, UInt<5>(0h1f)) node _source_ok_T_252 = and(_source_ok_T_250, _source_ok_T_251) node _source_ok_uncommonBits_T_37 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_37 = bits(_source_ok_uncommonBits_T_37, 4, 0) node _source_ok_T_253 = shr(io.in.d.bits.source, 5) node _source_ok_T_254 = eq(_source_ok_T_253, UInt<3>(0h6)) node _source_ok_T_255 = leq(UInt<1>(0h0), source_ok_uncommonBits_37) node _source_ok_T_256 = and(_source_ok_T_254, _source_ok_T_255) node _source_ok_T_257 = leq(source_ok_uncommonBits_37, UInt<5>(0h1f)) node _source_ok_T_258 = and(_source_ok_T_256, _source_ok_T_257) node _source_ok_uncommonBits_T_38 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_38 = bits(_source_ok_uncommonBits_T_38, 4, 0) node _source_ok_T_259 = shr(io.in.d.bits.source, 5) node _source_ok_T_260 = eq(_source_ok_T_259, UInt<3>(0h5)) node _source_ok_T_261 = leq(UInt<1>(0h0), source_ok_uncommonBits_38) node _source_ok_T_262 = and(_source_ok_T_260, _source_ok_T_261) node _source_ok_T_263 = leq(source_ok_uncommonBits_38, UInt<5>(0h1f)) node _source_ok_T_264 = and(_source_ok_T_262, _source_ok_T_263) node _source_ok_uncommonBits_T_39 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_39 = bits(_source_ok_uncommonBits_T_39, 4, 0) node _source_ok_T_265 = shr(io.in.d.bits.source, 5) node _source_ok_T_266 = eq(_source_ok_T_265, UInt<3>(0h4)) node _source_ok_T_267 = leq(UInt<1>(0h0), source_ok_uncommonBits_39) node _source_ok_T_268 = and(_source_ok_T_266, _source_ok_T_267) node _source_ok_T_269 = leq(source_ok_uncommonBits_39, UInt<5>(0h1f)) node _source_ok_T_270 = and(_source_ok_T_268, _source_ok_T_269) node _source_ok_uncommonBits_T_40 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_40 = bits(_source_ok_uncommonBits_T_40, 4, 0) node _source_ok_T_271 = shr(io.in.d.bits.source, 5) node _source_ok_T_272 = eq(_source_ok_T_271, UInt<2>(0h3)) node _source_ok_T_273 = leq(UInt<1>(0h0), source_ok_uncommonBits_40) node _source_ok_T_274 = and(_source_ok_T_272, _source_ok_T_273) node _source_ok_T_275 = leq(source_ok_uncommonBits_40, UInt<5>(0h1f)) node _source_ok_T_276 = and(_source_ok_T_274, _source_ok_T_275) node _source_ok_uncommonBits_T_41 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_41 = bits(_source_ok_uncommonBits_T_41, 4, 0) node _source_ok_T_277 = shr(io.in.d.bits.source, 5) node _source_ok_T_278 = eq(_source_ok_T_277, UInt<2>(0h2)) node _source_ok_T_279 = leq(UInt<1>(0h0), source_ok_uncommonBits_41) node _source_ok_T_280 = and(_source_ok_T_278, _source_ok_T_279) node _source_ok_T_281 = leq(source_ok_uncommonBits_41, UInt<5>(0h1f)) node _source_ok_T_282 = and(_source_ok_T_280, _source_ok_T_281) node _source_ok_uncommonBits_T_42 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_42 = bits(_source_ok_uncommonBits_T_42, 4, 0) node _source_ok_T_283 = shr(io.in.d.bits.source, 5) node _source_ok_T_284 = eq(_source_ok_T_283, UInt<1>(0h1)) node _source_ok_T_285 = leq(UInt<1>(0h0), source_ok_uncommonBits_42) node _source_ok_T_286 = and(_source_ok_T_284, _source_ok_T_285) node _source_ok_T_287 = leq(source_ok_uncommonBits_42, UInt<5>(0h1f)) node _source_ok_T_288 = and(_source_ok_T_286, _source_ok_T_287) node _source_ok_uncommonBits_T_43 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_43 = bits(_source_ok_uncommonBits_T_43, 4, 0) node _source_ok_T_289 = shr(io.in.d.bits.source, 5) node _source_ok_T_290 = eq(_source_ok_T_289, UInt<1>(0h0)) node _source_ok_T_291 = leq(UInt<1>(0h0), source_ok_uncommonBits_43) node _source_ok_T_292 = and(_source_ok_T_290, _source_ok_T_291) node _source_ok_T_293 = leq(source_ok_uncommonBits_43, UInt<5>(0h1f)) node _source_ok_T_294 = and(_source_ok_T_292, _source_ok_T_293) node _source_ok_T_295 = eq(io.in.d.bits.source, UInt<9>(0h1e0)) node _source_ok_T_296 = eq(io.in.d.bits.source, UInt<9>(0h1e1)) node _source_ok_T_297 = eq(io.in.d.bits.source, UInt<9>(0h1e2)) node _source_ok_T_298 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[27] connect _source_ok_WIRE_1[0], _source_ok_T_162 connect _source_ok_WIRE_1[1], _source_ok_T_168 connect _source_ok_WIRE_1[2], _source_ok_T_174 connect _source_ok_WIRE_1[3], _source_ok_T_180 connect _source_ok_WIRE_1[4], _source_ok_T_186 connect _source_ok_WIRE_1[5], _source_ok_T_192 connect _source_ok_WIRE_1[6], _source_ok_T_198 connect _source_ok_WIRE_1[7], _source_ok_T_204 connect _source_ok_WIRE_1[8], _source_ok_T_210 connect _source_ok_WIRE_1[9], _source_ok_T_216 connect _source_ok_WIRE_1[10], _source_ok_T_222 connect _source_ok_WIRE_1[11], _source_ok_T_228 connect _source_ok_WIRE_1[12], _source_ok_T_234 connect _source_ok_WIRE_1[13], _source_ok_T_240 connect _source_ok_WIRE_1[14], _source_ok_T_246 connect _source_ok_WIRE_1[15], _source_ok_T_252 connect _source_ok_WIRE_1[16], _source_ok_T_258 connect _source_ok_WIRE_1[17], _source_ok_T_264 connect _source_ok_WIRE_1[18], _source_ok_T_270 connect _source_ok_WIRE_1[19], _source_ok_T_276 connect _source_ok_WIRE_1[20], _source_ok_T_282 connect _source_ok_WIRE_1[21], _source_ok_T_288 connect _source_ok_WIRE_1[22], _source_ok_T_294 connect _source_ok_WIRE_1[23], _source_ok_T_295 connect _source_ok_WIRE_1[24], _source_ok_T_296 connect _source_ok_WIRE_1[25], _source_ok_T_297 connect _source_ok_WIRE_1[26], _source_ok_T_298 node _source_ok_T_299 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_300 = or(_source_ok_T_299, _source_ok_WIRE_1[2]) node _source_ok_T_301 = or(_source_ok_T_300, _source_ok_WIRE_1[3]) node _source_ok_T_302 = or(_source_ok_T_301, _source_ok_WIRE_1[4]) node _source_ok_T_303 = or(_source_ok_T_302, _source_ok_WIRE_1[5]) node _source_ok_T_304 = or(_source_ok_T_303, _source_ok_WIRE_1[6]) node _source_ok_T_305 = or(_source_ok_T_304, _source_ok_WIRE_1[7]) node _source_ok_T_306 = or(_source_ok_T_305, _source_ok_WIRE_1[8]) node _source_ok_T_307 = or(_source_ok_T_306, _source_ok_WIRE_1[9]) node _source_ok_T_308 = or(_source_ok_T_307, _source_ok_WIRE_1[10]) node _source_ok_T_309 = or(_source_ok_T_308, _source_ok_WIRE_1[11]) node _source_ok_T_310 = or(_source_ok_T_309, _source_ok_WIRE_1[12]) node _source_ok_T_311 = or(_source_ok_T_310, _source_ok_WIRE_1[13]) node _source_ok_T_312 = or(_source_ok_T_311, _source_ok_WIRE_1[14]) node _source_ok_T_313 = or(_source_ok_T_312, _source_ok_WIRE_1[15]) node _source_ok_T_314 = or(_source_ok_T_313, _source_ok_WIRE_1[16]) node _source_ok_T_315 = or(_source_ok_T_314, _source_ok_WIRE_1[17]) node _source_ok_T_316 = or(_source_ok_T_315, _source_ok_WIRE_1[18]) node _source_ok_T_317 = or(_source_ok_T_316, _source_ok_WIRE_1[19]) node _source_ok_T_318 = or(_source_ok_T_317, _source_ok_WIRE_1[20]) node _source_ok_T_319 = or(_source_ok_T_318, _source_ok_WIRE_1[21]) node _source_ok_T_320 = or(_source_ok_T_319, _source_ok_WIRE_1[22]) node _source_ok_T_321 = or(_source_ok_T_320, _source_ok_WIRE_1[23]) node _source_ok_T_322 = or(_source_ok_T_321, _source_ok_WIRE_1[24]) node _source_ok_T_323 = or(_source_ok_T_322, _source_ok_WIRE_1[25]) node source_ok_1 = or(_source_ok_T_323, _source_ok_WIRE_1[26]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2378 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2378 : node _T_2379 = asUInt(reset) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) when _T_2380 : node _T_2381 = eq(source_ok_1, UInt<1>(0h0)) when _T_2381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2382 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2383 = asUInt(reset) node _T_2384 = eq(_T_2383, UInt<1>(0h0)) when _T_2384 : node _T_2385 = eq(_T_2382, UInt<1>(0h0)) when _T_2385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2382, UInt<1>(0h1), "") : assert_54 node _T_2386 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2387 = asUInt(reset) node _T_2388 = eq(_T_2387, UInt<1>(0h0)) when _T_2388 : node _T_2389 = eq(_T_2386, UInt<1>(0h0)) when _T_2389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2386, UInt<1>(0h1), "") : assert_55 node _T_2390 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2391 = asUInt(reset) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) when _T_2392 : node _T_2393 = eq(_T_2390, UInt<1>(0h0)) when _T_2393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2390, UInt<1>(0h1), "") : assert_56 node _T_2394 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2395 = asUInt(reset) node _T_2396 = eq(_T_2395, UInt<1>(0h0)) when _T_2396 : node _T_2397 = eq(_T_2394, UInt<1>(0h0)) when _T_2397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2394, UInt<1>(0h1), "") : assert_57 node _T_2398 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2398 : node _T_2399 = asUInt(reset) node _T_2400 = eq(_T_2399, UInt<1>(0h0)) when _T_2400 : node _T_2401 = eq(source_ok_1, UInt<1>(0h0)) when _T_2401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2402 = asUInt(reset) node _T_2403 = eq(_T_2402, UInt<1>(0h0)) when _T_2403 : node _T_2404 = eq(sink_ok, UInt<1>(0h0)) when _T_2404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_60 node _T_2409 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_61 node _T_2413 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2414 = asUInt(reset) node _T_2415 = eq(_T_2414, UInt<1>(0h0)) when _T_2415 : node _T_2416 = eq(_T_2413, UInt<1>(0h0)) when _T_2416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2413, UInt<1>(0h1), "") : assert_62 node _T_2417 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(_T_2417, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2417, UInt<1>(0h1), "") : assert_63 node _T_2421 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2422 = or(UInt<1>(0h0), _T_2421) node _T_2423 = asUInt(reset) node _T_2424 = eq(_T_2423, UInt<1>(0h0)) when _T_2424 : node _T_2425 = eq(_T_2422, UInt<1>(0h0)) when _T_2425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2422, UInt<1>(0h1), "") : assert_64 node _T_2426 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2426 : node _T_2427 = asUInt(reset) node _T_2428 = eq(_T_2427, UInt<1>(0h0)) when _T_2428 : node _T_2429 = eq(source_ok_1, UInt<1>(0h0)) when _T_2429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(sink_ok, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2433 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_67 node _T_2437 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2438 = asUInt(reset) node _T_2439 = eq(_T_2438, UInt<1>(0h0)) when _T_2439 : node _T_2440 = eq(_T_2437, UInt<1>(0h0)) when _T_2440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2437, UInt<1>(0h1), "") : assert_68 node _T_2441 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_69 node _T_2445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2446 = or(_T_2445, io.in.d.bits.corrupt) node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(_T_2446, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2446, UInt<1>(0h1), "") : assert_70 node _T_2450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2451 = or(UInt<1>(0h0), _T_2450) node _T_2452 = asUInt(reset) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) when _T_2453 : node _T_2454 = eq(_T_2451, UInt<1>(0h0)) when _T_2454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2451, UInt<1>(0h1), "") : assert_71 node _T_2455 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2455 : node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(source_ok_1, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_73 node _T_2463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_74 node _T_2467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2468 = or(UInt<1>(0h0), _T_2467) node _T_2469 = asUInt(reset) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) when _T_2470 : node _T_2471 = eq(_T_2468, UInt<1>(0h0)) when _T_2471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2468, UInt<1>(0h1), "") : assert_75 node _T_2472 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2472 : node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(source_ok_1, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2477 = asUInt(reset) node _T_2478 = eq(_T_2477, UInt<1>(0h0)) when _T_2478 : node _T_2479 = eq(_T_2476, UInt<1>(0h0)) when _T_2479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2476, UInt<1>(0h1), "") : assert_77 node _T_2480 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2481 = or(_T_2480, io.in.d.bits.corrupt) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_78 node _T_2485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2486 = or(UInt<1>(0h0), _T_2485) node _T_2487 = asUInt(reset) node _T_2488 = eq(_T_2487, UInt<1>(0h0)) when _T_2488 : node _T_2489 = eq(_T_2486, UInt<1>(0h0)) when _T_2489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2486, UInt<1>(0h1), "") : assert_79 node _T_2490 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2490 : node _T_2491 = asUInt(reset) node _T_2492 = eq(_T_2491, UInt<1>(0h0)) when _T_2492 : node _T_2493 = eq(source_ok_1, UInt<1>(0h0)) when _T_2493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2494 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2495 = asUInt(reset) node _T_2496 = eq(_T_2495, UInt<1>(0h0)) when _T_2496 : node _T_2497 = eq(_T_2494, UInt<1>(0h0)) when _T_2497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2494, UInt<1>(0h1), "") : assert_81 node _T_2498 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2499 = asUInt(reset) node _T_2500 = eq(_T_2499, UInt<1>(0h0)) when _T_2500 : node _T_2501 = eq(_T_2498, UInt<1>(0h0)) when _T_2501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2498, UInt<1>(0h1), "") : assert_82 node _T_2502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2503 = or(UInt<1>(0h0), _T_2502) node _T_2504 = asUInt(reset) node _T_2505 = eq(_T_2504, UInt<1>(0h0)) when _T_2505 : node _T_2506 = eq(_T_2503, UInt<1>(0h0)) when _T_2506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2503, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2507 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2508 = asUInt(reset) node _T_2509 = eq(_T_2508, UInt<1>(0h0)) when _T_2509 : node _T_2510 = eq(_T_2507, UInt<1>(0h0)) when _T_2510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2507, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2511 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2512 = asUInt(reset) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) when _T_2513 : node _T_2514 = eq(_T_2511, UInt<1>(0h0)) when _T_2514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2511, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2515 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2519 = eq(a_first, UInt<1>(0h0)) node _T_2520 = and(io.in.a.valid, _T_2519) when _T_2520 : node _T_2521 = eq(io.in.a.bits.opcode, opcode) node _T_2522 = asUInt(reset) node _T_2523 = eq(_T_2522, UInt<1>(0h0)) when _T_2523 : node _T_2524 = eq(_T_2521, UInt<1>(0h0)) when _T_2524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2521, UInt<1>(0h1), "") : assert_87 node _T_2525 = eq(io.in.a.bits.param, param) node _T_2526 = asUInt(reset) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) when _T_2527 : node _T_2528 = eq(_T_2525, UInt<1>(0h0)) when _T_2528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2525, UInt<1>(0h1), "") : assert_88 node _T_2529 = eq(io.in.a.bits.size, size) node _T_2530 = asUInt(reset) node _T_2531 = eq(_T_2530, UInt<1>(0h0)) when _T_2531 : node _T_2532 = eq(_T_2529, UInt<1>(0h0)) when _T_2532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2529, UInt<1>(0h1), "") : assert_89 node _T_2533 = eq(io.in.a.bits.source, source) node _T_2534 = asUInt(reset) node _T_2535 = eq(_T_2534, UInt<1>(0h0)) when _T_2535 : node _T_2536 = eq(_T_2533, UInt<1>(0h0)) when _T_2536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2533, UInt<1>(0h1), "") : assert_90 node _T_2537 = eq(io.in.a.bits.address, address) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_91 node _T_2541 = and(io.in.a.ready, io.in.a.valid) node _T_2542 = and(_T_2541, a_first) when _T_2542 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2543 = eq(d_first, UInt<1>(0h0)) node _T_2544 = and(io.in.d.valid, _T_2543) when _T_2544 : node _T_2545 = eq(io.in.d.bits.opcode, opcode_1) node _T_2546 = asUInt(reset) node _T_2547 = eq(_T_2546, UInt<1>(0h0)) when _T_2547 : node _T_2548 = eq(_T_2545, UInt<1>(0h0)) when _T_2548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2545, UInt<1>(0h1), "") : assert_92 node _T_2549 = eq(io.in.d.bits.param, param_1) node _T_2550 = asUInt(reset) node _T_2551 = eq(_T_2550, UInt<1>(0h0)) when _T_2551 : node _T_2552 = eq(_T_2549, UInt<1>(0h0)) when _T_2552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2549, UInt<1>(0h1), "") : assert_93 node _T_2553 = eq(io.in.d.bits.size, size_1) node _T_2554 = asUInt(reset) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) when _T_2555 : node _T_2556 = eq(_T_2553, UInt<1>(0h0)) when _T_2556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2553, UInt<1>(0h1), "") : assert_94 node _T_2557 = eq(io.in.d.bits.source, source_1) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_95 node _T_2561 = eq(io.in.d.bits.sink, sink) node _T_2562 = asUInt(reset) node _T_2563 = eq(_T_2562, UInt<1>(0h0)) when _T_2563 : node _T_2564 = eq(_T_2561, UInt<1>(0h0)) when _T_2564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2561, UInt<1>(0h1), "") : assert_96 node _T_2565 = eq(io.in.d.bits.denied, denied) node _T_2566 = asUInt(reset) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) when _T_2567 : node _T_2568 = eq(_T_2565, UInt<1>(0h0)) when _T_2568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2565, UInt<1>(0h1), "") : assert_97 node _T_2569 = and(io.in.d.ready, io.in.d.valid) node _T_2570 = and(_T_2569, d_first) when _T_2570 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<2052>, clock, reset, UInt<2052>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<2052> connect a_sizes_set, UInt<2052>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2571 = and(io.in.a.valid, a_first_1) node _T_2572 = and(_T_2571, UInt<1>(0h1)) when _T_2572 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2573 = and(io.in.a.ready, io.in.a.valid) node _T_2574 = and(_T_2573, a_first_1) node _T_2575 = and(_T_2574, UInt<1>(0h1)) when _T_2575 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2576 = dshr(inflight, io.in.a.bits.source) node _T_2577 = bits(_T_2576, 0, 0) node _T_2578 = eq(_T_2577, UInt<1>(0h0)) node _T_2579 = asUInt(reset) node _T_2580 = eq(_T_2579, UInt<1>(0h0)) when _T_2580 : node _T_2581 = eq(_T_2578, UInt<1>(0h0)) when _T_2581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2578, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<2052> connect d_sizes_clr, UInt<2052>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2582 = and(io.in.d.valid, d_first_1) node _T_2583 = and(_T_2582, UInt<1>(0h1)) node _T_2584 = eq(d_release_ack, UInt<1>(0h0)) node _T_2585 = and(_T_2583, _T_2584) when _T_2585 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2586 = and(io.in.d.ready, io.in.d.valid) node _T_2587 = and(_T_2586, d_first_1) node _T_2588 = and(_T_2587, UInt<1>(0h1)) node _T_2589 = eq(d_release_ack, UInt<1>(0h0)) node _T_2590 = and(_T_2588, _T_2589) when _T_2590 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2591 = and(io.in.d.valid, d_first_1) node _T_2592 = and(_T_2591, UInt<1>(0h1)) node _T_2593 = eq(d_release_ack, UInt<1>(0h0)) node _T_2594 = and(_T_2592, _T_2593) when _T_2594 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2595 = dshr(inflight, io.in.d.bits.source) node _T_2596 = bits(_T_2595, 0, 0) node _T_2597 = or(_T_2596, same_cycle_resp) node _T_2598 = asUInt(reset) node _T_2599 = eq(_T_2598, UInt<1>(0h0)) when _T_2599 : node _T_2600 = eq(_T_2597, UInt<1>(0h0)) when _T_2600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2597, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2601 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2602 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2603 = or(_T_2601, _T_2602) node _T_2604 = asUInt(reset) node _T_2605 = eq(_T_2604, UInt<1>(0h0)) when _T_2605 : node _T_2606 = eq(_T_2603, UInt<1>(0h0)) when _T_2606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2603, UInt<1>(0h1), "") : assert_100 node _T_2607 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2608 = asUInt(reset) node _T_2609 = eq(_T_2608, UInt<1>(0h0)) when _T_2609 : node _T_2610 = eq(_T_2607, UInt<1>(0h0)) when _T_2610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2607, UInt<1>(0h1), "") : assert_101 else : node _T_2611 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2612 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2613 = or(_T_2611, _T_2612) node _T_2614 = asUInt(reset) node _T_2615 = eq(_T_2614, UInt<1>(0h0)) when _T_2615 : node _T_2616 = eq(_T_2613, UInt<1>(0h0)) when _T_2616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2613, UInt<1>(0h1), "") : assert_102 node _T_2617 = eq(io.in.d.bits.size, a_size_lookup) node _T_2618 = asUInt(reset) node _T_2619 = eq(_T_2618, UInt<1>(0h0)) when _T_2619 : node _T_2620 = eq(_T_2617, UInt<1>(0h0)) when _T_2620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2617, UInt<1>(0h1), "") : assert_103 node _T_2621 = and(io.in.d.valid, d_first_1) node _T_2622 = and(_T_2621, a_first_1) node _T_2623 = and(_T_2622, io.in.a.valid) node _T_2624 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2625 = and(_T_2623, _T_2624) node _T_2626 = eq(d_release_ack, UInt<1>(0h0)) node _T_2627 = and(_T_2625, _T_2626) when _T_2627 : node _T_2628 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2629 = or(_T_2628, io.in.a.ready) node _T_2630 = asUInt(reset) node _T_2631 = eq(_T_2630, UInt<1>(0h0)) when _T_2631 : node _T_2632 = eq(_T_2629, UInt<1>(0h0)) when _T_2632 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2629, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_225 node _T_2633 = orr(inflight) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) node _T_2635 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2636 = or(_T_2634, _T_2635) node _T_2637 = lt(watchdog, plusarg_reader.out) node _T_2638 = or(_T_2636, _T_2637) node _T_2639 = asUInt(reset) node _T_2640 = eq(_T_2639, UInt<1>(0h0)) when _T_2640 : node _T_2641 = eq(_T_2638, UInt<1>(0h0)) when _T_2641 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2638, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2642 = and(io.in.a.ready, io.in.a.valid) node _T_2643 = and(io.in.d.ready, io.in.d.valid) node _T_2644 = or(_T_2642, _T_2643) when _T_2644 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<2052> connect c_sizes_set, UInt<2052>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2645 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2646 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2647 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2648 = and(_T_2646, _T_2647) node _T_2649 = and(_T_2645, _T_2648) when _T_2649 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2650 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2651 = and(_T_2650, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2652 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2653 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2654 = and(_T_2652, _T_2653) node _T_2655 = and(_T_2651, _T_2654) when _T_2655 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2656 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2657 = bits(_T_2656, 0, 0) node _T_2658 = eq(_T_2657, UInt<1>(0h0)) node _T_2659 = asUInt(reset) node _T_2660 = eq(_T_2659, UInt<1>(0h0)) when _T_2660 : node _T_2661 = eq(_T_2658, UInt<1>(0h0)) when _T_2661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2658, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<2052> connect d_sizes_clr_1, UInt<2052>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2662 = and(io.in.d.valid, d_first_2) node _T_2663 = and(_T_2662, UInt<1>(0h1)) node _T_2664 = and(_T_2663, d_release_ack_1) when _T_2664 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2665 = and(io.in.d.ready, io.in.d.valid) node _T_2666 = and(_T_2665, d_first_2) node _T_2667 = and(_T_2666, UInt<1>(0h1)) node _T_2668 = and(_T_2667, d_release_ack_1) when _T_2668 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2669 = and(io.in.d.valid, d_first_2) node _T_2670 = and(_T_2669, UInt<1>(0h1)) node _T_2671 = and(_T_2670, d_release_ack_1) when _T_2671 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2672 = dshr(inflight_1, io.in.d.bits.source) node _T_2673 = bits(_T_2672, 0, 0) node _T_2674 = or(_T_2673, same_cycle_resp_1) node _T_2675 = asUInt(reset) node _T_2676 = eq(_T_2675, UInt<1>(0h0)) when _T_2676 : node _T_2677 = eq(_T_2674, UInt<1>(0h0)) when _T_2677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2674, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2678 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2679 = asUInt(reset) node _T_2680 = eq(_T_2679, UInt<1>(0h0)) when _T_2680 : node _T_2681 = eq(_T_2678, UInt<1>(0h0)) when _T_2681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2678, UInt<1>(0h1), "") : assert_108 else : node _T_2682 = eq(io.in.d.bits.size, c_size_lookup) node _T_2683 = asUInt(reset) node _T_2684 = eq(_T_2683, UInt<1>(0h0)) when _T_2684 : node _T_2685 = eq(_T_2682, UInt<1>(0h0)) when _T_2685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2682, UInt<1>(0h1), "") : assert_109 node _T_2686 = and(io.in.d.valid, d_first_2) node _T_2687 = and(_T_2686, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2688 = and(_T_2687, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2689 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2690 = and(_T_2688, _T_2689) node _T_2691 = and(_T_2690, d_release_ack_1) node _T_2692 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2693 = and(_T_2691, _T_2692) when _T_2693 : node _T_2694 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2695 = or(_T_2694, _WIRE_27.ready) node _T_2696 = asUInt(reset) node _T_2697 = eq(_T_2696, UInt<1>(0h0)) when _T_2697 : node _T_2698 = eq(_T_2695, UInt<1>(0h0)) when _T_2698 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2695, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_226 node _T_2699 = orr(inflight_1) node _T_2700 = eq(_T_2699, UInt<1>(0h0)) node _T_2701 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2702 = or(_T_2700, _T_2701) node _T_2703 = lt(watchdog_1, plusarg_reader_1.out) node _T_2704 = or(_T_2702, _T_2703) node _T_2705 = asUInt(reset) node _T_2706 = eq(_T_2705, UInt<1>(0h0)) when _T_2706 : node _T_2707 = eq(_T_2704, UInt<1>(0h0)) when _T_2707 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2704, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2708 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2709 = and(io.in.d.ready, io.in.d.valid) node _T_2710 = or(_T_2708, _T_2709) when _T_2710 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_111( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_165 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_171 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_177 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_183 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_189 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_195 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_201 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_207 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_213 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_219 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_225 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_231 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_237 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_243 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_249 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_255 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_261 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_267 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_273 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_279 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_285 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_291 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_293 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_wo_ready_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_wo_ready_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_4_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_5_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [8194:0] _c_opcodes_set_T_1 = 8195'h0; // @[Monitor.scala:767:54] wire [8194:0] _c_sizes_set_T_1 = 8195'h0; // @[Monitor.scala:768:52] wire [12:0] _c_opcodes_set_T = 13'h0; // @[Monitor.scala:767:79] wire [12:0] _c_sizes_set_T = 13'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [1023:0] _c_set_wo_ready_T = 1024'h1; // @[OneHot.scala:58:35] wire [1023:0] _c_set_T = 1024'h1; // @[OneHot.scala:58:35] wire [2051:0] c_opcodes_set = 2052'h0; // @[Monitor.scala:740:34] wire [2051:0] c_sizes_set = 2052'h0; // @[Monitor.scala:741:34] wire [512:0] c_set = 513'h0; // @[Monitor.scala:738:34] wire [512:0] c_set_wo_ready = 513'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [9:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_1 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_7 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_13 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_19 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_25 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_31 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_73 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_79 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_67 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_109 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_115 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_121 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_127 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_74 = _source_ok_T_73 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_110 = _source_ok_T_109 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_116 = _source_ok_T_115 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_122 = _source_ok_T_121 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_128 = _source_ok_T_127 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31] wire _source_ok_T_133 = io_in_a_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31] wire _source_ok_T_134 = io_in_a_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31] wire _source_ok_T_135 = io_in_a_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_135; // @[Parameters.scala:1138:31] wire _source_ok_T_136 = io_in_a_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_136; // @[Parameters.scala:1138:31] wire _source_ok_T_137 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 \| _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 \| _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_156 = _source_ok_T_155 \| _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_157 = _source_ok_T_156 \| _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_158 = _source_ok_T_157 \| _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_159 = _source_ok_T_158 \| _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_160 = _source_ok_T_159 \| _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_161 = _source_ok_T_160 \| _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_161 \| _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_162 = io_in_d_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_162; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_163 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_169 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_175 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_181 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_187 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_193 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_235 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_241 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_164 = _source_ok_T_163 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_166 = _source_ok_T_164; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_168; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_170 = _source_ok_T_169 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_172 = _source_ok_T_170; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_174; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_176 = _source_ok_T_175 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_178 = _source_ok_T_176; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_180; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_182 = _source_ok_T_181 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_184 = _source_ok_T_182; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_186; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_188 = _source_ok_T_187 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_190 = _source_ok_T_188; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_192; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_194 = _source_ok_T_193 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_196 = _source_ok_T_194; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_198; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_199 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_205 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_211 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_217 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_223 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_229 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_247 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_253 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_259 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_265 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_271 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_277 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_283 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_289 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_200 = _source_ok_T_199 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_202 = _source_ok_T_200; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_204; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_206 = _source_ok_T_205 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_208 = _source_ok_T_206; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_210; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_212 = _source_ok_T_211 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_214 = _source_ok_T_212; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_9 = _source_ok_T_216; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_218 = _source_ok_T_217 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_220 = _source_ok_T_218; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_10 = _source_ok_T_222; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_224 = _source_ok_T_223 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_226 = _source_ok_T_224; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_11 = _source_ok_T_228; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_230 = _source_ok_T_229 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_232 = _source_ok_T_230; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_12 = _source_ok_T_234; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_236 = _source_ok_T_235 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_238 = _source_ok_T_236; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_13 = _source_ok_T_240; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_242 = _source_ok_T_241 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_244 = _source_ok_T_242; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_14 = _source_ok_T_246; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_248 = _source_ok_T_247 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_250 = _source_ok_T_248; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_15 = _source_ok_T_252; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_254 = _source_ok_T_253 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_256 = _source_ok_T_254; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_16 = _source_ok_T_258; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_260 = _source_ok_T_259 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_262 = _source_ok_T_260; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_17 = _source_ok_T_264; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_266 = _source_ok_T_265 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_268 = _source_ok_T_266; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_18 = _source_ok_T_270; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_272 = _source_ok_T_271 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_274 = _source_ok_T_272; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_19 = _source_ok_T_276; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_278 = _source_ok_T_277 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_280 = _source_ok_T_278; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_20 = _source_ok_T_282; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_284 = _source_ok_T_283 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_286 = _source_ok_T_284; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_21 = _source_ok_T_288; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_290 = _source_ok_T_289 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_292 = _source_ok_T_290; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_294 = _source_ok_T_292; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_22 = _source_ok_T_294; // @[Parameters.scala:1138:31] wire _source_ok_T_295 = io_in_d_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_295; // @[Parameters.scala:1138:31] wire _source_ok_T_296 = io_in_d_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_296; // @[Parameters.scala:1138:31] wire _source_ok_T_297 = io_in_d_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_297; // @[Parameters.scala:1138:31] wire _source_ok_T_298 = io_in_d_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_298; // @[Parameters.scala:1138:31] wire _source_ok_T_299 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_300 = _source_ok_T_299 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_301 = _source_ok_T_300 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_302 = _source_ok_T_301 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_303 = _source_ok_T_302 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_304 = _source_ok_T_303 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_305 = _source_ok_T_304 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_306 = _source_ok_T_305 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_307 = _source_ok_T_306 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_308 = _source_ok_T_307 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_309 = _source_ok_T_308 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_310 = _source_ok_T_309 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_311 = _source_ok_T_310 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_312 = _source_ok_T_311 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_313 = _source_ok_T_312 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_314 = _source_ok_T_313 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_315 = _source_ok_T_314 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_316 = _source_ok_T_315 \| _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_317 = _source_ok_T_316 \| _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_318 = _source_ok_T_317 \| _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_319 = _source_ok_T_318 \| _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_320 = _source_ok_T_319 \| _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_321 = _source_ok_T_320 \| _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_322 = _source_ok_T_321 \| _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_323 = _source_ok_T_322 \| _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_323 \| _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _T_2642 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2642; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2642; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_2710 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2710; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2710; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2710; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [512:0] a_set; // @[Monitor.scala:626:34] wire [512:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [2051:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [2051:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [12:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [12:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [12:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [12:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [12:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [12:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [12:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [12:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [12:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [2051:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [2051:0] _a_opcode_lookup_T_6 = {2048'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [2051:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [2051:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [2051:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [2051:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2051:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1023:0] _GEN_2 = 1024'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1023:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2575 = _T_2642 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2575 ? _a_set_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2575 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2575 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [12:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [12:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [12:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [8194:0] _a_opcodes_set_T_1 = {8191'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2575 ? _a_opcodes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8194:0] _a_sizes_set_T_1 = {8191'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2575 ? _a_sizes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [512:0] d_clr; // @[Monitor.scala:664:34] wire [512:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [2051:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [2051:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_2621 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1023:0] _GEN_5 = 1024'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2621 & ~d_release_ack ? _d_clr_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2590 = _T_2710 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2590 ? _d_clr_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_5 = 8207'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2590 ? _d_opcodes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [8206:0] _d_sizes_clr_T_5 = 8207'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2590 ? _d_sizes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [512:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [512:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [512:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [2051:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [2051:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [2051:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [2051:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [2051:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [2051:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [512:0] inflight_1; // @[Monitor.scala:726:35] wire [512:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [2051:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [2051:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [2051:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [2051:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [2051:0] _c_opcode_lookup_T_6 = {2048'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [2051:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [2051:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [2051:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [2051:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2051:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [512:0] d_clr_1; // @[Monitor.scala:774:34] wire [512:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [2051:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [2051:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2686 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2686 & d_release_ack_1 ? _d_clr_wo_ready_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2668 = _T_2710 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2668 ? _d_clr_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_11 = 8207'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2668 ? _d_opcodes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [8206:0] _d_sizes_clr_T_11 = 8207'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2668 ? _d_sizes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 10'h0; // @[Monitor.scala:36:7, :795:113] wire [512:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [512:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [2051:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [2051:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [2051:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [2051:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_243 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_243( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_75 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_75( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = \|_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 \| reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 \| _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_78 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_79 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_39( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_2 = 2'h1 << _GEN_1; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_111 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_111( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TransposePreloadUnroller : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}} regreset state : UInt<2>, clock, reset, UInt<1>(0h0) node garbage_addr = not(UInt<32>(0h0)) inst q of MultiHeadedQueue connect q.clock, clock connect q.reset, reset connect q.io.enq, io.in node _first_preload_T = eq(q.io.deq.bits[0].cmd.inst.funct, UInt<3>(0h6)) node _first_preload_T_1 = and(q.io.deq.valid[0], _first_preload_T) node _first_preload_T_2 = eq(state, UInt<1>(0h0)) node first_preload = and(_first_preload_T_1, _first_preload_T_2) reg b_transposed_and_ws : UInt<1>, clock node _unroll_preload_T = and(b_transposed_and_ws, q.io.deq.valid[1]) node _unroll_preload_T_1 = eq(q.io.deq.bits[1].cmd.inst.funct, UInt<3>(0h4)) node unroll_preload = and(_unroll_preload_T, _unroll_preload_T_1) wire first_preload_cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} connect first_preload_cmd, q.io.deq.bits[0] node _first_preload_cmd_cmd_rs2_T = bits(q.io.deq.bits[0].cmd.rs2, 63, 32) node _first_preload_cmd_cmd_rs2_T_1 = cat(_first_preload_cmd_cmd_rs2_T, garbage_addr) connect first_preload_cmd.cmd.rs2, _first_preload_cmd_cmd_rs2_T_1 connect first_preload_cmd.rob_id.valid, UInt<1>(0h0) wire first_compute_cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} connect first_compute_cmd, q.io.deq.bits[1] node _first_compute_cmd_cmd_inst_rs1_T = bits(q.io.deq.bits[1].cmd.rs1, 63, 32) node _first_compute_cmd_cmd_inst_rs1_T_1 = cat(_first_compute_cmd_cmd_inst_rs1_T, garbage_addr) connect first_compute_cmd.cmd.inst.rs1, _first_compute_cmd_cmd_inst_rs1_T_1 node _first_compute_cmd_cmd_inst_rs2_T = bits(q.io.deq.bits[1].cmd.rs2, 63, 32) node _first_compute_cmd_cmd_inst_rs2_T_1 = cat(_first_compute_cmd_cmd_inst_rs2_T, garbage_addr) connect first_compute_cmd.cmd.inst.rs2, _first_compute_cmd_cmd_inst_rs2_T_1 connect first_compute_cmd.cmd.inst.funct, UInt<3>(0h5) connect first_compute_cmd.rob_id.valid, UInt<1>(0h0) wire second_preload_cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} connect second_preload_cmd, q.io.deq.bits[0] node _second_preload_cmd_cmd_rs1_T = bits(q.io.deq.bits[0].cmd.rs1, 63, 32) node _second_preload_cmd_cmd_rs1_T_1 = cat(_second_preload_cmd_cmd_rs1_T, garbage_addr) connect second_preload_cmd.cmd.rs1, _second_preload_cmd_cmd_rs1_T_1 node config_cmd_type = bits(q.io.deq.bits[0].cmd.rs1, 1, 0) node _is_config_T = eq(q.io.deq.bits[0].cmd.inst.funct, UInt<1>(0h0)) node _is_config_T_1 = eq(config_cmd_type, UInt<1>(0h0)) node is_config = and(_is_config_T, _is_config_T_1) node _io_out_valid_T = eq(b_transposed_and_ws, UInt<1>(0h0)) node _io_out_valid_T_1 = or(_io_out_valid_T, q.io.deq.valid[1]) node _io_out_valid_T_2 = gt(state, UInt<1>(0h1)) node _io_out_valid_T_3 = mux(_io_out_valid_T_2, UInt<1>(0h1), q.io.deq.valid[0]) node _io_out_valid_T_4 = mux(first_preload, _io_out_valid_T_1, _io_out_valid_T_3) connect io.out.valid, _io_out_valid_T_4 node _io_out_bits_T = and(first_preload, unroll_preload) node _io_out_bits_T_1 = eq(state, UInt<1>(0h1)) node _io_out_bits_T_2 = eq(state, UInt<2>(0h2)) node _io_out_bits_T_3 = mux(_io_out_bits_T_2, second_preload_cmd, q.io.deq.bits[0]) node _io_out_bits_T_4 = mux(_io_out_bits_T_1, first_compute_cmd, _io_out_bits_T_3) node _io_out_bits_T_5 = mux(_io_out_bits_T, first_preload_cmd, _io_out_bits_T_4) connect io.out.bits, _io_out_bits_T_5 node _q_io_deq_pop_T = and(io.out.ready, io.out.valid) node _q_io_deq_pop_T_1 = and(first_preload, unroll_preload) node _q_io_deq_pop_T_2 = eq(_q_io_deq_pop_T_1, UInt<1>(0h0)) node _q_io_deq_pop_T_3 = and(_q_io_deq_pop_T, _q_io_deq_pop_T_2) node _q_io_deq_pop_T_4 = neq(state, UInt<1>(0h1)) node _q_io_deq_pop_T_5 = and(_q_io_deq_pop_T_3, _q_io_deq_pop_T_4) node _q_io_deq_pop_T_6 = mux(_q_io_deq_pop_T_5, UInt<1>(0h1), UInt<1>(0h0)) connect q.io.deq.pop, _q_io_deq_pop_T_6 node _T = and(io.out.ready, io.out.valid) when _T : when is_config : node set_only_strides = bits(q.io.deq.bits[0].cmd.rs1, 7, 7) node _T_1 = eq(set_only_strides, UInt<1>(0h0)) when _T_1 : node _b_transposed_and_ws_T = bits(q.io.deq.bits[0].cmd.rs1, 2, 2) node _b_transposed_and_ws_T_1 = eq(_b_transposed_and_ws_T, UInt<1>(0h1)) node _b_transposed_and_ws_T_2 = or(UInt<1>(0h1), _b_transposed_and_ws_T_1) node _b_transposed_and_ws_T_3 = bits(q.io.deq.bits[0].cmd.rs1, 9, 9) node _b_transposed_and_ws_T_4 = and(_b_transposed_and_ws_T_2, _b_transposed_and_ws_T_3) connect b_transposed_and_ws, _b_transposed_and_ws_T_4 else : node _T_2 = and(first_preload, unroll_preload) when _T_2 : connect state, UInt<1>(0h1) else : node _T_3 = geq(state, UInt<1>(0h1)) when _T_3 : node _state_T = eq(state, UInt<1>(0h0)) node _state_T_1 = eq(state, UInt<1>(0h1)) node _state_T_2 = eq(state, UInt<2>(0h2)) node _state_T_3 = mux(_state_T_1, UInt<2>(0h2), UInt<1>(0h0)) node _state_T_4 = mux(_state_T, UInt<1>(0h1), _state_T_3) connect state, _state_T_4 wire _WIRE : UInt<1>[45] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect _WIRE[8], UInt<1>(0h0) connect _WIRE[9], UInt<1>(0h0) connect _WIRE[10], UInt<1>(0h0) connect _WIRE[11], UInt<1>(0h0) connect _WIRE[12], UInt<1>(0h0) connect _WIRE[13], UInt<1>(0h0) connect _WIRE[14], UInt<1>(0h0) connect _WIRE[15], UInt<1>(0h0) connect _WIRE[16], UInt<1>(0h0) connect _WIRE[17], UInt<1>(0h0) connect _WIRE[18], UInt<1>(0h0) connect _WIRE[19], UInt<1>(0h0) connect _WIRE[20], UInt<1>(0h0) connect _WIRE[21], UInt<1>(0h0) connect _WIRE[22], UInt<1>(0h0) connect _WIRE[23], UInt<1>(0h0) connect _WIRE[24], UInt<1>(0h0) connect _WIRE[25], UInt<1>(0h0) connect _WIRE[26], UInt<1>(0h0) connect _WIRE[27], UInt<1>(0h0) connect _WIRE[28], UInt<1>(0h0) connect _WIRE[29], UInt<1>(0h0) connect _WIRE[30], UInt<1>(0h0) connect _WIRE[31], UInt<1>(0h0) connect _WIRE[32], UInt<1>(0h0) connect _WIRE[33], UInt<1>(0h0) connect _WIRE[34], UInt<1>(0h0) connect _WIRE[35], UInt<1>(0h0) connect _WIRE[36], UInt<1>(0h0) connect _WIRE[37], UInt<1>(0h0) connect _WIRE[38], UInt<1>(0h0) connect _WIRE[39], UInt<1>(0h0) connect _WIRE[40], UInt<1>(0h0) connect _WIRE[41], UInt<1>(0h0) connect _WIRE[42], UInt<1>(0h0) connect _WIRE[43], UInt<1>(0h0) connect _WIRE[44], UInt<1>(0h0) connect io.counter.event_signal, _WIRE wire _WIRE_1 : UInt<32>[8] connect _WIRE_1[0], UInt<32>(0h0) connect _WIRE_1[1], UInt<32>(0h0) connect _WIRE_1[2], UInt<32>(0h0) connect _WIRE_1[3], UInt<32>(0h0) connect _WIRE_1[4], UInt<32>(0h0) connect _WIRE_1[5], UInt<32>(0h0) connect _WIRE_1[6], UInt<32>(0h0) connect _WIRE_1[7], UInt<32>(0h0) connect io.counter.external_values, _WIRE_1 node _T_4 = neq(state, UInt<1>(0h0)) connect io.counter.event_signal[44], _T_4	module TransposePreloadUnroller( // @[TransposePreloadUnroller.scala:9:7] input clock, // @[TransposePreloadUnroller.scala:9:7] input reset, // @[TransposePreloadUnroller.scala:9:7] output io_in_ready, // @[TransposePreloadUnroller.scala:14:14] input io_in_valid, // @[TransposePreloadUnroller.scala:14:14] input [6:0] io_in_bits_cmd_inst_funct, // @[TransposePreloadUnroller.scala:14:14] input [4:0] io_in_bits_cmd_inst_rs2, // @[TransposePreloadUnroller.scala:14:14] input [4:0] io_in_bits_cmd_inst_rs1, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_inst_xd, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_inst_xs1, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_inst_xs2, // @[TransposePreloadUnroller.scala:14:14] input [4:0] io_in_bits_cmd_inst_rd, // @[TransposePreloadUnroller.scala:14:14] input [6:0] io_in_bits_cmd_inst_opcode, // @[TransposePreloadUnroller.scala:14:14] input [63:0] io_in_bits_cmd_rs1, // @[TransposePreloadUnroller.scala:14:14] input [63:0] io_in_bits_cmd_rs2, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_debug, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_cease, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_wfi, // @[TransposePreloadUnroller.scala:14:14] input [31:0] io_in_bits_cmd_status_isa, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_dprv, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_dv, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_prv, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_v, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sd, // @[TransposePreloadUnroller.scala:14:14] input [22:0] io_in_bits_cmd_status_zero2, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mpv, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_gva, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mbe, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sbe, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_sxl, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_uxl, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sd_rv32, // @[TransposePreloadUnroller.scala:14:14] input [7:0] io_in_bits_cmd_status_zero1, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_tsr, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_tw, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_tvm, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mxr, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sum, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mprv, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_xs, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_fs, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_mpp, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_vs, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_spp, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mpie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_ube, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_spie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_upie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_hie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_uie, // @[TransposePreloadUnroller.scala:14:14] input [5:0] io_in_bits_rob_id_bits, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_from_matmul_fsm, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_from_conv_fsm, // @[TransposePreloadUnroller.scala:14:14] input io_out_ready, // @[TransposePreloadUnroller.scala:14:14] output io_out_valid, // @[TransposePreloadUnroller.scala:14:14] output [6:0] io_out_bits_cmd_inst_funct, // @[TransposePreloadUnroller.scala:14:14] output [4:0] io_out_bits_cmd_inst_rs2, // @[TransposePreloadUnroller.scala:14:14] output [4:0] io_out_bits_cmd_inst_rs1, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_inst_xd, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_inst_xs1, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_inst_xs2, // @[TransposePreloadUnroller.scala:14:14] output [4:0] io_out_bits_cmd_inst_rd, // @[TransposePreloadUnroller.scala:14:14] output [6:0] io_out_bits_cmd_inst_opcode, // @[TransposePreloadUnroller.scala:14:14] output [63:0] io_out_bits_cmd_rs1, // @[TransposePreloadUnroller.scala:14:14] output [63:0] io_out_bits_cmd_rs2, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_debug, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_cease, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_wfi, // @[TransposePreloadUnroller.scala:14:14] output [31:0] io_out_bits_cmd_status_isa, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_dprv, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_dv, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_prv, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_v, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sd, // @[TransposePreloadUnroller.scala:14:14] output [22:0] io_out_bits_cmd_status_zero2, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mpv, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_gva, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mbe, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sbe, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_sxl, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_uxl, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sd_rv32, // @[TransposePreloadUnroller.scala:14:14] output [7:0] io_out_bits_cmd_status_zero1, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_tsr, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_tw, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_tvm, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mxr, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sum, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mprv, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_xs, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_fs, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_mpp, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_vs, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_spp, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mpie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_ube, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_spie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_upie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_hie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_uie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_rob_id_valid, // @[TransposePreloadUnroller.scala:14:14] output [5:0] io_out_bits_rob_id_bits, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_from_matmul_fsm, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_from_conv_fsm, // @[TransposePreloadUnroller.scala:14:14] input io_counter_external_reset // @[TransposePreloadUnroller.scala:14:14] ); wire _q_io_deq_valid_0; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_valid_1; // @[MultiHeadedQueue.scala:53:19] wire [6:0] _q_io_deq_bits_0_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19] wire [4:0] _q_io_deq_bits_0_cmd_inst_rs2; // @[MultiHeadedQueue.scala:53:19] wire [4:0] _q_io_deq_bits_0_cmd_inst_rs1; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_inst_xd; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_inst_xs1; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_inst_xs2; // @[MultiHeadedQueue.scala:53:19] wire [4:0] _q_io_deq_bits_0_cmd_inst_rd; // @[MultiHeadedQueue.scala:53:19] wire [6:0] _q_io_deq_bits_0_cmd_inst_opcode; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_0_cmd_rs1; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_0_cmd_rs2; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_debug; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_cease; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_wfi; // @[MultiHeadedQueue.scala:53:19] wire [31:0] _q_io_deq_bits_0_cmd_status_isa; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_dprv; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_dv; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_prv; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_v; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sd; // @[MultiHeadedQueue.scala:53:19] wire [22:0] _q_io_deq_bits_0_cmd_status_zero2; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mpv; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_gva; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mbe; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sbe; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_sxl; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_uxl; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sd_rv32; // @[MultiHeadedQueue.scala:53:19] wire [7:0] _q_io_deq_bits_0_cmd_status_zero1; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_tsr; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_tw; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_tvm; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mxr; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sum; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mprv; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_xs; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_fs; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_mpp; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_vs; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_spp; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mpie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_ube; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_spie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_upie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_hie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_uie; // @[MultiHeadedQueue.scala:53:19] wire [5:0] _q_io_deq_bits_0_rob_id_bits; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_from_matmul_fsm; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_from_conv_fsm; // @[MultiHeadedQueue.scala:53:19] wire [6:0] _q_io_deq_bits_1_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_1_cmd_rs1; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_1_cmd_rs2; // @[MultiHeadedQueue.scala:53:19] wire io_in_valid_0 = io_in_valid; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_in_bits_cmd_inst_rs2_0 = io_in_bits_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_in_bits_cmd_inst_rs1_0 = io_in_bits_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_inst_xd_0 = io_in_bits_cmd_inst_xd; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_inst_xs1_0 = io_in_bits_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_inst_xs2_0 = io_in_bits_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_in_bits_cmd_inst_rd_0 = io_in_bits_cmd_inst_rd; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_in_bits_cmd_inst_opcode_0 = io_in_bits_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_debug_0 = io_in_bits_cmd_status_debug; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_cease_0 = io_in_bits_cmd_status_cease; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_wfi_0 = io_in_bits_cmd_status_wfi; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_in_bits_cmd_status_isa_0 = io_in_bits_cmd_status_isa; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_dprv_0 = io_in_bits_cmd_status_dprv; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_dv_0 = io_in_bits_cmd_status_dv; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_prv_0 = io_in_bits_cmd_status_prv; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_v_0 = io_in_bits_cmd_status_v; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sd_0 = io_in_bits_cmd_status_sd; // @[TransposePreloadUnroller.scala:9:7] wire [22:0] io_in_bits_cmd_status_zero2_0 = io_in_bits_cmd_status_zero2; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mpv_0 = io_in_bits_cmd_status_mpv; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_gva_0 = io_in_bits_cmd_status_gva; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mbe_0 = io_in_bits_cmd_status_mbe; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sbe_0 = io_in_bits_cmd_status_sbe; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_sxl_0 = io_in_bits_cmd_status_sxl; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_uxl_0 = io_in_bits_cmd_status_uxl; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sd_rv32_0 = io_in_bits_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:9:7] wire [7:0] io_in_bits_cmd_status_zero1_0 = io_in_bits_cmd_status_zero1; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_tsr_0 = io_in_bits_cmd_status_tsr; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_tw_0 = io_in_bits_cmd_status_tw; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_tvm_0 = io_in_bits_cmd_status_tvm; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mxr_0 = io_in_bits_cmd_status_mxr; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sum_0 = io_in_bits_cmd_status_sum; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mprv_0 = io_in_bits_cmd_status_mprv; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_xs_0 = io_in_bits_cmd_status_xs; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_fs_0 = io_in_bits_cmd_status_fs; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_mpp_0 = io_in_bits_cmd_status_mpp; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_vs_0 = io_in_bits_cmd_status_vs; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_spp_0 = io_in_bits_cmd_status_spp; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mpie_0 = io_in_bits_cmd_status_mpie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_ube_0 = io_in_bits_cmd_status_ube; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_spie_0 = io_in_bits_cmd_status_spie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_upie_0 = io_in_bits_cmd_status_upie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mie_0 = io_in_bits_cmd_status_mie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_hie_0 = io_in_bits_cmd_status_hie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sie_0 = io_in_bits_cmd_status_sie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_uie_0 = io_in_bits_cmd_status_uie; // @[TransposePreloadUnroller.scala:9:7] wire [5:0] io_in_bits_rob_id_bits_0 = io_in_bits_rob_id_bits; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_from_matmul_fsm_0 = io_in_bits_from_matmul_fsm; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_from_conv_fsm_0 = io_in_bits_from_conv_fsm; // @[TransposePreloadUnroller.scala:9:7] wire io_out_ready_0 = io_out_ready; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_external_reset_0 = io_counter_external_reset; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] garbage_addr = 32'hFFFFFFFF; // @[TransposePreloadUnroller.scala:27:22] wire [6:0] first_compute_cmd_cmd_inst_funct = 7'h5; // @[TransposePreloadUnroller.scala:44:35] wire [31:0] io_counter_external_values_0 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_1 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_2 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_3 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_4 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_5 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_6 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_7 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_0 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_1 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_2 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_3 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_4 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_5 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_6 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_7 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_8 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_9 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_10 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_11 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_12 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_13 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_14 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_15 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_16 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_17 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_18 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_19 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_20 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_21 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_22 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_23 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_24 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_25 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_26 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_27 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_28 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_29 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_30 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_31 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_32 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_33 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_34 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_35 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_36 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_37 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_38 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_39 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_40 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_41 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_42 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_43 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire first_preload_cmd_rob_id_valid = 1'h0; // @[TransposePreloadUnroller.scala:40:35] wire first_compute_cmd_rob_id_valid = 1'h0; // @[TransposePreloadUnroller.scala:44:35] wire io_in_bits_rob_id_valid = 1'h1; // @[TransposePreloadUnroller.scala:9:7] wire second_preload_cmd_rob_id_valid = 1'h1; // @[TransposePreloadUnroller.scala:50:36] wire _io_out_bits_T_3_rob_id_valid = 1'h1; // @[Mux.scala:126:16] wire _b_transposed_and_ws_T_2 = 1'h1; // @[TransposePreloadUnroller.scala:73:61] wire _io_out_valid_T_4; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_5_cmd_inst_funct; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_5_cmd_inst_rs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_5_cmd_inst_rs1; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_inst_xd; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_inst_xs1; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_inst_xs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_5_cmd_inst_rd; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_5_cmd_inst_opcode; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_5_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_5_cmd_rs2; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_debug; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_cease; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_wfi; // @[Mux.scala:126:16] wire [31:0] _io_out_bits_T_5_cmd_status_isa; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_dprv; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_dv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_prv; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_v; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sd; // @[Mux.scala:126:16] wire [22:0] _io_out_bits_T_5_cmd_status_zero2; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mpv; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_gva; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mbe; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sbe; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_sxl; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_uxl; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sd_rv32; // @[Mux.scala:126:16] wire [7:0] _io_out_bits_T_5_cmd_status_zero1; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_tsr; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_tw; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_tvm; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mxr; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sum; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mprv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_xs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_fs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_mpp; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_vs; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_spp; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mpie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_ube; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_spie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_upie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_hie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_uie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_rob_id_valid; // @[Mux.scala:126:16] wire [5:0] _io_out_bits_T_5_rob_id_bits; // @[Mux.scala:126:16] wire _io_out_bits_T_5_from_matmul_fsm; // @[Mux.scala:126:16] wire _io_out_bits_T_5_from_conv_fsm; // @[Mux.scala:126:16] wire io_in_ready_0; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_out_bits_cmd_inst_funct_0; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_inst_xd_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_inst_xs1_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_inst_xs2_0; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_out_bits_cmd_inst_rd_0; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_debug_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_cease_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_wfi_0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_out_bits_cmd_status_isa_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_dprv_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_dv_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_prv_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_v_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sd_0; // @[TransposePreloadUnroller.scala:9:7] wire [22:0] io_out_bits_cmd_status_zero2_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mpv_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_gva_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mbe_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sbe_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_sxl_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_uxl_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sd_rv32_0; // @[TransposePreloadUnroller.scala:9:7] wire [7:0] io_out_bits_cmd_status_zero1_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_tsr_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_tw_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_tvm_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mxr_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sum_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mprv_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_xs_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_fs_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_mpp_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_vs_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_spp_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mpie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_ube_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_spie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_upie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_hie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_uie_0; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_out_bits_cmd_rs1_0; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_out_bits_cmd_rs2_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_rob_id_valid_0; // @[TransposePreloadUnroller.scala:9:7] wire [5:0] io_out_bits_rob_id_bits_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_from_matmul_fsm_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_from_conv_fsm_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_valid_0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_44; // @[TransposePreloadUnroller.scala:9:7] reg [1:0] state; // @[TransposePreloadUnroller.scala:25:22] wire _first_preload_T = _q_io_deq_bits_0_cmd_inst_funct == 7'h6; // @[TransposePreloadUnroller.scala:35:46] wire _first_preload_T_1 = _q_io_deq_valid_0 & _first_preload_T; // @[TransposePreloadUnroller.scala:35:{33,46}] wire _GEN = state == 2'h0; // @[TransposePreloadUnroller.scala:25:22, :35:71] wire _first_preload_T_2; // @[TransposePreloadUnroller.scala:35:71] assign _first_preload_T_2 = _GEN; // @[TransposePreloadUnroller.scala:35:71] wire _state_T; // @[TransposePreloadUnroller.scala:78:22] assign _state_T = _GEN; // @[TransposePreloadUnroller.scala:35:71, :78:22] wire first_preload = _first_preload_T_1 & _first_preload_T_2; // @[TransposePreloadUnroller.scala:35:{33,62,71}] reg b_transposed_and_ws; // @[TransposePreloadUnroller.scala:37:32] wire _unroll_preload_T = b_transposed_and_ws & _q_io_deq_valid_1; // @[TransposePreloadUnroller.scala:37:32, :38:44] wire _unroll_preload_T_1 = _q_io_deq_bits_1_cmd_inst_funct == 7'h4; // @[TransposePreloadUnroller.scala:38:70] wire unroll_preload = _unroll_preload_T & _unroll_preload_T_1; // @[TransposePreloadUnroller.scala:38:{44,57,70}] wire [63:0] _first_preload_cmd_cmd_rs2_T_1; // @[TransposePreloadUnroller.scala:41:35] wire [6:0] first_preload_cmd_cmd_inst_funct; // @[TransposePreloadUnroller.scala:40:35] wire [4:0] first_preload_cmd_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:40:35] wire [4:0] first_preload_cmd_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_inst_xd; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:40:35] wire [4:0] first_preload_cmd_cmd_inst_rd; // @[TransposePreloadUnroller.scala:40:35] wire [6:0] first_preload_cmd_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_debug; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_cease; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_wfi; // @[TransposePreloadUnroller.scala:40:35] wire [31:0] first_preload_cmd_cmd_status_isa; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_dprv; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_dv; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_prv; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_v; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sd; // @[TransposePreloadUnroller.scala:40:35] wire [22:0] first_preload_cmd_cmd_status_zero2; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mpv; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_gva; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mbe; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sbe; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_sxl; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_uxl; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:40:35] wire [7:0] first_preload_cmd_cmd_status_zero1; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_tsr; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_tw; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_tvm; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mxr; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sum; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mprv; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_xs; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_fs; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_mpp; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_vs; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_spp; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mpie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_ube; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_spie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_upie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_hie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_uie; // @[TransposePreloadUnroller.scala:40:35] wire [63:0] first_preload_cmd_cmd_rs1; // @[TransposePreloadUnroller.scala:40:35] wire [63:0] first_preload_cmd_cmd_rs2; // @[TransposePreloadUnroller.scala:40:35] wire [5:0] first_preload_cmd_rob_id_bits; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_from_matmul_fsm; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_from_conv_fsm; // @[TransposePreloadUnroller.scala:40:35] wire [31:0] _first_preload_cmd_cmd_rs2_T = _q_io_deq_bits_0_cmd_rs2[63:32]; // @[TransposePreloadUnroller.scala:41:51] assign _first_preload_cmd_cmd_rs2_T_1 = {_first_preload_cmd_cmd_rs2_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:41:{35,51}] assign first_preload_cmd_cmd_rs2 = _first_preload_cmd_cmd_rs2_T_1; // @[TransposePreloadUnroller.scala:40:35, :41:35] wire [4:0] first_compute_cmd_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:44:35] wire [4:0] first_compute_cmd_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_inst_xd; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:44:35] wire [4:0] first_compute_cmd_cmd_inst_rd; // @[TransposePreloadUnroller.scala:44:35] wire [6:0] first_compute_cmd_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_debug; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_cease; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_wfi; // @[TransposePreloadUnroller.scala:44:35] wire [31:0] first_compute_cmd_cmd_status_isa; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_dprv; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_dv; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_prv; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_v; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sd; // @[TransposePreloadUnroller.scala:44:35] wire [22:0] first_compute_cmd_cmd_status_zero2; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mpv; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_gva; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mbe; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sbe; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_sxl; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_uxl; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:44:35] wire [7:0] first_compute_cmd_cmd_status_zero1; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_tsr; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_tw; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_tvm; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mxr; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sum; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mprv; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_xs; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_fs; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_mpp; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_vs; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_spp; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mpie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_ube; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_spie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_upie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_hie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_uie; // @[TransposePreloadUnroller.scala:44:35] wire [63:0] first_compute_cmd_cmd_rs1; // @[TransposePreloadUnroller.scala:44:35] wire [63:0] first_compute_cmd_cmd_rs2; // @[TransposePreloadUnroller.scala:44:35] wire [5:0] first_compute_cmd_rob_id_bits; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_from_matmul_fsm; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_from_conv_fsm; // @[TransposePreloadUnroller.scala:44:35] wire [31:0] _first_compute_cmd_cmd_inst_rs1_T = _q_io_deq_bits_1_cmd_rs1[63:32]; // @[TransposePreloadUnroller.scala:45:56] wire [63:0] _first_compute_cmd_cmd_inst_rs1_T_1 = {_first_compute_cmd_cmd_inst_rs1_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:45:{40,56}] assign first_compute_cmd_cmd_inst_rs1 = _first_compute_cmd_cmd_inst_rs1_T_1[4:0]; // @[TransposePreloadUnroller.scala:44:35, :45:{34,40}] wire [31:0] _first_compute_cmd_cmd_inst_rs2_T = _q_io_deq_bits_1_cmd_rs2[63:32]; // @[TransposePreloadUnroller.scala:46:56] wire [63:0] _first_compute_cmd_cmd_inst_rs2_T_1 = {_first_compute_cmd_cmd_inst_rs2_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:46:{40,56}] assign first_compute_cmd_cmd_inst_rs2 = _first_compute_cmd_cmd_inst_rs2_T_1[4:0]; // @[TransposePreloadUnroller.scala:44:35, :46:{34,40}] wire [63:0] _second_preload_cmd_cmd_rs1_T_1; // @[TransposePreloadUnroller.scala:51:36] wire [6:0] second_preload_cmd_cmd_inst_funct; // @[TransposePreloadUnroller.scala:50:36] wire [4:0] second_preload_cmd_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:50:36] wire [4:0] second_preload_cmd_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_inst_xd; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:50:36] wire [4:0] second_preload_cmd_cmd_inst_rd; // @[TransposePreloadUnroller.scala:50:36] wire [6:0] second_preload_cmd_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_debug; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_cease; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_wfi; // @[TransposePreloadUnroller.scala:50:36] wire [31:0] second_preload_cmd_cmd_status_isa; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_dprv; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_dv; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_prv; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_v; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sd; // @[TransposePreloadUnroller.scala:50:36] wire [22:0] second_preload_cmd_cmd_status_zero2; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mpv; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_gva; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mbe; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sbe; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_sxl; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_uxl; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:50:36] wire [7:0] second_preload_cmd_cmd_status_zero1; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_tsr; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_tw; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_tvm; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mxr; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sum; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mprv; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_xs; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_fs; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_mpp; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_vs; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_spp; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mpie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_ube; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_spie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_upie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_hie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_uie; // @[TransposePreloadUnroller.scala:50:36] wire [63:0] second_preload_cmd_cmd_rs1; // @[TransposePreloadUnroller.scala:50:36] wire [63:0] second_preload_cmd_cmd_rs2; // @[TransposePreloadUnroller.scala:50:36] wire [5:0] second_preload_cmd_rob_id_bits; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_from_matmul_fsm; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_from_conv_fsm; // @[TransposePreloadUnroller.scala:50:36] wire [31:0] _second_preload_cmd_cmd_rs1_T = _q_io_deq_bits_0_cmd_rs1[63:32]; // @[TransposePreloadUnroller.scala:51:52] assign _second_preload_cmd_cmd_rs1_T_1 = {_second_preload_cmd_cmd_rs1_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:51:{36,52}] assign second_preload_cmd_cmd_rs1 = _second_preload_cmd_cmd_rs1_T_1; // @[TransposePreloadUnroller.scala:50:36, :51:36] wire [1:0] config_cmd_type = _q_io_deq_bits_0_cmd_rs1[1:0]; // @[TransposePreloadUnroller.scala:53:40] wire _is_config_T = _q_io_deq_bits_0_cmd_inst_funct == 7'h0; // @[TransposePreloadUnroller.scala:54:29] wire _is_config_T_1 = config_cmd_type == 2'h0; // @[TransposePreloadUnroller.scala:53:40, :54:63] wire is_config = _is_config_T & _is_config_T_1; // @[TransposePreloadUnroller.scala:54:{29,44,63}] wire _io_out_valid_T = ~b_transposed_and_ws; // @[TransposePreloadUnroller.scala:37:32, :57:23] wire _io_out_valid_T_1 = _io_out_valid_T \| _q_io_deq_valid_1; // @[TransposePreloadUnroller.scala:57:{23,44}] wire _io_out_valid_T_2 = state[1]; // @[TransposePreloadUnroller.scala:25:22, :58:12] wire _io_out_valid_T_3 = _io_out_valid_T_2 \| _q_io_deq_valid_0; // @[Mux.scala:126:16] assign _io_out_valid_T_4 = first_preload ? _io_out_valid_T_1 : _io_out_valid_T_3; // @[Mux.scala:126:16] assign io_out_valid_0 = _io_out_valid_T_4; // @[Mux.scala:126:16] wire _T_2 = first_preload & unroll_preload; // @[TransposePreloadUnroller.scala:35:62, :38:57, :62:20] wire _io_out_bits_T; // @[TransposePreloadUnroller.scala:62:20] assign _io_out_bits_T = _T_2; // @[TransposePreloadUnroller.scala:62:20] wire _q_io_deq_pop_T_1; // @[TransposePreloadUnroller.scala:67:47] assign _q_io_deq_pop_T_1 = _T_2; // @[TransposePreloadUnroller.scala:62:20, :67:47] wire _GEN_0 = state == 2'h1; // @[TransposePreloadUnroller.scala:25:22, :58:12, :63:12] wire _io_out_bits_T_1; // @[TransposePreloadUnroller.scala:63:12] assign _io_out_bits_T_1 = _GEN_0; // @[TransposePreloadUnroller.scala:63:12] wire _state_T_1; // @[TransposePreloadUnroller.scala:78:22] assign _state_T_1 = _GEN_0; // @[TransposePreloadUnroller.scala:63:12, :78:22] wire _GEN_1 = state == 2'h2; // @[TransposePreloadUnroller.scala:25:22, :64:12] wire _io_out_bits_T_2; // @[TransposePreloadUnroller.scala:64:12] assign _io_out_bits_T_2 = _GEN_1; // @[TransposePreloadUnroller.scala:64:12] wire _state_T_2; // @[TransposePreloadUnroller.scala:78:22] assign _state_T_2 = _GEN_1; // @[TransposePreloadUnroller.scala:64:12, :78:22] wire [6:0] _io_out_bits_T_3_cmd_inst_funct = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_funct : _q_io_deq_bits_0_cmd_inst_funct; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_3_cmd_inst_rs2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_rs2 : _q_io_deq_bits_0_cmd_inst_rs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_3_cmd_inst_rs1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_rs1 : _q_io_deq_bits_0_cmd_inst_rs1; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_inst_xd = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_xd : _q_io_deq_bits_0_cmd_inst_xd; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_inst_xs1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_xs1 : _q_io_deq_bits_0_cmd_inst_xs1; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_inst_xs2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_xs2 : _q_io_deq_bits_0_cmd_inst_xs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_3_cmd_inst_rd = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_rd : _q_io_deq_bits_0_cmd_inst_rd; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_3_cmd_inst_opcode = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_opcode : _q_io_deq_bits_0_cmd_inst_opcode; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_3_cmd_rs1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_rs1 : _q_io_deq_bits_0_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_3_cmd_rs2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_rs2 : _q_io_deq_bits_0_cmd_rs2; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_debug = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_debug : _q_io_deq_bits_0_cmd_status_debug; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_cease = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_cease : _q_io_deq_bits_0_cmd_status_cease; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_wfi = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_wfi : _q_io_deq_bits_0_cmd_status_wfi; // @[Mux.scala:126:16] wire [31:0] _io_out_bits_T_3_cmd_status_isa = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_isa : _q_io_deq_bits_0_cmd_status_isa; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_dprv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_dprv : _q_io_deq_bits_0_cmd_status_dprv; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_dv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_dv : _q_io_deq_bits_0_cmd_status_dv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_prv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_prv : _q_io_deq_bits_0_cmd_status_prv; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_v = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_v : _q_io_deq_bits_0_cmd_status_v; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sd = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sd : _q_io_deq_bits_0_cmd_status_sd; // @[Mux.scala:126:16] wire [22:0] _io_out_bits_T_3_cmd_status_zero2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_zero2 : _q_io_deq_bits_0_cmd_status_zero2; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mpv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mpv : _q_io_deq_bits_0_cmd_status_mpv; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_gva = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_gva : _q_io_deq_bits_0_cmd_status_gva; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mbe = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mbe : _q_io_deq_bits_0_cmd_status_mbe; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sbe = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sbe : _q_io_deq_bits_0_cmd_status_sbe; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_sxl = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sxl : _q_io_deq_bits_0_cmd_status_sxl; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_uxl = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_uxl : _q_io_deq_bits_0_cmd_status_uxl; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sd_rv32 = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sd_rv32 : _q_io_deq_bits_0_cmd_status_sd_rv32; // @[Mux.scala:126:16] wire [7:0] _io_out_bits_T_3_cmd_status_zero1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_zero1 : _q_io_deq_bits_0_cmd_status_zero1; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_tsr = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_tsr : _q_io_deq_bits_0_cmd_status_tsr; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_tw = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_tw : _q_io_deq_bits_0_cmd_status_tw; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_tvm = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_tvm : _q_io_deq_bits_0_cmd_status_tvm; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mxr = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mxr : _q_io_deq_bits_0_cmd_status_mxr; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sum = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sum : _q_io_deq_bits_0_cmd_status_sum; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mprv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mprv : _q_io_deq_bits_0_cmd_status_mprv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_xs = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_xs : _q_io_deq_bits_0_cmd_status_xs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_fs = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_fs : _q_io_deq_bits_0_cmd_status_fs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_mpp = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mpp : _q_io_deq_bits_0_cmd_status_mpp; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_vs = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_vs : _q_io_deq_bits_0_cmd_status_vs; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_spp = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_spp : _q_io_deq_bits_0_cmd_status_spp; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mpie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mpie : _q_io_deq_bits_0_cmd_status_mpie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_ube = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_ube : _q_io_deq_bits_0_cmd_status_ube; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_spie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_spie : _q_io_deq_bits_0_cmd_status_spie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_upie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_upie : _q_io_deq_bits_0_cmd_status_upie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mie : _q_io_deq_bits_0_cmd_status_mie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_hie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_hie : _q_io_deq_bits_0_cmd_status_hie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sie : _q_io_deq_bits_0_cmd_status_sie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_uie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_uie : _q_io_deq_bits_0_cmd_status_uie; // @[Mux.scala:126:16] wire [5:0] _io_out_bits_T_3_rob_id_bits = _io_out_bits_T_2 ? second_preload_cmd_rob_id_bits : _q_io_deq_bits_0_rob_id_bits; // @[Mux.scala:126:16] wire _io_out_bits_T_3_from_matmul_fsm = _io_out_bits_T_2 ? second_preload_cmd_from_matmul_fsm : _q_io_deq_bits_0_from_matmul_fsm; // @[Mux.scala:126:16] wire _io_out_bits_T_3_from_conv_fsm = _io_out_bits_T_2 ? second_preload_cmd_from_conv_fsm : _q_io_deq_bits_0_from_conv_fsm; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_4_cmd_inst_funct = _io_out_bits_T_1 ? 7'h5 : _io_out_bits_T_3_cmd_inst_funct; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_4_cmd_inst_rs2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_rs2 : _io_out_bits_T_3_cmd_inst_rs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_4_cmd_inst_rs1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_rs1 : _io_out_bits_T_3_cmd_inst_rs1; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_inst_xd = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_xd : _io_out_bits_T_3_cmd_inst_xd; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_inst_xs1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_xs1 : _io_out_bits_T_3_cmd_inst_xs1; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_inst_xs2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_xs2 : _io_out_bits_T_3_cmd_inst_xs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_4_cmd_inst_rd = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_rd : _io_out_bits_T_3_cmd_inst_rd; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_4_cmd_inst_opcode = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_opcode : _io_out_bits_T_3_cmd_inst_opcode; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_4_cmd_rs1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_rs1 : _io_out_bits_T_3_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_4_cmd_rs2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_rs2 : _io_out_bits_T_3_cmd_rs2; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_debug = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_debug : _io_out_bits_T_3_cmd_status_debug; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_cease = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_cease : _io_out_bits_T_3_cmd_status_cease; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_wfi = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_wfi : _io_out_bits_T_3_cmd_status_wfi; // @[Mux.scala:126:16] wire [31:0] _io_out_bits_T_4_cmd_status_isa = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_isa : _io_out_bits_T_3_cmd_status_isa; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_dprv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_dprv : _io_out_bits_T_3_cmd_status_dprv; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_dv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_dv : _io_out_bits_T_3_cmd_status_dv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_prv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_prv : _io_out_bits_T_3_cmd_status_prv; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_v = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_v : _io_out_bits_T_3_cmd_status_v; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sd = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sd : _io_out_bits_T_3_cmd_status_sd; // @[Mux.scala:126:16] wire [22:0] _io_out_bits_T_4_cmd_status_zero2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_zero2 : _io_out_bits_T_3_cmd_status_zero2; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mpv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mpv : _io_out_bits_T_3_cmd_status_mpv; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_gva = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_gva : _io_out_bits_T_3_cmd_status_gva; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mbe = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mbe : _io_out_bits_T_3_cmd_status_mbe; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sbe = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sbe : _io_out_bits_T_3_cmd_status_sbe; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_sxl = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sxl : _io_out_bits_T_3_cmd_status_sxl; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_uxl = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_uxl : _io_out_bits_T_3_cmd_status_uxl; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sd_rv32 = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sd_rv32 : _io_out_bits_T_3_cmd_status_sd_rv32; // @[Mux.scala:126:16] wire [7:0] _io_out_bits_T_4_cmd_status_zero1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_zero1 : _io_out_bits_T_3_cmd_status_zero1; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_tsr = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_tsr : _io_out_bits_T_3_cmd_status_tsr; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_tw = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_tw : _io_out_bits_T_3_cmd_status_tw; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_tvm = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_tvm : _io_out_bits_T_3_cmd_status_tvm; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mxr = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mxr : _io_out_bits_T_3_cmd_status_mxr; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sum = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sum : _io_out_bits_T_3_cmd_status_sum; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mprv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mprv : _io_out_bits_T_3_cmd_status_mprv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_xs = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_xs : _io_out_bits_T_3_cmd_status_xs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_fs = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_fs : _io_out_bits_T_3_cmd_status_fs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_mpp = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mpp : _io_out_bits_T_3_cmd_status_mpp; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_vs = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_vs : _io_out_bits_T_3_cmd_status_vs; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_spp = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_spp : _io_out_bits_T_3_cmd_status_spp; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mpie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mpie : _io_out_bits_T_3_cmd_status_mpie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_ube = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_ube : _io_out_bits_T_3_cmd_status_ube; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_spie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_spie : _io_out_bits_T_3_cmd_status_spie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_upie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_upie : _io_out_bits_T_3_cmd_status_upie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mie : _io_out_bits_T_3_cmd_status_mie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_hie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_hie : _io_out_bits_T_3_cmd_status_hie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sie : _io_out_bits_T_3_cmd_status_sie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_uie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_uie : _io_out_bits_T_3_cmd_status_uie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_rob_id_valid = ~_io_out_bits_T_1; // @[Mux.scala:126:16] wire [5:0] _io_out_bits_T_4_rob_id_bits = _io_out_bits_T_1 ? first_compute_cmd_rob_id_bits : _io_out_bits_T_3_rob_id_bits; // @[Mux.scala:126:16] wire _io_out_bits_T_4_from_matmul_fsm = _io_out_bits_T_1 ? first_compute_cmd_from_matmul_fsm : _io_out_bits_T_3_from_matmul_fsm; // @[Mux.scala:126:16] wire _io_out_bits_T_4_from_conv_fsm = _io_out_bits_T_1 ? first_compute_cmd_from_conv_fsm : _io_out_bits_T_3_from_conv_fsm; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_funct = _io_out_bits_T ? first_preload_cmd_cmd_inst_funct : _io_out_bits_T_4_cmd_inst_funct; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_rs2 = _io_out_bits_T ? first_preload_cmd_cmd_inst_rs2 : _io_out_bits_T_4_cmd_inst_rs2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_rs1 = _io_out_bits_T ? first_preload_cmd_cmd_inst_rs1 : _io_out_bits_T_4_cmd_inst_rs1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_xd = _io_out_bits_T ? first_preload_cmd_cmd_inst_xd : _io_out_bits_T_4_cmd_inst_xd; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_xs1 = _io_out_bits_T ? first_preload_cmd_cmd_inst_xs1 : _io_out_bits_T_4_cmd_inst_xs1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_xs2 = _io_out_bits_T ? first_preload_cmd_cmd_inst_xs2 : _io_out_bits_T_4_cmd_inst_xs2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_rd = _io_out_bits_T ? first_preload_cmd_cmd_inst_rd : _io_out_bits_T_4_cmd_inst_rd; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_opcode = _io_out_bits_T ? first_preload_cmd_cmd_inst_opcode : _io_out_bits_T_4_cmd_inst_opcode; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_rs1 = _io_out_bits_T ? first_preload_cmd_cmd_rs1 : _io_out_bits_T_4_cmd_rs1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_rs2 = _io_out_bits_T ? first_preload_cmd_cmd_rs2 : _io_out_bits_T_4_cmd_rs2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_debug = _io_out_bits_T ? first_preload_cmd_cmd_status_debug : _io_out_bits_T_4_cmd_status_debug; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_cease = _io_out_bits_T ? first_preload_cmd_cmd_status_cease : _io_out_bits_T_4_cmd_status_cease; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_wfi = _io_out_bits_T ? first_preload_cmd_cmd_status_wfi : _io_out_bits_T_4_cmd_status_wfi; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_isa = _io_out_bits_T ? first_preload_cmd_cmd_status_isa : _io_out_bits_T_4_cmd_status_isa; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_dprv = _io_out_bits_T ? first_preload_cmd_cmd_status_dprv : _io_out_bits_T_4_cmd_status_dprv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_dv = _io_out_bits_T ? first_preload_cmd_cmd_status_dv : _io_out_bits_T_4_cmd_status_dv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_prv = _io_out_bits_T ? first_preload_cmd_cmd_status_prv : _io_out_bits_T_4_cmd_status_prv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_v = _io_out_bits_T ? first_preload_cmd_cmd_status_v : _io_out_bits_T_4_cmd_status_v; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sd = _io_out_bits_T ? first_preload_cmd_cmd_status_sd : _io_out_bits_T_4_cmd_status_sd; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_zero2 = _io_out_bits_T ? first_preload_cmd_cmd_status_zero2 : _io_out_bits_T_4_cmd_status_zero2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mpv = _io_out_bits_T ? first_preload_cmd_cmd_status_mpv : _io_out_bits_T_4_cmd_status_mpv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_gva = _io_out_bits_T ? first_preload_cmd_cmd_status_gva : _io_out_bits_T_4_cmd_status_gva; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mbe = _io_out_bits_T ? first_preload_cmd_cmd_status_mbe : _io_out_bits_T_4_cmd_status_mbe; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sbe = _io_out_bits_T ? first_preload_cmd_cmd_status_sbe : _io_out_bits_T_4_cmd_status_sbe; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sxl = _io_out_bits_T ? first_preload_cmd_cmd_status_sxl : _io_out_bits_T_4_cmd_status_sxl; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_uxl = _io_out_bits_T ? first_preload_cmd_cmd_status_uxl : _io_out_bits_T_4_cmd_status_uxl; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sd_rv32 = _io_out_bits_T ? first_preload_cmd_cmd_status_sd_rv32 : _io_out_bits_T_4_cmd_status_sd_rv32; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_zero1 = _io_out_bits_T ? first_preload_cmd_cmd_status_zero1 : _io_out_bits_T_4_cmd_status_zero1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_tsr = _io_out_bits_T ? first_preload_cmd_cmd_status_tsr : _io_out_bits_T_4_cmd_status_tsr; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_tw = _io_out_bits_T ? first_preload_cmd_cmd_status_tw : _io_out_bits_T_4_cmd_status_tw; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_tvm = _io_out_bits_T ? first_preload_cmd_cmd_status_tvm : _io_out_bits_T_4_cmd_status_tvm; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mxr = _io_out_bits_T ? first_preload_cmd_cmd_status_mxr : _io_out_bits_T_4_cmd_status_mxr; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sum = _io_out_bits_T ? first_preload_cmd_cmd_status_sum : _io_out_bits_T_4_cmd_status_sum; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mprv = _io_out_bits_T ? first_preload_cmd_cmd_status_mprv : _io_out_bits_T_4_cmd_status_mprv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_xs = _io_out_bits_T ? first_preload_cmd_cmd_status_xs : _io_out_bits_T_4_cmd_status_xs; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_fs = _io_out_bits_T ? first_preload_cmd_cmd_status_fs : _io_out_bits_T_4_cmd_status_fs; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mpp = _io_out_bits_T ? first_preload_cmd_cmd_status_mpp : _io_out_bits_T_4_cmd_status_mpp; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_vs = _io_out_bits_T ? first_preload_cmd_cmd_status_vs : _io_out_bits_T_4_cmd_status_vs; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_spp = _io_out_bits_T ? first_preload_cmd_cmd_status_spp : _io_out_bits_T_4_cmd_status_spp; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mpie = _io_out_bits_T ? first_preload_cmd_cmd_status_mpie : _io_out_bits_T_4_cmd_status_mpie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_ube = _io_out_bits_T ? first_preload_cmd_cmd_status_ube : _io_out_bits_T_4_cmd_status_ube; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_spie = _io_out_bits_T ? first_preload_cmd_cmd_status_spie : _io_out_bits_T_4_cmd_status_spie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_upie = _io_out_bits_T ? first_preload_cmd_cmd_status_upie : _io_out_bits_T_4_cmd_status_upie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mie = _io_out_bits_T ? first_preload_cmd_cmd_status_mie : _io_out_bits_T_4_cmd_status_mie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_hie = _io_out_bits_T ? first_preload_cmd_cmd_status_hie : _io_out_bits_T_4_cmd_status_hie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sie = _io_out_bits_T ? first_preload_cmd_cmd_status_sie : _io_out_bits_T_4_cmd_status_sie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_uie = _io_out_bits_T ? first_preload_cmd_cmd_status_uie : _io_out_bits_T_4_cmd_status_uie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_rob_id_valid = ~_io_out_bits_T & _io_out_bits_T_4_rob_id_valid; // @[Mux.scala:126:16] assign _io_out_bits_T_5_rob_id_bits = _io_out_bits_T ? first_preload_cmd_rob_id_bits : _io_out_bits_T_4_rob_id_bits; // @[Mux.scala:126:16] assign _io_out_bits_T_5_from_matmul_fsm = _io_out_bits_T ? first_preload_cmd_from_matmul_fsm : _io_out_bits_T_4_from_matmul_fsm; // @[Mux.scala:126:16] assign _io_out_bits_T_5_from_conv_fsm = _io_out_bits_T ? first_preload_cmd_from_conv_fsm : _io_out_bits_T_4_from_conv_fsm; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_funct_0 = _io_out_bits_T_5_cmd_inst_funct; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_rs2_0 = _io_out_bits_T_5_cmd_inst_rs2; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_rs1_0 = _io_out_bits_T_5_cmd_inst_rs1; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_xd_0 = _io_out_bits_T_5_cmd_inst_xd; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_xs1_0 = _io_out_bits_T_5_cmd_inst_xs1; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_xs2_0 = _io_out_bits_T_5_cmd_inst_xs2; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_rd_0 = _io_out_bits_T_5_cmd_inst_rd; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_opcode_0 = _io_out_bits_T_5_cmd_inst_opcode; // @[Mux.scala:126:16] assign io_out_bits_cmd_rs1_0 = _io_out_bits_T_5_cmd_rs1; // @[Mux.scala:126:16] assign io_out_bits_cmd_rs2_0 = _io_out_bits_T_5_cmd_rs2; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_debug_0 = _io_out_bits_T_5_cmd_status_debug; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_cease_0 = _io_out_bits_T_5_cmd_status_cease; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_wfi_0 = _io_out_bits_T_5_cmd_status_wfi; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_isa_0 = _io_out_bits_T_5_cmd_status_isa; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_dprv_0 = _io_out_bits_T_5_cmd_status_dprv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_dv_0 = _io_out_bits_T_5_cmd_status_dv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_prv_0 = _io_out_bits_T_5_cmd_status_prv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_v_0 = _io_out_bits_T_5_cmd_status_v; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sd_0 = _io_out_bits_T_5_cmd_status_sd; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_zero2_0 = _io_out_bits_T_5_cmd_status_zero2; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mpv_0 = _io_out_bits_T_5_cmd_status_mpv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_gva_0 = _io_out_bits_T_5_cmd_status_gva; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mbe_0 = _io_out_bits_T_5_cmd_status_mbe; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sbe_0 = _io_out_bits_T_5_cmd_status_sbe; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sxl_0 = _io_out_bits_T_5_cmd_status_sxl; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_uxl_0 = _io_out_bits_T_5_cmd_status_uxl; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sd_rv32_0 = _io_out_bits_T_5_cmd_status_sd_rv32; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_zero1_0 = _io_out_bits_T_5_cmd_status_zero1; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_tsr_0 = _io_out_bits_T_5_cmd_status_tsr; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_tw_0 = _io_out_bits_T_5_cmd_status_tw; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_tvm_0 = _io_out_bits_T_5_cmd_status_tvm; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mxr_0 = _io_out_bits_T_5_cmd_status_mxr; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sum_0 = _io_out_bits_T_5_cmd_status_sum; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mprv_0 = _io_out_bits_T_5_cmd_status_mprv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_xs_0 = _io_out_bits_T_5_cmd_status_xs; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_fs_0 = _io_out_bits_T_5_cmd_status_fs; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mpp_0 = _io_out_bits_T_5_cmd_status_mpp; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_vs_0 = _io_out_bits_T_5_cmd_status_vs; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_spp_0 = _io_out_bits_T_5_cmd_status_spp; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mpie_0 = _io_out_bits_T_5_cmd_status_mpie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_ube_0 = _io_out_bits_T_5_cmd_status_ube; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_spie_0 = _io_out_bits_T_5_cmd_status_spie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_upie_0 = _io_out_bits_T_5_cmd_status_upie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mie_0 = _io_out_bits_T_5_cmd_status_mie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_hie_0 = _io_out_bits_T_5_cmd_status_hie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sie_0 = _io_out_bits_T_5_cmd_status_sie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_uie_0 = _io_out_bits_T_5_cmd_status_uie; // @[Mux.scala:126:16] assign io_out_bits_rob_id_valid_0 = _io_out_bits_T_5_rob_id_valid; // @[Mux.scala:126:16] assign io_out_bits_rob_id_bits_0 = _io_out_bits_T_5_rob_id_bits; // @[Mux.scala:126:16] assign io_out_bits_from_matmul_fsm_0 = _io_out_bits_T_5_from_matmul_fsm; // @[Mux.scala:126:16] assign io_out_bits_from_conv_fsm_0 = _io_out_bits_T_5_from_conv_fsm; // @[Mux.scala:126:16] wire _q_io_deq_pop_T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] wire _q_io_deq_pop_T_2 = ~_q_io_deq_pop_T_1; // @[TransposePreloadUnroller.scala:67:{31,47}] wire _q_io_deq_pop_T_3 = _q_io_deq_pop_T & _q_io_deq_pop_T_2; // @[Decoupled.scala:51:35] wire _q_io_deq_pop_T_4 = state != 2'h1; // @[TransposePreloadUnroller.scala:25:22, :58:12, :67:75] wire _q_io_deq_pop_T_5 = _q_io_deq_pop_T_3 & _q_io_deq_pop_T_4; // @[TransposePreloadUnroller.scala:67:{28,66,75}] wire _q_io_deq_pop_T_6 = _q_io_deq_pop_T_5; // @[TransposePreloadUnroller.scala:67:{15,66}] wire set_only_strides = _q_io_deq_bits_0_cmd_rs1[7]; // @[TransposePreloadUnroller.scala:71:45] wire _b_transposed_and_ws_T = _q_io_deq_bits_0_cmd_rs1[2]; // @[TransposePreloadUnroller.scala:73:79] wire _b_transposed_and_ws_T_1 = _b_transposed_and_ws_T; // @[TransposePreloadUnroller.scala:73:{79,83}] wire _b_transposed_and_ws_T_3 = _q_io_deq_bits_0_cmd_rs1[9]; // @[TransposePreloadUnroller.scala:73:123] wire _b_transposed_and_ws_T_4 = _b_transposed_and_ws_T_3; // @[TransposePreloadUnroller.scala:73:{105,123}] wire [1:0] _state_T_3 = {_state_T_1, 1'h0}; // @[TransposePreloadUnroller.scala:78:22] wire [1:0] _state_T_4 = _state_T ? 2'h1 : _state_T_3; // @[TransposePreloadUnroller.scala:58:12, :78:22] assign io_counter_event_signal_44 = \|state; // @[TransposePreloadUnroller.scala:9:7, :25:22, :83:94] always @(posedge clock) begin // @[TransposePreloadUnroller.scala:9:7] if (reset) // @[TransposePreloadUnroller.scala:9:7] state <= 2'h0; // @[TransposePreloadUnroller.scala:25:22] else if (~_q_io_deq_pop_T \| is_config) begin // @[Decoupled.scala:51:35] end else if (_T_2) // @[TransposePreloadUnroller.scala:62:20] state <= 2'h1; // @[TransposePreloadUnroller.scala:25:22, :58:12] else if (\|state) // @[TransposePreloadUnroller.scala:25:22, :77:23] state <= _state_T_4; // @[TransposePreloadUnroller.scala:25:22, :78:22] if (_q_io_deq_pop_T & is_config & ~set_only_strides) // @[Decoupled.scala:51:35] b_transposed_and_ws <= _b_transposed_and_ws_T_4; // @[TransposePreloadUnroller.scala:37:32, :73:105] always @(posedge) MultiHeadedQueue q ( // @[MultiHeadedQueue.scala:53:19] .clock (clock), .reset (reset), .io_enq_ready (io_in_ready_0), .io_enq_valid (io_in_valid_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_funct (io_in_bits_cmd_inst_funct_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_rs2 (io_in_bits_cmd_inst_rs2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_rs1 (io_in_bits_cmd_inst_rs1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_xd (io_in_bits_cmd_inst_xd_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_xs1 (io_in_bits_cmd_inst_xs1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_xs2 (io_in_bits_cmd_inst_xs2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_rd (io_in_bits_cmd_inst_rd_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_opcode (io_in_bits_cmd_inst_opcode_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_rs1 (io_in_bits_cmd_rs1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_rs2 (io_in_bits_cmd_rs2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_debug (io_in_bits_cmd_status_debug_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_cease (io_in_bits_cmd_status_cease_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_wfi (io_in_bits_cmd_status_wfi_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_isa (io_in_bits_cmd_status_isa_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_dprv (io_in_bits_cmd_status_dprv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_dv (io_in_bits_cmd_status_dv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_prv (io_in_bits_cmd_status_prv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_v (io_in_bits_cmd_status_v_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sd (io_in_bits_cmd_status_sd_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_zero2 (io_in_bits_cmd_status_zero2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mpv (io_in_bits_cmd_status_mpv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_gva (io_in_bits_cmd_status_gva_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mbe (io_in_bits_cmd_status_mbe_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sbe (io_in_bits_cmd_status_sbe_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sxl (io_in_bits_cmd_status_sxl_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_uxl (io_in_bits_cmd_status_uxl_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sd_rv32 (io_in_bits_cmd_status_sd_rv32_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_zero1 (io_in_bits_cmd_status_zero1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_tsr (io_in_bits_cmd_status_tsr_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_tw (io_in_bits_cmd_status_tw_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_tvm (io_in_bits_cmd_status_tvm_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mxr (io_in_bits_cmd_status_mxr_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sum (io_in_bits_cmd_status_sum_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mprv (io_in_bits_cmd_status_mprv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_xs (io_in_bits_cmd_status_xs_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_fs (io_in_bits_cmd_status_fs_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mpp (io_in_bits_cmd_status_mpp_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_vs (io_in_bits_cmd_status_vs_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_spp (io_in_bits_cmd_status_spp_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mpie (io_in_bits_cmd_status_mpie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_ube (io_in_bits_cmd_status_ube_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_spie (io_in_bits_cmd_status_spie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_upie (io_in_bits_cmd_status_upie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mie (io_in_bits_cmd_status_mie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_hie (io_in_bits_cmd_status_hie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sie (io_in_bits_cmd_status_sie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_uie (io_in_bits_cmd_status_uie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_rob_id_bits (io_in_bits_rob_id_bits_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_from_matmul_fsm (io_in_bits_from_matmul_fsm_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_from_conv_fsm (io_in_bits_from_conv_fsm_0), // @[TransposePreloadUnroller.scala:9:7] .io_deq_valid_0 (_q_io_deq_valid_0), .io_deq_valid_1 (_q_io_deq_valid_1), .io_deq_bits_0_cmd_inst_funct (_q_io_deq_bits_0_cmd_inst_funct), .io_deq_bits_0_cmd_inst_rs2 (_q_io_deq_bits_0_cmd_inst_rs2), .io_deq_bits_0_cmd_inst_rs1 (_q_io_deq_bits_0_cmd_inst_rs1), .io_deq_bits_0_cmd_inst_xd (_q_io_deq_bits_0_cmd_inst_xd), .io_deq_bits_0_cmd_inst_xs1 (_q_io_deq_bits_0_cmd_inst_xs1), .io_deq_bits_0_cmd_inst_xs2 (_q_io_deq_bits_0_cmd_inst_xs2), .io_deq_bits_0_cmd_inst_rd (_q_io_deq_bits_0_cmd_inst_rd), .io_deq_bits_0_cmd_inst_opcode (_q_io_deq_bits_0_cmd_inst_opcode), .io_deq_bits_0_cmd_rs1 (_q_io_deq_bits_0_cmd_rs1), .io_deq_bits_0_cmd_rs2 (_q_io_deq_bits_0_cmd_rs2), .io_deq_bits_0_cmd_status_debug (_q_io_deq_bits_0_cmd_status_debug), .io_deq_bits_0_cmd_status_cease (_q_io_deq_bits_0_cmd_status_cease), .io_deq_bits_0_cmd_status_wfi (_q_io_deq_bits_0_cmd_status_wfi), .io_deq_bits_0_cmd_status_isa (_q_io_deq_bits_0_cmd_status_isa), .io_deq_bits_0_cmd_status_dprv (_q_io_deq_bits_0_cmd_status_dprv), .io_deq_bits_0_cmd_status_dv (_q_io_deq_bits_0_cmd_status_dv), .io_deq_bits_0_cmd_status_prv (_q_io_deq_bits_0_cmd_status_prv), .io_deq_bits_0_cmd_status_v (_q_io_deq_bits_0_cmd_status_v), .io_deq_bits_0_cmd_status_sd (_q_io_deq_bits_0_cmd_status_sd), .io_deq_bits_0_cmd_status_zero2 (_q_io_deq_bits_0_cmd_status_zero2), .io_deq_bits_0_cmd_status_mpv (_q_io_deq_bits_0_cmd_status_mpv), .io_deq_bits_0_cmd_status_gva (_q_io_deq_bits_0_cmd_status_gva), .io_deq_bits_0_cmd_status_mbe (_q_io_deq_bits_0_cmd_status_mbe), .io_deq_bits_0_cmd_status_sbe (_q_io_deq_bits_0_cmd_status_sbe), .io_deq_bits_0_cmd_status_sxl (_q_io_deq_bits_0_cmd_status_sxl), .io_deq_bits_0_cmd_status_uxl (_q_io_deq_bits_0_cmd_status_uxl), .io_deq_bits_0_cmd_status_sd_rv32 (_q_io_deq_bits_0_cmd_status_sd_rv32), .io_deq_bits_0_cmd_status_zero1 (_q_io_deq_bits_0_cmd_status_zero1), .io_deq_bits_0_cmd_status_tsr (_q_io_deq_bits_0_cmd_status_tsr), .io_deq_bits_0_cmd_status_tw (_q_io_deq_bits_0_cmd_status_tw), .io_deq_bits_0_cmd_status_tvm (_q_io_deq_bits_0_cmd_status_tvm), .io_deq_bits_0_cmd_status_mxr (_q_io_deq_bits_0_cmd_status_mxr), .io_deq_bits_0_cmd_status_sum (_q_io_deq_bits_0_cmd_status_sum), .io_deq_bits_0_cmd_status_mprv (_q_io_deq_bits_0_cmd_status_mprv), .io_deq_bits_0_cmd_status_xs (_q_io_deq_bits_0_cmd_status_xs), .io_deq_bits_0_cmd_status_fs (_q_io_deq_bits_0_cmd_status_fs), .io_deq_bits_0_cmd_status_mpp (_q_io_deq_bits_0_cmd_status_mpp), .io_deq_bits_0_cmd_status_vs (_q_io_deq_bits_0_cmd_status_vs), .io_deq_bits_0_cmd_status_spp (_q_io_deq_bits_0_cmd_status_spp), .io_deq_bits_0_cmd_status_mpie (_q_io_deq_bits_0_cmd_status_mpie), .io_deq_bits_0_cmd_status_ube (_q_io_deq_bits_0_cmd_status_ube), .io_deq_bits_0_cmd_status_spie (_q_io_deq_bits_0_cmd_status_spie), .io_deq_bits_0_cmd_status_upie (_q_io_deq_bits_0_cmd_status_upie), .io_deq_bits_0_cmd_status_mie (_q_io_deq_bits_0_cmd_status_mie), .io_deq_bits_0_cmd_status_hie (_q_io_deq_bits_0_cmd_status_hie), .io_deq_bits_0_cmd_status_sie (_q_io_deq_bits_0_cmd_status_sie), .io_deq_bits_0_cmd_status_uie (_q_io_deq_bits_0_cmd_status_uie), .io_deq_bits_0_rob_id_bits (_q_io_deq_bits_0_rob_id_bits), .io_deq_bits_0_from_matmul_fsm (_q_io_deq_bits_0_from_matmul_fsm), .io_deq_bits_0_from_conv_fsm (_q_io_deq_bits_0_from_conv_fsm), .io_deq_bits_1_cmd_inst_funct (_q_io_deq_bits_1_cmd_inst_funct), .io_deq_bits_1_cmd_inst_xd (first_compute_cmd_cmd_inst_xd), .io_deq_bits_1_cmd_inst_xs1 (first_compute_cmd_cmd_inst_xs1), .io_deq_bits_1_cmd_inst_xs2 (first_compute_cmd_cmd_inst_xs2), .io_deq_bits_1_cmd_inst_rd (first_compute_cmd_cmd_inst_rd), .io_deq_bits_1_cmd_inst_opcode (first_compute_cmd_cmd_inst_opcode), .io_deq_bits_1_cmd_rs1 (_q_io_deq_bits_1_cmd_rs1), .io_deq_bits_1_cmd_rs2 (_q_io_deq_bits_1_cmd_rs2), .io_deq_bits_1_cmd_status_debug (first_compute_cmd_cmd_status_debug), .io_deq_bits_1_cmd_status_cease (first_compute_cmd_cmd_status_cease), .io_deq_bits_1_cmd_status_wfi (first_compute_cmd_cmd_status_wfi), .io_deq_bits_1_cmd_status_isa (first_compute_cmd_cmd_status_isa), .io_deq_bits_1_cmd_status_dprv (first_compute_cmd_cmd_status_dprv), .io_deq_bits_1_cmd_status_dv (first_compute_cmd_cmd_status_dv), .io_deq_bits_1_cmd_status_prv (first_compute_cmd_cmd_status_prv), .io_deq_bits_1_cmd_status_v (first_compute_cmd_cmd_status_v), .io_deq_bits_1_cmd_status_sd (first_compute_cmd_cmd_status_sd), .io_deq_bits_1_cmd_status_zero2 (first_compute_cmd_cmd_status_zero2), .io_deq_bits_1_cmd_status_mpv (first_compute_cmd_cmd_status_mpv), .io_deq_bits_1_cmd_status_gva (first_compute_cmd_cmd_status_gva), .io_deq_bits_1_cmd_status_mbe (first_compute_cmd_cmd_status_mbe), .io_deq_bits_1_cmd_status_sbe (first_compute_cmd_cmd_status_sbe), .io_deq_bits_1_cmd_status_sxl (first_compute_cmd_cmd_status_sxl), .io_deq_bits_1_cmd_status_uxl (first_compute_cmd_cmd_status_uxl), .io_deq_bits_1_cmd_status_sd_rv32 (first_compute_cmd_cmd_status_sd_rv32), .io_deq_bits_1_cmd_status_zero1 (first_compute_cmd_cmd_status_zero1), .io_deq_bits_1_cmd_status_tsr (first_compute_cmd_cmd_status_tsr), .io_deq_bits_1_cmd_status_tw (first_compute_cmd_cmd_status_tw), .io_deq_bits_1_cmd_status_tvm (first_compute_cmd_cmd_status_tvm), .io_deq_bits_1_cmd_status_mxr (first_compute_cmd_cmd_status_mxr), .io_deq_bits_1_cmd_status_sum (first_compute_cmd_cmd_status_sum), .io_deq_bits_1_cmd_status_mprv (first_compute_cmd_cmd_status_mprv), .io_deq_bits_1_cmd_status_xs (first_compute_cmd_cmd_status_xs), .io_deq_bits_1_cmd_status_fs (first_compute_cmd_cmd_status_fs), .io_deq_bits_1_cmd_status_mpp (first_compute_cmd_cmd_status_mpp), .io_deq_bits_1_cmd_status_vs (first_compute_cmd_cmd_status_vs), .io_deq_bits_1_cmd_status_spp (first_compute_cmd_cmd_status_spp), .io_deq_bits_1_cmd_status_mpie (first_compute_cmd_cmd_status_mpie), .io_deq_bits_1_cmd_status_ube (first_compute_cmd_cmd_status_ube), .io_deq_bits_1_cmd_status_spie (first_compute_cmd_cmd_status_spie), .io_deq_bits_1_cmd_status_upie (first_compute_cmd_cmd_status_upie), .io_deq_bits_1_cmd_status_mie (first_compute_cmd_cmd_status_mie), .io_deq_bits_1_cmd_status_hie (first_compute_cmd_cmd_status_hie), .io_deq_bits_1_cmd_status_sie (first_compute_cmd_cmd_status_sie), .io_deq_bits_1_cmd_status_uie (first_compute_cmd_cmd_status_uie), .io_deq_bits_1_rob_id_bits (first_compute_cmd_rob_id_bits), .io_deq_bits_1_from_matmul_fsm (first_compute_cmd_from_matmul_fsm), .io_deq_bits_1_from_conv_fsm (first_compute_cmd_from_conv_fsm), .io_deq_pop (_q_io_deq_pop_T_6) // @[TransposePreloadUnroller.scala:67:15] ); // @[MultiHeadedQueue.scala:53:19] assign first_preload_cmd_cmd_inst_funct = _q_io_deq_bits_0_cmd_inst_funct; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_rs2 = _q_io_deq_bits_0_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_rs1 = _q_io_deq_bits_0_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_xd = _q_io_deq_bits_0_cmd_inst_xd; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_xs1 = _q_io_deq_bits_0_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_xs2 = _q_io_deq_bits_0_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_rd = _q_io_deq_bits_0_cmd_inst_rd; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_opcode = _q_io_deq_bits_0_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_rs1 = _q_io_deq_bits_0_cmd_rs1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_debug = _q_io_deq_bits_0_cmd_status_debug; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_cease = _q_io_deq_bits_0_cmd_status_cease; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_wfi = _q_io_deq_bits_0_cmd_status_wfi; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_isa = _q_io_deq_bits_0_cmd_status_isa; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_dprv = _q_io_deq_bits_0_cmd_status_dprv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_dv = _q_io_deq_bits_0_cmd_status_dv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_prv = _q_io_deq_bits_0_cmd_status_prv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_v = _q_io_deq_bits_0_cmd_status_v; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sd = _q_io_deq_bits_0_cmd_status_sd; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_zero2 = _q_io_deq_bits_0_cmd_status_zero2; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mpv = _q_io_deq_bits_0_cmd_status_mpv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_gva = _q_io_deq_bits_0_cmd_status_gva; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mbe = _q_io_deq_bits_0_cmd_status_mbe; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sbe = _q_io_deq_bits_0_cmd_status_sbe; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sxl = _q_io_deq_bits_0_cmd_status_sxl; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_uxl = _q_io_deq_bits_0_cmd_status_uxl; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sd_rv32 = _q_io_deq_bits_0_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_zero1 = _q_io_deq_bits_0_cmd_status_zero1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_tsr = _q_io_deq_bits_0_cmd_status_tsr; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_tw = _q_io_deq_bits_0_cmd_status_tw; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_tvm = _q_io_deq_bits_0_cmd_status_tvm; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mxr = _q_io_deq_bits_0_cmd_status_mxr; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sum = _q_io_deq_bits_0_cmd_status_sum; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mprv = _q_io_deq_bits_0_cmd_status_mprv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_xs = _q_io_deq_bits_0_cmd_status_xs; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_fs = _q_io_deq_bits_0_cmd_status_fs; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mpp = _q_io_deq_bits_0_cmd_status_mpp; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_vs = _q_io_deq_bits_0_cmd_status_vs; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_spp = _q_io_deq_bits_0_cmd_status_spp; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mpie = _q_io_deq_bits_0_cmd_status_mpie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_ube = _q_io_deq_bits_0_cmd_status_ube; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_spie = _q_io_deq_bits_0_cmd_status_spie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_upie = _q_io_deq_bits_0_cmd_status_upie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mie = _q_io_deq_bits_0_cmd_status_mie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_hie = _q_io_deq_bits_0_cmd_status_hie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sie = _q_io_deq_bits_0_cmd_status_sie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_uie = _q_io_deq_bits_0_cmd_status_uie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_rob_id_bits = _q_io_deq_bits_0_rob_id_bits; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_from_matmul_fsm = _q_io_deq_bits_0_from_matmul_fsm; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_from_conv_fsm = _q_io_deq_bits_0_from_conv_fsm; // @[TransposePreloadUnroller.scala:40:35] assign first_compute_cmd_cmd_rs1 = _q_io_deq_bits_1_cmd_rs1; // @[TransposePreloadUnroller.scala:44:35] assign first_compute_cmd_cmd_rs2 = _q_io_deq_bits_1_cmd_rs2; // @[TransposePreloadUnroller.scala:44:35] assign second_preload_cmd_cmd_inst_funct = _q_io_deq_bits_0_cmd_inst_funct; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_rs2 = _q_io_deq_bits_0_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_rs1 = _q_io_deq_bits_0_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_xd = _q_io_deq_bits_0_cmd_inst_xd; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_xs1 = _q_io_deq_bits_0_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_xs2 = _q_io_deq_bits_0_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_rd = _q_io_deq_bits_0_cmd_inst_rd; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_opcode = _q_io_deq_bits_0_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_rs2 = _q_io_deq_bits_0_cmd_rs2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_debug = _q_io_deq_bits_0_cmd_status_debug; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_cease = _q_io_deq_bits_0_cmd_status_cease; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_wfi = _q_io_deq_bits_0_cmd_status_wfi; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_isa = _q_io_deq_bits_0_cmd_status_isa; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_dprv = _q_io_deq_bits_0_cmd_status_dprv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_dv = _q_io_deq_bits_0_cmd_status_dv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_prv = _q_io_deq_bits_0_cmd_status_prv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_v = _q_io_deq_bits_0_cmd_status_v; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sd = _q_io_deq_bits_0_cmd_status_sd; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_zero2 = _q_io_deq_bits_0_cmd_status_zero2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mpv = _q_io_deq_bits_0_cmd_status_mpv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_gva = _q_io_deq_bits_0_cmd_status_gva; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mbe = _q_io_deq_bits_0_cmd_status_mbe; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sbe = _q_io_deq_bits_0_cmd_status_sbe; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sxl = _q_io_deq_bits_0_cmd_status_sxl; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_uxl = _q_io_deq_bits_0_cmd_status_uxl; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sd_rv32 = _q_io_deq_bits_0_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_zero1 = _q_io_deq_bits_0_cmd_status_zero1; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_tsr = _q_io_deq_bits_0_cmd_status_tsr; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_tw = _q_io_deq_bits_0_cmd_status_tw; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_tvm = _q_io_deq_bits_0_cmd_status_tvm; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mxr = _q_io_deq_bits_0_cmd_status_mxr; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sum = _q_io_deq_bits_0_cmd_status_sum; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mprv = _q_io_deq_bits_0_cmd_status_mprv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_xs = _q_io_deq_bits_0_cmd_status_xs; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_fs = _q_io_deq_bits_0_cmd_status_fs; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mpp = _q_io_deq_bits_0_cmd_status_mpp; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_vs = _q_io_deq_bits_0_cmd_status_vs; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_spp = _q_io_deq_bits_0_cmd_status_spp; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mpie = _q_io_deq_bits_0_cmd_status_mpie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_ube = _q_io_deq_bits_0_cmd_status_ube; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_spie = _q_io_deq_bits_0_cmd_status_spie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_upie = _q_io_deq_bits_0_cmd_status_upie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mie = _q_io_deq_bits_0_cmd_status_mie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_hie = _q_io_deq_bits_0_cmd_status_hie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sie = _q_io_deq_bits_0_cmd_status_sie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_uie = _q_io_deq_bits_0_cmd_status_uie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_rob_id_bits = _q_io_deq_bits_0_rob_id_bits; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_from_matmul_fsm = _q_io_deq_bits_0_from_matmul_fsm; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_from_conv_fsm = _q_io_deq_bits_0_from_conv_fsm; // @[TransposePreloadUnroller.scala:50:36] assign io_in_ready = io_in_ready_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_valid = io_out_valid_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_funct = io_out_bits_cmd_inst_funct_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_rs2 = io_out_bits_cmd_inst_rs2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_rs1 = io_out_bits_cmd_inst_rs1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_xd = io_out_bits_cmd_inst_xd_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_xs1 = io_out_bits_cmd_inst_xs1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_xs2 = io_out_bits_cmd_inst_xs2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_rd = io_out_bits_cmd_inst_rd_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_opcode = io_out_bits_cmd_inst_opcode_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_rs1 = io_out_bits_cmd_rs1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_rs2 = io_out_bits_cmd_rs2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_debug = io_out_bits_cmd_status_debug_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_cease = io_out_bits_cmd_status_cease_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_wfi = io_out_bits_cmd_status_wfi_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_isa = io_out_bits_cmd_status_isa_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_dprv = io_out_bits_cmd_status_dprv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_dv = io_out_bits_cmd_status_dv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_prv = io_out_bits_cmd_status_prv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_v = io_out_bits_cmd_status_v_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sd = io_out_bits_cmd_status_sd_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_zero2 = io_out_bits_cmd_status_zero2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mpv = io_out_bits_cmd_status_mpv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_gva = io_out_bits_cmd_status_gva_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mbe = io_out_bits_cmd_status_mbe_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sbe = io_out_bits_cmd_status_sbe_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sxl = io_out_bits_cmd_status_sxl_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_uxl = io_out_bits_cmd_status_uxl_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sd_rv32 = io_out_bits_cmd_status_sd_rv32_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_zero1 = io_out_bits_cmd_status_zero1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_tsr = io_out_bits_cmd_status_tsr_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_tw = io_out_bits_cmd_status_tw_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_tvm = io_out_bits_cmd_status_tvm_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mxr = io_out_bits_cmd_status_mxr_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sum = io_out_bits_cmd_status_sum_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mprv = io_out_bits_cmd_status_mprv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_xs = io_out_bits_cmd_status_xs_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_fs = io_out_bits_cmd_status_fs_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mpp = io_out_bits_cmd_status_mpp_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_vs = io_out_bits_cmd_status_vs_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_spp = io_out_bits_cmd_status_spp_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mpie = io_out_bits_cmd_status_mpie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_ube = io_out_bits_cmd_status_ube_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_spie = io_out_bits_cmd_status_spie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_upie = io_out_bits_cmd_status_upie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mie = io_out_bits_cmd_status_mie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_hie = io_out_bits_cmd_status_hie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sie = io_out_bits_cmd_status_sie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_uie = io_out_bits_cmd_status_uie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_rob_id_valid = io_out_bits_rob_id_valid_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_rob_id_bits = io_out_bits_rob_id_bits_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_from_matmul_fsm = io_out_bits_from_matmul_fsm_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_from_conv_fsm = io_out_bits_from_conv_fsm_0; // @[TransposePreloadUnroller.scala:9:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SodorMasterAdapter : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip dport : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}} inst buffer of TLBuffer_a32d32s1k1z4u connect buffer.clock, clock connect buffer.reset, reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready connect nodeOut, nodeIn wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect buffer.auto.in, masterNodeOut connect buffer.auto.out.d, nodeIn.d connect nodeIn.a.bits, buffer.auto.out.a.bits connect nodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, nodeIn.a.ready connect auto.out, nodeOut regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg a_address_reg : UInt<32>, clock reg a_signed_reg : UInt<1>, clock reg req_address_reg : UInt<32>, clock reg req_size_reg : UInt<2>, clock reg req_data_reg : UInt<32>, clock node _a_signed_T = sub(io.dport.req.bits.typ, UInt<1>(0h1)) node _a_signed_T_1 = tail(_a_signed_T, 1) node _a_signed_T_2 = bits(_a_signed_T_1, 2, 2) node a_signed = not(_a_signed_T_2) node _a_size_T = sub(io.dport.req.bits.typ, UInt<1>(0h1)) node _a_size_T_1 = tail(_a_size_T, 1) node a_size = bits(_a_size_T_1, 1, 0) node _T = eq(state, UInt<2>(0h0)) node _T_1 = and(_T, io.dport.req.valid) when _T_1 : connect state, UInt<2>(0h1) connect req_address_reg, io.dport.req.bits.addr connect req_size_reg, a_size connect req_data_reg, io.dport.req.bits.data node _T_2 = eq(state, UInt<2>(0h1)) node _T_3 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) node _T_4 = and(_T_2, _T_3) when _T_4 : connect state, UInt<2>(0h2) node _T_5 = eq(state, UInt<2>(0h2)) node _T_6 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _T_7 = and(_T_5, _T_6) when _T_7 : connect state, UInt<2>(0h0) node _masterNodeOut_a_valid_T = eq(state, UInt<2>(0h1)) connect masterNodeOut.a.valid, _masterNodeOut_a_valid_T connect masterNodeOut.d.ready, UInt<1>(0h1) node _io_dport_req_ready_T = eq(state, UInt<2>(0h0)) connect io.dport.req.ready, _io_dport_req_ready_T connect io.dport.resp.valid, masterNodeOut.d.valid node _T_8 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_8 : connect a_address_reg, io.dport.req.bits.addr connect a_signed_reg, a_size node _legal_T = leq(UInt<1>(0h0), req_size_reg) node _legal_T_1 = leq(req_size_reg, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(req_address_reg, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h8a113000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), req_size_reg) node _legal_T_11 = leq(req_size_reg, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(req_address_reg, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h8a112000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(req_address_reg, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h8a110000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(req_address_reg, UInt<21>(0h100000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h8a103000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(req_address_reg, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h8a110000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(req_address_reg, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h88000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(req_address_reg, UInt<32>(0h80000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h8a100000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = or(_legal_T_18, _legal_T_23) node _legal_T_45 = or(_legal_T_44, _legal_T_28) node _legal_T_46 = or(_legal_T_45, _legal_T_33) node _legal_T_47 = or(_legal_T_46, _legal_T_38) node _legal_T_48 = or(_legal_T_47, _legal_T_43) node _legal_T_49 = and(_legal_T_13, _legal_T_48) node _legal_T_50 = or(UInt<1>(0h0), _legal_T_9) node legal_get = or(_legal_T_50, _legal_T_49) wire get_bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} connect get_bundle.opcode, UInt<3>(0h4) connect get_bundle.param, UInt<1>(0h0) connect get_bundle.size, req_size_reg connect get_bundle.source, UInt<1>(0h0) connect get_bundle.address, req_address_reg node _a_mask_sizeOH_T = or(req_size_reg, UInt<2>(0h0)) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_T, 0, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 1, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_0_1 = geq(req_size_reg, UInt<2>(0h2)) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(req_address_reg, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(req_address_reg, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_hi = cat(a_mask_acc_3, a_mask_acc_2) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect get_bundle.mask, _a_mask_T invalidate get_bundle.data connect get_bundle.corrupt, UInt<1>(0h0) node _legal_T_51 = leq(UInt<1>(0h0), req_size_reg) node _legal_T_52 = leq(req_size_reg, UInt<4>(0hc)) node _legal_T_53 = and(_legal_T_51, _legal_T_52) node _legal_T_54 = or(UInt<1>(0h0), _legal_T_53) node _legal_T_55 = xor(req_address_reg, UInt<14>(0h3000)) node _legal_T_56 = cvt(_legal_T_55) node _legal_T_57 = and(_legal_T_56, asSInt(UInt<33>(0h8a113000))) node _legal_T_58 = asSInt(_legal_T_57) node _legal_T_59 = eq(_legal_T_58, asSInt(UInt<1>(0h0))) node _legal_T_60 = and(_legal_T_54, _legal_T_59) node _legal_T_61 = leq(UInt<1>(0h0), req_size_reg) node _legal_T_62 = leq(req_size_reg, UInt<3>(0h6)) node _legal_T_63 = and(_legal_T_61, _legal_T_62) node _legal_T_64 = or(UInt<1>(0h0), _legal_T_63) node _legal_T_65 = xor(req_address_reg, UInt<1>(0h0)) node _legal_T_66 = cvt(_legal_T_65) node _legal_T_67 = and(_legal_T_66, asSInt(UInt<33>(0h8a112000))) node _legal_T_68 = asSInt(_legal_T_67) node _legal_T_69 = eq(_legal_T_68, asSInt(UInt<1>(0h0))) node _legal_T_70 = xor(req_address_reg, UInt<21>(0h100000)) node _legal_T_71 = cvt(_legal_T_70) node _legal_T_72 = and(_legal_T_71, asSInt(UInt<33>(0h8a103000))) node _legal_T_73 = asSInt(_legal_T_72) node _legal_T_74 = eq(_legal_T_73, asSInt(UInt<1>(0h0))) node _legal_T_75 = xor(req_address_reg, UInt<26>(0h2000000)) node _legal_T_76 = cvt(_legal_T_75) node _legal_T_77 = and(_legal_T_76, asSInt(UInt<33>(0h8a110000))) node _legal_T_78 = asSInt(_legal_T_77) node _legal_T_79 = eq(_legal_T_78, asSInt(UInt<1>(0h0))) node _legal_T_80 = xor(req_address_reg, UInt<28>(0h8000000)) node _legal_T_81 = cvt(_legal_T_80) node _legal_T_82 = and(_legal_T_81, asSInt(UInt<33>(0h88000000))) node _legal_T_83 = asSInt(_legal_T_82) node _legal_T_84 = eq(_legal_T_83, asSInt(UInt<1>(0h0))) node _legal_T_85 = xor(req_address_reg, UInt<32>(0h80000000)) node _legal_T_86 = cvt(_legal_T_85) node _legal_T_87 = and(_legal_T_86, asSInt(UInt<33>(0h8a100000))) node _legal_T_88 = asSInt(_legal_T_87) node _legal_T_89 = eq(_legal_T_88, asSInt(UInt<1>(0h0))) node _legal_T_90 = or(_legal_T_69, _legal_T_74) node _legal_T_91 = or(_legal_T_90, _legal_T_79) node _legal_T_92 = or(_legal_T_91, _legal_T_84) node _legal_T_93 = or(_legal_T_92, _legal_T_89) node _legal_T_94 = and(_legal_T_64, _legal_T_93) node _legal_T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_96 = xor(req_address_reg, UInt<17>(0h10000)) node _legal_T_97 = cvt(_legal_T_96) node _legal_T_98 = and(_legal_T_97, asSInt(UInt<33>(0h8a110000))) node _legal_T_99 = asSInt(_legal_T_98) node _legal_T_100 = eq(_legal_T_99, asSInt(UInt<1>(0h0))) node _legal_T_101 = and(_legal_T_95, _legal_T_100) node _legal_T_102 = or(UInt<1>(0h0), _legal_T_60) node _legal_T_103 = or(_legal_T_102, _legal_T_94) node legal_put = or(_legal_T_103, _legal_T_101) wire put_bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} connect put_bundle.opcode, UInt<1>(0h0) connect put_bundle.param, UInt<1>(0h0) connect put_bundle.size, req_size_reg connect put_bundle.source, UInt<1>(0h0) connect put_bundle.address, req_address_reg node _a_mask_sizeOH_T_3 = or(req_size_reg, UInt<2>(0h0)) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_T_3, 0, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 1, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_0_1_1 = geq(req_size_reg, UInt<2>(0h2)) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(req_address_reg, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_nbit_1) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_bit_1) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_3) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(req_address_reg, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_4 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_4 = and(a_mask_size_1, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_0_1_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_5 = and(a_mask_size_1, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_0_1_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_6 = and(a_mask_size_1, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_1_1_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_7 = and(a_mask_size_1, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_1_1_1, _a_mask_acc_T_7) node a_mask_lo_1 = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_hi_1 = cat(a_mask_acc_7, a_mask_acc_6) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect put_bundle.mask, _a_mask_T_1 connect put_bundle.data, req_data_reg connect put_bundle.corrupt, UInt<1>(0h0) node _masterNodeOut_a_bits_T = eq(io.dport.req.bits.fcn, UInt<1>(0h0)) node _masterNodeOut_a_bits_T_1 = mux(_masterNodeOut_a_bits_T, get_bundle, put_bundle) connect masterNodeOut.a.bits, _masterNodeOut_a_bits_T_1 wire io_dport_resp_bits_data_size : UInt<2> connect io_dport_resp_bits_data_size, masterNodeOut.d.bits.size node _io_dport_resp_bits_data_shifted_T = bits(a_address_reg, 1, 1) node _io_dport_resp_bits_data_shifted_T_1 = bits(masterNodeOut.d.bits.data, 31, 16) node _io_dport_resp_bits_data_shifted_T_2 = bits(masterNodeOut.d.bits.data, 15, 0) node io_dport_resp_bits_data_shifted = mux(_io_dport_resp_bits_data_shifted_T, _io_dport_resp_bits_data_shifted_T_1, _io_dport_resp_bits_data_shifted_T_2) node io_dport_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_dport_resp_bits_data_zeroed = mux(io_dport_resp_bits_data_doZero, UInt<1>(0h0), io_dport_resp_bits_data_shifted) node _io_dport_resp_bits_data_T = eq(io_dport_resp_bits_data_size, UInt<1>(0h1)) node _io_dport_resp_bits_data_T_1 = or(_io_dport_resp_bits_data_T, io_dport_resp_bits_data_doZero) node _io_dport_resp_bits_data_T_2 = bits(io_dport_resp_bits_data_zeroed, 15, 15) node _io_dport_resp_bits_data_T_3 = and(a_signed_reg, _io_dport_resp_bits_data_T_2) node _io_dport_resp_bits_data_T_4 = mux(_io_dport_resp_bits_data_T_3, UInt<16>(0hffff), UInt<16>(0h0)) node _io_dport_resp_bits_data_T_5 = bits(masterNodeOut.d.bits.data, 31, 16) node _io_dport_resp_bits_data_T_6 = mux(_io_dport_resp_bits_data_T_1, _io_dport_resp_bits_data_T_4, _io_dport_resp_bits_data_T_5) node _io_dport_resp_bits_data_T_7 = cat(_io_dport_resp_bits_data_T_6, io_dport_resp_bits_data_zeroed) node _io_dport_resp_bits_data_shifted_T_3 = bits(a_address_reg, 0, 0) node _io_dport_resp_bits_data_shifted_T_4 = bits(_io_dport_resp_bits_data_T_7, 15, 8) node _io_dport_resp_bits_data_shifted_T_5 = bits(_io_dport_resp_bits_data_T_7, 7, 0) node io_dport_resp_bits_data_shifted_1 = mux(_io_dport_resp_bits_data_shifted_T_3, _io_dport_resp_bits_data_shifted_T_4, _io_dport_resp_bits_data_shifted_T_5) node io_dport_resp_bits_data_doZero_1 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_dport_resp_bits_data_zeroed_1 = mux(io_dport_resp_bits_data_doZero_1, UInt<1>(0h0), io_dport_resp_bits_data_shifted_1) node _io_dport_resp_bits_data_T_8 = eq(io_dport_resp_bits_data_size, UInt<1>(0h0)) node _io_dport_resp_bits_data_T_9 = or(_io_dport_resp_bits_data_T_8, io_dport_resp_bits_data_doZero_1) node _io_dport_resp_bits_data_T_10 = bits(io_dport_resp_bits_data_zeroed_1, 7, 7) node _io_dport_resp_bits_data_T_11 = and(a_signed_reg, _io_dport_resp_bits_data_T_10) node _io_dport_resp_bits_data_T_12 = mux(_io_dport_resp_bits_data_T_11, UInt<24>(0hffffff), UInt<24>(0h0)) node _io_dport_resp_bits_data_T_13 = bits(_io_dport_resp_bits_data_T_7, 31, 8) node _io_dport_resp_bits_data_T_14 = mux(_io_dport_resp_bits_data_T_9, _io_dport_resp_bits_data_T_12, _io_dport_resp_bits_data_T_13) node _io_dport_resp_bits_data_T_15 = cat(_io_dport_resp_bits_data_T_14, io_dport_resp_bits_data_zeroed_1) connect io.dport.resp.bits.data, _io_dport_resp_bits_data_T_15 node _legal_op_T = eq(io.dport.req.bits.fcn, UInt<1>(0h0)) node legal_op = mux(_legal_op_T, legal_get, legal_put) node resp_xp = or(masterNodeOut.d.bits.corrupt, masterNodeOut.d.bits.denied) node _T_9 = eq(masterNodeOut.a.valid, UInt<1>(0h0)) node _T_10 = or(legal_op, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed: Illegal operation\n at master_adapter.scala:101 assert(legal_op \| !tl_out.a.valid, \"Illegal operation\")\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = eq(resp_xp, UInt<1>(0h0)) node _T_15 = eq(masterNodeOut.d.valid, UInt<1>(0h0)) node _T_16 = or(_T_14, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: Responds exception\n at master_adapter.scala:102 assert(!resp_xp \| !tl_out.d.valid, \"Responds exception\")\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_62 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_63 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module SodorMasterAdapter( // @[master_adapter.scala:38:7] input clock, // @[master_adapter.scala:38:7] input reset, // @[master_adapter.scala:38:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_dport_req_ready, // @[master_adapter.scala:41:14] input io_dport_req_valid, // @[master_adapter.scala:41:14] input [31:0] io_dport_req_bits_addr, // @[master_adapter.scala:41:14] output io_dport_resp_valid, // @[master_adapter.scala:41:14] output [31:0] io_dport_resp_bits_data // @[master_adapter.scala:41:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[master_adapter.scala:38:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[master_adapter.scala:38:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[master_adapter.scala:38:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[master_adapter.scala:38:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[master_adapter.scala:38:7] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[master_adapter.scala:38:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[master_adapter.scala:38:7] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[master_adapter.scala:38:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[master_adapter.scala:38:7] wire io_dport_req_valid_0 = io_dport_req_valid; // @[master_adapter.scala:38:7] wire [31:0] io_dport_req_bits_addr_0 = io_dport_req_bits_addr; // @[master_adapter.scala:38:7] wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _a_signed_T_2 = 1'h1; // @[memory.scala:61:33] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _legal_T_51 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_52 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_53 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_54 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_61 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_62 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_64 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _masterNodeOut_a_bits_T = 1'h1; // @[master_adapter.scala:92:46] wire _legal_op_T = 1'h1; // @[master_adapter.scala:98:44] wire [23:0] _io_dport_resp_bits_data_T_12 = 24'h0; // @[AMOALU.scala:45:49] wire auto_out_d_bits_source = 1'h0; // @[master_adapter.scala:38:7] wire io_dport_req_bits_fcn = 1'h0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire a_signed = 1'h0; // @[memory.scala:61:21] wire get_bundle_source = 1'h0; // @[Edges.scala:460:17] wire get_bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire a_mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _legal_T_95 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_101 = 1'h0; // @[Parameters.scala:684:54] wire put_bundle_source = 1'h0; // @[Edges.scala:480:17] wire put_bundle_corrupt = 1'h0; // @[Edges.scala:480:17] wire a_mask_sizeOH_shiftAmount_1 = 1'h0; // @[OneHot.scala:64:49] wire a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_T_1_source = 1'h0; // @[master_adapter.scala:92:23] wire _masterNodeOut_a_bits_T_1_corrupt = 1'h0; // @[master_adapter.scala:92:23] wire io_dport_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _io_dport_resp_bits_data_T_3 = 1'h0; // @[AMOALU.scala:45:72] wire io_dport_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire _io_dport_resp_bits_data_T_11 = 1'h0; // @[AMOALU.scala:45:72] wire [15:0] _io_dport_resp_bits_data_T_4 = 16'h0; // @[AMOALU.scala:45:49] wire [31:0] io_dport_req_bits_data = 32'h0; // @[master_adapter.scala:38:7] wire [31:0] masterNodeOut_a_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] get_bundle_data = 32'h0; // @[Edges.scala:460:17] wire [31:0] put_bundle_data = 32'h0; // @[Edges.scala:480:17] wire [31:0] _masterNodeOut_a_bits_T_1_data = 32'h0; // @[master_adapter.scala:92:23] wire [3:0] masterNodeOut_a_bits_mask = 4'hF; // @[MixedNode.scala:542:17] wire [3:0] get_bundle_mask = 4'hF; // @[Edges.scala:460:17] wire [3:0] _a_mask_T = 4'hF; // @[Misc.scala:222:10] wire [3:0] put_bundle_mask = 4'hF; // @[Edges.scala:480:17] wire [3:0] _a_mask_T_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] _masterNodeOut_a_bits_T_1_mask = 4'hF; // @[master_adapter.scala:92:23] wire [3:0] masterNodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] get_bundle_size = 4'h2; // @[Edges.scala:460:17] wire [3:0] put_bundle_size = 4'h2; // @[Edges.scala:480:17] wire [3:0] _masterNodeOut_a_bits_T_1_size = 4'h2; // @[master_adapter.scala:92:23] wire [1:0] a_mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _a_mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] a_mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_mask_sizeOH_T_4 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _a_mask_sizeOH_T_5 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] a_mask_sizeOH_1 = 2'h1; // @[Misc.scala:202:81] wire [1:0] a_size = 2'h2; // @[memory.scala:60:30] wire [1:0] _a_mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] _a_mask_sizeOH_T_3 = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_dport_req_bits_typ = 3'h7; // @[master_adapter.scala:38:7] wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] get_bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_bundle_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_bundle_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _masterNodeOut_a_bits_T_1_param = 3'h0; // @[master_adapter.scala:92:23] wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] get_bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] _masterNodeOut_a_bits_T_1_opcode = 3'h4; // @[master_adapter.scala:92:23] wire [2:0] _a_signed_T_1 = 3'h6; // @[memory.scala:61:27] wire [2:0] _a_size_T_1 = 3'h6; // @[memory.scala:60:24] wire [3:0] _a_signed_T = 4'h6; // @[memory.scala:61:27] wire [3:0] _a_size_T = 4'h6; // @[memory.scala:60:24] wire nodeOut_a_ready = auto_out_a_ready_0; // @[master_adapter.scala:38:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[master_adapter.scala:38:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[master_adapter.scala:38:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[master_adapter.scala:38:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[master_adapter.scala:38:7] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[master_adapter.scala:38:7] wire _io_dport_req_ready_T; // @[master_adapter.scala:77:31] wire masterNodeOut_d_valid; // @[MixedNode.scala:542:17] wire [31:0] _io_dport_resp_bits_data_T_15; // @[AMOALU.scala:45:16] wire [2:0] auto_out_a_bits_opcode_0; // @[master_adapter.scala:38:7] wire [2:0] auto_out_a_bits_param_0; // @[master_adapter.scala:38:7] wire [3:0] auto_out_a_bits_size_0; // @[master_adapter.scala:38:7] wire auto_out_a_bits_source_0; // @[master_adapter.scala:38:7] wire [31:0] auto_out_a_bits_address_0; // @[master_adapter.scala:38:7] wire [3:0] auto_out_a_bits_mask_0; // @[master_adapter.scala:38:7] wire [31:0] auto_out_a_bits_data_0; // @[master_adapter.scala:38:7] wire auto_out_a_bits_corrupt_0; // @[master_adapter.scala:38:7] wire auto_out_a_valid_0; // @[master_adapter.scala:38:7] wire auto_out_d_ready_0; // @[master_adapter.scala:38:7] wire io_dport_req_ready_0; // @[master_adapter.scala:38:7] wire [31:0] io_dport_resp_bits_data_0; // @[master_adapter.scala:38:7] wire io_dport_resp_valid_0; // @[master_adapter.scala:38:7] wire nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[master_adapter.scala:38:7] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[master_adapter.scala:38:7] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[master_adapter.scala:38:7] wire [3:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[master_adapter.scala:38:7] wire nodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[master_adapter.scala:38:7] wire [31:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[master_adapter.scala:38:7] wire [3:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[master_adapter.scala:38:7] wire [31:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[master_adapter.scala:38:7] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[master_adapter.scala:38:7] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[master_adapter.scala:38:7] wire nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [31:0] nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire _masterNodeOut_a_valid_T; // @[master_adapter.scala:75:27] wire [31:0] _masterNodeOut_a_bits_T_1_address; // @[master_adapter.scala:92:23] assign io_dport_resp_valid_0 = masterNodeOut_d_valid; // @[master_adapter.scala:38:7] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire masterNodeOut_a_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] reg [1:0] state; // @[master_adapter.scala:50:22] reg [31:0] a_address_reg; // @[master_adapter.scala:52:26] reg [31:0] req_address_reg; // @[master_adapter.scala:55:28] wire [31:0] _legal_T_14 = req_address_reg; // @[Parameters.scala:137:31] wire [31:0] get_bundle_address = req_address_reg; // @[Edges.scala:460:17] wire [31:0] _legal_T_65 = req_address_reg; // @[Parameters.scala:137:31] wire [31:0] put_bundle_address = req_address_reg; // @[Edges.scala:480:17] assign _io_dport_req_ready_T = state == 2'h0; // @[master_adapter.scala:50:22, :63:15, :77:31] assign _masterNodeOut_a_valid_T = state == 2'h1; // @[master_adapter.scala:50:22, :69:15, :75:27] assign masterNodeOut_a_valid = _masterNodeOut_a_valid_T; // @[master_adapter.scala:75:27] assign io_dport_req_ready_0 = _io_dport_req_ready_T; // @[master_adapter.scala:38:7, :77:31] wire [31:0] _GEN = {req_address_reg[31:14], req_address_reg[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [31:0] _legal_T_55; // @[Parameters.scala:137:31] assign _legal_T_55 = _GEN; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h8A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_50 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h8A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_0 = {req_address_reg[31:17], req_address_reg[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [31:0] _legal_T_96; // @[Parameters.scala:137:31] assign _legal_T_96 = _GEN_0; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {req_address_reg[31:21], req_address_reg[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _legal_T_70; // @[Parameters.scala:137:31] assign _legal_T_70 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h8A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {req_address_reg[31:26], req_address_reg[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_75; // @[Parameters.scala:137:31] assign _legal_T_75 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {req_address_reg[31:28], req_address_reg[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_80; // @[Parameters.scala:137:31] assign _legal_T_80 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h88000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = req_address_reg ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_85; // @[Parameters.scala:137:31] assign _legal_T_85 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h8A100000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_44 = _legal_T_18 \| _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_45 = _legal_T_44 \| _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_46 = _legal_T_45 \| _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_47 = _legal_T_46 \| _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_48 = _legal_T_47 \| _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_49 = _legal_T_48; // @[Parameters.scala:684:54, :685:42] wire legal_get = _legal_T_50 \| _legal_T_49; // @[Parameters.scala:684:54, :686:26] wire legal_op = legal_get; // @[Parameters.scala:686:26] assign _masterNodeOut_a_bits_T_1_address = get_bundle_address; // @[Edges.scala:460:17] wire a_mask_sub_bit = req_address_reg[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = req_address_reg[1]; // @[Misc.scala:210:26] wire a_mask_sub_1_2 = a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_bit = req_address_reg[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = req_address_reg[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire [32:0] _legal_T_56 = {1'h0, _legal_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_57 = _legal_T_56 & 33'h8A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_58 = _legal_T_57; // @[Parameters.scala:137:46] wire _legal_T_59 = _legal_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_60 = _legal_T_59; // @[Parameters.scala:684:54] wire _legal_T_102 = _legal_T_60; // @[Parameters.scala:684:54, :686:26] wire [32:0] _legal_T_66 = {1'h0, _legal_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_67 = _legal_T_66 & 33'h8A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_68 = _legal_T_67; // @[Parameters.scala:137:46] wire _legal_T_69 = _legal_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_71 = {1'h0, _legal_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_72 = _legal_T_71 & 33'h8A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_73 = _legal_T_72; // @[Parameters.scala:137:46] wire _legal_T_74 = _legal_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_76 = {1'h0, _legal_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_77 = _legal_T_76 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_78 = _legal_T_77; // @[Parameters.scala:137:46] wire _legal_T_79 = _legal_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_81 = {1'h0, _legal_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_82 = _legal_T_81 & 33'h88000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_83 = _legal_T_82; // @[Parameters.scala:137:46] wire _legal_T_84 = _legal_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_86 = {1'h0, _legal_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_87 = _legal_T_86 & 33'h8A100000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_88 = _legal_T_87; // @[Parameters.scala:137:46] wire _legal_T_89 = _legal_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_90 = _legal_T_69 \| _legal_T_74; // @[Parameters.scala:685:42] wire _legal_T_91 = _legal_T_90 \| _legal_T_79; // @[Parameters.scala:685:42] wire _legal_T_92 = _legal_T_91 \| _legal_T_84; // @[Parameters.scala:685:42] wire _legal_T_93 = _legal_T_92 \| _legal_T_89; // @[Parameters.scala:685:42] wire _legal_T_94 = _legal_T_93; // @[Parameters.scala:684:54, :685:42] wire [32:0] _legal_T_97 = {1'h0, _legal_T_96}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_98 = _legal_T_97 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_99 = _legal_T_98; // @[Parameters.scala:137:46] wire _legal_T_100 = _legal_T_99 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_103 = _legal_T_102 \| _legal_T_94; // @[Parameters.scala:684:54, :686:26] wire legal_put = _legal_T_103; // @[Parameters.scala:686:26] wire a_mask_sub_1_2_1 = a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_4 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign masterNodeOut_a_bits_address = _masterNodeOut_a_bits_T_1_address; // @[master_adapter.scala:92:23] wire [1:0] io_dport_resp_bits_data_size; // @[AMOALU.scala:11:18] assign io_dport_resp_bits_data_size = masterNodeOut_d_bits_size[1:0]; // @[AMOALU.scala:11:18, :12:8] wire _io_dport_resp_bits_data_shifted_T = a_address_reg[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_dport_resp_bits_data_shifted_T_1 = masterNodeOut_d_bits_data[31:16]; // @[AMOALU.scala:42:37] wire [15:0] _io_dport_resp_bits_data_T_5 = masterNodeOut_d_bits_data[31:16]; // @[AMOALU.scala:42:37, :45:94] wire [15:0] _io_dport_resp_bits_data_shifted_T_2 = masterNodeOut_d_bits_data[15:0]; // @[AMOALU.scala:42:55] wire [15:0] io_dport_resp_bits_data_shifted = _io_dport_resp_bits_data_shifted_T ? _io_dport_resp_bits_data_shifted_T_1 : _io_dport_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_dport_resp_bits_data_zeroed = io_dport_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_dport_resp_bits_data_T = io_dport_resp_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_dport_resp_bits_data_T_1 = _io_dport_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_dport_resp_bits_data_T_2 = io_dport_resp_bits_data_zeroed[15]; // @[AMOALU.scala:44:23, :45:81] wire [15:0] _io_dport_resp_bits_data_T_6 = _io_dport_resp_bits_data_T_1 ? 16'h0 : _io_dport_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,94}] wire [31:0] _io_dport_resp_bits_data_T_7 = {_io_dport_resp_bits_data_T_6, io_dport_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_dport_resp_bits_data_shifted_T_3 = a_address_reg[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_dport_resp_bits_data_shifted_T_4 = _io_dport_resp_bits_data_T_7[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_dport_resp_bits_data_shifted_T_5 = _io_dport_resp_bits_data_T_7[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_dport_resp_bits_data_shifted_1 = _io_dport_resp_bits_data_shifted_T_3 ? _io_dport_resp_bits_data_shifted_T_4 : _io_dport_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_dport_resp_bits_data_zeroed_1 = io_dport_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_dport_resp_bits_data_T_8 = io_dport_resp_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_dport_resp_bits_data_T_9 = _io_dport_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_dport_resp_bits_data_T_10 = io_dport_resp_bits_data_zeroed_1[7]; // @[AMOALU.scala:44:23, :45:81] wire [23:0] _io_dport_resp_bits_data_T_13 = _io_dport_resp_bits_data_T_7[31:8]; // @[AMOALU.scala:45:{16,94}] wire [23:0] _io_dport_resp_bits_data_T_14 = _io_dport_resp_bits_data_T_9 ? 24'h0 : _io_dport_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,94}] assign _io_dport_resp_bits_data_T_15 = {_io_dport_resp_bits_data_T_14, io_dport_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_dport_resp_bits_data_0 = _io_dport_resp_bits_data_T_15; // @[AMOALU.scala:45:16] wire resp_xp = masterNodeOut_d_bits_corrupt \| masterNodeOut_d_bits_denied; // @[master_adapter.scala:99:39]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_77 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_77 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_77( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_77 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i32_e8_s24_14 : output io : { flip signedIn : UInt<1>, flip in : UInt<32>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 31, 31) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<32>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 31, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<5>(0h1e), UInt<5>(0h1f)) node _intAsRawFloat_adjustedNormDist_T_33 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_32) node _intAsRawFloat_adjustedNormDist_T_34 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_33) node _intAsRawFloat_adjustedNormDist_T_35 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_34) node _intAsRawFloat_adjustedNormDist_T_36 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_35) node _intAsRawFloat_adjustedNormDist_T_37 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_36) node _intAsRawFloat_adjustedNormDist_T_38 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_37) node _intAsRawFloat_adjustedNormDist_T_39 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_38) node _intAsRawFloat_adjustedNormDist_T_40 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_39) node _intAsRawFloat_adjustedNormDist_T_41 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_40) node _intAsRawFloat_adjustedNormDist_T_42 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_41) node _intAsRawFloat_adjustedNormDist_T_43 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_42) node _intAsRawFloat_adjustedNormDist_T_44 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_43) node _intAsRawFloat_adjustedNormDist_T_45 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_44) node _intAsRawFloat_adjustedNormDist_T_46 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_45) node _intAsRawFloat_adjustedNormDist_T_47 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_46) node _intAsRawFloat_adjustedNormDist_T_48 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_47) node _intAsRawFloat_adjustedNormDist_T_49 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_48) node _intAsRawFloat_adjustedNormDist_T_50 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_49) node _intAsRawFloat_adjustedNormDist_T_51 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_50) node _intAsRawFloat_adjustedNormDist_T_52 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_51) node _intAsRawFloat_adjustedNormDist_T_53 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_52) node _intAsRawFloat_adjustedNormDist_T_54 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_53) node _intAsRawFloat_adjustedNormDist_T_55 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_54) node _intAsRawFloat_adjustedNormDist_T_56 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_55) node _intAsRawFloat_adjustedNormDist_T_57 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_56) node _intAsRawFloat_adjustedNormDist_T_58 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_57) node _intAsRawFloat_adjustedNormDist_T_59 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_58) node _intAsRawFloat_adjustedNormDist_T_60 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_59) node _intAsRawFloat_adjustedNormDist_T_61 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_60) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_61) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 31, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 31, 31) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 4, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_14 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i32_e8_s24_14( // @[INToRecFN.scala:43:7] input [31:0] io_in, // @[INToRecFN.scala:46:16] output [32:0] io_out // @[INToRecFN.scala:46:16] ); wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [32:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31] wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70] wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_14 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_43 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<3>(0h7)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<3>(0h6)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 5) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<3>(0h5)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h13)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 5) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<3>(0h4)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h13)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_24 = shr(io.in.a.bits.source, 5) node _source_ok_T_25 = eq(_source_ok_T_24, UInt<2>(0h3)) node _source_ok_T_26 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_27 = and(_source_ok_T_25, _source_ok_T_26) node _source_ok_T_28 = leq(source_ok_uncommonBits_4, UInt<5>(0h13)) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_30 = shr(io.in.a.bits.source, 5) node _source_ok_T_31 = eq(_source_ok_T_30, UInt<2>(0h2)) node _source_ok_T_32 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_T_34 = leq(source_ok_uncommonBits_5, UInt<5>(0h13)) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_36 = shr(io.in.a.bits.source, 5) node _source_ok_T_37 = eq(_source_ok_T_36, UInt<1>(0h1)) node _source_ok_T_38 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_T_40 = leq(source_ok_uncommonBits_6, UInt<5>(0h13)) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_42 = shr(io.in.a.bits.source, 5) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_7, UInt<5>(0h13)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 connect _source_ok_WIRE[4], _source_ok_T_29 connect _source_ok_WIRE[5], _source_ok_T_35 connect _source_ok_WIRE[6], _source_ok_T_41 connect _source_ok_WIRE[7], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_53, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<3>(0h7)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h13)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<10>(0h1c0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_17 = shr(io.in.a.bits.source, 5) node _T_18 = eq(_T_17, UInt<3>(0h6)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<5>(0h13)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<10>(0h1c0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_30 = shr(io.in.a.bits.source, 5) node _T_31 = eq(_T_30, UInt<3>(0h5)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<5>(0h13)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<10>(0h1c0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_43 = shr(io.in.a.bits.source, 5) node _T_44 = eq(_T_43, UInt<3>(0h4)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<5>(0h13)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<8>(0hc0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<10>(0h1c0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_56 = shr(io.in.a.bits.source, 5) node _T_57 = eq(_T_56, UInt<2>(0h3)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_4) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_4, UInt<5>(0h13)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<10>(0h1c0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_69 = shr(io.in.a.bits.source, 5) node _T_70 = eq(_T_69, UInt<2>(0h2)) node _T_71 = leq(UInt<1>(0h0), uncommonBits_5) node _T_72 = and(_T_70, _T_71) node _T_73 = leq(uncommonBits_5, UInt<5>(0h13)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<9>(0h140)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<10>(0h1c0))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = or(_T_75, _T_80) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_82 = shr(io.in.a.bits.source, 5) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_6) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_6, UInt<5>(0h13)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(_T_87, UInt<1>(0h0)) node _T_89 = xor(io.in.a.bits.address, UInt<9>(0h180)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<10>(0h1c0))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_95 = shr(io.in.a.bits.source, 5) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = leq(UInt<1>(0h0), uncommonBits_7) node _T_98 = and(_T_96, _T_97) node _T_99 = leq(uncommonBits_7, UInt<5>(0h13)) node _T_100 = and(_T_98, _T_99) node _T_101 = eq(_T_100, UInt<1>(0h0)) node _T_102 = xor(io.in.a.bits.address, UInt<9>(0h1c0)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<10>(0h1c0))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = or(_T_101, _T_106) node _T_108 = and(_T_16, _T_29) node _T_109 = and(_T_108, _T_42) node _T_110 = and(_T_109, _T_55) node _T_111 = and(_T_110, _T_68) node _T_112 = and(_T_111, _T_81) node _T_113 = and(_T_112, _T_94) node _T_114 = and(_T_113, _T_107) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_114, UInt<1>(0h1), "") : assert_1 node _T_118 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_118 : node _T_119 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_120 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_121 = and(_T_119, _T_120) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_122 = shr(io.in.a.bits.source, 5) node _T_123 = eq(_T_122, UInt<3>(0h7)) node _T_124 = leq(UInt<1>(0h0), uncommonBits_8) node _T_125 = and(_T_123, _T_124) node _T_126 = leq(uncommonBits_8, UInt<5>(0h13)) node _T_127 = and(_T_125, _T_126) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_128 = shr(io.in.a.bits.source, 5) node _T_129 = eq(_T_128, UInt<3>(0h6)) node _T_130 = leq(UInt<1>(0h0), uncommonBits_9) node _T_131 = and(_T_129, _T_130) node _T_132 = leq(uncommonBits_9, UInt<5>(0h13)) node _T_133 = and(_T_131, _T_132) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_134 = shr(io.in.a.bits.source, 5) node _T_135 = eq(_T_134, UInt<3>(0h5)) node _T_136 = leq(UInt<1>(0h0), uncommonBits_10) node _T_137 = and(_T_135, _T_136) node _T_138 = leq(uncommonBits_10, UInt<5>(0h13)) node _T_139 = and(_T_137, _T_138) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_11) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_11, UInt<5>(0h13)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0) node _T_146 = shr(io.in.a.bits.source, 5) node _T_147 = eq(_T_146, UInt<2>(0h3)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_12) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_12, UInt<5>(0h13)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<2>(0h2)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_13) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_13, UInt<5>(0h13)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_158 = shr(io.in.a.bits.source, 5) node _T_159 = eq(_T_158, UInt<1>(0h1)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_14) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_14, UInt<5>(0h13)) node _T_163 = and(_T_161, _T_162) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_164 = shr(io.in.a.bits.source, 5) node _T_165 = eq(_T_164, UInt<1>(0h0)) node _T_166 = leq(UInt<1>(0h0), uncommonBits_15) node _T_167 = and(_T_165, _T_166) node _T_168 = leq(uncommonBits_15, UInt<5>(0h13)) node _T_169 = and(_T_167, _T_168) node _T_170 = or(_T_127, _T_133) node _T_171 = or(_T_170, _T_139) node _T_172 = or(_T_171, _T_145) node _T_173 = or(_T_172, _T_151) node _T_174 = or(_T_173, _T_157) node _T_175 = or(_T_174, _T_163) node _T_176 = or(_T_175, _T_169) node _T_177 = and(_T_121, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<17>(0h10000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = and(_T_179, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_T_178, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_187, UInt<1>(0h1), "") : assert_2 node _T_191 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_192 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_193 = and(_T_191, _T_192) node _T_194 = or(UInt<1>(0h0), _T_193) node _T_195 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<17>(0h10000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = and(_T_194, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(UInt<1>(0h0), _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_233 = shr(io.in.a.bits.source, 5) node _T_234 = eq(_T_233, UInt<3>(0h7)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_16) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_16, UInt<5>(0h13)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_239 = shr(io.in.a.bits.source, 5) node _T_240 = eq(_T_239, UInt<3>(0h6)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_17) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_17, UInt<5>(0h13)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_245 = shr(io.in.a.bits.source, 5) node _T_246 = eq(_T_245, UInt<3>(0h5)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_18) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_18, UInt<5>(0h13)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<3>(0h4)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_19) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_19, UInt<5>(0h13)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<2>(0h3)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_20) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_20, UInt<5>(0h13)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_21) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_21, UInt<5>(0h13)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<1>(0h1)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_22) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_22, UInt<5>(0h13)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_23) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_23, UInt<5>(0h13)) node _T_280 = and(_T_278, _T_279) node _T_281 = or(_T_238, _T_244) node _T_282 = or(_T_281, _T_250) node _T_283 = or(_T_282, _T_256) node _T_284 = or(_T_283, _T_262) node _T_285 = or(_T_284, _T_268) node _T_286 = or(_T_285, _T_274) node _T_287 = or(_T_286, _T_280) node _T_288 = and(_T_232, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = and(_T_305, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = and(UInt<1>(0h0), _T_312) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_313, UInt<1>(0h1), "") : assert_11 node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(source_ok, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_320 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_T_320, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_320, UInt<1>(0h1), "") : assert_13 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_327 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_327, UInt<1>(0h1), "") : assert_15 node _T_331 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_331, UInt<1>(0h1), "") : assert_16 node _T_335 = not(io.in.a.bits.mask) node _T_336 = eq(_T_335, UInt<1>(0h0)) node _T_337 = asUInt(reset) node _T_338 = eq(_T_337, UInt<1>(0h0)) when _T_338 : node _T_339 = eq(_T_336, UInt<1>(0h0)) when _T_339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_336, UInt<1>(0h1), "") : assert_17 node _T_340 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_T_340, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_340, UInt<1>(0h1), "") : assert_18 node _T_344 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_344 : node _T_345 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_346 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_347 = and(_T_345, _T_346) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0) node _T_348 = shr(io.in.a.bits.source, 5) node _T_349 = eq(_T_348, UInt<3>(0h7)) node _T_350 = leq(UInt<1>(0h0), uncommonBits_24) node _T_351 = and(_T_349, _T_350) node _T_352 = leq(uncommonBits_24, UInt<5>(0h13)) node _T_353 = and(_T_351, _T_352) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0) node _T_354 = shr(io.in.a.bits.source, 5) node _T_355 = eq(_T_354, UInt<3>(0h6)) node _T_356 = leq(UInt<1>(0h0), uncommonBits_25) node _T_357 = and(_T_355, _T_356) node _T_358 = leq(uncommonBits_25, UInt<5>(0h13)) node _T_359 = and(_T_357, _T_358) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0) node _T_360 = shr(io.in.a.bits.source, 5) node _T_361 = eq(_T_360, UInt<3>(0h5)) node _T_362 = leq(UInt<1>(0h0), uncommonBits_26) node _T_363 = and(_T_361, _T_362) node _T_364 = leq(uncommonBits_26, UInt<5>(0h13)) node _T_365 = and(_T_363, _T_364) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0) node _T_366 = shr(io.in.a.bits.source, 5) node _T_367 = eq(_T_366, UInt<3>(0h4)) node _T_368 = leq(UInt<1>(0h0), uncommonBits_27) node _T_369 = and(_T_367, _T_368) node _T_370 = leq(uncommonBits_27, UInt<5>(0h13)) node _T_371 = and(_T_369, _T_370) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_372 = shr(io.in.a.bits.source, 5) node _T_373 = eq(_T_372, UInt<2>(0h3)) node _T_374 = leq(UInt<1>(0h0), uncommonBits_28) node _T_375 = and(_T_373, _T_374) node _T_376 = leq(uncommonBits_28, UInt<5>(0h13)) node _T_377 = and(_T_375, _T_376) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_378 = shr(io.in.a.bits.source, 5) node _T_379 = eq(_T_378, UInt<2>(0h2)) node _T_380 = leq(UInt<1>(0h0), uncommonBits_29) node _T_381 = and(_T_379, _T_380) node _T_382 = leq(uncommonBits_29, UInt<5>(0h13)) node _T_383 = and(_T_381, _T_382) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_384 = shr(io.in.a.bits.source, 5) node _T_385 = eq(_T_384, UInt<1>(0h1)) node _T_386 = leq(UInt<1>(0h0), uncommonBits_30) node _T_387 = and(_T_385, _T_386) node _T_388 = leq(uncommonBits_30, UInt<5>(0h13)) node _T_389 = and(_T_387, _T_388) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_390 = shr(io.in.a.bits.source, 5) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = leq(UInt<1>(0h0), uncommonBits_31) node _T_393 = and(_T_391, _T_392) node _T_394 = leq(uncommonBits_31, UInt<5>(0h13)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(_T_353, _T_359) node _T_397 = or(_T_396, _T_365) node _T_398 = or(_T_397, _T_371) node _T_399 = or(_T_398, _T_377) node _T_400 = or(_T_399, _T_383) node _T_401 = or(_T_400, _T_389) node _T_402 = or(_T_401, _T_395) node _T_403 = and(_T_347, _T_402) node _T_404 = or(UInt<1>(0h0), _T_403) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_404, UInt<1>(0h1), "") : assert_19 node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_409 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_410 = and(_T_408, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<17>(0h10000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = and(_T_411, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_418, UInt<1>(0h1), "") : assert_20 node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(source_ok, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(is_aligned, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_428 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_428, UInt<1>(0h1), "") : assert_23 node _T_432 = eq(io.in.a.bits.mask, mask) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_432, UInt<1>(0h1), "") : assert_24 node _T_436 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_436, UInt<1>(0h1), "") : assert_25 node _T_440 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_440 : node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_444 = shr(io.in.a.bits.source, 5) node _T_445 = eq(_T_444, UInt<3>(0h7)) node _T_446 = leq(UInt<1>(0h0), uncommonBits_32) node _T_447 = and(_T_445, _T_446) node _T_448 = leq(uncommonBits_32, UInt<5>(0h13)) node _T_449 = and(_T_447, _T_448) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_450 = shr(io.in.a.bits.source, 5) node _T_451 = eq(_T_450, UInt<3>(0h6)) node _T_452 = leq(UInt<1>(0h0), uncommonBits_33) node _T_453 = and(_T_451, _T_452) node _T_454 = leq(uncommonBits_33, UInt<5>(0h13)) node _T_455 = and(_T_453, _T_454) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_456 = shr(io.in.a.bits.source, 5) node _T_457 = eq(_T_456, UInt<3>(0h5)) node _T_458 = leq(UInt<1>(0h0), uncommonBits_34) node _T_459 = and(_T_457, _T_458) node _T_460 = leq(uncommonBits_34, UInt<5>(0h13)) node _T_461 = and(_T_459, _T_460) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_462 = shr(io.in.a.bits.source, 5) node _T_463 = eq(_T_462, UInt<3>(0h4)) node _T_464 = leq(UInt<1>(0h0), uncommonBits_35) node _T_465 = and(_T_463, _T_464) node _T_466 = leq(uncommonBits_35, UInt<5>(0h13)) node _T_467 = and(_T_465, _T_466) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_468 = shr(io.in.a.bits.source, 5) node _T_469 = eq(_T_468, UInt<2>(0h3)) node _T_470 = leq(UInt<1>(0h0), uncommonBits_36) node _T_471 = and(_T_469, _T_470) node _T_472 = leq(uncommonBits_36, UInt<5>(0h13)) node _T_473 = and(_T_471, _T_472) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_474 = shr(io.in.a.bits.source, 5) node _T_475 = eq(_T_474, UInt<2>(0h2)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_37) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_37, UInt<5>(0h13)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_38) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_38, UInt<5>(0h13)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_486 = shr(io.in.a.bits.source, 5) node _T_487 = eq(_T_486, UInt<1>(0h0)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_39) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_39, UInt<5>(0h13)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(_T_449, _T_455) node _T_493 = or(_T_492, _T_461) node _T_494 = or(_T_493, _T_467) node _T_495 = or(_T_494, _T_473) node _T_496 = or(_T_495, _T_479) node _T_497 = or(_T_496, _T_485) node _T_498 = or(_T_497, _T_491) node _T_499 = and(_T_443, _T_498) node _T_500 = or(UInt<1>(0h0), _T_499) node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_502 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_503 = and(_T_501, _T_502) node _T_504 = or(UInt<1>(0h0), _T_503) node _T_505 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<17>(0h10000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = and(_T_504, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = and(_T_500, _T_511) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_512, UInt<1>(0h1), "") : assert_26 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_522, UInt<1>(0h1), "") : assert_29 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_526, UInt<1>(0h1), "") : assert_30 node _T_530 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_530 : node _T_531 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_532 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_533 = and(_T_531, _T_532) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_534 = shr(io.in.a.bits.source, 5) node _T_535 = eq(_T_534, UInt<3>(0h7)) node _T_536 = leq(UInt<1>(0h0), uncommonBits_40) node _T_537 = and(_T_535, _T_536) node _T_538 = leq(uncommonBits_40, UInt<5>(0h13)) node _T_539 = and(_T_537, _T_538) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_540 = shr(io.in.a.bits.source, 5) node _T_541 = eq(_T_540, UInt<3>(0h6)) node _T_542 = leq(UInt<1>(0h0), uncommonBits_41) node _T_543 = and(_T_541, _T_542) node _T_544 = leq(uncommonBits_41, UInt<5>(0h13)) node _T_545 = and(_T_543, _T_544) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_546 = shr(io.in.a.bits.source, 5) node _T_547 = eq(_T_546, UInt<3>(0h5)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_42) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_42, UInt<5>(0h13)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_552 = shr(io.in.a.bits.source, 5) node _T_553 = eq(_T_552, UInt<3>(0h4)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_43) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_43, UInt<5>(0h13)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_558 = shr(io.in.a.bits.source, 5) node _T_559 = eq(_T_558, UInt<2>(0h3)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_44) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_44, UInt<5>(0h13)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_564 = shr(io.in.a.bits.source, 5) node _T_565 = eq(_T_564, UInt<2>(0h2)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_45) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_45, UInt<5>(0h13)) node _T_569 = and(_T_567, _T_568) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_570 = shr(io.in.a.bits.source, 5) node _T_571 = eq(_T_570, UInt<1>(0h1)) node _T_572 = leq(UInt<1>(0h0), uncommonBits_46) node _T_573 = and(_T_571, _T_572) node _T_574 = leq(uncommonBits_46, UInt<5>(0h13)) node _T_575 = and(_T_573, _T_574) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_576 = shr(io.in.a.bits.source, 5) node _T_577 = eq(_T_576, UInt<1>(0h0)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_47) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_47, UInt<5>(0h13)) node _T_581 = and(_T_579, _T_580) node _T_582 = or(_T_539, _T_545) node _T_583 = or(_T_582, _T_551) node _T_584 = or(_T_583, _T_557) node _T_585 = or(_T_584, _T_563) node _T_586 = or(_T_585, _T_569) node _T_587 = or(_T_586, _T_575) node _T_588 = or(_T_587, _T_581) node _T_589 = and(_T_533, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_593 = and(_T_591, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_596 = cvt(_T_595) node _T_597 = and(_T_596, asSInt(UInt<17>(0h10000))) node _T_598 = asSInt(_T_597) node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0))) node _T_600 = and(_T_594, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = and(_T_590, _T_601) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_602, UInt<1>(0h1), "") : assert_31 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(source_ok, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(is_aligned, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_612 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_612, UInt<1>(0h1), "") : assert_34 node _T_616 = not(mask) node _T_617 = and(io.in.a.bits.mask, _T_616) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_618, UInt<1>(0h1), "") : assert_35 node _T_622 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_622 : node _T_623 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_624 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 4, 0) node _T_626 = shr(io.in.a.bits.source, 5) node _T_627 = eq(_T_626, UInt<3>(0h7)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_48) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_48, UInt<5>(0h13)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 4, 0) node _T_632 = shr(io.in.a.bits.source, 5) node _T_633 = eq(_T_632, UInt<3>(0h6)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_49) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_49, UInt<5>(0h13)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_638 = shr(io.in.a.bits.source, 5) node _T_639 = eq(_T_638, UInt<3>(0h5)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_50) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_50, UInt<5>(0h13)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_644 = shr(io.in.a.bits.source, 5) node _T_645 = eq(_T_644, UInt<3>(0h4)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_51) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_51, UInt<5>(0h13)) node _T_649 = and(_T_647, _T_648) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_650 = shr(io.in.a.bits.source, 5) node _T_651 = eq(_T_650, UInt<2>(0h3)) node _T_652 = leq(UInt<1>(0h0), uncommonBits_52) node _T_653 = and(_T_651, _T_652) node _T_654 = leq(uncommonBits_52, UInt<5>(0h13)) node _T_655 = and(_T_653, _T_654) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_656 = shr(io.in.a.bits.source, 5) node _T_657 = eq(_T_656, UInt<2>(0h2)) node _T_658 = leq(UInt<1>(0h0), uncommonBits_53) node _T_659 = and(_T_657, _T_658) node _T_660 = leq(uncommonBits_53, UInt<5>(0h13)) node _T_661 = and(_T_659, _T_660) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_662 = shr(io.in.a.bits.source, 5) node _T_663 = eq(_T_662, UInt<1>(0h1)) node _T_664 = leq(UInt<1>(0h0), uncommonBits_54) node _T_665 = and(_T_663, _T_664) node _T_666 = leq(uncommonBits_54, UInt<5>(0h13)) node _T_667 = and(_T_665, _T_666) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_668 = shr(io.in.a.bits.source, 5) node _T_669 = eq(_T_668, UInt<1>(0h0)) node _T_670 = leq(UInt<1>(0h0), uncommonBits_55) node _T_671 = and(_T_669, _T_670) node _T_672 = leq(uncommonBits_55, UInt<5>(0h13)) node _T_673 = and(_T_671, _T_672) node _T_674 = or(_T_631, _T_637) node _T_675 = or(_T_674, _T_643) node _T_676 = or(_T_675, _T_649) node _T_677 = or(_T_676, _T_655) node _T_678 = or(_T_677, _T_661) node _T_679 = or(_T_678, _T_667) node _T_680 = or(_T_679, _T_673) node _T_681 = and(_T_625, _T_680) node _T_682 = or(UInt<1>(0h0), _T_681) node _T_683 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_685 = cvt(_T_684) node _T_686 = and(_T_685, asSInt(UInt<17>(0h10000))) node _T_687 = asSInt(_T_686) node _T_688 = eq(_T_687, asSInt(UInt<1>(0h0))) node _T_689 = and(_T_683, _T_688) node _T_690 = or(UInt<1>(0h0), _T_689) node _T_691 = and(_T_682, _T_690) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_691, UInt<1>(0h1), "") : assert_36 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(source_ok, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(is_aligned, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_701 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_701, UInt<1>(0h1), "") : assert_39 node _T_705 = eq(io.in.a.bits.mask, mask) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_705, UInt<1>(0h1), "") : assert_40 node _T_709 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_709 : node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_711 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_712 = and(_T_710, _T_711) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_713 = shr(io.in.a.bits.source, 5) node _T_714 = eq(_T_713, UInt<3>(0h7)) node _T_715 = leq(UInt<1>(0h0), uncommonBits_56) node _T_716 = and(_T_714, _T_715) node _T_717 = leq(uncommonBits_56, UInt<5>(0h13)) node _T_718 = and(_T_716, _T_717) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_719 = shr(io.in.a.bits.source, 5) node _T_720 = eq(_T_719, UInt<3>(0h6)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_57) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_57, UInt<5>(0h13)) node _T_724 = and(_T_722, _T_723) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_725 = shr(io.in.a.bits.source, 5) node _T_726 = eq(_T_725, UInt<3>(0h5)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_58) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_58, UInt<5>(0h13)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_731 = shr(io.in.a.bits.source, 5) node _T_732 = eq(_T_731, UInt<3>(0h4)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_59) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_59, UInt<5>(0h13)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_737 = shr(io.in.a.bits.source, 5) node _T_738 = eq(_T_737, UInt<2>(0h3)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_60) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_60, UInt<5>(0h13)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_743 = shr(io.in.a.bits.source, 5) node _T_744 = eq(_T_743, UInt<2>(0h2)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_61) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_61, UInt<5>(0h13)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_749 = shr(io.in.a.bits.source, 5) node _T_750 = eq(_T_749, UInt<1>(0h1)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_62) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_62, UInt<5>(0h13)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_755 = shr(io.in.a.bits.source, 5) node _T_756 = eq(_T_755, UInt<1>(0h0)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_63) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_63, UInt<5>(0h13)) node _T_760 = and(_T_758, _T_759) node _T_761 = or(_T_718, _T_724) node _T_762 = or(_T_761, _T_730) node _T_763 = or(_T_762, _T_736) node _T_764 = or(_T_763, _T_742) node _T_765 = or(_T_764, _T_748) node _T_766 = or(_T_765, _T_754) node _T_767 = or(_T_766, _T_760) node _T_768 = and(_T_712, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = and(_T_770, _T_775) node _T_777 = or(UInt<1>(0h0), _T_776) node _T_778 = and(_T_769, _T_777) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_778, UInt<1>(0h1), "") : assert_41 node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(source_ok, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(is_aligned, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_788 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(_T_788, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_788, UInt<1>(0h1), "") : assert_44 node _T_792 = eq(io.in.a.bits.mask, mask) node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(_T_792, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_792, UInt<1>(0h1), "") : assert_45 node _T_796 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_796 : node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_799 = and(_T_797, _T_798) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_800 = shr(io.in.a.bits.source, 5) node _T_801 = eq(_T_800, UInt<3>(0h7)) node _T_802 = leq(UInt<1>(0h0), uncommonBits_64) node _T_803 = and(_T_801, _T_802) node _T_804 = leq(uncommonBits_64, UInt<5>(0h13)) node _T_805 = and(_T_803, _T_804) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_806 = shr(io.in.a.bits.source, 5) node _T_807 = eq(_T_806, UInt<3>(0h6)) node _T_808 = leq(UInt<1>(0h0), uncommonBits_65) node _T_809 = and(_T_807, _T_808) node _T_810 = leq(uncommonBits_65, UInt<5>(0h13)) node _T_811 = and(_T_809, _T_810) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_812 = shr(io.in.a.bits.source, 5) node _T_813 = eq(_T_812, UInt<3>(0h5)) node _T_814 = leq(UInt<1>(0h0), uncommonBits_66) node _T_815 = and(_T_813, _T_814) node _T_816 = leq(uncommonBits_66, UInt<5>(0h13)) node _T_817 = and(_T_815, _T_816) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_818 = shr(io.in.a.bits.source, 5) node _T_819 = eq(_T_818, UInt<3>(0h4)) node _T_820 = leq(UInt<1>(0h0), uncommonBits_67) node _T_821 = and(_T_819, _T_820) node _T_822 = leq(uncommonBits_67, UInt<5>(0h13)) node _T_823 = and(_T_821, _T_822) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_824 = shr(io.in.a.bits.source, 5) node _T_825 = eq(_T_824, UInt<2>(0h3)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_68) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_68, UInt<5>(0h13)) node _T_829 = and(_T_827, _T_828) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_830 = shr(io.in.a.bits.source, 5) node _T_831 = eq(_T_830, UInt<2>(0h2)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_69) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_69, UInt<5>(0h13)) node _T_835 = and(_T_833, _T_834) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_836 = shr(io.in.a.bits.source, 5) node _T_837 = eq(_T_836, UInt<1>(0h1)) node _T_838 = leq(UInt<1>(0h0), uncommonBits_70) node _T_839 = and(_T_837, _T_838) node _T_840 = leq(uncommonBits_70, UInt<5>(0h13)) node _T_841 = and(_T_839, _T_840) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_842 = shr(io.in.a.bits.source, 5) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_71) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_71, UInt<5>(0h13)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(_T_805, _T_811) node _T_849 = or(_T_848, _T_817) node _T_850 = or(_T_849, _T_823) node _T_851 = or(_T_850, _T_829) node _T_852 = or(_T_851, _T_835) node _T_853 = or(_T_852, _T_841) node _T_854 = or(_T_853, _T_847) node _T_855 = and(_T_799, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_858 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_859 = cvt(_T_858) node _T_860 = and(_T_859, asSInt(UInt<17>(0h10000))) node _T_861 = asSInt(_T_860) node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0))) node _T_863 = and(_T_857, _T_862) node _T_864 = or(UInt<1>(0h0), _T_863) node _T_865 = and(_T_856, _T_864) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_865, UInt<1>(0h1), "") : assert_46 node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(source_ok, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(is_aligned, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_875 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_875, UInt<1>(0h1), "") : assert_49 node _T_879 = eq(io.in.a.bits.mask, mask) node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(_T_879, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_879, UInt<1>(0h1), "") : assert_50 node _T_883 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_883, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_887 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_887, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 5) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<3>(0h7)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_8, UInt<5>(0h13)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 5) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<3>(0h6)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_9, UInt<5>(0h13)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 5) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h5)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_10, UInt<5>(0h13)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 5) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<3>(0h4)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_11, UInt<5>(0h13)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 4, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 5) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<2>(0h3)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_12, UInt<5>(0h13)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 4, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 5) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<2>(0h2)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_13, UInt<5>(0h13)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 5) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<1>(0h1)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_14, UInt<5>(0h13)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_96 = shr(io.in.d.bits.source, 5) node _source_ok_T_97 = eq(_source_ok_T_96, UInt<1>(0h0)) node _source_ok_T_98 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_99 = and(_source_ok_T_97, _source_ok_T_98) node _source_ok_T_100 = leq(source_ok_uncommonBits_15, UInt<5>(0h13)) node _source_ok_T_101 = and(_source_ok_T_99, _source_ok_T_100) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_59 connect _source_ok_WIRE_1[1], _source_ok_T_65 connect _source_ok_WIRE_1[2], _source_ok_T_71 connect _source_ok_WIRE_1[3], _source_ok_T_77 connect _source_ok_WIRE_1[4], _source_ok_T_83 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_95 connect _source_ok_WIRE_1[7], _source_ok_T_101 node _source_ok_T_102 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[2]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[3]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[4]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[5]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_891 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_891 : node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(source_ok_1, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_895 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_895, UInt<1>(0h1), "") : assert_54 node _T_899 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_899, UInt<1>(0h1), "") : assert_55 node _T_903 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_903, UInt<1>(0h1), "") : assert_56 node _T_907 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_907, UInt<1>(0h1), "") : assert_57 node _T_911 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_911 : node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(source_ok_1, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(sink_ok, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_918 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_918, UInt<1>(0h1), "") : assert_60 node _T_922 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_922, UInt<1>(0h1), "") : assert_61 node _T_926 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_926, UInt<1>(0h1), "") : assert_62 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_930, UInt<1>(0h1), "") : assert_63 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h0), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_935, UInt<1>(0h1), "") : assert_64 node _T_939 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_939 : node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(source_ok_1, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(sink_ok, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_946 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_946, UInt<1>(0h1), "") : assert_67 node _T_950 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_950, UInt<1>(0h1), "") : assert_68 node _T_954 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(_T_954, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_954, UInt<1>(0h1), "") : assert_69 node _T_958 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_959 = or(_T_958, io.in.d.bits.corrupt) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_959, UInt<1>(0h1), "") : assert_70 node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_964 = or(UInt<1>(0h0), _T_963) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_964, UInt<1>(0h1), "") : assert_71 node _T_968 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_968 : node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(source_ok_1, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_972 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_972, UInt<1>(0h1), "") : assert_73 node _T_976 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_976, UInt<1>(0h1), "") : assert_74 node _T_980 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_981 = or(UInt<1>(0h0), _T_980) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_981, UInt<1>(0h1), "") : assert_75 node _T_985 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_985 : node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(source_ok_1, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_989 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_989, UInt<1>(0h1), "") : assert_77 node _T_993 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_994 = or(_T_993, io.in.d.bits.corrupt) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_994, UInt<1>(0h1), "") : assert_78 node _T_998 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_999, UInt<1>(0h1), "") : assert_79 node _T_1003 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1003 : node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(source_ok_1, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1007 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_81 node _T_1011 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_82 node _T_1015 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1016 = or(UInt<1>(0h0), _T_1015) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1020 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1024 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1028 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1032 = eq(a_first, UInt<1>(0h0)) node _T_1033 = and(io.in.a.valid, _T_1032) when _T_1033 : node _T_1034 = eq(io.in.a.bits.opcode, opcode) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_87 node _T_1038 = eq(io.in.a.bits.param, param) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_88 node _T_1042 = eq(io.in.a.bits.size, size) node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(_T_1042, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1042, UInt<1>(0h1), "") : assert_89 node _T_1046 = eq(io.in.a.bits.source, source) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_90 node _T_1050 = eq(io.in.a.bits.address, address) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_91 node _T_1054 = and(io.in.a.ready, io.in.a.valid) node _T_1055 = and(_T_1054, a_first) when _T_1055 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1056 = eq(d_first, UInt<1>(0h0)) node _T_1057 = and(io.in.d.valid, _T_1056) when _T_1057 : node _T_1058 = eq(io.in.d.bits.opcode, opcode_1) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_92 node _T_1062 = eq(io.in.d.bits.param, param_1) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_93 node _T_1066 = eq(io.in.d.bits.size, size_1) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_94 node _T_1070 = eq(io.in.d.bits.source, source_1) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_95 node _T_1074 = eq(io.in.d.bits.sink, sink) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_96 node _T_1078 = eq(io.in.d.bits.denied, denied) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_97 node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = and(_T_1082, d_first) when _T_1083 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<244>, clock, reset, UInt<244>(0h0) regreset inflight_opcodes : UInt<976>, clock, reset, UInt<976>(0h0) regreset inflight_sizes : UInt<976>, clock, reset, UInt<976>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<244> connect a_set, UInt<244>(0h0) wire a_set_wo_ready : UInt<244> connect a_set_wo_ready, UInt<244>(0h0) wire a_opcodes_set : UInt<976> connect a_opcodes_set, UInt<976>(0h0) wire a_sizes_set : UInt<976> connect a_sizes_set, UInt<976>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1084 = and(io.in.a.valid, a_first_1) node _T_1085 = and(_T_1084, UInt<1>(0h1)) when _T_1085 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1086 = and(io.in.a.ready, io.in.a.valid) node _T_1087 = and(_T_1086, a_first_1) node _T_1088 = and(_T_1087, UInt<1>(0h1)) when _T_1088 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1089 = dshr(inflight, io.in.a.bits.source) node _T_1090 = bits(_T_1089, 0, 0) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<244> connect d_clr, UInt<244>(0h0) wire d_clr_wo_ready : UInt<244> connect d_clr_wo_ready, UInt<244>(0h0) wire d_opcodes_clr : UInt<976> connect d_opcodes_clr, UInt<976>(0h0) wire d_sizes_clr : UInt<976> connect d_sizes_clr, UInt<976>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1095 = and(io.in.d.valid, d_first_1) node _T_1096 = and(_T_1095, UInt<1>(0h1)) node _T_1097 = eq(d_release_ack, UInt<1>(0h0)) node _T_1098 = and(_T_1096, _T_1097) when _T_1098 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1099 = and(io.in.d.ready, io.in.d.valid) node _T_1100 = and(_T_1099, d_first_1) node _T_1101 = and(_T_1100, UInt<1>(0h1)) node _T_1102 = eq(d_release_ack, UInt<1>(0h0)) node _T_1103 = and(_T_1101, _T_1102) when _T_1103 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1104 = and(io.in.d.valid, d_first_1) node _T_1105 = and(_T_1104, UInt<1>(0h1)) node _T_1106 = eq(d_release_ack, UInt<1>(0h0)) node _T_1107 = and(_T_1105, _T_1106) when _T_1107 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1108 = dshr(inflight, io.in.d.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = or(_T_1109, same_cycle_resp) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1114 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1115 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1116 = or(_T_1114, _T_1115) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_100 node _T_1120 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_101 else : node _T_1124 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1125 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1126 = or(_T_1124, _T_1125) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_102 node _T_1130 = eq(io.in.d.bits.size, a_size_lookup) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_103 node _T_1134 = and(io.in.d.valid, d_first_1) node _T_1135 = and(_T_1134, a_first_1) node _T_1136 = and(_T_1135, io.in.a.valid) node _T_1137 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1138 = and(_T_1136, _T_1137) node _T_1139 = eq(d_release_ack, UInt<1>(0h0)) node _T_1140 = and(_T_1138, _T_1139) when _T_1140 : node _T_1141 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1142 = or(_T_1141, io.in.a.ready) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_104 node _T_1146 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1147 = orr(a_set_wo_ready) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) node _T_1149 = or(_T_1146, _T_1148) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_86 node _T_1153 = orr(inflight) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) node _T_1155 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = lt(watchdog, plusarg_reader.out) node _T_1158 = or(_T_1156, _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1162 = and(io.in.a.ready, io.in.a.valid) node _T_1163 = and(io.in.d.ready, io.in.d.valid) node _T_1164 = or(_T_1162, _T_1163) when _T_1164 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<244>, clock, reset, UInt<244>(0h0) regreset inflight_opcodes_1 : UInt<976>, clock, reset, UInt<976>(0h0) regreset inflight_sizes_1 : UInt<976>, clock, reset, UInt<976>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<244> connect c_set, UInt<244>(0h0) wire c_set_wo_ready : UInt<244> connect c_set_wo_ready, UInt<244>(0h0) wire c_opcodes_set : UInt<976> connect c_opcodes_set, UInt<976>(0h0) wire c_sizes_set : UInt<976> connect c_sizes_set, UInt<976>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1165 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1166 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1167 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = and(_T_1165, _T_1168) when _T_1169 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1170 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1171 = and(_T_1170, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1172 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1173 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = and(_T_1171, _T_1174) when _T_1175 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1176 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1177 = bits(_T_1176, 0, 0) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<244> connect d_clr_1, UInt<244>(0h0) wire d_clr_wo_ready_1 : UInt<244> connect d_clr_wo_ready_1, UInt<244>(0h0) wire d_opcodes_clr_1 : UInt<976> connect d_opcodes_clr_1, UInt<976>(0h0) wire d_sizes_clr_1 : UInt<976> connect d_sizes_clr_1, UInt<976>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1182 = and(io.in.d.valid, d_first_2) node _T_1183 = and(_T_1182, UInt<1>(0h1)) node _T_1184 = and(_T_1183, d_release_ack_1) when _T_1184 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1185 = and(io.in.d.ready, io.in.d.valid) node _T_1186 = and(_T_1185, d_first_2) node _T_1187 = and(_T_1186, UInt<1>(0h1)) node _T_1188 = and(_T_1187, d_release_ack_1) when _T_1188 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1189 = and(io.in.d.valid, d_first_2) node _T_1190 = and(_T_1189, UInt<1>(0h1)) node _T_1191 = and(_T_1190, d_release_ack_1) when _T_1191 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1192 = dshr(inflight_1, io.in.d.bits.source) node _T_1193 = bits(_T_1192, 0, 0) node _T_1194 = or(_T_1193, same_cycle_resp_1) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1198 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_109 else : node _T_1202 = eq(io.in.d.bits.size, c_size_lookup) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110 node _T_1206 = and(io.in.d.valid, d_first_2) node _T_1207 = and(_T_1206, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1208 = and(_T_1207, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1209 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = and(_T_1210, d_release_ack_1) node _T_1212 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1213 = and(_T_1211, _T_1212) when _T_1213 : node _T_1214 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1215 = or(_T_1214, _WIRE_23.ready) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_111 node _T_1219 = orr(c_set_wo_ready) when _T_1219 : node _T_1220 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_87 node _T_1224 = orr(inflight_1) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) node _T_1226 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1227 = or(_T_1225, _T_1226) node _T_1228 = lt(watchdog_1, plusarg_reader_1.out) node _T_1229 = or(_T_1227, _T_1228) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1233 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1234 = and(io.in.d.ready, io.in.d.valid) node _T_1235 = or(_T_1233, _T_1234) when _T_1235 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_43( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_26 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_38 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_98 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [975:0] c_opcodes_set = 976'h0; // @[Monitor.scala:740:34] wire [975:0] c_sizes_set = 976'h0; // @[Monitor.scala:741:34] wire [243:0] c_set = 244'h0; // @[Monitor.scala:738:34] wire [243:0] c_set_wo_ready = 244'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_14 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_15 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_6 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_12 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_18 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_24 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_30 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_36 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_42 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = &_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 3'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_9 & _source_ok_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 3'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_15 & _source_ok_T_16; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = _source_ok_T_18 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_3 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_25 = _source_ok_T_24 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_27 = _source_ok_T_25; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_28 = source_ok_uncommonBits_4 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_29 = _source_ok_T_27 & _source_ok_T_28; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_4 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_31 = _source_ok_T_30 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = source_ok_uncommonBits_5 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_35 = _source_ok_T_33 & _source_ok_T_34; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_37 = _source_ok_T_36 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_39 = _source_ok_T_37; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = source_ok_uncommonBits_6 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_41 = _source_ok_T_39 & _source_ok_T_40; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_6 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_43 = _source_ok_T_42 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = source_ok_uncommonBits_7 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_47 = _source_ok_T_45 & _source_ok_T_46; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_53 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_12 = _uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_13 = _uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_24 = _uncommonBits_T_24[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_25 = _uncommonBits_T_25[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_26 = _uncommonBits_T_26[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_27 = _uncommonBits_T_27[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_44 = _uncommonBits_T_44[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_45 = _uncommonBits_T_45[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_48 = _uncommonBits_T_48[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_49 = _uncommonBits_T_49[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_56 = _uncommonBits_T_56[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_57 = _uncommonBits_T_57[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_66 = _uncommonBits_T_66[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_67 = _uncommonBits_T_67[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_68 = _uncommonBits_T_68[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_69 = _uncommonBits_T_69[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_70 = _uncommonBits_T_70[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_71 = _uncommonBits_T_71[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_54 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_60 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_66 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_72 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_78 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_84 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_90 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_96 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire _source_ok_T_55 = &_source_ok_T_54; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = source_ok_uncommonBits_8 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_59 = _source_ok_T_57 & _source_ok_T_58; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 3'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = source_ok_uncommonBits_9 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_65 = _source_ok_T_63 & _source_ok_T_64; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_1 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 3'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_10 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_2 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_73 = _source_ok_T_72 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = source_ok_uncommonBits_11 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_77 = _source_ok_T_75 & _source_ok_T_76; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_3 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_79 = _source_ok_T_78 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = source_ok_uncommonBits_12 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_83 = _source_ok_T_81 & _source_ok_T_82; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_4 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_85 = _source_ok_T_84 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = source_ok_uncommonBits_13 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_89 = _source_ok_T_87 & _source_ok_T_88; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_91 = _source_ok_T_90 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_94 = source_ok_uncommonBits_14 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_6 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_97 = _source_ok_T_96 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_99 = _source_ok_T_97; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_100 = source_ok_uncommonBits_15 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_101 = _source_ok_T_99 & _source_ok_T_100; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_107 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1162 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1235 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1235; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1235; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1235; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [243:0] inflight; // @[Monitor.scala:614:27] reg [975:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [975:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [243:0] a_set; // @[Monitor.scala:626:34] wire [243:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [975:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [975:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [975:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [975:0] _a_opcode_lookup_T_6 = {972'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [975:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [975:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [975:0] _a_size_lookup_T_6 = {972'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [975:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[975:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_1088 = _T_1162 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1088 ? _a_set_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1088 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1088 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1088 ? _a_opcodes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1088 ? _a_sizes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [243:0] d_clr; // @[Monitor.scala:664:34] wire [243:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [975:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [975:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1134 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1134 & ~d_release_ack ? _d_clr_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_1103 = _T_1235 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1103 ? _d_clr_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1103 ? _d_opcodes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1103 ? _d_sizes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [243:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [243:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [243:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [975:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [975:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [975:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [975:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [975:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [975:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [243:0] inflight_1; // @[Monitor.scala:726:35] wire [243:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [975:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [975:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [975:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [975:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [975:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [975:0] _c_opcode_lookup_T_6 = {972'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [975:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [975:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [975:0] _c_size_lookup_T_6 = {972'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [975:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[975:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [243:0] d_clr_1; // @[Monitor.scala:774:34] wire [243:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [975:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [975:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1206 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1206 & d_release_ack_1 ? _d_clr_wo_ready_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_1188 = _T_1235 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1188 ? _d_clr_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1188 ? _d_opcodes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1188 ? _d_sizes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [243:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [243:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [975:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [975:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [975:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [975:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_41 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready	module TLBuffer_a32d64s2k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLROM : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in wire rom : UInt<64>[512] connect rom[0], UInt<64>(0h405051300000517) connect rom[1], UInt<64>(0h301022f330551073) connect rom[2], UInt<64>(0h12f2934122d293) connect rom[3], UInt<64>(0h3030107300028863) connect rom[4], UInt<64>(0h3445307322200513) connect rom[5], UInt<64>(0h3045107300800513) connect rom[6], UInt<64>(0h1050007330052073) connect rom[7], UInt<64>(0hffdff06f) connect rom[8], UInt<64>(0hf1402573020005b7) connect rom[9], UInt<64>(0h380006f00050463) connect rom[10], UInt<64>(0h10069300458613) connect rom[11], UInt<64>(0h46061300d62023) connect rom[12], UInt<64>(0hfe069ae3ffc62683) connect rom[13], UInt<64>(0h2c0006f) connect rom[14], UInt<64>(0h0) connect rom[15], UInt<64>(0h0) connect rom[16], UInt<64>(0h5a283f81ff06f) connect rom[17], UInt<64>(0h251513fe029ee3) connect rom[18], UInt<64>(0h5a02300b505b3) connect rom[19], UInt<64>(0h5350300001537) connect rom[20], UInt<64>(0hf140257334151073) connect rom[21], UInt<64>(0h185859300000597) connect rom[22], UInt<64>(0h3006307308000613) connect rom[23], UInt<64>(0h1330200073) connect rom[24], UInt<64>(0h2b0b0000edfe0dd0) connect rom[25], UInt<64>(0h6809000038000000) connect rom[26], UInt<64>(0h1100000028000000) connect rom[27], UInt<64>(0h10000000) connect rom[28], UInt<64>(0h30090000c3010000) connect rom[29], UInt<64>(0h0) connect rom[30], UInt<64>(0h0) connect rom[31], UInt<64>(0h1000000) connect rom[32], UInt<64>(0h400000003000000) connect rom[33], UInt<64>(0h100000000000000) connect rom[34], UInt<64>(0h400000003000000) connect rom[35], UInt<64>(0h10000000f000000) connect rom[36], UInt<64>(0h1500000003000000) connect rom[37], UInt<64>(0h2d6263751b000000) connect rom[38], UInt<64>(0h706968632c726162) connect rom[39], UInt<64>(0h7665642d64726179) connect rom[40], UInt<64>(0h300000000000000) connect rom[41], UInt<64>(0h2600000011000000) connect rom[42], UInt<64>(0h2c7261622d626375) connect rom[43], UInt<64>(0h6472617970696863) connect rom[44], UInt<64>(0h100000000000000) connect rom[45], UInt<64>(0h73657361696c61) connect rom[46], UInt<64>(0h1500000003000000) connect rom[47], UInt<64>(0h636f732f2c000000) connect rom[48], UInt<64>(0h406c61697265732f) connect rom[49], UInt<64>(0h3030303032303031) connect rom[50], UInt<64>(0h200000000000000) connect rom[51], UInt<64>(0h736f686301000000) connect rom[52], UInt<64>(0h300000000006e65) connect rom[53], UInt<64>(0h3400000015000000) connect rom[54], UInt<64>(0h7265732f636f732f) connect rom[55], UInt<64>(0h32303031406c6169) connect rom[56], UInt<64>(0h30303030) connect rom[57], UInt<64>(0h100000002000000) connect rom[58], UInt<64>(0h73757063) connect rom[59], UInt<64>(0h400000003000000) connect rom[60], UInt<64>(0h100000000000000) connect rom[61], UInt<64>(0h400000003000000) connect rom[62], UInt<64>(0hf000000) connect rom[63], UInt<64>(0h400000003000000) connect rom[64], UInt<64>(0h20a1070040000000) connect rom[65], UInt<64>(0h4075706301000000) connect rom[66], UInt<64>(0h300000000000030) connect rom[67], UInt<64>(0h5300000004000000) connect rom[68], UInt<64>(0h300000000000000) connect rom[69], UInt<64>(0h1b00000015000000) connect rom[70], UInt<64>(0h722c657669666973) connect rom[71], UInt<64>(0h72003074656b636f) connect rom[72], UInt<64>(0h76637369) connect rom[73], UInt<64>(0h400000003000000) connect rom[74], UInt<64>(0h75706363000000) connect rom[75], UInt<64>(0h400000003000000) connect rom[76], UInt<64>(0h10000006f000000) connect rom[77], UInt<64>(0h400000003000000) connect rom[78], UInt<64>(0h400000008e000000) connect rom[79], UInt<64>(0h400000003000000) connect rom[80], UInt<64>(0h40000000a1000000) connect rom[81], UInt<64>(0h400000003000000) connect rom[82], UInt<64>(0h800000ae000000) connect rom[83], UInt<64>(0h400000003000000) connect rom[84], UInt<64>(0hbb000000) connect rom[85], UInt<64>(0h3800000003000000) connect rom[86], UInt<64>(0h34367672bf000000) connect rom[87], UInt<64>(0h7a62636466616d69) connect rom[88], UInt<64>(0h66697a5f72736369) connect rom[89], UInt<64>(0h697a5f6965636e65) connect rom[90], UInt<64>(0h5f68667a5f6d7068) connect rom[91], UInt<64>(0h5f62627a5f61627a) connect rom[92], UInt<64>(0h636f72785f73627a) connect rom[93], UInt<64>(0h30000000074656b) connect rom[94], UInt<64>(0hc900000004000000) connect rom[95], UInt<64>(0h300000004000000) connect rom[96], UInt<64>(0hde00000004000000) connect rom[97], UInt<64>(0h300000008000000) connect rom[98], UInt<64>(0hef00000004000000) connect rom[99], UInt<64>(0h300000001000000) connect rom[100], UInt<64>(0hfb00000005000000) connect rom[101], UInt<64>(0h79616b6f) connect rom[102], UInt<64>(0h400000003000000) connect rom[103], UInt<64>(0h20a1070040000000) connect rom[104], UInt<64>(0h65746e6901000000) connect rom[105], UInt<64>(0h6f632d7470757272) connect rom[106], UInt<64>(0h72656c6c6f72746e) connect rom[107], UInt<64>(0h300000000000000) connect rom[108], UInt<64>(0h201000004000000) connect rom[109], UInt<64>(0h300000001000000) connect rom[110], UInt<64>(0h1b0000000f000000) connect rom[111], UInt<64>(0h70632c7663736972) connect rom[112], UInt<64>(0h63746e692d75) connect rom[113], UInt<64>(0h3000000) connect rom[114], UInt<64>(0h300000013010000) connect rom[115], UInt<64>(0h2801000004000000) connect rom[116], UInt<64>(0h200000002000000) connect rom[117], UInt<64>(0h200000002000000) connect rom[118], UInt<64>(0h6669746801000000) connect rom[119], UInt<64>(0h300000000000000) connect rom[120], UInt<64>(0h1b0000000a000000) connect rom[121], UInt<64>(0h666974682c626375) connect rom[122], UInt<64>(0h200000000000030) connect rom[123], UInt<64>(0h636f7301000000) connect rom[124], UInt<64>(0h400000003000000) connect rom[125], UInt<64>(0h100000000000000) connect rom[126], UInt<64>(0h400000003000000) connect rom[127], UInt<64>(0h10000000f000000) connect rom[128], UInt<64>(0h2000000003000000) connect rom[129], UInt<64>(0h2d6263751b000000) connect rom[130], UInt<64>(0h706968632c726162) connect rom[131], UInt<64>(0h636f732d64726179) connect rom[132], UInt<64>(0h2d656c706d697300) connect rom[133], UInt<64>(0h300000000737562) connect rom[134], UInt<64>(0h3001000000000000) connect rom[135], UInt<64>(0h746f6f6201000000) connect rom[136], UInt<64>(0h737365726464612d) connect rom[137], UInt<64>(0h303031406765722d) connect rom[138], UInt<64>(0h300000000000030) connect rom[139], UInt<64>(0hbb00000008000000) connect rom[140], UInt<64>(0h10000000100000) connect rom[141], UInt<64>(0h800000003000000) connect rom[142], UInt<64>(0h746e6f6337010000) connect rom[143], UInt<64>(0h2000000006c6f72) connect rom[144], UInt<64>(0h7375626301000000) connect rom[145], UInt<64>(0h6b636f6c635f) connect rom[146], UInt<64>(0h400000003000000) connect rom[147], UInt<64>(0h41010000) connect rom[148], UInt<64>(0h400000003000000) connect rom[149], UInt<64>(0h65cd1d53000000) connect rom[150], UInt<64>(0hb00000003000000) connect rom[151], UInt<64>(0h737562634e010000) connect rom[152], UInt<64>(0h6b636f6c635f) connect rom[153], UInt<64>(0hc00000003000000) connect rom[154], UInt<64>(0h657869661b000000) connect rom[155], UInt<64>(0h6b636f6c632d64) connect rom[156], UInt<64>(0h100000002000000) connect rom[157], UInt<64>(0h303240746e696c63) connect rom[158], UInt<64>(0h3030303030) connect rom[159], UInt<64>(0hd00000003000000) connect rom[160], UInt<64>(0h637369721b000000) connect rom[161], UInt<64>(0h30746e696c632c76) connect rom[162], UInt<64>(0h300000000000000) connect rom[163], UInt<64>(0h6101000010000000) connect rom[164], UInt<64>(0h300000002000000) connect rom[165], UInt<64>(0h700000002000000) connect rom[166], UInt<64>(0h800000003000000) connect rom[167], UInt<64>(0h2bb000000) connect rom[168], UInt<64>(0h300000000000100) connect rom[169], UInt<64>(0h3701000008000000) connect rom[170], UInt<64>(0h6c6f72746e6f63) connect rom[171], UInt<64>(0h100000002000000) connect rom[172], UInt<64>(0h61672d6b636f6c63) connect rom[173], UInt<64>(0h3030303140726574) connect rom[174], UInt<64>(0h300000000003030) connect rom[175], UInt<64>(0hbb00000008000000) connect rom[176], UInt<64>(0h10000000001000) connect rom[177], UInt<64>(0h800000003000000) connect rom[178], UInt<64>(0h746e6f6337010000) connect rom[179], UInt<64>(0h2000000006c6f72) connect rom[180], UInt<64>(0h7562656401000000) connect rom[181], UInt<64>(0h6f72746e6f632d67) connect rom[182], UInt<64>(0h304072656c6c) connect rom[183], UInt<64>(0h2100000003000000) connect rom[184], UInt<64>(0h696669731b000000) connect rom[185], UInt<64>(0h67756265642c6576) connect rom[186], UInt<64>(0h736972003331302d) connect rom[187], UInt<64>(0h67756265642c7663) connect rom[188], UInt<64>(0h3331302d) connect rom[189], UInt<64>(0h500000003000000) connect rom[190], UInt<64>(0h6761746a75010000) connect rom[191], UInt<64>(0h300000000000000) connect rom[192], UInt<64>(0h6101000008000000) connect rom[193], UInt<64>(0hffff000002000000) connect rom[194], UInt<64>(0h800000003000000) connect rom[195], UInt<64>(0hbb000000) connect rom[196], UInt<64>(0h300000000100000) connect rom[197], UInt<64>(0h3701000008000000) connect rom[198], UInt<64>(0h6c6f72746e6f63) connect rom[199], UInt<64>(0h100000002000000) connect rom[200], UInt<64>(0h303038406d697464) connect rom[201], UInt<64>(0h3030303030) connect rom[202], UInt<64>(0hd00000003000000) connect rom[203], UInt<64>(0h696669731b000000) connect rom[204], UInt<64>(0h306d6974642c6576) connect rom[205], UInt<64>(0h300000000000000) connect rom[206], UInt<64>(0hbb00000008000000) connect rom[207], UInt<64>(0h40000000000080) connect rom[208], UInt<64>(0h400000003000000) connect rom[209], UInt<64>(0h6d656d37010000) connect rom[210], UInt<64>(0h400000003000000) connect rom[211], UInt<64>(0h100000028010000) connect rom[212], UInt<64>(0h100000002000000) connect rom[213], UInt<64>(0h65642d726f727265) connect rom[214], UInt<64>(0h3030334065636976) connect rom[215], UInt<64>(0h300000000000030) connect rom[216], UInt<64>(0h1b0000000e000000) connect rom[217], UInt<64>(0h652c657669666973) connect rom[218], UInt<64>(0h30726f7272) connect rom[219], UInt<64>(0h800000003000000) connect rom[220], UInt<64>(0h300000bb000000) connect rom[221], UInt<64>(0h200000000100000) connect rom[222], UInt<64>(0h7375626601000000) connect rom[223], UInt<64>(0h6b636f6c635f) connect rom[224], UInt<64>(0h400000003000000) connect rom[225], UInt<64>(0h41010000) connect rom[226], UInt<64>(0h400000003000000) connect rom[227], UInt<64>(0h65cd1d53000000) connect rom[228], UInt<64>(0hb00000003000000) connect rom[229], UInt<64>(0h737562664e010000) connect rom[230], UInt<64>(0h6b636f6c635f) connect rom[231], UInt<64>(0hc00000003000000) connect rom[232], UInt<64>(0h657869661b000000) connect rom[233], UInt<64>(0h6b636f6c632d64) connect rom[234], UInt<64>(0h100000002000000) connect rom[235], UInt<64>(0h7075727265746e69) connect rom[236], UInt<64>(0h6f72746e6f632d74) connect rom[237], UInt<64>(0h3030634072656c6c) connect rom[238], UInt<64>(0h30303030) connect rom[239], UInt<64>(0h400000003000000) connect rom[240], UInt<64>(0h100000002010000) connect rom[241], UInt<64>(0hc00000003000000) connect rom[242], UInt<64>(0h637369721b000000) connect rom[243], UInt<64>(0h3063696c702c76) connect rom[244], UInt<64>(0h3000000) connect rom[245], UInt<64>(0h300000013010000) connect rom[246], UInt<64>(0h6101000008000000) connect rom[247], UInt<64>(0hb00000002000000) connect rom[248], UInt<64>(0h800000003000000) connect rom[249], UInt<64>(0hcbb000000) connect rom[250], UInt<64>(0h300000000000004) connect rom[251], UInt<64>(0h3701000008000000) connect rom[252], UInt<64>(0h6c6f72746e6f63) connect rom[253], UInt<64>(0h400000003000000) connect rom[254], UInt<64>(0h100000082010000) connect rom[255], UInt<64>(0h400000003000000) connect rom[256], UInt<64>(0h100000095010000) connect rom[257], UInt<64>(0h400000003000000) connect rom[258], UInt<64>(0h400000028010000) connect rom[259], UInt<64>(0h100000002000000) connect rom[260], UInt<64>(0h6f6c635f73756270) connect rom[261], UInt<64>(0h300000000006b63) connect rom[262], UInt<64>(0h4101000004000000) connect rom[263], UInt<64>(0h300000000000000) connect rom[264], UInt<64>(0h5300000004000000) connect rom[265], UInt<64>(0h30000000065cd1d) connect rom[266], UInt<64>(0h4e0100000b000000) connect rom[267], UInt<64>(0h6f6c635f73756270) connect rom[268], UInt<64>(0h300000000006b63) connect rom[269], UInt<64>(0h1b0000000c000000) connect rom[270], UInt<64>(0h6c632d6465786966) connect rom[271], UInt<64>(0h3000000006b636f) connect rom[272], UInt<64>(0h2801000004000000) connect rom[273], UInt<64>(0h200000003000000) connect rom[274], UInt<64>(0h406d6f7201000000) connect rom[275], UInt<64>(0h3030303031) connect rom[276], UInt<64>(0hc00000003000000) connect rom[277], UInt<64>(0h696669731b000000) connect rom[278], UInt<64>(0h306d6f722c6576) connect rom[279], UInt<64>(0h800000003000000) connect rom[280], UInt<64>(0h100bb000000) connect rom[281], UInt<64>(0h300000000000100) connect rom[282], UInt<64>(0h3701000004000000) connect rom[283], UInt<64>(0h2000000006d656d) connect rom[284], UInt<64>(0h7375627301000000) connect rom[285], UInt<64>(0h6b636f6c635f) connect rom[286], UInt<64>(0h400000003000000) connect rom[287], UInt<64>(0h41010000) connect rom[288], UInt<64>(0h400000003000000) connect rom[289], UInt<64>(0h65cd1d53000000) connect rom[290], UInt<64>(0hb00000003000000) connect rom[291], UInt<64>(0h737562734e010000) connect rom[292], UInt<64>(0h6b636f6c635f) connect rom[293], UInt<64>(0hc00000003000000) connect rom[294], UInt<64>(0h657869661b000000) connect rom[295], UInt<64>(0h6b636f6c632d64) connect rom[296], UInt<64>(0h100000002000000) connect rom[297], UInt<64>(0h31406c6169726573) connect rom[298], UInt<64>(0h30303030323030) connect rom[299], UInt<64>(0h400000003000000) connect rom[300], UInt<64>(0h3000000a0010000) connect rom[301], UInt<64>(0hd00000003000000) connect rom[302], UInt<64>(0h696669731b000000) connect rom[303], UInt<64>(0h30747261752c6576) connect rom[304], UInt<64>(0h300000000000000) connect rom[305], UInt<64>(0ha701000004000000) connect rom[306], UInt<64>(0h300000004000000) connect rom[307], UInt<64>(0hb801000004000000) connect rom[308], UInt<64>(0h300000001000000) connect rom[309], UInt<64>(0hbb00000008000000) connect rom[310], UInt<64>(0h10000000000210) connect rom[311], UInt<64>(0h800000003000000) connect rom[312], UInt<64>(0h746e6f6337010000) connect rom[313], UInt<64>(0h2000000006c6f72) connect rom[314], UInt<64>(0h656c697401000000) connect rom[315], UInt<64>(0h732d74657365722d) connect rom[316], UInt<64>(0h3131407265747465) connect rom[317], UInt<64>(0h30303030) connect rom[318], UInt<64>(0h800000003000000) connect rom[319], UInt<64>(0h1100bb000000) connect rom[320], UInt<64>(0h300000000100000) connect rom[321], UInt<64>(0h3701000008000000) connect rom[322], UInt<64>(0h6c6f72746e6f63) connect rom[323], UInt<64>(0h200000002000000) connect rom[324], UInt<64>(0h900000002000000) connect rom[325], UInt<64>(0h7373657264646123) connect rom[326], UInt<64>(0h2300736c6c65632d) connect rom[327], UInt<64>(0h6c65632d657a6973) connect rom[328], UInt<64>(0h61706d6f6300736c) connect rom[329], UInt<64>(0h6f6d00656c626974) connect rom[330], UInt<64>(0h69726573006c6564) connect rom[331], UInt<64>(0h6f64747300306c61) connect rom[332], UInt<64>(0h687461702d7475) connect rom[333], UInt<64>(0h65736162656d6974) connect rom[334], UInt<64>(0h6e6575716572662d) connect rom[335], UInt<64>(0h6b636f6c63007963) connect rom[336], UInt<64>(0h6e6575716572662d) connect rom[337], UInt<64>(0h6369766564007963) connect rom[338], UInt<64>(0h6800657079745f65) connect rom[339], UInt<64>(0h2d65726177647261) connect rom[340], UInt<64>(0h6572622d63657865) connect rom[341], UInt<64>(0h2d746e696f706b61) connect rom[342], UInt<64>(0h2d6900746e756f63) connect rom[343], UInt<64>(0h6c622d6568636163) connect rom[344], UInt<64>(0h657a69732d6b636f) connect rom[345], UInt<64>(0h65686361632d6900) connect rom[346], UInt<64>(0h2d6900737465732d) connect rom[347], UInt<64>(0h69732d6568636163) connect rom[348], UInt<64>(0h720067657200657a) connect rom[349], UInt<64>(0h6173692c76637369) connect rom[350], UInt<64>(0h702c766373697200) connect rom[351], UInt<64>(0h6c756e617267706d) connect rom[352], UInt<64>(0h6972007974697261) connect rom[353], UInt<64>(0h72706d702c766373) connect rom[354], UInt<64>(0h7300736e6f696765) connect rom[355], UInt<64>(0h74642c6576696669) connect rom[356], UInt<64>(0h7574617473006d69) connect rom[357], UInt<64>(0h7265746e69230073) connect rom[358], UInt<64>(0h6c65632d74707572) connect rom[359], UInt<64>(0h7265746e6900736c) connect rom[360], UInt<64>(0h6e6f632d74707572) connect rom[361], UInt<64>(0h72656c6c6f7274) connect rom[362], UInt<64>(0h656c646e616870) connect rom[363], UInt<64>(0h72007365676e6172) connect rom[364], UInt<64>(0h73656d616e2d6765) connect rom[365], UInt<64>(0h2d6b636f6c632300) connect rom[366], UInt<64>(0h6c6300736c6c6563) connect rom[367], UInt<64>(0h7074756f2d6b636f) connect rom[368], UInt<64>(0h73656d616e2d7475) connect rom[369], UInt<64>(0h75727265746e6900) connect rom[370], UInt<64>(0h657478652d737470) connect rom[371], UInt<64>(0h626564006465646e) connect rom[372], UInt<64>(0h63617474612d6775) connect rom[373], UInt<64>(0h2c76637369720068) connect rom[374], UInt<64>(0h6f6972702d78616d) connect rom[375], UInt<64>(0h7369720079746972) connect rom[376], UInt<64>(0h7665646e2c7663) connect rom[377], UInt<64>(0h6900736b636f6c63) connect rom[378], UInt<64>(0h747075727265746e) connect rom[379], UInt<64>(0h746e657261702d) connect rom[380], UInt<64>(0h7075727265746e69) connect rom[381], UInt<64>(0h7374) connect rom[382], UInt<64>(0h0) connect rom[383], UInt<64>(0h0) connect rom[384], UInt<64>(0h0) connect rom[385], UInt<64>(0h0) connect rom[386], UInt<64>(0h0) connect rom[387], UInt<64>(0h0) connect rom[388], UInt<64>(0h0) connect rom[389], UInt<64>(0h0) connect rom[390], UInt<64>(0h0) connect rom[391], UInt<64>(0h0) connect rom[392], UInt<64>(0h0) connect rom[393], UInt<64>(0h0) connect rom[394], UInt<64>(0h0) connect rom[395], UInt<64>(0h0) connect rom[396], UInt<64>(0h0) connect rom[397], UInt<64>(0h0) connect rom[398], UInt<64>(0h0) connect rom[399], UInt<64>(0h0) connect rom[400], UInt<64>(0h0) connect rom[401], UInt<64>(0h0) connect rom[402], UInt<64>(0h0) connect rom[403], UInt<64>(0h0) connect rom[404], UInt<64>(0h0) connect rom[405], UInt<64>(0h0) connect rom[406], UInt<64>(0h0) connect rom[407], UInt<64>(0h0) connect rom[408], UInt<64>(0h0) connect rom[409], UInt<64>(0h0) connect rom[410], UInt<64>(0h0) connect rom[411], UInt<64>(0h0) connect rom[412], UInt<64>(0h0) connect rom[413], UInt<64>(0h0) connect rom[414], UInt<64>(0h0) connect rom[415], UInt<64>(0h0) connect rom[416], UInt<64>(0h0) connect rom[417], UInt<64>(0h0) connect rom[418], UInt<64>(0h0) connect rom[419], UInt<64>(0h0) connect rom[420], UInt<64>(0h0) connect rom[421], UInt<64>(0h0) connect rom[422], UInt<64>(0h0) connect rom[423], UInt<64>(0h0) connect rom[424], UInt<64>(0h0) connect rom[425], UInt<64>(0h0) connect rom[426], UInt<64>(0h0) connect rom[427], UInt<64>(0h0) connect rom[428], UInt<64>(0h0) connect rom[429], UInt<64>(0h0) connect rom[430], UInt<64>(0h0) connect rom[431], UInt<64>(0h0) connect rom[432], UInt<64>(0h0) connect rom[433], UInt<64>(0h0) connect rom[434], UInt<64>(0h0) connect rom[435], UInt<64>(0h0) connect rom[436], UInt<64>(0h0) connect rom[437], UInt<64>(0h0) connect rom[438], UInt<64>(0h0) connect rom[439], UInt<64>(0h0) connect rom[440], UInt<64>(0h0) connect rom[441], UInt<64>(0h0) connect rom[442], UInt<64>(0h0) connect rom[443], UInt<64>(0h0) connect rom[444], UInt<64>(0h0) connect rom[445], UInt<64>(0h0) connect rom[446], UInt<64>(0h0) connect rom[447], UInt<64>(0h0) connect rom[448], UInt<64>(0h0) connect rom[449], UInt<64>(0h0) connect rom[450], UInt<64>(0h0) connect rom[451], UInt<64>(0h0) connect rom[452], UInt<64>(0h0) connect rom[453], UInt<64>(0h0) connect rom[454], UInt<64>(0h0) connect rom[455], UInt<64>(0h0) connect rom[456], UInt<64>(0h0) connect rom[457], UInt<64>(0h0) connect rom[458], UInt<64>(0h0) connect rom[459], UInt<64>(0h0) connect rom[460], UInt<64>(0h0) connect rom[461], UInt<64>(0h0) connect rom[462], UInt<64>(0h0) connect rom[463], UInt<64>(0h0) connect rom[464], UInt<64>(0h0) connect rom[465], UInt<64>(0h0) connect rom[466], UInt<64>(0h0) connect rom[467], UInt<64>(0h0) connect rom[468], UInt<64>(0h0) connect rom[469], UInt<64>(0h0) connect rom[470], UInt<64>(0h0) connect rom[471], UInt<64>(0h0) connect rom[472], UInt<64>(0h0) connect rom[473], UInt<64>(0h0) connect rom[474], UInt<64>(0h0) connect rom[475], UInt<64>(0h0) connect rom[476], UInt<64>(0h0) connect rom[477], UInt<64>(0h0) connect rom[478], UInt<64>(0h0) connect rom[479], UInt<64>(0h0) connect rom[480], UInt<64>(0h0) connect rom[481], UInt<64>(0h0) connect rom[482], UInt<64>(0h0) connect rom[483], UInt<64>(0h0) connect rom[484], UInt<64>(0h0) connect rom[485], UInt<64>(0h0) connect rom[486], UInt<64>(0h0) connect rom[487], UInt<64>(0h0) connect rom[488], UInt<64>(0h0) connect rom[489], UInt<64>(0h0) connect rom[490], UInt<64>(0h0) connect rom[491], UInt<64>(0h0) connect rom[492], UInt<64>(0h0) connect rom[493], UInt<64>(0h0) connect rom[494], UInt<64>(0h0) connect rom[495], UInt<64>(0h0) connect rom[496], UInt<64>(0h0) connect rom[497], UInt<64>(0h0) connect rom[498], UInt<64>(0h0) connect rom[499], UInt<64>(0h0) connect rom[500], UInt<64>(0h0) connect rom[501], UInt<64>(0h0) connect rom[502], UInt<64>(0h0) connect rom[503], UInt<64>(0h0) connect rom[504], UInt<64>(0h0) connect rom[505], UInt<64>(0h0) connect rom[506], UInt<64>(0h0) connect rom[507], UInt<64>(0h0) connect rom[508], UInt<64>(0h0) connect rom[509], UInt<64>(0h0) connect rom[510], UInt<64>(0h0) connect rom[511], UInt<64>(0h0) connect nodeIn.d.valid, nodeIn.a.valid connect nodeIn.a.ready, nodeIn.d.ready node index = bits(nodeIn.a.bits.address, 11, 3) node high = bits(nodeIn.a.bits.address, 15, 12) node _nodeIn_d_bits_T = orr(high) node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, nodeIn.a.bits.size connect nodeIn_d_bits_d.source, nodeIn.a.bits.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module TLROM( // @[BootROM.scala:41:9] input clock, // @[BootROM.scala:41:9] input reset, // @[BootROM.scala:41:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9] wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9] wire [511:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h7374, 64'h7075727265746E69, 64'h746E657261702D, 64'h747075727265746E, 64'h6900736B636F6C63, 64'h7665646E2C7663, 64'h7369720079746972, 64'h6F6972702D78616D, 64'h2C76637369720068, 64'h63617474612D6775, 64'h626564006465646E, 64'h657478652D737470, 64'h75727265746E6900, 64'h73656D616E2D7475, 64'h7074756F2D6B636F, 64'h6C6300736C6C6563, 64'h2D6B636F6C632300, 64'h73656D616E2D6765, 64'h72007365676E6172, 64'h656C646E616870, 64'h72656C6C6F7274, 64'h6E6F632D74707572, 64'h7265746E6900736C, 64'h6C65632D74707572, 64'h7265746E69230073, 64'h7574617473006D69, 64'h74642C6576696669, 64'h7300736E6F696765, 64'h72706D702C766373, 64'h6972007974697261, 64'h6C756E617267706D, 64'h702C766373697200, 64'h6173692C76637369, 64'h720067657200657A, 64'h69732D6568636163, 64'h2D6900737465732D, 64'h65686361632D6900, 64'h657A69732D6B636F, 64'h6C622D6568636163, 64'h2D6900746E756F63, 64'h2D746E696F706B61, 64'h6572622D63657865, 64'h2D65726177647261, 64'h6800657079745F65, 64'h6369766564007963, 64'h6E6575716572662D, 64'h6B636F6C63007963, 64'h6E6575716572662D, 64'h65736162656D6974, 64'h687461702D7475, 64'h6F64747300306C61, 64'h69726573006C6564, 64'h6F6D00656C626974, 64'h61706D6F6300736C, 64'h6C65632D657A6973, 64'h2300736C6C65632D, 64'h7373657264646123, 64'h900000002000000, 64'h200000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000100000, 64'h1100BB000000, 64'h800000003000000, 64'h30303030, 64'h3131407265747465, 64'h732D74657365722D, 64'h656C697401000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000000210, 64'hBB00000008000000, 64'h300000001000000, 64'hB801000004000000, 64'h300000004000000, 64'hA701000004000000, 64'h300000000000000, 64'h30747261752C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h3000000A0010000, 64'h400000003000000, 64'h30303030323030, 64'h31406C6169726573, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562734E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375627301000000, 64'h2000000006D656D, 64'h3701000004000000, 64'h300000000000100, 64'h100BB000000, 64'h800000003000000, 64'h306D6F722C6576, 64'h696669731B000000, 64'hC00000003000000, 64'h3030303031, 64'h406D6F7201000000, 64'h200000003000000, 64'h2801000004000000, 64'h3000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h4E0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'h4101000004000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h100000002000000, 64'h400000028010000, 64'h400000003000000, 64'h100000095010000, 64'h400000003000000, 64'h100000082010000, 64'h400000003000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000000004, 64'hCBB000000, 64'h800000003000000, 64'hB00000002000000, 64'h6101000008000000, 64'h300000013010000, 64'h3000000, 64'h3063696C702C76, 64'h637369721B000000, 64'hC00000003000000, 64'h100000002010000, 64'h400000003000000, 64'h30303030, 64'h3030634072656C6C, 64'h6F72746E6F632D74, 64'h7075727265746E69, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562664E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626601000000, 64'h200000000100000, 64'h300000BB000000, 64'h800000003000000, 64'h30726F7272, 64'h652C657669666973, 64'h1B0000000E000000, 64'h300000000000030, 64'h3030334065636976, 64'h65642D726F727265, 64'h100000002000000, 64'h100000028010000, 64'h400000003000000, 64'h6D656D37010000, 64'h400000003000000, 64'h40000000000080, 64'hBB00000008000000, 64'h300000000000000, 64'h306D6974642C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h3030303030, 64'h303038406D697464, 64'h100000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000100000, 64'hBB000000, 64'h800000003000000, 64'hFFFF000002000000, 64'h6101000008000000, 64'h300000000000000, 64'h6761746A75010000, 64'h500000003000000, 64'h3331302D, 64'h67756265642C7663, 64'h736972003331302D, 64'h67756265642C6576, 64'h696669731B000000, 64'h2100000003000000, 64'h304072656C6C, 64'h6F72746E6F632D67, 64'h7562656401000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000001000, 64'hBB00000008000000, 64'h300000000003030, 64'h3030303140726574, 64'h61672D6B636F6C63, 64'h100000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000000100, 64'h2BB000000, 64'h800000003000000, 64'h700000002000000, 64'h300000002000000, 64'h6101000010000000, 64'h300000000000000, 64'h30746E696C632C76, 64'h637369721B000000, 64'hD00000003000000, 64'h3030303030, 64'h303240746E696C63, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562634E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626301000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000100000, 64'hBB00000008000000, 64'h300000000000030, 64'h303031406765722D, 64'h737365726464612D, 64'h746F6F6201000000, 64'h3001000000000000, 64'h300000000737562, 64'h2D656C706D697300, 64'h636F732D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h2000000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h636F7301000000, 64'h200000000000030, 64'h666974682C626375, 64'h1B0000000A000000, 64'h300000000000000, 64'h6669746801000000, 64'h200000002000000, 64'h200000002000000, 64'h2801000004000000, 64'h300000013010000, 64'h3000000, 64'h63746E692D75, 64'h70632C7663736972, 64'h1B0000000F000000, 64'h300000001000000, 64'h201000004000000, 64'h300000000000000, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6901000000, 64'h20A1070040000000, 64'h400000003000000, 64'h79616B6F, 64'hFB00000005000000, 64'h300000001000000, 64'hEF00000004000000, 64'h300000008000000, 64'hDE00000004000000, 64'h300000004000000, 64'hC900000004000000, 64'h30000000074656B, 64'h636F72785F73627A, 64'h5F62627A5F61627A, 64'h5F68667A5F6D7068, 64'h697A5F6965636E65, 64'h66697A5F72736369, 64'h7A62636466616D69, 64'h34367672BF000000, 64'h3800000003000000, 64'hBB000000, 64'h400000003000000, 64'h800000AE000000, 64'h400000003000000, 64'h40000000A1000000, 64'h400000003000000, 64'h400000008E000000, 64'h400000003000000, 64'h10000006F000000, 64'h400000003000000, 64'h75706363000000, 64'h400000003000000, 64'h76637369, 64'h72003074656B636F, 64'h722C657669666973, 64'h1B00000015000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000030, 64'h4075706301000000, 64'h20A1070040000000, 64'h400000003000000, 64'hF000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h73757063, 64'h100000002000000, 64'h30303030, 64'h32303031406C6169, 64'h7265732F636F732F, 64'h3400000015000000, 64'h300000000006E65, 64'h736F686301000000, 64'h200000000000000, 64'h3030303032303031, 64'h406C61697265732F, 64'h636F732F2C000000, 64'h1500000003000000, 64'h73657361696C61, 64'h100000000000000, 64'h6472617970696863, 64'h2C7261622D626375, 64'h2600000011000000, 64'h300000000000000, 64'h7665642D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h1500000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h1000000, 64'h0, 64'h0, 64'h30090000C3010000, 64'h10000000, 64'h1100000028000000, 64'h6809000038000000, 64'h2B0B0000EDFE0DD0, 64'h1330200073, 64'h3006307308000613, 64'h185859300000597, 64'hF140257334151073, 64'h5350300001537, 64'h5A02300B505B3, 64'h251513FE029EE3, 64'h5A283F81FF06F, 64'h0, 64'h0, 64'h2C0006F, 64'hFE069AE3FFC62683, 64'h46061300D62023, 64'h10069300458613, 64'h380006F00050463, 64'hF1402573020005B7, 64'hFFDFF06F, 64'h1050007330052073, 64'h3045107300800513, 64'h3445307322200513, 64'h3030107300028863, 64'h12F2934122D293, 64'h301022F330551073, 64'h405051300000517}; wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22] wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22] wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22] wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22] wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22] wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22] wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22] wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22] wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22] wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22] wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22] wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22] wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22] wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22] wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22] wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22] wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22] wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22] wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22] wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22] wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22] wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22] wire [63:0] rom_24 = 64'h2B0B0000EDFE0DD0; // @[BootROM.scala:50:22] wire [63:0] rom_25 = 64'h6809000038000000; // @[BootROM.scala:50:22] wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22] wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22] wire [63:0] rom_28 = 64'h30090000C3010000; // @[BootROM.scala:50:22] wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22] wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22] wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22] wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22] wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22] wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22] wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22] wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22] wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22] wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22] wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22] wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22] wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22] wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22] wire [63:0] rom_74 = 64'h75706363000000; // @[BootROM.scala:50:22] wire [63:0] rom_76 = 64'h10000006F000000; // @[BootROM.scala:50:22] wire [63:0] rom_78 = 64'h400000008E000000; // @[BootROM.scala:50:22] wire [63:0] rom_80 = 64'h40000000A1000000; // @[BootROM.scala:50:22] wire [63:0] rom_82 = 64'h800000AE000000; // @[BootROM.scala:50:22] wire [63:0] rom_85 = 64'h3800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_86 = 64'h34367672BF000000; // @[BootROM.scala:50:22] wire [63:0] rom_87 = 64'h7A62636466616D69; // @[BootROM.scala:50:22] wire [63:0] rom_88 = 64'h66697A5F72736369; // @[BootROM.scala:50:22] wire [63:0] rom_89 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22] wire [63:0] rom_90 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22] wire [63:0] rom_91 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22] wire [63:0] rom_92 = 64'h636F72785F73627A; // @[BootROM.scala:50:22] wire [63:0] rom_93 = 64'h30000000074656B; // @[BootROM.scala:50:22] wire [63:0] rom_94 = 64'hC900000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_96 = 64'hDE00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_97 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_98 = 64'hEF00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_100 = 64'hFB00000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_101 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_103 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_104 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_105 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_106 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_108 = 64'h201000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_110 = 64'h1B0000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_111 = 64'h70632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_112 = 64'h63746E692D75; // @[BootROM.scala:50:22] wire [63:0] rom_118 = 64'h6669746801000000; // @[BootROM.scala:50:22] wire [63:0] rom_120 = 64'h1B0000000A000000; // @[BootROM.scala:50:22] wire [63:0] rom_121 = 64'h666974682C626375; // @[BootROM.scala:50:22] wire [63:0] rom_122 = 64'h200000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_123 = 64'h636F7301000000; // @[BootROM.scala:50:22] wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_125 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_127 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_128 = 64'h2000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_129 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_130 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_131 = 64'h636F732D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_132 = 64'h2D656C706D697300; // @[BootROM.scala:50:22] wire [63:0] rom_133 = 64'h300000000737562; // @[BootROM.scala:50:22] wire [63:0] rom_134 = 64'h3001000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_135 = 64'h746F6F6201000000; // @[BootROM.scala:50:22] wire [63:0] rom_136 = 64'h737365726464612D; // @[BootROM.scala:50:22] wire [63:0] rom_137 = 64'h303031406765722D; // @[BootROM.scala:50:22] wire [63:0] rom_140 = 64'h10000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_144 = 64'h7375626301000000; // @[BootROM.scala:50:22] wire [63:0] rom_151 = 64'h737562634E010000; // @[BootROM.scala:50:22] wire [63:0] rom_157 = 64'h303240746E696C63; // @[BootROM.scala:50:22] wire [63:0] rom_161 = 64'h30746E696C632C76; // @[BootROM.scala:50:22] wire [63:0] rom_163 = 64'h6101000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_164 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_165 = 64'h700000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_167 = 64'h2BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_172 = 64'h61672D6B636F6C63; // @[BootROM.scala:50:22] wire [63:0] rom_173 = 64'h3030303140726574; // @[BootROM.scala:50:22] wire [63:0] rom_174 = 64'h300000000003030; // @[BootROM.scala:50:22] wire [63:0] rom_176 = 64'h10000000001000; // @[BootROM.scala:50:22] wire [63:0] rom_180 = 64'h7562656401000000; // @[BootROM.scala:50:22] wire [63:0] rom_181 = 64'h6F72746E6F632D67; // @[BootROM.scala:50:22] wire [63:0] rom_182 = 64'h304072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_183 = 64'h2100000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_185 = 64'h67756265642C6576; // @[BootROM.scala:50:22] wire [63:0] rom_186 = 64'h736972003331302D; // @[BootROM.scala:50:22] wire [63:0] rom_187 = 64'h67756265642C7663; // @[BootROM.scala:50:22] wire [63:0] rom_188 = 64'h3331302D; // @[BootROM.scala:50:22] wire [63:0] rom_189 = 64'h500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_190 = 64'h6761746A75010000; // @[BootROM.scala:50:22] wire [63:0] rom_193 = 64'hFFFF000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_84 = 64'hBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_195 = 64'hBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_200 = 64'h303038406D697464; // @[BootROM.scala:50:22] wire [63:0] rom_158 = 64'h3030303030; // @[BootROM.scala:50:22] wire [63:0] rom_201 = 64'h3030303030; // @[BootROM.scala:50:22] wire [63:0] rom_204 = 64'h306D6974642C6576; // @[BootROM.scala:50:22] wire [63:0] rom_207 = 64'h40000000000080; // @[BootROM.scala:50:22] wire [63:0] rom_209 = 64'h6D656D37010000; // @[BootROM.scala:50:22] wire [63:0] rom_211 = 64'h100000028010000; // @[BootROM.scala:50:22] wire [63:0] rom_213 = 64'h65642D726F727265; // @[BootROM.scala:50:22] wire [63:0] rom_214 = 64'h3030334065636976; // @[BootROM.scala:50:22] wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_138 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_215 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_216 = 64'h1B0000000E000000; // @[BootROM.scala:50:22] wire [63:0] rom_217 = 64'h652C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_218 = 64'h30726F7272; // @[BootROM.scala:50:22] wire [63:0] rom_220 = 64'h300000BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_221 = 64'h200000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_222 = 64'h7375626601000000; // @[BootROM.scala:50:22] wire [63:0] rom_229 = 64'h737562664E010000; // @[BootROM.scala:50:22] wire [63:0] rom_236 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_237 = 64'h3030634072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_240 = 64'h100000002010000; // @[BootROM.scala:50:22] wire [63:0] rom_160 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_242 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_243 = 64'h3063696C702C76; // @[BootROM.scala:50:22] wire [63:0] rom_113 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_244 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_114 = 64'h300000013010000; // @[BootROM.scala:50:22] wire [63:0] rom_245 = 64'h300000013010000; // @[BootROM.scala:50:22] wire [63:0] rom_192 = 64'h6101000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_246 = 64'h6101000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_247 = 64'hB00000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_249 = 64'hCBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_250 = 64'h300000000000004; // @[BootROM.scala:50:22] wire [63:0] rom_254 = 64'h100000082010000; // @[BootROM.scala:50:22] wire [63:0] rom_256 = 64'h100000095010000; // @[BootROM.scala:50:22] wire [63:0] rom_258 = 64'h400000028010000; // @[BootROM.scala:50:22] wire [63:0] rom_262 = 64'h4101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_264 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_265 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_266 = 64'h4E0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_260 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_267 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_261 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_268 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_269 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_270 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_271 = 64'h3000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_115 = 64'h2801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_272 = 64'h2801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_273 = 64'h200000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_274 = 64'h406D6F7201000000; // @[BootROM.scala:50:22] wire [63:0] rom_275 = 64'h3030303031; // @[BootROM.scala:50:22] wire [63:0] rom_278 = 64'h306D6F722C6576; // @[BootROM.scala:50:22] wire [63:0] rom_280 = 64'h100BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_168 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_281 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_282 = 64'h3701000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_283 = 64'h2000000006D656D; // @[BootROM.scala:50:22] wire [63:0] rom_284 = 64'h7375627301000000; // @[BootROM.scala:50:22] wire [63:0] rom_147 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_225 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_287 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_149 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_227 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_289 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_150 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_228 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_290 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_291 = 64'h737562734E010000; // @[BootROM.scala:50:22] wire [63:0] rom_145 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_152 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_223 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_230 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_285 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_292 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_153 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_231 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_241 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_276 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_293 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_154 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_232 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_294 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_155 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_233 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_295 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_156 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_171 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_199 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_212 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_234 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_259 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_296 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_297 = 64'h31406C6169726573; // @[BootROM.scala:50:22] wire [63:0] rom_298 = 64'h30303030323030; // @[BootROM.scala:50:22] wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_102 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_124 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_126 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_146 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_148 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_208 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_210 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_224 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_226 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_239 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_253 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_255 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_257 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_286 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_288 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_299 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_300 = 64'h3000000A0010000; // @[BootROM.scala:50:22] wire [63:0] rom_159 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_202 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_301 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_184 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_203 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_277 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_302 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_303 = 64'h30747261752C6576; // @[BootROM.scala:50:22] wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_107 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_119 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_162 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_191 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_205 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_263 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_304 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_305 = 64'hA701000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_95 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_306 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_307 = 64'hB801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_99 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_109 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_308 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_139 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_175 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_206 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_309 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_310 = 64'h10000000000210; // @[BootROM.scala:50:22] wire [63:0] rom_142 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_178 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_312 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_143 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_179 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_313 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_314 = 64'h656C697401000000; // @[BootROM.scala:50:22] wire [63:0] rom_315 = 64'h732D74657365722D; // @[BootROM.scala:50:22] wire [63:0] rom_316 = 64'h3131407265747465; // @[BootROM.scala:50:22] wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_238 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_317 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_141 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_166 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_177 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_194 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_219 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_248 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_279 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_311 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_318 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_319 = 64'h1100BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_196 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_320 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_169 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_197 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_251 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_321 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_170 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_198 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_252 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_322 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_116 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_117 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_323 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_324 = 64'h900000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_325 = 64'h7373657264646123; // @[BootROM.scala:50:22] wire [63:0] rom_326 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22] wire [63:0] rom_327 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22] wire [63:0] rom_328 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_329 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22] wire [63:0] rom_330 = 64'h69726573006C6564; // @[BootROM.scala:50:22] wire [63:0] rom_331 = 64'h6F64747300306C61; // @[BootROM.scala:50:22] wire [63:0] rom_332 = 64'h687461702D7475; // @[BootROM.scala:50:22] wire [63:0] rom_333 = 64'h65736162656D6974; // @[BootROM.scala:50:22] wire [63:0] rom_335 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22] wire [63:0] rom_334 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_336 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_337 = 64'h6369766564007963; // @[BootROM.scala:50:22] wire [63:0] rom_338 = 64'h6800657079745F65; // @[BootROM.scala:50:22] wire [63:0] rom_339 = 64'h2D65726177647261; // @[BootROM.scala:50:22] wire [63:0] rom_340 = 64'h6572622D63657865; // @[BootROM.scala:50:22] wire [63:0] rom_341 = 64'h2D746E696F706B61; // @[BootROM.scala:50:22] wire [63:0] rom_342 = 64'h2D6900746E756F63; // @[BootROM.scala:50:22] wire [63:0] rom_343 = 64'h6C622D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_344 = 64'h657A69732D6B636F; // @[BootROM.scala:50:22] wire [63:0] rom_345 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_346 = 64'h2D6900737465732D; // @[BootROM.scala:50:22] wire [63:0] rom_347 = 64'h69732D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_348 = 64'h720067657200657A; // @[BootROM.scala:50:22] wire [63:0] rom_349 = 64'h6173692C76637369; // @[BootROM.scala:50:22] wire [63:0] rom_350 = 64'h702C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_351 = 64'h6C756E617267706D; // @[BootROM.scala:50:22] wire [63:0] rom_352 = 64'h6972007974697261; // @[BootROM.scala:50:22] wire [63:0] rom_353 = 64'h72706D702C766373; // @[BootROM.scala:50:22] wire [63:0] rom_354 = 64'h7300736E6F696765; // @[BootROM.scala:50:22] wire [63:0] rom_355 = 64'h74642C6576696669; // @[BootROM.scala:50:22] wire [63:0] rom_356 = 64'h7574617473006D69; // @[BootROM.scala:50:22] wire [63:0] rom_357 = 64'h7265746E69230073; // @[BootROM.scala:50:22] wire [63:0] rom_358 = 64'h6C65632D74707572; // @[BootROM.scala:50:22] wire [63:0] rom_359 = 64'h7265746E6900736C; // @[BootROM.scala:50:22] wire [63:0] rom_360 = 64'h6E6F632D74707572; // @[BootROM.scala:50:22] wire [63:0] rom_361 = 64'h72656C6C6F7274; // @[BootROM.scala:50:22] wire [63:0] rom_362 = 64'h656C646E616870; // @[BootROM.scala:50:22] wire [63:0] rom_363 = 64'h72007365676E6172; // @[BootROM.scala:50:22] wire [63:0] rom_364 = 64'h73656D616E2D6765; // @[BootROM.scala:50:22] wire [63:0] rom_365 = 64'h2D6B636F6C632300; // @[BootROM.scala:50:22] wire [63:0] rom_366 = 64'h6C6300736C6C6563; // @[BootROM.scala:50:22] wire [63:0] rom_367 = 64'h7074756F2D6B636F; // @[BootROM.scala:50:22] wire [63:0] rom_368 = 64'h73656D616E2D7475; // @[BootROM.scala:50:22] wire [63:0] rom_369 = 64'h75727265746E6900; // @[BootROM.scala:50:22] wire [63:0] rom_370 = 64'h657478652D737470; // @[BootROM.scala:50:22] wire [63:0] rom_371 = 64'h626564006465646E; // @[BootROM.scala:50:22] wire [63:0] rom_372 = 64'h63617474612D6775; // @[BootROM.scala:50:22] wire [63:0] rom_373 = 64'h2C76637369720068; // @[BootROM.scala:50:22] wire [63:0] rom_374 = 64'h6F6972702D78616D; // @[BootROM.scala:50:22] wire [63:0] rom_375 = 64'h7369720079746972; // @[BootROM.scala:50:22] wire [63:0] rom_376 = 64'h7665646E2C7663; // @[BootROM.scala:50:22] wire [63:0] rom_377 = 64'h6900736B636F6C63; // @[BootROM.scala:50:22] wire [63:0] rom_378 = 64'h747075727265746E; // @[BootROM.scala:50:22] wire [63:0] rom_379 = 64'h746E657261702D; // @[BootROM.scala:50:22] wire [63:0] rom_235 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_380 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_381 = 64'h7374; // @[BootROM.scala:50:22] wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_382 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_383 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_384 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_385 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_386 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_387 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_388 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_389 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_390 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_391 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_392 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_393 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_394 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_395 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_396 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_397 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_398 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_399 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_400 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_401 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_402 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_403 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_404 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_405 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_406 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_407 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_408 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_409 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_410 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_411 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_412 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_413 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_414 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_415 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_416 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_417 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_418 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_419 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_420 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_421 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_422 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_423 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_424 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_425 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_426 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_427 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_428 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_429 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_430 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_431 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_432 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_433 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_434 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_435 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_436 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_437 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_438 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_439 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_440 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_441 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_442 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_443 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_444 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_445 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_446 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_447 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_448 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_449 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_450 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_451 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_452 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_453 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_454 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_455 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_456 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_457 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_458 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_459 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_460 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_461 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_462 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_463 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_464 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_465 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_466 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_467 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_468 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_469 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_470 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_471 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_472 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_473 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22] wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17] wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9] wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[BootROM.scala:41:9] wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9] wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9] wire auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9] assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17] wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17] assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9] wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9] wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34] wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64] wire _nodeIn_d_bits_T = \|high; // @[BootROM.scala:56:64, :57:53] wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}] assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17] assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17] TLMonitor_38 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[41] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 node _source_ok_T_61 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[2]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[3]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[4]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[5]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[6]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[7]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[8]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[9]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[10]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[11]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[12]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[13]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[14]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[15]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[16]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[17]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[18]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[19]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[20]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[21]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[22]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[23]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[24]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[25]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[26]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[27]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[28]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[29]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[30]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[31]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[32]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[33]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[34]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[35]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[36]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[37]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[38]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[39]) node source_ok = or(_source_ok_T_99, _source_ok_WIRE[40]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = and(_T_11, _T_24) node _T_353 = and(_T_352, _T_37) node _T_354 = and(_T_353, _T_50) node _T_355 = and(_T_354, _T_63) node _T_356 = and(_T_355, _T_71) node _T_357 = and(_T_356, _T_79) node _T_358 = and(_T_357, _T_87) node _T_359 = and(_T_358, _T_95) node _T_360 = and(_T_359, _T_103) node _T_361 = and(_T_360, _T_111) node _T_362 = and(_T_361, _T_119) node _T_363 = and(_T_362, _T_127) node _T_364 = and(_T_363, _T_135) node _T_365 = and(_T_364, _T_143) node _T_366 = and(_T_365, _T_151) node _T_367 = and(_T_366, _T_159) node _T_368 = and(_T_367, _T_167) node _T_369 = and(_T_368, _T_175) node _T_370 = and(_T_369, _T_183) node _T_371 = and(_T_370, _T_191) node _T_372 = and(_T_371, _T_199) node _T_373 = and(_T_372, _T_207) node _T_374 = and(_T_373, _T_215) node _T_375 = and(_T_374, _T_223) node _T_376 = and(_T_375, _T_231) node _T_377 = and(_T_376, _T_239) node _T_378 = and(_T_377, _T_247) node _T_379 = and(_T_378, _T_255) node _T_380 = and(_T_379, _T_263) node _T_381 = and(_T_380, _T_271) node _T_382 = and(_T_381, _T_279) node _T_383 = and(_T_382, _T_287) node _T_384 = and(_T_383, _T_295) node _T_385 = and(_T_384, _T_303) node _T_386 = and(_T_385, _T_311) node _T_387 = and(_T_386, _T_319) node _T_388 = and(_T_387, _T_327) node _T_389 = and(_T_388, _T_335) node _T_390 = and(_T_389, _T_343) node _T_391 = and(_T_390, _T_351) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_391, UInt<1>(0h1), "") : assert_1 node _T_395 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_397 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h0)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_4) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<1>(0h1)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_5) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h2)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_6) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_418 = shr(io.in.a.bits.source, 2) node _T_419 = eq(_T_418, UInt<2>(0h3)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_7) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_425 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_426 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_427 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_428 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_429 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_430 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_431 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_432 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_460 = or(_T_399, _T_405) node _T_461 = or(_T_460, _T_411) node _T_462 = or(_T_461, _T_417) node _T_463 = or(_T_462, _T_423) node _T_464 = or(_T_463, _T_424) node _T_465 = or(_T_464, _T_425) node _T_466 = or(_T_465, _T_426) node _T_467 = or(_T_466, _T_427) node _T_468 = or(_T_467, _T_428) node _T_469 = or(_T_468, _T_429) node _T_470 = or(_T_469, _T_430) node _T_471 = or(_T_470, _T_431) node _T_472 = or(_T_471, _T_432) node _T_473 = or(_T_472, _T_433) node _T_474 = or(_T_473, _T_434) node _T_475 = or(_T_474, _T_435) node _T_476 = or(_T_475, _T_436) node _T_477 = or(_T_476, _T_437) node _T_478 = or(_T_477, _T_438) node _T_479 = or(_T_478, _T_439) node _T_480 = or(_T_479, _T_440) node _T_481 = or(_T_480, _T_441) node _T_482 = or(_T_481, _T_442) node _T_483 = or(_T_482, _T_443) node _T_484 = or(_T_483, _T_444) node _T_485 = or(_T_484, _T_445) node _T_486 = or(_T_485, _T_446) node _T_487 = or(_T_486, _T_447) node _T_488 = or(_T_487, _T_448) node _T_489 = or(_T_488, _T_449) node _T_490 = or(_T_489, _T_450) node _T_491 = or(_T_490, _T_451) node _T_492 = or(_T_491, _T_452) node _T_493 = or(_T_492, _T_453) node _T_494 = or(_T_493, _T_454) node _T_495 = or(_T_494, _T_455) node _T_496 = or(_T_495, _T_456) node _T_497 = or(_T_496, _T_457) node _T_498 = or(_T_497, _T_458) node _T_499 = or(_T_498, _T_459) node _T_500 = and(_T_398, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_503 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<14>(0h2000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<13>(0h1000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_519 = cvt(_T_518) node _T_520 = and(_T_519, asSInt(UInt<18>(0h2f000))) node _T_521 = asSInt(_T_520) node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0))) node _T_523 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_524 = cvt(_T_523) node _T_525 = and(_T_524, asSInt(UInt<17>(0h10000))) node _T_526 = asSInt(_T_525) node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0))) node _T_528 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_529 = cvt(_T_528) node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000))) node _T_531 = asSInt(_T_530) node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0))) node _T_533 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<27>(0h4000000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_539 = cvt(_T_538) node _T_540 = and(_T_539, asSInt(UInt<13>(0h1000))) node _T_541 = asSInt(_T_540) node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0))) node _T_543 = or(_T_507, _T_512) node _T_544 = or(_T_543, _T_517) node _T_545 = or(_T_544, _T_522) node _T_546 = or(_T_545, _T_527) node _T_547 = or(_T_546, _T_532) node _T_548 = or(_T_547, _T_537) node _T_549 = or(_T_548, _T_542) node _T_550 = and(_T_502, _T_549) node _T_551 = or(UInt<1>(0h0), _T_550) node _T_552 = and(_T_501, _T_551) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_552, UInt<1>(0h1), "") : assert_2 node _T_556 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_8) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_563 = shr(io.in.a.bits.source, 2) node _T_564 = eq(_T_563, UInt<1>(0h1)) node _T_565 = leq(UInt<1>(0h0), uncommonBits_9) node _T_566 = and(_T_564, _T_565) node _T_567 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_568 = and(_T_566, _T_567) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<2>(0h2)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_10) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<2>(0h3)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_11) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _T_581 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_582 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_583 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_584 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_585 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_586 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_587 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_588 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_589 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_590 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_591 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_592 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_602 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_603 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_613 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_615 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_616 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[41] connect _WIRE[0], _T_556 connect _WIRE[1], _T_562 connect _WIRE[2], _T_568 connect _WIRE[3], _T_574 connect _WIRE[4], _T_580 connect _WIRE[5], _T_581 connect _WIRE[6], _T_582 connect _WIRE[7], _T_583 connect _WIRE[8], _T_584 connect _WIRE[9], _T_585 connect _WIRE[10], _T_586 connect _WIRE[11], _T_587 connect _WIRE[12], _T_588 connect _WIRE[13], _T_589 connect _WIRE[14], _T_590 connect _WIRE[15], _T_591 connect _WIRE[16], _T_592 connect _WIRE[17], _T_593 connect _WIRE[18], _T_594 connect _WIRE[19], _T_595 connect _WIRE[20], _T_596 connect _WIRE[21], _T_597 connect _WIRE[22], _T_598 connect _WIRE[23], _T_599 connect _WIRE[24], _T_600 connect _WIRE[25], _T_601 connect _WIRE[26], _T_602 connect _WIRE[27], _T_603 connect _WIRE[28], _T_604 connect _WIRE[29], _T_605 connect _WIRE[30], _T_606 connect _WIRE[31], _T_607 connect _WIRE[32], _T_608 connect _WIRE[33], _T_609 connect _WIRE[34], _T_610 connect _WIRE[35], _T_611 connect _WIRE[36], _T_612 connect _WIRE[37], _T_613 connect _WIRE[38], _T_614 connect _WIRE[39], _T_615 connect _WIRE[40], _T_616 node _T_617 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_618 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_619 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_620 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_621 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_622 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_623 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_624 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_625 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_626 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_627 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_628 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_629 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_632 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[5], _T_617, UInt<1>(0h0)) node _T_635 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[8], _T_618, UInt<1>(0h0)) node _T_638 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[11], _T_619, UInt<1>(0h0)) node _T_641 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_642 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_643 = mux(_WIRE[14], _T_620, UInt<1>(0h0)) node _T_644 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_645 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_646 = mux(_WIRE[17], _T_621, UInt<1>(0h0)) node _T_647 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_648 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_649 = mux(_WIRE[20], _T_622, UInt<1>(0h0)) node _T_650 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_651 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_652 = mux(_WIRE[23], _T_623, UInt<1>(0h0)) node _T_653 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_654 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_655 = mux(_WIRE[26], _T_624, UInt<1>(0h0)) node _T_656 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_657 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_658 = mux(_WIRE[29], _T_625, UInt<1>(0h0)) node _T_659 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_660 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_661 = mux(_WIRE[32], _T_626, UInt<1>(0h0)) node _T_662 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_663 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_664 = mux(_WIRE[35], _T_627, UInt<1>(0h0)) node _T_665 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_666 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = mux(_WIRE[38], _T_628, UInt<1>(0h0)) node _T_668 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = or(_T_629, _T_630) node _T_671 = or(_T_670, _T_631) node _T_672 = or(_T_671, _T_632) node _T_673 = or(_T_672, _T_633) node _T_674 = or(_T_673, _T_634) node _T_675 = or(_T_674, _T_635) node _T_676 = or(_T_675, _T_636) node _T_677 = or(_T_676, _T_637) node _T_678 = or(_T_677, _T_638) node _T_679 = or(_T_678, _T_639) node _T_680 = or(_T_679, _T_640) node _T_681 = or(_T_680, _T_641) node _T_682 = or(_T_681, _T_642) node _T_683 = or(_T_682, _T_643) node _T_684 = or(_T_683, _T_644) node _T_685 = or(_T_684, _T_645) node _T_686 = or(_T_685, _T_646) node _T_687 = or(_T_686, _T_647) node _T_688 = or(_T_687, _T_648) node _T_689 = or(_T_688, _T_649) node _T_690 = or(_T_689, _T_650) node _T_691 = or(_T_690, _T_651) node _T_692 = or(_T_691, _T_652) node _T_693 = or(_T_692, _T_653) node _T_694 = or(_T_693, _T_654) node _T_695 = or(_T_694, _T_655) node _T_696 = or(_T_695, _T_656) node _T_697 = or(_T_696, _T_657) node _T_698 = or(_T_697, _T_658) node _T_699 = or(_T_698, _T_659) node _T_700 = or(_T_699, _T_660) node _T_701 = or(_T_700, _T_661) node _T_702 = or(_T_701, _T_662) node _T_703 = or(_T_702, _T_663) node _T_704 = or(_T_703, _T_664) node _T_705 = or(_T_704, _T_665) node _T_706 = or(_T_705, _T_666) node _T_707 = or(_T_706, _T_667) node _T_708 = or(_T_707, _T_668) node _T_709 = or(_T_708, _T_669) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_709 node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_711 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_712 = and(_T_710, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_715 = cvt(_T_714) node _T_716 = and(_T_715, asSInt(UInt<14>(0h2000))) node _T_717 = asSInt(_T_716) node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0))) node _T_719 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<13>(0h1000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_725 = cvt(_T_724) node _T_726 = and(_T_725, asSInt(UInt<17>(0h10000))) node _T_727 = asSInt(_T_726) node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) node _T_729 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<18>(0h2f000))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_735 = cvt(_T_734) node _T_736 = and(_T_735, asSInt(UInt<17>(0h10000))) node _T_737 = asSInt(_T_736) node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0))) node _T_739 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_745 = cvt(_T_744) node _T_746 = and(_T_745, asSInt(UInt<27>(0h4000000))) node _T_747 = asSInt(_T_746) node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0))) node _T_749 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<13>(0h1000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = or(_T_718, _T_723) node _T_755 = or(_T_754, _T_728) node _T_756 = or(_T_755, _T_733) node _T_757 = or(_T_756, _T_738) node _T_758 = or(_T_757, _T_743) node _T_759 = or(_T_758, _T_748) node _T_760 = or(_T_759, _T_753) node _T_761 = and(_T_713, _T_760) node _T_762 = or(UInt<1>(0h0), _T_761) node _T_763 = and(_WIRE_1, _T_762) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_763, UInt<1>(0h1), "") : assert_3 node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(source_ok, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_770 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_770, UInt<1>(0h1), "") : assert_5 node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(is_aligned, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_777 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_777, UInt<1>(0h1), "") : assert_7 node _T_781 = not(io.in.a.bits.mask) node _T_782 = eq(_T_781, UInt<1>(0h0)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_782, UInt<1>(0h1), "") : assert_8 node _T_786 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_786, UInt<1>(0h1), "") : assert_9 node _T_790 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_790 : node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_795 = shr(io.in.a.bits.source, 2) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = leq(UInt<1>(0h0), uncommonBits_12) node _T_798 = and(_T_796, _T_797) node _T_799 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_800 = and(_T_798, _T_799) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_801 = shr(io.in.a.bits.source, 2) node _T_802 = eq(_T_801, UInt<1>(0h1)) node _T_803 = leq(UInt<1>(0h0), uncommonBits_13) node _T_804 = and(_T_802, _T_803) node _T_805 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_806 = and(_T_804, _T_805) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_807 = shr(io.in.a.bits.source, 2) node _T_808 = eq(_T_807, UInt<2>(0h2)) node _T_809 = leq(UInt<1>(0h0), uncommonBits_14) node _T_810 = and(_T_808, _T_809) node _T_811 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_812 = and(_T_810, _T_811) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_813 = shr(io.in.a.bits.source, 2) node _T_814 = eq(_T_813, UInt<2>(0h3)) node _T_815 = leq(UInt<1>(0h0), uncommonBits_15) node _T_816 = and(_T_814, _T_815) node _T_817 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_821 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_822 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_823 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_824 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_825 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_826 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_827 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_828 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_829 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_830 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_831 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_855 = or(_T_794, _T_800) node _T_856 = or(_T_855, _T_806) node _T_857 = or(_T_856, _T_812) node _T_858 = or(_T_857, _T_818) node _T_859 = or(_T_858, _T_819) node _T_860 = or(_T_859, _T_820) node _T_861 = or(_T_860, _T_821) node _T_862 = or(_T_861, _T_822) node _T_863 = or(_T_862, _T_823) node _T_864 = or(_T_863, _T_824) node _T_865 = or(_T_864, _T_825) node _T_866 = or(_T_865, _T_826) node _T_867 = or(_T_866, _T_827) node _T_868 = or(_T_867, _T_828) node _T_869 = or(_T_868, _T_829) node _T_870 = or(_T_869, _T_830) node _T_871 = or(_T_870, _T_831) node _T_872 = or(_T_871, _T_832) node _T_873 = or(_T_872, _T_833) node _T_874 = or(_T_873, _T_834) node _T_875 = or(_T_874, _T_835) node _T_876 = or(_T_875, _T_836) node _T_877 = or(_T_876, _T_837) node _T_878 = or(_T_877, _T_838) node _T_879 = or(_T_878, _T_839) node _T_880 = or(_T_879, _T_840) node _T_881 = or(_T_880, _T_841) node _T_882 = or(_T_881, _T_842) node _T_883 = or(_T_882, _T_843) node _T_884 = or(_T_883, _T_844) node _T_885 = or(_T_884, _T_845) node _T_886 = or(_T_885, _T_846) node _T_887 = or(_T_886, _T_847) node _T_888 = or(_T_887, _T_848) node _T_889 = or(_T_888, _T_849) node _T_890 = or(_T_889, _T_850) node _T_891 = or(_T_890, _T_851) node _T_892 = or(_T_891, _T_852) node _T_893 = or(_T_892, _T_853) node _T_894 = or(_T_893, _T_854) node _T_895 = and(_T_793, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_898 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_899 = cvt(_T_898) node _T_900 = and(_T_899, asSInt(UInt<14>(0h2000))) node _T_901 = asSInt(_T_900) node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0))) node _T_903 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_904 = cvt(_T_903) node _T_905 = and(_T_904, asSInt(UInt<13>(0h1000))) node _T_906 = asSInt(_T_905) node _T_907 = eq(_T_906, asSInt(UInt<1>(0h0))) node _T_908 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_909 = cvt(_T_908) node _T_910 = and(_T_909, asSInt(UInt<17>(0h10000))) node _T_911 = asSInt(_T_910) node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0))) node _T_913 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<18>(0h2f000))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<17>(0h10000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<13>(0h1000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<27>(0h4000000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<13>(0h1000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = or(_T_902, _T_907) node _T_939 = or(_T_938, _T_912) node _T_940 = or(_T_939, _T_917) node _T_941 = or(_T_940, _T_922) node _T_942 = or(_T_941, _T_927) node _T_943 = or(_T_942, _T_932) node _T_944 = or(_T_943, _T_937) node _T_945 = and(_T_897, _T_944) node _T_946 = or(UInt<1>(0h0), _T_945) node _T_947 = and(_T_896, _T_946) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_947, UInt<1>(0h1), "") : assert_10 node _T_951 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<1>(0h0)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_16) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<1>(0h1)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_17) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_964 = shr(io.in.a.bits.source, 2) node _T_965 = eq(_T_964, UInt<2>(0h2)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_18) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_969 = and(_T_967, _T_968) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_970 = shr(io.in.a.bits.source, 2) node _T_971 = eq(_T_970, UInt<2>(0h3)) node _T_972 = leq(UInt<1>(0h0), uncommonBits_19) node _T_973 = and(_T_971, _T_972) node _T_974 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_975 = and(_T_973, _T_974) node _T_976 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_978 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_979 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_980 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_981 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_982 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_983 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_984 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_985 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_986 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_987 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_990 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_991 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_992 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_993 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_994 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_995 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_996 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_997 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_998 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_999 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1000 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1001 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[41] connect _WIRE_2[0], _T_951 connect _WIRE_2[1], _T_957 connect _WIRE_2[2], _T_963 connect _WIRE_2[3], _T_969 connect _WIRE_2[4], _T_975 connect _WIRE_2[5], _T_976 connect _WIRE_2[6], _T_977 connect _WIRE_2[7], _T_978 connect _WIRE_2[8], _T_979 connect _WIRE_2[9], _T_980 connect _WIRE_2[10], _T_981 connect _WIRE_2[11], _T_982 connect _WIRE_2[12], _T_983 connect _WIRE_2[13], _T_984 connect _WIRE_2[14], _T_985 connect _WIRE_2[15], _T_986 connect _WIRE_2[16], _T_987 connect _WIRE_2[17], _T_988 connect _WIRE_2[18], _T_989 connect _WIRE_2[19], _T_990 connect _WIRE_2[20], _T_991 connect _WIRE_2[21], _T_992 connect _WIRE_2[22], _T_993 connect _WIRE_2[23], _T_994 connect _WIRE_2[24], _T_995 connect _WIRE_2[25], _T_996 connect _WIRE_2[26], _T_997 connect _WIRE_2[27], _T_998 connect _WIRE_2[28], _T_999 connect _WIRE_2[29], _T_1000 connect _WIRE_2[30], _T_1001 connect _WIRE_2[31], _T_1002 connect _WIRE_2[32], _T_1003 connect _WIRE_2[33], _T_1004 connect _WIRE_2[34], _T_1005 connect _WIRE_2[35], _T_1006 connect _WIRE_2[36], _T_1007 connect _WIRE_2[37], _T_1008 connect _WIRE_2[38], _T_1009 connect _WIRE_2[39], _T_1010 connect _WIRE_2[40], _T_1011 node _T_1012 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1013 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1014 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1015 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1016 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1017 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1018 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1019 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1020 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1021 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1022 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1023 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1024 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1025 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1026 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1027 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1028 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1029 = mux(_WIRE_2[5], _T_1012, UInt<1>(0h0)) node _T_1030 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1031 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1032 = mux(_WIRE_2[8], _T_1013, UInt<1>(0h0)) node _T_1033 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_1034 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1035 = mux(_WIRE_2[11], _T_1014, UInt<1>(0h0)) node _T_1036 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1037 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_1038 = mux(_WIRE_2[14], _T_1015, UInt<1>(0h0)) node _T_1039 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_1040 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1041 = mux(_WIRE_2[17], _T_1016, UInt<1>(0h0)) node _T_1042 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1043 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_1044 = mux(_WIRE_2[20], _T_1017, UInt<1>(0h0)) node _T_1045 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_1046 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_1047 = mux(_WIRE_2[23], _T_1018, UInt<1>(0h0)) node _T_1048 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_1049 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_1050 = mux(_WIRE_2[26], _T_1019, UInt<1>(0h0)) node _T_1051 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_1052 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_1053 = mux(_WIRE_2[29], _T_1020, UInt<1>(0h0)) node _T_1054 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_1055 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_1056 = mux(_WIRE_2[32], _T_1021, UInt<1>(0h0)) node _T_1057 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_1058 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_1059 = mux(_WIRE_2[35], _T_1022, UInt<1>(0h0)) node _T_1060 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_1061 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_1062 = mux(_WIRE_2[38], _T_1023, UInt<1>(0h0)) node _T_1063 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_1064 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_1065 = or(_T_1024, _T_1025) node _T_1066 = or(_T_1065, _T_1026) node _T_1067 = or(_T_1066, _T_1027) node _T_1068 = or(_T_1067, _T_1028) node _T_1069 = or(_T_1068, _T_1029) node _T_1070 = or(_T_1069, _T_1030) node _T_1071 = or(_T_1070, _T_1031) node _T_1072 = or(_T_1071, _T_1032) node _T_1073 = or(_T_1072, _T_1033) node _T_1074 = or(_T_1073, _T_1034) node _T_1075 = or(_T_1074, _T_1035) node _T_1076 = or(_T_1075, _T_1036) node _T_1077 = or(_T_1076, _T_1037) node _T_1078 = or(_T_1077, _T_1038) node _T_1079 = or(_T_1078, _T_1039) node _T_1080 = or(_T_1079, _T_1040) node _T_1081 = or(_T_1080, _T_1041) node _T_1082 = or(_T_1081, _T_1042) node _T_1083 = or(_T_1082, _T_1043) node _T_1084 = or(_T_1083, _T_1044) node _T_1085 = or(_T_1084, _T_1045) node _T_1086 = or(_T_1085, _T_1046) node _T_1087 = or(_T_1086, _T_1047) node _T_1088 = or(_T_1087, _T_1048) node _T_1089 = or(_T_1088, _T_1049) node _T_1090 = or(_T_1089, _T_1050) node _T_1091 = or(_T_1090, _T_1051) node _T_1092 = or(_T_1091, _T_1052) node _T_1093 = or(_T_1092, _T_1053) node _T_1094 = or(_T_1093, _T_1054) node _T_1095 = or(_T_1094, _T_1055) node _T_1096 = or(_T_1095, _T_1056) node _T_1097 = or(_T_1096, _T_1057) node _T_1098 = or(_T_1097, _T_1058) node _T_1099 = or(_T_1098, _T_1059) node _T_1100 = or(_T_1099, _T_1060) node _T_1101 = or(_T_1100, _T_1061) node _T_1102 = or(_T_1101, _T_1062) node _T_1103 = or(_T_1102, _T_1063) node _T_1104 = or(_T_1103, _T_1064) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1104 node _T_1105 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1106 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = or(UInt<1>(0h0), _T_1107) node _T_1109 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1110 = cvt(_T_1109) node _T_1111 = and(_T_1110, asSInt(UInt<14>(0h2000))) node _T_1112 = asSInt(_T_1111) node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0))) node _T_1114 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<13>(0h1000))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<17>(0h10000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<18>(0h2f000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1130 = cvt(_T_1129) node _T_1131 = and(_T_1130, asSInt(UInt<17>(0h10000))) node _T_1132 = asSInt(_T_1131) node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0))) node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<13>(0h1000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<27>(0h4000000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<13>(0h1000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1113, _T_1118) node _T_1150 = or(_T_1149, _T_1123) node _T_1151 = or(_T_1150, _T_1128) node _T_1152 = or(_T_1151, _T_1133) node _T_1153 = or(_T_1152, _T_1138) node _T_1154 = or(_T_1153, _T_1143) node _T_1155 = or(_T_1154, _T_1148) node _T_1156 = and(_T_1108, _T_1155) node _T_1157 = or(UInt<1>(0h0), _T_1156) node _T_1158 = and(_WIRE_3, _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_11 node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(source_ok, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1165 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_13 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1172 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_15 node _T_1176 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_16 node _T_1180 = not(io.in.a.bits.mask) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_17 node _T_1185 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_18 node _T_1189 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1189 : node _T_1190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<1>(0h1)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1206 = shr(io.in.a.bits.source, 2) node _T_1207 = eq(_T_1206, UInt<2>(0h2)) node _T_1208 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1211 = and(_T_1209, _T_1210) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1212 = shr(io.in.a.bits.source, 2) node _T_1213 = eq(_T_1212, UInt<2>(0h3)) node _T_1214 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1217 = and(_T_1215, _T_1216) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1225 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1226 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1227 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1228 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1229 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1249 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1250 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1251 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1252 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1253 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1254 = or(_T_1193, _T_1199) node _T_1255 = or(_T_1254, _T_1205) node _T_1256 = or(_T_1255, _T_1211) node _T_1257 = or(_T_1256, _T_1217) node _T_1258 = or(_T_1257, _T_1218) node _T_1259 = or(_T_1258, _T_1219) node _T_1260 = or(_T_1259, _T_1220) node _T_1261 = or(_T_1260, _T_1221) node _T_1262 = or(_T_1261, _T_1222) node _T_1263 = or(_T_1262, _T_1223) node _T_1264 = or(_T_1263, _T_1224) node _T_1265 = or(_T_1264, _T_1225) node _T_1266 = or(_T_1265, _T_1226) node _T_1267 = or(_T_1266, _T_1227) node _T_1268 = or(_T_1267, _T_1228) node _T_1269 = or(_T_1268, _T_1229) node _T_1270 = or(_T_1269, _T_1230) node _T_1271 = or(_T_1270, _T_1231) node _T_1272 = or(_T_1271, _T_1232) node _T_1273 = or(_T_1272, _T_1233) node _T_1274 = or(_T_1273, _T_1234) node _T_1275 = or(_T_1274, _T_1235) node _T_1276 = or(_T_1275, _T_1236) node _T_1277 = or(_T_1276, _T_1237) node _T_1278 = or(_T_1277, _T_1238) node _T_1279 = or(_T_1278, _T_1239) node _T_1280 = or(_T_1279, _T_1240) node _T_1281 = or(_T_1280, _T_1241) node _T_1282 = or(_T_1281, _T_1242) node _T_1283 = or(_T_1282, _T_1243) node _T_1284 = or(_T_1283, _T_1244) node _T_1285 = or(_T_1284, _T_1245) node _T_1286 = or(_T_1285, _T_1246) node _T_1287 = or(_T_1286, _T_1247) node _T_1288 = or(_T_1287, _T_1248) node _T_1289 = or(_T_1288, _T_1249) node _T_1290 = or(_T_1289, _T_1250) node _T_1291 = or(_T_1290, _T_1251) node _T_1292 = or(_T_1291, _T_1252) node _T_1293 = or(_T_1292, _T_1253) node _T_1294 = and(_T_1192, _T_1293) node _T_1295 = or(UInt<1>(0h0), _T_1294) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_19 node _T_1299 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1300 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1301 = and(_T_1299, _T_1300) node _T_1302 = or(UInt<1>(0h0), _T_1301) node _T_1303 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1304 = cvt(_T_1303) node _T_1305 = and(_T_1304, asSInt(UInt<13>(0h1000))) node _T_1306 = asSInt(_T_1305) node _T_1307 = eq(_T_1306, asSInt(UInt<1>(0h0))) node _T_1308 = and(_T_1302, _T_1307) node _T_1309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1310 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = or(UInt<1>(0h0), _T_1311) node _T_1313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1314 = cvt(_T_1313) node _T_1315 = and(_T_1314, asSInt(UInt<14>(0h2000))) node _T_1316 = asSInt(_T_1315) node _T_1317 = eq(_T_1316, asSInt(UInt<1>(0h0))) node _T_1318 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<17>(0h10000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<18>(0h2f000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<17>(0h10000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<13>(0h1000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<27>(0h4000000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<13>(0h1000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = or(_T_1317, _T_1322) node _T_1349 = or(_T_1348, _T_1327) node _T_1350 = or(_T_1349, _T_1332) node _T_1351 = or(_T_1350, _T_1337) node _T_1352 = or(_T_1351, _T_1342) node _T_1353 = or(_T_1352, _T_1347) node _T_1354 = and(_T_1312, _T_1353) node _T_1355 = or(UInt<1>(0h0), _T_1308) node _T_1356 = or(_T_1355, _T_1354) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_20 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(source_ok, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(is_aligned, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1366 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1367 = asUInt(reset) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) when _T_1368 : node _T_1369 = eq(_T_1366, UInt<1>(0h0)) when _T_1369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1366, UInt<1>(0h1), "") : assert_23 node _T_1370 = eq(io.in.a.bits.mask, mask) node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(_T_1370, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1370, UInt<1>(0h1), "") : assert_24 node _T_1374 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_25 node _T_1378 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1378 : node _T_1379 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1380 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1381 = and(_T_1379, _T_1380) node _T_1382 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1383 = shr(io.in.a.bits.source, 2) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) node _T_1385 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1388 = and(_T_1386, _T_1387) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1389 = shr(io.in.a.bits.source, 2) node _T_1390 = eq(_T_1389, UInt<1>(0h1)) node _T_1391 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1392 = and(_T_1390, _T_1391) node _T_1393 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1394 = and(_T_1392, _T_1393) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1395 = shr(io.in.a.bits.source, 2) node _T_1396 = eq(_T_1395, UInt<2>(0h2)) node _T_1397 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1398 = and(_T_1396, _T_1397) node _T_1399 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1400 = and(_T_1398, _T_1399) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1401 = shr(io.in.a.bits.source, 2) node _T_1402 = eq(_T_1401, UInt<2>(0h3)) node _T_1403 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1404 = and(_T_1402, _T_1403) node _T_1405 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1406 = and(_T_1404, _T_1405) node _T_1407 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1408 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1409 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1410 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1411 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1412 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1413 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1414 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1415 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1416 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1417 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1418 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1429 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1430 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1431 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1434 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1435 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1436 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1437 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1438 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1439 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1440 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1441 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1442 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1443 = or(_T_1382, _T_1388) node _T_1444 = or(_T_1443, _T_1394) node _T_1445 = or(_T_1444, _T_1400) node _T_1446 = or(_T_1445, _T_1406) node _T_1447 = or(_T_1446, _T_1407) node _T_1448 = or(_T_1447, _T_1408) node _T_1449 = or(_T_1448, _T_1409) node _T_1450 = or(_T_1449, _T_1410) node _T_1451 = or(_T_1450, _T_1411) node _T_1452 = or(_T_1451, _T_1412) node _T_1453 = or(_T_1452, _T_1413) node _T_1454 = or(_T_1453, _T_1414) node _T_1455 = or(_T_1454, _T_1415) node _T_1456 = or(_T_1455, _T_1416) node _T_1457 = or(_T_1456, _T_1417) node _T_1458 = or(_T_1457, _T_1418) node _T_1459 = or(_T_1458, _T_1419) node _T_1460 = or(_T_1459, _T_1420) node _T_1461 = or(_T_1460, _T_1421) node _T_1462 = or(_T_1461, _T_1422) node _T_1463 = or(_T_1462, _T_1423) node _T_1464 = or(_T_1463, _T_1424) node _T_1465 = or(_T_1464, _T_1425) node _T_1466 = or(_T_1465, _T_1426) node _T_1467 = or(_T_1466, _T_1427) node _T_1468 = or(_T_1467, _T_1428) node _T_1469 = or(_T_1468, _T_1429) node _T_1470 = or(_T_1469, _T_1430) node _T_1471 = or(_T_1470, _T_1431) node _T_1472 = or(_T_1471, _T_1432) node _T_1473 = or(_T_1472, _T_1433) node _T_1474 = or(_T_1473, _T_1434) node _T_1475 = or(_T_1474, _T_1435) node _T_1476 = or(_T_1475, _T_1436) node _T_1477 = or(_T_1476, _T_1437) node _T_1478 = or(_T_1477, _T_1438) node _T_1479 = or(_T_1478, _T_1439) node _T_1480 = or(_T_1479, _T_1440) node _T_1481 = or(_T_1480, _T_1441) node _T_1482 = or(_T_1481, _T_1442) node _T_1483 = and(_T_1381, _T_1482) node _T_1484 = or(UInt<1>(0h0), _T_1483) node _T_1485 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1486 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = or(UInt<1>(0h0), _T_1487) node _T_1489 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<13>(0h1000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = and(_T_1488, _T_1493) node _T_1495 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1496 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1497 = and(_T_1495, _T_1496) node _T_1498 = or(UInt<1>(0h0), _T_1497) node _T_1499 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<14>(0h2000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1505 = cvt(_T_1504) node _T_1506 = and(_T_1505, asSInt(UInt<18>(0h2f000))) node _T_1507 = asSInt(_T_1506) node _T_1508 = eq(_T_1507, asSInt(UInt<1>(0h0))) node _T_1509 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1510 = cvt(_T_1509) node _T_1511 = and(_T_1510, asSInt(UInt<17>(0h10000))) node _T_1512 = asSInt(_T_1511) node _T_1513 = eq(_T_1512, asSInt(UInt<1>(0h0))) node _T_1514 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1515 = cvt(_T_1514) node _T_1516 = and(_T_1515, asSInt(UInt<13>(0h1000))) node _T_1517 = asSInt(_T_1516) node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0))) node _T_1519 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1520 = cvt(_T_1519) node _T_1521 = and(_T_1520, asSInt(UInt<27>(0h4000000))) node _T_1522 = asSInt(_T_1521) node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1525 = cvt(_T_1524) node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000))) node _T_1527 = asSInt(_T_1526) node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) node _T_1529 = or(_T_1503, _T_1508) node _T_1530 = or(_T_1529, _T_1513) node _T_1531 = or(_T_1530, _T_1518) node _T_1532 = or(_T_1531, _T_1523) node _T_1533 = or(_T_1532, _T_1528) node _T_1534 = and(_T_1498, _T_1533) node _T_1535 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1536 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1537 = cvt(_T_1536) node _T_1538 = and(_T_1537, asSInt(UInt<17>(0h10000))) node _T_1539 = asSInt(_T_1538) node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = and(_T_1535, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1494) node _T_1543 = or(_T_1542, _T_1534) node _T_1544 = or(_T_1543, _T_1541) node _T_1545 = and(_T_1484, _T_1544) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_26 node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(source_ok, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(is_aligned, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1555 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_29 node _T_1559 = eq(io.in.a.bits.mask, mask) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_30 node _T_1563 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1563 : node _T_1564 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1565 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1566 = and(_T_1564, _T_1565) node _T_1567 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1568 = shr(io.in.a.bits.source, 2) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) node _T_1570 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1571 = and(_T_1569, _T_1570) node _T_1572 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1573 = and(_T_1571, _T_1572) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1574 = shr(io.in.a.bits.source, 2) node _T_1575 = eq(_T_1574, UInt<1>(0h1)) node _T_1576 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1577 = and(_T_1575, _T_1576) node _T_1578 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1579 = and(_T_1577, _T_1578) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1580 = shr(io.in.a.bits.source, 2) node _T_1581 = eq(_T_1580, UInt<2>(0h2)) node _T_1582 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1583 = and(_T_1581, _T_1582) node _T_1584 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1585 = and(_T_1583, _T_1584) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1586 = shr(io.in.a.bits.source, 2) node _T_1587 = eq(_T_1586, UInt<2>(0h3)) node _T_1588 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1589 = and(_T_1587, _T_1588) node _T_1590 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1593 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1594 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1595 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1596 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1597 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1598 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1599 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1600 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1602 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1603 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1604 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1605 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1606 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1607 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1608 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1609 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1610 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1611 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1612 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1613 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1614 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1615 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1616 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1617 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1618 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1619 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1620 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1621 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1622 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1623 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1624 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1625 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1626 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1627 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1628 = or(_T_1567, _T_1573) node _T_1629 = or(_T_1628, _T_1579) node _T_1630 = or(_T_1629, _T_1585) node _T_1631 = or(_T_1630, _T_1591) node _T_1632 = or(_T_1631, _T_1592) node _T_1633 = or(_T_1632, _T_1593) node _T_1634 = or(_T_1633, _T_1594) node _T_1635 = or(_T_1634, _T_1595) node _T_1636 = or(_T_1635, _T_1596) node _T_1637 = or(_T_1636, _T_1597) node _T_1638 = or(_T_1637, _T_1598) node _T_1639 = or(_T_1638, _T_1599) node _T_1640 = or(_T_1639, _T_1600) node _T_1641 = or(_T_1640, _T_1601) node _T_1642 = or(_T_1641, _T_1602) node _T_1643 = or(_T_1642, _T_1603) node _T_1644 = or(_T_1643, _T_1604) node _T_1645 = or(_T_1644, _T_1605) node _T_1646 = or(_T_1645, _T_1606) node _T_1647 = or(_T_1646, _T_1607) node _T_1648 = or(_T_1647, _T_1608) node _T_1649 = or(_T_1648, _T_1609) node _T_1650 = or(_T_1649, _T_1610) node _T_1651 = or(_T_1650, _T_1611) node _T_1652 = or(_T_1651, _T_1612) node _T_1653 = or(_T_1652, _T_1613) node _T_1654 = or(_T_1653, _T_1614) node _T_1655 = or(_T_1654, _T_1615) node _T_1656 = or(_T_1655, _T_1616) node _T_1657 = or(_T_1656, _T_1617) node _T_1658 = or(_T_1657, _T_1618) node _T_1659 = or(_T_1658, _T_1619) node _T_1660 = or(_T_1659, _T_1620) node _T_1661 = or(_T_1660, _T_1621) node _T_1662 = or(_T_1661, _T_1622) node _T_1663 = or(_T_1662, _T_1623) node _T_1664 = or(_T_1663, _T_1624) node _T_1665 = or(_T_1664, _T_1625) node _T_1666 = or(_T_1665, _T_1626) node _T_1667 = or(_T_1666, _T_1627) node _T_1668 = and(_T_1566, _T_1667) node _T_1669 = or(UInt<1>(0h0), _T_1668) node _T_1670 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1671 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1675 = cvt(_T_1674) node _T_1676 = and(_T_1675, asSInt(UInt<13>(0h1000))) node _T_1677 = asSInt(_T_1676) node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0))) node _T_1679 = and(_T_1673, _T_1678) node _T_1680 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1681 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = or(UInt<1>(0h0), _T_1682) node _T_1684 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1685 = cvt(_T_1684) node _T_1686 = and(_T_1685, asSInt(UInt<14>(0h2000))) node _T_1687 = asSInt(_T_1686) node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1690 = cvt(_T_1689) node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000))) node _T_1692 = asSInt(_T_1691) node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1695 = cvt(_T_1694) node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000))) node _T_1697 = asSInt(_T_1696) node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0))) node _T_1699 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1705 = cvt(_T_1704) node _T_1706 = and(_T_1705, asSInt(UInt<27>(0h4000000))) node _T_1707 = asSInt(_T_1706) node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1710 = cvt(_T_1709) node _T_1711 = and(_T_1710, asSInt(UInt<13>(0h1000))) node _T_1712 = asSInt(_T_1711) node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0))) node _T_1714 = or(_T_1688, _T_1693) node _T_1715 = or(_T_1714, _T_1698) node _T_1716 = or(_T_1715, _T_1703) node _T_1717 = or(_T_1716, _T_1708) node _T_1718 = or(_T_1717, _T_1713) node _T_1719 = and(_T_1683, _T_1718) node _T_1720 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1721 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1722 = cvt(_T_1721) node _T_1723 = and(_T_1722, asSInt(UInt<17>(0h10000))) node _T_1724 = asSInt(_T_1723) node _T_1725 = eq(_T_1724, asSInt(UInt<1>(0h0))) node _T_1726 = and(_T_1720, _T_1725) node _T_1727 = or(UInt<1>(0h0), _T_1679) node _T_1728 = or(_T_1727, _T_1719) node _T_1729 = or(_T_1728, _T_1726) node _T_1730 = and(_T_1669, _T_1729) node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(_T_1730, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1730, UInt<1>(0h1), "") : assert_31 node _T_1734 = asUInt(reset) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) when _T_1735 : node _T_1736 = eq(source_ok, UInt<1>(0h0)) when _T_1736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(is_aligned, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1740 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1741 = asUInt(reset) node _T_1742 = eq(_T_1741, UInt<1>(0h0)) when _T_1742 : node _T_1743 = eq(_T_1740, UInt<1>(0h0)) when _T_1743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1740, UInt<1>(0h1), "") : assert_34 node _T_1744 = not(mask) node _T_1745 = and(io.in.a.bits.mask, _T_1744) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) node _T_1747 = asUInt(reset) node _T_1748 = eq(_T_1747, UInt<1>(0h0)) when _T_1748 : node _T_1749 = eq(_T_1746, UInt<1>(0h0)) when _T_1749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1746, UInt<1>(0h1), "") : assert_35 node _T_1750 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1750 : node _T_1751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1752 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1753 = and(_T_1751, _T_1752) node _T_1754 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1761 = shr(io.in.a.bits.source, 2) node _T_1762 = eq(_T_1761, UInt<1>(0h1)) node _T_1763 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1764 = and(_T_1762, _T_1763) node _T_1765 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1766 = and(_T_1764, _T_1765) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1767 = shr(io.in.a.bits.source, 2) node _T_1768 = eq(_T_1767, UInt<2>(0h2)) node _T_1769 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1770 = and(_T_1768, _T_1769) node _T_1771 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1772 = and(_T_1770, _T_1771) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1773 = shr(io.in.a.bits.source, 2) node _T_1774 = eq(_T_1773, UInt<2>(0h3)) node _T_1775 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1776 = and(_T_1774, _T_1775) node _T_1777 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1778 = and(_T_1776, _T_1777) node _T_1779 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1780 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1781 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1782 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1783 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1784 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1785 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1786 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1787 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1788 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1789 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1790 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1797 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1798 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1799 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1800 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1801 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1802 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1803 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1804 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1805 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1806 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1807 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1808 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1809 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1810 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1811 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1812 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1813 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1814 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1815 = or(_T_1754, _T_1760) node _T_1816 = or(_T_1815, _T_1766) node _T_1817 = or(_T_1816, _T_1772) node _T_1818 = or(_T_1817, _T_1778) node _T_1819 = or(_T_1818, _T_1779) node _T_1820 = or(_T_1819, _T_1780) node _T_1821 = or(_T_1820, _T_1781) node _T_1822 = or(_T_1821, _T_1782) node _T_1823 = or(_T_1822, _T_1783) node _T_1824 = or(_T_1823, _T_1784) node _T_1825 = or(_T_1824, _T_1785) node _T_1826 = or(_T_1825, _T_1786) node _T_1827 = or(_T_1826, _T_1787) node _T_1828 = or(_T_1827, _T_1788) node _T_1829 = or(_T_1828, _T_1789) node _T_1830 = or(_T_1829, _T_1790) node _T_1831 = or(_T_1830, _T_1791) node _T_1832 = or(_T_1831, _T_1792) node _T_1833 = or(_T_1832, _T_1793) node _T_1834 = or(_T_1833, _T_1794) node _T_1835 = or(_T_1834, _T_1795) node _T_1836 = or(_T_1835, _T_1796) node _T_1837 = or(_T_1836, _T_1797) node _T_1838 = or(_T_1837, _T_1798) node _T_1839 = or(_T_1838, _T_1799) node _T_1840 = or(_T_1839, _T_1800) node _T_1841 = or(_T_1840, _T_1801) node _T_1842 = or(_T_1841, _T_1802) node _T_1843 = or(_T_1842, _T_1803) node _T_1844 = or(_T_1843, _T_1804) node _T_1845 = or(_T_1844, _T_1805) node _T_1846 = or(_T_1845, _T_1806) node _T_1847 = or(_T_1846, _T_1807) node _T_1848 = or(_T_1847, _T_1808) node _T_1849 = or(_T_1848, _T_1809) node _T_1850 = or(_T_1849, _T_1810) node _T_1851 = or(_T_1850, _T_1811) node _T_1852 = or(_T_1851, _T_1812) node _T_1853 = or(_T_1852, _T_1813) node _T_1854 = or(_T_1853, _T_1814) node _T_1855 = and(_T_1753, _T_1854) node _T_1856 = or(UInt<1>(0h0), _T_1855) node _T_1857 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1858 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = or(UInt<1>(0h0), _T_1859) node _T_1861 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1862 = cvt(_T_1861) node _T_1863 = and(_T_1862, asSInt(UInt<14>(0h2000))) node _T_1864 = asSInt(_T_1863) node _T_1865 = eq(_T_1864, asSInt(UInt<1>(0h0))) node _T_1866 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1867 = cvt(_T_1866) node _T_1868 = and(_T_1867, asSInt(UInt<13>(0h1000))) node _T_1869 = asSInt(_T_1868) node _T_1870 = eq(_T_1869, asSInt(UInt<1>(0h0))) node _T_1871 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1872 = cvt(_T_1871) node _T_1873 = and(_T_1872, asSInt(UInt<18>(0h2f000))) node _T_1874 = asSInt(_T_1873) node _T_1875 = eq(_T_1874, asSInt(UInt<1>(0h0))) node _T_1876 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1877 = cvt(_T_1876) node _T_1878 = and(_T_1877, asSInt(UInt<17>(0h10000))) node _T_1879 = asSInt(_T_1878) node _T_1880 = eq(_T_1879, asSInt(UInt<1>(0h0))) node _T_1881 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1882 = cvt(_T_1881) node _T_1883 = and(_T_1882, asSInt(UInt<13>(0h1000))) node _T_1884 = asSInt(_T_1883) node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1887 = cvt(_T_1886) node _T_1888 = and(_T_1887, asSInt(UInt<27>(0h4000000))) node _T_1889 = asSInt(_T_1888) node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0))) node _T_1891 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<13>(0h1000))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = or(_T_1865, _T_1870) node _T_1897 = or(_T_1896, _T_1875) node _T_1898 = or(_T_1897, _T_1880) node _T_1899 = or(_T_1898, _T_1885) node _T_1900 = or(_T_1899, _T_1890) node _T_1901 = or(_T_1900, _T_1895) node _T_1902 = and(_T_1860, _T_1901) node _T_1903 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = and(_T_1903, _T_1908) node _T_1910 = or(UInt<1>(0h0), _T_1902) node _T_1911 = or(_T_1910, _T_1909) node _T_1912 = and(_T_1856, _T_1911) node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(_T_1912, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1912, UInt<1>(0h1), "") : assert_36 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(source_ok, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(is_aligned, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1922 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(_T_1922, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1922, UInt<1>(0h1), "") : assert_39 node _T_1926 = eq(io.in.a.bits.mask, mask) node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(_T_1926, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1926, UInt<1>(0h1), "") : assert_40 node _T_1930 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1930 : node _T_1931 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1932 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1933 = and(_T_1931, _T_1932) node _T_1934 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1935 = shr(io.in.a.bits.source, 2) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) node _T_1937 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1938 = and(_T_1936, _T_1937) node _T_1939 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1940 = and(_T_1938, _T_1939) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1941 = shr(io.in.a.bits.source, 2) node _T_1942 = eq(_T_1941, UInt<1>(0h1)) node _T_1943 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1944 = and(_T_1942, _T_1943) node _T_1945 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1946 = and(_T_1944, _T_1945) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1947 = shr(io.in.a.bits.source, 2) node _T_1948 = eq(_T_1947, UInt<2>(0h2)) node _T_1949 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1950 = and(_T_1948, _T_1949) node _T_1951 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1952 = and(_T_1950, _T_1951) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1953 = shr(io.in.a.bits.source, 2) node _T_1954 = eq(_T_1953, UInt<2>(0h3)) node _T_1955 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1956 = and(_T_1954, _T_1955) node _T_1957 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1958 = and(_T_1956, _T_1957) node _T_1959 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1960 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1961 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1962 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1963 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1964 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1965 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1966 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1967 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1968 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1969 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1970 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1971 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1972 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1973 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1974 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1975 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1976 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1977 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1978 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1979 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1980 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1981 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1982 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1983 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1984 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1985 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1986 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1987 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1988 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1989 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1990 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1991 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1992 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1993 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1994 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1995 = or(_T_1934, _T_1940) node _T_1996 = or(_T_1995, _T_1946) node _T_1997 = or(_T_1996, _T_1952) node _T_1998 = or(_T_1997, _T_1958) node _T_1999 = or(_T_1998, _T_1959) node _T_2000 = or(_T_1999, _T_1960) node _T_2001 = or(_T_2000, _T_1961) node _T_2002 = or(_T_2001, _T_1962) node _T_2003 = or(_T_2002, _T_1963) node _T_2004 = or(_T_2003, _T_1964) node _T_2005 = or(_T_2004, _T_1965) node _T_2006 = or(_T_2005, _T_1966) node _T_2007 = or(_T_2006, _T_1967) node _T_2008 = or(_T_2007, _T_1968) node _T_2009 = or(_T_2008, _T_1969) node _T_2010 = or(_T_2009, _T_1970) node _T_2011 = or(_T_2010, _T_1971) node _T_2012 = or(_T_2011, _T_1972) node _T_2013 = or(_T_2012, _T_1973) node _T_2014 = or(_T_2013, _T_1974) node _T_2015 = or(_T_2014, _T_1975) node _T_2016 = or(_T_2015, _T_1976) node _T_2017 = or(_T_2016, _T_1977) node _T_2018 = or(_T_2017, _T_1978) node _T_2019 = or(_T_2018, _T_1979) node _T_2020 = or(_T_2019, _T_1980) node _T_2021 = or(_T_2020, _T_1981) node _T_2022 = or(_T_2021, _T_1982) node _T_2023 = or(_T_2022, _T_1983) node _T_2024 = or(_T_2023, _T_1984) node _T_2025 = or(_T_2024, _T_1985) node _T_2026 = or(_T_2025, _T_1986) node _T_2027 = or(_T_2026, _T_1987) node _T_2028 = or(_T_2027, _T_1988) node _T_2029 = or(_T_2028, _T_1989) node _T_2030 = or(_T_2029, _T_1990) node _T_2031 = or(_T_2030, _T_1991) node _T_2032 = or(_T_2031, _T_1992) node _T_2033 = or(_T_2032, _T_1993) node _T_2034 = or(_T_2033, _T_1994) node _T_2035 = and(_T_1933, _T_2034) node _T_2036 = or(UInt<1>(0h0), _T_2035) node _T_2037 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2038 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_2039 = and(_T_2037, _T_2038) node _T_2040 = or(UInt<1>(0h0), _T_2039) node _T_2041 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_2042 = cvt(_T_2041) node _T_2043 = and(_T_2042, asSInt(UInt<14>(0h2000))) node _T_2044 = asSInt(_T_2043) node _T_2045 = eq(_T_2044, asSInt(UInt<1>(0h0))) node _T_2046 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_2047 = cvt(_T_2046) node _T_2048 = and(_T_2047, asSInt(UInt<13>(0h1000))) node _T_2049 = asSInt(_T_2048) node _T_2050 = eq(_T_2049, asSInt(UInt<1>(0h0))) node _T_2051 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2052 = cvt(_T_2051) node _T_2053 = and(_T_2052, asSInt(UInt<18>(0h2f000))) node _T_2054 = asSInt(_T_2053) node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0))) node _T_2056 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_2057 = cvt(_T_2056) node _T_2058 = and(_T_2057, asSInt(UInt<17>(0h10000))) node _T_2059 = asSInt(_T_2058) node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0))) node _T_2061 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_2062 = cvt(_T_2061) node _T_2063 = and(_T_2062, asSInt(UInt<13>(0h1000))) node _T_2064 = asSInt(_T_2063) node _T_2065 = eq(_T_2064, asSInt(UInt<1>(0h0))) node _T_2066 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_2067 = cvt(_T_2066) node _T_2068 = and(_T_2067, asSInt(UInt<27>(0h4000000))) node _T_2069 = asSInt(_T_2068) node _T_2070 = eq(_T_2069, asSInt(UInt<1>(0h0))) node _T_2071 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_2072 = cvt(_T_2071) node _T_2073 = and(_T_2072, asSInt(UInt<13>(0h1000))) node _T_2074 = asSInt(_T_2073) node _T_2075 = eq(_T_2074, asSInt(UInt<1>(0h0))) node _T_2076 = or(_T_2045, _T_2050) node _T_2077 = or(_T_2076, _T_2055) node _T_2078 = or(_T_2077, _T_2060) node _T_2079 = or(_T_2078, _T_2065) node _T_2080 = or(_T_2079, _T_2070) node _T_2081 = or(_T_2080, _T_2075) node _T_2082 = and(_T_2040, _T_2081) node _T_2083 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2084 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<17>(0h10000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = and(_T_2083, _T_2088) node _T_2090 = or(UInt<1>(0h0), _T_2082) node _T_2091 = or(_T_2090, _T_2089) node _T_2092 = and(_T_2036, _T_2091) node _T_2093 = asUInt(reset) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) when _T_2094 : node _T_2095 = eq(_T_2092, UInt<1>(0h0)) when _T_2095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_2092, UInt<1>(0h1), "") : assert_41 node _T_2096 = asUInt(reset) node _T_2097 = eq(_T_2096, UInt<1>(0h0)) when _T_2097 : node _T_2098 = eq(source_ok, UInt<1>(0h0)) when _T_2098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_2099 = asUInt(reset) node _T_2100 = eq(_T_2099, UInt<1>(0h0)) when _T_2100 : node _T_2101 = eq(is_aligned, UInt<1>(0h0)) when _T_2101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_2102 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_2103 = asUInt(reset) node _T_2104 = eq(_T_2103, UInt<1>(0h0)) when _T_2104 : node _T_2105 = eq(_T_2102, UInt<1>(0h0)) when _T_2105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_2102, UInt<1>(0h1), "") : assert_44 node _T_2106 = eq(io.in.a.bits.mask, mask) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_45 node _T_2110 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_2110 : node _T_2111 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2112 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2113 = and(_T_2111, _T_2112) node _T_2114 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_2115 = shr(io.in.a.bits.source, 2) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) node _T_2117 = leq(UInt<1>(0h0), uncommonBits_40) node _T_2118 = and(_T_2116, _T_2117) node _T_2119 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_2120 = and(_T_2118, _T_2119) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_2121 = shr(io.in.a.bits.source, 2) node _T_2122 = eq(_T_2121, UInt<1>(0h1)) node _T_2123 = leq(UInt<1>(0h0), uncommonBits_41) node _T_2124 = and(_T_2122, _T_2123) node _T_2125 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_2126 = and(_T_2124, _T_2125) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_2127 = shr(io.in.a.bits.source, 2) node _T_2128 = eq(_T_2127, UInt<2>(0h2)) node _T_2129 = leq(UInt<1>(0h0), uncommonBits_42) node _T_2130 = and(_T_2128, _T_2129) node _T_2131 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_2132 = and(_T_2130, _T_2131) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_2133 = shr(io.in.a.bits.source, 2) node _T_2134 = eq(_T_2133, UInt<2>(0h3)) node _T_2135 = leq(UInt<1>(0h0), uncommonBits_43) node _T_2136 = and(_T_2134, _T_2135) node _T_2137 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_2138 = and(_T_2136, _T_2137) node _T_2139 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_2140 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_2141 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_2142 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_2143 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_2144 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_2145 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_2146 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_2147 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_2148 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_2149 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_2150 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_2151 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_2152 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_2153 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_2154 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_2155 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_2156 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_2157 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_2158 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_2159 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_2160 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_2161 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_2162 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_2163 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_2164 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_2165 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_2166 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_2167 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_2168 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_2169 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_2170 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_2171 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_2172 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_2173 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_2174 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_2175 = or(_T_2114, _T_2120) node _T_2176 = or(_T_2175, _T_2126) node _T_2177 = or(_T_2176, _T_2132) node _T_2178 = or(_T_2177, _T_2138) node _T_2179 = or(_T_2178, _T_2139) node _T_2180 = or(_T_2179, _T_2140) node _T_2181 = or(_T_2180, _T_2141) node _T_2182 = or(_T_2181, _T_2142) node _T_2183 = or(_T_2182, _T_2143) node _T_2184 = or(_T_2183, _T_2144) node _T_2185 = or(_T_2184, _T_2145) node _T_2186 = or(_T_2185, _T_2146) node _T_2187 = or(_T_2186, _T_2147) node _T_2188 = or(_T_2187, _T_2148) node _T_2189 = or(_T_2188, _T_2149) node _T_2190 = or(_T_2189, _T_2150) node _T_2191 = or(_T_2190, _T_2151) node _T_2192 = or(_T_2191, _T_2152) node _T_2193 = or(_T_2192, _T_2153) node _T_2194 = or(_T_2193, _T_2154) node _T_2195 = or(_T_2194, _T_2155) node _T_2196 = or(_T_2195, _T_2156) node _T_2197 = or(_T_2196, _T_2157) node _T_2198 = or(_T_2197, _T_2158) node _T_2199 = or(_T_2198, _T_2159) node _T_2200 = or(_T_2199, _T_2160) node _T_2201 = or(_T_2200, _T_2161) node _T_2202 = or(_T_2201, _T_2162) node _T_2203 = or(_T_2202, _T_2163) node _T_2204 = or(_T_2203, _T_2164) node _T_2205 = or(_T_2204, _T_2165) node _T_2206 = or(_T_2205, _T_2166) node _T_2207 = or(_T_2206, _T_2167) node _T_2208 = or(_T_2207, _T_2168) node _T_2209 = or(_T_2208, _T_2169) node _T_2210 = or(_T_2209, _T_2170) node _T_2211 = or(_T_2210, _T_2171) node _T_2212 = or(_T_2211, _T_2172) node _T_2213 = or(_T_2212, _T_2173) node _T_2214 = or(_T_2213, _T_2174) node _T_2215 = and(_T_2113, _T_2214) node _T_2216 = or(UInt<1>(0h0), _T_2215) node _T_2217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2219 = and(_T_2217, _T_2218) node _T_2220 = or(UInt<1>(0h0), _T_2219) node _T_2221 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_2222 = cvt(_T_2221) node _T_2223 = and(_T_2222, asSInt(UInt<13>(0h1000))) node _T_2224 = asSInt(_T_2223) node _T_2225 = eq(_T_2224, asSInt(UInt<1>(0h0))) node _T_2226 = and(_T_2220, _T_2225) node _T_2227 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2228 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_2229 = cvt(_T_2228) node _T_2230 = and(_T_2229, asSInt(UInt<14>(0h2000))) node _T_2231 = asSInt(_T_2230) node _T_2232 = eq(_T_2231, asSInt(UInt<1>(0h0))) node _T_2233 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_2234 = cvt(_T_2233) node _T_2235 = and(_T_2234, asSInt(UInt<17>(0h10000))) node _T_2236 = asSInt(_T_2235) node _T_2237 = eq(_T_2236, asSInt(UInt<1>(0h0))) node _T_2238 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2239 = cvt(_T_2238) node _T_2240 = and(_T_2239, asSInt(UInt<18>(0h2f000))) node _T_2241 = asSInt(_T_2240) node _T_2242 = eq(_T_2241, asSInt(UInt<1>(0h0))) node _T_2243 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_2244 = cvt(_T_2243) node _T_2245 = and(_T_2244, asSInt(UInt<17>(0h10000))) node _T_2246 = asSInt(_T_2245) node _T_2247 = eq(_T_2246, asSInt(UInt<1>(0h0))) node _T_2248 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_2249 = cvt(_T_2248) node _T_2250 = and(_T_2249, asSInt(UInt<13>(0h1000))) node _T_2251 = asSInt(_T_2250) node _T_2252 = eq(_T_2251, asSInt(UInt<1>(0h0))) node _T_2253 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_2254 = cvt(_T_2253) node _T_2255 = and(_T_2254, asSInt(UInt<27>(0h4000000))) node _T_2256 = asSInt(_T_2255) node _T_2257 = eq(_T_2256, asSInt(UInt<1>(0h0))) node _T_2258 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_2259 = cvt(_T_2258) node _T_2260 = and(_T_2259, asSInt(UInt<13>(0h1000))) node _T_2261 = asSInt(_T_2260) node _T_2262 = eq(_T_2261, asSInt(UInt<1>(0h0))) node _T_2263 = or(_T_2232, _T_2237) node _T_2264 = or(_T_2263, _T_2242) node _T_2265 = or(_T_2264, _T_2247) node _T_2266 = or(_T_2265, _T_2252) node _T_2267 = or(_T_2266, _T_2257) node _T_2268 = or(_T_2267, _T_2262) node _T_2269 = and(_T_2227, _T_2268) node _T_2270 = or(UInt<1>(0h0), _T_2226) node _T_2271 = or(_T_2270, _T_2269) node _T_2272 = and(_T_2216, _T_2271) node _T_2273 = asUInt(reset) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(_T_2272, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2272, UInt<1>(0h1), "") : assert_46 node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(source_ok, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2279 = asUInt(reset) node _T_2280 = eq(_T_2279, UInt<1>(0h0)) when _T_2280 : node _T_2281 = eq(is_aligned, UInt<1>(0h0)) when _T_2281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2282 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2283 = asUInt(reset) node _T_2284 = eq(_T_2283, UInt<1>(0h0)) when _T_2284 : node _T_2285 = eq(_T_2282, UInt<1>(0h0)) when _T_2285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2282, UInt<1>(0h1), "") : assert_49 node _T_2286 = eq(io.in.a.bits.mask, mask) node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(_T_2286, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2286, UInt<1>(0h1), "") : assert_50 node _T_2290 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2294 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_52 node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_101 = shr(io.in.d.bits.source, 2) node _source_ok_T_102 = eq(_source_ok_T_101, UInt<1>(0h0)) node _source_ok_T_103 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_T_105 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_107 = shr(io.in.d.bits.source, 2) node _source_ok_T_108 = eq(_source_ok_T_107, UInt<1>(0h1)) node _source_ok_T_109 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_T_111 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_113 = shr(io.in.d.bits.source, 2) node _source_ok_T_114 = eq(_source_ok_T_113, UInt<2>(0h2)) node _source_ok_T_115 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_119 = shr(io.in.d.bits.source, 2) node _source_ok_T_120 = eq(_source_ok_T_119, UInt<2>(0h3)) node _source_ok_T_121 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_122 = and(_source_ok_T_120, _source_ok_T_121) node _source_ok_T_123 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[41] connect _source_ok_WIRE_1[0], _source_ok_T_100 connect _source_ok_WIRE_1[1], _source_ok_T_106 connect _source_ok_WIRE_1[2], _source_ok_T_112 connect _source_ok_WIRE_1[3], _source_ok_T_118 connect _source_ok_WIRE_1[4], _source_ok_T_124 connect _source_ok_WIRE_1[5], _source_ok_T_125 connect _source_ok_WIRE_1[6], _source_ok_T_126 connect _source_ok_WIRE_1[7], _source_ok_T_127 connect _source_ok_WIRE_1[8], _source_ok_T_128 connect _source_ok_WIRE_1[9], _source_ok_T_129 connect _source_ok_WIRE_1[10], _source_ok_T_130 connect _source_ok_WIRE_1[11], _source_ok_T_131 connect _source_ok_WIRE_1[12], _source_ok_T_132 connect _source_ok_WIRE_1[13], _source_ok_T_133 connect _source_ok_WIRE_1[14], _source_ok_T_134 connect _source_ok_WIRE_1[15], _source_ok_T_135 connect _source_ok_WIRE_1[16], _source_ok_T_136 connect _source_ok_WIRE_1[17], _source_ok_T_137 connect _source_ok_WIRE_1[18], _source_ok_T_138 connect _source_ok_WIRE_1[19], _source_ok_T_139 connect _source_ok_WIRE_1[20], _source_ok_T_140 connect _source_ok_WIRE_1[21], _source_ok_T_141 connect _source_ok_WIRE_1[22], _source_ok_T_142 connect _source_ok_WIRE_1[23], _source_ok_T_143 connect _source_ok_WIRE_1[24], _source_ok_T_144 connect _source_ok_WIRE_1[25], _source_ok_T_145 connect _source_ok_WIRE_1[26], _source_ok_T_146 connect _source_ok_WIRE_1[27], _source_ok_T_147 connect _source_ok_WIRE_1[28], _source_ok_T_148 connect _source_ok_WIRE_1[29], _source_ok_T_149 connect _source_ok_WIRE_1[30], _source_ok_T_150 connect _source_ok_WIRE_1[31], _source_ok_T_151 connect _source_ok_WIRE_1[32], _source_ok_T_152 connect _source_ok_WIRE_1[33], _source_ok_T_153 connect _source_ok_WIRE_1[34], _source_ok_T_154 connect _source_ok_WIRE_1[35], _source_ok_T_155 connect _source_ok_WIRE_1[36], _source_ok_T_156 connect _source_ok_WIRE_1[37], _source_ok_T_157 connect _source_ok_WIRE_1[38], _source_ok_T_158 connect _source_ok_WIRE_1[39], _source_ok_T_159 connect _source_ok_WIRE_1[40], _source_ok_T_160 node _source_ok_T_161 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_162 = or(_source_ok_T_161, _source_ok_WIRE_1[2]) node _source_ok_T_163 = or(_source_ok_T_162, _source_ok_WIRE_1[3]) node _source_ok_T_164 = or(_source_ok_T_163, _source_ok_WIRE_1[4]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[5]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[6]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[7]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[8]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[9]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[10]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[11]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[12]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[13]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[14]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[15]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[16]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[17]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[18]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[19]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[20]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[21]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[22]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[23]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[24]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[25]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[26]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[27]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[28]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[29]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[30]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[31]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[32]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[33]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[34]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[35]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[36]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[37]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[38]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[39]) node source_ok_1 = or(_source_ok_T_199, _source_ok_WIRE_1[40]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2298 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2298 : node _T_2299 = asUInt(reset) node _T_2300 = eq(_T_2299, UInt<1>(0h0)) when _T_2300 : node _T_2301 = eq(source_ok_1, UInt<1>(0h0)) when _T_2301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2302 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_54 node _T_2306 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2307 = asUInt(reset) node _T_2308 = eq(_T_2307, UInt<1>(0h0)) when _T_2308 : node _T_2309 = eq(_T_2306, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2306, UInt<1>(0h1), "") : assert_55 node _T_2310 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2311 = asUInt(reset) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) when _T_2312 : node _T_2313 = eq(_T_2310, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2310, UInt<1>(0h1), "") : assert_56 node _T_2314 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2315 = asUInt(reset) node _T_2316 = eq(_T_2315, UInt<1>(0h0)) when _T_2316 : node _T_2317 = eq(_T_2314, UInt<1>(0h0)) when _T_2317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2314, UInt<1>(0h1), "") : assert_57 node _T_2318 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2318 : node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(source_ok_1, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2322 = asUInt(reset) node _T_2323 = eq(_T_2322, UInt<1>(0h0)) when _T_2323 : node _T_2324 = eq(sink_ok, UInt<1>(0h0)) when _T_2324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2325 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2326 = asUInt(reset) node _T_2327 = eq(_T_2326, UInt<1>(0h0)) when _T_2327 : node _T_2328 = eq(_T_2325, UInt<1>(0h0)) when _T_2328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2325, UInt<1>(0h1), "") : assert_60 node _T_2329 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2330 = asUInt(reset) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) when _T_2331 : node _T_2332 = eq(_T_2329, UInt<1>(0h0)) when _T_2332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2329, UInt<1>(0h1), "") : assert_61 node _T_2333 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2334 = asUInt(reset) node _T_2335 = eq(_T_2334, UInt<1>(0h0)) when _T_2335 : node _T_2336 = eq(_T_2333, UInt<1>(0h0)) when _T_2336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2333, UInt<1>(0h1), "") : assert_62 node _T_2337 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_63 node _T_2341 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2342 = or(UInt<1>(0h1), _T_2341) node _T_2343 = asUInt(reset) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) when _T_2344 : node _T_2345 = eq(_T_2342, UInt<1>(0h0)) when _T_2345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2342, UInt<1>(0h1), "") : assert_64 node _T_2346 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2346 : node _T_2347 = asUInt(reset) node _T_2348 = eq(_T_2347, UInt<1>(0h0)) when _T_2348 : node _T_2349 = eq(source_ok_1, UInt<1>(0h0)) when _T_2349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2350 = asUInt(reset) node _T_2351 = eq(_T_2350, UInt<1>(0h0)) when _T_2351 : node _T_2352 = eq(sink_ok, UInt<1>(0h0)) when _T_2352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2353 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2354 = asUInt(reset) node _T_2355 = eq(_T_2354, UInt<1>(0h0)) when _T_2355 : node _T_2356 = eq(_T_2353, UInt<1>(0h0)) when _T_2356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2353, UInt<1>(0h1), "") : assert_67 node _T_2357 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2358 = asUInt(reset) node _T_2359 = eq(_T_2358, UInt<1>(0h0)) when _T_2359 : node _T_2360 = eq(_T_2357, UInt<1>(0h0)) when _T_2360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2357, UInt<1>(0h1), "") : assert_68 node _T_2361 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2362 = asUInt(reset) node _T_2363 = eq(_T_2362, UInt<1>(0h0)) when _T_2363 : node _T_2364 = eq(_T_2361, UInt<1>(0h0)) when _T_2364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2361, UInt<1>(0h1), "") : assert_69 node _T_2365 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2366 = or(_T_2365, io.in.d.bits.corrupt) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_70 node _T_2370 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2371 = or(UInt<1>(0h1), _T_2370) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_71 node _T_2375 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2375 : node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(source_ok_1, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2379 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_73 node _T_2383 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_74 node _T_2387 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2388 = or(UInt<1>(0h1), _T_2387) node _T_2389 = asUInt(reset) node _T_2390 = eq(_T_2389, UInt<1>(0h0)) when _T_2390 : node _T_2391 = eq(_T_2388, UInt<1>(0h0)) when _T_2391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2388, UInt<1>(0h1), "") : assert_75 node _T_2392 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2392 : node _T_2393 = asUInt(reset) node _T_2394 = eq(_T_2393, UInt<1>(0h0)) when _T_2394 : node _T_2395 = eq(source_ok_1, UInt<1>(0h0)) when _T_2395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2396 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2397 = asUInt(reset) node _T_2398 = eq(_T_2397, UInt<1>(0h0)) when _T_2398 : node _T_2399 = eq(_T_2396, UInt<1>(0h0)) when _T_2399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2396, UInt<1>(0h1), "") : assert_77 node _T_2400 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2401 = or(_T_2400, io.in.d.bits.corrupt) node _T_2402 = asUInt(reset) node _T_2403 = eq(_T_2402, UInt<1>(0h0)) when _T_2403 : node _T_2404 = eq(_T_2401, UInt<1>(0h0)) when _T_2404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2401, UInt<1>(0h1), "") : assert_78 node _T_2405 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2406 = or(UInt<1>(0h1), _T_2405) node _T_2407 = asUInt(reset) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) when _T_2408 : node _T_2409 = eq(_T_2406, UInt<1>(0h0)) when _T_2409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2406, UInt<1>(0h1), "") : assert_79 node _T_2410 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2410 : node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(source_ok_1, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2414 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_81 node _T_2418 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2419 = asUInt(reset) node _T_2420 = eq(_T_2419, UInt<1>(0h0)) when _T_2420 : node _T_2421 = eq(_T_2418, UInt<1>(0h0)) when _T_2421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2418, UInt<1>(0h1), "") : assert_82 node _T_2422 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2423 = or(UInt<1>(0h1), _T_2422) node _T_2424 = asUInt(reset) node _T_2425 = eq(_T_2424, UInt<1>(0h0)) when _T_2425 : node _T_2426 = eq(_T_2423, UInt<1>(0h0)) when _T_2426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2423, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2427 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2431 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2435 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2439 = eq(a_first, UInt<1>(0h0)) node _T_2440 = and(io.in.a.valid, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.a.bits.opcode, opcode) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_87 node _T_2445 = eq(io.in.a.bits.param, param) node _T_2446 = asUInt(reset) node _T_2447 = eq(_T_2446, UInt<1>(0h0)) when _T_2447 : node _T_2448 = eq(_T_2445, UInt<1>(0h0)) when _T_2448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2445, UInt<1>(0h1), "") : assert_88 node _T_2449 = eq(io.in.a.bits.size, size) node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(_T_2449, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2449, UInt<1>(0h1), "") : assert_89 node _T_2453 = eq(io.in.a.bits.source, source) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_90 node _T_2457 = eq(io.in.a.bits.address, address) node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(_T_2457, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2457, UInt<1>(0h1), "") : assert_91 node _T_2461 = and(io.in.a.ready, io.in.a.valid) node _T_2462 = and(_T_2461, a_first) when _T_2462 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2463 = eq(d_first, UInt<1>(0h0)) node _T_2464 = and(io.in.d.valid, _T_2463) when _T_2464 : node _T_2465 = eq(io.in.d.bits.opcode, opcode_1) node _T_2466 = asUInt(reset) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) when _T_2467 : node _T_2468 = eq(_T_2465, UInt<1>(0h0)) when _T_2468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2465, UInt<1>(0h1), "") : assert_92 node _T_2469 = eq(io.in.d.bits.param, param_1) node _T_2470 = asUInt(reset) node _T_2471 = eq(_T_2470, UInt<1>(0h0)) when _T_2471 : node _T_2472 = eq(_T_2469, UInt<1>(0h0)) when _T_2472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2469, UInt<1>(0h1), "") : assert_93 node _T_2473 = eq(io.in.d.bits.size, size_1) node _T_2474 = asUInt(reset) node _T_2475 = eq(_T_2474, UInt<1>(0h0)) when _T_2475 : node _T_2476 = eq(_T_2473, UInt<1>(0h0)) when _T_2476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2473, UInt<1>(0h1), "") : assert_94 node _T_2477 = eq(io.in.d.bits.source, source_1) node _T_2478 = asUInt(reset) node _T_2479 = eq(_T_2478, UInt<1>(0h0)) when _T_2479 : node _T_2480 = eq(_T_2477, UInt<1>(0h0)) when _T_2480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2477, UInt<1>(0h1), "") : assert_95 node _T_2481 = eq(io.in.d.bits.sink, sink) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_96 node _T_2485 = eq(io.in.d.bits.denied, denied) node _T_2486 = asUInt(reset) node _T_2487 = eq(_T_2486, UInt<1>(0h0)) when _T_2487 : node _T_2488 = eq(_T_2485, UInt<1>(0h0)) when _T_2488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2485, UInt<1>(0h1), "") : assert_97 node _T_2489 = and(io.in.d.ready, io.in.d.valid) node _T_2490 = and(_T_2489, d_first) when _T_2490 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<79>, clock, reset, UInt<79>(0h0) regreset inflight_opcodes : UInt<316>, clock, reset, UInt<316>(0h0) regreset inflight_sizes : UInt<632>, clock, reset, UInt<632>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<79> connect a_set, UInt<79>(0h0) wire a_set_wo_ready : UInt<79> connect a_set_wo_ready, UInt<79>(0h0) wire a_opcodes_set : UInt<316> connect a_opcodes_set, UInt<316>(0h0) wire a_sizes_set : UInt<632> connect a_sizes_set, UInt<632>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2491 = and(io.in.a.valid, a_first_1) node _T_2492 = and(_T_2491, UInt<1>(0h1)) when _T_2492 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2493 = and(io.in.a.ready, io.in.a.valid) node _T_2494 = and(_T_2493, a_first_1) node _T_2495 = and(_T_2494, UInt<1>(0h1)) when _T_2495 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2496 = dshr(inflight, io.in.a.bits.source) node _T_2497 = bits(_T_2496, 0, 0) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) node _T_2499 = asUInt(reset) node _T_2500 = eq(_T_2499, UInt<1>(0h0)) when _T_2500 : node _T_2501 = eq(_T_2498, UInt<1>(0h0)) when _T_2501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2498, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<79> connect d_clr, UInt<79>(0h0) wire d_clr_wo_ready : UInt<79> connect d_clr_wo_ready, UInt<79>(0h0) wire d_opcodes_clr : UInt<316> connect d_opcodes_clr, UInt<316>(0h0) wire d_sizes_clr : UInt<632> connect d_sizes_clr, UInt<632>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2502 = and(io.in.d.valid, d_first_1) node _T_2503 = and(_T_2502, UInt<1>(0h1)) node _T_2504 = eq(d_release_ack, UInt<1>(0h0)) node _T_2505 = and(_T_2503, _T_2504) when _T_2505 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2506 = and(io.in.d.ready, io.in.d.valid) node _T_2507 = and(_T_2506, d_first_1) node _T_2508 = and(_T_2507, UInt<1>(0h1)) node _T_2509 = eq(d_release_ack, UInt<1>(0h0)) node _T_2510 = and(_T_2508, _T_2509) when _T_2510 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2511 = and(io.in.d.valid, d_first_1) node _T_2512 = and(_T_2511, UInt<1>(0h1)) node _T_2513 = eq(d_release_ack, UInt<1>(0h0)) node _T_2514 = and(_T_2512, _T_2513) when _T_2514 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2515 = dshr(inflight, io.in.d.bits.source) node _T_2516 = bits(_T_2515, 0, 0) node _T_2517 = or(_T_2516, same_cycle_resp) node _T_2518 = asUInt(reset) node _T_2519 = eq(_T_2518, UInt<1>(0h0)) when _T_2519 : node _T_2520 = eq(_T_2517, UInt<1>(0h0)) when _T_2520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2517, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2521 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2522 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2523 = or(_T_2521, _T_2522) node _T_2524 = asUInt(reset) node _T_2525 = eq(_T_2524, UInt<1>(0h0)) when _T_2525 : node _T_2526 = eq(_T_2523, UInt<1>(0h0)) when _T_2526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2523, UInt<1>(0h1), "") : assert_100 node _T_2527 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2528 = asUInt(reset) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) when _T_2529 : node _T_2530 = eq(_T_2527, UInt<1>(0h0)) when _T_2530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2527, UInt<1>(0h1), "") : assert_101 else : node _T_2531 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2532 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2533 = or(_T_2531, _T_2532) node _T_2534 = asUInt(reset) node _T_2535 = eq(_T_2534, UInt<1>(0h0)) when _T_2535 : node _T_2536 = eq(_T_2533, UInt<1>(0h0)) when _T_2536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2533, UInt<1>(0h1), "") : assert_102 node _T_2537 = eq(io.in.d.bits.size, a_size_lookup) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_103 node _T_2541 = and(io.in.d.valid, d_first_1) node _T_2542 = and(_T_2541, a_first_1) node _T_2543 = and(_T_2542, io.in.a.valid) node _T_2544 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2545 = and(_T_2543, _T_2544) node _T_2546 = eq(d_release_ack, UInt<1>(0h0)) node _T_2547 = and(_T_2545, _T_2546) when _T_2547 : node _T_2548 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2549 = or(_T_2548, io.in.a.ready) node _T_2550 = asUInt(reset) node _T_2551 = eq(_T_2550, UInt<1>(0h0)) when _T_2551 : node _T_2552 = eq(_T_2549, UInt<1>(0h0)) when _T_2552 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2549, UInt<1>(0h1), "") : assert_104 node _T_2553 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2554 = orr(a_set_wo_ready) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) node _T_2556 = or(_T_2553, _T_2555) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_86 node _T_2560 = orr(inflight) node _T_2561 = eq(_T_2560, UInt<1>(0h0)) node _T_2562 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2563 = or(_T_2561, _T_2562) node _T_2564 = lt(watchdog, plusarg_reader.out) node _T_2565 = or(_T_2563, _T_2564) node _T_2566 = asUInt(reset) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) when _T_2567 : node _T_2568 = eq(_T_2565, UInt<1>(0h0)) when _T_2568 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2565, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2569 = and(io.in.a.ready, io.in.a.valid) node _T_2570 = and(io.in.d.ready, io.in.d.valid) node _T_2571 = or(_T_2569, _T_2570) when _T_2571 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<79>, clock, reset, UInt<79>(0h0) regreset inflight_opcodes_1 : UInt<316>, clock, reset, UInt<316>(0h0) regreset inflight_sizes_1 : UInt<632>, clock, reset, UInt<632>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<79> connect c_set, UInt<79>(0h0) wire c_set_wo_ready : UInt<79> connect c_set_wo_ready, UInt<79>(0h0) wire c_opcodes_set : UInt<316> connect c_opcodes_set, UInt<316>(0h0) wire c_sizes_set : UInt<632> connect c_sizes_set, UInt<632>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2572 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2573 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2574 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2575 = and(_T_2573, _T_2574) node _T_2576 = and(_T_2572, _T_2575) when _T_2576 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2577 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2578 = and(_T_2577, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2579 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2580 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2581 = and(_T_2579, _T_2580) node _T_2582 = and(_T_2578, _T_2581) when _T_2582 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2583 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2584 = bits(_T_2583, 0, 0) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<79> connect d_clr_1, UInt<79>(0h0) wire d_clr_wo_ready_1 : UInt<79> connect d_clr_wo_ready_1, UInt<79>(0h0) wire d_opcodes_clr_1 : UInt<316> connect d_opcodes_clr_1, UInt<316>(0h0) wire d_sizes_clr_1 : UInt<632> connect d_sizes_clr_1, UInt<632>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2589 = and(io.in.d.valid, d_first_2) node _T_2590 = and(_T_2589, UInt<1>(0h1)) node _T_2591 = and(_T_2590, d_release_ack_1) when _T_2591 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2592 = and(io.in.d.ready, io.in.d.valid) node _T_2593 = and(_T_2592, d_first_2) node _T_2594 = and(_T_2593, UInt<1>(0h1)) node _T_2595 = and(_T_2594, d_release_ack_1) when _T_2595 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2596 = and(io.in.d.valid, d_first_2) node _T_2597 = and(_T_2596, UInt<1>(0h1)) node _T_2598 = and(_T_2597, d_release_ack_1) when _T_2598 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2599 = dshr(inflight_1, io.in.d.bits.source) node _T_2600 = bits(_T_2599, 0, 0) node _T_2601 = or(_T_2600, same_cycle_resp_1) node _T_2602 = asUInt(reset) node _T_2603 = eq(_T_2602, UInt<1>(0h0)) when _T_2603 : node _T_2604 = eq(_T_2601, UInt<1>(0h0)) when _T_2604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2601, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2605 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2606 = asUInt(reset) node _T_2607 = eq(_T_2606, UInt<1>(0h0)) when _T_2607 : node _T_2608 = eq(_T_2605, UInt<1>(0h0)) when _T_2608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2605, UInt<1>(0h1), "") : assert_109 else : node _T_2609 = eq(io.in.d.bits.size, c_size_lookup) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_110 node _T_2613 = and(io.in.d.valid, d_first_2) node _T_2614 = and(_T_2613, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2615 = and(_T_2614, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2616 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2617 = and(_T_2615, _T_2616) node _T_2618 = and(_T_2617, d_release_ack_1) node _T_2619 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2620 = and(_T_2618, _T_2619) when _T_2620 : node _T_2621 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2622 = or(_T_2621, _WIRE_27.ready) node _T_2623 = asUInt(reset) node _T_2624 = eq(_T_2623, UInt<1>(0h0)) when _T_2624 : node _T_2625 = eq(_T_2622, UInt<1>(0h0)) when _T_2625 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_2622, UInt<1>(0h1), "") : assert_111 node _T_2626 = orr(c_set_wo_ready) when _T_2626 : node _T_2627 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2628 = asUInt(reset) node _T_2629 = eq(_T_2628, UInt<1>(0h0)) when _T_2629 : node _T_2630 = eq(_T_2627, UInt<1>(0h0)) when _T_2630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_2627, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_87 node _T_2631 = orr(inflight_1) node _T_2632 = eq(_T_2631, UInt<1>(0h0)) node _T_2633 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2634 = or(_T_2632, _T_2633) node _T_2635 = lt(watchdog_1, plusarg_reader_1.out) node _T_2636 = or(_T_2634, _T_2635) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2640 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2641 = and(io.in.d.ready, io.in.d.valid) node _T_2642 = or(_T_2640, _T_2641) when _T_2642 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_89 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [78:0] inflight; // @[Monitor.scala:614:27] reg [315:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [631:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [78:0] inflight_1; // @[Monitor.scala:726:35] reg [631:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_104 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, flip out_credit_available : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} inst input_buffer of InputBuffer_104 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) inst route_arbiter of Arbiter5_RouteComputerReq_32 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h11)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id connect route_arbiter.io.in[4].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[4].bits.flow.egress_node_id invalidate route_arbiter.io.in[4].bits.flow.egress_node invalidate route_arbiter.io.in[4].bits.flow.ingress_node_id invalidate route_arbiter.io.in[4].bits.flow.ingress_node invalidate route_arbiter.io.in[4].bits.flow.vnet_id invalidate route_arbiter.io.in[4].bits.src_virt_id node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}[5] wire vcalloc_vals : UInt<1>[5] node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0)) node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23) node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_20 = and(io.router_req.ready, io.router_req.valid) when _T_20 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_22 = or(_T_21, vcalloc_vals[2]) node _T_23 = or(_T_22, vcalloc_vals[3]) node _T_24 = or(_T_23, vcalloc_vals[4]) when _T_24 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = bits(vcalloc_sel, 0, 0) node _mask_T_9 = bits(vcalloc_sel, 1, 1) node _mask_T_10 = bits(vcalloc_sel, 2, 2) node _mask_T_11 = bits(vcalloc_sel, 3, 3) node _mask_T_12 = bits(vcalloc_sel, 4, 4) node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0)) node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0)) node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0)) node _mask_T_18 = or(_mask_T_13, _mask_T_14) node _mask_T_19 = or(_mask_T_18, _mask_T_15) node _mask_T_20 = or(_mask_T_19, _mask_T_16) node _mask_T_21 = or(_mask_T_20, _mask_T_17) wire _mask_WIRE : UInt<5> connect _mask_WIRE, _mask_T_21 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}} wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5] node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[5] node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_76 connect _io_vcalloc_req_bits_WIRE_8[2], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_8[3], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_94 connect _io_vcalloc_req_bits_WIRE_8[4], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_14 : UInt<3> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_103 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_15 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_15.egress_node_id, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117) wire _io_vcalloc_req_bits_WIRE_17 : UInt<5> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_121 connect _io_vcalloc_req_bits_WIRE_15.egress_node, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123) node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124) node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_130 connect _io_vcalloc_req_bits_WIRE_15.ingress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_131, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_19 : UInt<5> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_139 connect _io_vcalloc_req_bits_WIRE_15.ingress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_143) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_144) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_15.vnet_id, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_15 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].flow, states[1].flow node _T_25 = bits(vcalloc_sel, 1, 1) node _T_26 = and(vcalloc_vals[1], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[1].g, UInt<3>(0h3) connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id connect vcalloc_vals[4], UInt<1>(0h0) invalidate vcalloc_reqs[4].vc_sel.`0`[0] invalidate vcalloc_reqs[4].vc_sel.`0`[1] invalidate vcalloc_reqs[4].vc_sel.`0`[2] invalidate vcalloc_reqs[4].vc_sel.`0`[3] invalidate vcalloc_reqs[4].vc_sel.`0`[4] invalidate vcalloc_reqs[4].vc_sel.`1`[0] invalidate vcalloc_reqs[4].vc_sel.`1`[1] invalidate vcalloc_reqs[4].vc_sel.`1`[2] invalidate vcalloc_reqs[4].vc_sel.`1`[3] invalidate vcalloc_reqs[4].vc_sel.`1`[4] invalidate vcalloc_reqs[4].in_vc invalidate vcalloc_reqs[4].flow.egress_node_id invalidate vcalloc_reqs[4].flow.egress_node invalidate vcalloc_reqs[4].flow.ingress_node_id invalidate vcalloc_reqs[4].flow.ingress_node invalidate vcalloc_reqs[4].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready) node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1) connect io.debug.va_stall, _io_debug_va_stall_T_9 node _T_28 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_28 : node _T_29 = bits(vcalloc_sel, 0, 0) when _T_29 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].g, UInt<3>(0h3) node _T_30 = eq(states[0].g, UInt<3>(0h2)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].g, UInt<3>(0h3) node _T_35 = eq(states[1].g, UInt<3>(0h2)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_35, UInt<1>(0h1), "") : assert_4 node _T_39 = bits(vcalloc_sel, 2, 2) when _T_39 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].g, UInt<3>(0h3) node _T_40 = eq(states[2].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = bits(vcalloc_sel, 3, 3) when _T_44 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].g, UInt<3>(0h3) node _T_45 = eq(states[3].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_45, UInt<1>(0h1), "") : assert_6 node _T_49 = bits(vcalloc_sel, 4, 4) when _T_49 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].g, UInt<3>(0h3) node _T_50 = eq(states[4].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_50, UInt<1>(0h1), "") : assert_7 inst salloc_arb of SwitchArbiter_267 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] node credit_available_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[4], states[1].vc_sel.`0`[3]) node credit_available_hi = cat(credit_available_hi_hi, states[1].vc_sel.`0`[2]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[4], states[1].vc_sel.`1`[3]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[1].vc_sel.`1`[2]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_2 = cat(_credit_available_T_1, _credit_available_T) node credit_available_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_hi_hi_2 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, io.out_credit_available.`0`[2]) node _credit_available_T_3 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_3 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`1`[2]) node _credit_available_T_4 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_5 = cat(_credit_available_T_4, _credit_available_T_3) node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5) node credit_available = neq(_credit_available_T_6, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_54 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_55 = and(_T_54, input_buffer.io.deq[1].bits.tail) when _T_55 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] connect salloc_arb.io.in[4].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[4].bits.tail invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[4] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_17 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7) node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14 node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_16 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _vc_sel_WIRE : UInt<1>[5] node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6) node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_13 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_22 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25) node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26) node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_31 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34) node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_40 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_49 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_6 : UInt<1>[5] node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_58 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_67 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70) node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71) node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_76 connect _vc_sel_WIRE_6[2], _vc_sel_WIRE_9 node _vc_sel_T_77 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_78 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_79 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_80 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_81 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_82 = or(_vc_sel_T_77, _vc_sel_T_78) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_79) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_80) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_81) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_85 connect _vc_sel_WIRE_6[3], _vc_sel_WIRE_10 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_88) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_89) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_90) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_94 connect _vc_sel_WIRE_6[4], _vc_sel_WIRE_11 connect vc_sel.`1`, _vc_sel_WIRE_6 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_3 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`1`[2]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`1`[3]) node channel_oh_1 = or(_channel_oh_T_5, vc_sel.`1`[4]) node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_3 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, vc_sel.`1`[2]) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 4, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node _virt_channel_T_16 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_18 = or(_virt_channel_T_16, _virt_channel_T_17) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_18 node _T_56 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_56 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6) node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6) node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6) node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[1], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].g invalidate states[4].fifo_deps invalidate states[4].flow.egress_node_id invalidate states[4].flow.egress_node invalidate states[4].flow.ingress_node_id invalidate states[4].flow.ingress_node invalidate states[4].flow.vnet_id invalidate states[4].vc_sel.`0`[0] invalidate states[4].vc_sel.`0`[1] invalidate states[4].vc_sel.`0`[2] invalidate states[4].vc_sel.`0`[3] invalidate states[4].vc_sel.`0`[4] invalidate states[4].vc_sel.`1`[0] invalidate states[4].vc_sel.`1`[1] invalidate states[4].vc_sel.`1`[2] invalidate states[4].vc_sel.`1`[3] invalidate states[4].vc_sel.`1`[4] invalidate states[4].g node _T_57 = asUInt(reset) when _T_57 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0)	module InputUnit_104( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {3'h0, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {3'h0, vcalloc_vals_1, 6'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] \| vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_1; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_64 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_129 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_130 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_31 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_31 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_31 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h14)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_10 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_11 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_12 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_13 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_14 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_15 : connect states[7].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) node _T_35 = or(_T_34, vcalloc_vals[6]) node _T_36 = or(_T_35, vcalloc_vals[7]) when _T_36 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_38 : UInt<3> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38 wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<2> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<5> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<2> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<5> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<3> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[3] invalidate vcalloc_reqs[0].vc_sel.`3`[4] invalidate vcalloc_reqs[0].vc_sel.`3`[5] invalidate vcalloc_reqs[0].vc_sel.`3`[6] invalidate vcalloc_reqs[0].vc_sel.`3`[7] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_37 = bits(vcalloc_sel, 1, 1) node _T_38 = and(vcalloc_vals[1], _T_37) node _T_39 = and(_T_38, io.vcalloc_req.ready) when _T_39 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].flow, states[2].flow node _T_40 = bits(vcalloc_sel, 2, 2) node _T_41 = and(vcalloc_vals[2], _T_40) node _T_42 = and(_T_41, io.vcalloc_req.ready) when _T_42 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_43 = bits(vcalloc_sel, 3, 3) node _T_44 = and(vcalloc_vals[3], _T_43) node _T_45 = and(_T_44, io.vcalloc_req.ready) when _T_45 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_46 = bits(vcalloc_sel, 4, 4) node _T_47 = and(vcalloc_vals[4], _T_46) node _T_48 = and(_T_47, io.vcalloc_req.ready) when _T_48 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_49 = bits(vcalloc_sel, 5, 5) node _T_50 = and(vcalloc_vals[5], _T_49) node _T_51 = and(_T_50, io.vcalloc_req.ready) when _T_51 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].flow, states[6].flow node _T_52 = bits(vcalloc_sel, 6, 6) node _T_53 = and(vcalloc_vals[6], _T_52) node _T_54 = and(_T_53, io.vcalloc_req.ready) when _T_54 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].flow, states[7].flow node _T_55 = bits(vcalloc_sel, 7, 7) node _T_56 = and(vcalloc_vals[7], _T_55) node _T_57 = and(_T_56, io.vcalloc_req.ready) when _T_57 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_58 : node _T_59 = bits(vcalloc_sel, 0, 0) when _T_59 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_60 = eq(states[0].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_60, UInt<1>(0h1), "") : assert_3 node _T_64 = bits(vcalloc_sel, 1, 1) when _T_64 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_65 = eq(states[1].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_65, UInt<1>(0h1), "") : assert_4 node _T_69 = bits(vcalloc_sel, 2, 2) when _T_69 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_70 = eq(states[2].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _T_74 = bits(vcalloc_sel, 3, 3) when _T_74 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_75 = eq(states[3].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_75, UInt<1>(0h1), "") : assert_6 node _T_79 = bits(vcalloc_sel, 4, 4) when _T_79 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_80 = eq(states[4].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_80, UInt<1>(0h1), "") : assert_7 node _T_84 = bits(vcalloc_sel, 5, 5) when _T_84 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_85 = eq(states[5].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_85, UInt<1>(0h1), "") : assert_8 node _T_89 = bits(vcalloc_sel, 6, 6) when _T_89 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].g, UInt<3>(0h3) node _T_90 = eq(states[6].g, UInt<3>(0h2)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = bits(vcalloc_sel, 7, 7) when _T_94 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].g, UInt<3>(0h3) node _T_95 = eq(states[7].g, UInt<3>(0h2)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_95, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_92 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[7] node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5) node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail) when _T_100 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_8 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_8 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_8 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_lo_9 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_9 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_9 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11) node credit_available_lo_lo_10 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_10 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_10 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_11 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_11 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11) node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail) when _T_102 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_16 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_16 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_16 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_17 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_17 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_17 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_18 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_18 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_18 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_lo_19 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_19 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_19 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23) node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27) node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31) node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail) when _T_104 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_24 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_24 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_25 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_25 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_26 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_26 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_27 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_27 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33) node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35) node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35) node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38) node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42) node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail) when _T_106 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_32 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_32 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_32 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_lo_33 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_33 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_33 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_34 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_34 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_34 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_35 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_35 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_35 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44) node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47) node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49) node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53) node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail) when _T_108 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_40 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_40 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_41 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_41 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_42 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_42 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42) node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_lo_43 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_43 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43) node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57) node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44) node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45) node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46) node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47) node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60) node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62) node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64) node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail) when _T_110 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_48 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_48 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48) node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_49 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_49 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49) node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_50 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_50 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50) node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_51 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_51 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51) node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66) node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68) node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52) node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53) node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54) node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55) node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73) node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69) node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75) node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail) when _T_112 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34) node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_38 node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_113 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`3`[3] invalidate states[0].vc_sel.`3`[4] invalidate states[0].vc_sel.`3`[5] invalidate states[0].vc_sel.`3`[6] invalidate states[0].vc_sel.`3`[7] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[3], UInt<1>(0h0) connect states[1].vc_sel.`3`[4], UInt<1>(0h0) connect states[1].vc_sel.`3`[5], UInt<1>(0h0) connect states[1].vc_sel.`3`[6], UInt<1>(0h0) connect states[1].vc_sel.`3`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[3], UInt<1>(0h0) connect states[2].vc_sel.`3`[4], UInt<1>(0h0) connect states[2].vc_sel.`3`[5], UInt<1>(0h0) connect states[2].vc_sel.`3`[6], UInt<1>(0h0) connect states[2].vc_sel.`3`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[1], UInt<1>(0h0) connect states[3].vc_sel.`3`[2], UInt<1>(0h0) connect states[3].vc_sel.`3`[3], UInt<1>(0h0) connect states[3].vc_sel.`3`[4], UInt<1>(0h0) connect states[3].vc_sel.`3`[5], UInt<1>(0h0) connect states[3].vc_sel.`3`[6], UInt<1>(0h0) connect states[3].vc_sel.`3`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[1], UInt<1>(0h0) connect states[4].vc_sel.`3`[2], UInt<1>(0h0) connect states[4].vc_sel.`3`[3], UInt<1>(0h0) connect states[4].vc_sel.`3`[4], UInt<1>(0h0) connect states[4].vc_sel.`3`[5], UInt<1>(0h0) connect states[4].vc_sel.`3`[6], UInt<1>(0h0) connect states[4].vc_sel.`3`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[1], UInt<1>(0h0) connect states[5].vc_sel.`3`[2], UInt<1>(0h0) connect states[5].vc_sel.`3`[3], UInt<1>(0h0) connect states[5].vc_sel.`3`[4], UInt<1>(0h0) connect states[5].vc_sel.`3`[5], UInt<1>(0h0) connect states[5].vc_sel.`3`[6], UInt<1>(0h0) connect states[5].vc_sel.`3`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[1], UInt<1>(0h0) connect states[6].vc_sel.`3`[2], UInt<1>(0h0) connect states[6].vc_sel.`3`[3], UInt<1>(0h0) connect states[6].vc_sel.`3`[4], UInt<1>(0h0) connect states[6].vc_sel.`3`[5], UInt<1>(0h0) connect states[6].vc_sel.`3`[6], UInt<1>(0h0) connect states[6].vc_sel.`3`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[1], UInt<1>(0h0) connect states[7].vc_sel.`3`[2], UInt<1>(0h0) connect states[7].vc_sel.`3`[3], UInt<1>(0h0) connect states[7].vc_sel.`3`[4], UInt<1>(0h0) connect states[7].vc_sel.`3`[5], UInt<1>(0h0) connect states[7].vc_sel.`3`[6], UInt<1>(0h0) connect states[7].vc_sel.`3`[7], UInt<1>(0h0) node _T_114 = asUInt(reset) when _T_114 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)	module InputUnit_31( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] \| vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 \| vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_6 \| vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_95 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_96 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_14 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg	module PE_14( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_199 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_455 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_199( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_455 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<10>(0h200))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<10>(0h200))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<10>(0h200))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<10>(0h200))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<10>(0h200))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<10>(0h200))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<10>(0h200))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<10>(0h200))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<10>(0h200))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<10>(0h200))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_121 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_122 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_200 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_200( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_190 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_350 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_190( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_350 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_15 : output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_7 node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51) node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0)) node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1) connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2 connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RecFNToRecFN_15( // @[RecFNToRecFN.scala:44:5] input [64:0] io_in, // @[RecFNToRecFN.scala:48:16] input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out, // @[RecFNToRecFN.scala:48:16] output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23] RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_7 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23] .io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23] .io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RecFNToRecFN.scala:72:19] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_T = eq(request.source, UInt<6>(0h24)) node _req_clientBit_T_1 = eq(request.source, UInt<6>(0h20)) node req_clientBit = cat(_req_clientBit_T_1, _req_clientBit_T) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_T = eq(io.sinkc.bits.source, UInt<6>(0h24)) node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<6>(0h20)) node probe_bit = cat(_probe_bit_T_1, _probe_bit_T) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_T = eq(new_request.source, UInt<6>(0h24)) node _new_clientBit_T_1 = eq(new_request.source, UInt<6>(0h20)) node new_clientBit = cat(_new_clientBit_T_1, _new_clientBit_T) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53] wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s2k3z4u_3 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a32d256s2k3z4u_3( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [1:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [1:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [1:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [31:0] saved_mask; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_8 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_16 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_8 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h2) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<2>(0h2) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h7), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_16 = eq(UInt<3>(0h6), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<3>(0h7), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(route_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_17 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_8 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_24 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_25 = and(vcalloc_q.io.enq.valid, _T_24) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_26, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_14, _out_bundle_bits_out_virt_channel_T_13) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_15 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_8( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_WIRE = {_route_buffer_io_enq_bits_flow_egress_node_id_T_3, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0) \| {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_2}}}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_WIRE == 4'h2; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_WIRE != 4'h2; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_107 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_107 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_107( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_107 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_414 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_158 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_414( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_158 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e5_s11_6 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e5_s11_6 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e5_s11_6 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<23>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<23>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11_12 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFNPipe_l2_e5_s11_6( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [16:0] io_a, // @[FPU.scala:638:16] input [16:0] io_b, // @[FPU.scala:638:16] input [16:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [16:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [16:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [16:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [16:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [16:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [21:0] _mulAddResult_T = {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [22:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [6:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [13:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 \| roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e5_s11_6 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e5_s11_6 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e5_s11_12 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_197 = shr(io.in.a.bits.source, 3) node _T_198 = eq(_T_197, UInt<3>(0h4)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_291 = shr(io.in.a.bits.source, 3) node _T_292 = eq(_T_291, UInt<3>(0h4)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_347 = shr(io.in.a.bits.source, 3) node _T_348 = eq(_T_347, UInt<3>(0h4)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_445 = shr(io.in.a.bits.source, 3) node _T_446 = eq(_T_445, UInt<3>(0h4)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_528 = shr(io.in.a.bits.source, 3) node _T_529 = eq(_T_528, UInt<3>(0h4)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_549 = and(_T_547, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_556) node _T_558 = and(_T_546, _T_557) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_558, UInt<1>(0h1), "") : assert_26 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(source_ok, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(is_aligned, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_568, UInt<1>(0h1), "") : assert_29 node _T_572 = eq(io.in.a.bits.mask, mask) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_572, UInt<1>(0h1), "") : assert_30 node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_576 : node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_35) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<1>(0h1)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_36) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_593 = shr(io.in.a.bits.source, 2) node _T_594 = eq(_T_593, UInt<2>(0h2)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_37) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_598 = and(_T_596, _T_597) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_599 = shr(io.in.a.bits.source, 2) node _T_600 = eq(_T_599, UInt<2>(0h3)) node _T_601 = leq(UInt<1>(0h0), uncommonBits_38) node _T_602 = and(_T_600, _T_601) node _T_603 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_604 = and(_T_602, _T_603) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_605 = shr(io.in.a.bits.source, 3) node _T_606 = eq(_T_605, UInt<3>(0h4)) node _T_607 = leq(UInt<1>(0h0), uncommonBits_39) node _T_608 = and(_T_606, _T_607) node _T_609 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_614 = or(_T_580, _T_586) node _T_615 = or(_T_614, _T_592) node _T_616 = or(_T_615, _T_598) node _T_617 = or(_T_616, _T_604) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_579, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = and(_T_627, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_635, UInt<1>(0h1), "") : assert_31 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(source_ok, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(is_aligned, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_645, UInt<1>(0h1), "") : assert_34 node _T_649 = not(mask) node _T_650 = and(io.in.a.bits.mask, _T_649) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_651, UInt<1>(0h1), "") : assert_35 node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_655 : node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_40) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h1)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_41) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h2)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_42) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h3)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_43) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_684 = shr(io.in.a.bits.source, 3) node _T_685 = eq(_T_684, UInt<3>(0h4)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_44) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_693 = or(_T_659, _T_665) node _T_694 = or(_T_693, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = and(_T_658, _T_700) node _T_702 = or(UInt<1>(0h0), _T_701) node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_705 = cvt(_T_704) node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000))) node _T_707 = asSInt(_T_706) node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0))) node _T_709 = and(_T_703, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = and(_T_702, _T_710) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_711, UInt<1>(0h1), "") : assert_36 node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(source_ok, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(is_aligned, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_721, UInt<1>(0h1), "") : assert_39 node _T_725 = eq(io.in.a.bits.mask, mask) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_725, UInt<1>(0h1), "") : assert_40 node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_729 : node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_45) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<1>(0h1)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_46) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<2>(0h2)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_47) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<2>(0h3)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_48) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_757 = and(_T_755, _T_756) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_758 = shr(io.in.a.bits.source, 3) node _T_759 = eq(_T_758, UInt<3>(0h4)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_49) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_763 = and(_T_761, _T_762) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_767 = or(_T_733, _T_739) node _T_768 = or(_T_767, _T_745) node _T_769 = or(_T_768, _T_751) node _T_770 = or(_T_769, _T_757) node _T_771 = or(_T_770, _T_763) node _T_772 = or(_T_771, _T_764) node _T_773 = or(_T_772, _T_765) node _T_774 = or(_T_773, _T_766) node _T_775 = and(_T_732, _T_774) node _T_776 = or(UInt<1>(0h0), _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_783) node _T_785 = and(_T_776, _T_784) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_785, UInt<1>(0h1), "") : assert_41 node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(source_ok, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(is_aligned, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_795, UInt<1>(0h1), "") : assert_44 node _T_799 = eq(io.in.a.bits.mask, mask) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_799, UInt<1>(0h1), "") : assert_45 node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_803 : node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_806 = and(_T_804, _T_805) node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<1>(0h0)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_50) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<1>(0h1)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_51) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<2>(0h2)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_52) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<2>(0h3)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_53) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_832 = shr(io.in.a.bits.source, 3) node _T_833 = eq(_T_832, UInt<3>(0h4)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_54) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_837 = and(_T_835, _T_836) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_841 = or(_T_807, _T_813) node _T_842 = or(_T_841, _T_819) node _T_843 = or(_T_842, _T_825) node _T_844 = or(_T_843, _T_831) node _T_845 = or(_T_844, _T_837) node _T_846 = or(_T_845, _T_838) node _T_847 = or(_T_846, _T_839) node _T_848 = or(_T_847, _T_840) node _T_849 = and(_T_806, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_852 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_853 = cvt(_T_852) node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000))) node _T_855 = asSInt(_T_854) node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0))) node _T_857 = and(_T_851, _T_856) node _T_858 = or(UInt<1>(0h0), _T_857) node _T_859 = and(_T_850, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_859, UInt<1>(0h1), "") : assert_46 node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(source_ok, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(is_aligned, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_869, UInt<1>(0h1), "") : assert_49 node _T_873 = eq(io.in.a.bits.mask, mask) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_873, UInt<1>(0h1), "") : assert_50 node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_877, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_881, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 3) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_885 : node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok_1, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_889, UInt<1>(0h1), "") : assert_54 node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_893, UInt<1>(0h1), "") : assert_55 node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_897, UInt<1>(0h1), "") : assert_56 node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_901, UInt<1>(0h1), "") : assert_57 node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_905 : node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok_1, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(sink_ok, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_912, UInt<1>(0h1), "") : assert_60 node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_916, UInt<1>(0h1), "") : assert_61 node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_920, UInt<1>(0h1), "") : assert_62 node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_924, UInt<1>(0h1), "") : assert_63 node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_929 = or(UInt<1>(0h0), _T_928) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_929, UInt<1>(0h1), "") : assert_64 node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_933 : node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(source_ok_1, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(sink_ok, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_940, UInt<1>(0h1), "") : assert_67 node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_944, UInt<1>(0h1), "") : assert_68 node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_948, UInt<1>(0h1), "") : assert_69 node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_953 = or(_T_952, io.in.d.bits.corrupt) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_953, UInt<1>(0h1), "") : assert_70 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = or(UInt<1>(0h0), _T_957) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_958, UInt<1>(0h1), "") : assert_71 node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_962 : node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(source_ok_1, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_966, UInt<1>(0h1), "") : assert_73 node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_970, UInt<1>(0h1), "") : assert_74 node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_975, UInt<1>(0h1), "") : assert_75 node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_979 : node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok_1, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_983, UInt<1>(0h1), "") : assert_77 node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_988 = or(_T_987, io.in.d.bits.corrupt) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_988, UInt<1>(0h1), "") : assert_78 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(UInt<1>(0h0), _T_992) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_993, UInt<1>(0h1), "") : assert_79 node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_997 : node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(source_ok_1, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81 node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82 node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1010 = or(UInt<1>(0h0), _T_1009) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1026 = eq(a_first, UInt<1>(0h0)) node _T_1027 = and(io.in.a.valid, _T_1026) when _T_1027 : node _T_1028 = eq(io.in.a.bits.opcode, opcode) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87 node _T_1032 = eq(io.in.a.bits.param, param) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88 node _T_1036 = eq(io.in.a.bits.size, size) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89 node _T_1040 = eq(io.in.a.bits.source, source) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90 node _T_1044 = eq(io.in.a.bits.address, address) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91 node _T_1048 = and(io.in.a.ready, io.in.a.valid) node _T_1049 = and(_T_1048, a_first) when _T_1049 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1050 = eq(d_first, UInt<1>(0h0)) node _T_1051 = and(io.in.d.valid, _T_1050) when _T_1051 : node _T_1052 = eq(io.in.d.bits.opcode, opcode_1) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92 node _T_1056 = eq(io.in.d.bits.param, param_1) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93 node _T_1060 = eq(io.in.d.bits.size, size_1) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94 node _T_1064 = eq(io.in.d.bits.source, source_1) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95 node _T_1068 = eq(io.in.d.bits.sink, sink) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96 node _T_1072 = eq(io.in.d.bits.denied, denied) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97 node _T_1076 = and(io.in.d.ready, io.in.d.valid) node _T_1077 = and(_T_1076, d_first) when _T_1077 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1078 = and(io.in.a.valid, a_first_1) node _T_1079 = and(_T_1078, UInt<1>(0h1)) when _T_1079 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1080 = and(io.in.a.ready, io.in.a.valid) node _T_1081 = and(_T_1080, a_first_1) node _T_1082 = and(_T_1081, UInt<1>(0h1)) when _T_1082 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1083 = dshr(inflight, io.in.a.bits.source) node _T_1084 = bits(_T_1083, 0, 0) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(_T_1085, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1089 = and(io.in.d.valid, d_first_1) node _T_1090 = and(_T_1089, UInt<1>(0h1)) node _T_1091 = eq(d_release_ack, UInt<1>(0h0)) node _T_1092 = and(_T_1090, _T_1091) when _T_1092 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1093 = and(io.in.d.ready, io.in.d.valid) node _T_1094 = and(_T_1093, d_first_1) node _T_1095 = and(_T_1094, UInt<1>(0h1)) node _T_1096 = eq(d_release_ack, UInt<1>(0h0)) node _T_1097 = and(_T_1095, _T_1096) when _T_1097 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1098 = and(io.in.d.valid, d_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) node _T_1100 = eq(d_release_ack, UInt<1>(0h0)) node _T_1101 = and(_T_1099, _T_1100) when _T_1101 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1102 = dshr(inflight, io.in.d.bits.source) node _T_1103 = bits(_T_1102, 0, 0) node _T_1104 = or(_T_1103, same_cycle_resp) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1110 = or(_T_1108, _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100 node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101 else : node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1120 = or(_T_1118, _T_1119) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102 node _T_1124 = eq(io.in.d.bits.size, a_size_lookup) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103 node _T_1128 = and(io.in.d.valid, d_first_1) node _T_1129 = and(_T_1128, a_first_1) node _T_1130 = and(_T_1129, io.in.a.valid) node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1132 = and(_T_1130, _T_1131) node _T_1133 = eq(d_release_ack, UInt<1>(0h0)) node _T_1134 = and(_T_1132, _T_1133) when _T_1134 : node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.a.ready) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_54 node _T_1140 = orr(inflight) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1143 = or(_T_1141, _T_1142) node _T_1144 = lt(watchdog, plusarg_reader.out) node _T_1145 = or(_T_1143, _T_1144) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(io.in.d.ready, io.in.d.valid) node _T_1151 = or(_T_1149, _T_1150) when _T_1151 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1152 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1153 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1154 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = and(_T_1152, _T_1155) when _T_1156 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1157 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1158 = and(_T_1157, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1159 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1160 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = and(_T_1158, _T_1161) when _T_1162 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1163 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1164 = bits(_T_1163, 0, 0) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1169 = and(io.in.d.valid, d_first_2) node _T_1170 = and(_T_1169, UInt<1>(0h1)) node _T_1171 = and(_T_1170, d_release_ack_1) when _T_1171 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1172 = and(io.in.d.ready, io.in.d.valid) node _T_1173 = and(_T_1172, d_first_2) node _T_1174 = and(_T_1173, UInt<1>(0h1)) node _T_1175 = and(_T_1174, d_release_ack_1) when _T_1175 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1176 = and(io.in.d.valid, d_first_2) node _T_1177 = and(_T_1176, UInt<1>(0h1)) node _T_1178 = and(_T_1177, d_release_ack_1) when _T_1178 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1179 = dshr(inflight_1, io.in.d.bits.source) node _T_1180 = bits(_T_1179, 0, 0) node _T_1181 = or(_T_1180, same_cycle_resp_1) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1185 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_108 else : node _T_1189 = eq(io.in.d.bits.size, c_size_lookup) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_109 node _T_1193 = and(io.in.d.valid, d_first_2) node _T_1194 = and(_T_1193, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1195 = and(_T_1194, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1196 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = and(_T_1197, d_release_ack_1) node _T_1199 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1202 = or(_T_1201, _WIRE_27.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_55 node _T_1206 = orr(inflight_1) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) node _T_1208 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1209 = or(_T_1207, _T_1208) node _T_1210 = lt(watchdog_1, plusarg_reader_1.out) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1215 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1216 = and(io.in.d.ready, io.in.d.valid) node _T_1217 = or(_T_1215, _T_1216) when _T_1217 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_99 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_99( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_76 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_76( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_155 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_172 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_155( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_172 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_5 : output auto : { flip rerocc_tile_ctrl_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rerocc_tile_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip rerocc_tile_re_ro_cc_in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, flip rerocc_tile_rerocc_manager_id_sink_in : UInt<7>, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst rerocc_tile of ReRoCCManagerTile_3 connect rerocc_tile.clock, childClock connect rerocc_tile.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect rerocc_tile.auto.rerocc_manager_id_sink_in, auto.rerocc_tile_rerocc_manager_id_sink_in connect rerocc_tile.auto.re_ro_cc_in, auto.rerocc_tile_re_ro_cc_in connect auto.rerocc_tile_buffer_out.e.bits, rerocc_tile.auto.buffer_out.e.bits connect auto.rerocc_tile_buffer_out.e.valid, rerocc_tile.auto.buffer_out.e.valid connect rerocc_tile.auto.buffer_out.e.ready, auto.rerocc_tile_buffer_out.e.ready connect rerocc_tile.auto.buffer_out.d, auto.rerocc_tile_buffer_out.d connect auto.rerocc_tile_buffer_out.c.bits, rerocc_tile.auto.buffer_out.c.bits connect auto.rerocc_tile_buffer_out.c.valid, rerocc_tile.auto.buffer_out.c.valid connect rerocc_tile.auto.buffer_out.c.ready, auto.rerocc_tile_buffer_out.c.ready connect rerocc_tile.auto.buffer_out.b, auto.rerocc_tile_buffer_out.b connect auto.rerocc_tile_buffer_out.a.bits, rerocc_tile.auto.buffer_out.a.bits connect auto.rerocc_tile_buffer_out.a.valid, rerocc_tile.auto.buffer_out.a.valid connect rerocc_tile.auto.buffer_out.a.ready, auto.rerocc_tile_buffer_out.a.ready connect rerocc_tile.auto.ctrl_ctrl_in, auto.rerocc_tile_ctrl_ctrl_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module ClockSinkDomain_5( // @[ClockDomain.scala:14:9] output auto_rerocc_tile_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_rerocc_tile_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_rerocc_tile_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire auto_rerocc_tile_ctrl_ctrl_in_a_valid_0 = auto_rerocc_tile_ctrl_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_ready_0 = auto_rerocc_tile_ctrl_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_ready_0 = auto_rerocc_tile_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_valid_0 = auto_rerocc_tile_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode_0 = auto_rerocc_tile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_b_bits_param_0 = auto_rerocc_tile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_b_bits_size_0 = auto_rerocc_tile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_source_0 = auto_rerocc_tile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_b_bits_address_0 = auto_rerocc_tile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_b_bits_mask_0 = auto_rerocc_tile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_b_bits_data_0 = auto_rerocc_tile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_corrupt_0 = auto_rerocc_tile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_ready_0 = auto_rerocc_tile_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_valid_0 = auto_rerocc_tile_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode_0 = auto_rerocc_tile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_d_bits_param_0 = auto_rerocc_tile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_d_bits_size_0 = auto_rerocc_tile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_source_0 = auto_rerocc_tile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_sink_0 = auto_rerocc_tile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_denied_0 = auto_rerocc_tile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_d_bits_data_0 = auto_rerocc_tile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_corrupt_0 = auto_rerocc_tile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_ready_0 = auto_rerocc_tile_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_valid_0 = auto_rerocc_tile_re_ro_cc_in_req_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_opcode; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_client_id; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_ready_0 = auto_rerocc_tile_re_ro_cc_in_resp_ready; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in_0 = auto_rerocc_tile_rerocc_manager_id_sink_in; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] ReRoCCManagerTile_3 rerocc_tile ( // @[Integration.scala:45:54] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrl_ctrl_in_a_ready (auto_rerocc_tile_ctrl_ctrl_in_a_ready_0), .auto_ctrl_ctrl_in_a_valid (auto_rerocc_tile_ctrl_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_param (auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_size (auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_source (auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_address (auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_mask (auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_data (auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_corrupt (auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_ready (auto_rerocc_tile_ctrl_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_valid (auto_rerocc_tile_ctrl_ctrl_in_d_valid_0), .auto_ctrl_ctrl_in_d_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0), .auto_ctrl_ctrl_in_d_bits_size (auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0), .auto_ctrl_ctrl_in_d_bits_source (auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0), .auto_ctrl_ctrl_in_d_bits_data (auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0), .auto_buffer_out_a_ready (auto_rerocc_tile_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_rerocc_tile_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_rerocc_tile_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_rerocc_tile_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_rerocc_tile_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_rerocc_tile_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_rerocc_tile_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_rerocc_tile_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_rerocc_tile_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_rerocc_tile_buffer_out_a_bits_corrupt_0), .auto_buffer_out_b_ready (auto_rerocc_tile_buffer_out_b_ready_0), .auto_buffer_out_b_valid (auto_rerocc_tile_buffer_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (auto_rerocc_tile_buffer_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (auto_rerocc_tile_buffer_out_b_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (auto_rerocc_tile_buffer_out_b_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (auto_rerocc_tile_buffer_out_b_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (auto_rerocc_tile_buffer_out_b_bits_address_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (auto_rerocc_tile_buffer_out_b_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (auto_rerocc_tile_buffer_out_b_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (auto_rerocc_tile_buffer_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (auto_rerocc_tile_buffer_out_c_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (auto_rerocc_tile_buffer_out_c_valid_0), .auto_buffer_out_c_bits_opcode (auto_rerocc_tile_buffer_out_c_bits_opcode_0), .auto_buffer_out_c_bits_param (auto_rerocc_tile_buffer_out_c_bits_param_0), .auto_buffer_out_c_bits_size (auto_rerocc_tile_buffer_out_c_bits_size_0), .auto_buffer_out_c_bits_source (auto_rerocc_tile_buffer_out_c_bits_source_0), .auto_buffer_out_c_bits_address (auto_rerocc_tile_buffer_out_c_bits_address_0), .auto_buffer_out_c_bits_data (auto_rerocc_tile_buffer_out_c_bits_data_0), .auto_buffer_out_c_bits_corrupt (auto_rerocc_tile_buffer_out_c_bits_corrupt_0), .auto_buffer_out_d_ready (auto_rerocc_tile_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_rerocc_tile_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_rerocc_tile_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (auto_rerocc_tile_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_rerocc_tile_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_rerocc_tile_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (auto_rerocc_tile_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (auto_rerocc_tile_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_rerocc_tile_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (auto_rerocc_tile_buffer_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (auto_rerocc_tile_buffer_out_e_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (auto_rerocc_tile_buffer_out_e_valid_0), .auto_buffer_out_e_bits_sink (auto_rerocc_tile_buffer_out_e_bits_sink_0), .auto_re_ro_cc_in_req_ready (auto_rerocc_tile_re_ro_cc_in_req_ready_0), .auto_re_ro_cc_in_req_valid (auto_rerocc_tile_re_ro_cc_in_req_valid_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_opcode (auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_client_id (auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_data (auto_rerocc_tile_re_ro_cc_in_req_bits_data_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_ready (auto_rerocc_tile_re_ro_cc_in_resp_ready_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_valid (auto_rerocc_tile_re_ro_cc_in_resp_valid_0), .auto_re_ro_cc_in_resp_bits_opcode (auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0), .auto_re_ro_cc_in_resp_bits_client_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0), .auto_re_ro_cc_in_resp_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0), .auto_re_ro_cc_in_resp_bits_data (auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0), .auto_rerocc_manager_id_sink_in (auto_rerocc_tile_rerocc_manager_id_sink_in_0) // @[ClockDomain.scala:14:9] ); // @[Integration.scala:45:54] assign auto_rerocc_tile_ctrl_ctrl_in_a_ready = auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_valid = auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode = auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_size = auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_source = auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_data = auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_valid = auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_opcode = auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_param = auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_size = auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_source = auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_address = auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_mask = auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_data = auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_corrupt = auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_b_ready = auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_valid = auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_opcode = auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_param = auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_size = auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_source = auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_address = auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_data = auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_corrupt = auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_d_ready = auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_valid = auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_bits_sink = auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_req_ready = auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_valid = auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode = auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_data = auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<14>(0h2000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<17>(0h10000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<18>(0h2f000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<27>(0h4000000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<13>(0h1000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<19>(0h40000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_144, _T_149) node _T_181 = or(_T_180, _T_154) node _T_182 = or(_T_181, _T_159) node _T_183 = or(_T_182, _T_164) node _T_184 = or(_T_183, _T_169) node _T_185 = or(_T_184, _T_174) node _T_186 = or(_T_185, _T_179) node _T_187 = and(_T_139, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_138, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_189, UInt<1>(0h1), "") : assert_2 node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_195 = and(_T_193, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<14>(0h2000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<13>(0h1000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<17>(0h10000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<18>(0h2f000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<17>(0h10000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<27>(0h4000000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<19>(0h40000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_201, _T_206) node _T_238 = or(_T_237, _T_211) node _T_239 = or(_T_238, _T_216) node _T_240 = or(_T_239, _T_221) node _T_241 = or(_T_240, _T_226) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_236) node _T_244 = and(_T_196, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = and(UInt<1>(0h0), _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_246, UInt<1>(0h1), "") : assert_3 node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(source_ok, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_253 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_253, UInt<1>(0h1), "") : assert_5 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(is_aligned, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_260 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_260, UInt<1>(0h1), "") : assert_7 node _T_264 = not(io.in.a.bits.mask) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_265, UInt<1>(0h1), "") : assert_8 node _T_269 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_269, UInt<1>(0h1), "") : assert_9 node _T_273 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h0)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_8) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h1)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_9) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h2)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_10) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h3)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_11) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_305 = or(_T_277, _T_283) node _T_306 = or(_T_305, _T_289) node _T_307 = or(_T_306, _T_295) node _T_308 = or(_T_307, _T_301) node _T_309 = or(_T_308, _T_302) node _T_310 = or(_T_309, _T_303) node _T_311 = or(_T_310, _T_304) node _T_312 = and(_T_276, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_315 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<14>(0h2000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<13>(0h1000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<17>(0h10000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<18>(0h2f000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<17>(0h10000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<27>(0h4000000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<19>(0h40000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = or(_T_319, _T_324) node _T_356 = or(_T_355, _T_329) node _T_357 = or(_T_356, _T_334) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_344) node _T_360 = or(_T_359, _T_349) node _T_361 = or(_T_360, _T_354) node _T_362 = and(_T_314, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = and(_T_313, _T_363) node _T_365 = asUInt(reset) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(_T_364, UInt<1>(0h0)) when _T_367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_364, UInt<1>(0h1), "") : assert_10 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<14>(0h2000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<13>(0h1000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<18>(0h2f000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<19>(0h40000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_376, _T_381) node _T_413 = or(_T_412, _T_386) node _T_414 = or(_T_413, _T_391) node _T_415 = or(_T_414, _T_396) node _T_416 = or(_T_415, _T_401) node _T_417 = or(_T_416, _T_406) node _T_418 = or(_T_417, _T_411) node _T_419 = and(_T_371, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = and(UInt<1>(0h0), _T_420) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_421, UInt<1>(0h1), "") : assert_11 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(source_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_428 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_428, UInt<1>(0h1), "") : assert_13 node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(is_aligned, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_435 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_435, UInt<1>(0h1), "") : assert_15 node _T_439 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_439, UInt<1>(0h1), "") : assert_16 node _T_443 = not(io.in.a.bits.mask) node _T_444 = eq(_T_443, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_444, UInt<1>(0h1), "") : assert_17 node _T_448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_448, UInt<1>(0h1), "") : assert_18 node _T_452 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_452 : node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<1>(0h0)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_12) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<1>(0h1)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_13) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_469 = shr(io.in.a.bits.source, 2) node _T_470 = eq(_T_469, UInt<2>(0h2)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_14) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_474 = and(_T_472, _T_473) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_475 = shr(io.in.a.bits.source, 2) node _T_476 = eq(_T_475, UInt<2>(0h3)) node _T_477 = leq(UInt<1>(0h0), uncommonBits_15) node _T_478 = and(_T_476, _T_477) node _T_479 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_484 = or(_T_456, _T_462) node _T_485 = or(_T_484, _T_468) node _T_486 = or(_T_485, _T_474) node _T_487 = or(_T_486, _T_480) node _T_488 = or(_T_487, _T_481) node _T_489 = or(_T_488, _T_482) node _T_490 = or(_T_489, _T_483) node _T_491 = and(_T_455, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_492, UInt<1>(0h1), "") : assert_19 node _T_496 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_497 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_498 = and(_T_496, _T_497) node _T_499 = or(UInt<1>(0h0), _T_498) node _T_500 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = and(_T_499, _T_504) node _T_506 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_507 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_508 = and(_T_506, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<14>(0h2000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<17>(0h10000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<18>(0h2f000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<17>(0h10000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_531 = cvt(_T_530) node _T_532 = and(_T_531, asSInt(UInt<27>(0h4000000))) node _T_533 = asSInt(_T_532) node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0))) node _T_535 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<13>(0h1000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<19>(0h40000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = or(_T_514, _T_519) node _T_546 = or(_T_545, _T_524) node _T_547 = or(_T_546, _T_529) node _T_548 = or(_T_547, _T_534) node _T_549 = or(_T_548, _T_539) node _T_550 = or(_T_549, _T_544) node _T_551 = and(_T_509, _T_550) node _T_552 = or(UInt<1>(0h0), _T_505) node _T_553 = or(_T_552, _T_551) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_553, UInt<1>(0h1), "") : assert_20 node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(source_ok, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(is_aligned, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_563 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_563, UInt<1>(0h1), "") : assert_23 node _T_567 = eq(io.in.a.bits.mask, mask) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_567, UInt<1>(0h1), "") : assert_24 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_571, UInt<1>(0h1), "") : assert_25 node _T_575 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h0)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_16) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h1)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_17) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h2)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_18) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h3)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_19) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_607 = or(_T_579, _T_585) node _T_608 = or(_T_607, _T_591) node _T_609 = or(_T_608, _T_597) node _T_610 = or(_T_609, _T_603) node _T_611 = or(_T_610, _T_604) node _T_612 = or(_T_611, _T_605) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_578, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<27>(0h4000000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<13>(0h1000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<19>(0h40000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_634, _T_639) node _T_661 = or(_T_660, _T_644) node _T_662 = or(_T_661, _T_649) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_659) node _T_665 = and(_T_629, _T_664) node _T_666 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_625) node _T_674 = or(_T_673, _T_665) node _T_675 = or(_T_674, _T_672) node _T_676 = and(_T_615, _T_675) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_676, UInt<1>(0h1), "") : assert_26 node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(source_ok, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(is_aligned, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_686 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_686, UInt<1>(0h1), "") : assert_29 node _T_690 = eq(io.in.a.bits.mask, mask) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_690, UInt<1>(0h1), "") : assert_30 node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_699 = shr(io.in.a.bits.source, 2) node _T_700 = eq(_T_699, UInt<1>(0h0)) node _T_701 = leq(UInt<1>(0h0), uncommonBits_20) node _T_702 = and(_T_700, _T_701) node _T_703 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_704 = and(_T_702, _T_703) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_705 = shr(io.in.a.bits.source, 2) node _T_706 = eq(_T_705, UInt<1>(0h1)) node _T_707 = leq(UInt<1>(0h0), uncommonBits_21) node _T_708 = and(_T_706, _T_707) node _T_709 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_710 = and(_T_708, _T_709) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_711 = shr(io.in.a.bits.source, 2) node _T_712 = eq(_T_711, UInt<2>(0h2)) node _T_713 = leq(UInt<1>(0h0), uncommonBits_22) node _T_714 = and(_T_712, _T_713) node _T_715 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_716 = and(_T_714, _T_715) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_717 = shr(io.in.a.bits.source, 2) node _T_718 = eq(_T_717, UInt<2>(0h3)) node _T_719 = leq(UInt<1>(0h0), uncommonBits_23) node _T_720 = and(_T_718, _T_719) node _T_721 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_722 = and(_T_720, _T_721) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_726 = or(_T_698, _T_704) node _T_727 = or(_T_726, _T_710) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = and(_T_697, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_736 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_737 = and(_T_735, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = and(_T_738, _T_743) node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<14>(0h2000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<18>(0h2f000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<27>(0h4000000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<13>(0h1000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<19>(0h40000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = or(_T_753, _T_758) node _T_780 = or(_T_779, _T_763) node _T_781 = or(_T_780, _T_768) node _T_782 = or(_T_781, _T_773) node _T_783 = or(_T_782, _T_778) node _T_784 = and(_T_748, _T_783) node _T_785 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_786 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = and(_T_785, _T_790) node _T_792 = or(UInt<1>(0h0), _T_744) node _T_793 = or(_T_792, _T_784) node _T_794 = or(_T_793, _T_791) node _T_795 = and(_T_734, _T_794) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_795, UInt<1>(0h1), "") : assert_31 node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(source_ok, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(is_aligned, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_805 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_805, UInt<1>(0h1), "") : assert_34 node _T_809 = not(mask) node _T_810 = and(io.in.a.bits.mask, _T_809) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_811, UInt<1>(0h1), "") : assert_35 node _T_815 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_815 : node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h0)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_24) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h1)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_25) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h2)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_26) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_838 = shr(io.in.a.bits.source, 2) node _T_839 = eq(_T_838, UInt<2>(0h3)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_27) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_819, _T_825) node _T_848 = or(_T_847, _T_831) node _T_849 = or(_T_848, _T_837) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = and(_T_818, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<15>(0h5000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<13>(0h1000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = or(_T_864, _T_869) node _T_871 = and(_T_859, _T_870) node _T_872 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<18>(0h2f000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<17>(0h10000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<27>(0h4000000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_899 = cvt(_T_898) node _T_900 = and(_T_899, asSInt(UInt<19>(0h40000))) node _T_901 = asSInt(_T_900) node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0))) node _T_903 = or(_T_877, _T_882) node _T_904 = or(_T_903, _T_887) node _T_905 = or(_T_904, _T_892) node _T_906 = or(_T_905, _T_897) node _T_907 = or(_T_906, _T_902) node _T_908 = and(_T_872, _T_907) node _T_909 = or(UInt<1>(0h0), _T_871) node _T_910 = or(_T_909, _T_908) node _T_911 = and(_T_855, _T_910) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_911, UInt<1>(0h1), "") : assert_36 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(source_ok, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(is_aligned, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_921 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_921, UInt<1>(0h1), "") : assert_39 node _T_925 = eq(io.in.a.bits.mask, mask) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_925, UInt<1>(0h1), "") : assert_40 node _T_929 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_929 : node _T_930 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_931 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_932 = and(_T_930, _T_931) node _T_933 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_934 = shr(io.in.a.bits.source, 2) node _T_935 = eq(_T_934, UInt<1>(0h0)) node _T_936 = leq(UInt<1>(0h0), uncommonBits_28) node _T_937 = and(_T_935, _T_936) node _T_938 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_939 = and(_T_937, _T_938) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<1>(0h1)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_29) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<2>(0h2)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_30) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<2>(0h3)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_31) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_961 = or(_T_933, _T_939) node _T_962 = or(_T_961, _T_945) node _T_963 = or(_T_962, _T_951) node _T_964 = or(_T_963, _T_957) node _T_965 = or(_T_964, _T_958) node _T_966 = or(_T_965, _T_959) node _T_967 = or(_T_966, _T_960) node _T_968 = and(_T_932, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_971 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_972 = and(_T_970, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_975 = cvt(_T_974) node _T_976 = and(_T_975, asSInt(UInt<15>(0h5000))) node _T_977 = asSInt(_T_976) node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0))) node _T_979 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<13>(0h1000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = or(_T_978, _T_983) node _T_985 = and(_T_973, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<13>(0h1000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<27>(0h4000000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<19>(0h40000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = or(_T_991, _T_996) node _T_1018 = or(_T_1017, _T_1001) node _T_1019 = or(_T_1018, _T_1006) node _T_1020 = or(_T_1019, _T_1011) node _T_1021 = or(_T_1020, _T_1016) node _T_1022 = and(_T_986, _T_1021) node _T_1023 = or(UInt<1>(0h0), _T_985) node _T_1024 = or(_T_1023, _T_1022) node _T_1025 = and(_T_969, _T_1024) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_41 node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(source_ok, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(is_aligned, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1035 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_44 node _T_1039 = eq(io.in.a.bits.mask, mask) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_45 node _T_1043 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1043 : node _T_1044 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1045 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1048 = shr(io.in.a.bits.source, 2) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) node _T_1050 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1053 = and(_T_1051, _T_1052) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<1>(0h1)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<2>(0h2)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1066 = shr(io.in.a.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<2>(0h3)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1075 = or(_T_1047, _T_1053) node _T_1076 = or(_T_1075, _T_1059) node _T_1077 = or(_T_1076, _T_1065) node _T_1078 = or(_T_1077, _T_1071) node _T_1079 = or(_T_1078, _T_1072) node _T_1080 = or(_T_1079, _T_1073) node _T_1081 = or(_T_1080, _T_1074) node _T_1082 = and(_T_1046, _T_1081) node _T_1083 = or(UInt<1>(0h0), _T_1082) node _T_1084 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1085 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = or(UInt<1>(0h0), _T_1086) node _T_1088 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1089 = cvt(_T_1088) node _T_1090 = and(_T_1089, asSInt(UInt<13>(0h1000))) node _T_1091 = asSInt(_T_1090) node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = and(_T_1087, _T_1092) node _T_1094 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1096 = cvt(_T_1095) node _T_1097 = and(_T_1096, asSInt(UInt<14>(0h2000))) node _T_1098 = asSInt(_T_1097) node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0))) node _T_1100 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1101 = cvt(_T_1100) node _T_1102 = and(_T_1101, asSInt(UInt<17>(0h10000))) node _T_1103 = asSInt(_T_1102) node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0))) node _T_1105 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1106 = cvt(_T_1105) node _T_1107 = and(_T_1106, asSInt(UInt<18>(0h2f000))) node _T_1108 = asSInt(_T_1107) node _T_1109 = eq(_T_1108, asSInt(UInt<1>(0h0))) node _T_1110 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1111 = cvt(_T_1110) node _T_1112 = and(_T_1111, asSInt(UInt<17>(0h10000))) node _T_1113 = asSInt(_T_1112) node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1116 = cvt(_T_1115) node _T_1117 = and(_T_1116, asSInt(UInt<27>(0h4000000))) node _T_1118 = asSInt(_T_1117) node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0))) node _T_1120 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1121 = cvt(_T_1120) node _T_1122 = and(_T_1121, asSInt(UInt<13>(0h1000))) node _T_1123 = asSInt(_T_1122) node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0))) node _T_1125 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<19>(0h40000))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1099, _T_1104) node _T_1131 = or(_T_1130, _T_1109) node _T_1132 = or(_T_1131, _T_1114) node _T_1133 = or(_T_1132, _T_1119) node _T_1134 = or(_T_1133, _T_1124) node _T_1135 = or(_T_1134, _T_1129) node _T_1136 = and(_T_1094, _T_1135) node _T_1137 = or(UInt<1>(0h0), _T_1093) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = and(_T_1083, _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_46 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(source_ok, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(is_aligned, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1149 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_49 node _T_1153 = eq(io.in.a.bits.mask, mask) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_50 node _T_1157 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1161 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1165 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1165 : node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok_1, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1169 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_54 node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_55 node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_56 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_57 node _T_1185 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1185 : node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(source_ok_1, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(sink_ok, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1192 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_60 node _T_1196 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_61 node _T_1200 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_62 node _T_1204 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_63 node _T_1208 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1209 = or(UInt<1>(0h1), _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_64 node _T_1213 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1213 : node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(source_ok_1, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(sink_ok, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1220 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_67 node _T_1224 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_68 node _T_1228 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_69 node _T_1232 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1233 = or(_T_1232, io.in.d.bits.corrupt) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_70 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_71 node _T_1242 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1242 : node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(source_ok_1, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1246 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_73 node _T_1250 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_74 node _T_1254 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1255 = or(UInt<1>(0h1), _T_1254) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_75 node _T_1259 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1259 : node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(source_ok_1, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1263 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_77 node _T_1267 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1268 = or(_T_1267, io.in.d.bits.corrupt) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_78 node _T_1272 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1273 = or(UInt<1>(0h1), _T_1272) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_79 node _T_1277 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1277 : node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(source_ok_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1281 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_81 node _T_1285 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_82 node _T_1289 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1290 = or(UInt<1>(0h1), _T_1289) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1294 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1298 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1302 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(_T_1302, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1302, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1306 = eq(a_first, UInt<1>(0h0)) node _T_1307 = and(io.in.a.valid, _T_1306) when _T_1307 : node _T_1308 = eq(io.in.a.bits.opcode, opcode) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_87 node _T_1312 = eq(io.in.a.bits.param, param) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_88 node _T_1316 = eq(io.in.a.bits.size, size) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_89 node _T_1320 = eq(io.in.a.bits.source, source) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_90 node _T_1324 = eq(io.in.a.bits.address, address) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_91 node _T_1328 = and(io.in.a.ready, io.in.a.valid) node _T_1329 = and(_T_1328, a_first) when _T_1329 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1330 = eq(d_first, UInt<1>(0h0)) node _T_1331 = and(io.in.d.valid, _T_1330) when _T_1331 : node _T_1332 = eq(io.in.d.bits.opcode, opcode_1) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92 node _T_1336 = eq(io.in.d.bits.param, param_1) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_93 node _T_1340 = eq(io.in.d.bits.size, size_1) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_94 node _T_1344 = eq(io.in.d.bits.source, source_1) node _T_1345 = asUInt(reset) node _T_1346 = eq(_T_1345, UInt<1>(0h0)) when _T_1346 : node _T_1347 = eq(_T_1344, UInt<1>(0h0)) when _T_1347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1344, UInt<1>(0h1), "") : assert_95 node _T_1348 = eq(io.in.d.bits.sink, sink) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_96 node _T_1352 = eq(io.in.d.bits.denied, denied) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_97 node _T_1356 = and(io.in.d.ready, io.in.d.valid) node _T_1357 = and(_T_1356, d_first) when _T_1357 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1358 = and(io.in.a.valid, a_first_1) node _T_1359 = and(_T_1358, UInt<1>(0h1)) when _T_1359 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1360 = and(io.in.a.ready, io.in.a.valid) node _T_1361 = and(_T_1360, a_first_1) node _T_1362 = and(_T_1361, UInt<1>(0h1)) when _T_1362 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1363 = dshr(inflight, io.in.a.bits.source) node _T_1364 = bits(_T_1363, 0, 0) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1369 = and(io.in.d.valid, d_first_1) node _T_1370 = and(_T_1369, UInt<1>(0h1)) node _T_1371 = eq(d_release_ack, UInt<1>(0h0)) node _T_1372 = and(_T_1370, _T_1371) when _T_1372 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1373 = and(io.in.d.ready, io.in.d.valid) node _T_1374 = and(_T_1373, d_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) node _T_1376 = eq(d_release_ack, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1378 = and(io.in.d.valid, d_first_1) node _T_1379 = and(_T_1378, UInt<1>(0h1)) node _T_1380 = eq(d_release_ack, UInt<1>(0h0)) node _T_1381 = and(_T_1379, _T_1380) when _T_1381 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1382 = dshr(inflight, io.in.d.bits.source) node _T_1383 = bits(_T_1382, 0, 0) node _T_1384 = or(_T_1383, same_cycle_resp) node _T_1385 = asUInt(reset) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(_T_1384, UInt<1>(0h0)) when _T_1387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1384, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1388 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1389 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1390 = or(_T_1388, _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_100 node _T_1394 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_101 else : node _T_1398 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1399 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_102 node _T_1404 = eq(io.in.d.bits.size, a_size_lookup) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_103 node _T_1408 = and(io.in.d.valid, d_first_1) node _T_1409 = and(_T_1408, a_first_1) node _T_1410 = and(_T_1409, io.in.a.valid) node _T_1411 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1412 = and(_T_1410, _T_1411) node _T_1413 = eq(d_release_ack, UInt<1>(0h0)) node _T_1414 = and(_T_1412, _T_1413) when _T_1414 : node _T_1415 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1416 = or(_T_1415, io.in.a.ready) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_36 node _T_1420 = orr(inflight) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) node _T_1422 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1423 = or(_T_1421, _T_1422) node _T_1424 = lt(watchdog, plusarg_reader.out) node _T_1425 = or(_T_1423, _T_1424) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1429 = and(io.in.a.ready, io.in.a.valid) node _T_1430 = and(io.in.d.ready, io.in.d.valid) node _T_1431 = or(_T_1429, _T_1430) when _T_1431 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1432 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1433 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1434 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1435 = and(_T_1433, _T_1434) node _T_1436 = and(_T_1432, _T_1435) when _T_1436 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1437 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1438 = and(_T_1437, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1439 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1440 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1441 = and(_T_1439, _T_1440) node _T_1442 = and(_T_1438, _T_1441) when _T_1442 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1443 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1444 = bits(_T_1443, 0, 0) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1449 = and(io.in.d.valid, d_first_2) node _T_1450 = and(_T_1449, UInt<1>(0h1)) node _T_1451 = and(_T_1450, d_release_ack_1) when _T_1451 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1452 = and(io.in.d.ready, io.in.d.valid) node _T_1453 = and(_T_1452, d_first_2) node _T_1454 = and(_T_1453, UInt<1>(0h1)) node _T_1455 = and(_T_1454, d_release_ack_1) when _T_1455 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1456 = and(io.in.d.valid, d_first_2) node _T_1457 = and(_T_1456, UInt<1>(0h1)) node _T_1458 = and(_T_1457, d_release_ack_1) when _T_1458 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1459 = dshr(inflight_1, io.in.d.bits.source) node _T_1460 = bits(_T_1459, 0, 0) node _T_1461 = or(_T_1460, same_cycle_resp_1) node _T_1462 = asUInt(reset) node _T_1463 = eq(_T_1462, UInt<1>(0h0)) when _T_1463 : node _T_1464 = eq(_T_1461, UInt<1>(0h0)) when _T_1464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1461, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1465 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1466 = asUInt(reset) node _T_1467 = eq(_T_1466, UInt<1>(0h0)) when _T_1467 : node _T_1468 = eq(_T_1465, UInt<1>(0h0)) when _T_1468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1465, UInt<1>(0h1), "") : assert_108 else : node _T_1469 = eq(io.in.d.bits.size, c_size_lookup) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_109 node _T_1473 = and(io.in.d.valid, d_first_2) node _T_1474 = and(_T_1473, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1475 = and(_T_1474, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1476 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1477 = and(_T_1475, _T_1476) node _T_1478 = and(_T_1477, d_release_ack_1) node _T_1479 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1480 = and(_T_1478, _T_1479) when _T_1480 : node _T_1481 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1482 = or(_T_1481, _WIRE_23.ready) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_37 node _T_1486 = orr(inflight_1) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) node _T_1488 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1489 = or(_T_1487, _T_1488) node _T_1490 = lt(watchdog_1, plusarg_reader_1.out) node _T_1491 = or(_T_1489, _T_1490) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1495 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1496 = and(io.in.d.ready, io.in.d.valid) node _T_1497 = or(_T_1495, _T_1496) when _T_1497 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1429 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1429; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1429; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1497 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1497; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1497; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1497; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1362 = _T_1429 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1362 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1362 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1362 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1362 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1362 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1408 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1408 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1377 = _T_1497 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1377 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1377 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1377 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1473 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1473 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1455 = _T_1497 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1455 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1455 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1455 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<13>(0h1000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = and(_T_381, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = and(_T_380, _T_388) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_389, UInt<1>(0h1), "") : assert_2 node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<1>(0h0)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_8) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h1)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_9) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<2>(0h2)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_10) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h3)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_11) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_393 connect _WIRE[1], _T_399 connect _WIRE[2], _T_405 connect _WIRE[3], _T_411 connect _WIRE[4], _T_417 connect _WIRE[5], _T_418 connect _WIRE[6], _T_419 connect _WIRE[7], _T_420 connect _WIRE[8], _T_421 connect _WIRE[9], _T_422 connect _WIRE[10], _T_423 connect _WIRE[11], _T_424 connect _WIRE[12], _T_425 connect _WIRE[13], _T_426 connect _WIRE[14], _T_427 connect _WIRE[15], _T_428 connect _WIRE[16], _T_429 connect _WIRE[17], _T_430 connect _WIRE[18], _T_431 connect _WIRE[19], _T_432 connect _WIRE[20], _T_433 connect _WIRE[21], _T_434 connect _WIRE[22], _T_435 connect _WIRE[23], _T_436 connect _WIRE[24], _T_437 connect _WIRE[25], _T_438 connect _WIRE[26], _T_439 connect _WIRE[27], _T_440 connect _WIRE[28], _T_441 connect _WIRE[29], _T_442 node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0)) node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0)) node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0)) node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0)) node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0)) node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0)) node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0)) node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0)) node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_481 = or(_T_451, _T_452) node _T_482 = or(_T_481, _T_453) node _T_483 = or(_T_482, _T_454) node _T_484 = or(_T_483, _T_455) node _T_485 = or(_T_484, _T_456) node _T_486 = or(_T_485, _T_457) node _T_487 = or(_T_486, _T_458) node _T_488 = or(_T_487, _T_459) node _T_489 = or(_T_488, _T_460) node _T_490 = or(_T_489, _T_461) node _T_491 = or(_T_490, _T_462) node _T_492 = or(_T_491, _T_463) node _T_493 = or(_T_492, _T_464) node _T_494 = or(_T_493, _T_465) node _T_495 = or(_T_494, _T_466) node _T_496 = or(_T_495, _T_467) node _T_497 = or(_T_496, _T_468) node _T_498 = or(_T_497, _T_469) node _T_499 = or(_T_498, _T_470) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_472) node _T_502 = or(_T_501, _T_473) node _T_503 = or(_T_502, _T_474) node _T_504 = or(_T_503, _T_475) node _T_505 = or(_T_504, _T_476) node _T_506 = or(_T_505, _T_477) node _T_507 = or(_T_506, _T_478) node _T_508 = or(_T_507, _T_479) node _T_509 = or(_T_508, _T_480) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_509 node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(UInt<1>(0h0), _T_512) node _T_514 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_WIRE_1, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_521, UInt<1>(0h1), "") : assert_3 node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(source_ok, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_528, UInt<1>(0h1), "") : assert_5 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(is_aligned, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_535, UInt<1>(0h1), "") : assert_7 node _T_539 = not(io.in.a.bits.mask) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_540, UInt<1>(0h1), "") : assert_8 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_544, UInt<1>(0h1), "") : assert_9 node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<1>(0h0)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_12) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<1>(0h1)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_13) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<2>(0h2)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_14) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<2>(0h3)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_15) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_602 = or(_T_552, _T_558) node _T_603 = or(_T_602, _T_564) node _T_604 = or(_T_603, _T_570) node _T_605 = or(_T_604, _T_576) node _T_606 = or(_T_605, _T_577) node _T_607 = or(_T_606, _T_578) node _T_608 = or(_T_607, _T_579) node _T_609 = or(_T_608, _T_580) node _T_610 = or(_T_609, _T_581) node _T_611 = or(_T_610, _T_582) node _T_612 = or(_T_611, _T_583) node _T_613 = or(_T_612, _T_584) node _T_614 = or(_T_613, _T_585) node _T_615 = or(_T_614, _T_586) node _T_616 = or(_T_615, _T_587) node _T_617 = or(_T_616, _T_588) node _T_618 = or(_T_617, _T_589) node _T_619 = or(_T_618, _T_590) node _T_620 = or(_T_619, _T_591) node _T_621 = or(_T_620, _T_592) node _T_622 = or(_T_621, _T_593) node _T_623 = or(_T_622, _T_594) node _T_624 = or(_T_623, _T_595) node _T_625 = or(_T_624, _T_596) node _T_626 = or(_T_625, _T_597) node _T_627 = or(_T_626, _T_598) node _T_628 = or(_T_627, _T_599) node _T_629 = or(_T_628, _T_600) node _T_630 = or(_T_629, _T_601) node _T_631 = and(_T_551, _T_630) node _T_632 = or(UInt<1>(0h0), _T_631) node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = and(_T_633, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = and(_T_632, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_641, UInt<1>(0h1), "") : assert_10 node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_646 = shr(io.in.a.bits.source, 2) node _T_647 = eq(_T_646, UInt<1>(0h0)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_16) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_652 = shr(io.in.a.bits.source, 2) node _T_653 = eq(_T_652, UInt<1>(0h1)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_17) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_658 = shr(io.in.a.bits.source, 2) node _T_659 = eq(_T_658, UInt<2>(0h2)) node _T_660 = leq(UInt<1>(0h0), uncommonBits_18) node _T_661 = and(_T_659, _T_660) node _T_662 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<2>(0h3)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_19) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_645 connect _WIRE_2[1], _T_651 connect _WIRE_2[2], _T_657 connect _WIRE_2[3], _T_663 connect _WIRE_2[4], _T_669 connect _WIRE_2[5], _T_670 connect _WIRE_2[6], _T_671 connect _WIRE_2[7], _T_672 connect _WIRE_2[8], _T_673 connect _WIRE_2[9], _T_674 connect _WIRE_2[10], _T_675 connect _WIRE_2[11], _T_676 connect _WIRE_2[12], _T_677 connect _WIRE_2[13], _T_678 connect _WIRE_2[14], _T_679 connect _WIRE_2[15], _T_680 connect _WIRE_2[16], _T_681 connect _WIRE_2[17], _T_682 connect _WIRE_2[18], _T_683 connect _WIRE_2[19], _T_684 connect _WIRE_2[20], _T_685 connect _WIRE_2[21], _T_686 connect _WIRE_2[22], _T_687 connect _WIRE_2[23], _T_688 connect _WIRE_2[24], _T_689 connect _WIRE_2[25], _T_690 connect _WIRE_2[26], _T_691 connect _WIRE_2[27], _T_692 connect _WIRE_2[28], _T_693 connect _WIRE_2[29], _T_694 node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0)) node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0)) node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0)) node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0)) node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0)) node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0)) node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0)) node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0)) node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_733 = or(_T_703, _T_704) node _T_734 = or(_T_733, _T_705) node _T_735 = or(_T_734, _T_706) node _T_736 = or(_T_735, _T_707) node _T_737 = or(_T_736, _T_708) node _T_738 = or(_T_737, _T_709) node _T_739 = or(_T_738, _T_710) node _T_740 = or(_T_739, _T_711) node _T_741 = or(_T_740, _T_712) node _T_742 = or(_T_741, _T_713) node _T_743 = or(_T_742, _T_714) node _T_744 = or(_T_743, _T_715) node _T_745 = or(_T_744, _T_716) node _T_746 = or(_T_745, _T_717) node _T_747 = or(_T_746, _T_718) node _T_748 = or(_T_747, _T_719) node _T_749 = or(_T_748, _T_720) node _T_750 = or(_T_749, _T_721) node _T_751 = or(_T_750, _T_722) node _T_752 = or(_T_751, _T_723) node _T_753 = or(_T_752, _T_724) node _T_754 = or(_T_753, _T_725) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_727) node _T_757 = or(_T_756, _T_728) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_730) node _T_760 = or(_T_759, _T_731) node _T_761 = or(_T_760, _T_732) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_761 node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_764 = and(_T_762, _T_763) node _T_765 = or(UInt<1>(0h0), _T_764) node _T_766 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_771) node _T_773 = and(_WIRE_3, _T_772) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_773, UInt<1>(0h1), "") : assert_11 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(source_ok, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_780, UInt<1>(0h1), "") : assert_13 node _T_784 = asUInt(reset) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(is_aligned, UInt<1>(0h0)) when _T_786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_787, UInt<1>(0h1), "") : assert_15 node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_791, UInt<1>(0h1), "") : assert_16 node _T_795 = not(io.in.a.bits.mask) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_796, UInt<1>(0h1), "") : assert_17 node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_800, UInt<1>(0h1), "") : assert_18 node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_20) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_21) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_22) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_23) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_858 = or(_T_808, _T_814) node _T_859 = or(_T_858, _T_820) node _T_860 = or(_T_859, _T_826) node _T_861 = or(_T_860, _T_832) node _T_862 = or(_T_861, _T_833) node _T_863 = or(_T_862, _T_834) node _T_864 = or(_T_863, _T_835) node _T_865 = or(_T_864, _T_836) node _T_866 = or(_T_865, _T_837) node _T_867 = or(_T_866, _T_838) node _T_868 = or(_T_867, _T_839) node _T_869 = or(_T_868, _T_840) node _T_870 = or(_T_869, _T_841) node _T_871 = or(_T_870, _T_842) node _T_872 = or(_T_871, _T_843) node _T_873 = or(_T_872, _T_844) node _T_874 = or(_T_873, _T_845) node _T_875 = or(_T_874, _T_846) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_848) node _T_878 = or(_T_877, _T_849) node _T_879 = or(_T_878, _T_850) node _T_880 = or(_T_879, _T_851) node _T_881 = or(_T_880, _T_852) node _T_882 = or(_T_881, _T_853) node _T_883 = or(_T_882, _T_854) node _T_884 = or(_T_883, _T_855) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = and(_T_807, _T_886) node _T_888 = or(UInt<1>(0h0), _T_887) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_888, UInt<1>(0h1), "") : assert_19 node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_893 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_894 = and(_T_892, _T_893) node _T_895 = or(UInt<1>(0h0), _T_894) node _T_896 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = and(_T_895, _T_900) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_902, UInt<1>(0h1), "") : assert_20 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(is_aligned, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_912, UInt<1>(0h1), "") : assert_23 node _T_916 = eq(io.in.a.bits.mask, mask) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_916, UInt<1>(0h1), "") : assert_24 node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_920, UInt<1>(0h1), "") : assert_25 node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_924 : node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_927 = and(_T_925, _T_926) node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_929 = shr(io.in.a.bits.source, 2) node _T_930 = eq(_T_929, UInt<1>(0h0)) node _T_931 = leq(UInt<1>(0h0), uncommonBits_24) node _T_932 = and(_T_930, _T_931) node _T_933 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_934 = and(_T_932, _T_933) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_935 = shr(io.in.a.bits.source, 2) node _T_936 = eq(_T_935, UInt<1>(0h1)) node _T_937 = leq(UInt<1>(0h0), uncommonBits_25) node _T_938 = and(_T_936, _T_937) node _T_939 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_940 = and(_T_938, _T_939) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_941 = shr(io.in.a.bits.source, 2) node _T_942 = eq(_T_941, UInt<2>(0h2)) node _T_943 = leq(UInt<1>(0h0), uncommonBits_26) node _T_944 = and(_T_942, _T_943) node _T_945 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_946 = and(_T_944, _T_945) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_947 = shr(io.in.a.bits.source, 2) node _T_948 = eq(_T_947, UInt<2>(0h3)) node _T_949 = leq(UInt<1>(0h0), uncommonBits_27) node _T_950 = and(_T_948, _T_949) node _T_951 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_952 = and(_T_950, _T_951) node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_978 = or(_T_928, _T_934) node _T_979 = or(_T_978, _T_940) node _T_980 = or(_T_979, _T_946) node _T_981 = or(_T_980, _T_952) node _T_982 = or(_T_981, _T_953) node _T_983 = or(_T_982, _T_954) node _T_984 = or(_T_983, _T_955) node _T_985 = or(_T_984, _T_956) node _T_986 = or(_T_985, _T_957) node _T_987 = or(_T_986, _T_958) node _T_988 = or(_T_987, _T_959) node _T_989 = or(_T_988, _T_960) node _T_990 = or(_T_989, _T_961) node _T_991 = or(_T_990, _T_962) node _T_992 = or(_T_991, _T_963) node _T_993 = or(_T_992, _T_964) node _T_994 = or(_T_993, _T_965) node _T_995 = or(_T_994, _T_966) node _T_996 = or(_T_995, _T_967) node _T_997 = or(_T_996, _T_968) node _T_998 = or(_T_997, _T_969) node _T_999 = or(_T_998, _T_970) node _T_1000 = or(_T_999, _T_971) node _T_1001 = or(_T_1000, _T_972) node _T_1002 = or(_T_1001, _T_973) node _T_1003 = or(_T_1002, _T_974) node _T_1004 = or(_T_1003, _T_975) node _T_1005 = or(_T_1004, _T_976) node _T_1006 = or(_T_1005, _T_977) node _T_1007 = and(_T_927, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1010 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = and(_T_1012, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = and(_T_1008, _T_1019) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_26 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(source_ok, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(is_aligned, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1030 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_29 node _T_1034 = eq(io.in.a.bits.mask, mask) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_30 node _T_1038 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1038 : node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1040 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1043 = shr(io.in.a.bits.source, 2) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1048 = and(_T_1046, _T_1047) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1049 = shr(io.in.a.bits.source, 2) node _T_1050 = eq(_T_1049, UInt<1>(0h1)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1055 = shr(io.in.a.bits.source, 2) node _T_1056 = eq(_T_1055, UInt<2>(0h2)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1061 = shr(io.in.a.bits.source, 2) node _T_1062 = eq(_T_1061, UInt<2>(0h3)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1092 = or(_T_1042, _T_1048) node _T_1093 = or(_T_1092, _T_1054) node _T_1094 = or(_T_1093, _T_1060) node _T_1095 = or(_T_1094, _T_1066) node _T_1096 = or(_T_1095, _T_1067) node _T_1097 = or(_T_1096, _T_1068) node _T_1098 = or(_T_1097, _T_1069) node _T_1099 = or(_T_1098, _T_1070) node _T_1100 = or(_T_1099, _T_1071) node _T_1101 = or(_T_1100, _T_1072) node _T_1102 = or(_T_1101, _T_1073) node _T_1103 = or(_T_1102, _T_1074) node _T_1104 = or(_T_1103, _T_1075) node _T_1105 = or(_T_1104, _T_1076) node _T_1106 = or(_T_1105, _T_1077) node _T_1107 = or(_T_1106, _T_1078) node _T_1108 = or(_T_1107, _T_1079) node _T_1109 = or(_T_1108, _T_1080) node _T_1110 = or(_T_1109, _T_1081) node _T_1111 = or(_T_1110, _T_1082) node _T_1112 = or(_T_1111, _T_1083) node _T_1113 = or(_T_1112, _T_1084) node _T_1114 = or(_T_1113, _T_1085) node _T_1115 = or(_T_1114, _T_1086) node _T_1116 = or(_T_1115, _T_1087) node _T_1117 = or(_T_1116, _T_1088) node _T_1118 = or(_T_1117, _T_1089) node _T_1119 = or(_T_1118, _T_1090) node _T_1120 = or(_T_1119, _T_1091) node _T_1121 = and(_T_1041, _T_1120) node _T_1122 = or(UInt<1>(0h0), _T_1121) node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = or(UInt<1>(0h0), _T_1125) node _T_1127 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = and(_T_1126, _T_1131) node _T_1133 = or(UInt<1>(0h0), _T_1132) node _T_1134 = and(_T_1122, _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_31 node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(source_ok, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(is_aligned, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1144 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_34 node _T_1148 = not(mask) node _T_1149 = and(io.in.a.bits.mask, _T_1148) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_35 node _T_1154 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1154 : node _T_1155 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1156 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1159 = shr(io.in.a.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1165 = shr(io.in.a.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1171 = shr(io.in.a.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1177 = shr(io.in.a.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1201 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1202 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1203 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1204 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1205 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1207 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1208 = or(_T_1158, _T_1164) node _T_1209 = or(_T_1208, _T_1170) node _T_1210 = or(_T_1209, _T_1176) node _T_1211 = or(_T_1210, _T_1182) node _T_1212 = or(_T_1211, _T_1183) node _T_1213 = or(_T_1212, _T_1184) node _T_1214 = or(_T_1213, _T_1185) node _T_1215 = or(_T_1214, _T_1186) node _T_1216 = or(_T_1215, _T_1187) node _T_1217 = or(_T_1216, _T_1188) node _T_1218 = or(_T_1217, _T_1189) node _T_1219 = or(_T_1218, _T_1190) node _T_1220 = or(_T_1219, _T_1191) node _T_1221 = or(_T_1220, _T_1192) node _T_1222 = or(_T_1221, _T_1193) node _T_1223 = or(_T_1222, _T_1194) node _T_1224 = or(_T_1223, _T_1195) node _T_1225 = or(_T_1224, _T_1196) node _T_1226 = or(_T_1225, _T_1197) node _T_1227 = or(_T_1226, _T_1198) node _T_1228 = or(_T_1227, _T_1199) node _T_1229 = or(_T_1228, _T_1200) node _T_1230 = or(_T_1229, _T_1201) node _T_1231 = or(_T_1230, _T_1202) node _T_1232 = or(_T_1231, _T_1203) node _T_1233 = or(_T_1232, _T_1204) node _T_1234 = or(_T_1233, _T_1205) node _T_1235 = or(_T_1234, _T_1206) node _T_1236 = or(_T_1235, _T_1207) node _T_1237 = and(_T_1157, _T_1236) node _T_1238 = or(UInt<1>(0h0), _T_1237) node _T_1239 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1240 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1241 = and(_T_1239, _T_1240) node _T_1242 = or(UInt<1>(0h0), _T_1241) node _T_1243 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<13>(0h1000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = and(_T_1242, _T_1247) node _T_1249 = or(UInt<1>(0h0), _T_1248) node _T_1250 = and(_T_1238, _T_1249) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_36 node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(source_ok, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(is_aligned, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1260 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_39 node _T_1264 = eq(io.in.a.bits.mask, mask) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_40 node _T_1268 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1268 : node _T_1269 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1270 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1271 = and(_T_1269, _T_1270) node _T_1272 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1273 = shr(io.in.a.bits.source, 2) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) node _T_1275 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1276 = and(_T_1274, _T_1275) node _T_1277 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1278 = and(_T_1276, _T_1277) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1279 = shr(io.in.a.bits.source, 2) node _T_1280 = eq(_T_1279, UInt<1>(0h1)) node _T_1281 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1284 = and(_T_1282, _T_1283) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1285 = shr(io.in.a.bits.source, 2) node _T_1286 = eq(_T_1285, UInt<2>(0h2)) node _T_1287 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1288 = and(_T_1286, _T_1287) node _T_1289 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1290 = and(_T_1288, _T_1289) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1291 = shr(io.in.a.bits.source, 2) node _T_1292 = eq(_T_1291, UInt<2>(0h3)) node _T_1293 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1294 = and(_T_1292, _T_1293) node _T_1295 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1312 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1313 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1315 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1316 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1317 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1318 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1319 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1320 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1321 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1322 = or(_T_1272, _T_1278) node _T_1323 = or(_T_1322, _T_1284) node _T_1324 = or(_T_1323, _T_1290) node _T_1325 = or(_T_1324, _T_1296) node _T_1326 = or(_T_1325, _T_1297) node _T_1327 = or(_T_1326, _T_1298) node _T_1328 = or(_T_1327, _T_1299) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1301) node _T_1331 = or(_T_1330, _T_1302) node _T_1332 = or(_T_1331, _T_1303) node _T_1333 = or(_T_1332, _T_1304) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1306) node _T_1336 = or(_T_1335, _T_1307) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1309) node _T_1339 = or(_T_1338, _T_1310) node _T_1340 = or(_T_1339, _T_1311) node _T_1341 = or(_T_1340, _T_1312) node _T_1342 = or(_T_1341, _T_1313) node _T_1343 = or(_T_1342, _T_1314) node _T_1344 = or(_T_1343, _T_1315) node _T_1345 = or(_T_1344, _T_1316) node _T_1346 = or(_T_1345, _T_1317) node _T_1347 = or(_T_1346, _T_1318) node _T_1348 = or(_T_1347, _T_1319) node _T_1349 = or(_T_1348, _T_1320) node _T_1350 = or(_T_1349, _T_1321) node _T_1351 = and(_T_1271, _T_1350) node _T_1352 = or(UInt<1>(0h0), _T_1351) node _T_1353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1354 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1355 = and(_T_1353, _T_1354) node _T_1356 = or(UInt<1>(0h0), _T_1355) node _T_1357 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1358 = cvt(_T_1357) node _T_1359 = and(_T_1358, asSInt(UInt<13>(0h1000))) node _T_1360 = asSInt(_T_1359) node _T_1361 = eq(_T_1360, asSInt(UInt<1>(0h0))) node _T_1362 = and(_T_1356, _T_1361) node _T_1363 = or(UInt<1>(0h0), _T_1362) node _T_1364 = and(_T_1352, _T_1363) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_41 node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(source_ok, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(is_aligned, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1374 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_44 node _T_1378 = eq(io.in.a.bits.mask, mask) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_45 node _T_1382 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1382 : node _T_1383 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1384 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1385 = and(_T_1383, _T_1384) node _T_1386 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1387 = shr(io.in.a.bits.source, 2) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1393 = shr(io.in.a.bits.source, 2) node _T_1394 = eq(_T_1393, UInt<1>(0h1)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1399 = shr(io.in.a.bits.source, 2) node _T_1400 = eq(_T_1399, UInt<2>(0h2)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1405 = shr(io.in.a.bits.source, 2) node _T_1406 = eq(_T_1405, UInt<2>(0h3)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1410 = and(_T_1408, _T_1409) node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1429 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1430 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1431 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1434 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1435 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1436 = or(_T_1386, _T_1392) node _T_1437 = or(_T_1436, _T_1398) node _T_1438 = or(_T_1437, _T_1404) node _T_1439 = or(_T_1438, _T_1410) node _T_1440 = or(_T_1439, _T_1411) node _T_1441 = or(_T_1440, _T_1412) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1414) node _T_1444 = or(_T_1443, _T_1415) node _T_1445 = or(_T_1444, _T_1416) node _T_1446 = or(_T_1445, _T_1417) node _T_1447 = or(_T_1446, _T_1418) node _T_1448 = or(_T_1447, _T_1419) node _T_1449 = or(_T_1448, _T_1420) node _T_1450 = or(_T_1449, _T_1421) node _T_1451 = or(_T_1450, _T_1422) node _T_1452 = or(_T_1451, _T_1423) node _T_1453 = or(_T_1452, _T_1424) node _T_1454 = or(_T_1453, _T_1425) node _T_1455 = or(_T_1454, _T_1426) node _T_1456 = or(_T_1455, _T_1427) node _T_1457 = or(_T_1456, _T_1428) node _T_1458 = or(_T_1457, _T_1429) node _T_1459 = or(_T_1458, _T_1430) node _T_1460 = or(_T_1459, _T_1431) node _T_1461 = or(_T_1460, _T_1432) node _T_1462 = or(_T_1461, _T_1433) node _T_1463 = or(_T_1462, _T_1434) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = and(_T_1385, _T_1464) node _T_1466 = or(UInt<1>(0h0), _T_1465) node _T_1467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = or(UInt<1>(0h0), _T_1469) node _T_1471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = and(_T_1470, _T_1475) node _T_1477 = or(UInt<1>(0h0), _T_1476) node _T_1478 = and(_T_1466, _T_1477) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_46 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(source_ok, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(is_aligned, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1488 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_49 node _T_1492 = eq(io.in.a.bits.mask, mask) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_50 node _T_1496 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(_T_1496, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1496, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1500 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1504 : node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok_1, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1508 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_54 node _T_1512 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_55 node _T_1516 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_56 node _T_1520 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_57 node _T_1524 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1524 : node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(source_ok_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(sink_ok, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1531 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(_T_1531, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1531, UInt<1>(0h1), "") : assert_60 node _T_1535 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_61 node _T_1539 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_62 node _T_1543 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_63 node _T_1547 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1548 = or(UInt<1>(0h1), _T_1547) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_64 node _T_1552 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1552 : node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(source_ok_1, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(sink_ok, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1559 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_67 node _T_1563 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_68 node _T_1567 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_69 node _T_1571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1572 = or(_T_1571, io.in.d.bits.corrupt) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_70 node _T_1576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1577 = or(UInt<1>(0h1), _T_1576) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_71 node _T_1581 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1581 : node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(source_ok_1, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_73 node _T_1589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_74 node _T_1593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1594 = or(UInt<1>(0h1), _T_1593) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_75 node _T_1598 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1598 : node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(source_ok_1, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1602 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(_T_1602, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1602, UInt<1>(0h1), "") : assert_77 node _T_1606 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1607 = or(_T_1606, io.in.d.bits.corrupt) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_78 node _T_1611 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1612 = or(UInt<1>(0h1), _T_1611) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_79 node _T_1616 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1616 : node _T_1617 = asUInt(reset) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) when _T_1618 : node _T_1619 = eq(source_ok_1, UInt<1>(0h0)) when _T_1619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1620 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(_T_1620, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1620, UInt<1>(0h1), "") : assert_81 node _T_1624 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(_T_1624, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1624, UInt<1>(0h1), "") : assert_82 node _T_1628 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1629 = or(UInt<1>(0h1), _T_1628) node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(_T_1629, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1629, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1633 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(_T_1633, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1633, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1637 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1641 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1642 = asUInt(reset) node _T_1643 = eq(_T_1642, UInt<1>(0h0)) when _T_1643 : node _T_1644 = eq(_T_1641, UInt<1>(0h0)) when _T_1644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1641, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1645 = eq(a_first, UInt<1>(0h0)) node _T_1646 = and(io.in.a.valid, _T_1645) when _T_1646 : node _T_1647 = eq(io.in.a.bits.opcode, opcode) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_87 node _T_1651 = eq(io.in.a.bits.param, param) node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(_T_1651, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1651, UInt<1>(0h1), "") : assert_88 node _T_1655 = eq(io.in.a.bits.size, size) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_89 node _T_1659 = eq(io.in.a.bits.source, source) node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(_T_1659, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1659, UInt<1>(0h1), "") : assert_90 node _T_1663 = eq(io.in.a.bits.address, address) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_91 node _T_1667 = and(io.in.a.ready, io.in.a.valid) node _T_1668 = and(_T_1667, a_first) when _T_1668 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1669 = eq(d_first, UInt<1>(0h0)) node _T_1670 = and(io.in.d.valid, _T_1669) when _T_1670 : node _T_1671 = eq(io.in.d.bits.opcode, opcode_1) node _T_1672 = asUInt(reset) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(_T_1671, UInt<1>(0h0)) when _T_1674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1671, UInt<1>(0h1), "") : assert_92 node _T_1675 = eq(io.in.d.bits.param, param_1) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_93 node _T_1679 = eq(io.in.d.bits.size, size_1) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_94 node _T_1683 = eq(io.in.d.bits.source, source_1) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_95 node _T_1687 = eq(io.in.d.bits.sink, sink) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_96 node _T_1691 = eq(io.in.d.bits.denied, denied) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_97 node _T_1695 = and(io.in.d.ready, io.in.d.valid) node _T_1696 = and(_T_1695, d_first) when _T_1696 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1697 = and(io.in.a.valid, a_first_1) node _T_1698 = and(_T_1697, UInt<1>(0h1)) when _T_1698 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first_1) node _T_1701 = and(_T_1700, UInt<1>(0h1)) when _T_1701 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1702 = dshr(inflight, io.in.a.bits.source) node _T_1703 = bits(_T_1702, 0, 0) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1708 = and(io.in.d.valid, d_first_1) node _T_1709 = and(_T_1708, UInt<1>(0h1)) node _T_1710 = eq(d_release_ack, UInt<1>(0h0)) node _T_1711 = and(_T_1709, _T_1710) when _T_1711 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1712 = and(io.in.d.ready, io.in.d.valid) node _T_1713 = and(_T_1712, d_first_1) node _T_1714 = and(_T_1713, UInt<1>(0h1)) node _T_1715 = eq(d_release_ack, UInt<1>(0h0)) node _T_1716 = and(_T_1714, _T_1715) when _T_1716 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1717 = and(io.in.d.valid, d_first_1) node _T_1718 = and(_T_1717, UInt<1>(0h1)) node _T_1719 = eq(d_release_ack, UInt<1>(0h0)) node _T_1720 = and(_T_1718, _T_1719) when _T_1720 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1721 = dshr(inflight, io.in.d.bits.source) node _T_1722 = bits(_T_1721, 0, 0) node _T_1723 = or(_T_1722, same_cycle_resp) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1727 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1728 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1729 = or(_T_1727, _T_1728) node _T_1730 = asUInt(reset) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) when _T_1731 : node _T_1732 = eq(_T_1729, UInt<1>(0h0)) when _T_1732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1729, UInt<1>(0h1), "") : assert_100 node _T_1733 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1734 = asUInt(reset) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) when _T_1735 : node _T_1736 = eq(_T_1733, UInt<1>(0h0)) when _T_1736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1733, UInt<1>(0h1), "") : assert_101 else : node _T_1737 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1738 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1739 = or(_T_1737, _T_1738) node _T_1740 = asUInt(reset) node _T_1741 = eq(_T_1740, UInt<1>(0h0)) when _T_1741 : node _T_1742 = eq(_T_1739, UInt<1>(0h0)) when _T_1742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1739, UInt<1>(0h1), "") : assert_102 node _T_1743 = eq(io.in.d.bits.size, a_size_lookup) node _T_1744 = asUInt(reset) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) when _T_1745 : node _T_1746 = eq(_T_1743, UInt<1>(0h0)) when _T_1746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1743, UInt<1>(0h1), "") : assert_103 node _T_1747 = and(io.in.d.valid, d_first_1) node _T_1748 = and(_T_1747, a_first_1) node _T_1749 = and(_T_1748, io.in.a.valid) node _T_1750 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1751 = and(_T_1749, _T_1750) node _T_1752 = eq(d_release_ack, UInt<1>(0h0)) node _T_1753 = and(_T_1751, _T_1752) when _T_1753 : node _T_1754 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1755 = or(_T_1754, io.in.a.ready) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_104 node _T_1759 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1760 = orr(a_set_wo_ready) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = or(_T_1759, _T_1761) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_42 node _T_1766 = orr(inflight) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) node _T_1768 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1769 = or(_T_1767, _T_1768) node _T_1770 = lt(watchdog, plusarg_reader.out) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1775 = and(io.in.a.ready, io.in.a.valid) node _T_1776 = and(io.in.d.ready, io.in.d.valid) node _T_1777 = or(_T_1775, _T_1776) when _T_1777 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1778 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1779 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1780 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1781 = and(_T_1779, _T_1780) node _T_1782 = and(_T_1778, _T_1781) when _T_1782 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1783 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1784 = and(_T_1783, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1785 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1786 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = and(_T_1784, _T_1787) when _T_1788 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1789 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1790 = bits(_T_1789, 0, 0) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1795 = and(io.in.d.valid, d_first_2) node _T_1796 = and(_T_1795, UInt<1>(0h1)) node _T_1797 = and(_T_1796, d_release_ack_1) when _T_1797 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1798 = and(io.in.d.ready, io.in.d.valid) node _T_1799 = and(_T_1798, d_first_2) node _T_1800 = and(_T_1799, UInt<1>(0h1)) node _T_1801 = and(_T_1800, d_release_ack_1) when _T_1801 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1802 = and(io.in.d.valid, d_first_2) node _T_1803 = and(_T_1802, UInt<1>(0h1)) node _T_1804 = and(_T_1803, d_release_ack_1) when _T_1804 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1805 = dshr(inflight_1, io.in.d.bits.source) node _T_1806 = bits(_T_1805, 0, 0) node _T_1807 = or(_T_1806, same_cycle_resp_1) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1811 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1812 = asUInt(reset) node _T_1813 = eq(_T_1812, UInt<1>(0h0)) when _T_1813 : node _T_1814 = eq(_T_1811, UInt<1>(0h0)) when _T_1814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1811, UInt<1>(0h1), "") : assert_109 else : node _T_1815 = eq(io.in.d.bits.size, c_size_lookup) node _T_1816 = asUInt(reset) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) when _T_1817 : node _T_1818 = eq(_T_1815, UInt<1>(0h0)) when _T_1818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1815, UInt<1>(0h1), "") : assert_110 node _T_1819 = and(io.in.d.valid, d_first_2) node _T_1820 = and(_T_1819, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1821 = and(_T_1820, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1822 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = and(_T_1823, d_release_ack_1) node _T_1825 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1826 = and(_T_1824, _T_1825) when _T_1826 : node _T_1827 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1828 = or(_T_1827, _WIRE_27.ready) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_111 node _T_1832 = orr(c_set_wo_ready) when _T_1832 : node _T_1833 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1834 = asUInt(reset) node _T_1835 = eq(_T_1834, UInt<1>(0h0)) when _T_1835 : node _T_1836 = eq(_T_1833, UInt<1>(0h0)) when _T_1836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1833, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_43 node _T_1837 = orr(inflight_1) node _T_1838 = eq(_T_1837, UInt<1>(0h0)) node _T_1839 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1840 = or(_T_1838, _T_1839) node _T_1841 = lt(watchdog_1, plusarg_reader_1.out) node _T_1842 = or(_T_1840, _T_1841) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1846 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1847 = and(io.in.d.ready, io.in.d.valid) node _T_1848 = or(_T_1846, _T_1847) when _T_1848 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 \| _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 \| _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 \| _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 \| _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 \| _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 \| _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 \| _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 \| _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 \| _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 \| _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 \| _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 \| _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 \| _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 \| _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 \| _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 \| _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1775 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1775; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1775; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1848 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1848; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1701 = _T_1775 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1701 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1701 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1701 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1701 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1701 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1747 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1747 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1716 = _T_1848 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1716 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1716 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1716 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1819 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1819 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1801 = _T_1848 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1801 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1801 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1801 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MSHR_80 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_80( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_38 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_38 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_38( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_38 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_75 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_75( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_69 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_69( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = \|_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 \| reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 \| _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_257 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_257( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_66 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_valid, slot_uop.iw_issued) when _T_40 : connect next_valid, rebusied	module IssueSlot_66( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module PE_206 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_206( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_54 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_54( // @[MulAddRecFN.scala:71:7] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [9:0] rawA_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawA_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [24:0] rawA_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawA_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [10:0] _sExpAlignedProd_T = 11'h12B; // @[MulAddRecFN.scala:100:19] wire [11:0] _sExpAlignedProd_T_1 = 12'h46; // @[MulAddRecFN.scala:100:32] wire [10:0] _sExpAlignedProd_T_2 = 11'h46; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = 11'h46; // @[MulAddRecFN.scala:100:32] wire [32:0] reduced4CExtra_shift = 33'h100000000; // @[primitives.scala:76:56] wire [3:0] _reduced4CExtra_T_4 = 4'h0; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = 4'h0; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_3 = 6'h0; // @[primitives.scala:77:20, :78:22] wire [5:0] _reduced4CExtra_T_18 = 6'h0; // @[primitives.scala:77:20, :78:22] wire [6:0] CAlignDist = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68] wire [11:0] _io_toPostMul_sExpSum_T = 12'h2E; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = 11'h2E; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = 11'h2E; // @[MulAddRecFN.scala:158:53] wire [4:0] io_toPostMul_CDom_CAlignDist = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47] wire [4:0] _reduced4CExtra_T_2 = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47] wire [4:0] _io_toPostMul_CDom_CAlignDist_T = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47] wire io_toPostMul_isZeroA = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawA_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawA_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawA_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawA_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _signProd_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _isMinCAlign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire isMinCAlign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _CIsDominant_T_2 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_isNaNAOrB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _reduced4CExtra_T_6 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_15 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = 1'h0; // @[primitives.scala:77:20] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_2 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_6 = 1'h0; // @[MulAddRecFN.scala:146:32] wire _io_toPostMul_isNaNAOrB_T = 1'h0; // @[MulAddRecFN.scala:148:42] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [23:0] io_mulAddA = 24'h0; // @[MulAddRecFN.scala:71:7, :74:16, :141:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawA_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawA_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_5 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_8 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_9 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_12 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_14 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_17 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _doSubMags_T = ~rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = 12'h46 - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] assign CIsDominant = _CIsDominant_T; // @[MulAddRecFN.scala:110:{9,23}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = _mainAlignedSigC_T_4; // @[MulAddRecFN.scala:120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:53:28, :55:23, :61:32] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : 11'h2E; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_2 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_2( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_1 : input clock : Clock input reset : Reset output auto : { } wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0]	module TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_1( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset // @[Xbar.scala:74:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_1 : output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}, last : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset output io : { gcd_busy : UInt<1>} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready connect clockNodeIn, auto.clock_in connect nodeIn, auto.in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset reg x : UInt<32>, clock wire y : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>} wire gcd : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>} wire status : UInt<2> inst impl_io_impl of GCDMMIOBlackBox connect impl_io_impl.clock, clock node _impl_impl_io_reset_T = asUInt(reset) connect impl_io_impl.reset, _impl_impl_io_reset_T connect impl_io_impl.x, x connect impl_io_impl.y, y.bits connect impl_io_impl.input_valid, y.valid connect y.ready, impl_io_impl.input_ready connect gcd.bits, impl_io_impl.gcd connect gcd.valid, impl_io_impl.output_valid connect impl_io_impl.output_ready, gcd.ready node _status_T = cat(impl_io_impl.input_ready, impl_io_impl.output_valid) connect status, _status_T connect io.gcd_busy, impl_io_impl.busy wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} wire ar_extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>} wire aw_extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>} node _in_valid_T = and(nodeIn.aw.valid, nodeIn.w.valid) node _in_valid_T_1 = or(nodeIn.ar.valid, _in_valid_T) connect in.valid, _in_valid_T_1 connect nodeIn.ar.ready, in.ready node _nodeIn_aw_ready_T = eq(nodeIn.ar.valid, UInt<1>(0h0)) node _nodeIn_aw_ready_T_1 = and(in.ready, _nodeIn_aw_ready_T) node _nodeIn_aw_ready_T_2 = and(_nodeIn_aw_ready_T_1, nodeIn.w.valid) connect nodeIn.aw.ready, _nodeIn_aw_ready_T_2 node _nodeIn_w_ready_T = eq(nodeIn.ar.valid, UInt<1>(0h0)) node _nodeIn_w_ready_T_1 = and(in.ready, _nodeIn_w_ready_T) node _nodeIn_w_ready_T_2 = and(_nodeIn_w_ready_T_1, nodeIn.aw.valid) connect nodeIn.w.ready, _nodeIn_w_ready_T_2 connect ar_extra.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect ar_extra.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect aw_extra.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect aw_extra.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect ar_extra.extra_id, nodeIn.ar.bits.id connect aw_extra.extra_id, nodeIn.aw.bits.id node addr = mux(nodeIn.ar.valid, nodeIn.ar.bits.addr, nodeIn.aw.bits.addr) node _mask_sizeOH_T = or(nodeIn.ar.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(nodeIn.ar.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(nodeIn.ar.bits.addr, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(nodeIn.ar.bits.addr, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(nodeIn.ar.bits.addr, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) connect in.bits.read, nodeIn.ar.valid node _in_bits_index_T = shr(addr, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.w.bits.data node _in_bits_mask_T = mux(nodeIn.ar.valid, mask, nodeIn.w.bits.strb) connect in.bits.mask, _in_bits_mask_T node _in_bits_extra_T = mux(nodeIn.ar.valid, ar_extra, aw_extra) connect in.bits.extra, _in_bits_extra_T wire out_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h1)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[4] wire out_wivalid : UInt<1>[4] wire out_roready : UInt<1>[4] wire out_woready : UInt<1>[4] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 1, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 1, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 1, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 1, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_4 = bits(out_front.bits.data, 1, 0) node _out_T_5 = eq(out_rimask, UInt<1>(0h0)) node _out_T_6 = eq(out_wimask, UInt<1>(0h0)) node _out_T_7 = eq(out_romask, UInt<1>(0h0)) node _out_T_8 = eq(out_womask, UInt<1>(0h0)) node _out_T_9 = or(status, UInt<2>(0h0)) node _out_T_10 = bits(_out_T_9, 1, 0) node _out_rimask_T_1 = bits(out_frontMask, 63, 32) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 63, 32) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 63, 32) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 63, 32) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_11 = bits(out_front.bits.data, 63, 32) when out_f_woready_1 : connect x, _out_T_11 node _out_T_12 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_14 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_15 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_10, UInt<32>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_16 = or(out_prepend, UInt<64>(0h0)) node _out_T_17 = bits(_out_T_16, 63, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_18 = bits(out_front.bits.data, 31, 0) connect y.valid, out_f_woready_2 connect y.bits, _out_T_18 node _out_T_19 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_21 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_22 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_23 = or(y.ready, _out_T_22) node _out_T_24 = or(UInt<1>(0h0), UInt<32>(0h0)) node _out_T_25 = bits(_out_T_24, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 63, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 63, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 63, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 63, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect gcd.ready, out_f_roready_3 node _out_T_26 = bits(out_front.bits.data, 63, 32) node _out_T_27 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_28 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_29 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_30 = or(gcd.valid, _out_T_29) node _out_T_31 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<32>(0h0)) node out_prepend_1 = cat(gcd.bits, _out_prepend_T_1) node _out_T_32 = or(out_prepend_1, UInt<64>(0h0)) node _out_T_33 = bits(_out_T_32, 63, 0) node out_iindex = bits(out_front.bits.index, 0, 0) node _out_iindex_T = bits(out_front.bits.index, 1, 1) node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_4 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_5 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_6 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_7 = bits(out_front.bits.index, 8, 8) node out_oindex = bits(out_front.bits.index, 0, 0) node _out_oindex_T = bits(out_front.bits.index, 1, 1) node _out_oindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_4 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_5 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_6 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_7 = bits(out_front.bits.index, 8, 8) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_7 connect out_rivalid[2], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) wire _out_rifireMux_WIRE : UInt<1>[2] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_8 connect out_wivalid[2], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) wire _out_wifireMux_WIRE : UInt<1>[2] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out_out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) node out_rofireMux_all = and(_out_rofireMux_T_7, _out_T_30) connect out_rofireMux_out_1, _out_T_30 connect out_roready[3], _out_rofireMux_T_7 connect out_roready[2], out_rofireMux_all node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) wire _out_rofireMux_WIRE : UInt<1>[2] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out_out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) node out_wofireMux_all = and(_out_wofireMux_T_8, _out_T_23) connect out_wofireMux_out_1, _out_T_23 connect out_woready[3], out_wofireMux_all connect out_woready[2], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) wire _out_wofireMux_WIRE : UInt<1>[2] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out_out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out_out.valid, _out_out_valid_T connect out_out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE : UInt<1>[2] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE_1 : UInt<64>[2] connect _out_out_bits_data_WIRE_1[0], _out_T_17 connect _out_out_bits_data_WIRE_1[1], _out_T_33 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out_out.bits.data, _out_out_bits_data_T_4 connect out_out.bits.extra, out_front.bits.extra inst out_deq_q of Queue2_RegMapperOutput connect out_deq_q.clock, clock connect out_deq_q.reset, reset connect out_deq_q.io.enq.valid, out_out.valid connect out_deq_q.io.enq.bits.extra.extra_id, out_out.bits.extra.extra_id connect out_deq_q.io.enq.bits.extra.tl_state.source, out_out.bits.extra.tl_state.source connect out_deq_q.io.enq.bits.extra.tl_state.size, out_out.bits.extra.tl_state.size connect out_deq_q.io.enq.bits.data, out_out.bits.data connect out_deq_q.io.enq.bits.read, out_out.bits.read connect out_out.ready, out_deq_q.io.enq.ready wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} connect out.bits, out_deq_q.io.deq.bits connect out.valid, out_deq_q.io.deq.valid connect out_deq_q.io.deq.ready, out.ready node _out_ready_T = mux(out.bits.read, nodeIn.r.ready, nodeIn.b.ready) connect out.ready, _out_ready_T node _nodeIn_r_valid_T = and(out.valid, out.bits.read) connect nodeIn.r.valid, _nodeIn_r_valid_T node _nodeIn_b_valid_T = eq(out.bits.read, UInt<1>(0h0)) node _nodeIn_b_valid_T_1 = and(out.valid, _nodeIn_b_valid_T) connect nodeIn.b.valid, _nodeIn_b_valid_T_1 connect nodeIn.r.bits.id, out.bits.extra.extra_id connect nodeIn.r.bits.data, out.bits.data connect nodeIn.r.bits.last, UInt<1>(0h1) connect nodeIn.r.bits.resp, UInt<2>(0h0) connect nodeIn.r.bits.echo.tl_state.source, out.bits.extra.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, out.bits.extra.tl_state.size connect nodeIn.b.bits.id, out.bits.extra.extra_id connect nodeIn.b.bits.resp, UInt<2>(0h0) connect nodeIn.b.bits.echo.tl_state.source, out.bits.extra.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, out.bits.extra.tl_state.size extmodule plusarg_reader_117 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_118 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module ClockSinkDomain_1( // @[GCD.scala:179:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [14:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [14:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] output io_gcd_busy // @[GCD.scala:180:16] ); wire out_front_ready; // @[RegisterRouter.scala:72:16] wire _out_wofireMux_T_2; // @[RegisterRouter.scala:72:16] wire _out_wofireMux_T; // @[RegisterRouter.scala:72:16] wire out_iindex; // @[RegisterRouter.scala:72:16] wire _out_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _out_deq_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _out_deq_q_io_deq_bits_read; // @[Decoupled.scala:362:21] wire [3:0] _out_deq_q_io_deq_bits_extra_tl_state_size; // @[Decoupled.scala:362:21] wire [10:0] _out_deq_q_io_deq_bits_extra_tl_state_source; // @[Decoupled.scala:362:21] wire _out_deq_q_io_deq_bits_extra_extra_id; // @[Decoupled.scala:362:21] wire _impl_io_impl_input_ready; // @[GCD.scala:189:26] wire _impl_io_impl_output_valid; // @[GCD.scala:189:26] wire [31:0] _impl_io_impl_gcd; // @[GCD.scala:189:26] reg [31:0] x; // @[GCD.scala:183:18] wire in_valid = auto_in_ar_valid \| auto_in_aw_valid & auto_in_w_valid; // @[RegisterRouter.scala:52:{26,39}] wire [8:0] addr = auto_in_ar_valid ? auto_in_ar_bits_addr[11:3] : auto_in_aw_bits_addr[11:3]; // @[RegisterRouter.scala:61:19] wire mask_sub_sub_sub_0_1 = auto_in_ar_bits_size > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = auto_in_ar_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| mask_sub_sub_size & ~(auto_in_ar_bits_addr[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| mask_sub_sub_size & auto_in_ar_bits_addr[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}] wire mask_sub_size = auto_in_ar_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49] wire mask_sub_0_2 = ~(auto_in_ar_bits_addr[2]) & ~(auto_in_ar_bits_addr[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire mask_sub_0_1 = mask_sub_sub_0_1 \| mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire mask_sub_1_2 = ~(auto_in_ar_bits_addr[2]) & auto_in_ar_bits_addr[1]; // @[Misc.scala:210:26, :211:20, :214:27] wire mask_sub_1_1 = mask_sub_sub_0_1 \| mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire mask_sub_2_2 = auto_in_ar_bits_addr[2] & ~(auto_in_ar_bits_addr[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire mask_sub_2_1 = mask_sub_sub_1_1 \| mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire mask_sub_3_2 = auto_in_ar_bits_addr[2] & auto_in_ar_bits_addr[1]; // @[Misc.scala:210:26, :214:27] wire mask_sub_3_1 = mask_sub_sub_1_1 \| mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire [7:0] in_bits_mask = auto_in_ar_valid ? {mask_sub_3_1 \| mask_sub_3_2 & auto_in_ar_bits_addr[0], mask_sub_3_1 \| mask_sub_3_2 & ~(auto_in_ar_bits_addr[0]), mask_sub_2_1 \| mask_sub_2_2 & auto_in_ar_bits_addr[0], mask_sub_2_1 \| mask_sub_2_2 & ~(auto_in_ar_bits_addr[0]), mask_sub_1_1 \| mask_sub_1_2 & auto_in_ar_bits_addr[0], mask_sub_1_1 \| mask_sub_1_2 & ~(auto_in_ar_bits_addr[0]), mask_sub_0_1 \| mask_sub_0_2 & auto_in_ar_bits_addr[0], mask_sub_0_1 \| mask_sub_0_2 & ~(auto_in_ar_bits_addr[0])} : auto_in_w_bits_strb; // @[Misc.scala:210:26, :211:20, :214:27, :215:29, :222:10] wire _out_T_3 = addr[8:1] == 8'h0; // @[RegisterRouter.scala:61:19, :72:16] wire [31:0] _out_womask_T_3 = {{8{in_bits_mask[7]}}, {8{in_bits_mask[6]}}, {8{in_bits_mask[5]}}, {8{in_bits_mask[4]}}}; // @[RegisterRouter.scala:67:25, :72:16] wire [31:0] _out_womask_T_2 = {{8{in_bits_mask[3]}}, {8{in_bits_mask[2]}}, {8{in_bits_mask[1]}}, {8{in_bits_mask[0]}}}; // @[RegisterRouter.scala:67:25, :72:16] assign out_iindex = addr[0]; // @[RegisterRouter.scala:61:19, :72:16] assign _out_wofireMux_T = in_valid & _out_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] assign _out_wofireMux_T_2 = _out_wofireMux_T & ~auto_in_ar_valid; // @[RegisterRouter.scala:72:16] wire out_oready = auto_in_ar_valid ? ~out_iindex \| (\|{_impl_io_impl_output_valid \| ~(\|_out_womask_T_3), addr[8:1]}) : ~out_iindex \| (\|{_impl_io_impl_input_ready \| ~(&_out_womask_T_2), addr[8:1]}); // @[MuxLiteral.scala:49:10] assign out_front_ready = _out_deq_q_io_enq_ready & out_oready; // @[Decoupled.scala:362:21] always @(posedge auto_clock_in_clock) begin // @[LazyModuleImp.scala:107:25] if (_out_wofireMux_T_2 & ~out_iindex & _out_T_3 & (&_out_womask_T_3)) // @[RegisterRouter.scala:72:16] x <= auto_in_w_bits_data[63:32]; // @[RegisterRouter.scala:72:16] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<13>(0h1000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = and(_T_139, _T_144) node _T_146 = or(UInt<1>(0h0), _T_145) node _T_147 = and(_T_138, _T_146) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_147, UInt<1>(0h1), "") : assert_2 node _T_151 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_152 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_153 = and(_T_151, _T_152) node _T_154 = or(UInt<1>(0h0), _T_153) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<13>(0h1000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = and(_T_154, _T_159) node _T_161 = or(UInt<1>(0h0), _T_160) node _T_162 = and(UInt<1>(0h0), _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_162, UInt<1>(0h1), "") : assert_3 node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(source_ok, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_169 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_169, UInt<1>(0h1), "") : assert_5 node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(is_aligned, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_176 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_176, UInt<1>(0h1), "") : assert_7 node _T_180 = not(io.in.a.bits.mask) node _T_181 = eq(_T_180, UInt<1>(0h0)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_181, UInt<1>(0h1), "") : assert_8 node _T_185 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_185, UInt<1>(0h1), "") : assert_9 node _T_189 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_189 : node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_194 = shr(io.in.a.bits.source, 2) node _T_195 = eq(_T_194, UInt<1>(0h0)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_8) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_199 = and(_T_197, _T_198) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_200 = shr(io.in.a.bits.source, 2) node _T_201 = eq(_T_200, UInt<1>(0h1)) node _T_202 = leq(UInt<1>(0h0), uncommonBits_9) node _T_203 = and(_T_201, _T_202) node _T_204 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_205 = and(_T_203, _T_204) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<2>(0h2)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_10) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<2>(0h3)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_11) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_220 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_221 = or(_T_193, _T_199) node _T_222 = or(_T_221, _T_205) node _T_223 = or(_T_222, _T_211) node _T_224 = or(_T_223, _T_217) node _T_225 = or(_T_224, _T_218) node _T_226 = or(_T_225, _T_219) node _T_227 = or(_T_226, _T_220) node _T_228 = and(_T_192, _T_227) node _T_229 = or(UInt<1>(0h0), _T_228) node _T_230 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = and(_T_230, _T_235) node _T_237 = or(UInt<1>(0h0), _T_236) node _T_238 = and(_T_229, _T_237) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_238, UInt<1>(0h1), "") : assert_10 node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(UInt<1>(0h0), _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_253, UInt<1>(0h1), "") : assert_11 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(source_ok, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_260 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_260, UInt<1>(0h1), "") : assert_13 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(is_aligned, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_267 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_267, UInt<1>(0h1), "") : assert_15 node _T_271 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : node _T_274 = eq(_T_271, UInt<1>(0h0)) when _T_274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_271, UInt<1>(0h1), "") : assert_16 node _T_275 = not(io.in.a.bits.mask) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_276, UInt<1>(0h1), "") : assert_17 node _T_280 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(_T_280, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_280, UInt<1>(0h1), "") : assert_18 node _T_284 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_284 : node _T_285 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_286 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_287 = and(_T_285, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_289 = shr(io.in.a.bits.source, 2) node _T_290 = eq(_T_289, UInt<1>(0h0)) node _T_291 = leq(UInt<1>(0h0), uncommonBits_12) node _T_292 = and(_T_290, _T_291) node _T_293 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_294 = and(_T_292, _T_293) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h1)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_13) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<2>(0h2)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_14) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h3)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_15) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_315 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_316 = or(_T_288, _T_294) node _T_317 = or(_T_316, _T_300) node _T_318 = or(_T_317, _T_306) node _T_319 = or(_T_318, _T_312) node _T_320 = or(_T_319, _T_313) node _T_321 = or(_T_320, _T_314) node _T_322 = or(_T_321, _T_315) node _T_323 = and(_T_287, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_324, UInt<1>(0h1), "") : assert_19 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = and(_T_331, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_338, UInt<1>(0h1), "") : assert_20 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(source_ok, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(is_aligned, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_348 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_348, UInt<1>(0h1), "") : assert_23 node _T_352 = eq(io.in.a.bits.mask, mask) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_352, UInt<1>(0h1), "") : assert_24 node _T_356 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_356, UInt<1>(0h1), "") : assert_25 node _T_360 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_360 : node _T_361 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_362 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_365 = shr(io.in.a.bits.source, 2) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = leq(UInt<1>(0h0), uncommonBits_16) node _T_368 = and(_T_366, _T_367) node _T_369 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_370 = and(_T_368, _T_369) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_371 = shr(io.in.a.bits.source, 2) node _T_372 = eq(_T_371, UInt<1>(0h1)) node _T_373 = leq(UInt<1>(0h0), uncommonBits_17) node _T_374 = and(_T_372, _T_373) node _T_375 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_377 = shr(io.in.a.bits.source, 2) node _T_378 = eq(_T_377, UInt<2>(0h2)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_18) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_382 = and(_T_380, _T_381) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_383 = shr(io.in.a.bits.source, 2) node _T_384 = eq(_T_383, UInt<2>(0h3)) node _T_385 = leq(UInt<1>(0h0), uncommonBits_19) node _T_386 = and(_T_384, _T_385) node _T_387 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_390 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_392 = or(_T_364, _T_370) node _T_393 = or(_T_392, _T_376) node _T_394 = or(_T_393, _T_382) node _T_395 = or(_T_394, _T_388) node _T_396 = or(_T_395, _T_389) node _T_397 = or(_T_396, _T_390) node _T_398 = or(_T_397, _T_391) node _T_399 = and(_T_363, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_402 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_403 = and(_T_401, _T_402) node _T_404 = or(UInt<1>(0h0), _T_403) node _T_405 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<13>(0h1000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = and(_T_404, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = and(_T_400, _T_411) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_412, UInt<1>(0h1), "") : assert_26 node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(source_ok, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_422 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_422, UInt<1>(0h1), "") : assert_29 node _T_426 = eq(io.in.a.bits.mask, mask) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_426, UInt<1>(0h1), "") : assert_30 node _T_430 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_430 : node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_432 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_435 = shr(io.in.a.bits.source, 2) node _T_436 = eq(_T_435, UInt<1>(0h0)) node _T_437 = leq(UInt<1>(0h0), uncommonBits_20) node _T_438 = and(_T_436, _T_437) node _T_439 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_440 = and(_T_438, _T_439) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_441 = shr(io.in.a.bits.source, 2) node _T_442 = eq(_T_441, UInt<1>(0h1)) node _T_443 = leq(UInt<1>(0h0), uncommonBits_21) node _T_444 = and(_T_442, _T_443) node _T_445 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_446 = and(_T_444, _T_445) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_447 = shr(io.in.a.bits.source, 2) node _T_448 = eq(_T_447, UInt<2>(0h2)) node _T_449 = leq(UInt<1>(0h0), uncommonBits_22) node _T_450 = and(_T_448, _T_449) node _T_451 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_452 = and(_T_450, _T_451) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_453 = shr(io.in.a.bits.source, 2) node _T_454 = eq(_T_453, UInt<2>(0h3)) node _T_455 = leq(UInt<1>(0h0), uncommonBits_23) node _T_456 = and(_T_454, _T_455) node _T_457 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_461 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_462 = or(_T_434, _T_440) node _T_463 = or(_T_462, _T_446) node _T_464 = or(_T_463, _T_452) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = or(_T_466, _T_460) node _T_468 = or(_T_467, _T_461) node _T_469 = and(_T_433, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_472 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_473 = and(_T_471, _T_472) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<13>(0h1000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = and(_T_474, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = and(_T_470, _T_481) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_482, UInt<1>(0h1), "") : assert_31 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_492, UInt<1>(0h1), "") : assert_34 node _T_496 = not(mask) node _T_497 = and(io.in.a.bits.mask, _T_496) node _T_498 = eq(_T_497, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_498, UInt<1>(0h1), "") : assert_35 node _T_502 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_502 : node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_505 = and(_T_503, _T_504) node _T_506 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<1>(0h0)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_24) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<1>(0h1)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_25) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_519 = shr(io.in.a.bits.source, 2) node _T_520 = eq(_T_519, UInt<2>(0h2)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_26) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_524 = and(_T_522, _T_523) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_525 = shr(io.in.a.bits.source, 2) node _T_526 = eq(_T_525, UInt<2>(0h3)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_27) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_533 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_534 = or(_T_506, _T_512) node _T_535 = or(_T_534, _T_518) node _T_536 = or(_T_535, _T_524) node _T_537 = or(_T_536, _T_530) node _T_538 = or(_T_537, _T_531) node _T_539 = or(_T_538, _T_532) node _T_540 = or(_T_539, _T_533) node _T_541 = and(_T_505, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_544 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = and(_T_543, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = and(_T_542, _T_550) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_551, UInt<1>(0h1), "") : assert_36 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(source_ok, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_558 = asUInt(reset) node _T_559 = eq(_T_558, UInt<1>(0h0)) when _T_559 : node _T_560 = eq(is_aligned, UInt<1>(0h0)) when _T_560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_561 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_561, UInt<1>(0h1), "") : assert_39 node _T_565 = eq(io.in.a.bits.mask, mask) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_565, UInt<1>(0h1), "") : assert_40 node _T_569 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_569 : node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_574 = shr(io.in.a.bits.source, 2) node _T_575 = eq(_T_574, UInt<1>(0h0)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_28) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_579 = and(_T_577, _T_578) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h1)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_29) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<2>(0h2)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_30) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h3)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_31) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_601 = or(_T_573, _T_579) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_591) node _T_604 = or(_T_603, _T_597) node _T_605 = or(_T_604, _T_598) node _T_606 = or(_T_605, _T_599) node _T_607 = or(_T_606, _T_600) node _T_608 = and(_T_572, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_611 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_612 = cvt(_T_611) node _T_613 = and(_T_612, asSInt(UInt<13>(0h1000))) node _T_614 = asSInt(_T_613) node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0))) node _T_616 = and(_T_610, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = and(_T_609, _T_617) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_618, UInt<1>(0h1), "") : assert_41 node _T_622 = asUInt(reset) node _T_623 = eq(_T_622, UInt<1>(0h0)) when _T_623 : node _T_624 = eq(source_ok, UInt<1>(0h0)) when _T_624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(is_aligned, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_628 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_628, UInt<1>(0h1), "") : assert_44 node _T_632 = eq(io.in.a.bits.mask, mask) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_632, UInt<1>(0h1), "") : assert_45 node _T_636 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_636 : node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_639 = and(_T_637, _T_638) node _T_640 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_641 = shr(io.in.a.bits.source, 2) node _T_642 = eq(_T_641, UInt<1>(0h0)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_32) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_646 = and(_T_644, _T_645) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_647 = shr(io.in.a.bits.source, 2) node _T_648 = eq(_T_647, UInt<1>(0h1)) node _T_649 = leq(UInt<1>(0h0), uncommonBits_33) node _T_650 = and(_T_648, _T_649) node _T_651 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_652 = and(_T_650, _T_651) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_653 = shr(io.in.a.bits.source, 2) node _T_654 = eq(_T_653, UInt<2>(0h2)) node _T_655 = leq(UInt<1>(0h0), uncommonBits_34) node _T_656 = and(_T_654, _T_655) node _T_657 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_658 = and(_T_656, _T_657) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_659 = shr(io.in.a.bits.source, 2) node _T_660 = eq(_T_659, UInt<2>(0h3)) node _T_661 = leq(UInt<1>(0h0), uncommonBits_35) node _T_662 = and(_T_660, _T_661) node _T_663 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_666 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_667 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_668 = or(_T_640, _T_646) node _T_669 = or(_T_668, _T_652) node _T_670 = or(_T_669, _T_658) node _T_671 = or(_T_670, _T_664) node _T_672 = or(_T_671, _T_665) node _T_673 = or(_T_672, _T_666) node _T_674 = or(_T_673, _T_667) node _T_675 = and(_T_639, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = and(_T_677, _T_682) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = and(_T_676, _T_684) node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(_T_685, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_685, UInt<1>(0h1), "") : assert_46 node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(source_ok, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(is_aligned, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_695 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_695, UInt<1>(0h1), "") : assert_49 node _T_699 = eq(io.in.a.bits.mask, mask) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_699, UInt<1>(0h1), "") : assert_50 node _T_703 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_703, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_707 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_707, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_711 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(source_ok_1, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_715 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_715, UInt<1>(0h1), "") : assert_54 node _T_719 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_719, UInt<1>(0h1), "") : assert_55 node _T_723 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_723, UInt<1>(0h1), "") : assert_56 node _T_727 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_727, UInt<1>(0h1), "") : assert_57 node _T_731 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_731 : node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok_1, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(sink_ok, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_738 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_738, UInt<1>(0h1), "") : assert_60 node _T_742 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_742, UInt<1>(0h1), "") : assert_61 node _T_746 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_746, UInt<1>(0h1), "") : assert_62 node _T_750 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_750, UInt<1>(0h1), "") : assert_63 node _T_754 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_755, UInt<1>(0h1), "") : assert_64 node _T_759 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_759 : node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(source_ok_1, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(sink_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_766 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(_T_766, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_766, UInt<1>(0h1), "") : assert_67 node _T_770 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_770, UInt<1>(0h1), "") : assert_68 node _T_774 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_774, UInt<1>(0h1), "") : assert_69 node _T_778 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_779 = or(_T_778, io.in.d.bits.corrupt) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_779, UInt<1>(0h1), "") : assert_70 node _T_783 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_784 = or(UInt<1>(0h0), _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_784, UInt<1>(0h1), "") : assert_71 node _T_788 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_788 : node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(source_ok_1, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_792 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(_T_792, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_792, UInt<1>(0h1), "") : assert_73 node _T_796 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_796, UInt<1>(0h1), "") : assert_74 node _T_800 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_801, UInt<1>(0h1), "") : assert_75 node _T_805 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_805 : node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(source_ok_1, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_809 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_809, UInt<1>(0h1), "") : assert_77 node _T_813 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_814 = or(_T_813, io.in.d.bits.corrupt) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_814, UInt<1>(0h1), "") : assert_78 node _T_818 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_819, UInt<1>(0h1), "") : assert_79 node _T_823 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_823 : node _T_824 = asUInt(reset) node _T_825 = eq(_T_824, UInt<1>(0h0)) when _T_825 : node _T_826 = eq(source_ok_1, UInt<1>(0h0)) when _T_826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_827 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(_T_827, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_827, UInt<1>(0h1), "") : assert_81 node _T_831 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_T_831, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_831, UInt<1>(0h1), "") : assert_82 node _T_835 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_836, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_840 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_840, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_844 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_844, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_848 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(_T_848, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_848, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_852 = eq(a_first, UInt<1>(0h0)) node _T_853 = and(io.in.a.valid, _T_852) when _T_853 : node _T_854 = eq(io.in.a.bits.opcode, opcode) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_854, UInt<1>(0h1), "") : assert_87 node _T_858 = eq(io.in.a.bits.param, param) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_858, UInt<1>(0h1), "") : assert_88 node _T_862 = eq(io.in.a.bits.size, size) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_862, UInt<1>(0h1), "") : assert_89 node _T_866 = eq(io.in.a.bits.source, source) node _T_867 = asUInt(reset) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : node _T_869 = eq(_T_866, UInt<1>(0h0)) when _T_869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_866, UInt<1>(0h1), "") : assert_90 node _T_870 = eq(io.in.a.bits.address, address) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_870, UInt<1>(0h1), "") : assert_91 node _T_874 = and(io.in.a.ready, io.in.a.valid) node _T_875 = and(_T_874, a_first) when _T_875 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_876 = eq(d_first, UInt<1>(0h0)) node _T_877 = and(io.in.d.valid, _T_876) when _T_877 : node _T_878 = eq(io.in.d.bits.opcode, opcode_1) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_878, UInt<1>(0h1), "") : assert_92 node _T_882 = eq(io.in.d.bits.param, param_1) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_882, UInt<1>(0h1), "") : assert_93 node _T_886 = eq(io.in.d.bits.size, size_1) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_886, UInt<1>(0h1), "") : assert_94 node _T_890 = eq(io.in.d.bits.source, source_1) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_890, UInt<1>(0h1), "") : assert_95 node _T_894 = eq(io.in.d.bits.sink, sink) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_894, UInt<1>(0h1), "") : assert_96 node _T_898 = eq(io.in.d.bits.denied, denied) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_898, UInt<1>(0h1), "") : assert_97 node _T_902 = and(io.in.d.ready, io.in.d.valid) node _T_903 = and(_T_902, d_first) when _T_903 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_904 = and(io.in.a.valid, a_first_1) node _T_905 = and(_T_904, UInt<1>(0h1)) when _T_905 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_906 = and(io.in.a.ready, io.in.a.valid) node _T_907 = and(_T_906, a_first_1) node _T_908 = and(_T_907, UInt<1>(0h1)) when _T_908 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_909 = dshr(inflight, io.in.a.bits.source) node _T_910 = bits(_T_909, 0, 0) node _T_911 = eq(_T_910, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_911, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_915 = and(io.in.d.valid, d_first_1) node _T_916 = and(_T_915, UInt<1>(0h1)) node _T_917 = eq(d_release_ack, UInt<1>(0h0)) node _T_918 = and(_T_916, _T_917) when _T_918 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_919 = and(io.in.d.ready, io.in.d.valid) node _T_920 = and(_T_919, d_first_1) node _T_921 = and(_T_920, UInt<1>(0h1)) node _T_922 = eq(d_release_ack, UInt<1>(0h0)) node _T_923 = and(_T_921, _T_922) when _T_923 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_924 = and(io.in.d.valid, d_first_1) node _T_925 = and(_T_924, UInt<1>(0h1)) node _T_926 = eq(d_release_ack, UInt<1>(0h0)) node _T_927 = and(_T_925, _T_926) when _T_927 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_928 = dshr(inflight, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_930, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_934 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_935 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_936 = or(_T_934, _T_935) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_936, UInt<1>(0h1), "") : assert_100 node _T_940 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_940, UInt<1>(0h1), "") : assert_101 else : node _T_944 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_945 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_946 = or(_T_944, _T_945) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_946, UInt<1>(0h1), "") : assert_102 node _T_950 = eq(io.in.d.bits.size, a_size_lookup) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_950, UInt<1>(0h1), "") : assert_103 node _T_954 = and(io.in.d.valid, d_first_1) node _T_955 = and(_T_954, a_first_1) node _T_956 = and(_T_955, io.in.a.valid) node _T_957 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_958 = and(_T_956, _T_957) node _T_959 = eq(d_release_ack, UInt<1>(0h0)) node _T_960 = and(_T_958, _T_959) when _T_960 : node _T_961 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_962 = or(_T_961, io.in.a.ready) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_962, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_124 node _T_966 = orr(inflight) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_969 = or(_T_967, _T_968) node _T_970 = lt(watchdog, plusarg_reader.out) node _T_971 = or(_T_969, _T_970) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_971, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_975 = and(io.in.a.ready, io.in.a.valid) node _T_976 = and(io.in.d.ready, io.in.d.valid) node _T_977 = or(_T_975, _T_976) when _T_977 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_978 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_979 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_980 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_981 = and(_T_979, _T_980) node _T_982 = and(_T_978, _T_981) when _T_982 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_983 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_984 = and(_T_983, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_985 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_986 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_987 = and(_T_985, _T_986) node _T_988 = and(_T_984, _T_987) when _T_988 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_989 = dshr(inflight_1, _WIRE_15.bits.source) node _T_990 = bits(_T_989, 0, 0) node _T_991 = eq(_T_990, UInt<1>(0h0)) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_991, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_995 = and(io.in.d.valid, d_first_2) node _T_996 = and(_T_995, UInt<1>(0h1)) node _T_997 = and(_T_996, d_release_ack_1) when _T_997 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_998 = and(io.in.d.ready, io.in.d.valid) node _T_999 = and(_T_998, d_first_2) node _T_1000 = and(_T_999, UInt<1>(0h1)) node _T_1001 = and(_T_1000, d_release_ack_1) when _T_1001 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1002 = and(io.in.d.valid, d_first_2) node _T_1003 = and(_T_1002, UInt<1>(0h1)) node _T_1004 = and(_T_1003, d_release_ack_1) when _T_1004 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1005 = dshr(inflight_1, io.in.d.bits.source) node _T_1006 = bits(_T_1005, 0, 0) node _T_1007 = or(_T_1006, same_cycle_resp_1) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1011 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_108 else : node _T_1015 = eq(io.in.d.bits.size, c_size_lookup) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_109 node _T_1019 = and(io.in.d.valid, d_first_2) node _T_1020 = and(_T_1019, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1021 = and(_T_1020, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1022 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = and(_T_1023, d_release_ack_1) node _T_1025 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _T_1027 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1028 = or(_T_1027, _WIRE_23.ready) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_125 node _T_1032 = orr(inflight_1) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) node _T_1034 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = lt(watchdog_1, plusarg_reader_1.out) node _T_1037 = or(_T_1035, _T_1036) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1041 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1042 = and(io.in.d.ready, io.in.d.valid) node _T_1043 = or(_T_1041, _T_1042) when _T_1043 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_975; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_128 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_145 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_128( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_145 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_146 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_146( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NullPrefetcher : input clock : Clock input reset : Reset output io : { flip mshr_avail : UInt<1>, flip req_val : UInt<1>, flip req_addr : UInt<40>, flip req_coh : { state : UInt<2>}, prefetch : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}} connect io.prefetch.valid, UInt<1>(0h0) invalidate io.prefetch.bits.is_hella invalidate io.prefetch.bits.data invalidate io.prefetch.bits.addr invalidate io.prefetch.bits.uop.debug_tsrc invalidate io.prefetch.bits.uop.debug_fsrc invalidate io.prefetch.bits.uop.bp_xcpt_if invalidate io.prefetch.bits.uop.bp_debug_if invalidate io.prefetch.bits.uop.xcpt_ma_if invalidate io.prefetch.bits.uop.xcpt_ae_if invalidate io.prefetch.bits.uop.xcpt_pf_if invalidate io.prefetch.bits.uop.fp_typ invalidate io.prefetch.bits.uop.fp_rm invalidate io.prefetch.bits.uop.fp_val invalidate io.prefetch.bits.uop.fcn_op invalidate io.prefetch.bits.uop.fcn_dw invalidate io.prefetch.bits.uop.frs3_en invalidate io.prefetch.bits.uop.lrs2_rtype invalidate io.prefetch.bits.uop.lrs1_rtype invalidate io.prefetch.bits.uop.dst_rtype invalidate io.prefetch.bits.uop.lrs3 invalidate io.prefetch.bits.uop.lrs2 invalidate io.prefetch.bits.uop.lrs1 invalidate io.prefetch.bits.uop.ldst invalidate io.prefetch.bits.uop.ldst_is_rs1 invalidate io.prefetch.bits.uop.csr_cmd invalidate io.prefetch.bits.uop.flush_on_commit invalidate io.prefetch.bits.uop.is_unique invalidate io.prefetch.bits.uop.uses_stq invalidate io.prefetch.bits.uop.uses_ldq invalidate io.prefetch.bits.uop.mem_signed invalidate io.prefetch.bits.uop.mem_size invalidate io.prefetch.bits.uop.mem_cmd invalidate io.prefetch.bits.uop.exc_cause invalidate io.prefetch.bits.uop.exception invalidate io.prefetch.bits.uop.stale_pdst invalidate io.prefetch.bits.uop.ppred_busy invalidate io.prefetch.bits.uop.prs3_busy invalidate io.prefetch.bits.uop.prs2_busy invalidate io.prefetch.bits.uop.prs1_busy invalidate io.prefetch.bits.uop.ppred invalidate io.prefetch.bits.uop.prs3 invalidate io.prefetch.bits.uop.prs2 invalidate io.prefetch.bits.uop.prs1 invalidate io.prefetch.bits.uop.pdst invalidate io.prefetch.bits.uop.rxq_idx invalidate io.prefetch.bits.uop.stq_idx invalidate io.prefetch.bits.uop.ldq_idx invalidate io.prefetch.bits.uop.rob_idx invalidate io.prefetch.bits.uop.fp_ctrl.vec invalidate io.prefetch.bits.uop.fp_ctrl.wflags invalidate io.prefetch.bits.uop.fp_ctrl.sqrt invalidate io.prefetch.bits.uop.fp_ctrl.div invalidate io.prefetch.bits.uop.fp_ctrl.fma invalidate io.prefetch.bits.uop.fp_ctrl.fastpipe invalidate io.prefetch.bits.uop.fp_ctrl.toint invalidate io.prefetch.bits.uop.fp_ctrl.fromint invalidate io.prefetch.bits.uop.fp_ctrl.typeTagOut invalidate io.prefetch.bits.uop.fp_ctrl.typeTagIn invalidate io.prefetch.bits.uop.fp_ctrl.swap23 invalidate io.prefetch.bits.uop.fp_ctrl.swap12 invalidate io.prefetch.bits.uop.fp_ctrl.ren3 invalidate io.prefetch.bits.uop.fp_ctrl.ren2 invalidate io.prefetch.bits.uop.fp_ctrl.ren1 invalidate io.prefetch.bits.uop.fp_ctrl.wen invalidate io.prefetch.bits.uop.fp_ctrl.ldst invalidate io.prefetch.bits.uop.op2_sel invalidate io.prefetch.bits.uop.op1_sel invalidate io.prefetch.bits.uop.imm_packed invalidate io.prefetch.bits.uop.pimm invalidate io.prefetch.bits.uop.imm_sel invalidate io.prefetch.bits.uop.imm_rename invalidate io.prefetch.bits.uop.taken invalidate io.prefetch.bits.uop.pc_lob invalidate io.prefetch.bits.uop.edge_inst invalidate io.prefetch.bits.uop.ftq_idx invalidate io.prefetch.bits.uop.is_mov invalidate io.prefetch.bits.uop.is_rocc invalidate io.prefetch.bits.uop.is_sys_pc2epc invalidate io.prefetch.bits.uop.is_eret invalidate io.prefetch.bits.uop.is_amo invalidate io.prefetch.bits.uop.is_sfence invalidate io.prefetch.bits.uop.is_fencei invalidate io.prefetch.bits.uop.is_fence invalidate io.prefetch.bits.uop.is_sfb invalidate io.prefetch.bits.uop.br_type invalidate io.prefetch.bits.uop.br_tag invalidate io.prefetch.bits.uop.br_mask invalidate io.prefetch.bits.uop.dis_col_sel invalidate io.prefetch.bits.uop.iw_p3_bypass_hint invalidate io.prefetch.bits.uop.iw_p2_bypass_hint invalidate io.prefetch.bits.uop.iw_p1_bypass_hint invalidate io.prefetch.bits.uop.iw_p2_speculative_child invalidate io.prefetch.bits.uop.iw_p1_speculative_child invalidate io.prefetch.bits.uop.iw_issued_partial_dgen invalidate io.prefetch.bits.uop.iw_issued_partial_agen invalidate io.prefetch.bits.uop.iw_issued invalidate io.prefetch.bits.uop.fu_code[0] invalidate io.prefetch.bits.uop.fu_code[1] invalidate io.prefetch.bits.uop.fu_code[2] invalidate io.prefetch.bits.uop.fu_code[3] invalidate io.prefetch.bits.uop.fu_code[4] invalidate io.prefetch.bits.uop.fu_code[5] invalidate io.prefetch.bits.uop.fu_code[6] invalidate io.prefetch.bits.uop.fu_code[7] invalidate io.prefetch.bits.uop.fu_code[8] invalidate io.prefetch.bits.uop.fu_code[9] invalidate io.prefetch.bits.uop.iq_type[0] invalidate io.prefetch.bits.uop.iq_type[1] invalidate io.prefetch.bits.uop.iq_type[2] invalidate io.prefetch.bits.uop.iq_type[3] invalidate io.prefetch.bits.uop.debug_pc invalidate io.prefetch.bits.uop.is_rvc invalidate io.prefetch.bits.uop.debug_inst invalidate io.prefetch.bits.uop.inst	module NullPrefetcher( // @[prefetcher.scala:39:7] input clock, // @[prefetcher.scala:39:7] input reset, // @[prefetcher.scala:39:7] input io_mshr_avail, // @[prefetcher.scala:26:14] input io_req_val, // @[prefetcher.scala:26:14] input [39:0] io_req_addr, // @[prefetcher.scala:26:14] input [1:0] io_req_coh_state, // @[prefetcher.scala:26:14] input io_prefetch_ready // @[prefetcher.scala:26:14] ); wire io_mshr_avail_0 = io_mshr_avail; // @[prefetcher.scala:39:7] wire io_req_val_0 = io_req_val; // @[prefetcher.scala:39:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[prefetcher.scala:39:7] wire [1:0] io_req_coh_state_0 = io_req_coh_state; // @[prefetcher.scala:39:7] wire io_prefetch_ready_0 = io_prefetch_ready; // @[prefetcher.scala:39:7] wire [63:0] io_prefetch_bits_uop_exc_cause = 64'h0; // @[prefetcher.scala:39:7] wire [63:0] io_prefetch_bits_data = 64'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_rob_idx = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_pdst = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_prs1 = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_prs2 = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_prs3 = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_stale_pdst = 7'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_op1_sel = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_rxq_idx = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_mem_size = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_dst_rtype = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_lrs1_rtype = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_lrs2_rtype = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_fp_typ = 2'h0; // @[prefetcher.scala:39:7] wire [19:0] io_prefetch_bits_uop_imm_packed = 20'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_pc_lob = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_ldst = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_lrs1 = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_lrs2 = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_lrs3 = 6'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_ftq_idx = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_pimm = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_ldq_idx = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_stq_idx = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_ppred = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_mem_cmd = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_fcn_op = 5'h0; // @[prefetcher.scala:39:7] wire [3:0] io_prefetch_bits_uop_br_tag = 4'h0; // @[prefetcher.scala:39:7] wire [3:0] io_prefetch_bits_uop_br_type = 4'h0; // @[prefetcher.scala:39:7] wire [15:0] io_prefetch_bits_uop_br_mask = 16'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_iw_p1_speculative_child = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_iw_p2_speculative_child = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_dis_col_sel = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_imm_sel = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_op2_sel = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_csr_cmd = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_fp_rm = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_debug_fsrc = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_debug_tsrc = 3'h0; // @[prefetcher.scala:39:7] wire [39:0] io_prefetch_bits_uop_debug_pc = 40'h0; // @[prefetcher.scala:39:7] wire [39:0] io_prefetch_bits_addr = 40'h0; // @[prefetcher.scala:39:7] wire [31:0] io_prefetch_bits_uop_inst = 32'h0; // @[prefetcher.scala:39:7] wire [31:0] io_prefetch_bits_uop_debug_inst = 32'h0; // @[prefetcher.scala:39:7] wire io_prefetch_valid = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_rvc = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_0 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_2 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_3 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_0 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_2 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_3 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_4 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_5 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_6 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_7 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_8 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_9 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_issued = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_issued_partial_agen = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_issued_partial_dgen = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_p1_bypass_hint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_p2_bypass_hint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_p3_bypass_hint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_sfb = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_fence = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_fencei = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_sfence = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_amo = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_eret = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_sys_pc2epc = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_rocc = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_mov = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_edge_inst = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_taken = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_imm_rename = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ldst = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_wen = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ren1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ren2 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ren3 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_swap12 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_swap23 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_fromint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_toint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_fma = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_div = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_sqrt = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_wflags = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_vec = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_prs1_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_prs2_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_prs3_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_ppred_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_exception = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_mem_signed = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_uses_ldq = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_uses_stq = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_unique = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_flush_on_commit = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_ldst_is_rs1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_frs3_en = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fcn_dw = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_val = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_xcpt_pf_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_xcpt_ae_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_xcpt_ma_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_bp_debug_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_bp_xcpt_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_is_hella = 1'h0; // @[prefetcher.scala:39:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s12k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_34 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s12k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s12k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_102 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_103 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a26d64s12k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_34 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s12k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s12k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_data (auto_out_d_bits_data), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d64s6k5z4c connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<4> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<1>(0h0)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T	module TLDToNoC( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d32s6k3z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_37 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a32d32s6k3z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a32d32s6k3z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a32d32s6k3z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_37 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a32d32s6k3z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a32d32s6k3z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_325 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_69 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_325( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_69 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ZstdCompressorMemWriter_1 : input clock : Clock input reset : Reset output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, l2io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip dest_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>, cmpval : UInt<64>}}, bufs_completed : UInt<64>, no_writes_inflight : UInt<1>} inst incoming_writes_Q of Queue4_WriterBundle_1 connect incoming_writes_Q.clock, clock connect incoming_writes_Q.reset, reset connect incoming_writes_Q.io.enq, io.memwrites_in inst dest_info_Q of Queue4_DstWithValInfo_5 connect dest_info_Q.clock, clock connect dest_info_Q.reset, reset connect dest_info_Q.io.enq, io.dest_info node _decompress_dest_last_fire_T = and(dest_info_Q.io.deq.ready, dest_info_Q.io.deq.valid) reg decompress_dest_last_fire : UInt<1>, clock connect decompress_dest_last_fire, _decompress_dest_last_fire_T reg decompress_dest_last_valid : UInt<1>, clock connect decompress_dest_last_valid, dest_info_Q.io.deq.valid node _decompress_dest_printhelp_T = eq(decompress_dest_last_valid, UInt<1>(0h0)) node _decompress_dest_printhelp_T_1 = or(decompress_dest_last_fire, _decompress_dest_printhelp_T) node decompress_dest_printhelp = and(dest_info_Q.io.deq.valid, _decompress_dest_printhelp_T_1) when decompress_dest_printhelp : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[config-memwriter] got dest info op: 0x%x, cmpflag 0x%x\n", dest_info_Q.io.deq.bits.op, dest_info_Q.io.deq.bits.cmpflag) : printf_1 inst buf_lens_Q of Queue10_UInt64_1 connect buf_lens_Q.clock, clock connect buf_lens_Q.reset, reset node _T_4 = and(buf_lens_Q.io.enq.ready, buf_lens_Q.io.enq.valid) when _T_4 : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits) : printf_3 regreset buf_len_tracker : UInt<64>, clock, reset, UInt<64>(0h0) node _T_9 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_9 : when incoming_writes_Q.io.deq.bits.end_of_message : connect buf_len_tracker, UInt<1>(0h0) else : node _buf_len_tracker_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_len_tracker, _buf_len_tracker_T node _T_10 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_10 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_5 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue2_UInt8 of Queue2_UInt8_32 connect Queue2_UInt8.clock, clock connect Queue2_UInt8.reset, reset inst Queue2_UInt8_1 of Queue2_UInt8_33 connect Queue2_UInt8_1.clock, clock connect Queue2_UInt8_1.reset, reset inst Queue2_UInt8_2 of Queue2_UInt8_34 connect Queue2_UInt8_2.clock, clock connect Queue2_UInt8_2.reset, reset inst Queue2_UInt8_3 of Queue2_UInt8_35 connect Queue2_UInt8_3.clock, clock connect Queue2_UInt8_3.reset, reset inst Queue2_UInt8_4 of Queue2_UInt8_36 connect Queue2_UInt8_4.clock, clock connect Queue2_UInt8_4.reset, reset inst Queue2_UInt8_5 of Queue2_UInt8_37 connect Queue2_UInt8_5.clock, clock connect Queue2_UInt8_5.reset, reset inst Queue2_UInt8_6 of Queue2_UInt8_38 connect Queue2_UInt8_6.clock, clock connect Queue2_UInt8_6.reset, reset inst Queue2_UInt8_7 of Queue2_UInt8_39 connect Queue2_UInt8_7.clock, clock connect Queue2_UInt8_7.reset, reset inst Queue2_UInt8_8 of Queue2_UInt8_40 connect Queue2_UInt8_8.clock, clock connect Queue2_UInt8_8.reset, reset inst Queue2_UInt8_9 of Queue2_UInt8_41 connect Queue2_UInt8_9.clock, clock connect Queue2_UInt8_9.reset, reset inst Queue2_UInt8_10 of Queue2_UInt8_42 connect Queue2_UInt8_10.clock, clock connect Queue2_UInt8_10.reset, reset inst Queue2_UInt8_11 of Queue2_UInt8_43 connect Queue2_UInt8_11.clock, clock connect Queue2_UInt8_11.reset, reset inst Queue2_UInt8_12 of Queue2_UInt8_44 connect Queue2_UInt8_12.clock, clock connect Queue2_UInt8_12.reset, reset inst Queue2_UInt8_13 of Queue2_UInt8_45 connect Queue2_UInt8_13.clock, clock connect Queue2_UInt8_13.reset, reset inst Queue2_UInt8_14 of Queue2_UInt8_46 connect Queue2_UInt8_14.clock, clock connect Queue2_UInt8_14.reset, reset inst Queue2_UInt8_15 of Queue2_UInt8_47 connect Queue2_UInt8_15.clock, clock connect Queue2_UInt8_15.reset, reset inst Queue2_UInt8_16 of Queue2_UInt8_48 connect Queue2_UInt8_16.clock, clock connect Queue2_UInt8_16.reset, reset inst Queue2_UInt8_17 of Queue2_UInt8_49 connect Queue2_UInt8_17.clock, clock connect Queue2_UInt8_17.reset, reset inst Queue2_UInt8_18 of Queue2_UInt8_50 connect Queue2_UInt8_18.clock, clock connect Queue2_UInt8_18.reset, reset inst Queue2_UInt8_19 of Queue2_UInt8_51 connect Queue2_UInt8_19.clock, clock connect Queue2_UInt8_19.reset, reset inst Queue2_UInt8_20 of Queue2_UInt8_52 connect Queue2_UInt8_20.clock, clock connect Queue2_UInt8_20.reset, reset inst Queue2_UInt8_21 of Queue2_UInt8_53 connect Queue2_UInt8_21.clock, clock connect Queue2_UInt8_21.reset, reset inst Queue2_UInt8_22 of Queue2_UInt8_54 connect Queue2_UInt8_22.clock, clock connect Queue2_UInt8_22.reset, reset inst Queue2_UInt8_23 of Queue2_UInt8_55 connect Queue2_UInt8_23.clock, clock connect Queue2_UInt8_23.reset, reset inst Queue2_UInt8_24 of Queue2_UInt8_56 connect Queue2_UInt8_24.clock, clock connect Queue2_UInt8_24.reset, reset inst Queue2_UInt8_25 of Queue2_UInt8_57 connect Queue2_UInt8_25.clock, clock connect Queue2_UInt8_25.reset, reset inst Queue2_UInt8_26 of Queue2_UInt8_58 connect Queue2_UInt8_26.clock, clock connect Queue2_UInt8_26.reset, reset inst Queue2_UInt8_27 of Queue2_UInt8_59 connect Queue2_UInt8_27.clock, clock connect Queue2_UInt8_27.reset, reset inst Queue2_UInt8_28 of Queue2_UInt8_60 connect Queue2_UInt8_28.clock, clock connect Queue2_UInt8_28.reset, reset inst Queue2_UInt8_29 of Queue2_UInt8_61 connect Queue2_UInt8_29.clock, clock connect Queue2_UInt8_29.reset, reset inst Queue2_UInt8_30 of Queue2_UInt8_62 connect Queue2_UInt8_30.clock, clock connect Queue2_UInt8_30.reset, reset inst Queue2_UInt8_31 of Queue2_UInt8_63 connect Queue2_UInt8_31.clock, clock connect Queue2_UInt8_31.reset, reset connect Queue2_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_15 = eq(UInt<1>(0h0), idx) when _T_15 : node _T_16 = shl(UInt<1>(0h0), 3) node _T_17 = dshr(incoming_writes_Q.io.deq.bits.data, _T_16) node _T_18 = bits(_T_17, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_18 node _T_19 = eq(UInt<1>(0h1), idx) when _T_19 : node _T_20 = shl(UInt<1>(0h0), 3) node _T_21 = dshr(incoming_writes_Q.io.deq.bits.data, _T_20) node _T_22 = bits(_T_21, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_22 node _T_23 = eq(UInt<2>(0h2), idx) when _T_23 : node _T_24 = shl(UInt<1>(0h0), 3) node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24) node _T_26 = bits(_T_25, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_26 node _T_27 = eq(UInt<2>(0h3), idx) when _T_27 : node _T_28 = shl(UInt<1>(0h0), 3) node _T_29 = dshr(incoming_writes_Q.io.deq.bits.data, _T_28) node _T_30 = bits(_T_29, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_30 node _T_31 = eq(UInt<3>(0h4), idx) when _T_31 : node _T_32 = shl(UInt<1>(0h0), 3) node _T_33 = dshr(incoming_writes_Q.io.deq.bits.data, _T_32) node _T_34 = bits(_T_33, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_34 node _T_35 = eq(UInt<3>(0h5), idx) when _T_35 : node _T_36 = shl(UInt<1>(0h0), 3) node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36) node _T_38 = bits(_T_37, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_38 node _T_39 = eq(UInt<3>(0h6), idx) when _T_39 : node _T_40 = shl(UInt<1>(0h0), 3) node _T_41 = dshr(incoming_writes_Q.io.deq.bits.data, _T_40) node _T_42 = bits(_T_41, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_42 node _T_43 = eq(UInt<3>(0h7), idx) when _T_43 : node _T_44 = shl(UInt<1>(0h0), 3) node _T_45 = dshr(incoming_writes_Q.io.deq.bits.data, _T_44) node _T_46 = bits(_T_45, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_46 node _T_47 = eq(UInt<4>(0h8), idx) when _T_47 : node _T_48 = shl(UInt<1>(0h0), 3) node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48) node _T_50 = bits(_T_49, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_50 node _T_51 = eq(UInt<4>(0h9), idx) when _T_51 : node _T_52 = shl(UInt<1>(0h0), 3) node _T_53 = dshr(incoming_writes_Q.io.deq.bits.data, _T_52) node _T_54 = bits(_T_53, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_54 node _T_55 = eq(UInt<4>(0ha), idx) when _T_55 : node _T_56 = shl(UInt<1>(0h0), 3) node _T_57 = dshr(incoming_writes_Q.io.deq.bits.data, _T_56) node _T_58 = bits(_T_57, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_58 node _T_59 = eq(UInt<4>(0hb), idx) when _T_59 : node _T_60 = shl(UInt<1>(0h0), 3) node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60) node _T_62 = bits(_T_61, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_62 node _T_63 = eq(UInt<4>(0hc), idx) when _T_63 : node _T_64 = shl(UInt<1>(0h0), 3) node _T_65 = dshr(incoming_writes_Q.io.deq.bits.data, _T_64) node _T_66 = bits(_T_65, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_66 node _T_67 = eq(UInt<4>(0hd), idx) when _T_67 : node _T_68 = shl(UInt<1>(0h0), 3) node _T_69 = dshr(incoming_writes_Q.io.deq.bits.data, _T_68) node _T_70 = bits(_T_69, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_70 node _T_71 = eq(UInt<4>(0he), idx) when _T_71 : node _T_72 = shl(UInt<1>(0h0), 3) node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72) node _T_74 = bits(_T_73, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_74 node _T_75 = eq(UInt<4>(0hf), idx) when _T_75 : node _T_76 = shl(UInt<1>(0h0), 3) node _T_77 = dshr(incoming_writes_Q.io.deq.bits.data, _T_76) node _T_78 = bits(_T_77, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_78 node _T_79 = eq(UInt<5>(0h10), idx) when _T_79 : node _T_80 = shl(UInt<1>(0h0), 3) node _T_81 = dshr(incoming_writes_Q.io.deq.bits.data, _T_80) node _T_82 = bits(_T_81, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_82 node _T_83 = eq(UInt<5>(0h11), idx) when _T_83 : node _T_84 = shl(UInt<1>(0h0), 3) node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84) node _T_86 = bits(_T_85, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_86 node _T_87 = eq(UInt<5>(0h12), idx) when _T_87 : node _T_88 = shl(UInt<1>(0h0), 3) node _T_89 = dshr(incoming_writes_Q.io.deq.bits.data, _T_88) node _T_90 = bits(_T_89, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_90 node _T_91 = eq(UInt<5>(0h13), idx) when _T_91 : node _T_92 = shl(UInt<1>(0h0), 3) node _T_93 = dshr(incoming_writes_Q.io.deq.bits.data, _T_92) node _T_94 = bits(_T_93, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_94 node _T_95 = eq(UInt<5>(0h14), idx) when _T_95 : node _T_96 = shl(UInt<1>(0h0), 3) node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96) node _T_98 = bits(_T_97, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_98 node _T_99 = eq(UInt<5>(0h15), idx) when _T_99 : node _T_100 = shl(UInt<1>(0h0), 3) node _T_101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_100) node _T_102 = bits(_T_101, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_102 node _T_103 = eq(UInt<5>(0h16), idx) when _T_103 : node _T_104 = shl(UInt<1>(0h0), 3) node _T_105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_104) node _T_106 = bits(_T_105, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_106 node _T_107 = eq(UInt<5>(0h17), idx) when _T_107 : node _T_108 = shl(UInt<1>(0h0), 3) node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108) node _T_110 = bits(_T_109, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_110 node _T_111 = eq(UInt<5>(0h18), idx) when _T_111 : node _T_112 = shl(UInt<1>(0h0), 3) node _T_113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_112) node _T_114 = bits(_T_113, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_114 node _T_115 = eq(UInt<5>(0h19), idx) when _T_115 : node _T_116 = shl(UInt<1>(0h0), 3) node _T_117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_116) node _T_118 = bits(_T_117, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_118 node _T_119 = eq(UInt<5>(0h1a), idx) when _T_119 : node _T_120 = shl(UInt<1>(0h0), 3) node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120) node _T_122 = bits(_T_121, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_122 node _T_123 = eq(UInt<5>(0h1b), idx) when _T_123 : node _T_124 = shl(UInt<1>(0h0), 3) node _T_125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_124) node _T_126 = bits(_T_125, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_126 node _T_127 = eq(UInt<5>(0h1c), idx) when _T_127 : node _T_128 = shl(UInt<1>(0h0), 3) node _T_129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_128) node _T_130 = bits(_T_129, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_130 node _T_131 = eq(UInt<5>(0h1d), idx) when _T_131 : node _T_132 = shl(UInt<1>(0h0), 3) node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132) node _T_134 = bits(_T_133, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_134 node _T_135 = eq(UInt<5>(0h1e), idx) when _T_135 : node _T_136 = shl(UInt<1>(0h0), 3) node _T_137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_136) node _T_138 = bits(_T_137, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_138 node _T_139 = eq(UInt<5>(0h1f), idx) when _T_139 : node _T_140 = shl(UInt<1>(0h0), 3) node _T_141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_140) node _T_142 = bits(_T_141, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_142 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_143 = eq(UInt<1>(0h0), idx_1) when _T_143 : node _T_144 = shl(UInt<1>(0h1), 3) node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144) node _T_146 = bits(_T_145, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_146 node _T_147 = eq(UInt<1>(0h1), idx_1) when _T_147 : node _T_148 = shl(UInt<1>(0h1), 3) node _T_149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_148) node _T_150 = bits(_T_149, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_150 node _T_151 = eq(UInt<2>(0h2), idx_1) when _T_151 : node _T_152 = shl(UInt<1>(0h1), 3) node _T_153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_152) node _T_154 = bits(_T_153, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_154 node _T_155 = eq(UInt<2>(0h3), idx_1) when _T_155 : node _T_156 = shl(UInt<1>(0h1), 3) node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156) node _T_158 = bits(_T_157, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_158 node _T_159 = eq(UInt<3>(0h4), idx_1) when _T_159 : node _T_160 = shl(UInt<1>(0h1), 3) node _T_161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_160) node _T_162 = bits(_T_161, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_162 node _T_163 = eq(UInt<3>(0h5), idx_1) when _T_163 : node _T_164 = shl(UInt<1>(0h1), 3) node _T_165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_164) node _T_166 = bits(_T_165, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_166 node _T_167 = eq(UInt<3>(0h6), idx_1) when _T_167 : node _T_168 = shl(UInt<1>(0h1), 3) node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168) node _T_170 = bits(_T_169, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_170 node _T_171 = eq(UInt<3>(0h7), idx_1) when _T_171 : node _T_172 = shl(UInt<1>(0h1), 3) node _T_173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_172) node _T_174 = bits(_T_173, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_174 node _T_175 = eq(UInt<4>(0h8), idx_1) when _T_175 : node _T_176 = shl(UInt<1>(0h1), 3) node _T_177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_176) node _T_178 = bits(_T_177, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_178 node _T_179 = eq(UInt<4>(0h9), idx_1) when _T_179 : node _T_180 = shl(UInt<1>(0h1), 3) node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180) node _T_182 = bits(_T_181, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_182 node _T_183 = eq(UInt<4>(0ha), idx_1) when _T_183 : node _T_184 = shl(UInt<1>(0h1), 3) node _T_185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_184) node _T_186 = bits(_T_185, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_186 node _T_187 = eq(UInt<4>(0hb), idx_1) when _T_187 : node _T_188 = shl(UInt<1>(0h1), 3) node _T_189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_188) node _T_190 = bits(_T_189, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_190 node _T_191 = eq(UInt<4>(0hc), idx_1) when _T_191 : node _T_192 = shl(UInt<1>(0h1), 3) node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192) node _T_194 = bits(_T_193, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_194 node _T_195 = eq(UInt<4>(0hd), idx_1) when _T_195 : node _T_196 = shl(UInt<1>(0h1), 3) node _T_197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_196) node _T_198 = bits(_T_197, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_198 node _T_199 = eq(UInt<4>(0he), idx_1) when _T_199 : node _T_200 = shl(UInt<1>(0h1), 3) node _T_201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_200) node _T_202 = bits(_T_201, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_202 node _T_203 = eq(UInt<4>(0hf), idx_1) when _T_203 : node _T_204 = shl(UInt<1>(0h1), 3) node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204) node _T_206 = bits(_T_205, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_206 node _T_207 = eq(UInt<5>(0h10), idx_1) when _T_207 : node _T_208 = shl(UInt<1>(0h1), 3) node _T_209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_208) node _T_210 = bits(_T_209, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_210 node _T_211 = eq(UInt<5>(0h11), idx_1) when _T_211 : node _T_212 = shl(UInt<1>(0h1), 3) node _T_213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_212) node _T_214 = bits(_T_213, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_214 node _T_215 = eq(UInt<5>(0h12), idx_1) when _T_215 : node _T_216 = shl(UInt<1>(0h1), 3) node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216) node _T_218 = bits(_T_217, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_218 node _T_219 = eq(UInt<5>(0h13), idx_1) when _T_219 : node _T_220 = shl(UInt<1>(0h1), 3) node _T_221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_220) node _T_222 = bits(_T_221, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_222 node _T_223 = eq(UInt<5>(0h14), idx_1) when _T_223 : node _T_224 = shl(UInt<1>(0h1), 3) node _T_225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_224) node _T_226 = bits(_T_225, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_226 node _T_227 = eq(UInt<5>(0h15), idx_1) when _T_227 : node _T_228 = shl(UInt<1>(0h1), 3) node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228) node _T_230 = bits(_T_229, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_230 node _T_231 = eq(UInt<5>(0h16), idx_1) when _T_231 : node _T_232 = shl(UInt<1>(0h1), 3) node _T_233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_232) node _T_234 = bits(_T_233, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_234 node _T_235 = eq(UInt<5>(0h17), idx_1) when _T_235 : node _T_236 = shl(UInt<1>(0h1), 3) node _T_237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_236) node _T_238 = bits(_T_237, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_238 node _T_239 = eq(UInt<5>(0h18), idx_1) when _T_239 : node _T_240 = shl(UInt<1>(0h1), 3) node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240) node _T_242 = bits(_T_241, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_242 node _T_243 = eq(UInt<5>(0h19), idx_1) when _T_243 : node _T_244 = shl(UInt<1>(0h1), 3) node _T_245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_244) node _T_246 = bits(_T_245, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_246 node _T_247 = eq(UInt<5>(0h1a), idx_1) when _T_247 : node _T_248 = shl(UInt<1>(0h1), 3) node _T_249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_248) node _T_250 = bits(_T_249, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_250 node _T_251 = eq(UInt<5>(0h1b), idx_1) when _T_251 : node _T_252 = shl(UInt<1>(0h1), 3) node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252) node _T_254 = bits(_T_253, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_254 node _T_255 = eq(UInt<5>(0h1c), idx_1) when _T_255 : node _T_256 = shl(UInt<1>(0h1), 3) node _T_257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_256) node _T_258 = bits(_T_257, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_258 node _T_259 = eq(UInt<5>(0h1d), idx_1) when _T_259 : node _T_260 = shl(UInt<1>(0h1), 3) node _T_261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_260) node _T_262 = bits(_T_261, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_262 node _T_263 = eq(UInt<5>(0h1e), idx_1) when _T_263 : node _T_264 = shl(UInt<1>(0h1), 3) node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264) node _T_266 = bits(_T_265, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_266 node _T_267 = eq(UInt<5>(0h1f), idx_1) when _T_267 : node _T_268 = shl(UInt<1>(0h1), 3) node _T_269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_268) node _T_270 = bits(_T_269, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_270 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_271 = eq(UInt<1>(0h0), idx_2) when _T_271 : node _T_272 = shl(UInt<2>(0h2), 3) node _T_273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_272) node _T_274 = bits(_T_273, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_274 node _T_275 = eq(UInt<1>(0h1), idx_2) when _T_275 : node _T_276 = shl(UInt<2>(0h2), 3) node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276) node _T_278 = bits(_T_277, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_278 node _T_279 = eq(UInt<2>(0h2), idx_2) when _T_279 : node _T_280 = shl(UInt<2>(0h2), 3) node _T_281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_280) node _T_282 = bits(_T_281, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_282 node _T_283 = eq(UInt<2>(0h3), idx_2) when _T_283 : node _T_284 = shl(UInt<2>(0h2), 3) node _T_285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_284) node _T_286 = bits(_T_285, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_286 node _T_287 = eq(UInt<3>(0h4), idx_2) when _T_287 : node _T_288 = shl(UInt<2>(0h2), 3) node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288) node _T_290 = bits(_T_289, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_290 node _T_291 = eq(UInt<3>(0h5), idx_2) when _T_291 : node _T_292 = shl(UInt<2>(0h2), 3) node _T_293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_292) node _T_294 = bits(_T_293, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_294 node _T_295 = eq(UInt<3>(0h6), idx_2) when _T_295 : node _T_296 = shl(UInt<2>(0h2), 3) node _T_297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_296) node _T_298 = bits(_T_297, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_298 node _T_299 = eq(UInt<3>(0h7), idx_2) when _T_299 : node _T_300 = shl(UInt<2>(0h2), 3) node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300) node _T_302 = bits(_T_301, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_302 node _T_303 = eq(UInt<4>(0h8), idx_2) when _T_303 : node _T_304 = shl(UInt<2>(0h2), 3) node _T_305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_304) node _T_306 = bits(_T_305, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_306 node _T_307 = eq(UInt<4>(0h9), idx_2) when _T_307 : node _T_308 = shl(UInt<2>(0h2), 3) node _T_309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_308) node _T_310 = bits(_T_309, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_310 node _T_311 = eq(UInt<4>(0ha), idx_2) when _T_311 : node _T_312 = shl(UInt<2>(0h2), 3) node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312) node _T_314 = bits(_T_313, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_314 node _T_315 = eq(UInt<4>(0hb), idx_2) when _T_315 : node _T_316 = shl(UInt<2>(0h2), 3) node _T_317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_316) node _T_318 = bits(_T_317, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_318 node _T_319 = eq(UInt<4>(0hc), idx_2) when _T_319 : node _T_320 = shl(UInt<2>(0h2), 3) node _T_321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_320) node _T_322 = bits(_T_321, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_322 node _T_323 = eq(UInt<4>(0hd), idx_2) when _T_323 : node _T_324 = shl(UInt<2>(0h2), 3) node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324) node _T_326 = bits(_T_325, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_326 node _T_327 = eq(UInt<4>(0he), idx_2) when _T_327 : node _T_328 = shl(UInt<2>(0h2), 3) node _T_329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_328) node _T_330 = bits(_T_329, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_330 node _T_331 = eq(UInt<4>(0hf), idx_2) when _T_331 : node _T_332 = shl(UInt<2>(0h2), 3) node _T_333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_332) node _T_334 = bits(_T_333, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_334 node _T_335 = eq(UInt<5>(0h10), idx_2) when _T_335 : node _T_336 = shl(UInt<2>(0h2), 3) node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336) node _T_338 = bits(_T_337, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_338 node _T_339 = eq(UInt<5>(0h11), idx_2) when _T_339 : node _T_340 = shl(UInt<2>(0h2), 3) node _T_341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_340) node _T_342 = bits(_T_341, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_342 node _T_343 = eq(UInt<5>(0h12), idx_2) when _T_343 : node _T_344 = shl(UInt<2>(0h2), 3) node _T_345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_344) node _T_346 = bits(_T_345, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_346 node _T_347 = eq(UInt<5>(0h13), idx_2) when _T_347 : node _T_348 = shl(UInt<2>(0h2), 3) node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348) node _T_350 = bits(_T_349, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_350 node _T_351 = eq(UInt<5>(0h14), idx_2) when _T_351 : node _T_352 = shl(UInt<2>(0h2), 3) node _T_353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_352) node _T_354 = bits(_T_353, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_354 node _T_355 = eq(UInt<5>(0h15), idx_2) when _T_355 : node _T_356 = shl(UInt<2>(0h2), 3) node _T_357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_356) node _T_358 = bits(_T_357, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_358 node _T_359 = eq(UInt<5>(0h16), idx_2) when _T_359 : node _T_360 = shl(UInt<2>(0h2), 3) node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360) node _T_362 = bits(_T_361, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_362 node _T_363 = eq(UInt<5>(0h17), idx_2) when _T_363 : node _T_364 = shl(UInt<2>(0h2), 3) node _T_365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_364) node _T_366 = bits(_T_365, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_366 node _T_367 = eq(UInt<5>(0h18), idx_2) when _T_367 : node _T_368 = shl(UInt<2>(0h2), 3) node _T_369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_368) node _T_370 = bits(_T_369, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_370 node _T_371 = eq(UInt<5>(0h19), idx_2) when _T_371 : node _T_372 = shl(UInt<2>(0h2), 3) node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372) node _T_374 = bits(_T_373, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_374 node _T_375 = eq(UInt<5>(0h1a), idx_2) when _T_375 : node _T_376 = shl(UInt<2>(0h2), 3) node _T_377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_376) node _T_378 = bits(_T_377, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_378 node _T_379 = eq(UInt<5>(0h1b), idx_2) when _T_379 : node _T_380 = shl(UInt<2>(0h2), 3) node _T_381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_380) node _T_382 = bits(_T_381, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_382 node _T_383 = eq(UInt<5>(0h1c), idx_2) when _T_383 : node _T_384 = shl(UInt<2>(0h2), 3) node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384) node _T_386 = bits(_T_385, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_386 node _T_387 = eq(UInt<5>(0h1d), idx_2) when _T_387 : node _T_388 = shl(UInt<2>(0h2), 3) node _T_389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_388) node _T_390 = bits(_T_389, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_390 node _T_391 = eq(UInt<5>(0h1e), idx_2) when _T_391 : node _T_392 = shl(UInt<2>(0h2), 3) node _T_393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_392) node _T_394 = bits(_T_393, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_394 node _T_395 = eq(UInt<5>(0h1f), idx_2) when _T_395 : node _T_396 = shl(UInt<2>(0h2), 3) node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396) node _T_398 = bits(_T_397, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_398 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_399 = eq(UInt<1>(0h0), idx_3) when _T_399 : node _T_400 = shl(UInt<2>(0h3), 3) node _T_401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_400) node _T_402 = bits(_T_401, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_402 node _T_403 = eq(UInt<1>(0h1), idx_3) when _T_403 : node _T_404 = shl(UInt<2>(0h3), 3) node _T_405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_404) node _T_406 = bits(_T_405, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_406 node _T_407 = eq(UInt<2>(0h2), idx_3) when _T_407 : node _T_408 = shl(UInt<2>(0h3), 3) node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408) node _T_410 = bits(_T_409, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_410 node _T_411 = eq(UInt<2>(0h3), idx_3) when _T_411 : node _T_412 = shl(UInt<2>(0h3), 3) node _T_413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_412) node _T_414 = bits(_T_413, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_414 node _T_415 = eq(UInt<3>(0h4), idx_3) when _T_415 : node _T_416 = shl(UInt<2>(0h3), 3) node _T_417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_416) node _T_418 = bits(_T_417, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_418 node _T_419 = eq(UInt<3>(0h5), idx_3) when _T_419 : node _T_420 = shl(UInt<2>(0h3), 3) node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420) node _T_422 = bits(_T_421, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_422 node _T_423 = eq(UInt<3>(0h6), idx_3) when _T_423 : node _T_424 = shl(UInt<2>(0h3), 3) node _T_425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_424) node _T_426 = bits(_T_425, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_426 node _T_427 = eq(UInt<3>(0h7), idx_3) when _T_427 : node _T_428 = shl(UInt<2>(0h3), 3) node _T_429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_428) node _T_430 = bits(_T_429, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_430 node _T_431 = eq(UInt<4>(0h8), idx_3) when _T_431 : node _T_432 = shl(UInt<2>(0h3), 3) node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432) node _T_434 = bits(_T_433, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_434 node _T_435 = eq(UInt<4>(0h9), idx_3) when _T_435 : node _T_436 = shl(UInt<2>(0h3), 3) node _T_437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_436) node _T_438 = bits(_T_437, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_438 node _T_439 = eq(UInt<4>(0ha), idx_3) when _T_439 : node _T_440 = shl(UInt<2>(0h3), 3) node _T_441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_440) node _T_442 = bits(_T_441, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_442 node _T_443 = eq(UInt<4>(0hb), idx_3) when _T_443 : node _T_444 = shl(UInt<2>(0h3), 3) node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444) node _T_446 = bits(_T_445, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_446 node _T_447 = eq(UInt<4>(0hc), idx_3) when _T_447 : node _T_448 = shl(UInt<2>(0h3), 3) node _T_449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_448) node _T_450 = bits(_T_449, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_450 node _T_451 = eq(UInt<4>(0hd), idx_3) when _T_451 : node _T_452 = shl(UInt<2>(0h3), 3) node _T_453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_452) node _T_454 = bits(_T_453, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_454 node _T_455 = eq(UInt<4>(0he), idx_3) when _T_455 : node _T_456 = shl(UInt<2>(0h3), 3) node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456) node _T_458 = bits(_T_457, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_458 node _T_459 = eq(UInt<4>(0hf), idx_3) when _T_459 : node _T_460 = shl(UInt<2>(0h3), 3) node _T_461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_460) node _T_462 = bits(_T_461, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_462 node _T_463 = eq(UInt<5>(0h10), idx_3) when _T_463 : node _T_464 = shl(UInt<2>(0h3), 3) node _T_465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_464) node _T_466 = bits(_T_465, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_466 node _T_467 = eq(UInt<5>(0h11), idx_3) when _T_467 : node _T_468 = shl(UInt<2>(0h3), 3) node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468) node _T_470 = bits(_T_469, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_470 node _T_471 = eq(UInt<5>(0h12), idx_3) when _T_471 : node _T_472 = shl(UInt<2>(0h3), 3) node _T_473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_472) node _T_474 = bits(_T_473, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_474 node _T_475 = eq(UInt<5>(0h13), idx_3) when _T_475 : node _T_476 = shl(UInt<2>(0h3), 3) node _T_477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_476) node _T_478 = bits(_T_477, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_478 node _T_479 = eq(UInt<5>(0h14), idx_3) when _T_479 : node _T_480 = shl(UInt<2>(0h3), 3) node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480) node _T_482 = bits(_T_481, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_482 node _T_483 = eq(UInt<5>(0h15), idx_3) when _T_483 : node _T_484 = shl(UInt<2>(0h3), 3) node _T_485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_484) node _T_486 = bits(_T_485, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_486 node _T_487 = eq(UInt<5>(0h16), idx_3) when _T_487 : node _T_488 = shl(UInt<2>(0h3), 3) node _T_489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_488) node _T_490 = bits(_T_489, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_490 node _T_491 = eq(UInt<5>(0h17), idx_3) when _T_491 : node _T_492 = shl(UInt<2>(0h3), 3) node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492) node _T_494 = bits(_T_493, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_494 node _T_495 = eq(UInt<5>(0h18), idx_3) when _T_495 : node _T_496 = shl(UInt<2>(0h3), 3) node _T_497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_496) node _T_498 = bits(_T_497, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_498 node _T_499 = eq(UInt<5>(0h19), idx_3) when _T_499 : node _T_500 = shl(UInt<2>(0h3), 3) node _T_501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_500) node _T_502 = bits(_T_501, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_502 node _T_503 = eq(UInt<5>(0h1a), idx_3) when _T_503 : node _T_504 = shl(UInt<2>(0h3), 3) node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504) node _T_506 = bits(_T_505, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_506 node _T_507 = eq(UInt<5>(0h1b), idx_3) when _T_507 : node _T_508 = shl(UInt<2>(0h3), 3) node _T_509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_508) node _T_510 = bits(_T_509, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_510 node _T_511 = eq(UInt<5>(0h1c), idx_3) when _T_511 : node _T_512 = shl(UInt<2>(0h3), 3) node _T_513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_512) node _T_514 = bits(_T_513, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_514 node _T_515 = eq(UInt<5>(0h1d), idx_3) when _T_515 : node _T_516 = shl(UInt<2>(0h3), 3) node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516) node _T_518 = bits(_T_517, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_518 node _T_519 = eq(UInt<5>(0h1e), idx_3) when _T_519 : node _T_520 = shl(UInt<2>(0h3), 3) node _T_521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_520) node _T_522 = bits(_T_521, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_522 node _T_523 = eq(UInt<5>(0h1f), idx_3) when _T_523 : node _T_524 = shl(UInt<2>(0h3), 3) node _T_525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_524) node _T_526 = bits(_T_525, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_526 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_527 = eq(UInt<1>(0h0), idx_4) when _T_527 : node _T_528 = shl(UInt<3>(0h4), 3) node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528) node _T_530 = bits(_T_529, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_530 node _T_531 = eq(UInt<1>(0h1), idx_4) when _T_531 : node _T_532 = shl(UInt<3>(0h4), 3) node _T_533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_532) node _T_534 = bits(_T_533, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_534 node _T_535 = eq(UInt<2>(0h2), idx_4) when _T_535 : node _T_536 = shl(UInt<3>(0h4), 3) node _T_537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_536) node _T_538 = bits(_T_537, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_538 node _T_539 = eq(UInt<2>(0h3), idx_4) when _T_539 : node _T_540 = shl(UInt<3>(0h4), 3) node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540) node _T_542 = bits(_T_541, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_542 node _T_543 = eq(UInt<3>(0h4), idx_4) when _T_543 : node _T_544 = shl(UInt<3>(0h4), 3) node _T_545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_544) node _T_546 = bits(_T_545, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_546 node _T_547 = eq(UInt<3>(0h5), idx_4) when _T_547 : node _T_548 = shl(UInt<3>(0h4), 3) node _T_549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_548) node _T_550 = bits(_T_549, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_550 node _T_551 = eq(UInt<3>(0h6), idx_4) when _T_551 : node _T_552 = shl(UInt<3>(0h4), 3) node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552) node _T_554 = bits(_T_553, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_554 node _T_555 = eq(UInt<3>(0h7), idx_4) when _T_555 : node _T_556 = shl(UInt<3>(0h4), 3) node _T_557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_556) node _T_558 = bits(_T_557, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_558 node _T_559 = eq(UInt<4>(0h8), idx_4) when _T_559 : node _T_560 = shl(UInt<3>(0h4), 3) node _T_561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_560) node _T_562 = bits(_T_561, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_562 node _T_563 = eq(UInt<4>(0h9), idx_4) when _T_563 : node _T_564 = shl(UInt<3>(0h4), 3) node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564) node _T_566 = bits(_T_565, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_566 node _T_567 = eq(UInt<4>(0ha), idx_4) when _T_567 : node _T_568 = shl(UInt<3>(0h4), 3) node _T_569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_568) node _T_570 = bits(_T_569, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_570 node _T_571 = eq(UInt<4>(0hb), idx_4) when _T_571 : node _T_572 = shl(UInt<3>(0h4), 3) node _T_573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_572) node _T_574 = bits(_T_573, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_574 node _T_575 = eq(UInt<4>(0hc), idx_4) when _T_575 : node _T_576 = shl(UInt<3>(0h4), 3) node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576) node _T_578 = bits(_T_577, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_578 node _T_579 = eq(UInt<4>(0hd), idx_4) when _T_579 : node _T_580 = shl(UInt<3>(0h4), 3) node _T_581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_580) node _T_582 = bits(_T_581, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_582 node _T_583 = eq(UInt<4>(0he), idx_4) when _T_583 : node _T_584 = shl(UInt<3>(0h4), 3) node _T_585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_584) node _T_586 = bits(_T_585, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_586 node _T_587 = eq(UInt<4>(0hf), idx_4) when _T_587 : node _T_588 = shl(UInt<3>(0h4), 3) node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588) node _T_590 = bits(_T_589, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_590 node _T_591 = eq(UInt<5>(0h10), idx_4) when _T_591 : node _T_592 = shl(UInt<3>(0h4), 3) node _T_593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_592) node _T_594 = bits(_T_593, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_594 node _T_595 = eq(UInt<5>(0h11), idx_4) when _T_595 : node _T_596 = shl(UInt<3>(0h4), 3) node _T_597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_596) node _T_598 = bits(_T_597, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_598 node _T_599 = eq(UInt<5>(0h12), idx_4) when _T_599 : node _T_600 = shl(UInt<3>(0h4), 3) node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600) node _T_602 = bits(_T_601, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_602 node _T_603 = eq(UInt<5>(0h13), idx_4) when _T_603 : node _T_604 = shl(UInt<3>(0h4), 3) node _T_605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_604) node _T_606 = bits(_T_605, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_606 node _T_607 = eq(UInt<5>(0h14), idx_4) when _T_607 : node _T_608 = shl(UInt<3>(0h4), 3) node _T_609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_608) node _T_610 = bits(_T_609, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_610 node _T_611 = eq(UInt<5>(0h15), idx_4) when _T_611 : node _T_612 = shl(UInt<3>(0h4), 3) node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612) node _T_614 = bits(_T_613, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_614 node _T_615 = eq(UInt<5>(0h16), idx_4) when _T_615 : node _T_616 = shl(UInt<3>(0h4), 3) node _T_617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_616) node _T_618 = bits(_T_617, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_618 node _T_619 = eq(UInt<5>(0h17), idx_4) when _T_619 : node _T_620 = shl(UInt<3>(0h4), 3) node _T_621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_620) node _T_622 = bits(_T_621, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_622 node _T_623 = eq(UInt<5>(0h18), idx_4) when _T_623 : node _T_624 = shl(UInt<3>(0h4), 3) node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624) node _T_626 = bits(_T_625, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_626 node _T_627 = eq(UInt<5>(0h19), idx_4) when _T_627 : node _T_628 = shl(UInt<3>(0h4), 3) node _T_629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_628) node _T_630 = bits(_T_629, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_630 node _T_631 = eq(UInt<5>(0h1a), idx_4) when _T_631 : node _T_632 = shl(UInt<3>(0h4), 3) node _T_633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_632) node _T_634 = bits(_T_633, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_634 node _T_635 = eq(UInt<5>(0h1b), idx_4) when _T_635 : node _T_636 = shl(UInt<3>(0h4), 3) node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636) node _T_638 = bits(_T_637, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_638 node _T_639 = eq(UInt<5>(0h1c), idx_4) when _T_639 : node _T_640 = shl(UInt<3>(0h4), 3) node _T_641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_640) node _T_642 = bits(_T_641, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_642 node _T_643 = eq(UInt<5>(0h1d), idx_4) when _T_643 : node _T_644 = shl(UInt<3>(0h4), 3) node _T_645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_644) node _T_646 = bits(_T_645, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_646 node _T_647 = eq(UInt<5>(0h1e), idx_4) when _T_647 : node _T_648 = shl(UInt<3>(0h4), 3) node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648) node _T_650 = bits(_T_649, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_650 node _T_651 = eq(UInt<5>(0h1f), idx_4) when _T_651 : node _T_652 = shl(UInt<3>(0h4), 3) node _T_653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_652) node _T_654 = bits(_T_653, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_654 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_655 = eq(UInt<1>(0h0), idx_5) when _T_655 : node _T_656 = shl(UInt<3>(0h5), 3) node _T_657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_656) node _T_658 = bits(_T_657, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_658 node _T_659 = eq(UInt<1>(0h1), idx_5) when _T_659 : node _T_660 = shl(UInt<3>(0h5), 3) node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660) node _T_662 = bits(_T_661, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_662 node _T_663 = eq(UInt<2>(0h2), idx_5) when _T_663 : node _T_664 = shl(UInt<3>(0h5), 3) node _T_665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_664) node _T_666 = bits(_T_665, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_666 node _T_667 = eq(UInt<2>(0h3), idx_5) when _T_667 : node _T_668 = shl(UInt<3>(0h5), 3) node _T_669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_668) node _T_670 = bits(_T_669, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_670 node _T_671 = eq(UInt<3>(0h4), idx_5) when _T_671 : node _T_672 = shl(UInt<3>(0h5), 3) node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672) node _T_674 = bits(_T_673, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_674 node _T_675 = eq(UInt<3>(0h5), idx_5) when _T_675 : node _T_676 = shl(UInt<3>(0h5), 3) node _T_677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_676) node _T_678 = bits(_T_677, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_678 node _T_679 = eq(UInt<3>(0h6), idx_5) when _T_679 : node _T_680 = shl(UInt<3>(0h5), 3) node _T_681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_680) node _T_682 = bits(_T_681, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_682 node _T_683 = eq(UInt<3>(0h7), idx_5) when _T_683 : node _T_684 = shl(UInt<3>(0h5), 3) node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684) node _T_686 = bits(_T_685, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_686 node _T_687 = eq(UInt<4>(0h8), idx_5) when _T_687 : node _T_688 = shl(UInt<3>(0h5), 3) node _T_689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_688) node _T_690 = bits(_T_689, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_690 node _T_691 = eq(UInt<4>(0h9), idx_5) when _T_691 : node _T_692 = shl(UInt<3>(0h5), 3) node _T_693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_692) node _T_694 = bits(_T_693, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_694 node _T_695 = eq(UInt<4>(0ha), idx_5) when _T_695 : node _T_696 = shl(UInt<3>(0h5), 3) node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696) node _T_698 = bits(_T_697, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_698 node _T_699 = eq(UInt<4>(0hb), idx_5) when _T_699 : node _T_700 = shl(UInt<3>(0h5), 3) node _T_701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_700) node _T_702 = bits(_T_701, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_702 node _T_703 = eq(UInt<4>(0hc), idx_5) when _T_703 : node _T_704 = shl(UInt<3>(0h5), 3) node _T_705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_704) node _T_706 = bits(_T_705, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_706 node _T_707 = eq(UInt<4>(0hd), idx_5) when _T_707 : node _T_708 = shl(UInt<3>(0h5), 3) node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708) node _T_710 = bits(_T_709, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_710 node _T_711 = eq(UInt<4>(0he), idx_5) when _T_711 : node _T_712 = shl(UInt<3>(0h5), 3) node _T_713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_712) node _T_714 = bits(_T_713, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_714 node _T_715 = eq(UInt<4>(0hf), idx_5) when _T_715 : node _T_716 = shl(UInt<3>(0h5), 3) node _T_717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_716) node _T_718 = bits(_T_717, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_718 node _T_719 = eq(UInt<5>(0h10), idx_5) when _T_719 : node _T_720 = shl(UInt<3>(0h5), 3) node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720) node _T_722 = bits(_T_721, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_722 node _T_723 = eq(UInt<5>(0h11), idx_5) when _T_723 : node _T_724 = shl(UInt<3>(0h5), 3) node _T_725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_724) node _T_726 = bits(_T_725, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_726 node _T_727 = eq(UInt<5>(0h12), idx_5) when _T_727 : node _T_728 = shl(UInt<3>(0h5), 3) node _T_729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_728) node _T_730 = bits(_T_729, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_730 node _T_731 = eq(UInt<5>(0h13), idx_5) when _T_731 : node _T_732 = shl(UInt<3>(0h5), 3) node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732) node _T_734 = bits(_T_733, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_734 node _T_735 = eq(UInt<5>(0h14), idx_5) when _T_735 : node _T_736 = shl(UInt<3>(0h5), 3) node _T_737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_736) node _T_738 = bits(_T_737, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_738 node _T_739 = eq(UInt<5>(0h15), idx_5) when _T_739 : node _T_740 = shl(UInt<3>(0h5), 3) node _T_741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_740) node _T_742 = bits(_T_741, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_742 node _T_743 = eq(UInt<5>(0h16), idx_5) when _T_743 : node _T_744 = shl(UInt<3>(0h5), 3) node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744) node _T_746 = bits(_T_745, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_746 node _T_747 = eq(UInt<5>(0h17), idx_5) when _T_747 : node _T_748 = shl(UInt<3>(0h5), 3) node _T_749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_748) node _T_750 = bits(_T_749, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_750 node _T_751 = eq(UInt<5>(0h18), idx_5) when _T_751 : node _T_752 = shl(UInt<3>(0h5), 3) node _T_753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_752) node _T_754 = bits(_T_753, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_754 node _T_755 = eq(UInt<5>(0h19), idx_5) when _T_755 : node _T_756 = shl(UInt<3>(0h5), 3) node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756) node _T_758 = bits(_T_757, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_758 node _T_759 = eq(UInt<5>(0h1a), idx_5) when _T_759 : node _T_760 = shl(UInt<3>(0h5), 3) node _T_761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_760) node _T_762 = bits(_T_761, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_762 node _T_763 = eq(UInt<5>(0h1b), idx_5) when _T_763 : node _T_764 = shl(UInt<3>(0h5), 3) node _T_765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_764) node _T_766 = bits(_T_765, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_766 node _T_767 = eq(UInt<5>(0h1c), idx_5) when _T_767 : node _T_768 = shl(UInt<3>(0h5), 3) node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768) node _T_770 = bits(_T_769, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_770 node _T_771 = eq(UInt<5>(0h1d), idx_5) when _T_771 : node _T_772 = shl(UInt<3>(0h5), 3) node _T_773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_772) node _T_774 = bits(_T_773, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_774 node _T_775 = eq(UInt<5>(0h1e), idx_5) when _T_775 : node _T_776 = shl(UInt<3>(0h5), 3) node _T_777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_776) node _T_778 = bits(_T_777, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_778 node _T_779 = eq(UInt<5>(0h1f), idx_5) when _T_779 : node _T_780 = shl(UInt<3>(0h5), 3) node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780) node _T_782 = bits(_T_781, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_782 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_783 = eq(UInt<1>(0h0), idx_6) when _T_783 : node _T_784 = shl(UInt<3>(0h6), 3) node _T_785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_784) node _T_786 = bits(_T_785, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_786 node _T_787 = eq(UInt<1>(0h1), idx_6) when _T_787 : node _T_788 = shl(UInt<3>(0h6), 3) node _T_789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_788) node _T_790 = bits(_T_789, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_790 node _T_791 = eq(UInt<2>(0h2), idx_6) when _T_791 : node _T_792 = shl(UInt<3>(0h6), 3) node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792) node _T_794 = bits(_T_793, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_794 node _T_795 = eq(UInt<2>(0h3), idx_6) when _T_795 : node _T_796 = shl(UInt<3>(0h6), 3) node _T_797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_796) node _T_798 = bits(_T_797, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_798 node _T_799 = eq(UInt<3>(0h4), idx_6) when _T_799 : node _T_800 = shl(UInt<3>(0h6), 3) node _T_801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_800) node _T_802 = bits(_T_801, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_802 node _T_803 = eq(UInt<3>(0h5), idx_6) when _T_803 : node _T_804 = shl(UInt<3>(0h6), 3) node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804) node _T_806 = bits(_T_805, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_806 node _T_807 = eq(UInt<3>(0h6), idx_6) when _T_807 : node _T_808 = shl(UInt<3>(0h6), 3) node _T_809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_808) node _T_810 = bits(_T_809, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_810 node _T_811 = eq(UInt<3>(0h7), idx_6) when _T_811 : node _T_812 = shl(UInt<3>(0h6), 3) node _T_813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_812) node _T_814 = bits(_T_813, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_814 node _T_815 = eq(UInt<4>(0h8), idx_6) when _T_815 : node _T_816 = shl(UInt<3>(0h6), 3) node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816) node _T_818 = bits(_T_817, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_818 node _T_819 = eq(UInt<4>(0h9), idx_6) when _T_819 : node _T_820 = shl(UInt<3>(0h6), 3) node _T_821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_820) node _T_822 = bits(_T_821, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_822 node _T_823 = eq(UInt<4>(0ha), idx_6) when _T_823 : node _T_824 = shl(UInt<3>(0h6), 3) node _T_825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_824) node _T_826 = bits(_T_825, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_826 node _T_827 = eq(UInt<4>(0hb), idx_6) when _T_827 : node _T_828 = shl(UInt<3>(0h6), 3) node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828) node _T_830 = bits(_T_829, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_830 node _T_831 = eq(UInt<4>(0hc), idx_6) when _T_831 : node _T_832 = shl(UInt<3>(0h6), 3) node _T_833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_832) node _T_834 = bits(_T_833, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_834 node _T_835 = eq(UInt<4>(0hd), idx_6) when _T_835 : node _T_836 = shl(UInt<3>(0h6), 3) node _T_837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_836) node _T_838 = bits(_T_837, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_838 node _T_839 = eq(UInt<4>(0he), idx_6) when _T_839 : node _T_840 = shl(UInt<3>(0h6), 3) node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840) node _T_842 = bits(_T_841, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_842 node _T_843 = eq(UInt<4>(0hf), idx_6) when _T_843 : node _T_844 = shl(UInt<3>(0h6), 3) node _T_845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_844) node _T_846 = bits(_T_845, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_846 node _T_847 = eq(UInt<5>(0h10), idx_6) when _T_847 : node _T_848 = shl(UInt<3>(0h6), 3) node _T_849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_848) node _T_850 = bits(_T_849, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_850 node _T_851 = eq(UInt<5>(0h11), idx_6) when _T_851 : node _T_852 = shl(UInt<3>(0h6), 3) node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852) node _T_854 = bits(_T_853, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_854 node _T_855 = eq(UInt<5>(0h12), idx_6) when _T_855 : node _T_856 = shl(UInt<3>(0h6), 3) node _T_857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_856) node _T_858 = bits(_T_857, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_858 node _T_859 = eq(UInt<5>(0h13), idx_6) when _T_859 : node _T_860 = shl(UInt<3>(0h6), 3) node _T_861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_860) node _T_862 = bits(_T_861, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_862 node _T_863 = eq(UInt<5>(0h14), idx_6) when _T_863 : node _T_864 = shl(UInt<3>(0h6), 3) node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864) node _T_866 = bits(_T_865, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_866 node _T_867 = eq(UInt<5>(0h15), idx_6) when _T_867 : node _T_868 = shl(UInt<3>(0h6), 3) node _T_869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_868) node _T_870 = bits(_T_869, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_870 node _T_871 = eq(UInt<5>(0h16), idx_6) when _T_871 : node _T_872 = shl(UInt<3>(0h6), 3) node _T_873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_872) node _T_874 = bits(_T_873, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_874 node _T_875 = eq(UInt<5>(0h17), idx_6) when _T_875 : node _T_876 = shl(UInt<3>(0h6), 3) node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876) node _T_878 = bits(_T_877, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_878 node _T_879 = eq(UInt<5>(0h18), idx_6) when _T_879 : node _T_880 = shl(UInt<3>(0h6), 3) node _T_881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_880) node _T_882 = bits(_T_881, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_882 node _T_883 = eq(UInt<5>(0h19), idx_6) when _T_883 : node _T_884 = shl(UInt<3>(0h6), 3) node _T_885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_884) node _T_886 = bits(_T_885, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_886 node _T_887 = eq(UInt<5>(0h1a), idx_6) when _T_887 : node _T_888 = shl(UInt<3>(0h6), 3) node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888) node _T_890 = bits(_T_889, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_890 node _T_891 = eq(UInt<5>(0h1b), idx_6) when _T_891 : node _T_892 = shl(UInt<3>(0h6), 3) node _T_893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_892) node _T_894 = bits(_T_893, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_894 node _T_895 = eq(UInt<5>(0h1c), idx_6) when _T_895 : node _T_896 = shl(UInt<3>(0h6), 3) node _T_897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_896) node _T_898 = bits(_T_897, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_898 node _T_899 = eq(UInt<5>(0h1d), idx_6) when _T_899 : node _T_900 = shl(UInt<3>(0h6), 3) node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900) node _T_902 = bits(_T_901, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_902 node _T_903 = eq(UInt<5>(0h1e), idx_6) when _T_903 : node _T_904 = shl(UInt<3>(0h6), 3) node _T_905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_904) node _T_906 = bits(_T_905, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_906 node _T_907 = eq(UInt<5>(0h1f), idx_6) when _T_907 : node _T_908 = shl(UInt<3>(0h6), 3) node _T_909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_908) node _T_910 = bits(_T_909, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_910 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_911 = eq(UInt<1>(0h0), idx_7) when _T_911 : node _T_912 = shl(UInt<3>(0h7), 3) node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912) node _T_914 = bits(_T_913, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_914 node _T_915 = eq(UInt<1>(0h1), idx_7) when _T_915 : node _T_916 = shl(UInt<3>(0h7), 3) node _T_917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_916) node _T_918 = bits(_T_917, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_918 node _T_919 = eq(UInt<2>(0h2), idx_7) when _T_919 : node _T_920 = shl(UInt<3>(0h7), 3) node _T_921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_920) node _T_922 = bits(_T_921, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_922 node _T_923 = eq(UInt<2>(0h3), idx_7) when _T_923 : node _T_924 = shl(UInt<3>(0h7), 3) node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924) node _T_926 = bits(_T_925, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_926 node _T_927 = eq(UInt<3>(0h4), idx_7) when _T_927 : node _T_928 = shl(UInt<3>(0h7), 3) node _T_929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_928) node _T_930 = bits(_T_929, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_930 node _T_931 = eq(UInt<3>(0h5), idx_7) when _T_931 : node _T_932 = shl(UInt<3>(0h7), 3) node _T_933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_932) node _T_934 = bits(_T_933, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_934 node _T_935 = eq(UInt<3>(0h6), idx_7) when _T_935 : node _T_936 = shl(UInt<3>(0h7), 3) node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936) node _T_938 = bits(_T_937, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_938 node _T_939 = eq(UInt<3>(0h7), idx_7) when _T_939 : node _T_940 = shl(UInt<3>(0h7), 3) node _T_941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_940) node _T_942 = bits(_T_941, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_942 node _T_943 = eq(UInt<4>(0h8), idx_7) when _T_943 : node _T_944 = shl(UInt<3>(0h7), 3) node _T_945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_944) node _T_946 = bits(_T_945, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_946 node _T_947 = eq(UInt<4>(0h9), idx_7) when _T_947 : node _T_948 = shl(UInt<3>(0h7), 3) node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948) node _T_950 = bits(_T_949, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_950 node _T_951 = eq(UInt<4>(0ha), idx_7) when _T_951 : node _T_952 = shl(UInt<3>(0h7), 3) node _T_953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_952) node _T_954 = bits(_T_953, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_954 node _T_955 = eq(UInt<4>(0hb), idx_7) when _T_955 : node _T_956 = shl(UInt<3>(0h7), 3) node _T_957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_956) node _T_958 = bits(_T_957, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_958 node _T_959 = eq(UInt<4>(0hc), idx_7) when _T_959 : node _T_960 = shl(UInt<3>(0h7), 3) node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960) node _T_962 = bits(_T_961, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_962 node _T_963 = eq(UInt<4>(0hd), idx_7) when _T_963 : node _T_964 = shl(UInt<3>(0h7), 3) node _T_965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_964) node _T_966 = bits(_T_965, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_966 node _T_967 = eq(UInt<4>(0he), idx_7) when _T_967 : node _T_968 = shl(UInt<3>(0h7), 3) node _T_969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_968) node _T_970 = bits(_T_969, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_970 node _T_971 = eq(UInt<4>(0hf), idx_7) when _T_971 : node _T_972 = shl(UInt<3>(0h7), 3) node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972) node _T_974 = bits(_T_973, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_974 node _T_975 = eq(UInt<5>(0h10), idx_7) when _T_975 : node _T_976 = shl(UInt<3>(0h7), 3) node _T_977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_976) node _T_978 = bits(_T_977, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_978 node _T_979 = eq(UInt<5>(0h11), idx_7) when _T_979 : node _T_980 = shl(UInt<3>(0h7), 3) node _T_981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_980) node _T_982 = bits(_T_981, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_982 node _T_983 = eq(UInt<5>(0h12), idx_7) when _T_983 : node _T_984 = shl(UInt<3>(0h7), 3) node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984) node _T_986 = bits(_T_985, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_986 node _T_987 = eq(UInt<5>(0h13), idx_7) when _T_987 : node _T_988 = shl(UInt<3>(0h7), 3) node _T_989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_988) node _T_990 = bits(_T_989, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_990 node _T_991 = eq(UInt<5>(0h14), idx_7) when _T_991 : node _T_992 = shl(UInt<3>(0h7), 3) node _T_993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_992) node _T_994 = bits(_T_993, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_994 node _T_995 = eq(UInt<5>(0h15), idx_7) when _T_995 : node _T_996 = shl(UInt<3>(0h7), 3) node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996) node _T_998 = bits(_T_997, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_998 node _T_999 = eq(UInt<5>(0h16), idx_7) when _T_999 : node _T_1000 = shl(UInt<3>(0h7), 3) node _T_1001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1000) node _T_1002 = bits(_T_1001, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1002 node _T_1003 = eq(UInt<5>(0h17), idx_7) when _T_1003 : node _T_1004 = shl(UInt<3>(0h7), 3) node _T_1005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1004) node _T_1006 = bits(_T_1005, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1006 node _T_1007 = eq(UInt<5>(0h18), idx_7) when _T_1007 : node _T_1008 = shl(UInt<3>(0h7), 3) node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008) node _T_1010 = bits(_T_1009, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1010 node _T_1011 = eq(UInt<5>(0h19), idx_7) when _T_1011 : node _T_1012 = shl(UInt<3>(0h7), 3) node _T_1013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1012) node _T_1014 = bits(_T_1013, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1014 node _T_1015 = eq(UInt<5>(0h1a), idx_7) when _T_1015 : node _T_1016 = shl(UInt<3>(0h7), 3) node _T_1017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1016) node _T_1018 = bits(_T_1017, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1018 node _T_1019 = eq(UInt<5>(0h1b), idx_7) when _T_1019 : node _T_1020 = shl(UInt<3>(0h7), 3) node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020) node _T_1022 = bits(_T_1021, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1022 node _T_1023 = eq(UInt<5>(0h1c), idx_7) when _T_1023 : node _T_1024 = shl(UInt<3>(0h7), 3) node _T_1025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1024) node _T_1026 = bits(_T_1025, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1026 node _T_1027 = eq(UInt<5>(0h1d), idx_7) when _T_1027 : node _T_1028 = shl(UInt<3>(0h7), 3) node _T_1029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1028) node _T_1030 = bits(_T_1029, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1030 node _T_1031 = eq(UInt<5>(0h1e), idx_7) when _T_1031 : node _T_1032 = shl(UInt<3>(0h7), 3) node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032) node _T_1034 = bits(_T_1033, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1034 node _T_1035 = eq(UInt<5>(0h1f), idx_7) when _T_1035 : node _T_1036 = shl(UInt<3>(0h7), 3) node _T_1037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1036) node _T_1038 = bits(_T_1037, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1038 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_1039 = eq(UInt<1>(0h0), idx_8) when _T_1039 : node _T_1040 = shl(UInt<4>(0h8), 3) node _T_1041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1040) node _T_1042 = bits(_T_1041, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1042 node _T_1043 = eq(UInt<1>(0h1), idx_8) when _T_1043 : node _T_1044 = shl(UInt<4>(0h8), 3) node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044) node _T_1046 = bits(_T_1045, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1046 node _T_1047 = eq(UInt<2>(0h2), idx_8) when _T_1047 : node _T_1048 = shl(UInt<4>(0h8), 3) node _T_1049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1048) node _T_1050 = bits(_T_1049, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1050 node _T_1051 = eq(UInt<2>(0h3), idx_8) when _T_1051 : node _T_1052 = shl(UInt<4>(0h8), 3) node _T_1053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1052) node _T_1054 = bits(_T_1053, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1054 node _T_1055 = eq(UInt<3>(0h4), idx_8) when _T_1055 : node _T_1056 = shl(UInt<4>(0h8), 3) node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056) node _T_1058 = bits(_T_1057, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1058 node _T_1059 = eq(UInt<3>(0h5), idx_8) when _T_1059 : node _T_1060 = shl(UInt<4>(0h8), 3) node _T_1061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1060) node _T_1062 = bits(_T_1061, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1062 node _T_1063 = eq(UInt<3>(0h6), idx_8) when _T_1063 : node _T_1064 = shl(UInt<4>(0h8), 3) node _T_1065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1064) node _T_1066 = bits(_T_1065, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1066 node _T_1067 = eq(UInt<3>(0h7), idx_8) when _T_1067 : node _T_1068 = shl(UInt<4>(0h8), 3) node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068) node _T_1070 = bits(_T_1069, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1070 node _T_1071 = eq(UInt<4>(0h8), idx_8) when _T_1071 : node _T_1072 = shl(UInt<4>(0h8), 3) node _T_1073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1072) node _T_1074 = bits(_T_1073, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1074 node _T_1075 = eq(UInt<4>(0h9), idx_8) when _T_1075 : node _T_1076 = shl(UInt<4>(0h8), 3) node _T_1077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1076) node _T_1078 = bits(_T_1077, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1078 node _T_1079 = eq(UInt<4>(0ha), idx_8) when _T_1079 : node _T_1080 = shl(UInt<4>(0h8), 3) node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080) node _T_1082 = bits(_T_1081, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1082 node _T_1083 = eq(UInt<4>(0hb), idx_8) when _T_1083 : node _T_1084 = shl(UInt<4>(0h8), 3) node _T_1085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1084) node _T_1086 = bits(_T_1085, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1086 node _T_1087 = eq(UInt<4>(0hc), idx_8) when _T_1087 : node _T_1088 = shl(UInt<4>(0h8), 3) node _T_1089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1088) node _T_1090 = bits(_T_1089, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1090 node _T_1091 = eq(UInt<4>(0hd), idx_8) when _T_1091 : node _T_1092 = shl(UInt<4>(0h8), 3) node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092) node _T_1094 = bits(_T_1093, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1094 node _T_1095 = eq(UInt<4>(0he), idx_8) when _T_1095 : node _T_1096 = shl(UInt<4>(0h8), 3) node _T_1097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1096) node _T_1098 = bits(_T_1097, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1098 node _T_1099 = eq(UInt<4>(0hf), idx_8) when _T_1099 : node _T_1100 = shl(UInt<4>(0h8), 3) node _T_1101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1100) node _T_1102 = bits(_T_1101, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1102 node _T_1103 = eq(UInt<5>(0h10), idx_8) when _T_1103 : node _T_1104 = shl(UInt<4>(0h8), 3) node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104) node _T_1106 = bits(_T_1105, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1106 node _T_1107 = eq(UInt<5>(0h11), idx_8) when _T_1107 : node _T_1108 = shl(UInt<4>(0h8), 3) node _T_1109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1108) node _T_1110 = bits(_T_1109, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1110 node _T_1111 = eq(UInt<5>(0h12), idx_8) when _T_1111 : node _T_1112 = shl(UInt<4>(0h8), 3) node _T_1113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1112) node _T_1114 = bits(_T_1113, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1114 node _T_1115 = eq(UInt<5>(0h13), idx_8) when _T_1115 : node _T_1116 = shl(UInt<4>(0h8), 3) node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116) node _T_1118 = bits(_T_1117, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1118 node _T_1119 = eq(UInt<5>(0h14), idx_8) when _T_1119 : node _T_1120 = shl(UInt<4>(0h8), 3) node _T_1121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1120) node _T_1122 = bits(_T_1121, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1122 node _T_1123 = eq(UInt<5>(0h15), idx_8) when _T_1123 : node _T_1124 = shl(UInt<4>(0h8), 3) node _T_1125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1124) node _T_1126 = bits(_T_1125, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1126 node _T_1127 = eq(UInt<5>(0h16), idx_8) when _T_1127 : node _T_1128 = shl(UInt<4>(0h8), 3) node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128) node _T_1130 = bits(_T_1129, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1130 node _T_1131 = eq(UInt<5>(0h17), idx_8) when _T_1131 : node _T_1132 = shl(UInt<4>(0h8), 3) node _T_1133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1132) node _T_1134 = bits(_T_1133, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1134 node _T_1135 = eq(UInt<5>(0h18), idx_8) when _T_1135 : node _T_1136 = shl(UInt<4>(0h8), 3) node _T_1137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1136) node _T_1138 = bits(_T_1137, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1138 node _T_1139 = eq(UInt<5>(0h19), idx_8) when _T_1139 : node _T_1140 = shl(UInt<4>(0h8), 3) node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140) node _T_1142 = bits(_T_1141, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1142 node _T_1143 = eq(UInt<5>(0h1a), idx_8) when _T_1143 : node _T_1144 = shl(UInt<4>(0h8), 3) node _T_1145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1144) node _T_1146 = bits(_T_1145, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1146 node _T_1147 = eq(UInt<5>(0h1b), idx_8) when _T_1147 : node _T_1148 = shl(UInt<4>(0h8), 3) node _T_1149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1148) node _T_1150 = bits(_T_1149, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1150 node _T_1151 = eq(UInt<5>(0h1c), idx_8) when _T_1151 : node _T_1152 = shl(UInt<4>(0h8), 3) node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152) node _T_1154 = bits(_T_1153, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1154 node _T_1155 = eq(UInt<5>(0h1d), idx_8) when _T_1155 : node _T_1156 = shl(UInt<4>(0h8), 3) node _T_1157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1156) node _T_1158 = bits(_T_1157, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1158 node _T_1159 = eq(UInt<5>(0h1e), idx_8) when _T_1159 : node _T_1160 = shl(UInt<4>(0h8), 3) node _T_1161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1160) node _T_1162 = bits(_T_1161, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1162 node _T_1163 = eq(UInt<5>(0h1f), idx_8) when _T_1163 : node _T_1164 = shl(UInt<4>(0h8), 3) node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164) node _T_1166 = bits(_T_1165, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1166 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_1167 = eq(UInt<1>(0h0), idx_9) when _T_1167 : node _T_1168 = shl(UInt<4>(0h9), 3) node _T_1169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1168) node _T_1170 = bits(_T_1169, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1170 node _T_1171 = eq(UInt<1>(0h1), idx_9) when _T_1171 : node _T_1172 = shl(UInt<4>(0h9), 3) node _T_1173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1172) node _T_1174 = bits(_T_1173, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1174 node _T_1175 = eq(UInt<2>(0h2), idx_9) when _T_1175 : node _T_1176 = shl(UInt<4>(0h9), 3) node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176) node _T_1178 = bits(_T_1177, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1178 node _T_1179 = eq(UInt<2>(0h3), idx_9) when _T_1179 : node _T_1180 = shl(UInt<4>(0h9), 3) node _T_1181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1180) node _T_1182 = bits(_T_1181, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1182 node _T_1183 = eq(UInt<3>(0h4), idx_9) when _T_1183 : node _T_1184 = shl(UInt<4>(0h9), 3) node _T_1185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1184) node _T_1186 = bits(_T_1185, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1186 node _T_1187 = eq(UInt<3>(0h5), idx_9) when _T_1187 : node _T_1188 = shl(UInt<4>(0h9), 3) node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188) node _T_1190 = bits(_T_1189, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1190 node _T_1191 = eq(UInt<3>(0h6), idx_9) when _T_1191 : node _T_1192 = shl(UInt<4>(0h9), 3) node _T_1193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1192) node _T_1194 = bits(_T_1193, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1194 node _T_1195 = eq(UInt<3>(0h7), idx_9) when _T_1195 : node _T_1196 = shl(UInt<4>(0h9), 3) node _T_1197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1196) node _T_1198 = bits(_T_1197, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1198 node _T_1199 = eq(UInt<4>(0h8), idx_9) when _T_1199 : node _T_1200 = shl(UInt<4>(0h9), 3) node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200) node _T_1202 = bits(_T_1201, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1202 node _T_1203 = eq(UInt<4>(0h9), idx_9) when _T_1203 : node _T_1204 = shl(UInt<4>(0h9), 3) node _T_1205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1204) node _T_1206 = bits(_T_1205, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1206 node _T_1207 = eq(UInt<4>(0ha), idx_9) when _T_1207 : node _T_1208 = shl(UInt<4>(0h9), 3) node _T_1209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1208) node _T_1210 = bits(_T_1209, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1210 node _T_1211 = eq(UInt<4>(0hb), idx_9) when _T_1211 : node _T_1212 = shl(UInt<4>(0h9), 3) node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212) node _T_1214 = bits(_T_1213, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1214 node _T_1215 = eq(UInt<4>(0hc), idx_9) when _T_1215 : node _T_1216 = shl(UInt<4>(0h9), 3) node _T_1217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1216) node _T_1218 = bits(_T_1217, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1218 node _T_1219 = eq(UInt<4>(0hd), idx_9) when _T_1219 : node _T_1220 = shl(UInt<4>(0h9), 3) node _T_1221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1220) node _T_1222 = bits(_T_1221, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1222 node _T_1223 = eq(UInt<4>(0he), idx_9) when _T_1223 : node _T_1224 = shl(UInt<4>(0h9), 3) node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224) node _T_1226 = bits(_T_1225, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1226 node _T_1227 = eq(UInt<4>(0hf), idx_9) when _T_1227 : node _T_1228 = shl(UInt<4>(0h9), 3) node _T_1229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1228) node _T_1230 = bits(_T_1229, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1230 node _T_1231 = eq(UInt<5>(0h10), idx_9) when _T_1231 : node _T_1232 = shl(UInt<4>(0h9), 3) node _T_1233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1232) node _T_1234 = bits(_T_1233, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1234 node _T_1235 = eq(UInt<5>(0h11), idx_9) when _T_1235 : node _T_1236 = shl(UInt<4>(0h9), 3) node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236) node _T_1238 = bits(_T_1237, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1238 node _T_1239 = eq(UInt<5>(0h12), idx_9) when _T_1239 : node _T_1240 = shl(UInt<4>(0h9), 3) node _T_1241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1240) node _T_1242 = bits(_T_1241, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1242 node _T_1243 = eq(UInt<5>(0h13), idx_9) when _T_1243 : node _T_1244 = shl(UInt<4>(0h9), 3) node _T_1245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1244) node _T_1246 = bits(_T_1245, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1246 node _T_1247 = eq(UInt<5>(0h14), idx_9) when _T_1247 : node _T_1248 = shl(UInt<4>(0h9), 3) node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248) node _T_1250 = bits(_T_1249, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1250 node _T_1251 = eq(UInt<5>(0h15), idx_9) when _T_1251 : node _T_1252 = shl(UInt<4>(0h9), 3) node _T_1253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1252) node _T_1254 = bits(_T_1253, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1254 node _T_1255 = eq(UInt<5>(0h16), idx_9) when _T_1255 : node _T_1256 = shl(UInt<4>(0h9), 3) node _T_1257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1256) node _T_1258 = bits(_T_1257, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1258 node _T_1259 = eq(UInt<5>(0h17), idx_9) when _T_1259 : node _T_1260 = shl(UInt<4>(0h9), 3) node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260) node _T_1262 = bits(_T_1261, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1262 node _T_1263 = eq(UInt<5>(0h18), idx_9) when _T_1263 : node _T_1264 = shl(UInt<4>(0h9), 3) node _T_1265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1264) node _T_1266 = bits(_T_1265, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1266 node _T_1267 = eq(UInt<5>(0h19), idx_9) when _T_1267 : node _T_1268 = shl(UInt<4>(0h9), 3) node _T_1269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1268) node _T_1270 = bits(_T_1269, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1270 node _T_1271 = eq(UInt<5>(0h1a), idx_9) when _T_1271 : node _T_1272 = shl(UInt<4>(0h9), 3) node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272) node _T_1274 = bits(_T_1273, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1274 node _T_1275 = eq(UInt<5>(0h1b), idx_9) when _T_1275 : node _T_1276 = shl(UInt<4>(0h9), 3) node _T_1277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1276) node _T_1278 = bits(_T_1277, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1278 node _T_1279 = eq(UInt<5>(0h1c), idx_9) when _T_1279 : node _T_1280 = shl(UInt<4>(0h9), 3) node _T_1281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1280) node _T_1282 = bits(_T_1281, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1282 node _T_1283 = eq(UInt<5>(0h1d), idx_9) when _T_1283 : node _T_1284 = shl(UInt<4>(0h9), 3) node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284) node _T_1286 = bits(_T_1285, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1286 node _T_1287 = eq(UInt<5>(0h1e), idx_9) when _T_1287 : node _T_1288 = shl(UInt<4>(0h9), 3) node _T_1289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1288) node _T_1290 = bits(_T_1289, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1290 node _T_1291 = eq(UInt<5>(0h1f), idx_9) when _T_1291 : node _T_1292 = shl(UInt<4>(0h9), 3) node _T_1293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1292) node _T_1294 = bits(_T_1293, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1294 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_1295 = eq(UInt<1>(0h0), idx_10) when _T_1295 : node _T_1296 = shl(UInt<4>(0ha), 3) node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296) node _T_1298 = bits(_T_1297, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1298 node _T_1299 = eq(UInt<1>(0h1), idx_10) when _T_1299 : node _T_1300 = shl(UInt<4>(0ha), 3) node _T_1301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1300) node _T_1302 = bits(_T_1301, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1302 node _T_1303 = eq(UInt<2>(0h2), idx_10) when _T_1303 : node _T_1304 = shl(UInt<4>(0ha), 3) node _T_1305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1304) node _T_1306 = bits(_T_1305, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1306 node _T_1307 = eq(UInt<2>(0h3), idx_10) when _T_1307 : node _T_1308 = shl(UInt<4>(0ha), 3) node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308) node _T_1310 = bits(_T_1309, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1310 node _T_1311 = eq(UInt<3>(0h4), idx_10) when _T_1311 : node _T_1312 = shl(UInt<4>(0ha), 3) node _T_1313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1312) node _T_1314 = bits(_T_1313, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1314 node _T_1315 = eq(UInt<3>(0h5), idx_10) when _T_1315 : node _T_1316 = shl(UInt<4>(0ha), 3) node _T_1317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1316) node _T_1318 = bits(_T_1317, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1318 node _T_1319 = eq(UInt<3>(0h6), idx_10) when _T_1319 : node _T_1320 = shl(UInt<4>(0ha), 3) node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320) node _T_1322 = bits(_T_1321, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1322 node _T_1323 = eq(UInt<3>(0h7), idx_10) when _T_1323 : node _T_1324 = shl(UInt<4>(0ha), 3) node _T_1325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1324) node _T_1326 = bits(_T_1325, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1326 node _T_1327 = eq(UInt<4>(0h8), idx_10) when _T_1327 : node _T_1328 = shl(UInt<4>(0ha), 3) node _T_1329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1328) node _T_1330 = bits(_T_1329, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1330 node _T_1331 = eq(UInt<4>(0h9), idx_10) when _T_1331 : node _T_1332 = shl(UInt<4>(0ha), 3) node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332) node _T_1334 = bits(_T_1333, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1334 node _T_1335 = eq(UInt<4>(0ha), idx_10) when _T_1335 : node _T_1336 = shl(UInt<4>(0ha), 3) node _T_1337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1336) node _T_1338 = bits(_T_1337, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1338 node _T_1339 = eq(UInt<4>(0hb), idx_10) when _T_1339 : node _T_1340 = shl(UInt<4>(0ha), 3) node _T_1341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1340) node _T_1342 = bits(_T_1341, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1342 node _T_1343 = eq(UInt<4>(0hc), idx_10) when _T_1343 : node _T_1344 = shl(UInt<4>(0ha), 3) node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344) node _T_1346 = bits(_T_1345, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1346 node _T_1347 = eq(UInt<4>(0hd), idx_10) when _T_1347 : node _T_1348 = shl(UInt<4>(0ha), 3) node _T_1349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1348) node _T_1350 = bits(_T_1349, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1350 node _T_1351 = eq(UInt<4>(0he), idx_10) when _T_1351 : node _T_1352 = shl(UInt<4>(0ha), 3) node _T_1353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1352) node _T_1354 = bits(_T_1353, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1354 node _T_1355 = eq(UInt<4>(0hf), idx_10) when _T_1355 : node _T_1356 = shl(UInt<4>(0ha), 3) node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356) node _T_1358 = bits(_T_1357, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1358 node _T_1359 = eq(UInt<5>(0h10), idx_10) when _T_1359 : node _T_1360 = shl(UInt<4>(0ha), 3) node _T_1361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1360) node _T_1362 = bits(_T_1361, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1362 node _T_1363 = eq(UInt<5>(0h11), idx_10) when _T_1363 : node _T_1364 = shl(UInt<4>(0ha), 3) node _T_1365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1364) node _T_1366 = bits(_T_1365, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1366 node _T_1367 = eq(UInt<5>(0h12), idx_10) when _T_1367 : node _T_1368 = shl(UInt<4>(0ha), 3) node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368) node _T_1370 = bits(_T_1369, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1370 node _T_1371 = eq(UInt<5>(0h13), idx_10) when _T_1371 : node _T_1372 = shl(UInt<4>(0ha), 3) node _T_1373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1372) node _T_1374 = bits(_T_1373, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1374 node _T_1375 = eq(UInt<5>(0h14), idx_10) when _T_1375 : node _T_1376 = shl(UInt<4>(0ha), 3) node _T_1377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1376) node _T_1378 = bits(_T_1377, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1378 node _T_1379 = eq(UInt<5>(0h15), idx_10) when _T_1379 : node _T_1380 = shl(UInt<4>(0ha), 3) node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380) node _T_1382 = bits(_T_1381, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1382 node _T_1383 = eq(UInt<5>(0h16), idx_10) when _T_1383 : node _T_1384 = shl(UInt<4>(0ha), 3) node _T_1385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1384) node _T_1386 = bits(_T_1385, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1386 node _T_1387 = eq(UInt<5>(0h17), idx_10) when _T_1387 : node _T_1388 = shl(UInt<4>(0ha), 3) node _T_1389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1388) node _T_1390 = bits(_T_1389, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1390 node _T_1391 = eq(UInt<5>(0h18), idx_10) when _T_1391 : node _T_1392 = shl(UInt<4>(0ha), 3) node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392) node _T_1394 = bits(_T_1393, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1394 node _T_1395 = eq(UInt<5>(0h19), idx_10) when _T_1395 : node _T_1396 = shl(UInt<4>(0ha), 3) node _T_1397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1396) node _T_1398 = bits(_T_1397, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1398 node _T_1399 = eq(UInt<5>(0h1a), idx_10) when _T_1399 : node _T_1400 = shl(UInt<4>(0ha), 3) node _T_1401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1400) node _T_1402 = bits(_T_1401, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1402 node _T_1403 = eq(UInt<5>(0h1b), idx_10) when _T_1403 : node _T_1404 = shl(UInt<4>(0ha), 3) node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404) node _T_1406 = bits(_T_1405, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1406 node _T_1407 = eq(UInt<5>(0h1c), idx_10) when _T_1407 : node _T_1408 = shl(UInt<4>(0ha), 3) node _T_1409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1408) node _T_1410 = bits(_T_1409, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1410 node _T_1411 = eq(UInt<5>(0h1d), idx_10) when _T_1411 : node _T_1412 = shl(UInt<4>(0ha), 3) node _T_1413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1412) node _T_1414 = bits(_T_1413, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1414 node _T_1415 = eq(UInt<5>(0h1e), idx_10) when _T_1415 : node _T_1416 = shl(UInt<4>(0ha), 3) node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416) node _T_1418 = bits(_T_1417, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1418 node _T_1419 = eq(UInt<5>(0h1f), idx_10) when _T_1419 : node _T_1420 = shl(UInt<4>(0ha), 3) node _T_1421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1420) node _T_1422 = bits(_T_1421, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1422 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_1423 = eq(UInt<1>(0h0), idx_11) when _T_1423 : node _T_1424 = shl(UInt<4>(0hb), 3) node _T_1425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1424) node _T_1426 = bits(_T_1425, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1426 node _T_1427 = eq(UInt<1>(0h1), idx_11) when _T_1427 : node _T_1428 = shl(UInt<4>(0hb), 3) node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428) node _T_1430 = bits(_T_1429, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1430 node _T_1431 = eq(UInt<2>(0h2), idx_11) when _T_1431 : node _T_1432 = shl(UInt<4>(0hb), 3) node _T_1433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1432) node _T_1434 = bits(_T_1433, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1434 node _T_1435 = eq(UInt<2>(0h3), idx_11) when _T_1435 : node _T_1436 = shl(UInt<4>(0hb), 3) node _T_1437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1436) node _T_1438 = bits(_T_1437, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1438 node _T_1439 = eq(UInt<3>(0h4), idx_11) when _T_1439 : node _T_1440 = shl(UInt<4>(0hb), 3) node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440) node _T_1442 = bits(_T_1441, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1442 node _T_1443 = eq(UInt<3>(0h5), idx_11) when _T_1443 : node _T_1444 = shl(UInt<4>(0hb), 3) node _T_1445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1444) node _T_1446 = bits(_T_1445, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1446 node _T_1447 = eq(UInt<3>(0h6), idx_11) when _T_1447 : node _T_1448 = shl(UInt<4>(0hb), 3) node _T_1449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1448) node _T_1450 = bits(_T_1449, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1450 node _T_1451 = eq(UInt<3>(0h7), idx_11) when _T_1451 : node _T_1452 = shl(UInt<4>(0hb), 3) node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452) node _T_1454 = bits(_T_1453, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1454 node _T_1455 = eq(UInt<4>(0h8), idx_11) when _T_1455 : node _T_1456 = shl(UInt<4>(0hb), 3) node _T_1457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1456) node _T_1458 = bits(_T_1457, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1458 node _T_1459 = eq(UInt<4>(0h9), idx_11) when _T_1459 : node _T_1460 = shl(UInt<4>(0hb), 3) node _T_1461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1460) node _T_1462 = bits(_T_1461, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1462 node _T_1463 = eq(UInt<4>(0ha), idx_11) when _T_1463 : node _T_1464 = shl(UInt<4>(0hb), 3) node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464) node _T_1466 = bits(_T_1465, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1466 node _T_1467 = eq(UInt<4>(0hb), idx_11) when _T_1467 : node _T_1468 = shl(UInt<4>(0hb), 3) node _T_1469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1468) node _T_1470 = bits(_T_1469, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1470 node _T_1471 = eq(UInt<4>(0hc), idx_11) when _T_1471 : node _T_1472 = shl(UInt<4>(0hb), 3) node _T_1473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1472) node _T_1474 = bits(_T_1473, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1474 node _T_1475 = eq(UInt<4>(0hd), idx_11) when _T_1475 : node _T_1476 = shl(UInt<4>(0hb), 3) node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476) node _T_1478 = bits(_T_1477, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1478 node _T_1479 = eq(UInt<4>(0he), idx_11) when _T_1479 : node _T_1480 = shl(UInt<4>(0hb), 3) node _T_1481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1480) node _T_1482 = bits(_T_1481, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1482 node _T_1483 = eq(UInt<4>(0hf), idx_11) when _T_1483 : node _T_1484 = shl(UInt<4>(0hb), 3) node _T_1485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1484) node _T_1486 = bits(_T_1485, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1486 node _T_1487 = eq(UInt<5>(0h10), idx_11) when _T_1487 : node _T_1488 = shl(UInt<4>(0hb), 3) node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488) node _T_1490 = bits(_T_1489, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1490 node _T_1491 = eq(UInt<5>(0h11), idx_11) when _T_1491 : node _T_1492 = shl(UInt<4>(0hb), 3) node _T_1493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1492) node _T_1494 = bits(_T_1493, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1494 node _T_1495 = eq(UInt<5>(0h12), idx_11) when _T_1495 : node _T_1496 = shl(UInt<4>(0hb), 3) node _T_1497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1496) node _T_1498 = bits(_T_1497, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1498 node _T_1499 = eq(UInt<5>(0h13), idx_11) when _T_1499 : node _T_1500 = shl(UInt<4>(0hb), 3) node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500) node _T_1502 = bits(_T_1501, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1502 node _T_1503 = eq(UInt<5>(0h14), idx_11) when _T_1503 : node _T_1504 = shl(UInt<4>(0hb), 3) node _T_1505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1504) node _T_1506 = bits(_T_1505, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1506 node _T_1507 = eq(UInt<5>(0h15), idx_11) when _T_1507 : node _T_1508 = shl(UInt<4>(0hb), 3) node _T_1509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1508) node _T_1510 = bits(_T_1509, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1510 node _T_1511 = eq(UInt<5>(0h16), idx_11) when _T_1511 : node _T_1512 = shl(UInt<4>(0hb), 3) node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512) node _T_1514 = bits(_T_1513, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1514 node _T_1515 = eq(UInt<5>(0h17), idx_11) when _T_1515 : node _T_1516 = shl(UInt<4>(0hb), 3) node _T_1517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1516) node _T_1518 = bits(_T_1517, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1518 node _T_1519 = eq(UInt<5>(0h18), idx_11) when _T_1519 : node _T_1520 = shl(UInt<4>(0hb), 3) node _T_1521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1520) node _T_1522 = bits(_T_1521, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1522 node _T_1523 = eq(UInt<5>(0h19), idx_11) when _T_1523 : node _T_1524 = shl(UInt<4>(0hb), 3) node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524) node _T_1526 = bits(_T_1525, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1526 node _T_1527 = eq(UInt<5>(0h1a), idx_11) when _T_1527 : node _T_1528 = shl(UInt<4>(0hb), 3) node _T_1529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1528) node _T_1530 = bits(_T_1529, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1530 node _T_1531 = eq(UInt<5>(0h1b), idx_11) when _T_1531 : node _T_1532 = shl(UInt<4>(0hb), 3) node _T_1533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1532) node _T_1534 = bits(_T_1533, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1534 node _T_1535 = eq(UInt<5>(0h1c), idx_11) when _T_1535 : node _T_1536 = shl(UInt<4>(0hb), 3) node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536) node _T_1538 = bits(_T_1537, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1538 node _T_1539 = eq(UInt<5>(0h1d), idx_11) when _T_1539 : node _T_1540 = shl(UInt<4>(0hb), 3) node _T_1541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1540) node _T_1542 = bits(_T_1541, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1542 node _T_1543 = eq(UInt<5>(0h1e), idx_11) when _T_1543 : node _T_1544 = shl(UInt<4>(0hb), 3) node _T_1545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1544) node _T_1546 = bits(_T_1545, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1546 node _T_1547 = eq(UInt<5>(0h1f), idx_11) when _T_1547 : node _T_1548 = shl(UInt<4>(0hb), 3) node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548) node _T_1550 = bits(_T_1549, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1550 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_1551 = eq(UInt<1>(0h0), idx_12) when _T_1551 : node _T_1552 = shl(UInt<4>(0hc), 3) node _T_1553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1552) node _T_1554 = bits(_T_1553, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1554 node _T_1555 = eq(UInt<1>(0h1), idx_12) when _T_1555 : node _T_1556 = shl(UInt<4>(0hc), 3) node _T_1557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1556) node _T_1558 = bits(_T_1557, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1558 node _T_1559 = eq(UInt<2>(0h2), idx_12) when _T_1559 : node _T_1560 = shl(UInt<4>(0hc), 3) node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560) node _T_1562 = bits(_T_1561, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1562 node _T_1563 = eq(UInt<2>(0h3), idx_12) when _T_1563 : node _T_1564 = shl(UInt<4>(0hc), 3) node _T_1565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1564) node _T_1566 = bits(_T_1565, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1566 node _T_1567 = eq(UInt<3>(0h4), idx_12) when _T_1567 : node _T_1568 = shl(UInt<4>(0hc), 3) node _T_1569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1568) node _T_1570 = bits(_T_1569, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1570 node _T_1571 = eq(UInt<3>(0h5), idx_12) when _T_1571 : node _T_1572 = shl(UInt<4>(0hc), 3) node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572) node _T_1574 = bits(_T_1573, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1574 node _T_1575 = eq(UInt<3>(0h6), idx_12) when _T_1575 : node _T_1576 = shl(UInt<4>(0hc), 3) node _T_1577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1576) node _T_1578 = bits(_T_1577, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1578 node _T_1579 = eq(UInt<3>(0h7), idx_12) when _T_1579 : node _T_1580 = shl(UInt<4>(0hc), 3) node _T_1581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1580) node _T_1582 = bits(_T_1581, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1582 node _T_1583 = eq(UInt<4>(0h8), idx_12) when _T_1583 : node _T_1584 = shl(UInt<4>(0hc), 3) node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584) node _T_1586 = bits(_T_1585, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1586 node _T_1587 = eq(UInt<4>(0h9), idx_12) when _T_1587 : node _T_1588 = shl(UInt<4>(0hc), 3) node _T_1589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1588) node _T_1590 = bits(_T_1589, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1590 node _T_1591 = eq(UInt<4>(0ha), idx_12) when _T_1591 : node _T_1592 = shl(UInt<4>(0hc), 3) node _T_1593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1592) node _T_1594 = bits(_T_1593, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1594 node _T_1595 = eq(UInt<4>(0hb), idx_12) when _T_1595 : node _T_1596 = shl(UInt<4>(0hc), 3) node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596) node _T_1598 = bits(_T_1597, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1598 node _T_1599 = eq(UInt<4>(0hc), idx_12) when _T_1599 : node _T_1600 = shl(UInt<4>(0hc), 3) node _T_1601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1600) node _T_1602 = bits(_T_1601, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1602 node _T_1603 = eq(UInt<4>(0hd), idx_12) when _T_1603 : node _T_1604 = shl(UInt<4>(0hc), 3) node _T_1605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1604) node _T_1606 = bits(_T_1605, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1606 node _T_1607 = eq(UInt<4>(0he), idx_12) when _T_1607 : node _T_1608 = shl(UInt<4>(0hc), 3) node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608) node _T_1610 = bits(_T_1609, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1610 node _T_1611 = eq(UInt<4>(0hf), idx_12) when _T_1611 : node _T_1612 = shl(UInt<4>(0hc), 3) node _T_1613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1612) node _T_1614 = bits(_T_1613, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1614 node _T_1615 = eq(UInt<5>(0h10), idx_12) when _T_1615 : node _T_1616 = shl(UInt<4>(0hc), 3) node _T_1617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1616) node _T_1618 = bits(_T_1617, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1618 node _T_1619 = eq(UInt<5>(0h11), idx_12) when _T_1619 : node _T_1620 = shl(UInt<4>(0hc), 3) node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620) node _T_1622 = bits(_T_1621, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1622 node _T_1623 = eq(UInt<5>(0h12), idx_12) when _T_1623 : node _T_1624 = shl(UInt<4>(0hc), 3) node _T_1625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1624) node _T_1626 = bits(_T_1625, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1626 node _T_1627 = eq(UInt<5>(0h13), idx_12) when _T_1627 : node _T_1628 = shl(UInt<4>(0hc), 3) node _T_1629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1628) node _T_1630 = bits(_T_1629, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1630 node _T_1631 = eq(UInt<5>(0h14), idx_12) when _T_1631 : node _T_1632 = shl(UInt<4>(0hc), 3) node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632) node _T_1634 = bits(_T_1633, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1634 node _T_1635 = eq(UInt<5>(0h15), idx_12) when _T_1635 : node _T_1636 = shl(UInt<4>(0hc), 3) node _T_1637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1636) node _T_1638 = bits(_T_1637, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1638 node _T_1639 = eq(UInt<5>(0h16), idx_12) when _T_1639 : node _T_1640 = shl(UInt<4>(0hc), 3) node _T_1641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1640) node _T_1642 = bits(_T_1641, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1642 node _T_1643 = eq(UInt<5>(0h17), idx_12) when _T_1643 : node _T_1644 = shl(UInt<4>(0hc), 3) node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644) node _T_1646 = bits(_T_1645, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1646 node _T_1647 = eq(UInt<5>(0h18), idx_12) when _T_1647 : node _T_1648 = shl(UInt<4>(0hc), 3) node _T_1649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1648) node _T_1650 = bits(_T_1649, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1650 node _T_1651 = eq(UInt<5>(0h19), idx_12) when _T_1651 : node _T_1652 = shl(UInt<4>(0hc), 3) node _T_1653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1652) node _T_1654 = bits(_T_1653, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1654 node _T_1655 = eq(UInt<5>(0h1a), idx_12) when _T_1655 : node _T_1656 = shl(UInt<4>(0hc), 3) node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656) node _T_1658 = bits(_T_1657, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1658 node _T_1659 = eq(UInt<5>(0h1b), idx_12) when _T_1659 : node _T_1660 = shl(UInt<4>(0hc), 3) node _T_1661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1660) node _T_1662 = bits(_T_1661, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1662 node _T_1663 = eq(UInt<5>(0h1c), idx_12) when _T_1663 : node _T_1664 = shl(UInt<4>(0hc), 3) node _T_1665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1664) node _T_1666 = bits(_T_1665, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1666 node _T_1667 = eq(UInt<5>(0h1d), idx_12) when _T_1667 : node _T_1668 = shl(UInt<4>(0hc), 3) node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668) node _T_1670 = bits(_T_1669, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1670 node _T_1671 = eq(UInt<5>(0h1e), idx_12) when _T_1671 : node _T_1672 = shl(UInt<4>(0hc), 3) node _T_1673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1672) node _T_1674 = bits(_T_1673, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1674 node _T_1675 = eq(UInt<5>(0h1f), idx_12) when _T_1675 : node _T_1676 = shl(UInt<4>(0hc), 3) node _T_1677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1676) node _T_1678 = bits(_T_1677, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1678 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_1679 = eq(UInt<1>(0h0), idx_13) when _T_1679 : node _T_1680 = shl(UInt<4>(0hd), 3) node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680) node _T_1682 = bits(_T_1681, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1682 node _T_1683 = eq(UInt<1>(0h1), idx_13) when _T_1683 : node _T_1684 = shl(UInt<4>(0hd), 3) node _T_1685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1684) node _T_1686 = bits(_T_1685, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1686 node _T_1687 = eq(UInt<2>(0h2), idx_13) when _T_1687 : node _T_1688 = shl(UInt<4>(0hd), 3) node _T_1689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1688) node _T_1690 = bits(_T_1689, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1690 node _T_1691 = eq(UInt<2>(0h3), idx_13) when _T_1691 : node _T_1692 = shl(UInt<4>(0hd), 3) node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692) node _T_1694 = bits(_T_1693, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1694 node _T_1695 = eq(UInt<3>(0h4), idx_13) when _T_1695 : node _T_1696 = shl(UInt<4>(0hd), 3) node _T_1697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1696) node _T_1698 = bits(_T_1697, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1698 node _T_1699 = eq(UInt<3>(0h5), idx_13) when _T_1699 : node _T_1700 = shl(UInt<4>(0hd), 3) node _T_1701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1700) node _T_1702 = bits(_T_1701, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1702 node _T_1703 = eq(UInt<3>(0h6), idx_13) when _T_1703 : node _T_1704 = shl(UInt<4>(0hd), 3) node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704) node _T_1706 = bits(_T_1705, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1706 node _T_1707 = eq(UInt<3>(0h7), idx_13) when _T_1707 : node _T_1708 = shl(UInt<4>(0hd), 3) node _T_1709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1708) node _T_1710 = bits(_T_1709, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1710 node _T_1711 = eq(UInt<4>(0h8), idx_13) when _T_1711 : node _T_1712 = shl(UInt<4>(0hd), 3) node _T_1713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1712) node _T_1714 = bits(_T_1713, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1714 node _T_1715 = eq(UInt<4>(0h9), idx_13) when _T_1715 : node _T_1716 = shl(UInt<4>(0hd), 3) node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716) node _T_1718 = bits(_T_1717, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1718 node _T_1719 = eq(UInt<4>(0ha), idx_13) when _T_1719 : node _T_1720 = shl(UInt<4>(0hd), 3) node _T_1721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1720) node _T_1722 = bits(_T_1721, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1722 node _T_1723 = eq(UInt<4>(0hb), idx_13) when _T_1723 : node _T_1724 = shl(UInt<4>(0hd), 3) node _T_1725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1724) node _T_1726 = bits(_T_1725, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1726 node _T_1727 = eq(UInt<4>(0hc), idx_13) when _T_1727 : node _T_1728 = shl(UInt<4>(0hd), 3) node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728) node _T_1730 = bits(_T_1729, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1730 node _T_1731 = eq(UInt<4>(0hd), idx_13) when _T_1731 : node _T_1732 = shl(UInt<4>(0hd), 3) node _T_1733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1732) node _T_1734 = bits(_T_1733, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1734 node _T_1735 = eq(UInt<4>(0he), idx_13) when _T_1735 : node _T_1736 = shl(UInt<4>(0hd), 3) node _T_1737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1736) node _T_1738 = bits(_T_1737, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1738 node _T_1739 = eq(UInt<4>(0hf), idx_13) when _T_1739 : node _T_1740 = shl(UInt<4>(0hd), 3) node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740) node _T_1742 = bits(_T_1741, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1742 node _T_1743 = eq(UInt<5>(0h10), idx_13) when _T_1743 : node _T_1744 = shl(UInt<4>(0hd), 3) node _T_1745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1744) node _T_1746 = bits(_T_1745, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1746 node _T_1747 = eq(UInt<5>(0h11), idx_13) when _T_1747 : node _T_1748 = shl(UInt<4>(0hd), 3) node _T_1749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1748) node _T_1750 = bits(_T_1749, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1750 node _T_1751 = eq(UInt<5>(0h12), idx_13) when _T_1751 : node _T_1752 = shl(UInt<4>(0hd), 3) node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752) node _T_1754 = bits(_T_1753, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1754 node _T_1755 = eq(UInt<5>(0h13), idx_13) when _T_1755 : node _T_1756 = shl(UInt<4>(0hd), 3) node _T_1757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1756) node _T_1758 = bits(_T_1757, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1758 node _T_1759 = eq(UInt<5>(0h14), idx_13) when _T_1759 : node _T_1760 = shl(UInt<4>(0hd), 3) node _T_1761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1760) node _T_1762 = bits(_T_1761, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1762 node _T_1763 = eq(UInt<5>(0h15), idx_13) when _T_1763 : node _T_1764 = shl(UInt<4>(0hd), 3) node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764) node _T_1766 = bits(_T_1765, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1766 node _T_1767 = eq(UInt<5>(0h16), idx_13) when _T_1767 : node _T_1768 = shl(UInt<4>(0hd), 3) node _T_1769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1768) node _T_1770 = bits(_T_1769, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1770 node _T_1771 = eq(UInt<5>(0h17), idx_13) when _T_1771 : node _T_1772 = shl(UInt<4>(0hd), 3) node _T_1773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1772) node _T_1774 = bits(_T_1773, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1774 node _T_1775 = eq(UInt<5>(0h18), idx_13) when _T_1775 : node _T_1776 = shl(UInt<4>(0hd), 3) node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776) node _T_1778 = bits(_T_1777, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1778 node _T_1779 = eq(UInt<5>(0h19), idx_13) when _T_1779 : node _T_1780 = shl(UInt<4>(0hd), 3) node _T_1781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1780) node _T_1782 = bits(_T_1781, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1782 node _T_1783 = eq(UInt<5>(0h1a), idx_13) when _T_1783 : node _T_1784 = shl(UInt<4>(0hd), 3) node _T_1785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1784) node _T_1786 = bits(_T_1785, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1786 node _T_1787 = eq(UInt<5>(0h1b), idx_13) when _T_1787 : node _T_1788 = shl(UInt<4>(0hd), 3) node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788) node _T_1790 = bits(_T_1789, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1790 node _T_1791 = eq(UInt<5>(0h1c), idx_13) when _T_1791 : node _T_1792 = shl(UInt<4>(0hd), 3) node _T_1793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1792) node _T_1794 = bits(_T_1793, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1794 node _T_1795 = eq(UInt<5>(0h1d), idx_13) when _T_1795 : node _T_1796 = shl(UInt<4>(0hd), 3) node _T_1797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1796) node _T_1798 = bits(_T_1797, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1798 node _T_1799 = eq(UInt<5>(0h1e), idx_13) when _T_1799 : node _T_1800 = shl(UInt<4>(0hd), 3) node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800) node _T_1802 = bits(_T_1801, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1802 node _T_1803 = eq(UInt<5>(0h1f), idx_13) when _T_1803 : node _T_1804 = shl(UInt<4>(0hd), 3) node _T_1805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1804) node _T_1806 = bits(_T_1805, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1806 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_1807 = eq(UInt<1>(0h0), idx_14) when _T_1807 : node _T_1808 = shl(UInt<4>(0he), 3) node _T_1809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1808) node _T_1810 = bits(_T_1809, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1810 node _T_1811 = eq(UInt<1>(0h1), idx_14) when _T_1811 : node _T_1812 = shl(UInt<4>(0he), 3) node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812) node _T_1814 = bits(_T_1813, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1814 node _T_1815 = eq(UInt<2>(0h2), idx_14) when _T_1815 : node _T_1816 = shl(UInt<4>(0he), 3) node _T_1817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1816) node _T_1818 = bits(_T_1817, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1818 node _T_1819 = eq(UInt<2>(0h3), idx_14) when _T_1819 : node _T_1820 = shl(UInt<4>(0he), 3) node _T_1821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1820) node _T_1822 = bits(_T_1821, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1822 node _T_1823 = eq(UInt<3>(0h4), idx_14) when _T_1823 : node _T_1824 = shl(UInt<4>(0he), 3) node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824) node _T_1826 = bits(_T_1825, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1826 node _T_1827 = eq(UInt<3>(0h5), idx_14) when _T_1827 : node _T_1828 = shl(UInt<4>(0he), 3) node _T_1829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1828) node _T_1830 = bits(_T_1829, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1830 node _T_1831 = eq(UInt<3>(0h6), idx_14) when _T_1831 : node _T_1832 = shl(UInt<4>(0he), 3) node _T_1833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1832) node _T_1834 = bits(_T_1833, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1834 node _T_1835 = eq(UInt<3>(0h7), idx_14) when _T_1835 : node _T_1836 = shl(UInt<4>(0he), 3) node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836) node _T_1838 = bits(_T_1837, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1838 node _T_1839 = eq(UInt<4>(0h8), idx_14) when _T_1839 : node _T_1840 = shl(UInt<4>(0he), 3) node _T_1841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1840) node _T_1842 = bits(_T_1841, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1842 node _T_1843 = eq(UInt<4>(0h9), idx_14) when _T_1843 : node _T_1844 = shl(UInt<4>(0he), 3) node _T_1845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1844) node _T_1846 = bits(_T_1845, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1846 node _T_1847 = eq(UInt<4>(0ha), idx_14) when _T_1847 : node _T_1848 = shl(UInt<4>(0he), 3) node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848) node _T_1850 = bits(_T_1849, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1850 node _T_1851 = eq(UInt<4>(0hb), idx_14) when _T_1851 : node _T_1852 = shl(UInt<4>(0he), 3) node _T_1853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1852) node _T_1854 = bits(_T_1853, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1854 node _T_1855 = eq(UInt<4>(0hc), idx_14) when _T_1855 : node _T_1856 = shl(UInt<4>(0he), 3) node _T_1857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1856) node _T_1858 = bits(_T_1857, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1858 node _T_1859 = eq(UInt<4>(0hd), idx_14) when _T_1859 : node _T_1860 = shl(UInt<4>(0he), 3) node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860) node _T_1862 = bits(_T_1861, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1862 node _T_1863 = eq(UInt<4>(0he), idx_14) when _T_1863 : node _T_1864 = shl(UInt<4>(0he), 3) node _T_1865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1864) node _T_1866 = bits(_T_1865, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1866 node _T_1867 = eq(UInt<4>(0hf), idx_14) when _T_1867 : node _T_1868 = shl(UInt<4>(0he), 3) node _T_1869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1868) node _T_1870 = bits(_T_1869, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1870 node _T_1871 = eq(UInt<5>(0h10), idx_14) when _T_1871 : node _T_1872 = shl(UInt<4>(0he), 3) node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872) node _T_1874 = bits(_T_1873, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1874 node _T_1875 = eq(UInt<5>(0h11), idx_14) when _T_1875 : node _T_1876 = shl(UInt<4>(0he), 3) node _T_1877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1876) node _T_1878 = bits(_T_1877, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1878 node _T_1879 = eq(UInt<5>(0h12), idx_14) when _T_1879 : node _T_1880 = shl(UInt<4>(0he), 3) node _T_1881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1880) node _T_1882 = bits(_T_1881, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1882 node _T_1883 = eq(UInt<5>(0h13), idx_14) when _T_1883 : node _T_1884 = shl(UInt<4>(0he), 3) node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884) node _T_1886 = bits(_T_1885, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1886 node _T_1887 = eq(UInt<5>(0h14), idx_14) when _T_1887 : node _T_1888 = shl(UInt<4>(0he), 3) node _T_1889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1888) node _T_1890 = bits(_T_1889, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1890 node _T_1891 = eq(UInt<5>(0h15), idx_14) when _T_1891 : node _T_1892 = shl(UInt<4>(0he), 3) node _T_1893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1892) node _T_1894 = bits(_T_1893, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1894 node _T_1895 = eq(UInt<5>(0h16), idx_14) when _T_1895 : node _T_1896 = shl(UInt<4>(0he), 3) node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896) node _T_1898 = bits(_T_1897, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1898 node _T_1899 = eq(UInt<5>(0h17), idx_14) when _T_1899 : node _T_1900 = shl(UInt<4>(0he), 3) node _T_1901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1900) node _T_1902 = bits(_T_1901, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1902 node _T_1903 = eq(UInt<5>(0h18), idx_14) when _T_1903 : node _T_1904 = shl(UInt<4>(0he), 3) node _T_1905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1904) node _T_1906 = bits(_T_1905, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1906 node _T_1907 = eq(UInt<5>(0h19), idx_14) when _T_1907 : node _T_1908 = shl(UInt<4>(0he), 3) node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908) node _T_1910 = bits(_T_1909, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1910 node _T_1911 = eq(UInt<5>(0h1a), idx_14) when _T_1911 : node _T_1912 = shl(UInt<4>(0he), 3) node _T_1913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1912) node _T_1914 = bits(_T_1913, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1914 node _T_1915 = eq(UInt<5>(0h1b), idx_14) when _T_1915 : node _T_1916 = shl(UInt<4>(0he), 3) node _T_1917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1916) node _T_1918 = bits(_T_1917, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1918 node _T_1919 = eq(UInt<5>(0h1c), idx_14) when _T_1919 : node _T_1920 = shl(UInt<4>(0he), 3) node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920) node _T_1922 = bits(_T_1921, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1922 node _T_1923 = eq(UInt<5>(0h1d), idx_14) when _T_1923 : node _T_1924 = shl(UInt<4>(0he), 3) node _T_1925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1924) node _T_1926 = bits(_T_1925, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1926 node _T_1927 = eq(UInt<5>(0h1e), idx_14) when _T_1927 : node _T_1928 = shl(UInt<4>(0he), 3) node _T_1929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1928) node _T_1930 = bits(_T_1929, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1930 node _T_1931 = eq(UInt<5>(0h1f), idx_14) when _T_1931 : node _T_1932 = shl(UInt<4>(0he), 3) node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932) node _T_1934 = bits(_T_1933, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1934 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1935 = eq(UInt<1>(0h0), idx_15) when _T_1935 : node _T_1936 = shl(UInt<4>(0hf), 3) node _T_1937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1936) node _T_1938 = bits(_T_1937, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1938 node _T_1939 = eq(UInt<1>(0h1), idx_15) when _T_1939 : node _T_1940 = shl(UInt<4>(0hf), 3) node _T_1941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1940) node _T_1942 = bits(_T_1941, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1942 node _T_1943 = eq(UInt<2>(0h2), idx_15) when _T_1943 : node _T_1944 = shl(UInt<4>(0hf), 3) node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944) node _T_1946 = bits(_T_1945, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1946 node _T_1947 = eq(UInt<2>(0h3), idx_15) when _T_1947 : node _T_1948 = shl(UInt<4>(0hf), 3) node _T_1949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1948) node _T_1950 = bits(_T_1949, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1950 node _T_1951 = eq(UInt<3>(0h4), idx_15) when _T_1951 : node _T_1952 = shl(UInt<4>(0hf), 3) node _T_1953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1952) node _T_1954 = bits(_T_1953, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1954 node _T_1955 = eq(UInt<3>(0h5), idx_15) when _T_1955 : node _T_1956 = shl(UInt<4>(0hf), 3) node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956) node _T_1958 = bits(_T_1957, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1958 node _T_1959 = eq(UInt<3>(0h6), idx_15) when _T_1959 : node _T_1960 = shl(UInt<4>(0hf), 3) node _T_1961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1960) node _T_1962 = bits(_T_1961, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1962 node _T_1963 = eq(UInt<3>(0h7), idx_15) when _T_1963 : node _T_1964 = shl(UInt<4>(0hf), 3) node _T_1965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1964) node _T_1966 = bits(_T_1965, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1966 node _T_1967 = eq(UInt<4>(0h8), idx_15) when _T_1967 : node _T_1968 = shl(UInt<4>(0hf), 3) node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968) node _T_1970 = bits(_T_1969, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1970 node _T_1971 = eq(UInt<4>(0h9), idx_15) when _T_1971 : node _T_1972 = shl(UInt<4>(0hf), 3) node _T_1973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1972) node _T_1974 = bits(_T_1973, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1974 node _T_1975 = eq(UInt<4>(0ha), idx_15) when _T_1975 : node _T_1976 = shl(UInt<4>(0hf), 3) node _T_1977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1976) node _T_1978 = bits(_T_1977, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1978 node _T_1979 = eq(UInt<4>(0hb), idx_15) when _T_1979 : node _T_1980 = shl(UInt<4>(0hf), 3) node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980) node _T_1982 = bits(_T_1981, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1982 node _T_1983 = eq(UInt<4>(0hc), idx_15) when _T_1983 : node _T_1984 = shl(UInt<4>(0hf), 3) node _T_1985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1984) node _T_1986 = bits(_T_1985, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1986 node _T_1987 = eq(UInt<4>(0hd), idx_15) when _T_1987 : node _T_1988 = shl(UInt<4>(0hf), 3) node _T_1989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1988) node _T_1990 = bits(_T_1989, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1990 node _T_1991 = eq(UInt<4>(0he), idx_15) when _T_1991 : node _T_1992 = shl(UInt<4>(0hf), 3) node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992) node _T_1994 = bits(_T_1993, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1994 node _T_1995 = eq(UInt<4>(0hf), idx_15) when _T_1995 : node _T_1996 = shl(UInt<4>(0hf), 3) node _T_1997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1996) node _T_1998 = bits(_T_1997, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1998 node _T_1999 = eq(UInt<5>(0h10), idx_15) when _T_1999 : node _T_2000 = shl(UInt<4>(0hf), 3) node _T_2001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2000) node _T_2002 = bits(_T_2001, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2002 node _T_2003 = eq(UInt<5>(0h11), idx_15) when _T_2003 : node _T_2004 = shl(UInt<4>(0hf), 3) node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004) node _T_2006 = bits(_T_2005, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2006 node _T_2007 = eq(UInt<5>(0h12), idx_15) when _T_2007 : node _T_2008 = shl(UInt<4>(0hf), 3) node _T_2009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2008) node _T_2010 = bits(_T_2009, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2010 node _T_2011 = eq(UInt<5>(0h13), idx_15) when _T_2011 : node _T_2012 = shl(UInt<4>(0hf), 3) node _T_2013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2012) node _T_2014 = bits(_T_2013, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2014 node _T_2015 = eq(UInt<5>(0h14), idx_15) when _T_2015 : node _T_2016 = shl(UInt<4>(0hf), 3) node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016) node _T_2018 = bits(_T_2017, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2018 node _T_2019 = eq(UInt<5>(0h15), idx_15) when _T_2019 : node _T_2020 = shl(UInt<4>(0hf), 3) node _T_2021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2020) node _T_2022 = bits(_T_2021, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2022 node _T_2023 = eq(UInt<5>(0h16), idx_15) when _T_2023 : node _T_2024 = shl(UInt<4>(0hf), 3) node _T_2025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2024) node _T_2026 = bits(_T_2025, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2026 node _T_2027 = eq(UInt<5>(0h17), idx_15) when _T_2027 : node _T_2028 = shl(UInt<4>(0hf), 3) node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028) node _T_2030 = bits(_T_2029, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2030 node _T_2031 = eq(UInt<5>(0h18), idx_15) when _T_2031 : node _T_2032 = shl(UInt<4>(0hf), 3) node _T_2033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2032) node _T_2034 = bits(_T_2033, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2034 node _T_2035 = eq(UInt<5>(0h19), idx_15) when _T_2035 : node _T_2036 = shl(UInt<4>(0hf), 3) node _T_2037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2036) node _T_2038 = bits(_T_2037, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2038 node _T_2039 = eq(UInt<5>(0h1a), idx_15) when _T_2039 : node _T_2040 = shl(UInt<4>(0hf), 3) node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040) node _T_2042 = bits(_T_2041, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2042 node _T_2043 = eq(UInt<5>(0h1b), idx_15) when _T_2043 : node _T_2044 = shl(UInt<4>(0hf), 3) node _T_2045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2044) node _T_2046 = bits(_T_2045, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2046 node _T_2047 = eq(UInt<5>(0h1c), idx_15) when _T_2047 : node _T_2048 = shl(UInt<4>(0hf), 3) node _T_2049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2048) node _T_2050 = bits(_T_2049, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2050 node _T_2051 = eq(UInt<5>(0h1d), idx_15) when _T_2051 : node _T_2052 = shl(UInt<4>(0hf), 3) node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052) node _T_2054 = bits(_T_2053, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2054 node _T_2055 = eq(UInt<5>(0h1e), idx_15) when _T_2055 : node _T_2056 = shl(UInt<4>(0hf), 3) node _T_2057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2056) node _T_2058 = bits(_T_2057, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2058 node _T_2059 = eq(UInt<5>(0h1f), idx_15) when _T_2059 : node _T_2060 = shl(UInt<4>(0hf), 3) node _T_2061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2060) node _T_2062 = bits(_T_2061, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2062 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_2063 = eq(UInt<1>(0h0), idx_16) when _T_2063 : node _T_2064 = shl(UInt<5>(0h10), 3) node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064) node _T_2066 = bits(_T_2065, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2066 node _T_2067 = eq(UInt<1>(0h1), idx_16) when _T_2067 : node _T_2068 = shl(UInt<5>(0h10), 3) node _T_2069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2068) node _T_2070 = bits(_T_2069, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2070 node _T_2071 = eq(UInt<2>(0h2), idx_16) when _T_2071 : node _T_2072 = shl(UInt<5>(0h10), 3) node _T_2073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2072) node _T_2074 = bits(_T_2073, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2074 node _T_2075 = eq(UInt<2>(0h3), idx_16) when _T_2075 : node _T_2076 = shl(UInt<5>(0h10), 3) node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076) node _T_2078 = bits(_T_2077, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2078 node _T_2079 = eq(UInt<3>(0h4), idx_16) when _T_2079 : node _T_2080 = shl(UInt<5>(0h10), 3) node _T_2081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2080) node _T_2082 = bits(_T_2081, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2082 node _T_2083 = eq(UInt<3>(0h5), idx_16) when _T_2083 : node _T_2084 = shl(UInt<5>(0h10), 3) node _T_2085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2084) node _T_2086 = bits(_T_2085, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2086 node _T_2087 = eq(UInt<3>(0h6), idx_16) when _T_2087 : node _T_2088 = shl(UInt<5>(0h10), 3) node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088) node _T_2090 = bits(_T_2089, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2090 node _T_2091 = eq(UInt<3>(0h7), idx_16) when _T_2091 : node _T_2092 = shl(UInt<5>(0h10), 3) node _T_2093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2092) node _T_2094 = bits(_T_2093, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2094 node _T_2095 = eq(UInt<4>(0h8), idx_16) when _T_2095 : node _T_2096 = shl(UInt<5>(0h10), 3) node _T_2097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2096) node _T_2098 = bits(_T_2097, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2098 node _T_2099 = eq(UInt<4>(0h9), idx_16) when _T_2099 : node _T_2100 = shl(UInt<5>(0h10), 3) node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100) node _T_2102 = bits(_T_2101, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2102 node _T_2103 = eq(UInt<4>(0ha), idx_16) when _T_2103 : node _T_2104 = shl(UInt<5>(0h10), 3) node _T_2105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2104) node _T_2106 = bits(_T_2105, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2106 node _T_2107 = eq(UInt<4>(0hb), idx_16) when _T_2107 : node _T_2108 = shl(UInt<5>(0h10), 3) node _T_2109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2108) node _T_2110 = bits(_T_2109, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2110 node _T_2111 = eq(UInt<4>(0hc), idx_16) when _T_2111 : node _T_2112 = shl(UInt<5>(0h10), 3) node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112) node _T_2114 = bits(_T_2113, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2114 node _T_2115 = eq(UInt<4>(0hd), idx_16) when _T_2115 : node _T_2116 = shl(UInt<5>(0h10), 3) node _T_2117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2116) node _T_2118 = bits(_T_2117, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2118 node _T_2119 = eq(UInt<4>(0he), idx_16) when _T_2119 : node _T_2120 = shl(UInt<5>(0h10), 3) node _T_2121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2120) node _T_2122 = bits(_T_2121, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2122 node _T_2123 = eq(UInt<4>(0hf), idx_16) when _T_2123 : node _T_2124 = shl(UInt<5>(0h10), 3) node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124) node _T_2126 = bits(_T_2125, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2126 node _T_2127 = eq(UInt<5>(0h10), idx_16) when _T_2127 : node _T_2128 = shl(UInt<5>(0h10), 3) node _T_2129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2128) node _T_2130 = bits(_T_2129, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2130 node _T_2131 = eq(UInt<5>(0h11), idx_16) when _T_2131 : node _T_2132 = shl(UInt<5>(0h10), 3) node _T_2133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2132) node _T_2134 = bits(_T_2133, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2134 node _T_2135 = eq(UInt<5>(0h12), idx_16) when _T_2135 : node _T_2136 = shl(UInt<5>(0h10), 3) node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136) node _T_2138 = bits(_T_2137, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2138 node _T_2139 = eq(UInt<5>(0h13), idx_16) when _T_2139 : node _T_2140 = shl(UInt<5>(0h10), 3) node _T_2141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2140) node _T_2142 = bits(_T_2141, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2142 node _T_2143 = eq(UInt<5>(0h14), idx_16) when _T_2143 : node _T_2144 = shl(UInt<5>(0h10), 3) node _T_2145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2144) node _T_2146 = bits(_T_2145, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2146 node _T_2147 = eq(UInt<5>(0h15), idx_16) when _T_2147 : node _T_2148 = shl(UInt<5>(0h10), 3) node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148) node _T_2150 = bits(_T_2149, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2150 node _T_2151 = eq(UInt<5>(0h16), idx_16) when _T_2151 : node _T_2152 = shl(UInt<5>(0h10), 3) node _T_2153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2152) node _T_2154 = bits(_T_2153, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2154 node _T_2155 = eq(UInt<5>(0h17), idx_16) when _T_2155 : node _T_2156 = shl(UInt<5>(0h10), 3) node _T_2157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2156) node _T_2158 = bits(_T_2157, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2158 node _T_2159 = eq(UInt<5>(0h18), idx_16) when _T_2159 : node _T_2160 = shl(UInt<5>(0h10), 3) node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160) node _T_2162 = bits(_T_2161, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2162 node _T_2163 = eq(UInt<5>(0h19), idx_16) when _T_2163 : node _T_2164 = shl(UInt<5>(0h10), 3) node _T_2165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2164) node _T_2166 = bits(_T_2165, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2166 node _T_2167 = eq(UInt<5>(0h1a), idx_16) when _T_2167 : node _T_2168 = shl(UInt<5>(0h10), 3) node _T_2169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2168) node _T_2170 = bits(_T_2169, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2170 node _T_2171 = eq(UInt<5>(0h1b), idx_16) when _T_2171 : node _T_2172 = shl(UInt<5>(0h10), 3) node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172) node _T_2174 = bits(_T_2173, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2174 node _T_2175 = eq(UInt<5>(0h1c), idx_16) when _T_2175 : node _T_2176 = shl(UInt<5>(0h10), 3) node _T_2177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2176) node _T_2178 = bits(_T_2177, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2178 node _T_2179 = eq(UInt<5>(0h1d), idx_16) when _T_2179 : node _T_2180 = shl(UInt<5>(0h10), 3) node _T_2181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2180) node _T_2182 = bits(_T_2181, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2182 node _T_2183 = eq(UInt<5>(0h1e), idx_16) when _T_2183 : node _T_2184 = shl(UInt<5>(0h10), 3) node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184) node _T_2186 = bits(_T_2185, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2186 node _T_2187 = eq(UInt<5>(0h1f), idx_16) when _T_2187 : node _T_2188 = shl(UInt<5>(0h10), 3) node _T_2189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2188) node _T_2190 = bits(_T_2189, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2190 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_2191 = eq(UInt<1>(0h0), idx_17) when _T_2191 : node _T_2192 = shl(UInt<5>(0h11), 3) node _T_2193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2192) node _T_2194 = bits(_T_2193, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2194 node _T_2195 = eq(UInt<1>(0h1), idx_17) when _T_2195 : node _T_2196 = shl(UInt<5>(0h11), 3) node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196) node _T_2198 = bits(_T_2197, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2198 node _T_2199 = eq(UInt<2>(0h2), idx_17) when _T_2199 : node _T_2200 = shl(UInt<5>(0h11), 3) node _T_2201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2200) node _T_2202 = bits(_T_2201, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2202 node _T_2203 = eq(UInt<2>(0h3), idx_17) when _T_2203 : node _T_2204 = shl(UInt<5>(0h11), 3) node _T_2205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2204) node _T_2206 = bits(_T_2205, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2206 node _T_2207 = eq(UInt<3>(0h4), idx_17) when _T_2207 : node _T_2208 = shl(UInt<5>(0h11), 3) node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208) node _T_2210 = bits(_T_2209, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2210 node _T_2211 = eq(UInt<3>(0h5), idx_17) when _T_2211 : node _T_2212 = shl(UInt<5>(0h11), 3) node _T_2213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2212) node _T_2214 = bits(_T_2213, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2214 node _T_2215 = eq(UInt<3>(0h6), idx_17) when _T_2215 : node _T_2216 = shl(UInt<5>(0h11), 3) node _T_2217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2216) node _T_2218 = bits(_T_2217, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2218 node _T_2219 = eq(UInt<3>(0h7), idx_17) when _T_2219 : node _T_2220 = shl(UInt<5>(0h11), 3) node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220) node _T_2222 = bits(_T_2221, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2222 node _T_2223 = eq(UInt<4>(0h8), idx_17) when _T_2223 : node _T_2224 = shl(UInt<5>(0h11), 3) node _T_2225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2224) node _T_2226 = bits(_T_2225, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2226 node _T_2227 = eq(UInt<4>(0h9), idx_17) when _T_2227 : node _T_2228 = shl(UInt<5>(0h11), 3) node _T_2229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2228) node _T_2230 = bits(_T_2229, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2230 node _T_2231 = eq(UInt<4>(0ha), idx_17) when _T_2231 : node _T_2232 = shl(UInt<5>(0h11), 3) node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232) node _T_2234 = bits(_T_2233, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2234 node _T_2235 = eq(UInt<4>(0hb), idx_17) when _T_2235 : node _T_2236 = shl(UInt<5>(0h11), 3) node _T_2237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2236) node _T_2238 = bits(_T_2237, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2238 node _T_2239 = eq(UInt<4>(0hc), idx_17) when _T_2239 : node _T_2240 = shl(UInt<5>(0h11), 3) node _T_2241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2240) node _T_2242 = bits(_T_2241, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2242 node _T_2243 = eq(UInt<4>(0hd), idx_17) when _T_2243 : node _T_2244 = shl(UInt<5>(0h11), 3) node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244) node _T_2246 = bits(_T_2245, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2246 node _T_2247 = eq(UInt<4>(0he), idx_17) when _T_2247 : node _T_2248 = shl(UInt<5>(0h11), 3) node _T_2249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2248) node _T_2250 = bits(_T_2249, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2250 node _T_2251 = eq(UInt<4>(0hf), idx_17) when _T_2251 : node _T_2252 = shl(UInt<5>(0h11), 3) node _T_2253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2252) node _T_2254 = bits(_T_2253, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2254 node _T_2255 = eq(UInt<5>(0h10), idx_17) when _T_2255 : node _T_2256 = shl(UInt<5>(0h11), 3) node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256) node _T_2258 = bits(_T_2257, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2258 node _T_2259 = eq(UInt<5>(0h11), idx_17) when _T_2259 : node _T_2260 = shl(UInt<5>(0h11), 3) node _T_2261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2260) node _T_2262 = bits(_T_2261, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2262 node _T_2263 = eq(UInt<5>(0h12), idx_17) when _T_2263 : node _T_2264 = shl(UInt<5>(0h11), 3) node _T_2265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2264) node _T_2266 = bits(_T_2265, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2266 node _T_2267 = eq(UInt<5>(0h13), idx_17) when _T_2267 : node _T_2268 = shl(UInt<5>(0h11), 3) node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268) node _T_2270 = bits(_T_2269, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2270 node _T_2271 = eq(UInt<5>(0h14), idx_17) when _T_2271 : node _T_2272 = shl(UInt<5>(0h11), 3) node _T_2273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2272) node _T_2274 = bits(_T_2273, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2274 node _T_2275 = eq(UInt<5>(0h15), idx_17) when _T_2275 : node _T_2276 = shl(UInt<5>(0h11), 3) node _T_2277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2276) node _T_2278 = bits(_T_2277, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2278 node _T_2279 = eq(UInt<5>(0h16), idx_17) when _T_2279 : node _T_2280 = shl(UInt<5>(0h11), 3) node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280) node _T_2282 = bits(_T_2281, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2282 node _T_2283 = eq(UInt<5>(0h17), idx_17) when _T_2283 : node _T_2284 = shl(UInt<5>(0h11), 3) node _T_2285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2284) node _T_2286 = bits(_T_2285, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2286 node _T_2287 = eq(UInt<5>(0h18), idx_17) when _T_2287 : node _T_2288 = shl(UInt<5>(0h11), 3) node _T_2289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2288) node _T_2290 = bits(_T_2289, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2290 node _T_2291 = eq(UInt<5>(0h19), idx_17) when _T_2291 : node _T_2292 = shl(UInt<5>(0h11), 3) node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292) node _T_2294 = bits(_T_2293, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2294 node _T_2295 = eq(UInt<5>(0h1a), idx_17) when _T_2295 : node _T_2296 = shl(UInt<5>(0h11), 3) node _T_2297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2296) node _T_2298 = bits(_T_2297, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2298 node _T_2299 = eq(UInt<5>(0h1b), idx_17) when _T_2299 : node _T_2300 = shl(UInt<5>(0h11), 3) node _T_2301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2300) node _T_2302 = bits(_T_2301, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2302 node _T_2303 = eq(UInt<5>(0h1c), idx_17) when _T_2303 : node _T_2304 = shl(UInt<5>(0h11), 3) node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304) node _T_2306 = bits(_T_2305, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2306 node _T_2307 = eq(UInt<5>(0h1d), idx_17) when _T_2307 : node _T_2308 = shl(UInt<5>(0h11), 3) node _T_2309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2308) node _T_2310 = bits(_T_2309, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2310 node _T_2311 = eq(UInt<5>(0h1e), idx_17) when _T_2311 : node _T_2312 = shl(UInt<5>(0h11), 3) node _T_2313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2312) node _T_2314 = bits(_T_2313, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2314 node _T_2315 = eq(UInt<5>(0h1f), idx_17) when _T_2315 : node _T_2316 = shl(UInt<5>(0h11), 3) node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316) node _T_2318 = bits(_T_2317, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2318 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_2319 = eq(UInt<1>(0h0), idx_18) when _T_2319 : node _T_2320 = shl(UInt<5>(0h12), 3) node _T_2321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2320) node _T_2322 = bits(_T_2321, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2322 node _T_2323 = eq(UInt<1>(0h1), idx_18) when _T_2323 : node _T_2324 = shl(UInt<5>(0h12), 3) node _T_2325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2324) node _T_2326 = bits(_T_2325, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2326 node _T_2327 = eq(UInt<2>(0h2), idx_18) when _T_2327 : node _T_2328 = shl(UInt<5>(0h12), 3) node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328) node _T_2330 = bits(_T_2329, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2330 node _T_2331 = eq(UInt<2>(0h3), idx_18) when _T_2331 : node _T_2332 = shl(UInt<5>(0h12), 3) node _T_2333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2332) node _T_2334 = bits(_T_2333, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2334 node _T_2335 = eq(UInt<3>(0h4), idx_18) when _T_2335 : node _T_2336 = shl(UInt<5>(0h12), 3) node _T_2337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2336) node _T_2338 = bits(_T_2337, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2338 node _T_2339 = eq(UInt<3>(0h5), idx_18) when _T_2339 : node _T_2340 = shl(UInt<5>(0h12), 3) node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340) node _T_2342 = bits(_T_2341, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2342 node _T_2343 = eq(UInt<3>(0h6), idx_18) when _T_2343 : node _T_2344 = shl(UInt<5>(0h12), 3) node _T_2345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2344) node _T_2346 = bits(_T_2345, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2346 node _T_2347 = eq(UInt<3>(0h7), idx_18) when _T_2347 : node _T_2348 = shl(UInt<5>(0h12), 3) node _T_2349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2348) node _T_2350 = bits(_T_2349, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2350 node _T_2351 = eq(UInt<4>(0h8), idx_18) when _T_2351 : node _T_2352 = shl(UInt<5>(0h12), 3) node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352) node _T_2354 = bits(_T_2353, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2354 node _T_2355 = eq(UInt<4>(0h9), idx_18) when _T_2355 : node _T_2356 = shl(UInt<5>(0h12), 3) node _T_2357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2356) node _T_2358 = bits(_T_2357, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2358 node _T_2359 = eq(UInt<4>(0ha), idx_18) when _T_2359 : node _T_2360 = shl(UInt<5>(0h12), 3) node _T_2361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2360) node _T_2362 = bits(_T_2361, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2362 node _T_2363 = eq(UInt<4>(0hb), idx_18) when _T_2363 : node _T_2364 = shl(UInt<5>(0h12), 3) node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364) node _T_2366 = bits(_T_2365, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2366 node _T_2367 = eq(UInt<4>(0hc), idx_18) when _T_2367 : node _T_2368 = shl(UInt<5>(0h12), 3) node _T_2369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2368) node _T_2370 = bits(_T_2369, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2370 node _T_2371 = eq(UInt<4>(0hd), idx_18) when _T_2371 : node _T_2372 = shl(UInt<5>(0h12), 3) node _T_2373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2372) node _T_2374 = bits(_T_2373, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2374 node _T_2375 = eq(UInt<4>(0he), idx_18) when _T_2375 : node _T_2376 = shl(UInt<5>(0h12), 3) node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376) node _T_2378 = bits(_T_2377, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2378 node _T_2379 = eq(UInt<4>(0hf), idx_18) when _T_2379 : node _T_2380 = shl(UInt<5>(0h12), 3) node _T_2381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2380) node _T_2382 = bits(_T_2381, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2382 node _T_2383 = eq(UInt<5>(0h10), idx_18) when _T_2383 : node _T_2384 = shl(UInt<5>(0h12), 3) node _T_2385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2384) node _T_2386 = bits(_T_2385, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2386 node _T_2387 = eq(UInt<5>(0h11), idx_18) when _T_2387 : node _T_2388 = shl(UInt<5>(0h12), 3) node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388) node _T_2390 = bits(_T_2389, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2390 node _T_2391 = eq(UInt<5>(0h12), idx_18) when _T_2391 : node _T_2392 = shl(UInt<5>(0h12), 3) node _T_2393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2392) node _T_2394 = bits(_T_2393, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2394 node _T_2395 = eq(UInt<5>(0h13), idx_18) when _T_2395 : node _T_2396 = shl(UInt<5>(0h12), 3) node _T_2397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2396) node _T_2398 = bits(_T_2397, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2398 node _T_2399 = eq(UInt<5>(0h14), idx_18) when _T_2399 : node _T_2400 = shl(UInt<5>(0h12), 3) node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400) node _T_2402 = bits(_T_2401, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2402 node _T_2403 = eq(UInt<5>(0h15), idx_18) when _T_2403 : node _T_2404 = shl(UInt<5>(0h12), 3) node _T_2405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2404) node _T_2406 = bits(_T_2405, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2406 node _T_2407 = eq(UInt<5>(0h16), idx_18) when _T_2407 : node _T_2408 = shl(UInt<5>(0h12), 3) node _T_2409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2408) node _T_2410 = bits(_T_2409, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2410 node _T_2411 = eq(UInt<5>(0h17), idx_18) when _T_2411 : node _T_2412 = shl(UInt<5>(0h12), 3) node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412) node _T_2414 = bits(_T_2413, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2414 node _T_2415 = eq(UInt<5>(0h18), idx_18) when _T_2415 : node _T_2416 = shl(UInt<5>(0h12), 3) node _T_2417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2416) node _T_2418 = bits(_T_2417, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2418 node _T_2419 = eq(UInt<5>(0h19), idx_18) when _T_2419 : node _T_2420 = shl(UInt<5>(0h12), 3) node _T_2421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2420) node _T_2422 = bits(_T_2421, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2422 node _T_2423 = eq(UInt<5>(0h1a), idx_18) when _T_2423 : node _T_2424 = shl(UInt<5>(0h12), 3) node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424) node _T_2426 = bits(_T_2425, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2426 node _T_2427 = eq(UInt<5>(0h1b), idx_18) when _T_2427 : node _T_2428 = shl(UInt<5>(0h12), 3) node _T_2429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2428) node _T_2430 = bits(_T_2429, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2430 node _T_2431 = eq(UInt<5>(0h1c), idx_18) when _T_2431 : node _T_2432 = shl(UInt<5>(0h12), 3) node _T_2433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2432) node _T_2434 = bits(_T_2433, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2434 node _T_2435 = eq(UInt<5>(0h1d), idx_18) when _T_2435 : node _T_2436 = shl(UInt<5>(0h12), 3) node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436) node _T_2438 = bits(_T_2437, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2438 node _T_2439 = eq(UInt<5>(0h1e), idx_18) when _T_2439 : node _T_2440 = shl(UInt<5>(0h12), 3) node _T_2441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2440) node _T_2442 = bits(_T_2441, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2442 node _T_2443 = eq(UInt<5>(0h1f), idx_18) when _T_2443 : node _T_2444 = shl(UInt<5>(0h12), 3) node _T_2445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2444) node _T_2446 = bits(_T_2445, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2446 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_2447 = eq(UInt<1>(0h0), idx_19) when _T_2447 : node _T_2448 = shl(UInt<5>(0h13), 3) node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448) node _T_2450 = bits(_T_2449, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2450 node _T_2451 = eq(UInt<1>(0h1), idx_19) when _T_2451 : node _T_2452 = shl(UInt<5>(0h13), 3) node _T_2453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2452) node _T_2454 = bits(_T_2453, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2454 node _T_2455 = eq(UInt<2>(0h2), idx_19) when _T_2455 : node _T_2456 = shl(UInt<5>(0h13), 3) node _T_2457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2456) node _T_2458 = bits(_T_2457, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2458 node _T_2459 = eq(UInt<2>(0h3), idx_19) when _T_2459 : node _T_2460 = shl(UInt<5>(0h13), 3) node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460) node _T_2462 = bits(_T_2461, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2462 node _T_2463 = eq(UInt<3>(0h4), idx_19) when _T_2463 : node _T_2464 = shl(UInt<5>(0h13), 3) node _T_2465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2464) node _T_2466 = bits(_T_2465, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2466 node _T_2467 = eq(UInt<3>(0h5), idx_19) when _T_2467 : node _T_2468 = shl(UInt<5>(0h13), 3) node _T_2469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2468) node _T_2470 = bits(_T_2469, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2470 node _T_2471 = eq(UInt<3>(0h6), idx_19) when _T_2471 : node _T_2472 = shl(UInt<5>(0h13), 3) node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472) node _T_2474 = bits(_T_2473, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2474 node _T_2475 = eq(UInt<3>(0h7), idx_19) when _T_2475 : node _T_2476 = shl(UInt<5>(0h13), 3) node _T_2477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2476) node _T_2478 = bits(_T_2477, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2478 node _T_2479 = eq(UInt<4>(0h8), idx_19) when _T_2479 : node _T_2480 = shl(UInt<5>(0h13), 3) node _T_2481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2480) node _T_2482 = bits(_T_2481, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2482 node _T_2483 = eq(UInt<4>(0h9), idx_19) when _T_2483 : node _T_2484 = shl(UInt<5>(0h13), 3) node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484) node _T_2486 = bits(_T_2485, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2486 node _T_2487 = eq(UInt<4>(0ha), idx_19) when _T_2487 : node _T_2488 = shl(UInt<5>(0h13), 3) node _T_2489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2488) node _T_2490 = bits(_T_2489, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2490 node _T_2491 = eq(UInt<4>(0hb), idx_19) when _T_2491 : node _T_2492 = shl(UInt<5>(0h13), 3) node _T_2493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2492) node _T_2494 = bits(_T_2493, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2494 node _T_2495 = eq(UInt<4>(0hc), idx_19) when _T_2495 : node _T_2496 = shl(UInt<5>(0h13), 3) node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496) node _T_2498 = bits(_T_2497, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2498 node _T_2499 = eq(UInt<4>(0hd), idx_19) when _T_2499 : node _T_2500 = shl(UInt<5>(0h13), 3) node _T_2501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2500) node _T_2502 = bits(_T_2501, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2502 node _T_2503 = eq(UInt<4>(0he), idx_19) when _T_2503 : node _T_2504 = shl(UInt<5>(0h13), 3) node _T_2505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2504) node _T_2506 = bits(_T_2505, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2506 node _T_2507 = eq(UInt<4>(0hf), idx_19) when _T_2507 : node _T_2508 = shl(UInt<5>(0h13), 3) node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508) node _T_2510 = bits(_T_2509, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2510 node _T_2511 = eq(UInt<5>(0h10), idx_19) when _T_2511 : node _T_2512 = shl(UInt<5>(0h13), 3) node _T_2513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2512) node _T_2514 = bits(_T_2513, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2514 node _T_2515 = eq(UInt<5>(0h11), idx_19) when _T_2515 : node _T_2516 = shl(UInt<5>(0h13), 3) node _T_2517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2516) node _T_2518 = bits(_T_2517, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2518 node _T_2519 = eq(UInt<5>(0h12), idx_19) when _T_2519 : node _T_2520 = shl(UInt<5>(0h13), 3) node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520) node _T_2522 = bits(_T_2521, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2522 node _T_2523 = eq(UInt<5>(0h13), idx_19) when _T_2523 : node _T_2524 = shl(UInt<5>(0h13), 3) node _T_2525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2524) node _T_2526 = bits(_T_2525, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2526 node _T_2527 = eq(UInt<5>(0h14), idx_19) when _T_2527 : node _T_2528 = shl(UInt<5>(0h13), 3) node _T_2529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2528) node _T_2530 = bits(_T_2529, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2530 node _T_2531 = eq(UInt<5>(0h15), idx_19) when _T_2531 : node _T_2532 = shl(UInt<5>(0h13), 3) node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532) node _T_2534 = bits(_T_2533, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2534 node _T_2535 = eq(UInt<5>(0h16), idx_19) when _T_2535 : node _T_2536 = shl(UInt<5>(0h13), 3) node _T_2537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2536) node _T_2538 = bits(_T_2537, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2538 node _T_2539 = eq(UInt<5>(0h17), idx_19) when _T_2539 : node _T_2540 = shl(UInt<5>(0h13), 3) node _T_2541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2540) node _T_2542 = bits(_T_2541, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2542 node _T_2543 = eq(UInt<5>(0h18), idx_19) when _T_2543 : node _T_2544 = shl(UInt<5>(0h13), 3) node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544) node _T_2546 = bits(_T_2545, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2546 node _T_2547 = eq(UInt<5>(0h19), idx_19) when _T_2547 : node _T_2548 = shl(UInt<5>(0h13), 3) node _T_2549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2548) node _T_2550 = bits(_T_2549, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2550 node _T_2551 = eq(UInt<5>(0h1a), idx_19) when _T_2551 : node _T_2552 = shl(UInt<5>(0h13), 3) node _T_2553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2552) node _T_2554 = bits(_T_2553, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2554 node _T_2555 = eq(UInt<5>(0h1b), idx_19) when _T_2555 : node _T_2556 = shl(UInt<5>(0h13), 3) node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556) node _T_2558 = bits(_T_2557, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2558 node _T_2559 = eq(UInt<5>(0h1c), idx_19) when _T_2559 : node _T_2560 = shl(UInt<5>(0h13), 3) node _T_2561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2560) node _T_2562 = bits(_T_2561, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2562 node _T_2563 = eq(UInt<5>(0h1d), idx_19) when _T_2563 : node _T_2564 = shl(UInt<5>(0h13), 3) node _T_2565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2564) node _T_2566 = bits(_T_2565, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2566 node _T_2567 = eq(UInt<5>(0h1e), idx_19) when _T_2567 : node _T_2568 = shl(UInt<5>(0h13), 3) node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568) node _T_2570 = bits(_T_2569, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2570 node _T_2571 = eq(UInt<5>(0h1f), idx_19) when _T_2571 : node _T_2572 = shl(UInt<5>(0h13), 3) node _T_2573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2572) node _T_2574 = bits(_T_2573, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2574 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_2575 = eq(UInt<1>(0h0), idx_20) when _T_2575 : node _T_2576 = shl(UInt<5>(0h14), 3) node _T_2577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2576) node _T_2578 = bits(_T_2577, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2578 node _T_2579 = eq(UInt<1>(0h1), idx_20) when _T_2579 : node _T_2580 = shl(UInt<5>(0h14), 3) node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580) node _T_2582 = bits(_T_2581, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2582 node _T_2583 = eq(UInt<2>(0h2), idx_20) when _T_2583 : node _T_2584 = shl(UInt<5>(0h14), 3) node _T_2585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2584) node _T_2586 = bits(_T_2585, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2586 node _T_2587 = eq(UInt<2>(0h3), idx_20) when _T_2587 : node _T_2588 = shl(UInt<5>(0h14), 3) node _T_2589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2588) node _T_2590 = bits(_T_2589, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2590 node _T_2591 = eq(UInt<3>(0h4), idx_20) when _T_2591 : node _T_2592 = shl(UInt<5>(0h14), 3) node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592) node _T_2594 = bits(_T_2593, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2594 node _T_2595 = eq(UInt<3>(0h5), idx_20) when _T_2595 : node _T_2596 = shl(UInt<5>(0h14), 3) node _T_2597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2596) node _T_2598 = bits(_T_2597, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2598 node _T_2599 = eq(UInt<3>(0h6), idx_20) when _T_2599 : node _T_2600 = shl(UInt<5>(0h14), 3) node _T_2601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2600) node _T_2602 = bits(_T_2601, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2602 node _T_2603 = eq(UInt<3>(0h7), idx_20) when _T_2603 : node _T_2604 = shl(UInt<5>(0h14), 3) node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604) node _T_2606 = bits(_T_2605, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2606 node _T_2607 = eq(UInt<4>(0h8), idx_20) when _T_2607 : node _T_2608 = shl(UInt<5>(0h14), 3) node _T_2609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2608) node _T_2610 = bits(_T_2609, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2610 node _T_2611 = eq(UInt<4>(0h9), idx_20) when _T_2611 : node _T_2612 = shl(UInt<5>(0h14), 3) node _T_2613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2612) node _T_2614 = bits(_T_2613, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2614 node _T_2615 = eq(UInt<4>(0ha), idx_20) when _T_2615 : node _T_2616 = shl(UInt<5>(0h14), 3) node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616) node _T_2618 = bits(_T_2617, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2618 node _T_2619 = eq(UInt<4>(0hb), idx_20) when _T_2619 : node _T_2620 = shl(UInt<5>(0h14), 3) node _T_2621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2620) node _T_2622 = bits(_T_2621, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2622 node _T_2623 = eq(UInt<4>(0hc), idx_20) when _T_2623 : node _T_2624 = shl(UInt<5>(0h14), 3) node _T_2625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2624) node _T_2626 = bits(_T_2625, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2626 node _T_2627 = eq(UInt<4>(0hd), idx_20) when _T_2627 : node _T_2628 = shl(UInt<5>(0h14), 3) node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628) node _T_2630 = bits(_T_2629, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2630 node _T_2631 = eq(UInt<4>(0he), idx_20) when _T_2631 : node _T_2632 = shl(UInt<5>(0h14), 3) node _T_2633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2632) node _T_2634 = bits(_T_2633, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2634 node _T_2635 = eq(UInt<4>(0hf), idx_20) when _T_2635 : node _T_2636 = shl(UInt<5>(0h14), 3) node _T_2637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2636) node _T_2638 = bits(_T_2637, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2638 node _T_2639 = eq(UInt<5>(0h10), idx_20) when _T_2639 : node _T_2640 = shl(UInt<5>(0h14), 3) node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640) node _T_2642 = bits(_T_2641, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2642 node _T_2643 = eq(UInt<5>(0h11), idx_20) when _T_2643 : node _T_2644 = shl(UInt<5>(0h14), 3) node _T_2645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2644) node _T_2646 = bits(_T_2645, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2646 node _T_2647 = eq(UInt<5>(0h12), idx_20) when _T_2647 : node _T_2648 = shl(UInt<5>(0h14), 3) node _T_2649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2648) node _T_2650 = bits(_T_2649, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2650 node _T_2651 = eq(UInt<5>(0h13), idx_20) when _T_2651 : node _T_2652 = shl(UInt<5>(0h14), 3) node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652) node _T_2654 = bits(_T_2653, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2654 node _T_2655 = eq(UInt<5>(0h14), idx_20) when _T_2655 : node _T_2656 = shl(UInt<5>(0h14), 3) node _T_2657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2656) node _T_2658 = bits(_T_2657, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2658 node _T_2659 = eq(UInt<5>(0h15), idx_20) when _T_2659 : node _T_2660 = shl(UInt<5>(0h14), 3) node _T_2661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2660) node _T_2662 = bits(_T_2661, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2662 node _T_2663 = eq(UInt<5>(0h16), idx_20) when _T_2663 : node _T_2664 = shl(UInt<5>(0h14), 3) node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664) node _T_2666 = bits(_T_2665, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2666 node _T_2667 = eq(UInt<5>(0h17), idx_20) when _T_2667 : node _T_2668 = shl(UInt<5>(0h14), 3) node _T_2669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2668) node _T_2670 = bits(_T_2669, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2670 node _T_2671 = eq(UInt<5>(0h18), idx_20) when _T_2671 : node _T_2672 = shl(UInt<5>(0h14), 3) node _T_2673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2672) node _T_2674 = bits(_T_2673, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2674 node _T_2675 = eq(UInt<5>(0h19), idx_20) when _T_2675 : node _T_2676 = shl(UInt<5>(0h14), 3) node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676) node _T_2678 = bits(_T_2677, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2678 node _T_2679 = eq(UInt<5>(0h1a), idx_20) when _T_2679 : node _T_2680 = shl(UInt<5>(0h14), 3) node _T_2681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2680) node _T_2682 = bits(_T_2681, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2682 node _T_2683 = eq(UInt<5>(0h1b), idx_20) when _T_2683 : node _T_2684 = shl(UInt<5>(0h14), 3) node _T_2685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2684) node _T_2686 = bits(_T_2685, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2686 node _T_2687 = eq(UInt<5>(0h1c), idx_20) when _T_2687 : node _T_2688 = shl(UInt<5>(0h14), 3) node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688) node _T_2690 = bits(_T_2689, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2690 node _T_2691 = eq(UInt<5>(0h1d), idx_20) when _T_2691 : node _T_2692 = shl(UInt<5>(0h14), 3) node _T_2693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2692) node _T_2694 = bits(_T_2693, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2694 node _T_2695 = eq(UInt<5>(0h1e), idx_20) when _T_2695 : node _T_2696 = shl(UInt<5>(0h14), 3) node _T_2697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2696) node _T_2698 = bits(_T_2697, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2698 node _T_2699 = eq(UInt<5>(0h1f), idx_20) when _T_2699 : node _T_2700 = shl(UInt<5>(0h14), 3) node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700) node _T_2702 = bits(_T_2701, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2702 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_2703 = eq(UInt<1>(0h0), idx_21) when _T_2703 : node _T_2704 = shl(UInt<5>(0h15), 3) node _T_2705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2704) node _T_2706 = bits(_T_2705, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2706 node _T_2707 = eq(UInt<1>(0h1), idx_21) when _T_2707 : node _T_2708 = shl(UInt<5>(0h15), 3) node _T_2709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2708) node _T_2710 = bits(_T_2709, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2710 node _T_2711 = eq(UInt<2>(0h2), idx_21) when _T_2711 : node _T_2712 = shl(UInt<5>(0h15), 3) node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712) node _T_2714 = bits(_T_2713, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2714 node _T_2715 = eq(UInt<2>(0h3), idx_21) when _T_2715 : node _T_2716 = shl(UInt<5>(0h15), 3) node _T_2717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2716) node _T_2718 = bits(_T_2717, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2718 node _T_2719 = eq(UInt<3>(0h4), idx_21) when _T_2719 : node _T_2720 = shl(UInt<5>(0h15), 3) node _T_2721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2720) node _T_2722 = bits(_T_2721, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2722 node _T_2723 = eq(UInt<3>(0h5), idx_21) when _T_2723 : node _T_2724 = shl(UInt<5>(0h15), 3) node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724) node _T_2726 = bits(_T_2725, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2726 node _T_2727 = eq(UInt<3>(0h6), idx_21) when _T_2727 : node _T_2728 = shl(UInt<5>(0h15), 3) node _T_2729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2728) node _T_2730 = bits(_T_2729, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2730 node _T_2731 = eq(UInt<3>(0h7), idx_21) when _T_2731 : node _T_2732 = shl(UInt<5>(0h15), 3) node _T_2733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2732) node _T_2734 = bits(_T_2733, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2734 node _T_2735 = eq(UInt<4>(0h8), idx_21) when _T_2735 : node _T_2736 = shl(UInt<5>(0h15), 3) node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736) node _T_2738 = bits(_T_2737, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2738 node _T_2739 = eq(UInt<4>(0h9), idx_21) when _T_2739 : node _T_2740 = shl(UInt<5>(0h15), 3) node _T_2741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2740) node _T_2742 = bits(_T_2741, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2742 node _T_2743 = eq(UInt<4>(0ha), idx_21) when _T_2743 : node _T_2744 = shl(UInt<5>(0h15), 3) node _T_2745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2744) node _T_2746 = bits(_T_2745, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2746 node _T_2747 = eq(UInt<4>(0hb), idx_21) when _T_2747 : node _T_2748 = shl(UInt<5>(0h15), 3) node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748) node _T_2750 = bits(_T_2749, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2750 node _T_2751 = eq(UInt<4>(0hc), idx_21) when _T_2751 : node _T_2752 = shl(UInt<5>(0h15), 3) node _T_2753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2752) node _T_2754 = bits(_T_2753, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2754 node _T_2755 = eq(UInt<4>(0hd), idx_21) when _T_2755 : node _T_2756 = shl(UInt<5>(0h15), 3) node _T_2757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2756) node _T_2758 = bits(_T_2757, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2758 node _T_2759 = eq(UInt<4>(0he), idx_21) when _T_2759 : node _T_2760 = shl(UInt<5>(0h15), 3) node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760) node _T_2762 = bits(_T_2761, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2762 node _T_2763 = eq(UInt<4>(0hf), idx_21) when _T_2763 : node _T_2764 = shl(UInt<5>(0h15), 3) node _T_2765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2764) node _T_2766 = bits(_T_2765, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2766 node _T_2767 = eq(UInt<5>(0h10), idx_21) when _T_2767 : node _T_2768 = shl(UInt<5>(0h15), 3) node _T_2769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2768) node _T_2770 = bits(_T_2769, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2770 node _T_2771 = eq(UInt<5>(0h11), idx_21) when _T_2771 : node _T_2772 = shl(UInt<5>(0h15), 3) node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772) node _T_2774 = bits(_T_2773, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2774 node _T_2775 = eq(UInt<5>(0h12), idx_21) when _T_2775 : node _T_2776 = shl(UInt<5>(0h15), 3) node _T_2777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2776) node _T_2778 = bits(_T_2777, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2778 node _T_2779 = eq(UInt<5>(0h13), idx_21) when _T_2779 : node _T_2780 = shl(UInt<5>(0h15), 3) node _T_2781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2780) node _T_2782 = bits(_T_2781, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2782 node _T_2783 = eq(UInt<5>(0h14), idx_21) when _T_2783 : node _T_2784 = shl(UInt<5>(0h15), 3) node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784) node _T_2786 = bits(_T_2785, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2786 node _T_2787 = eq(UInt<5>(0h15), idx_21) when _T_2787 : node _T_2788 = shl(UInt<5>(0h15), 3) node _T_2789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2788) node _T_2790 = bits(_T_2789, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2790 node _T_2791 = eq(UInt<5>(0h16), idx_21) when _T_2791 : node _T_2792 = shl(UInt<5>(0h15), 3) node _T_2793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2792) node _T_2794 = bits(_T_2793, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2794 node _T_2795 = eq(UInt<5>(0h17), idx_21) when _T_2795 : node _T_2796 = shl(UInt<5>(0h15), 3) node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796) node _T_2798 = bits(_T_2797, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2798 node _T_2799 = eq(UInt<5>(0h18), idx_21) when _T_2799 : node _T_2800 = shl(UInt<5>(0h15), 3) node _T_2801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2800) node _T_2802 = bits(_T_2801, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2802 node _T_2803 = eq(UInt<5>(0h19), idx_21) when _T_2803 : node _T_2804 = shl(UInt<5>(0h15), 3) node _T_2805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2804) node _T_2806 = bits(_T_2805, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2806 node _T_2807 = eq(UInt<5>(0h1a), idx_21) when _T_2807 : node _T_2808 = shl(UInt<5>(0h15), 3) node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808) node _T_2810 = bits(_T_2809, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2810 node _T_2811 = eq(UInt<5>(0h1b), idx_21) when _T_2811 : node _T_2812 = shl(UInt<5>(0h15), 3) node _T_2813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2812) node _T_2814 = bits(_T_2813, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2814 node _T_2815 = eq(UInt<5>(0h1c), idx_21) when _T_2815 : node _T_2816 = shl(UInt<5>(0h15), 3) node _T_2817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2816) node _T_2818 = bits(_T_2817, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2818 node _T_2819 = eq(UInt<5>(0h1d), idx_21) when _T_2819 : node _T_2820 = shl(UInt<5>(0h15), 3) node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820) node _T_2822 = bits(_T_2821, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2822 node _T_2823 = eq(UInt<5>(0h1e), idx_21) when _T_2823 : node _T_2824 = shl(UInt<5>(0h15), 3) node _T_2825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2824) node _T_2826 = bits(_T_2825, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2826 node _T_2827 = eq(UInt<5>(0h1f), idx_21) when _T_2827 : node _T_2828 = shl(UInt<5>(0h15), 3) node _T_2829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2828) node _T_2830 = bits(_T_2829, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2830 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_2831 = eq(UInt<1>(0h0), idx_22) when _T_2831 : node _T_2832 = shl(UInt<5>(0h16), 3) node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832) node _T_2834 = bits(_T_2833, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2834 node _T_2835 = eq(UInt<1>(0h1), idx_22) when _T_2835 : node _T_2836 = shl(UInt<5>(0h16), 3) node _T_2837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2836) node _T_2838 = bits(_T_2837, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2838 node _T_2839 = eq(UInt<2>(0h2), idx_22) when _T_2839 : node _T_2840 = shl(UInt<5>(0h16), 3) node _T_2841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2840) node _T_2842 = bits(_T_2841, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2842 node _T_2843 = eq(UInt<2>(0h3), idx_22) when _T_2843 : node _T_2844 = shl(UInt<5>(0h16), 3) node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844) node _T_2846 = bits(_T_2845, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2846 node _T_2847 = eq(UInt<3>(0h4), idx_22) when _T_2847 : node _T_2848 = shl(UInt<5>(0h16), 3) node _T_2849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2848) node _T_2850 = bits(_T_2849, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2850 node _T_2851 = eq(UInt<3>(0h5), idx_22) when _T_2851 : node _T_2852 = shl(UInt<5>(0h16), 3) node _T_2853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2852) node _T_2854 = bits(_T_2853, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2854 node _T_2855 = eq(UInt<3>(0h6), idx_22) when _T_2855 : node _T_2856 = shl(UInt<5>(0h16), 3) node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856) node _T_2858 = bits(_T_2857, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2858 node _T_2859 = eq(UInt<3>(0h7), idx_22) when _T_2859 : node _T_2860 = shl(UInt<5>(0h16), 3) node _T_2861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2860) node _T_2862 = bits(_T_2861, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2862 node _T_2863 = eq(UInt<4>(0h8), idx_22) when _T_2863 : node _T_2864 = shl(UInt<5>(0h16), 3) node _T_2865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2864) node _T_2866 = bits(_T_2865, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2866 node _T_2867 = eq(UInt<4>(0h9), idx_22) when _T_2867 : node _T_2868 = shl(UInt<5>(0h16), 3) node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868) node _T_2870 = bits(_T_2869, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2870 node _T_2871 = eq(UInt<4>(0ha), idx_22) when _T_2871 : node _T_2872 = shl(UInt<5>(0h16), 3) node _T_2873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2872) node _T_2874 = bits(_T_2873, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2874 node _T_2875 = eq(UInt<4>(0hb), idx_22) when _T_2875 : node _T_2876 = shl(UInt<5>(0h16), 3) node _T_2877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2876) node _T_2878 = bits(_T_2877, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2878 node _T_2879 = eq(UInt<4>(0hc), idx_22) when _T_2879 : node _T_2880 = shl(UInt<5>(0h16), 3) node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880) node _T_2882 = bits(_T_2881, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2882 node _T_2883 = eq(UInt<4>(0hd), idx_22) when _T_2883 : node _T_2884 = shl(UInt<5>(0h16), 3) node _T_2885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2884) node _T_2886 = bits(_T_2885, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2886 node _T_2887 = eq(UInt<4>(0he), idx_22) when _T_2887 : node _T_2888 = shl(UInt<5>(0h16), 3) node _T_2889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2888) node _T_2890 = bits(_T_2889, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2890 node _T_2891 = eq(UInt<4>(0hf), idx_22) when _T_2891 : node _T_2892 = shl(UInt<5>(0h16), 3) node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892) node _T_2894 = bits(_T_2893, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2894 node _T_2895 = eq(UInt<5>(0h10), idx_22) when _T_2895 : node _T_2896 = shl(UInt<5>(0h16), 3) node _T_2897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2896) node _T_2898 = bits(_T_2897, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2898 node _T_2899 = eq(UInt<5>(0h11), idx_22) when _T_2899 : node _T_2900 = shl(UInt<5>(0h16), 3) node _T_2901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2900) node _T_2902 = bits(_T_2901, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2902 node _T_2903 = eq(UInt<5>(0h12), idx_22) when _T_2903 : node _T_2904 = shl(UInt<5>(0h16), 3) node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904) node _T_2906 = bits(_T_2905, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2906 node _T_2907 = eq(UInt<5>(0h13), idx_22) when _T_2907 : node _T_2908 = shl(UInt<5>(0h16), 3) node _T_2909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2908) node _T_2910 = bits(_T_2909, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2910 node _T_2911 = eq(UInt<5>(0h14), idx_22) when _T_2911 : node _T_2912 = shl(UInt<5>(0h16), 3) node _T_2913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2912) node _T_2914 = bits(_T_2913, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2914 node _T_2915 = eq(UInt<5>(0h15), idx_22) when _T_2915 : node _T_2916 = shl(UInt<5>(0h16), 3) node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916) node _T_2918 = bits(_T_2917, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2918 node _T_2919 = eq(UInt<5>(0h16), idx_22) when _T_2919 : node _T_2920 = shl(UInt<5>(0h16), 3) node _T_2921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2920) node _T_2922 = bits(_T_2921, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2922 node _T_2923 = eq(UInt<5>(0h17), idx_22) when _T_2923 : node _T_2924 = shl(UInt<5>(0h16), 3) node _T_2925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2924) node _T_2926 = bits(_T_2925, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2926 node _T_2927 = eq(UInt<5>(0h18), idx_22) when _T_2927 : node _T_2928 = shl(UInt<5>(0h16), 3) node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928) node _T_2930 = bits(_T_2929, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2930 node _T_2931 = eq(UInt<5>(0h19), idx_22) when _T_2931 : node _T_2932 = shl(UInt<5>(0h16), 3) node _T_2933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2932) node _T_2934 = bits(_T_2933, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2934 node _T_2935 = eq(UInt<5>(0h1a), idx_22) when _T_2935 : node _T_2936 = shl(UInt<5>(0h16), 3) node _T_2937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2936) node _T_2938 = bits(_T_2937, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2938 node _T_2939 = eq(UInt<5>(0h1b), idx_22) when _T_2939 : node _T_2940 = shl(UInt<5>(0h16), 3) node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940) node _T_2942 = bits(_T_2941, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2942 node _T_2943 = eq(UInt<5>(0h1c), idx_22) when _T_2943 : node _T_2944 = shl(UInt<5>(0h16), 3) node _T_2945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2944) node _T_2946 = bits(_T_2945, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2946 node _T_2947 = eq(UInt<5>(0h1d), idx_22) when _T_2947 : node _T_2948 = shl(UInt<5>(0h16), 3) node _T_2949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2948) node _T_2950 = bits(_T_2949, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2950 node _T_2951 = eq(UInt<5>(0h1e), idx_22) when _T_2951 : node _T_2952 = shl(UInt<5>(0h16), 3) node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952) node _T_2954 = bits(_T_2953, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2954 node _T_2955 = eq(UInt<5>(0h1f), idx_22) when _T_2955 : node _T_2956 = shl(UInt<5>(0h16), 3) node _T_2957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2956) node _T_2958 = bits(_T_2957, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2958 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_2959 = eq(UInt<1>(0h0), idx_23) when _T_2959 : node _T_2960 = shl(UInt<5>(0h17), 3) node _T_2961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2960) node _T_2962 = bits(_T_2961, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2962 node _T_2963 = eq(UInt<1>(0h1), idx_23) when _T_2963 : node _T_2964 = shl(UInt<5>(0h17), 3) node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964) node _T_2966 = bits(_T_2965, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2966 node _T_2967 = eq(UInt<2>(0h2), idx_23) when _T_2967 : node _T_2968 = shl(UInt<5>(0h17), 3) node _T_2969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2968) node _T_2970 = bits(_T_2969, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2970 node _T_2971 = eq(UInt<2>(0h3), idx_23) when _T_2971 : node _T_2972 = shl(UInt<5>(0h17), 3) node _T_2973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2972) node _T_2974 = bits(_T_2973, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2974 node _T_2975 = eq(UInt<3>(0h4), idx_23) when _T_2975 : node _T_2976 = shl(UInt<5>(0h17), 3) node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976) node _T_2978 = bits(_T_2977, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2978 node _T_2979 = eq(UInt<3>(0h5), idx_23) when _T_2979 : node _T_2980 = shl(UInt<5>(0h17), 3) node _T_2981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2980) node _T_2982 = bits(_T_2981, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2982 node _T_2983 = eq(UInt<3>(0h6), idx_23) when _T_2983 : node _T_2984 = shl(UInt<5>(0h17), 3) node _T_2985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2984) node _T_2986 = bits(_T_2985, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2986 node _T_2987 = eq(UInt<3>(0h7), idx_23) when _T_2987 : node _T_2988 = shl(UInt<5>(0h17), 3) node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988) node _T_2990 = bits(_T_2989, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2990 node _T_2991 = eq(UInt<4>(0h8), idx_23) when _T_2991 : node _T_2992 = shl(UInt<5>(0h17), 3) node _T_2993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2992) node _T_2994 = bits(_T_2993, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2994 node _T_2995 = eq(UInt<4>(0h9), idx_23) when _T_2995 : node _T_2996 = shl(UInt<5>(0h17), 3) node _T_2997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2996) node _T_2998 = bits(_T_2997, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2998 node _T_2999 = eq(UInt<4>(0ha), idx_23) when _T_2999 : node _T_3000 = shl(UInt<5>(0h17), 3) node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000) node _T_3002 = bits(_T_3001, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3002 node _T_3003 = eq(UInt<4>(0hb), idx_23) when _T_3003 : node _T_3004 = shl(UInt<5>(0h17), 3) node _T_3005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3004) node _T_3006 = bits(_T_3005, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3006 node _T_3007 = eq(UInt<4>(0hc), idx_23) when _T_3007 : node _T_3008 = shl(UInt<5>(0h17), 3) node _T_3009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3008) node _T_3010 = bits(_T_3009, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3010 node _T_3011 = eq(UInt<4>(0hd), idx_23) when _T_3011 : node _T_3012 = shl(UInt<5>(0h17), 3) node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012) node _T_3014 = bits(_T_3013, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3014 node _T_3015 = eq(UInt<4>(0he), idx_23) when _T_3015 : node _T_3016 = shl(UInt<5>(0h17), 3) node _T_3017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3016) node _T_3018 = bits(_T_3017, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3018 node _T_3019 = eq(UInt<4>(0hf), idx_23) when _T_3019 : node _T_3020 = shl(UInt<5>(0h17), 3) node _T_3021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3020) node _T_3022 = bits(_T_3021, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3022 node _T_3023 = eq(UInt<5>(0h10), idx_23) when _T_3023 : node _T_3024 = shl(UInt<5>(0h17), 3) node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024) node _T_3026 = bits(_T_3025, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3026 node _T_3027 = eq(UInt<5>(0h11), idx_23) when _T_3027 : node _T_3028 = shl(UInt<5>(0h17), 3) node _T_3029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3028) node _T_3030 = bits(_T_3029, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3030 node _T_3031 = eq(UInt<5>(0h12), idx_23) when _T_3031 : node _T_3032 = shl(UInt<5>(0h17), 3) node _T_3033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3032) node _T_3034 = bits(_T_3033, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3034 node _T_3035 = eq(UInt<5>(0h13), idx_23) when _T_3035 : node _T_3036 = shl(UInt<5>(0h17), 3) node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036) node _T_3038 = bits(_T_3037, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3038 node _T_3039 = eq(UInt<5>(0h14), idx_23) when _T_3039 : node _T_3040 = shl(UInt<5>(0h17), 3) node _T_3041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3040) node _T_3042 = bits(_T_3041, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3042 node _T_3043 = eq(UInt<5>(0h15), idx_23) when _T_3043 : node _T_3044 = shl(UInt<5>(0h17), 3) node _T_3045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3044) node _T_3046 = bits(_T_3045, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3046 node _T_3047 = eq(UInt<5>(0h16), idx_23) when _T_3047 : node _T_3048 = shl(UInt<5>(0h17), 3) node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048) node _T_3050 = bits(_T_3049, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3050 node _T_3051 = eq(UInt<5>(0h17), idx_23) when _T_3051 : node _T_3052 = shl(UInt<5>(0h17), 3) node _T_3053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3052) node _T_3054 = bits(_T_3053, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3054 node _T_3055 = eq(UInt<5>(0h18), idx_23) when _T_3055 : node _T_3056 = shl(UInt<5>(0h17), 3) node _T_3057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3056) node _T_3058 = bits(_T_3057, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3058 node _T_3059 = eq(UInt<5>(0h19), idx_23) when _T_3059 : node _T_3060 = shl(UInt<5>(0h17), 3) node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060) node _T_3062 = bits(_T_3061, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3062 node _T_3063 = eq(UInt<5>(0h1a), idx_23) when _T_3063 : node _T_3064 = shl(UInt<5>(0h17), 3) node _T_3065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3064) node _T_3066 = bits(_T_3065, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3066 node _T_3067 = eq(UInt<5>(0h1b), idx_23) when _T_3067 : node _T_3068 = shl(UInt<5>(0h17), 3) node _T_3069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3068) node _T_3070 = bits(_T_3069, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3070 node _T_3071 = eq(UInt<5>(0h1c), idx_23) when _T_3071 : node _T_3072 = shl(UInt<5>(0h17), 3) node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072) node _T_3074 = bits(_T_3073, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3074 node _T_3075 = eq(UInt<5>(0h1d), idx_23) when _T_3075 : node _T_3076 = shl(UInt<5>(0h17), 3) node _T_3077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3076) node _T_3078 = bits(_T_3077, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3078 node _T_3079 = eq(UInt<5>(0h1e), idx_23) when _T_3079 : node _T_3080 = shl(UInt<5>(0h17), 3) node _T_3081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3080) node _T_3082 = bits(_T_3081, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3082 node _T_3083 = eq(UInt<5>(0h1f), idx_23) when _T_3083 : node _T_3084 = shl(UInt<5>(0h17), 3) node _T_3085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3084) node _T_3086 = bits(_T_3085, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3086 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_3087 = eq(UInt<1>(0h0), idx_24) when _T_3087 : node _T_3088 = shl(UInt<5>(0h18), 3) node _T_3089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3088) node _T_3090 = bits(_T_3089, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3090 node _T_3091 = eq(UInt<1>(0h1), idx_24) when _T_3091 : node _T_3092 = shl(UInt<5>(0h18), 3) node _T_3093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3092) node _T_3094 = bits(_T_3093, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3094 node _T_3095 = eq(UInt<2>(0h2), idx_24) when _T_3095 : node _T_3096 = shl(UInt<5>(0h18), 3) node _T_3097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3096) node _T_3098 = bits(_T_3097, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3098 node _T_3099 = eq(UInt<2>(0h3), idx_24) when _T_3099 : node _T_3100 = shl(UInt<5>(0h18), 3) node _T_3101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3100) node _T_3102 = bits(_T_3101, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3102 node _T_3103 = eq(UInt<3>(0h4), idx_24) when _T_3103 : node _T_3104 = shl(UInt<5>(0h18), 3) node _T_3105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3104) node _T_3106 = bits(_T_3105, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3106 node _T_3107 = eq(UInt<3>(0h5), idx_24) when _T_3107 : node _T_3108 = shl(UInt<5>(0h18), 3) node _T_3109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3108) node _T_3110 = bits(_T_3109, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3110 node _T_3111 = eq(UInt<3>(0h6), idx_24) when _T_3111 : node _T_3112 = shl(UInt<5>(0h18), 3) node _T_3113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3112) node _T_3114 = bits(_T_3113, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3114 node _T_3115 = eq(UInt<3>(0h7), idx_24) when _T_3115 : node _T_3116 = shl(UInt<5>(0h18), 3) node _T_3117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3116) node _T_3118 = bits(_T_3117, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3118 node _T_3119 = eq(UInt<4>(0h8), idx_24) when _T_3119 : node _T_3120 = shl(UInt<5>(0h18), 3) node _T_3121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3120) node _T_3122 = bits(_T_3121, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3122 node _T_3123 = eq(UInt<4>(0h9), idx_24) when _T_3123 : node _T_3124 = shl(UInt<5>(0h18), 3) node _T_3125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3124) node _T_3126 = bits(_T_3125, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3126 node _T_3127 = eq(UInt<4>(0ha), idx_24) when _T_3127 : node _T_3128 = shl(UInt<5>(0h18), 3) node _T_3129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3128) node _T_3130 = bits(_T_3129, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3130 node _T_3131 = eq(UInt<4>(0hb), idx_24) when _T_3131 : node _T_3132 = shl(UInt<5>(0h18), 3) node _T_3133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3132) node _T_3134 = bits(_T_3133, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3134 node _T_3135 = eq(UInt<4>(0hc), idx_24) when _T_3135 : node _T_3136 = shl(UInt<5>(0h18), 3) node _T_3137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3136) node _T_3138 = bits(_T_3137, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3138 node _T_3139 = eq(UInt<4>(0hd), idx_24) when _T_3139 : node _T_3140 = shl(UInt<5>(0h18), 3) node _T_3141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3140) node _T_3142 = bits(_T_3141, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3142 node _T_3143 = eq(UInt<4>(0he), idx_24) when _T_3143 : node _T_3144 = shl(UInt<5>(0h18), 3) node _T_3145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3144) node _T_3146 = bits(_T_3145, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3146 node _T_3147 = eq(UInt<4>(0hf), idx_24) when _T_3147 : node _T_3148 = shl(UInt<5>(0h18), 3) node _T_3149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3148) node _T_3150 = bits(_T_3149, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3150 node _T_3151 = eq(UInt<5>(0h10), idx_24) when _T_3151 : node _T_3152 = shl(UInt<5>(0h18), 3) node _T_3153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3152) node _T_3154 = bits(_T_3153, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3154 node _T_3155 = eq(UInt<5>(0h11), idx_24) when _T_3155 : node _T_3156 = shl(UInt<5>(0h18), 3) node _T_3157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3156) node _T_3158 = bits(_T_3157, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3158 node _T_3159 = eq(UInt<5>(0h12), idx_24) when _T_3159 : node _T_3160 = shl(UInt<5>(0h18), 3) node _T_3161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3160) node _T_3162 = bits(_T_3161, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3162 node _T_3163 = eq(UInt<5>(0h13), idx_24) when _T_3163 : node _T_3164 = shl(UInt<5>(0h18), 3) node _T_3165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3164) node _T_3166 = bits(_T_3165, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3166 node _T_3167 = eq(UInt<5>(0h14), idx_24) when _T_3167 : node _T_3168 = shl(UInt<5>(0h18), 3) node _T_3169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3168) node _T_3170 = bits(_T_3169, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3170 node _T_3171 = eq(UInt<5>(0h15), idx_24) when _T_3171 : node _T_3172 = shl(UInt<5>(0h18), 3) node _T_3173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3172) node _T_3174 = bits(_T_3173, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3174 node _T_3175 = eq(UInt<5>(0h16), idx_24) when _T_3175 : node _T_3176 = shl(UInt<5>(0h18), 3) node _T_3177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3176) node _T_3178 = bits(_T_3177, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3178 node _T_3179 = eq(UInt<5>(0h17), idx_24) when _T_3179 : node _T_3180 = shl(UInt<5>(0h18), 3) node _T_3181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3180) node _T_3182 = bits(_T_3181, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3182 node _T_3183 = eq(UInt<5>(0h18), idx_24) when _T_3183 : node _T_3184 = shl(UInt<5>(0h18), 3) node _T_3185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3184) node _T_3186 = bits(_T_3185, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3186 node _T_3187 = eq(UInt<5>(0h19), idx_24) when _T_3187 : node _T_3188 = shl(UInt<5>(0h18), 3) node _T_3189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3188) node _T_3190 = bits(_T_3189, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3190 node _T_3191 = eq(UInt<5>(0h1a), idx_24) when _T_3191 : node _T_3192 = shl(UInt<5>(0h18), 3) node _T_3193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3192) node _T_3194 = bits(_T_3193, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3194 node _T_3195 = eq(UInt<5>(0h1b), idx_24) when _T_3195 : node _T_3196 = shl(UInt<5>(0h18), 3) node _T_3197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3196) node _T_3198 = bits(_T_3197, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3198 node _T_3199 = eq(UInt<5>(0h1c), idx_24) when _T_3199 : node _T_3200 = shl(UInt<5>(0h18), 3) node _T_3201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3200) node _T_3202 = bits(_T_3201, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3202 node _T_3203 = eq(UInt<5>(0h1d), idx_24) when _T_3203 : node _T_3204 = shl(UInt<5>(0h18), 3) node _T_3205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3204) node _T_3206 = bits(_T_3205, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3206 node _T_3207 = eq(UInt<5>(0h1e), idx_24) when _T_3207 : node _T_3208 = shl(UInt<5>(0h18), 3) node _T_3209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3208) node _T_3210 = bits(_T_3209, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3210 node _T_3211 = eq(UInt<5>(0h1f), idx_24) when _T_3211 : node _T_3212 = shl(UInt<5>(0h18), 3) node _T_3213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3212) node _T_3214 = bits(_T_3213, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3214 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_3215 = eq(UInt<1>(0h0), idx_25) when _T_3215 : node _T_3216 = shl(UInt<5>(0h19), 3) node _T_3217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3216) node _T_3218 = bits(_T_3217, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3218 node _T_3219 = eq(UInt<1>(0h1), idx_25) when _T_3219 : node _T_3220 = shl(UInt<5>(0h19), 3) node _T_3221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3220) node _T_3222 = bits(_T_3221, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3222 node _T_3223 = eq(UInt<2>(0h2), idx_25) when _T_3223 : node _T_3224 = shl(UInt<5>(0h19), 3) node _T_3225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3224) node _T_3226 = bits(_T_3225, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3226 node _T_3227 = eq(UInt<2>(0h3), idx_25) when _T_3227 : node _T_3228 = shl(UInt<5>(0h19), 3) node _T_3229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3228) node _T_3230 = bits(_T_3229, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3230 node _T_3231 = eq(UInt<3>(0h4), idx_25) when _T_3231 : node _T_3232 = shl(UInt<5>(0h19), 3) node _T_3233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3232) node _T_3234 = bits(_T_3233, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3234 node _T_3235 = eq(UInt<3>(0h5), idx_25) when _T_3235 : node _T_3236 = shl(UInt<5>(0h19), 3) node _T_3237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3236) node _T_3238 = bits(_T_3237, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3238 node _T_3239 = eq(UInt<3>(0h6), idx_25) when _T_3239 : node _T_3240 = shl(UInt<5>(0h19), 3) node _T_3241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3240) node _T_3242 = bits(_T_3241, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3242 node _T_3243 = eq(UInt<3>(0h7), idx_25) when _T_3243 : node _T_3244 = shl(UInt<5>(0h19), 3) node _T_3245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3244) node _T_3246 = bits(_T_3245, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3246 node _T_3247 = eq(UInt<4>(0h8), idx_25) when _T_3247 : node _T_3248 = shl(UInt<5>(0h19), 3) node _T_3249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3248) node _T_3250 = bits(_T_3249, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3250 node _T_3251 = eq(UInt<4>(0h9), idx_25) when _T_3251 : node _T_3252 = shl(UInt<5>(0h19), 3) node _T_3253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3252) node _T_3254 = bits(_T_3253, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3254 node _T_3255 = eq(UInt<4>(0ha), idx_25) when _T_3255 : node _T_3256 = shl(UInt<5>(0h19), 3) node _T_3257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3256) node _T_3258 = bits(_T_3257, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3258 node _T_3259 = eq(UInt<4>(0hb), idx_25) when _T_3259 : node _T_3260 = shl(UInt<5>(0h19), 3) node _T_3261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3260) node _T_3262 = bits(_T_3261, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3262 node _T_3263 = eq(UInt<4>(0hc), idx_25) when _T_3263 : node _T_3264 = shl(UInt<5>(0h19), 3) node _T_3265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3264) node _T_3266 = bits(_T_3265, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3266 node _T_3267 = eq(UInt<4>(0hd), idx_25) when _T_3267 : node _T_3268 = shl(UInt<5>(0h19), 3) node _T_3269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3268) node _T_3270 = bits(_T_3269, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3270 node _T_3271 = eq(UInt<4>(0he), idx_25) when _T_3271 : node _T_3272 = shl(UInt<5>(0h19), 3) node _T_3273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3272) node _T_3274 = bits(_T_3273, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3274 node _T_3275 = eq(UInt<4>(0hf), idx_25) when _T_3275 : node _T_3276 = shl(UInt<5>(0h19), 3) node _T_3277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3276) node _T_3278 = bits(_T_3277, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3278 node _T_3279 = eq(UInt<5>(0h10), idx_25) when _T_3279 : node _T_3280 = shl(UInt<5>(0h19), 3) node _T_3281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3280) node _T_3282 = bits(_T_3281, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3282 node _T_3283 = eq(UInt<5>(0h11), idx_25) when _T_3283 : node _T_3284 = shl(UInt<5>(0h19), 3) node _T_3285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3284) node _T_3286 = bits(_T_3285, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3286 node _T_3287 = eq(UInt<5>(0h12), idx_25) when _T_3287 : node _T_3288 = shl(UInt<5>(0h19), 3) node _T_3289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3288) node _T_3290 = bits(_T_3289, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3290 node _T_3291 = eq(UInt<5>(0h13), idx_25) when _T_3291 : node _T_3292 = shl(UInt<5>(0h19), 3) node _T_3293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3292) node _T_3294 = bits(_T_3293, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3294 node _T_3295 = eq(UInt<5>(0h14), idx_25) when _T_3295 : node _T_3296 = shl(UInt<5>(0h19), 3) node _T_3297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3296) node _T_3298 = bits(_T_3297, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3298 node _T_3299 = eq(UInt<5>(0h15), idx_25) when _T_3299 : node _T_3300 = shl(UInt<5>(0h19), 3) node _T_3301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3300) node _T_3302 = bits(_T_3301, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3302 node _T_3303 = eq(UInt<5>(0h16), idx_25) when _T_3303 : node _T_3304 = shl(UInt<5>(0h19), 3) node _T_3305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3304) node _T_3306 = bits(_T_3305, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3306 node _T_3307 = eq(UInt<5>(0h17), idx_25) when _T_3307 : node _T_3308 = shl(UInt<5>(0h19), 3) node _T_3309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3308) node _T_3310 = bits(_T_3309, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3310 node _T_3311 = eq(UInt<5>(0h18), idx_25) when _T_3311 : node _T_3312 = shl(UInt<5>(0h19), 3) node _T_3313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3312) node _T_3314 = bits(_T_3313, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3314 node _T_3315 = eq(UInt<5>(0h19), idx_25) when _T_3315 : node _T_3316 = shl(UInt<5>(0h19), 3) node _T_3317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3316) node _T_3318 = bits(_T_3317, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3318 node _T_3319 = eq(UInt<5>(0h1a), idx_25) when _T_3319 : node _T_3320 = shl(UInt<5>(0h19), 3) node _T_3321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3320) node _T_3322 = bits(_T_3321, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3322 node _T_3323 = eq(UInt<5>(0h1b), idx_25) when _T_3323 : node _T_3324 = shl(UInt<5>(0h19), 3) node _T_3325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3324) node _T_3326 = bits(_T_3325, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3326 node _T_3327 = eq(UInt<5>(0h1c), idx_25) when _T_3327 : node _T_3328 = shl(UInt<5>(0h19), 3) node _T_3329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3328) node _T_3330 = bits(_T_3329, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3330 node _T_3331 = eq(UInt<5>(0h1d), idx_25) when _T_3331 : node _T_3332 = shl(UInt<5>(0h19), 3) node _T_3333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3332) node _T_3334 = bits(_T_3333, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3334 node _T_3335 = eq(UInt<5>(0h1e), idx_25) when _T_3335 : node _T_3336 = shl(UInt<5>(0h19), 3) node _T_3337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3336) node _T_3338 = bits(_T_3337, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3338 node _T_3339 = eq(UInt<5>(0h1f), idx_25) when _T_3339 : node _T_3340 = shl(UInt<5>(0h19), 3) node _T_3341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3340) node _T_3342 = bits(_T_3341, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3342 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_3343 = eq(UInt<1>(0h0), idx_26) when _T_3343 : node _T_3344 = shl(UInt<5>(0h1a), 3) node _T_3345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3344) node _T_3346 = bits(_T_3345, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3346 node _T_3347 = eq(UInt<1>(0h1), idx_26) when _T_3347 : node _T_3348 = shl(UInt<5>(0h1a), 3) node _T_3349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3348) node _T_3350 = bits(_T_3349, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3350 node _T_3351 = eq(UInt<2>(0h2), idx_26) when _T_3351 : node _T_3352 = shl(UInt<5>(0h1a), 3) node _T_3353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3352) node _T_3354 = bits(_T_3353, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3354 node _T_3355 = eq(UInt<2>(0h3), idx_26) when _T_3355 : node _T_3356 = shl(UInt<5>(0h1a), 3) node _T_3357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3356) node _T_3358 = bits(_T_3357, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3358 node _T_3359 = eq(UInt<3>(0h4), idx_26) when _T_3359 : node _T_3360 = shl(UInt<5>(0h1a), 3) node _T_3361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3360) node _T_3362 = bits(_T_3361, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3362 node _T_3363 = eq(UInt<3>(0h5), idx_26) when _T_3363 : node _T_3364 = shl(UInt<5>(0h1a), 3) node _T_3365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3364) node _T_3366 = bits(_T_3365, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3366 node _T_3367 = eq(UInt<3>(0h6), idx_26) when _T_3367 : node _T_3368 = shl(UInt<5>(0h1a), 3) node _T_3369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3368) node _T_3370 = bits(_T_3369, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3370 node _T_3371 = eq(UInt<3>(0h7), idx_26) when _T_3371 : node _T_3372 = shl(UInt<5>(0h1a), 3) node _T_3373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3372) node _T_3374 = bits(_T_3373, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3374 node _T_3375 = eq(UInt<4>(0h8), idx_26) when _T_3375 : node _T_3376 = shl(UInt<5>(0h1a), 3) node _T_3377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3376) node _T_3378 = bits(_T_3377, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3378 node _T_3379 = eq(UInt<4>(0h9), idx_26) when _T_3379 : node _T_3380 = shl(UInt<5>(0h1a), 3) node _T_3381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3380) node _T_3382 = bits(_T_3381, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3382 node _T_3383 = eq(UInt<4>(0ha), idx_26) when _T_3383 : node _T_3384 = shl(UInt<5>(0h1a), 3) node _T_3385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3384) node _T_3386 = bits(_T_3385, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3386 node _T_3387 = eq(UInt<4>(0hb), idx_26) when _T_3387 : node _T_3388 = shl(UInt<5>(0h1a), 3) node _T_3389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3388) node _T_3390 = bits(_T_3389, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3390 node _T_3391 = eq(UInt<4>(0hc), idx_26) when _T_3391 : node _T_3392 = shl(UInt<5>(0h1a), 3) node _T_3393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3392) node _T_3394 = bits(_T_3393, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3394 node _T_3395 = eq(UInt<4>(0hd), idx_26) when _T_3395 : node _T_3396 = shl(UInt<5>(0h1a), 3) node _T_3397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3396) node _T_3398 = bits(_T_3397, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3398 node _T_3399 = eq(UInt<4>(0he), idx_26) when _T_3399 : node _T_3400 = shl(UInt<5>(0h1a), 3) node _T_3401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3400) node _T_3402 = bits(_T_3401, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3402 node _T_3403 = eq(UInt<4>(0hf), idx_26) when _T_3403 : node _T_3404 = shl(UInt<5>(0h1a), 3) node _T_3405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3404) node _T_3406 = bits(_T_3405, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3406 node _T_3407 = eq(UInt<5>(0h10), idx_26) when _T_3407 : node _T_3408 = shl(UInt<5>(0h1a), 3) node _T_3409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3408) node _T_3410 = bits(_T_3409, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3410 node _T_3411 = eq(UInt<5>(0h11), idx_26) when _T_3411 : node _T_3412 = shl(UInt<5>(0h1a), 3) node _T_3413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3412) node _T_3414 = bits(_T_3413, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3414 node _T_3415 = eq(UInt<5>(0h12), idx_26) when _T_3415 : node _T_3416 = shl(UInt<5>(0h1a), 3) node _T_3417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3416) node _T_3418 = bits(_T_3417, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3418 node _T_3419 = eq(UInt<5>(0h13), idx_26) when _T_3419 : node _T_3420 = shl(UInt<5>(0h1a), 3) node _T_3421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3420) node _T_3422 = bits(_T_3421, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3422 node _T_3423 = eq(UInt<5>(0h14), idx_26) when _T_3423 : node _T_3424 = shl(UInt<5>(0h1a), 3) node _T_3425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3424) node _T_3426 = bits(_T_3425, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3426 node _T_3427 = eq(UInt<5>(0h15), idx_26) when _T_3427 : node _T_3428 = shl(UInt<5>(0h1a), 3) node _T_3429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3428) node _T_3430 = bits(_T_3429, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3430 node _T_3431 = eq(UInt<5>(0h16), idx_26) when _T_3431 : node _T_3432 = shl(UInt<5>(0h1a), 3) node _T_3433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3432) node _T_3434 = bits(_T_3433, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3434 node _T_3435 = eq(UInt<5>(0h17), idx_26) when _T_3435 : node _T_3436 = shl(UInt<5>(0h1a), 3) node _T_3437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3436) node _T_3438 = bits(_T_3437, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3438 node _T_3439 = eq(UInt<5>(0h18), idx_26) when _T_3439 : node _T_3440 = shl(UInt<5>(0h1a), 3) node _T_3441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3440) node _T_3442 = bits(_T_3441, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3442 node _T_3443 = eq(UInt<5>(0h19), idx_26) when _T_3443 : node _T_3444 = shl(UInt<5>(0h1a), 3) node _T_3445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3444) node _T_3446 = bits(_T_3445, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3446 node _T_3447 = eq(UInt<5>(0h1a), idx_26) when _T_3447 : node _T_3448 = shl(UInt<5>(0h1a), 3) node _T_3449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3448) node _T_3450 = bits(_T_3449, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3450 node _T_3451 = eq(UInt<5>(0h1b), idx_26) when _T_3451 : node _T_3452 = shl(UInt<5>(0h1a), 3) node _T_3453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3452) node _T_3454 = bits(_T_3453, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3454 node _T_3455 = eq(UInt<5>(0h1c), idx_26) when _T_3455 : node _T_3456 = shl(UInt<5>(0h1a), 3) node _T_3457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3456) node _T_3458 = bits(_T_3457, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3458 node _T_3459 = eq(UInt<5>(0h1d), idx_26) when _T_3459 : node _T_3460 = shl(UInt<5>(0h1a), 3) node _T_3461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3460) node _T_3462 = bits(_T_3461, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3462 node _T_3463 = eq(UInt<5>(0h1e), idx_26) when _T_3463 : node _T_3464 = shl(UInt<5>(0h1a), 3) node _T_3465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3464) node _T_3466 = bits(_T_3465, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3466 node _T_3467 = eq(UInt<5>(0h1f), idx_26) when _T_3467 : node _T_3468 = shl(UInt<5>(0h1a), 3) node _T_3469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3468) node _T_3470 = bits(_T_3469, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3470 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_3471 = eq(UInt<1>(0h0), idx_27) when _T_3471 : node _T_3472 = shl(UInt<5>(0h1b), 3) node _T_3473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3472) node _T_3474 = bits(_T_3473, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3474 node _T_3475 = eq(UInt<1>(0h1), idx_27) when _T_3475 : node _T_3476 = shl(UInt<5>(0h1b), 3) node _T_3477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3476) node _T_3478 = bits(_T_3477, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3478 node _T_3479 = eq(UInt<2>(0h2), idx_27) when _T_3479 : node _T_3480 = shl(UInt<5>(0h1b), 3) node _T_3481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3480) node _T_3482 = bits(_T_3481, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3482 node _T_3483 = eq(UInt<2>(0h3), idx_27) when _T_3483 : node _T_3484 = shl(UInt<5>(0h1b), 3) node _T_3485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3484) node _T_3486 = bits(_T_3485, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3486 node _T_3487 = eq(UInt<3>(0h4), idx_27) when _T_3487 : node _T_3488 = shl(UInt<5>(0h1b), 3) node _T_3489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3488) node _T_3490 = bits(_T_3489, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3490 node _T_3491 = eq(UInt<3>(0h5), idx_27) when _T_3491 : node _T_3492 = shl(UInt<5>(0h1b), 3) node _T_3493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3492) node _T_3494 = bits(_T_3493, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3494 node _T_3495 = eq(UInt<3>(0h6), idx_27) when _T_3495 : node _T_3496 = shl(UInt<5>(0h1b), 3) node _T_3497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3496) node _T_3498 = bits(_T_3497, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3498 node _T_3499 = eq(UInt<3>(0h7), idx_27) when _T_3499 : node _T_3500 = shl(UInt<5>(0h1b), 3) node _T_3501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3500) node _T_3502 = bits(_T_3501, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3502 node _T_3503 = eq(UInt<4>(0h8), idx_27) when _T_3503 : node _T_3504 = shl(UInt<5>(0h1b), 3) node _T_3505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3504) node _T_3506 = bits(_T_3505, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3506 node _T_3507 = eq(UInt<4>(0h9), idx_27) when _T_3507 : node _T_3508 = shl(UInt<5>(0h1b), 3) node _T_3509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3508) node _T_3510 = bits(_T_3509, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3510 node _T_3511 = eq(UInt<4>(0ha), idx_27) when _T_3511 : node _T_3512 = shl(UInt<5>(0h1b), 3) node _T_3513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3512) node _T_3514 = bits(_T_3513, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3514 node _T_3515 = eq(UInt<4>(0hb), idx_27) when _T_3515 : node _T_3516 = shl(UInt<5>(0h1b), 3) node _T_3517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3516) node _T_3518 = bits(_T_3517, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3518 node _T_3519 = eq(UInt<4>(0hc), idx_27) when _T_3519 : node _T_3520 = shl(UInt<5>(0h1b), 3) node _T_3521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3520) node _T_3522 = bits(_T_3521, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3522 node _T_3523 = eq(UInt<4>(0hd), idx_27) when _T_3523 : node _T_3524 = shl(UInt<5>(0h1b), 3) node _T_3525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3524) node _T_3526 = bits(_T_3525, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3526 node _T_3527 = eq(UInt<4>(0he), idx_27) when _T_3527 : node _T_3528 = shl(UInt<5>(0h1b), 3) node _T_3529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3528) node _T_3530 = bits(_T_3529, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3530 node _T_3531 = eq(UInt<4>(0hf), idx_27) when _T_3531 : node _T_3532 = shl(UInt<5>(0h1b), 3) node _T_3533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3532) node _T_3534 = bits(_T_3533, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3534 node _T_3535 = eq(UInt<5>(0h10), idx_27) when _T_3535 : node _T_3536 = shl(UInt<5>(0h1b), 3) node _T_3537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3536) node _T_3538 = bits(_T_3537, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3538 node _T_3539 = eq(UInt<5>(0h11), idx_27) when _T_3539 : node _T_3540 = shl(UInt<5>(0h1b), 3) node _T_3541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3540) node _T_3542 = bits(_T_3541, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3542 node _T_3543 = eq(UInt<5>(0h12), idx_27) when _T_3543 : node _T_3544 = shl(UInt<5>(0h1b), 3) node _T_3545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3544) node _T_3546 = bits(_T_3545, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3546 node _T_3547 = eq(UInt<5>(0h13), idx_27) when _T_3547 : node _T_3548 = shl(UInt<5>(0h1b), 3) node _T_3549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3548) node _T_3550 = bits(_T_3549, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3550 node _T_3551 = eq(UInt<5>(0h14), idx_27) when _T_3551 : node _T_3552 = shl(UInt<5>(0h1b), 3) node _T_3553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3552) node _T_3554 = bits(_T_3553, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3554 node _T_3555 = eq(UInt<5>(0h15), idx_27) when _T_3555 : node _T_3556 = shl(UInt<5>(0h1b), 3) node _T_3557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3556) node _T_3558 = bits(_T_3557, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3558 node _T_3559 = eq(UInt<5>(0h16), idx_27) when _T_3559 : node _T_3560 = shl(UInt<5>(0h1b), 3) node _T_3561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3560) node _T_3562 = bits(_T_3561, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3562 node _T_3563 = eq(UInt<5>(0h17), idx_27) when _T_3563 : node _T_3564 = shl(UInt<5>(0h1b), 3) node _T_3565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3564) node _T_3566 = bits(_T_3565, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3566 node _T_3567 = eq(UInt<5>(0h18), idx_27) when _T_3567 : node _T_3568 = shl(UInt<5>(0h1b), 3) node _T_3569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3568) node _T_3570 = bits(_T_3569, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3570 node _T_3571 = eq(UInt<5>(0h19), idx_27) when _T_3571 : node _T_3572 = shl(UInt<5>(0h1b), 3) node _T_3573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3572) node _T_3574 = bits(_T_3573, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3574 node _T_3575 = eq(UInt<5>(0h1a), idx_27) when _T_3575 : node _T_3576 = shl(UInt<5>(0h1b), 3) node _T_3577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3576) node _T_3578 = bits(_T_3577, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3578 node _T_3579 = eq(UInt<5>(0h1b), idx_27) when _T_3579 : node _T_3580 = shl(UInt<5>(0h1b), 3) node _T_3581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3580) node _T_3582 = bits(_T_3581, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3582 node _T_3583 = eq(UInt<5>(0h1c), idx_27) when _T_3583 : node _T_3584 = shl(UInt<5>(0h1b), 3) node _T_3585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3584) node _T_3586 = bits(_T_3585, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3586 node _T_3587 = eq(UInt<5>(0h1d), idx_27) when _T_3587 : node _T_3588 = shl(UInt<5>(0h1b), 3) node _T_3589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3588) node _T_3590 = bits(_T_3589, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3590 node _T_3591 = eq(UInt<5>(0h1e), idx_27) when _T_3591 : node _T_3592 = shl(UInt<5>(0h1b), 3) node _T_3593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3592) node _T_3594 = bits(_T_3593, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3594 node _T_3595 = eq(UInt<5>(0h1f), idx_27) when _T_3595 : node _T_3596 = shl(UInt<5>(0h1b), 3) node _T_3597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3596) node _T_3598 = bits(_T_3597, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3598 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_3599 = eq(UInt<1>(0h0), idx_28) when _T_3599 : node _T_3600 = shl(UInt<5>(0h1c), 3) node _T_3601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3600) node _T_3602 = bits(_T_3601, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3602 node _T_3603 = eq(UInt<1>(0h1), idx_28) when _T_3603 : node _T_3604 = shl(UInt<5>(0h1c), 3) node _T_3605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3604) node _T_3606 = bits(_T_3605, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3606 node _T_3607 = eq(UInt<2>(0h2), idx_28) when _T_3607 : node _T_3608 = shl(UInt<5>(0h1c), 3) node _T_3609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3608) node _T_3610 = bits(_T_3609, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3610 node _T_3611 = eq(UInt<2>(0h3), idx_28) when _T_3611 : node _T_3612 = shl(UInt<5>(0h1c), 3) node _T_3613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3612) node _T_3614 = bits(_T_3613, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3614 node _T_3615 = eq(UInt<3>(0h4), idx_28) when _T_3615 : node _T_3616 = shl(UInt<5>(0h1c), 3) node _T_3617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3616) node _T_3618 = bits(_T_3617, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3618 node _T_3619 = eq(UInt<3>(0h5), idx_28) when _T_3619 : node _T_3620 = shl(UInt<5>(0h1c), 3) node _T_3621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3620) node _T_3622 = bits(_T_3621, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3622 node _T_3623 = eq(UInt<3>(0h6), idx_28) when _T_3623 : node _T_3624 = shl(UInt<5>(0h1c), 3) node _T_3625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3624) node _T_3626 = bits(_T_3625, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3626 node _T_3627 = eq(UInt<3>(0h7), idx_28) when _T_3627 : node _T_3628 = shl(UInt<5>(0h1c), 3) node _T_3629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3628) node _T_3630 = bits(_T_3629, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3630 node _T_3631 = eq(UInt<4>(0h8), idx_28) when _T_3631 : node _T_3632 = shl(UInt<5>(0h1c), 3) node _T_3633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3632) node _T_3634 = bits(_T_3633, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3634 node _T_3635 = eq(UInt<4>(0h9), idx_28) when _T_3635 : node _T_3636 = shl(UInt<5>(0h1c), 3) node _T_3637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3636) node _T_3638 = bits(_T_3637, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3638 node _T_3639 = eq(UInt<4>(0ha), idx_28) when _T_3639 : node _T_3640 = shl(UInt<5>(0h1c), 3) node _T_3641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3640) node _T_3642 = bits(_T_3641, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3642 node _T_3643 = eq(UInt<4>(0hb), idx_28) when _T_3643 : node _T_3644 = shl(UInt<5>(0h1c), 3) node _T_3645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3644) node _T_3646 = bits(_T_3645, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3646 node _T_3647 = eq(UInt<4>(0hc), idx_28) when _T_3647 : node _T_3648 = shl(UInt<5>(0h1c), 3) node _T_3649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3648) node _T_3650 = bits(_T_3649, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3650 node _T_3651 = eq(UInt<4>(0hd), idx_28) when _T_3651 : node _T_3652 = shl(UInt<5>(0h1c), 3) node _T_3653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3652) node _T_3654 = bits(_T_3653, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3654 node _T_3655 = eq(UInt<4>(0he), idx_28) when _T_3655 : node _T_3656 = shl(UInt<5>(0h1c), 3) node _T_3657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3656) node _T_3658 = bits(_T_3657, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3658 node _T_3659 = eq(UInt<4>(0hf), idx_28) when _T_3659 : node _T_3660 = shl(UInt<5>(0h1c), 3) node _T_3661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3660) node _T_3662 = bits(_T_3661, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3662 node _T_3663 = eq(UInt<5>(0h10), idx_28) when _T_3663 : node _T_3664 = shl(UInt<5>(0h1c), 3) node _T_3665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3664) node _T_3666 = bits(_T_3665, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3666 node _T_3667 = eq(UInt<5>(0h11), idx_28) when _T_3667 : node _T_3668 = shl(UInt<5>(0h1c), 3) node _T_3669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3668) node _T_3670 = bits(_T_3669, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3670 node _T_3671 = eq(UInt<5>(0h12), idx_28) when _T_3671 : node _T_3672 = shl(UInt<5>(0h1c), 3) node _T_3673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3672) node _T_3674 = bits(_T_3673, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3674 node _T_3675 = eq(UInt<5>(0h13), idx_28) when _T_3675 : node _T_3676 = shl(UInt<5>(0h1c), 3) node _T_3677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3676) node _T_3678 = bits(_T_3677, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3678 node _T_3679 = eq(UInt<5>(0h14), idx_28) when _T_3679 : node _T_3680 = shl(UInt<5>(0h1c), 3) node _T_3681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3680) node _T_3682 = bits(_T_3681, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3682 node _T_3683 = eq(UInt<5>(0h15), idx_28) when _T_3683 : node _T_3684 = shl(UInt<5>(0h1c), 3) node _T_3685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3684) node _T_3686 = bits(_T_3685, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3686 node _T_3687 = eq(UInt<5>(0h16), idx_28) when _T_3687 : node _T_3688 = shl(UInt<5>(0h1c), 3) node _T_3689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3688) node _T_3690 = bits(_T_3689, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3690 node _T_3691 = eq(UInt<5>(0h17), idx_28) when _T_3691 : node _T_3692 = shl(UInt<5>(0h1c), 3) node _T_3693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3692) node _T_3694 = bits(_T_3693, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3694 node _T_3695 = eq(UInt<5>(0h18), idx_28) when _T_3695 : node _T_3696 = shl(UInt<5>(0h1c), 3) node _T_3697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3696) node _T_3698 = bits(_T_3697, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3698 node _T_3699 = eq(UInt<5>(0h19), idx_28) when _T_3699 : node _T_3700 = shl(UInt<5>(0h1c), 3) node _T_3701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3700) node _T_3702 = bits(_T_3701, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3702 node _T_3703 = eq(UInt<5>(0h1a), idx_28) when _T_3703 : node _T_3704 = shl(UInt<5>(0h1c), 3) node _T_3705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3704) node _T_3706 = bits(_T_3705, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3706 node _T_3707 = eq(UInt<5>(0h1b), idx_28) when _T_3707 : node _T_3708 = shl(UInt<5>(0h1c), 3) node _T_3709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3708) node _T_3710 = bits(_T_3709, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3710 node _T_3711 = eq(UInt<5>(0h1c), idx_28) when _T_3711 : node _T_3712 = shl(UInt<5>(0h1c), 3) node _T_3713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3712) node _T_3714 = bits(_T_3713, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3714 node _T_3715 = eq(UInt<5>(0h1d), idx_28) when _T_3715 : node _T_3716 = shl(UInt<5>(0h1c), 3) node _T_3717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3716) node _T_3718 = bits(_T_3717, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3718 node _T_3719 = eq(UInt<5>(0h1e), idx_28) when _T_3719 : node _T_3720 = shl(UInt<5>(0h1c), 3) node _T_3721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3720) node _T_3722 = bits(_T_3721, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3722 node _T_3723 = eq(UInt<5>(0h1f), idx_28) when _T_3723 : node _T_3724 = shl(UInt<5>(0h1c), 3) node _T_3725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3724) node _T_3726 = bits(_T_3725, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3726 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_3727 = eq(UInt<1>(0h0), idx_29) when _T_3727 : node _T_3728 = shl(UInt<5>(0h1d), 3) node _T_3729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3728) node _T_3730 = bits(_T_3729, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3730 node _T_3731 = eq(UInt<1>(0h1), idx_29) when _T_3731 : node _T_3732 = shl(UInt<5>(0h1d), 3) node _T_3733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3732) node _T_3734 = bits(_T_3733, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3734 node _T_3735 = eq(UInt<2>(0h2), idx_29) when _T_3735 : node _T_3736 = shl(UInt<5>(0h1d), 3) node _T_3737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3736) node _T_3738 = bits(_T_3737, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3738 node _T_3739 = eq(UInt<2>(0h3), idx_29) when _T_3739 : node _T_3740 = shl(UInt<5>(0h1d), 3) node _T_3741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3740) node _T_3742 = bits(_T_3741, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3742 node _T_3743 = eq(UInt<3>(0h4), idx_29) when _T_3743 : node _T_3744 = shl(UInt<5>(0h1d), 3) node _T_3745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3744) node _T_3746 = bits(_T_3745, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3746 node _T_3747 = eq(UInt<3>(0h5), idx_29) when _T_3747 : node _T_3748 = shl(UInt<5>(0h1d), 3) node _T_3749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3748) node _T_3750 = bits(_T_3749, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3750 node _T_3751 = eq(UInt<3>(0h6), idx_29) when _T_3751 : node _T_3752 = shl(UInt<5>(0h1d), 3) node _T_3753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3752) node _T_3754 = bits(_T_3753, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3754 node _T_3755 = eq(UInt<3>(0h7), idx_29) when _T_3755 : node _T_3756 = shl(UInt<5>(0h1d), 3) node _T_3757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3756) node _T_3758 = bits(_T_3757, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3758 node _T_3759 = eq(UInt<4>(0h8), idx_29) when _T_3759 : node _T_3760 = shl(UInt<5>(0h1d), 3) node _T_3761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3760) node _T_3762 = bits(_T_3761, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3762 node _T_3763 = eq(UInt<4>(0h9), idx_29) when _T_3763 : node _T_3764 = shl(UInt<5>(0h1d), 3) node _T_3765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3764) node _T_3766 = bits(_T_3765, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3766 node _T_3767 = eq(UInt<4>(0ha), idx_29) when _T_3767 : node _T_3768 = shl(UInt<5>(0h1d), 3) node _T_3769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3768) node _T_3770 = bits(_T_3769, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3770 node _T_3771 = eq(UInt<4>(0hb), idx_29) when _T_3771 : node _T_3772 = shl(UInt<5>(0h1d), 3) node _T_3773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3772) node _T_3774 = bits(_T_3773, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3774 node _T_3775 = eq(UInt<4>(0hc), idx_29) when _T_3775 : node _T_3776 = shl(UInt<5>(0h1d), 3) node _T_3777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3776) node _T_3778 = bits(_T_3777, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3778 node _T_3779 = eq(UInt<4>(0hd), idx_29) when _T_3779 : node _T_3780 = shl(UInt<5>(0h1d), 3) node _T_3781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3780) node _T_3782 = bits(_T_3781, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3782 node _T_3783 = eq(UInt<4>(0he), idx_29) when _T_3783 : node _T_3784 = shl(UInt<5>(0h1d), 3) node _T_3785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3784) node _T_3786 = bits(_T_3785, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3786 node _T_3787 = eq(UInt<4>(0hf), idx_29) when _T_3787 : node _T_3788 = shl(UInt<5>(0h1d), 3) node _T_3789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3788) node _T_3790 = bits(_T_3789, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3790 node _T_3791 = eq(UInt<5>(0h10), idx_29) when _T_3791 : node _T_3792 = shl(UInt<5>(0h1d), 3) node _T_3793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3792) node _T_3794 = bits(_T_3793, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3794 node _T_3795 = eq(UInt<5>(0h11), idx_29) when _T_3795 : node _T_3796 = shl(UInt<5>(0h1d), 3) node _T_3797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3796) node _T_3798 = bits(_T_3797, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3798 node _T_3799 = eq(UInt<5>(0h12), idx_29) when _T_3799 : node _T_3800 = shl(UInt<5>(0h1d), 3) node _T_3801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3800) node _T_3802 = bits(_T_3801, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3802 node _T_3803 = eq(UInt<5>(0h13), idx_29) when _T_3803 : node _T_3804 = shl(UInt<5>(0h1d), 3) node _T_3805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3804) node _T_3806 = bits(_T_3805, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3806 node _T_3807 = eq(UInt<5>(0h14), idx_29) when _T_3807 : node _T_3808 = shl(UInt<5>(0h1d), 3) node _T_3809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3808) node _T_3810 = bits(_T_3809, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3810 node _T_3811 = eq(UInt<5>(0h15), idx_29) when _T_3811 : node _T_3812 = shl(UInt<5>(0h1d), 3) node _T_3813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3812) node _T_3814 = bits(_T_3813, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3814 node _T_3815 = eq(UInt<5>(0h16), idx_29) when _T_3815 : node _T_3816 = shl(UInt<5>(0h1d), 3) node _T_3817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3816) node _T_3818 = bits(_T_3817, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3818 node _T_3819 = eq(UInt<5>(0h17), idx_29) when _T_3819 : node _T_3820 = shl(UInt<5>(0h1d), 3) node _T_3821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3820) node _T_3822 = bits(_T_3821, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3822 node _T_3823 = eq(UInt<5>(0h18), idx_29) when _T_3823 : node _T_3824 = shl(UInt<5>(0h1d), 3) node _T_3825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3824) node _T_3826 = bits(_T_3825, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3826 node _T_3827 = eq(UInt<5>(0h19), idx_29) when _T_3827 : node _T_3828 = shl(UInt<5>(0h1d), 3) node _T_3829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3828) node _T_3830 = bits(_T_3829, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3830 node _T_3831 = eq(UInt<5>(0h1a), idx_29) when _T_3831 : node _T_3832 = shl(UInt<5>(0h1d), 3) node _T_3833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3832) node _T_3834 = bits(_T_3833, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3834 node _T_3835 = eq(UInt<5>(0h1b), idx_29) when _T_3835 : node _T_3836 = shl(UInt<5>(0h1d), 3) node _T_3837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3836) node _T_3838 = bits(_T_3837, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3838 node _T_3839 = eq(UInt<5>(0h1c), idx_29) when _T_3839 : node _T_3840 = shl(UInt<5>(0h1d), 3) node _T_3841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3840) node _T_3842 = bits(_T_3841, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3842 node _T_3843 = eq(UInt<5>(0h1d), idx_29) when _T_3843 : node _T_3844 = shl(UInt<5>(0h1d), 3) node _T_3845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3844) node _T_3846 = bits(_T_3845, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3846 node _T_3847 = eq(UInt<5>(0h1e), idx_29) when _T_3847 : node _T_3848 = shl(UInt<5>(0h1d), 3) node _T_3849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3848) node _T_3850 = bits(_T_3849, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3850 node _T_3851 = eq(UInt<5>(0h1f), idx_29) when _T_3851 : node _T_3852 = shl(UInt<5>(0h1d), 3) node _T_3853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3852) node _T_3854 = bits(_T_3853, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3854 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_3855 = eq(UInt<1>(0h0), idx_30) when _T_3855 : node _T_3856 = shl(UInt<5>(0h1e), 3) node _T_3857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3856) node _T_3858 = bits(_T_3857, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3858 node _T_3859 = eq(UInt<1>(0h1), idx_30) when _T_3859 : node _T_3860 = shl(UInt<5>(0h1e), 3) node _T_3861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3860) node _T_3862 = bits(_T_3861, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3862 node _T_3863 = eq(UInt<2>(0h2), idx_30) when _T_3863 : node _T_3864 = shl(UInt<5>(0h1e), 3) node _T_3865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3864) node _T_3866 = bits(_T_3865, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3866 node _T_3867 = eq(UInt<2>(0h3), idx_30) when _T_3867 : node _T_3868 = shl(UInt<5>(0h1e), 3) node _T_3869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3868) node _T_3870 = bits(_T_3869, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3870 node _T_3871 = eq(UInt<3>(0h4), idx_30) when _T_3871 : node _T_3872 = shl(UInt<5>(0h1e), 3) node _T_3873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3872) node _T_3874 = bits(_T_3873, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3874 node _T_3875 = eq(UInt<3>(0h5), idx_30) when _T_3875 : node _T_3876 = shl(UInt<5>(0h1e), 3) node _T_3877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3876) node _T_3878 = bits(_T_3877, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3878 node _T_3879 = eq(UInt<3>(0h6), idx_30) when _T_3879 : node _T_3880 = shl(UInt<5>(0h1e), 3) node _T_3881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3880) node _T_3882 = bits(_T_3881, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3882 node _T_3883 = eq(UInt<3>(0h7), idx_30) when _T_3883 : node _T_3884 = shl(UInt<5>(0h1e), 3) node _T_3885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3884) node _T_3886 = bits(_T_3885, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3886 node _T_3887 = eq(UInt<4>(0h8), idx_30) when _T_3887 : node _T_3888 = shl(UInt<5>(0h1e), 3) node _T_3889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3888) node _T_3890 = bits(_T_3889, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3890 node _T_3891 = eq(UInt<4>(0h9), idx_30) when _T_3891 : node _T_3892 = shl(UInt<5>(0h1e), 3) node _T_3893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3892) node _T_3894 = bits(_T_3893, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3894 node _T_3895 = eq(UInt<4>(0ha), idx_30) when _T_3895 : node _T_3896 = shl(UInt<5>(0h1e), 3) node _T_3897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3896) node _T_3898 = bits(_T_3897, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3898 node _T_3899 = eq(UInt<4>(0hb), idx_30) when _T_3899 : node _T_3900 = shl(UInt<5>(0h1e), 3) node _T_3901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3900) node _T_3902 = bits(_T_3901, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3902 node _T_3903 = eq(UInt<4>(0hc), idx_30) when _T_3903 : node _T_3904 = shl(UInt<5>(0h1e), 3) node _T_3905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3904) node _T_3906 = bits(_T_3905, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3906 node _T_3907 = eq(UInt<4>(0hd), idx_30) when _T_3907 : node _T_3908 = shl(UInt<5>(0h1e), 3) node _T_3909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3908) node _T_3910 = bits(_T_3909, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3910 node _T_3911 = eq(UInt<4>(0he), idx_30) when _T_3911 : node _T_3912 = shl(UInt<5>(0h1e), 3) node _T_3913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3912) node _T_3914 = bits(_T_3913, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3914 node _T_3915 = eq(UInt<4>(0hf), idx_30) when _T_3915 : node _T_3916 = shl(UInt<5>(0h1e), 3) node _T_3917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3916) node _T_3918 = bits(_T_3917, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3918 node _T_3919 = eq(UInt<5>(0h10), idx_30) when _T_3919 : node _T_3920 = shl(UInt<5>(0h1e), 3) node _T_3921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3920) node _T_3922 = bits(_T_3921, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3922 node _T_3923 = eq(UInt<5>(0h11), idx_30) when _T_3923 : node _T_3924 = shl(UInt<5>(0h1e), 3) node _T_3925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3924) node _T_3926 = bits(_T_3925, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3926 node _T_3927 = eq(UInt<5>(0h12), idx_30) when _T_3927 : node _T_3928 = shl(UInt<5>(0h1e), 3) node _T_3929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3928) node _T_3930 = bits(_T_3929, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3930 node _T_3931 = eq(UInt<5>(0h13), idx_30) when _T_3931 : node _T_3932 = shl(UInt<5>(0h1e), 3) node _T_3933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3932) node _T_3934 = bits(_T_3933, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3934 node _T_3935 = eq(UInt<5>(0h14), idx_30) when _T_3935 : node _T_3936 = shl(UInt<5>(0h1e), 3) node _T_3937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3936) node _T_3938 = bits(_T_3937, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3938 node _T_3939 = eq(UInt<5>(0h15), idx_30) when _T_3939 : node _T_3940 = shl(UInt<5>(0h1e), 3) node _T_3941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3940) node _T_3942 = bits(_T_3941, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3942 node _T_3943 = eq(UInt<5>(0h16), idx_30) when _T_3943 : node _T_3944 = shl(UInt<5>(0h1e), 3) node _T_3945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3944) node _T_3946 = bits(_T_3945, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3946 node _T_3947 = eq(UInt<5>(0h17), idx_30) when _T_3947 : node _T_3948 = shl(UInt<5>(0h1e), 3) node _T_3949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3948) node _T_3950 = bits(_T_3949, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3950 node _T_3951 = eq(UInt<5>(0h18), idx_30) when _T_3951 : node _T_3952 = shl(UInt<5>(0h1e), 3) node _T_3953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3952) node _T_3954 = bits(_T_3953, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3954 node _T_3955 = eq(UInt<5>(0h19), idx_30) when _T_3955 : node _T_3956 = shl(UInt<5>(0h1e), 3) node _T_3957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3956) node _T_3958 = bits(_T_3957, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3958 node _T_3959 = eq(UInt<5>(0h1a), idx_30) when _T_3959 : node _T_3960 = shl(UInt<5>(0h1e), 3) node _T_3961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3960) node _T_3962 = bits(_T_3961, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3962 node _T_3963 = eq(UInt<5>(0h1b), idx_30) when _T_3963 : node _T_3964 = shl(UInt<5>(0h1e), 3) node _T_3965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3964) node _T_3966 = bits(_T_3965, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3966 node _T_3967 = eq(UInt<5>(0h1c), idx_30) when _T_3967 : node _T_3968 = shl(UInt<5>(0h1e), 3) node _T_3969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3968) node _T_3970 = bits(_T_3969, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3970 node _T_3971 = eq(UInt<5>(0h1d), idx_30) when _T_3971 : node _T_3972 = shl(UInt<5>(0h1e), 3) node _T_3973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3972) node _T_3974 = bits(_T_3973, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3974 node _T_3975 = eq(UInt<5>(0h1e), idx_30) when _T_3975 : node _T_3976 = shl(UInt<5>(0h1e), 3) node _T_3977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3976) node _T_3978 = bits(_T_3977, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3978 node _T_3979 = eq(UInt<5>(0h1f), idx_30) when _T_3979 : node _T_3980 = shl(UInt<5>(0h1e), 3) node _T_3981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3980) node _T_3982 = bits(_T_3981, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3982 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_3983 = eq(UInt<1>(0h0), idx_31) when _T_3983 : node _T_3984 = shl(UInt<5>(0h1f), 3) node _T_3985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3984) node _T_3986 = bits(_T_3985, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3986 node _T_3987 = eq(UInt<1>(0h1), idx_31) when _T_3987 : node _T_3988 = shl(UInt<5>(0h1f), 3) node _T_3989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3988) node _T_3990 = bits(_T_3989, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3990 node _T_3991 = eq(UInt<2>(0h2), idx_31) when _T_3991 : node _T_3992 = shl(UInt<5>(0h1f), 3) node _T_3993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3992) node _T_3994 = bits(_T_3993, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3994 node _T_3995 = eq(UInt<2>(0h3), idx_31) when _T_3995 : node _T_3996 = shl(UInt<5>(0h1f), 3) node _T_3997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3996) node _T_3998 = bits(_T_3997, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3998 node _T_3999 = eq(UInt<3>(0h4), idx_31) when _T_3999 : node _T_4000 = shl(UInt<5>(0h1f), 3) node _T_4001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4000) node _T_4002 = bits(_T_4001, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_4002 node _T_4003 = eq(UInt<3>(0h5), idx_31) when _T_4003 : node _T_4004 = shl(UInt<5>(0h1f), 3) node _T_4005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4004) node _T_4006 = bits(_T_4005, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_4006 node _T_4007 = eq(UInt<3>(0h6), idx_31) when _T_4007 : node _T_4008 = shl(UInt<5>(0h1f), 3) node _T_4009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4008) node _T_4010 = bits(_T_4009, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_4010 node _T_4011 = eq(UInt<3>(0h7), idx_31) when _T_4011 : node _T_4012 = shl(UInt<5>(0h1f), 3) node _T_4013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4012) node _T_4014 = bits(_T_4013, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_4014 node _T_4015 = eq(UInt<4>(0h8), idx_31) when _T_4015 : node _T_4016 = shl(UInt<5>(0h1f), 3) node _T_4017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4016) node _T_4018 = bits(_T_4017, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_4018 node _T_4019 = eq(UInt<4>(0h9), idx_31) when _T_4019 : node _T_4020 = shl(UInt<5>(0h1f), 3) node _T_4021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4020) node _T_4022 = bits(_T_4021, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_4022 node _T_4023 = eq(UInt<4>(0ha), idx_31) when _T_4023 : node _T_4024 = shl(UInt<5>(0h1f), 3) node _T_4025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4024) node _T_4026 = bits(_T_4025, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_4026 node _T_4027 = eq(UInt<4>(0hb), idx_31) when _T_4027 : node _T_4028 = shl(UInt<5>(0h1f), 3) node _T_4029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4028) node _T_4030 = bits(_T_4029, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_4030 node _T_4031 = eq(UInt<4>(0hc), idx_31) when _T_4031 : node _T_4032 = shl(UInt<5>(0h1f), 3) node _T_4033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4032) node _T_4034 = bits(_T_4033, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_4034 node _T_4035 = eq(UInt<4>(0hd), idx_31) when _T_4035 : node _T_4036 = shl(UInt<5>(0h1f), 3) node _T_4037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4036) node _T_4038 = bits(_T_4037, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_4038 node _T_4039 = eq(UInt<4>(0he), idx_31) when _T_4039 : node _T_4040 = shl(UInt<5>(0h1f), 3) node _T_4041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4040) node _T_4042 = bits(_T_4041, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_4042 node _T_4043 = eq(UInt<4>(0hf), idx_31) when _T_4043 : node _T_4044 = shl(UInt<5>(0h1f), 3) node _T_4045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4044) node _T_4046 = bits(_T_4045, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_4046 node _T_4047 = eq(UInt<5>(0h10), idx_31) when _T_4047 : node _T_4048 = shl(UInt<5>(0h1f), 3) node _T_4049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4048) node _T_4050 = bits(_T_4049, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_4050 node _T_4051 = eq(UInt<5>(0h11), idx_31) when _T_4051 : node _T_4052 = shl(UInt<5>(0h1f), 3) node _T_4053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4052) node _T_4054 = bits(_T_4053, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_4054 node _T_4055 = eq(UInt<5>(0h12), idx_31) when _T_4055 : node _T_4056 = shl(UInt<5>(0h1f), 3) node _T_4057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4056) node _T_4058 = bits(_T_4057, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_4058 node _T_4059 = eq(UInt<5>(0h13), idx_31) when _T_4059 : node _T_4060 = shl(UInt<5>(0h1f), 3) node _T_4061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4060) node _T_4062 = bits(_T_4061, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_4062 node _T_4063 = eq(UInt<5>(0h14), idx_31) when _T_4063 : node _T_4064 = shl(UInt<5>(0h1f), 3) node _T_4065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4064) node _T_4066 = bits(_T_4065, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_4066 node _T_4067 = eq(UInt<5>(0h15), idx_31) when _T_4067 : node _T_4068 = shl(UInt<5>(0h1f), 3) node _T_4069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4068) node _T_4070 = bits(_T_4069, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_4070 node _T_4071 = eq(UInt<5>(0h16), idx_31) when _T_4071 : node _T_4072 = shl(UInt<5>(0h1f), 3) node _T_4073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4072) node _T_4074 = bits(_T_4073, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_4074 node _T_4075 = eq(UInt<5>(0h17), idx_31) when _T_4075 : node _T_4076 = shl(UInt<5>(0h1f), 3) node _T_4077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4076) node _T_4078 = bits(_T_4077, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_4078 node _T_4079 = eq(UInt<5>(0h18), idx_31) when _T_4079 : node _T_4080 = shl(UInt<5>(0h1f), 3) node _T_4081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4080) node _T_4082 = bits(_T_4081, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_4082 node _T_4083 = eq(UInt<5>(0h19), idx_31) when _T_4083 : node _T_4084 = shl(UInt<5>(0h1f), 3) node _T_4085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4084) node _T_4086 = bits(_T_4085, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_4086 node _T_4087 = eq(UInt<5>(0h1a), idx_31) when _T_4087 : node _T_4088 = shl(UInt<5>(0h1f), 3) node _T_4089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4088) node _T_4090 = bits(_T_4089, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_4090 node _T_4091 = eq(UInt<5>(0h1b), idx_31) when _T_4091 : node _T_4092 = shl(UInt<5>(0h1f), 3) node _T_4093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4092) node _T_4094 = bits(_T_4093, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_4094 node _T_4095 = eq(UInt<5>(0h1c), idx_31) when _T_4095 : node _T_4096 = shl(UInt<5>(0h1f), 3) node _T_4097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4096) node _T_4098 = bits(_T_4097, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_4098 node _T_4099 = eq(UInt<5>(0h1d), idx_31) when _T_4099 : node _T_4100 = shl(UInt<5>(0h1f), 3) node _T_4101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4100) node _T_4102 = bits(_T_4101, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_4102 node _T_4103 = eq(UInt<5>(0h1e), idx_31) when _T_4103 : node _T_4104 = shl(UInt<5>(0h1f), 3) node _T_4105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4104) node _T_4106 = bits(_T_4105, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_4106 node _T_4107 = eq(UInt<5>(0h1f), idx_31) when _T_4107 : node _T_4108 = shl(UInt<5>(0h1f), 3) node _T_4109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4108) node _T_4110 = bits(_T_4109, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_4110 node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) node _all_queues_ready_T = and(Queue2_UInt8.io.enq.ready, Queue2_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue2_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue2_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue2_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue2_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue2_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue2_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue2_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue2_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue2_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue2_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue2_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue2_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue2_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue2_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue2_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue2_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue2_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue2_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue2_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue2_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue2_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue2_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue2_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue2_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue2_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue2_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue2_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue2_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue2_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue2_UInt8_31.io.enq.ready) node _account_for_buf_lens_Q_T = eq(incoming_writes_Q.io.deq.bits.end_of_message, UInt<1>(0h0)) node _account_for_buf_lens_Q_T_1 = and(incoming_writes_Q.io.deq.bits.end_of_message, buf_lens_Q.io.enq.ready) node account_for_buf_lens_Q = or(_account_for_buf_lens_Q_T, _account_for_buf_lens_Q_T_1) node _buf_lens_Q_io_enq_valid_T = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _buf_lens_Q_io_enq_valid_T_1 = and(_buf_lens_Q_io_enq_valid_T, incoming_writes_Q.io.deq.bits.end_of_message) connect buf_lens_Q.io.enq.valid, _buf_lens_Q_io_enq_valid_T_1 node _buf_lens_Q_io_enq_bits_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_lens_Q.io.enq.bits, _buf_lens_Q_io_enq_bits_T node _incoming_writes_Q_io_deq_ready_T = and(all_queues_ready, account_for_buf_lens_Q) connect incoming_writes_Q.io.deq.ready, _incoming_writes_Q_io_deq_ready_T node _T_4111 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4112 = and(_T_4111, account_for_buf_lens_Q) when _T_4112 : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_4113 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4114 = and(_T_4113, account_for_buf_lens_Q) node _T_4115 = and(_T_4114, use_this_queue) connect Queue2_UInt8.io.enq.valid, _T_4115 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_4116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4117 = and(_T_4116, account_for_buf_lens_Q) node _T_4118 = and(_T_4117, use_this_queue_1) connect Queue2_UInt8_1.io.enq.valid, _T_4118 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_4119 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4120 = and(_T_4119, account_for_buf_lens_Q) node _T_4121 = and(_T_4120, use_this_queue_2) connect Queue2_UInt8_2.io.enq.valid, _T_4121 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_4122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4123 = and(_T_4122, account_for_buf_lens_Q) node _T_4124 = and(_T_4123, use_this_queue_3) connect Queue2_UInt8_3.io.enq.valid, _T_4124 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_4125 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4126 = and(_T_4125, account_for_buf_lens_Q) node _T_4127 = and(_T_4126, use_this_queue_4) connect Queue2_UInt8_4.io.enq.valid, _T_4127 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_4128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4129 = and(_T_4128, account_for_buf_lens_Q) node _T_4130 = and(_T_4129, use_this_queue_5) connect Queue2_UInt8_5.io.enq.valid, _T_4130 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_4131 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4132 = and(_T_4131, account_for_buf_lens_Q) node _T_4133 = and(_T_4132, use_this_queue_6) connect Queue2_UInt8_6.io.enq.valid, _T_4133 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_4134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4135 = and(_T_4134, account_for_buf_lens_Q) node _T_4136 = and(_T_4135, use_this_queue_7) connect Queue2_UInt8_7.io.enq.valid, _T_4136 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_4137 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4138 = and(_T_4137, account_for_buf_lens_Q) node _T_4139 = and(_T_4138, use_this_queue_8) connect Queue2_UInt8_8.io.enq.valid, _T_4139 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_4140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4141 = and(_T_4140, account_for_buf_lens_Q) node _T_4142 = and(_T_4141, use_this_queue_9) connect Queue2_UInt8_9.io.enq.valid, _T_4142 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_4143 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4144 = and(_T_4143, account_for_buf_lens_Q) node _T_4145 = and(_T_4144, use_this_queue_10) connect Queue2_UInt8_10.io.enq.valid, _T_4145 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_4146 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4147 = and(_T_4146, account_for_buf_lens_Q) node _T_4148 = and(_T_4147, use_this_queue_11) connect Queue2_UInt8_11.io.enq.valid, _T_4148 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_4149 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4150 = and(_T_4149, account_for_buf_lens_Q) node _T_4151 = and(_T_4150, use_this_queue_12) connect Queue2_UInt8_12.io.enq.valid, _T_4151 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_4152 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4153 = and(_T_4152, account_for_buf_lens_Q) node _T_4154 = and(_T_4153, use_this_queue_13) connect Queue2_UInt8_13.io.enq.valid, _T_4154 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_4155 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4156 = and(_T_4155, account_for_buf_lens_Q) node _T_4157 = and(_T_4156, use_this_queue_14) connect Queue2_UInt8_14.io.enq.valid, _T_4157 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_4158 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4159 = and(_T_4158, account_for_buf_lens_Q) node _T_4160 = and(_T_4159, use_this_queue_15) connect Queue2_UInt8_15.io.enq.valid, _T_4160 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_4161 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4162 = and(_T_4161, account_for_buf_lens_Q) node _T_4163 = and(_T_4162, use_this_queue_16) connect Queue2_UInt8_16.io.enq.valid, _T_4163 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_4164 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4165 = and(_T_4164, account_for_buf_lens_Q) node _T_4166 = and(_T_4165, use_this_queue_17) connect Queue2_UInt8_17.io.enq.valid, _T_4166 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_4167 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4168 = and(_T_4167, account_for_buf_lens_Q) node _T_4169 = and(_T_4168, use_this_queue_18) connect Queue2_UInt8_18.io.enq.valid, _T_4169 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_4170 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4171 = and(_T_4170, account_for_buf_lens_Q) node _T_4172 = and(_T_4171, use_this_queue_19) connect Queue2_UInt8_19.io.enq.valid, _T_4172 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_4173 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4174 = and(_T_4173, account_for_buf_lens_Q) node _T_4175 = and(_T_4174, use_this_queue_20) connect Queue2_UInt8_20.io.enq.valid, _T_4175 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_4176 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4177 = and(_T_4176, account_for_buf_lens_Q) node _T_4178 = and(_T_4177, use_this_queue_21) connect Queue2_UInt8_21.io.enq.valid, _T_4178 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_4179 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4180 = and(_T_4179, account_for_buf_lens_Q) node _T_4181 = and(_T_4180, use_this_queue_22) connect Queue2_UInt8_22.io.enq.valid, _T_4181 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_4182 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4183 = and(_T_4182, account_for_buf_lens_Q) node _T_4184 = and(_T_4183, use_this_queue_23) connect Queue2_UInt8_23.io.enq.valid, _T_4184 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_4185 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4186 = and(_T_4185, account_for_buf_lens_Q) node _T_4187 = and(_T_4186, use_this_queue_24) connect Queue2_UInt8_24.io.enq.valid, _T_4187 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_4188 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4189 = and(_T_4188, account_for_buf_lens_Q) node _T_4190 = and(_T_4189, use_this_queue_25) connect Queue2_UInt8_25.io.enq.valid, _T_4190 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_4191 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4192 = and(_T_4191, account_for_buf_lens_Q) node _T_4193 = and(_T_4192, use_this_queue_26) connect Queue2_UInt8_26.io.enq.valid, _T_4193 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_4194 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4195 = and(_T_4194, account_for_buf_lens_Q) node _T_4196 = and(_T_4195, use_this_queue_27) connect Queue2_UInt8_27.io.enq.valid, _T_4196 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_4197 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4198 = and(_T_4197, account_for_buf_lens_Q) node _T_4199 = and(_T_4198, use_this_queue_28) connect Queue2_UInt8_28.io.enq.valid, _T_4199 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_4200 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4201 = and(_T_4200, account_for_buf_lens_Q) node _T_4202 = and(_T_4201, use_this_queue_29) connect Queue2_UInt8_29.io.enq.valid, _T_4202 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_4203 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4204 = and(_T_4203, account_for_buf_lens_Q) node _T_4205 = and(_T_4204, use_this_queue_30) connect Queue2_UInt8_30.io.enq.valid, _T_4205 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_4206 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4207 = and(_T_4206, account_for_buf_lens_Q) node _T_4208 = and(_T_4207, use_this_queue_31) connect Queue2_UInt8_31.io.enq.valid, _T_4208 when Queue2_UInt8.io.deq.valid : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_4209 = asUInt(reset) node _T_4210 = eq(_T_4209, UInt<1>(0h0)) when _T_4210 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_4211 = asUInt(reset) node _T_4212 = eq(_T_4211, UInt<1>(0h0)) when _T_4212 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h0), Queue2_UInt8.io.deq.bits) : printf_7 when Queue2_UInt8_1.io.deq.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_4213 = asUInt(reset) node _T_4214 = eq(_T_4213, UInt<1>(0h0)) when _T_4214 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_4215 = asUInt(reset) node _T_4216 = eq(_T_4215, UInt<1>(0h0)) when _T_4216 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h1), Queue2_UInt8_1.io.deq.bits) : printf_9 when Queue2_UInt8_2.io.deq.valid : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_4217 = asUInt(reset) node _T_4218 = eq(_T_4217, UInt<1>(0h0)) when _T_4218 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_4219 = asUInt(reset) node _T_4220 = eq(_T_4219, UInt<1>(0h0)) when _T_4220 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h2), Queue2_UInt8_2.io.deq.bits) : printf_11 when Queue2_UInt8_3.io.deq.valid : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_4221 = asUInt(reset) node _T_4222 = eq(_T_4221, UInt<1>(0h0)) when _T_4222 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_4223 = asUInt(reset) node _T_4224 = eq(_T_4223, UInt<1>(0h0)) when _T_4224 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h3), Queue2_UInt8_3.io.deq.bits) : printf_13 when Queue2_UInt8_4.io.deq.valid : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_4225 = asUInt(reset) node _T_4226 = eq(_T_4225, UInt<1>(0h0)) when _T_4226 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_4227 = asUInt(reset) node _T_4228 = eq(_T_4227, UInt<1>(0h0)) when _T_4228 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h4), Queue2_UInt8_4.io.deq.bits) : printf_15 when Queue2_UInt8_5.io.deq.valid : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_4229 = asUInt(reset) node _T_4230 = eq(_T_4229, UInt<1>(0h0)) when _T_4230 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_4231 = asUInt(reset) node _T_4232 = eq(_T_4231, UInt<1>(0h0)) when _T_4232 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h5), Queue2_UInt8_5.io.deq.bits) : printf_17 when Queue2_UInt8_6.io.deq.valid : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_4233 = asUInt(reset) node _T_4234 = eq(_T_4233, UInt<1>(0h0)) when _T_4234 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_4235 = asUInt(reset) node _T_4236 = eq(_T_4235, UInt<1>(0h0)) when _T_4236 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h6), Queue2_UInt8_6.io.deq.bits) : printf_19 when Queue2_UInt8_7.io.deq.valid : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_4237 = asUInt(reset) node _T_4238 = eq(_T_4237, UInt<1>(0h0)) when _T_4238 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_4239 = asUInt(reset) node _T_4240 = eq(_T_4239, UInt<1>(0h0)) when _T_4240 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h7), Queue2_UInt8_7.io.deq.bits) : printf_21 when Queue2_UInt8_8.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_4241 = asUInt(reset) node _T_4242 = eq(_T_4241, UInt<1>(0h0)) when _T_4242 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_4243 = asUInt(reset) node _T_4244 = eq(_T_4243, UInt<1>(0h0)) when _T_4244 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h8), Queue2_UInt8_8.io.deq.bits) : printf_23 when Queue2_UInt8_9.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_4245 = asUInt(reset) node _T_4246 = eq(_T_4245, UInt<1>(0h0)) when _T_4246 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_4247 = asUInt(reset) node _T_4248 = eq(_T_4247, UInt<1>(0h0)) when _T_4248 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h9), Queue2_UInt8_9.io.deq.bits) : printf_25 when Queue2_UInt8_10.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_4249 = asUInt(reset) node _T_4250 = eq(_T_4249, UInt<1>(0h0)) when _T_4250 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_4251 = asUInt(reset) node _T_4252 = eq(_T_4251, UInt<1>(0h0)) when _T_4252 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0ha), Queue2_UInt8_10.io.deq.bits) : printf_27 when Queue2_UInt8_11.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_4253 = asUInt(reset) node _T_4254 = eq(_T_4253, UInt<1>(0h0)) when _T_4254 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_4255 = asUInt(reset) node _T_4256 = eq(_T_4255, UInt<1>(0h0)) when _T_4256 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hb), Queue2_UInt8_11.io.deq.bits) : printf_29 when Queue2_UInt8_12.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_4257 = asUInt(reset) node _T_4258 = eq(_T_4257, UInt<1>(0h0)) when _T_4258 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_4259 = asUInt(reset) node _T_4260 = eq(_T_4259, UInt<1>(0h0)) when _T_4260 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hc), Queue2_UInt8_12.io.deq.bits) : printf_31 when Queue2_UInt8_13.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_4261 = asUInt(reset) node _T_4262 = eq(_T_4261, UInt<1>(0h0)) when _T_4262 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_4263 = asUInt(reset) node _T_4264 = eq(_T_4263, UInt<1>(0h0)) when _T_4264 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hd), Queue2_UInt8_13.io.deq.bits) : printf_33 when Queue2_UInt8_14.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_4265 = asUInt(reset) node _T_4266 = eq(_T_4265, UInt<1>(0h0)) when _T_4266 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_4267 = asUInt(reset) node _T_4268 = eq(_T_4267, UInt<1>(0h0)) when _T_4268 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0he), Queue2_UInt8_14.io.deq.bits) : printf_35 when Queue2_UInt8_15.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_4269 = asUInt(reset) node _T_4270 = eq(_T_4269, UInt<1>(0h0)) when _T_4270 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_4271 = asUInt(reset) node _T_4272 = eq(_T_4271, UInt<1>(0h0)) when _T_4272 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hf), Queue2_UInt8_15.io.deq.bits) : printf_37 when Queue2_UInt8_16.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_4273 = asUInt(reset) node _T_4274 = eq(_T_4273, UInt<1>(0h0)) when _T_4274 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_4275 = asUInt(reset) node _T_4276 = eq(_T_4275, UInt<1>(0h0)) when _T_4276 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h10), Queue2_UInt8_16.io.deq.bits) : printf_39 when Queue2_UInt8_17.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_4277 = asUInt(reset) node _T_4278 = eq(_T_4277, UInt<1>(0h0)) when _T_4278 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_4279 = asUInt(reset) node _T_4280 = eq(_T_4279, UInt<1>(0h0)) when _T_4280 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h11), Queue2_UInt8_17.io.deq.bits) : printf_41 when Queue2_UInt8_18.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_4281 = asUInt(reset) node _T_4282 = eq(_T_4281, UInt<1>(0h0)) when _T_4282 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_4283 = asUInt(reset) node _T_4284 = eq(_T_4283, UInt<1>(0h0)) when _T_4284 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h12), Queue2_UInt8_18.io.deq.bits) : printf_43 when Queue2_UInt8_19.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_4285 = asUInt(reset) node _T_4286 = eq(_T_4285, UInt<1>(0h0)) when _T_4286 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_4287 = asUInt(reset) node _T_4288 = eq(_T_4287, UInt<1>(0h0)) when _T_4288 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h13), Queue2_UInt8_19.io.deq.bits) : printf_45 when Queue2_UInt8_20.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_4289 = asUInt(reset) node _T_4290 = eq(_T_4289, UInt<1>(0h0)) when _T_4290 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_4291 = asUInt(reset) node _T_4292 = eq(_T_4291, UInt<1>(0h0)) when _T_4292 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h14), Queue2_UInt8_20.io.deq.bits) : printf_47 when Queue2_UInt8_21.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_4293 = asUInt(reset) node _T_4294 = eq(_T_4293, UInt<1>(0h0)) when _T_4294 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h15), Queue2_UInt8_21.io.deq.bits) : printf_49 when Queue2_UInt8_22.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_4297 = asUInt(reset) node _T_4298 = eq(_T_4297, UInt<1>(0h0)) when _T_4298 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_4299 = asUInt(reset) node _T_4300 = eq(_T_4299, UInt<1>(0h0)) when _T_4300 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h16), Queue2_UInt8_22.io.deq.bits) : printf_51 when Queue2_UInt8_23.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_4301 = asUInt(reset) node _T_4302 = eq(_T_4301, UInt<1>(0h0)) when _T_4302 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_4303 = asUInt(reset) node _T_4304 = eq(_T_4303, UInt<1>(0h0)) when _T_4304 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h17), Queue2_UInt8_23.io.deq.bits) : printf_53 when Queue2_UInt8_24.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_4305 = asUInt(reset) node _T_4306 = eq(_T_4305, UInt<1>(0h0)) when _T_4306 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_4307 = asUInt(reset) node _T_4308 = eq(_T_4307, UInt<1>(0h0)) when _T_4308 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h18), Queue2_UInt8_24.io.deq.bits) : printf_55 when Queue2_UInt8_25.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_4309 = asUInt(reset) node _T_4310 = eq(_T_4309, UInt<1>(0h0)) when _T_4310 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_4311 = asUInt(reset) node _T_4312 = eq(_T_4311, UInt<1>(0h0)) when _T_4312 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h19), Queue2_UInt8_25.io.deq.bits) : printf_57 when Queue2_UInt8_26.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_4313 = asUInt(reset) node _T_4314 = eq(_T_4313, UInt<1>(0h0)) when _T_4314 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_4315 = asUInt(reset) node _T_4316 = eq(_T_4315, UInt<1>(0h0)) when _T_4316 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1a), Queue2_UInt8_26.io.deq.bits) : printf_59 when Queue2_UInt8_27.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_4317 = asUInt(reset) node _T_4318 = eq(_T_4317, UInt<1>(0h0)) when _T_4318 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_4319 = asUInt(reset) node _T_4320 = eq(_T_4319, UInt<1>(0h0)) when _T_4320 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1b), Queue2_UInt8_27.io.deq.bits) : printf_61 when Queue2_UInt8_28.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_4321 = asUInt(reset) node _T_4322 = eq(_T_4321, UInt<1>(0h0)) when _T_4322 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_4323 = asUInt(reset) node _T_4324 = eq(_T_4323, UInt<1>(0h0)) when _T_4324 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1c), Queue2_UInt8_28.io.deq.bits) : printf_63 when Queue2_UInt8_29.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_4325 = asUInt(reset) node _T_4326 = eq(_T_4325, UInt<1>(0h0)) when _T_4326 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_4327 = asUInt(reset) node _T_4328 = eq(_T_4327, UInt<1>(0h0)) when _T_4328 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1d), Queue2_UInt8_29.io.deq.bits) : printf_65 when Queue2_UInt8_30.io.deq.valid : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_4329 = asUInt(reset) node _T_4330 = eq(_T_4329, UInt<1>(0h0)) when _T_4330 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_4331 = asUInt(reset) node _T_4332 = eq(_T_4331, UInt<1>(0h0)) when _T_4332 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1e), Queue2_UInt8_30.io.deq.bits) : printf_67 when Queue2_UInt8_31.io.deq.valid : regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_4333 = asUInt(reset) node _T_4334 = eq(_T_4333, UInt<1>(0h0)) when _T_4334 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_4335 = asUInt(reset) node _T_4336 = eq(_T_4335, UInt<1>(0h0)) when _T_4336 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1f), Queue2_UInt8_31.io.deq.bits) : printf_69 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue2_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue2_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue2_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue2_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue2_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue2_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue2_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue2_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue2_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue2_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue2_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue2_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue2_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue2_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue2_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue2_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue2_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue2_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue2_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue2_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue2_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue2_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue2_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue2_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue2_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue2_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue2_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue2_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue2_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue2_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue2_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue2_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_4337 = eq(UInt<1>(0h0), remapindex) when _T_4337 : connect remapVecData[0], Queue2_UInt8.io.deq.bits connect remapVecValids[0], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[0] node _T_4338 = eq(UInt<1>(0h1), remapindex) when _T_4338 : connect remapVecData[0], Queue2_UInt8_1.io.deq.bits connect remapVecValids[0], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_4339 = eq(UInt<2>(0h2), remapindex) when _T_4339 : connect remapVecData[0], Queue2_UInt8_2.io.deq.bits connect remapVecValids[0], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_4340 = eq(UInt<2>(0h3), remapindex) when _T_4340 : connect remapVecData[0], Queue2_UInt8_3.io.deq.bits connect remapVecValids[0], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_4341 = eq(UInt<3>(0h4), remapindex) when _T_4341 : connect remapVecData[0], Queue2_UInt8_4.io.deq.bits connect remapVecValids[0], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_4342 = eq(UInt<3>(0h5), remapindex) when _T_4342 : connect remapVecData[0], Queue2_UInt8_5.io.deq.bits connect remapVecValids[0], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_4343 = eq(UInt<3>(0h6), remapindex) when _T_4343 : connect remapVecData[0], Queue2_UInt8_6.io.deq.bits connect remapVecValids[0], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_4344 = eq(UInt<3>(0h7), remapindex) when _T_4344 : connect remapVecData[0], Queue2_UInt8_7.io.deq.bits connect remapVecValids[0], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_4345 = eq(UInt<4>(0h8), remapindex) when _T_4345 : connect remapVecData[0], Queue2_UInt8_8.io.deq.bits connect remapVecValids[0], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_4346 = eq(UInt<4>(0h9), remapindex) when _T_4346 : connect remapVecData[0], Queue2_UInt8_9.io.deq.bits connect remapVecValids[0], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_4347 = eq(UInt<4>(0ha), remapindex) when _T_4347 : connect remapVecData[0], Queue2_UInt8_10.io.deq.bits connect remapVecValids[0], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_4348 = eq(UInt<4>(0hb), remapindex) when _T_4348 : connect remapVecData[0], Queue2_UInt8_11.io.deq.bits connect remapVecValids[0], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_4349 = eq(UInt<4>(0hc), remapindex) when _T_4349 : connect remapVecData[0], Queue2_UInt8_12.io.deq.bits connect remapVecValids[0], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_4350 = eq(UInt<4>(0hd), remapindex) when _T_4350 : connect remapVecData[0], Queue2_UInt8_13.io.deq.bits connect remapVecValids[0], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_4351 = eq(UInt<4>(0he), remapindex) when _T_4351 : connect remapVecData[0], Queue2_UInt8_14.io.deq.bits connect remapVecValids[0], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_4352 = eq(UInt<4>(0hf), remapindex) when _T_4352 : connect remapVecData[0], Queue2_UInt8_15.io.deq.bits connect remapVecValids[0], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_4353 = eq(UInt<5>(0h10), remapindex) when _T_4353 : connect remapVecData[0], Queue2_UInt8_16.io.deq.bits connect remapVecValids[0], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_4354 = eq(UInt<5>(0h11), remapindex) when _T_4354 : connect remapVecData[0], Queue2_UInt8_17.io.deq.bits connect remapVecValids[0], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_4355 = eq(UInt<5>(0h12), remapindex) when _T_4355 : connect remapVecData[0], Queue2_UInt8_18.io.deq.bits connect remapVecValids[0], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_4356 = eq(UInt<5>(0h13), remapindex) when _T_4356 : connect remapVecData[0], Queue2_UInt8_19.io.deq.bits connect remapVecValids[0], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_4357 = eq(UInt<5>(0h14), remapindex) when _T_4357 : connect remapVecData[0], Queue2_UInt8_20.io.deq.bits connect remapVecValids[0], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_4358 = eq(UInt<5>(0h15), remapindex) when _T_4358 : connect remapVecData[0], Queue2_UInt8_21.io.deq.bits connect remapVecValids[0], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_4359 = eq(UInt<5>(0h16), remapindex) when _T_4359 : connect remapVecData[0], Queue2_UInt8_22.io.deq.bits connect remapVecValids[0], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_4360 = eq(UInt<5>(0h17), remapindex) when _T_4360 : connect remapVecData[0], Queue2_UInt8_23.io.deq.bits connect remapVecValids[0], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_4361 = eq(UInt<5>(0h18), remapindex) when _T_4361 : connect remapVecData[0], Queue2_UInt8_24.io.deq.bits connect remapVecValids[0], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_4362 = eq(UInt<5>(0h19), remapindex) when _T_4362 : connect remapVecData[0], Queue2_UInt8_25.io.deq.bits connect remapVecValids[0], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_4363 = eq(UInt<5>(0h1a), remapindex) when _T_4363 : connect remapVecData[0], Queue2_UInt8_26.io.deq.bits connect remapVecValids[0], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_4364 = eq(UInt<5>(0h1b), remapindex) when _T_4364 : connect remapVecData[0], Queue2_UInt8_27.io.deq.bits connect remapVecValids[0], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_4365 = eq(UInt<5>(0h1c), remapindex) when _T_4365 : connect remapVecData[0], Queue2_UInt8_28.io.deq.bits connect remapVecValids[0], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_4366 = eq(UInt<5>(0h1d), remapindex) when _T_4366 : connect remapVecData[0], Queue2_UInt8_29.io.deq.bits connect remapVecValids[0], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_4367 = eq(UInt<5>(0h1e), remapindex) when _T_4367 : connect remapVecData[0], Queue2_UInt8_30.io.deq.bits connect remapVecValids[0], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_4368 = eq(UInt<5>(0h1f), remapindex) when _T_4368 : connect remapVecData[0], Queue2_UInt8_31.io.deq.bits connect remapVecValids[0], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_4369 = eq(UInt<1>(0h0), remapindex_1) when _T_4369 : connect remapVecData[1], Queue2_UInt8.io.deq.bits connect remapVecValids[1], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[1] node _T_4370 = eq(UInt<1>(0h1), remapindex_1) when _T_4370 : connect remapVecData[1], Queue2_UInt8_1.io.deq.bits connect remapVecValids[1], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_4371 = eq(UInt<2>(0h2), remapindex_1) when _T_4371 : connect remapVecData[1], Queue2_UInt8_2.io.deq.bits connect remapVecValids[1], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_4372 = eq(UInt<2>(0h3), remapindex_1) when _T_4372 : connect remapVecData[1], Queue2_UInt8_3.io.deq.bits connect remapVecValids[1], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_4373 = eq(UInt<3>(0h4), remapindex_1) when _T_4373 : connect remapVecData[1], Queue2_UInt8_4.io.deq.bits connect remapVecValids[1], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_4374 = eq(UInt<3>(0h5), remapindex_1) when _T_4374 : connect remapVecData[1], Queue2_UInt8_5.io.deq.bits connect remapVecValids[1], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_4375 = eq(UInt<3>(0h6), remapindex_1) when _T_4375 : connect remapVecData[1], Queue2_UInt8_6.io.deq.bits connect remapVecValids[1], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_4376 = eq(UInt<3>(0h7), remapindex_1) when _T_4376 : connect remapVecData[1], Queue2_UInt8_7.io.deq.bits connect remapVecValids[1], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_4377 = eq(UInt<4>(0h8), remapindex_1) when _T_4377 : connect remapVecData[1], Queue2_UInt8_8.io.deq.bits connect remapVecValids[1], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_4378 = eq(UInt<4>(0h9), remapindex_1) when _T_4378 : connect remapVecData[1], Queue2_UInt8_9.io.deq.bits connect remapVecValids[1], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_4379 = eq(UInt<4>(0ha), remapindex_1) when _T_4379 : connect remapVecData[1], Queue2_UInt8_10.io.deq.bits connect remapVecValids[1], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_4380 = eq(UInt<4>(0hb), remapindex_1) when _T_4380 : connect remapVecData[1], Queue2_UInt8_11.io.deq.bits connect remapVecValids[1], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_4381 = eq(UInt<4>(0hc), remapindex_1) when _T_4381 : connect remapVecData[1], Queue2_UInt8_12.io.deq.bits connect remapVecValids[1], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_4382 = eq(UInt<4>(0hd), remapindex_1) when _T_4382 : connect remapVecData[1], Queue2_UInt8_13.io.deq.bits connect remapVecValids[1], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_4383 = eq(UInt<4>(0he), remapindex_1) when _T_4383 : connect remapVecData[1], Queue2_UInt8_14.io.deq.bits connect remapVecValids[1], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_4384 = eq(UInt<4>(0hf), remapindex_1) when _T_4384 : connect remapVecData[1], Queue2_UInt8_15.io.deq.bits connect remapVecValids[1], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_4385 = eq(UInt<5>(0h10), remapindex_1) when _T_4385 : connect remapVecData[1], Queue2_UInt8_16.io.deq.bits connect remapVecValids[1], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_4386 = eq(UInt<5>(0h11), remapindex_1) when _T_4386 : connect remapVecData[1], Queue2_UInt8_17.io.deq.bits connect remapVecValids[1], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_4387 = eq(UInt<5>(0h12), remapindex_1) when _T_4387 : connect remapVecData[1], Queue2_UInt8_18.io.deq.bits connect remapVecValids[1], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_4388 = eq(UInt<5>(0h13), remapindex_1) when _T_4388 : connect remapVecData[1], Queue2_UInt8_19.io.deq.bits connect remapVecValids[1], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_4389 = eq(UInt<5>(0h14), remapindex_1) when _T_4389 : connect remapVecData[1], Queue2_UInt8_20.io.deq.bits connect remapVecValids[1], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_4390 = eq(UInt<5>(0h15), remapindex_1) when _T_4390 : connect remapVecData[1], Queue2_UInt8_21.io.deq.bits connect remapVecValids[1], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_4391 = eq(UInt<5>(0h16), remapindex_1) when _T_4391 : connect remapVecData[1], Queue2_UInt8_22.io.deq.bits connect remapVecValids[1], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_4392 = eq(UInt<5>(0h17), remapindex_1) when _T_4392 : connect remapVecData[1], Queue2_UInt8_23.io.deq.bits connect remapVecValids[1], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_4393 = eq(UInt<5>(0h18), remapindex_1) when _T_4393 : connect remapVecData[1], Queue2_UInt8_24.io.deq.bits connect remapVecValids[1], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_4394 = eq(UInt<5>(0h19), remapindex_1) when _T_4394 : connect remapVecData[1], Queue2_UInt8_25.io.deq.bits connect remapVecValids[1], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_4395 = eq(UInt<5>(0h1a), remapindex_1) when _T_4395 : connect remapVecData[1], Queue2_UInt8_26.io.deq.bits connect remapVecValids[1], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_4396 = eq(UInt<5>(0h1b), remapindex_1) when _T_4396 : connect remapVecData[1], Queue2_UInt8_27.io.deq.bits connect remapVecValids[1], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_4397 = eq(UInt<5>(0h1c), remapindex_1) when _T_4397 : connect remapVecData[1], Queue2_UInt8_28.io.deq.bits connect remapVecValids[1], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_4398 = eq(UInt<5>(0h1d), remapindex_1) when _T_4398 : connect remapVecData[1], Queue2_UInt8_29.io.deq.bits connect remapVecValids[1], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_4399 = eq(UInt<5>(0h1e), remapindex_1) when _T_4399 : connect remapVecData[1], Queue2_UInt8_30.io.deq.bits connect remapVecValids[1], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_4400 = eq(UInt<5>(0h1f), remapindex_1) when _T_4400 : connect remapVecData[1], Queue2_UInt8_31.io.deq.bits connect remapVecValids[1], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_4401 = eq(UInt<1>(0h0), remapindex_2) when _T_4401 : connect remapVecData[2], Queue2_UInt8.io.deq.bits connect remapVecValids[2], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[2] node _T_4402 = eq(UInt<1>(0h1), remapindex_2) when _T_4402 : connect remapVecData[2], Queue2_UInt8_1.io.deq.bits connect remapVecValids[2], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_4403 = eq(UInt<2>(0h2), remapindex_2) when _T_4403 : connect remapVecData[2], Queue2_UInt8_2.io.deq.bits connect remapVecValids[2], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_4404 = eq(UInt<2>(0h3), remapindex_2) when _T_4404 : connect remapVecData[2], Queue2_UInt8_3.io.deq.bits connect remapVecValids[2], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_4405 = eq(UInt<3>(0h4), remapindex_2) when _T_4405 : connect remapVecData[2], Queue2_UInt8_4.io.deq.bits connect remapVecValids[2], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_4406 = eq(UInt<3>(0h5), remapindex_2) when _T_4406 : connect remapVecData[2], Queue2_UInt8_5.io.deq.bits connect remapVecValids[2], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_4407 = eq(UInt<3>(0h6), remapindex_2) when _T_4407 : connect remapVecData[2], Queue2_UInt8_6.io.deq.bits connect remapVecValids[2], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_4408 = eq(UInt<3>(0h7), remapindex_2) when _T_4408 : connect remapVecData[2], Queue2_UInt8_7.io.deq.bits connect remapVecValids[2], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_4409 = eq(UInt<4>(0h8), remapindex_2) when _T_4409 : connect remapVecData[2], Queue2_UInt8_8.io.deq.bits connect remapVecValids[2], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_4410 = eq(UInt<4>(0h9), remapindex_2) when _T_4410 : connect remapVecData[2], Queue2_UInt8_9.io.deq.bits connect remapVecValids[2], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_4411 = eq(UInt<4>(0ha), remapindex_2) when _T_4411 : connect remapVecData[2], Queue2_UInt8_10.io.deq.bits connect remapVecValids[2], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_4412 = eq(UInt<4>(0hb), remapindex_2) when _T_4412 : connect remapVecData[2], Queue2_UInt8_11.io.deq.bits connect remapVecValids[2], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_4413 = eq(UInt<4>(0hc), remapindex_2) when _T_4413 : connect remapVecData[2], Queue2_UInt8_12.io.deq.bits connect remapVecValids[2], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_4414 = eq(UInt<4>(0hd), remapindex_2) when _T_4414 : connect remapVecData[2], Queue2_UInt8_13.io.deq.bits connect remapVecValids[2], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_4415 = eq(UInt<4>(0he), remapindex_2) when _T_4415 : connect remapVecData[2], Queue2_UInt8_14.io.deq.bits connect remapVecValids[2], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_4416 = eq(UInt<4>(0hf), remapindex_2) when _T_4416 : connect remapVecData[2], Queue2_UInt8_15.io.deq.bits connect remapVecValids[2], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_4417 = eq(UInt<5>(0h10), remapindex_2) when _T_4417 : connect remapVecData[2], Queue2_UInt8_16.io.deq.bits connect remapVecValids[2], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_4418 = eq(UInt<5>(0h11), remapindex_2) when _T_4418 : connect remapVecData[2], Queue2_UInt8_17.io.deq.bits connect remapVecValids[2], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_4419 = eq(UInt<5>(0h12), remapindex_2) when _T_4419 : connect remapVecData[2], Queue2_UInt8_18.io.deq.bits connect remapVecValids[2], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_4420 = eq(UInt<5>(0h13), remapindex_2) when _T_4420 : connect remapVecData[2], Queue2_UInt8_19.io.deq.bits connect remapVecValids[2], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_4421 = eq(UInt<5>(0h14), remapindex_2) when _T_4421 : connect remapVecData[2], Queue2_UInt8_20.io.deq.bits connect remapVecValids[2], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_4422 = eq(UInt<5>(0h15), remapindex_2) when _T_4422 : connect remapVecData[2], Queue2_UInt8_21.io.deq.bits connect remapVecValids[2], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_4423 = eq(UInt<5>(0h16), remapindex_2) when _T_4423 : connect remapVecData[2], Queue2_UInt8_22.io.deq.bits connect remapVecValids[2], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_4424 = eq(UInt<5>(0h17), remapindex_2) when _T_4424 : connect remapVecData[2], Queue2_UInt8_23.io.deq.bits connect remapVecValids[2], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_4425 = eq(UInt<5>(0h18), remapindex_2) when _T_4425 : connect remapVecData[2], Queue2_UInt8_24.io.deq.bits connect remapVecValids[2], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_4426 = eq(UInt<5>(0h19), remapindex_2) when _T_4426 : connect remapVecData[2], Queue2_UInt8_25.io.deq.bits connect remapVecValids[2], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_4427 = eq(UInt<5>(0h1a), remapindex_2) when _T_4427 : connect remapVecData[2], Queue2_UInt8_26.io.deq.bits connect remapVecValids[2], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_4428 = eq(UInt<5>(0h1b), remapindex_2) when _T_4428 : connect remapVecData[2], Queue2_UInt8_27.io.deq.bits connect remapVecValids[2], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_4429 = eq(UInt<5>(0h1c), remapindex_2) when _T_4429 : connect remapVecData[2], Queue2_UInt8_28.io.deq.bits connect remapVecValids[2], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_4430 = eq(UInt<5>(0h1d), remapindex_2) when _T_4430 : connect remapVecData[2], Queue2_UInt8_29.io.deq.bits connect remapVecValids[2], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_4431 = eq(UInt<5>(0h1e), remapindex_2) when _T_4431 : connect remapVecData[2], Queue2_UInt8_30.io.deq.bits connect remapVecValids[2], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_4432 = eq(UInt<5>(0h1f), remapindex_2) when _T_4432 : connect remapVecData[2], Queue2_UInt8_31.io.deq.bits connect remapVecValids[2], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_4433 = eq(UInt<1>(0h0), remapindex_3) when _T_4433 : connect remapVecData[3], Queue2_UInt8.io.deq.bits connect remapVecValids[3], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[3] node _T_4434 = eq(UInt<1>(0h1), remapindex_3) when _T_4434 : connect remapVecData[3], Queue2_UInt8_1.io.deq.bits connect remapVecValids[3], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_4435 = eq(UInt<2>(0h2), remapindex_3) when _T_4435 : connect remapVecData[3], Queue2_UInt8_2.io.deq.bits connect remapVecValids[3], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_4436 = eq(UInt<2>(0h3), remapindex_3) when _T_4436 : connect remapVecData[3], Queue2_UInt8_3.io.deq.bits connect remapVecValids[3], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_4437 = eq(UInt<3>(0h4), remapindex_3) when _T_4437 : connect remapVecData[3], Queue2_UInt8_4.io.deq.bits connect remapVecValids[3], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_4438 = eq(UInt<3>(0h5), remapindex_3) when _T_4438 : connect remapVecData[3], Queue2_UInt8_5.io.deq.bits connect remapVecValids[3], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_4439 = eq(UInt<3>(0h6), remapindex_3) when _T_4439 : connect remapVecData[3], Queue2_UInt8_6.io.deq.bits connect remapVecValids[3], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_4440 = eq(UInt<3>(0h7), remapindex_3) when _T_4440 : connect remapVecData[3], Queue2_UInt8_7.io.deq.bits connect remapVecValids[3], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_4441 = eq(UInt<4>(0h8), remapindex_3) when _T_4441 : connect remapVecData[3], Queue2_UInt8_8.io.deq.bits connect remapVecValids[3], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_4442 = eq(UInt<4>(0h9), remapindex_3) when _T_4442 : connect remapVecData[3], Queue2_UInt8_9.io.deq.bits connect remapVecValids[3], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_4443 = eq(UInt<4>(0ha), remapindex_3) when _T_4443 : connect remapVecData[3], Queue2_UInt8_10.io.deq.bits connect remapVecValids[3], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_4444 = eq(UInt<4>(0hb), remapindex_3) when _T_4444 : connect remapVecData[3], Queue2_UInt8_11.io.deq.bits connect remapVecValids[3], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_4445 = eq(UInt<4>(0hc), remapindex_3) when _T_4445 : connect remapVecData[3], Queue2_UInt8_12.io.deq.bits connect remapVecValids[3], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_4446 = eq(UInt<4>(0hd), remapindex_3) when _T_4446 : connect remapVecData[3], Queue2_UInt8_13.io.deq.bits connect remapVecValids[3], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_4447 = eq(UInt<4>(0he), remapindex_3) when _T_4447 : connect remapVecData[3], Queue2_UInt8_14.io.deq.bits connect remapVecValids[3], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_4448 = eq(UInt<4>(0hf), remapindex_3) when _T_4448 : connect remapVecData[3], Queue2_UInt8_15.io.deq.bits connect remapVecValids[3], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_4449 = eq(UInt<5>(0h10), remapindex_3) when _T_4449 : connect remapVecData[3], Queue2_UInt8_16.io.deq.bits connect remapVecValids[3], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_4450 = eq(UInt<5>(0h11), remapindex_3) when _T_4450 : connect remapVecData[3], Queue2_UInt8_17.io.deq.bits connect remapVecValids[3], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_4451 = eq(UInt<5>(0h12), remapindex_3) when _T_4451 : connect remapVecData[3], Queue2_UInt8_18.io.deq.bits connect remapVecValids[3], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_4452 = eq(UInt<5>(0h13), remapindex_3) when _T_4452 : connect remapVecData[3], Queue2_UInt8_19.io.deq.bits connect remapVecValids[3], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_4453 = eq(UInt<5>(0h14), remapindex_3) when _T_4453 : connect remapVecData[3], Queue2_UInt8_20.io.deq.bits connect remapVecValids[3], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_4454 = eq(UInt<5>(0h15), remapindex_3) when _T_4454 : connect remapVecData[3], Queue2_UInt8_21.io.deq.bits connect remapVecValids[3], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_4455 = eq(UInt<5>(0h16), remapindex_3) when _T_4455 : connect remapVecData[3], Queue2_UInt8_22.io.deq.bits connect remapVecValids[3], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_4456 = eq(UInt<5>(0h17), remapindex_3) when _T_4456 : connect remapVecData[3], Queue2_UInt8_23.io.deq.bits connect remapVecValids[3], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_4457 = eq(UInt<5>(0h18), remapindex_3) when _T_4457 : connect remapVecData[3], Queue2_UInt8_24.io.deq.bits connect remapVecValids[3], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_4458 = eq(UInt<5>(0h19), remapindex_3) when _T_4458 : connect remapVecData[3], Queue2_UInt8_25.io.deq.bits connect remapVecValids[3], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_4459 = eq(UInt<5>(0h1a), remapindex_3) when _T_4459 : connect remapVecData[3], Queue2_UInt8_26.io.deq.bits connect remapVecValids[3], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_4460 = eq(UInt<5>(0h1b), remapindex_3) when _T_4460 : connect remapVecData[3], Queue2_UInt8_27.io.deq.bits connect remapVecValids[3], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_4461 = eq(UInt<5>(0h1c), remapindex_3) when _T_4461 : connect remapVecData[3], Queue2_UInt8_28.io.deq.bits connect remapVecValids[3], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_4462 = eq(UInt<5>(0h1d), remapindex_3) when _T_4462 : connect remapVecData[3], Queue2_UInt8_29.io.deq.bits connect remapVecValids[3], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_4463 = eq(UInt<5>(0h1e), remapindex_3) when _T_4463 : connect remapVecData[3], Queue2_UInt8_30.io.deq.bits connect remapVecValids[3], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_4464 = eq(UInt<5>(0h1f), remapindex_3) when _T_4464 : connect remapVecData[3], Queue2_UInt8_31.io.deq.bits connect remapVecValids[3], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_4465 = eq(UInt<1>(0h0), remapindex_4) when _T_4465 : connect remapVecData[4], Queue2_UInt8.io.deq.bits connect remapVecValids[4], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[4] node _T_4466 = eq(UInt<1>(0h1), remapindex_4) when _T_4466 : connect remapVecData[4], Queue2_UInt8_1.io.deq.bits connect remapVecValids[4], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_4467 = eq(UInt<2>(0h2), remapindex_4) when _T_4467 : connect remapVecData[4], Queue2_UInt8_2.io.deq.bits connect remapVecValids[4], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_4468 = eq(UInt<2>(0h3), remapindex_4) when _T_4468 : connect remapVecData[4], Queue2_UInt8_3.io.deq.bits connect remapVecValids[4], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_4469 = eq(UInt<3>(0h4), remapindex_4) when _T_4469 : connect remapVecData[4], Queue2_UInt8_4.io.deq.bits connect remapVecValids[4], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_4470 = eq(UInt<3>(0h5), remapindex_4) when _T_4470 : connect remapVecData[4], Queue2_UInt8_5.io.deq.bits connect remapVecValids[4], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_4471 = eq(UInt<3>(0h6), remapindex_4) when _T_4471 : connect remapVecData[4], Queue2_UInt8_6.io.deq.bits connect remapVecValids[4], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_4472 = eq(UInt<3>(0h7), remapindex_4) when _T_4472 : connect remapVecData[4], Queue2_UInt8_7.io.deq.bits connect remapVecValids[4], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_4473 = eq(UInt<4>(0h8), remapindex_4) when _T_4473 : connect remapVecData[4], Queue2_UInt8_8.io.deq.bits connect remapVecValids[4], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_4474 = eq(UInt<4>(0h9), remapindex_4) when _T_4474 : connect remapVecData[4], Queue2_UInt8_9.io.deq.bits connect remapVecValids[4], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_4475 = eq(UInt<4>(0ha), remapindex_4) when _T_4475 : connect remapVecData[4], Queue2_UInt8_10.io.deq.bits connect remapVecValids[4], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_4476 = eq(UInt<4>(0hb), remapindex_4) when _T_4476 : connect remapVecData[4], Queue2_UInt8_11.io.deq.bits connect remapVecValids[4], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_4477 = eq(UInt<4>(0hc), remapindex_4) when _T_4477 : connect remapVecData[4], Queue2_UInt8_12.io.deq.bits connect remapVecValids[4], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_4478 = eq(UInt<4>(0hd), remapindex_4) when _T_4478 : connect remapVecData[4], Queue2_UInt8_13.io.deq.bits connect remapVecValids[4], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_4479 = eq(UInt<4>(0he), remapindex_4) when _T_4479 : connect remapVecData[4], Queue2_UInt8_14.io.deq.bits connect remapVecValids[4], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_4480 = eq(UInt<4>(0hf), remapindex_4) when _T_4480 : connect remapVecData[4], Queue2_UInt8_15.io.deq.bits connect remapVecValids[4], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_4481 = eq(UInt<5>(0h10), remapindex_4) when _T_4481 : connect remapVecData[4], Queue2_UInt8_16.io.deq.bits connect remapVecValids[4], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_4482 = eq(UInt<5>(0h11), remapindex_4) when _T_4482 : connect remapVecData[4], Queue2_UInt8_17.io.deq.bits connect remapVecValids[4], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_4483 = eq(UInt<5>(0h12), remapindex_4) when _T_4483 : connect remapVecData[4], Queue2_UInt8_18.io.deq.bits connect remapVecValids[4], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_4484 = eq(UInt<5>(0h13), remapindex_4) when _T_4484 : connect remapVecData[4], Queue2_UInt8_19.io.deq.bits connect remapVecValids[4], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_4485 = eq(UInt<5>(0h14), remapindex_4) when _T_4485 : connect remapVecData[4], Queue2_UInt8_20.io.deq.bits connect remapVecValids[4], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_4486 = eq(UInt<5>(0h15), remapindex_4) when _T_4486 : connect remapVecData[4], Queue2_UInt8_21.io.deq.bits connect remapVecValids[4], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_4487 = eq(UInt<5>(0h16), remapindex_4) when _T_4487 : connect remapVecData[4], Queue2_UInt8_22.io.deq.bits connect remapVecValids[4], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_4488 = eq(UInt<5>(0h17), remapindex_4) when _T_4488 : connect remapVecData[4], Queue2_UInt8_23.io.deq.bits connect remapVecValids[4], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_4489 = eq(UInt<5>(0h18), remapindex_4) when _T_4489 : connect remapVecData[4], Queue2_UInt8_24.io.deq.bits connect remapVecValids[4], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_4490 = eq(UInt<5>(0h19), remapindex_4) when _T_4490 : connect remapVecData[4], Queue2_UInt8_25.io.deq.bits connect remapVecValids[4], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_4491 = eq(UInt<5>(0h1a), remapindex_4) when _T_4491 : connect remapVecData[4], Queue2_UInt8_26.io.deq.bits connect remapVecValids[4], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_4492 = eq(UInt<5>(0h1b), remapindex_4) when _T_4492 : connect remapVecData[4], Queue2_UInt8_27.io.deq.bits connect remapVecValids[4], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_4493 = eq(UInt<5>(0h1c), remapindex_4) when _T_4493 : connect remapVecData[4], Queue2_UInt8_28.io.deq.bits connect remapVecValids[4], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_4494 = eq(UInt<5>(0h1d), remapindex_4) when _T_4494 : connect remapVecData[4], Queue2_UInt8_29.io.deq.bits connect remapVecValids[4], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_4495 = eq(UInt<5>(0h1e), remapindex_4) when _T_4495 : connect remapVecData[4], Queue2_UInt8_30.io.deq.bits connect remapVecValids[4], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_4496 = eq(UInt<5>(0h1f), remapindex_4) when _T_4496 : connect remapVecData[4], Queue2_UInt8_31.io.deq.bits connect remapVecValids[4], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_4497 = eq(UInt<1>(0h0), remapindex_5) when _T_4497 : connect remapVecData[5], Queue2_UInt8.io.deq.bits connect remapVecValids[5], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[5] node _T_4498 = eq(UInt<1>(0h1), remapindex_5) when _T_4498 : connect remapVecData[5], Queue2_UInt8_1.io.deq.bits connect remapVecValids[5], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_4499 = eq(UInt<2>(0h2), remapindex_5) when _T_4499 : connect remapVecData[5], Queue2_UInt8_2.io.deq.bits connect remapVecValids[5], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_4500 = eq(UInt<2>(0h3), remapindex_5) when _T_4500 : connect remapVecData[5], Queue2_UInt8_3.io.deq.bits connect remapVecValids[5], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_4501 = eq(UInt<3>(0h4), remapindex_5) when _T_4501 : connect remapVecData[5], Queue2_UInt8_4.io.deq.bits connect remapVecValids[5], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_4502 = eq(UInt<3>(0h5), remapindex_5) when _T_4502 : connect remapVecData[5], Queue2_UInt8_5.io.deq.bits connect remapVecValids[5], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_4503 = eq(UInt<3>(0h6), remapindex_5) when _T_4503 : connect remapVecData[5], Queue2_UInt8_6.io.deq.bits connect remapVecValids[5], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_4504 = eq(UInt<3>(0h7), remapindex_5) when _T_4504 : connect remapVecData[5], Queue2_UInt8_7.io.deq.bits connect remapVecValids[5], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_4505 = eq(UInt<4>(0h8), remapindex_5) when _T_4505 : connect remapVecData[5], Queue2_UInt8_8.io.deq.bits connect remapVecValids[5], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_4506 = eq(UInt<4>(0h9), remapindex_5) when _T_4506 : connect remapVecData[5], Queue2_UInt8_9.io.deq.bits connect remapVecValids[5], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_4507 = eq(UInt<4>(0ha), remapindex_5) when _T_4507 : connect remapVecData[5], Queue2_UInt8_10.io.deq.bits connect remapVecValids[5], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_4508 = eq(UInt<4>(0hb), remapindex_5) when _T_4508 : connect remapVecData[5], Queue2_UInt8_11.io.deq.bits connect remapVecValids[5], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_4509 = eq(UInt<4>(0hc), remapindex_5) when _T_4509 : connect remapVecData[5], Queue2_UInt8_12.io.deq.bits connect remapVecValids[5], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_4510 = eq(UInt<4>(0hd), remapindex_5) when _T_4510 : connect remapVecData[5], Queue2_UInt8_13.io.deq.bits connect remapVecValids[5], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_4511 = eq(UInt<4>(0he), remapindex_5) when _T_4511 : connect remapVecData[5], Queue2_UInt8_14.io.deq.bits connect remapVecValids[5], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_4512 = eq(UInt<4>(0hf), remapindex_5) when _T_4512 : connect remapVecData[5], Queue2_UInt8_15.io.deq.bits connect remapVecValids[5], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_4513 = eq(UInt<5>(0h10), remapindex_5) when _T_4513 : connect remapVecData[5], Queue2_UInt8_16.io.deq.bits connect remapVecValids[5], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_4514 = eq(UInt<5>(0h11), remapindex_5) when _T_4514 : connect remapVecData[5], Queue2_UInt8_17.io.deq.bits connect remapVecValids[5], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_4515 = eq(UInt<5>(0h12), remapindex_5) when _T_4515 : connect remapVecData[5], Queue2_UInt8_18.io.deq.bits connect remapVecValids[5], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_4516 = eq(UInt<5>(0h13), remapindex_5) when _T_4516 : connect remapVecData[5], Queue2_UInt8_19.io.deq.bits connect remapVecValids[5], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_4517 = eq(UInt<5>(0h14), remapindex_5) when _T_4517 : connect remapVecData[5], Queue2_UInt8_20.io.deq.bits connect remapVecValids[5], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_4518 = eq(UInt<5>(0h15), remapindex_5) when _T_4518 : connect remapVecData[5], Queue2_UInt8_21.io.deq.bits connect remapVecValids[5], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_4519 = eq(UInt<5>(0h16), remapindex_5) when _T_4519 : connect remapVecData[5], Queue2_UInt8_22.io.deq.bits connect remapVecValids[5], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_4520 = eq(UInt<5>(0h17), remapindex_5) when _T_4520 : connect remapVecData[5], Queue2_UInt8_23.io.deq.bits connect remapVecValids[5], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_4521 = eq(UInt<5>(0h18), remapindex_5) when _T_4521 : connect remapVecData[5], Queue2_UInt8_24.io.deq.bits connect remapVecValids[5], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_4522 = eq(UInt<5>(0h19), remapindex_5) when _T_4522 : connect remapVecData[5], Queue2_UInt8_25.io.deq.bits connect remapVecValids[5], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_4523 = eq(UInt<5>(0h1a), remapindex_5) when _T_4523 : connect remapVecData[5], Queue2_UInt8_26.io.deq.bits connect remapVecValids[5], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_4524 = eq(UInt<5>(0h1b), remapindex_5) when _T_4524 : connect remapVecData[5], Queue2_UInt8_27.io.deq.bits connect remapVecValids[5], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_4525 = eq(UInt<5>(0h1c), remapindex_5) when _T_4525 : connect remapVecData[5], Queue2_UInt8_28.io.deq.bits connect remapVecValids[5], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_4526 = eq(UInt<5>(0h1d), remapindex_5) when _T_4526 : connect remapVecData[5], Queue2_UInt8_29.io.deq.bits connect remapVecValids[5], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_4527 = eq(UInt<5>(0h1e), remapindex_5) when _T_4527 : connect remapVecData[5], Queue2_UInt8_30.io.deq.bits connect remapVecValids[5], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_4528 = eq(UInt<5>(0h1f), remapindex_5) when _T_4528 : connect remapVecData[5], Queue2_UInt8_31.io.deq.bits connect remapVecValids[5], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_4529 = eq(UInt<1>(0h0), remapindex_6) when _T_4529 : connect remapVecData[6], Queue2_UInt8.io.deq.bits connect remapVecValids[6], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[6] node _T_4530 = eq(UInt<1>(0h1), remapindex_6) when _T_4530 : connect remapVecData[6], Queue2_UInt8_1.io.deq.bits connect remapVecValids[6], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_4531 = eq(UInt<2>(0h2), remapindex_6) when _T_4531 : connect remapVecData[6], Queue2_UInt8_2.io.deq.bits connect remapVecValids[6], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_4532 = eq(UInt<2>(0h3), remapindex_6) when _T_4532 : connect remapVecData[6], Queue2_UInt8_3.io.deq.bits connect remapVecValids[6], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_4533 = eq(UInt<3>(0h4), remapindex_6) when _T_4533 : connect remapVecData[6], Queue2_UInt8_4.io.deq.bits connect remapVecValids[6], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_4534 = eq(UInt<3>(0h5), remapindex_6) when _T_4534 : connect remapVecData[6], Queue2_UInt8_5.io.deq.bits connect remapVecValids[6], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_4535 = eq(UInt<3>(0h6), remapindex_6) when _T_4535 : connect remapVecData[6], Queue2_UInt8_6.io.deq.bits connect remapVecValids[6], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_4536 = eq(UInt<3>(0h7), remapindex_6) when _T_4536 : connect remapVecData[6], Queue2_UInt8_7.io.deq.bits connect remapVecValids[6], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_4537 = eq(UInt<4>(0h8), remapindex_6) when _T_4537 : connect remapVecData[6], Queue2_UInt8_8.io.deq.bits connect remapVecValids[6], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_4538 = eq(UInt<4>(0h9), remapindex_6) when _T_4538 : connect remapVecData[6], Queue2_UInt8_9.io.deq.bits connect remapVecValids[6], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_4539 = eq(UInt<4>(0ha), remapindex_6) when _T_4539 : connect remapVecData[6], Queue2_UInt8_10.io.deq.bits connect remapVecValids[6], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_4540 = eq(UInt<4>(0hb), remapindex_6) when _T_4540 : connect remapVecData[6], Queue2_UInt8_11.io.deq.bits connect remapVecValids[6], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_4541 = eq(UInt<4>(0hc), remapindex_6) when _T_4541 : connect remapVecData[6], Queue2_UInt8_12.io.deq.bits connect remapVecValids[6], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_4542 = eq(UInt<4>(0hd), remapindex_6) when _T_4542 : connect remapVecData[6], Queue2_UInt8_13.io.deq.bits connect remapVecValids[6], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_4543 = eq(UInt<4>(0he), remapindex_6) when _T_4543 : connect remapVecData[6], Queue2_UInt8_14.io.deq.bits connect remapVecValids[6], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_4544 = eq(UInt<4>(0hf), remapindex_6) when _T_4544 : connect remapVecData[6], Queue2_UInt8_15.io.deq.bits connect remapVecValids[6], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_4545 = eq(UInt<5>(0h10), remapindex_6) when _T_4545 : connect remapVecData[6], Queue2_UInt8_16.io.deq.bits connect remapVecValids[6], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_4546 = eq(UInt<5>(0h11), remapindex_6) when _T_4546 : connect remapVecData[6], Queue2_UInt8_17.io.deq.bits connect remapVecValids[6], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_4547 = eq(UInt<5>(0h12), remapindex_6) when _T_4547 : connect remapVecData[6], Queue2_UInt8_18.io.deq.bits connect remapVecValids[6], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_4548 = eq(UInt<5>(0h13), remapindex_6) when _T_4548 : connect remapVecData[6], Queue2_UInt8_19.io.deq.bits connect remapVecValids[6], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_4549 = eq(UInt<5>(0h14), remapindex_6) when _T_4549 : connect remapVecData[6], Queue2_UInt8_20.io.deq.bits connect remapVecValids[6], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_4550 = eq(UInt<5>(0h15), remapindex_6) when _T_4550 : connect remapVecData[6], Queue2_UInt8_21.io.deq.bits connect remapVecValids[6], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_4551 = eq(UInt<5>(0h16), remapindex_6) when _T_4551 : connect remapVecData[6], Queue2_UInt8_22.io.deq.bits connect remapVecValids[6], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_4552 = eq(UInt<5>(0h17), remapindex_6) when _T_4552 : connect remapVecData[6], Queue2_UInt8_23.io.deq.bits connect remapVecValids[6], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_4553 = eq(UInt<5>(0h18), remapindex_6) when _T_4553 : connect remapVecData[6], Queue2_UInt8_24.io.deq.bits connect remapVecValids[6], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_4554 = eq(UInt<5>(0h19), remapindex_6) when _T_4554 : connect remapVecData[6], Queue2_UInt8_25.io.deq.bits connect remapVecValids[6], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_4555 = eq(UInt<5>(0h1a), remapindex_6) when _T_4555 : connect remapVecData[6], Queue2_UInt8_26.io.deq.bits connect remapVecValids[6], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_4556 = eq(UInt<5>(0h1b), remapindex_6) when _T_4556 : connect remapVecData[6], Queue2_UInt8_27.io.deq.bits connect remapVecValids[6], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_4557 = eq(UInt<5>(0h1c), remapindex_6) when _T_4557 : connect remapVecData[6], Queue2_UInt8_28.io.deq.bits connect remapVecValids[6], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_4558 = eq(UInt<5>(0h1d), remapindex_6) when _T_4558 : connect remapVecData[6], Queue2_UInt8_29.io.deq.bits connect remapVecValids[6], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_4559 = eq(UInt<5>(0h1e), remapindex_6) when _T_4559 : connect remapVecData[6], Queue2_UInt8_30.io.deq.bits connect remapVecValids[6], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_4560 = eq(UInt<5>(0h1f), remapindex_6) when _T_4560 : connect remapVecData[6], Queue2_UInt8_31.io.deq.bits connect remapVecValids[6], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_4561 = eq(UInt<1>(0h0), remapindex_7) when _T_4561 : connect remapVecData[7], Queue2_UInt8.io.deq.bits connect remapVecValids[7], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[7] node _T_4562 = eq(UInt<1>(0h1), remapindex_7) when _T_4562 : connect remapVecData[7], Queue2_UInt8_1.io.deq.bits connect remapVecValids[7], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_4563 = eq(UInt<2>(0h2), remapindex_7) when _T_4563 : connect remapVecData[7], Queue2_UInt8_2.io.deq.bits connect remapVecValids[7], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_4564 = eq(UInt<2>(0h3), remapindex_7) when _T_4564 : connect remapVecData[7], Queue2_UInt8_3.io.deq.bits connect remapVecValids[7], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_4565 = eq(UInt<3>(0h4), remapindex_7) when _T_4565 : connect remapVecData[7], Queue2_UInt8_4.io.deq.bits connect remapVecValids[7], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_4566 = eq(UInt<3>(0h5), remapindex_7) when _T_4566 : connect remapVecData[7], Queue2_UInt8_5.io.deq.bits connect remapVecValids[7], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_4567 = eq(UInt<3>(0h6), remapindex_7) when _T_4567 : connect remapVecData[7], Queue2_UInt8_6.io.deq.bits connect remapVecValids[7], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_4568 = eq(UInt<3>(0h7), remapindex_7) when _T_4568 : connect remapVecData[7], Queue2_UInt8_7.io.deq.bits connect remapVecValids[7], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_4569 = eq(UInt<4>(0h8), remapindex_7) when _T_4569 : connect remapVecData[7], Queue2_UInt8_8.io.deq.bits connect remapVecValids[7], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_4570 = eq(UInt<4>(0h9), remapindex_7) when _T_4570 : connect remapVecData[7], Queue2_UInt8_9.io.deq.bits connect remapVecValids[7], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_4571 = eq(UInt<4>(0ha), remapindex_7) when _T_4571 : connect remapVecData[7], Queue2_UInt8_10.io.deq.bits connect remapVecValids[7], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_4572 = eq(UInt<4>(0hb), remapindex_7) when _T_4572 : connect remapVecData[7], Queue2_UInt8_11.io.deq.bits connect remapVecValids[7], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_4573 = eq(UInt<4>(0hc), remapindex_7) when _T_4573 : connect remapVecData[7], Queue2_UInt8_12.io.deq.bits connect remapVecValids[7], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_4574 = eq(UInt<4>(0hd), remapindex_7) when _T_4574 : connect remapVecData[7], Queue2_UInt8_13.io.deq.bits connect remapVecValids[7], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_4575 = eq(UInt<4>(0he), remapindex_7) when _T_4575 : connect remapVecData[7], Queue2_UInt8_14.io.deq.bits connect remapVecValids[7], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_4576 = eq(UInt<4>(0hf), remapindex_7) when _T_4576 : connect remapVecData[7], Queue2_UInt8_15.io.deq.bits connect remapVecValids[7], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_4577 = eq(UInt<5>(0h10), remapindex_7) when _T_4577 : connect remapVecData[7], Queue2_UInt8_16.io.deq.bits connect remapVecValids[7], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_4578 = eq(UInt<5>(0h11), remapindex_7) when _T_4578 : connect remapVecData[7], Queue2_UInt8_17.io.deq.bits connect remapVecValids[7], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_4579 = eq(UInt<5>(0h12), remapindex_7) when _T_4579 : connect remapVecData[7], Queue2_UInt8_18.io.deq.bits connect remapVecValids[7], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_4580 = eq(UInt<5>(0h13), remapindex_7) when _T_4580 : connect remapVecData[7], Queue2_UInt8_19.io.deq.bits connect remapVecValids[7], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_4581 = eq(UInt<5>(0h14), remapindex_7) when _T_4581 : connect remapVecData[7], Queue2_UInt8_20.io.deq.bits connect remapVecValids[7], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_4582 = eq(UInt<5>(0h15), remapindex_7) when _T_4582 : connect remapVecData[7], Queue2_UInt8_21.io.deq.bits connect remapVecValids[7], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_4583 = eq(UInt<5>(0h16), remapindex_7) when _T_4583 : connect remapVecData[7], Queue2_UInt8_22.io.deq.bits connect remapVecValids[7], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_4584 = eq(UInt<5>(0h17), remapindex_7) when _T_4584 : connect remapVecData[7], Queue2_UInt8_23.io.deq.bits connect remapVecValids[7], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_4585 = eq(UInt<5>(0h18), remapindex_7) when _T_4585 : connect remapVecData[7], Queue2_UInt8_24.io.deq.bits connect remapVecValids[7], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_4586 = eq(UInt<5>(0h19), remapindex_7) when _T_4586 : connect remapVecData[7], Queue2_UInt8_25.io.deq.bits connect remapVecValids[7], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_4587 = eq(UInt<5>(0h1a), remapindex_7) when _T_4587 : connect remapVecData[7], Queue2_UInt8_26.io.deq.bits connect remapVecValids[7], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_4588 = eq(UInt<5>(0h1b), remapindex_7) when _T_4588 : connect remapVecData[7], Queue2_UInt8_27.io.deq.bits connect remapVecValids[7], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_4589 = eq(UInt<5>(0h1c), remapindex_7) when _T_4589 : connect remapVecData[7], Queue2_UInt8_28.io.deq.bits connect remapVecValids[7], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_4590 = eq(UInt<5>(0h1d), remapindex_7) when _T_4590 : connect remapVecData[7], Queue2_UInt8_29.io.deq.bits connect remapVecValids[7], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_4591 = eq(UInt<5>(0h1e), remapindex_7) when _T_4591 : connect remapVecData[7], Queue2_UInt8_30.io.deq.bits connect remapVecValids[7], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_4592 = eq(UInt<5>(0h1f), remapindex_7) when _T_4592 : connect remapVecData[7], Queue2_UInt8_31.io.deq.bits connect remapVecValids[7], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_4593 = eq(UInt<1>(0h0), remapindex_8) when _T_4593 : connect remapVecData[8], Queue2_UInt8.io.deq.bits connect remapVecValids[8], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[8] node _T_4594 = eq(UInt<1>(0h1), remapindex_8) when _T_4594 : connect remapVecData[8], Queue2_UInt8_1.io.deq.bits connect remapVecValids[8], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_4595 = eq(UInt<2>(0h2), remapindex_8) when _T_4595 : connect remapVecData[8], Queue2_UInt8_2.io.deq.bits connect remapVecValids[8], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_4596 = eq(UInt<2>(0h3), remapindex_8) when _T_4596 : connect remapVecData[8], Queue2_UInt8_3.io.deq.bits connect remapVecValids[8], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_4597 = eq(UInt<3>(0h4), remapindex_8) when _T_4597 : connect remapVecData[8], Queue2_UInt8_4.io.deq.bits connect remapVecValids[8], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_4598 = eq(UInt<3>(0h5), remapindex_8) when _T_4598 : connect remapVecData[8], Queue2_UInt8_5.io.deq.bits connect remapVecValids[8], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_4599 = eq(UInt<3>(0h6), remapindex_8) when _T_4599 : connect remapVecData[8], Queue2_UInt8_6.io.deq.bits connect remapVecValids[8], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_4600 = eq(UInt<3>(0h7), remapindex_8) when _T_4600 : connect remapVecData[8], Queue2_UInt8_7.io.deq.bits connect remapVecValids[8], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_4601 = eq(UInt<4>(0h8), remapindex_8) when _T_4601 : connect remapVecData[8], Queue2_UInt8_8.io.deq.bits connect remapVecValids[8], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_4602 = eq(UInt<4>(0h9), remapindex_8) when _T_4602 : connect remapVecData[8], Queue2_UInt8_9.io.deq.bits connect remapVecValids[8], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_4603 = eq(UInt<4>(0ha), remapindex_8) when _T_4603 : connect remapVecData[8], Queue2_UInt8_10.io.deq.bits connect remapVecValids[8], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_4604 = eq(UInt<4>(0hb), remapindex_8) when _T_4604 : connect remapVecData[8], Queue2_UInt8_11.io.deq.bits connect remapVecValids[8], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_4605 = eq(UInt<4>(0hc), remapindex_8) when _T_4605 : connect remapVecData[8], Queue2_UInt8_12.io.deq.bits connect remapVecValids[8], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_4606 = eq(UInt<4>(0hd), remapindex_8) when _T_4606 : connect remapVecData[8], Queue2_UInt8_13.io.deq.bits connect remapVecValids[8], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_4607 = eq(UInt<4>(0he), remapindex_8) when _T_4607 : connect remapVecData[8], Queue2_UInt8_14.io.deq.bits connect remapVecValids[8], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_4608 = eq(UInt<4>(0hf), remapindex_8) when _T_4608 : connect remapVecData[8], Queue2_UInt8_15.io.deq.bits connect remapVecValids[8], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_4609 = eq(UInt<5>(0h10), remapindex_8) when _T_4609 : connect remapVecData[8], Queue2_UInt8_16.io.deq.bits connect remapVecValids[8], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_4610 = eq(UInt<5>(0h11), remapindex_8) when _T_4610 : connect remapVecData[8], Queue2_UInt8_17.io.deq.bits connect remapVecValids[8], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_4611 = eq(UInt<5>(0h12), remapindex_8) when _T_4611 : connect remapVecData[8], Queue2_UInt8_18.io.deq.bits connect remapVecValids[8], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_4612 = eq(UInt<5>(0h13), remapindex_8) when _T_4612 : connect remapVecData[8], Queue2_UInt8_19.io.deq.bits connect remapVecValids[8], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_4613 = eq(UInt<5>(0h14), remapindex_8) when _T_4613 : connect remapVecData[8], Queue2_UInt8_20.io.deq.bits connect remapVecValids[8], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_4614 = eq(UInt<5>(0h15), remapindex_8) when _T_4614 : connect remapVecData[8], Queue2_UInt8_21.io.deq.bits connect remapVecValids[8], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_4615 = eq(UInt<5>(0h16), remapindex_8) when _T_4615 : connect remapVecData[8], Queue2_UInt8_22.io.deq.bits connect remapVecValids[8], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_4616 = eq(UInt<5>(0h17), remapindex_8) when _T_4616 : connect remapVecData[8], Queue2_UInt8_23.io.deq.bits connect remapVecValids[8], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_4617 = eq(UInt<5>(0h18), remapindex_8) when _T_4617 : connect remapVecData[8], Queue2_UInt8_24.io.deq.bits connect remapVecValids[8], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_4618 = eq(UInt<5>(0h19), remapindex_8) when _T_4618 : connect remapVecData[8], Queue2_UInt8_25.io.deq.bits connect remapVecValids[8], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_4619 = eq(UInt<5>(0h1a), remapindex_8) when _T_4619 : connect remapVecData[8], Queue2_UInt8_26.io.deq.bits connect remapVecValids[8], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_4620 = eq(UInt<5>(0h1b), remapindex_8) when _T_4620 : connect remapVecData[8], Queue2_UInt8_27.io.deq.bits connect remapVecValids[8], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_4621 = eq(UInt<5>(0h1c), remapindex_8) when _T_4621 : connect remapVecData[8], Queue2_UInt8_28.io.deq.bits connect remapVecValids[8], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_4622 = eq(UInt<5>(0h1d), remapindex_8) when _T_4622 : connect remapVecData[8], Queue2_UInt8_29.io.deq.bits connect remapVecValids[8], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_4623 = eq(UInt<5>(0h1e), remapindex_8) when _T_4623 : connect remapVecData[8], Queue2_UInt8_30.io.deq.bits connect remapVecValids[8], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_4624 = eq(UInt<5>(0h1f), remapindex_8) when _T_4624 : connect remapVecData[8], Queue2_UInt8_31.io.deq.bits connect remapVecValids[8], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_4625 = eq(UInt<1>(0h0), remapindex_9) when _T_4625 : connect remapVecData[9], Queue2_UInt8.io.deq.bits connect remapVecValids[9], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[9] node _T_4626 = eq(UInt<1>(0h1), remapindex_9) when _T_4626 : connect remapVecData[9], Queue2_UInt8_1.io.deq.bits connect remapVecValids[9], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_4627 = eq(UInt<2>(0h2), remapindex_9) when _T_4627 : connect remapVecData[9], Queue2_UInt8_2.io.deq.bits connect remapVecValids[9], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_4628 = eq(UInt<2>(0h3), remapindex_9) when _T_4628 : connect remapVecData[9], Queue2_UInt8_3.io.deq.bits connect remapVecValids[9], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_4629 = eq(UInt<3>(0h4), remapindex_9) when _T_4629 : connect remapVecData[9], Queue2_UInt8_4.io.deq.bits connect remapVecValids[9], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_4630 = eq(UInt<3>(0h5), remapindex_9) when _T_4630 : connect remapVecData[9], Queue2_UInt8_5.io.deq.bits connect remapVecValids[9], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_4631 = eq(UInt<3>(0h6), remapindex_9) when _T_4631 : connect remapVecData[9], Queue2_UInt8_6.io.deq.bits connect remapVecValids[9], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_4632 = eq(UInt<3>(0h7), remapindex_9) when _T_4632 : connect remapVecData[9], Queue2_UInt8_7.io.deq.bits connect remapVecValids[9], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_4633 = eq(UInt<4>(0h8), remapindex_9) when _T_4633 : connect remapVecData[9], Queue2_UInt8_8.io.deq.bits connect remapVecValids[9], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_4634 = eq(UInt<4>(0h9), remapindex_9) when _T_4634 : connect remapVecData[9], Queue2_UInt8_9.io.deq.bits connect remapVecValids[9], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_4635 = eq(UInt<4>(0ha), remapindex_9) when _T_4635 : connect remapVecData[9], Queue2_UInt8_10.io.deq.bits connect remapVecValids[9], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_4636 = eq(UInt<4>(0hb), remapindex_9) when _T_4636 : connect remapVecData[9], Queue2_UInt8_11.io.deq.bits connect remapVecValids[9], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_4637 = eq(UInt<4>(0hc), remapindex_9) when _T_4637 : connect remapVecData[9], Queue2_UInt8_12.io.deq.bits connect remapVecValids[9], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_4638 = eq(UInt<4>(0hd), remapindex_9) when _T_4638 : connect remapVecData[9], Queue2_UInt8_13.io.deq.bits connect remapVecValids[9], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_4639 = eq(UInt<4>(0he), remapindex_9) when _T_4639 : connect remapVecData[9], Queue2_UInt8_14.io.deq.bits connect remapVecValids[9], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_4640 = eq(UInt<4>(0hf), remapindex_9) when _T_4640 : connect remapVecData[9], Queue2_UInt8_15.io.deq.bits connect remapVecValids[9], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_4641 = eq(UInt<5>(0h10), remapindex_9) when _T_4641 : connect remapVecData[9], Queue2_UInt8_16.io.deq.bits connect remapVecValids[9], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_4642 = eq(UInt<5>(0h11), remapindex_9) when _T_4642 : connect remapVecData[9], Queue2_UInt8_17.io.deq.bits connect remapVecValids[9], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_4643 = eq(UInt<5>(0h12), remapindex_9) when _T_4643 : connect remapVecData[9], Queue2_UInt8_18.io.deq.bits connect remapVecValids[9], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_4644 = eq(UInt<5>(0h13), remapindex_9) when _T_4644 : connect remapVecData[9], Queue2_UInt8_19.io.deq.bits connect remapVecValids[9], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_4645 = eq(UInt<5>(0h14), remapindex_9) when _T_4645 : connect remapVecData[9], Queue2_UInt8_20.io.deq.bits connect remapVecValids[9], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_4646 = eq(UInt<5>(0h15), remapindex_9) when _T_4646 : connect remapVecData[9], Queue2_UInt8_21.io.deq.bits connect remapVecValids[9], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_4647 = eq(UInt<5>(0h16), remapindex_9) when _T_4647 : connect remapVecData[9], Queue2_UInt8_22.io.deq.bits connect remapVecValids[9], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_4648 = eq(UInt<5>(0h17), remapindex_9) when _T_4648 : connect remapVecData[9], Queue2_UInt8_23.io.deq.bits connect remapVecValids[9], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_4649 = eq(UInt<5>(0h18), remapindex_9) when _T_4649 : connect remapVecData[9], Queue2_UInt8_24.io.deq.bits connect remapVecValids[9], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_4650 = eq(UInt<5>(0h19), remapindex_9) when _T_4650 : connect remapVecData[9], Queue2_UInt8_25.io.deq.bits connect remapVecValids[9], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_4651 = eq(UInt<5>(0h1a), remapindex_9) when _T_4651 : connect remapVecData[9], Queue2_UInt8_26.io.deq.bits connect remapVecValids[9], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_4652 = eq(UInt<5>(0h1b), remapindex_9) when _T_4652 : connect remapVecData[9], Queue2_UInt8_27.io.deq.bits connect remapVecValids[9], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_4653 = eq(UInt<5>(0h1c), remapindex_9) when _T_4653 : connect remapVecData[9], Queue2_UInt8_28.io.deq.bits connect remapVecValids[9], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_4654 = eq(UInt<5>(0h1d), remapindex_9) when _T_4654 : connect remapVecData[9], Queue2_UInt8_29.io.deq.bits connect remapVecValids[9], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_4655 = eq(UInt<5>(0h1e), remapindex_9) when _T_4655 : connect remapVecData[9], Queue2_UInt8_30.io.deq.bits connect remapVecValids[9], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_4656 = eq(UInt<5>(0h1f), remapindex_9) when _T_4656 : connect remapVecData[9], Queue2_UInt8_31.io.deq.bits connect remapVecValids[9], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_4657 = eq(UInt<1>(0h0), remapindex_10) when _T_4657 : connect remapVecData[10], Queue2_UInt8.io.deq.bits connect remapVecValids[10], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[10] node _T_4658 = eq(UInt<1>(0h1), remapindex_10) when _T_4658 : connect remapVecData[10], Queue2_UInt8_1.io.deq.bits connect remapVecValids[10], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_4659 = eq(UInt<2>(0h2), remapindex_10) when _T_4659 : connect remapVecData[10], Queue2_UInt8_2.io.deq.bits connect remapVecValids[10], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_4660 = eq(UInt<2>(0h3), remapindex_10) when _T_4660 : connect remapVecData[10], Queue2_UInt8_3.io.deq.bits connect remapVecValids[10], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_4661 = eq(UInt<3>(0h4), remapindex_10) when _T_4661 : connect remapVecData[10], Queue2_UInt8_4.io.deq.bits connect remapVecValids[10], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_4662 = eq(UInt<3>(0h5), remapindex_10) when _T_4662 : connect remapVecData[10], Queue2_UInt8_5.io.deq.bits connect remapVecValids[10], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_4663 = eq(UInt<3>(0h6), remapindex_10) when _T_4663 : connect remapVecData[10], Queue2_UInt8_6.io.deq.bits connect remapVecValids[10], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_4664 = eq(UInt<3>(0h7), remapindex_10) when _T_4664 : connect remapVecData[10], Queue2_UInt8_7.io.deq.bits connect remapVecValids[10], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_4665 = eq(UInt<4>(0h8), remapindex_10) when _T_4665 : connect remapVecData[10], Queue2_UInt8_8.io.deq.bits connect remapVecValids[10], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_4666 = eq(UInt<4>(0h9), remapindex_10) when _T_4666 : connect remapVecData[10], Queue2_UInt8_9.io.deq.bits connect remapVecValids[10], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_4667 = eq(UInt<4>(0ha), remapindex_10) when _T_4667 : connect remapVecData[10], Queue2_UInt8_10.io.deq.bits connect remapVecValids[10], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_4668 = eq(UInt<4>(0hb), remapindex_10) when _T_4668 : connect remapVecData[10], Queue2_UInt8_11.io.deq.bits connect remapVecValids[10], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_4669 = eq(UInt<4>(0hc), remapindex_10) when _T_4669 : connect remapVecData[10], Queue2_UInt8_12.io.deq.bits connect remapVecValids[10], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_4670 = eq(UInt<4>(0hd), remapindex_10) when _T_4670 : connect remapVecData[10], Queue2_UInt8_13.io.deq.bits connect remapVecValids[10], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_4671 = eq(UInt<4>(0he), remapindex_10) when _T_4671 : connect remapVecData[10], Queue2_UInt8_14.io.deq.bits connect remapVecValids[10], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_4672 = eq(UInt<4>(0hf), remapindex_10) when _T_4672 : connect remapVecData[10], Queue2_UInt8_15.io.deq.bits connect remapVecValids[10], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_4673 = eq(UInt<5>(0h10), remapindex_10) when _T_4673 : connect remapVecData[10], Queue2_UInt8_16.io.deq.bits connect remapVecValids[10], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_4674 = eq(UInt<5>(0h11), remapindex_10) when _T_4674 : connect remapVecData[10], Queue2_UInt8_17.io.deq.bits connect remapVecValids[10], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_4675 = eq(UInt<5>(0h12), remapindex_10) when _T_4675 : connect remapVecData[10], Queue2_UInt8_18.io.deq.bits connect remapVecValids[10], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_4676 = eq(UInt<5>(0h13), remapindex_10) when _T_4676 : connect remapVecData[10], Queue2_UInt8_19.io.deq.bits connect remapVecValids[10], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_4677 = eq(UInt<5>(0h14), remapindex_10) when _T_4677 : connect remapVecData[10], Queue2_UInt8_20.io.deq.bits connect remapVecValids[10], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_4678 = eq(UInt<5>(0h15), remapindex_10) when _T_4678 : connect remapVecData[10], Queue2_UInt8_21.io.deq.bits connect remapVecValids[10], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_4679 = eq(UInt<5>(0h16), remapindex_10) when _T_4679 : connect remapVecData[10], Queue2_UInt8_22.io.deq.bits connect remapVecValids[10], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_4680 = eq(UInt<5>(0h17), remapindex_10) when _T_4680 : connect remapVecData[10], Queue2_UInt8_23.io.deq.bits connect remapVecValids[10], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_4681 = eq(UInt<5>(0h18), remapindex_10) when _T_4681 : connect remapVecData[10], Queue2_UInt8_24.io.deq.bits connect remapVecValids[10], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_4682 = eq(UInt<5>(0h19), remapindex_10) when _T_4682 : connect remapVecData[10], Queue2_UInt8_25.io.deq.bits connect remapVecValids[10], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_4683 = eq(UInt<5>(0h1a), remapindex_10) when _T_4683 : connect remapVecData[10], Queue2_UInt8_26.io.deq.bits connect remapVecValids[10], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_4684 = eq(UInt<5>(0h1b), remapindex_10) when _T_4684 : connect remapVecData[10], Queue2_UInt8_27.io.deq.bits connect remapVecValids[10], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_4685 = eq(UInt<5>(0h1c), remapindex_10) when _T_4685 : connect remapVecData[10], Queue2_UInt8_28.io.deq.bits connect remapVecValids[10], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_4686 = eq(UInt<5>(0h1d), remapindex_10) when _T_4686 : connect remapVecData[10], Queue2_UInt8_29.io.deq.bits connect remapVecValids[10], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_4687 = eq(UInt<5>(0h1e), remapindex_10) when _T_4687 : connect remapVecData[10], Queue2_UInt8_30.io.deq.bits connect remapVecValids[10], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_4688 = eq(UInt<5>(0h1f), remapindex_10) when _T_4688 : connect remapVecData[10], Queue2_UInt8_31.io.deq.bits connect remapVecValids[10], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_4689 = eq(UInt<1>(0h0), remapindex_11) when _T_4689 : connect remapVecData[11], Queue2_UInt8.io.deq.bits connect remapVecValids[11], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[11] node _T_4690 = eq(UInt<1>(0h1), remapindex_11) when _T_4690 : connect remapVecData[11], Queue2_UInt8_1.io.deq.bits connect remapVecValids[11], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_4691 = eq(UInt<2>(0h2), remapindex_11) when _T_4691 : connect remapVecData[11], Queue2_UInt8_2.io.deq.bits connect remapVecValids[11], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_4692 = eq(UInt<2>(0h3), remapindex_11) when _T_4692 : connect remapVecData[11], Queue2_UInt8_3.io.deq.bits connect remapVecValids[11], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_4693 = eq(UInt<3>(0h4), remapindex_11) when _T_4693 : connect remapVecData[11], Queue2_UInt8_4.io.deq.bits connect remapVecValids[11], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_4694 = eq(UInt<3>(0h5), remapindex_11) when _T_4694 : connect remapVecData[11], Queue2_UInt8_5.io.deq.bits connect remapVecValids[11], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_4695 = eq(UInt<3>(0h6), remapindex_11) when _T_4695 : connect remapVecData[11], Queue2_UInt8_6.io.deq.bits connect remapVecValids[11], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_4696 = eq(UInt<3>(0h7), remapindex_11) when _T_4696 : connect remapVecData[11], Queue2_UInt8_7.io.deq.bits connect remapVecValids[11], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_4697 = eq(UInt<4>(0h8), remapindex_11) when _T_4697 : connect remapVecData[11], Queue2_UInt8_8.io.deq.bits connect remapVecValids[11], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_4698 = eq(UInt<4>(0h9), remapindex_11) when _T_4698 : connect remapVecData[11], Queue2_UInt8_9.io.deq.bits connect remapVecValids[11], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_4699 = eq(UInt<4>(0ha), remapindex_11) when _T_4699 : connect remapVecData[11], Queue2_UInt8_10.io.deq.bits connect remapVecValids[11], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_4700 = eq(UInt<4>(0hb), remapindex_11) when _T_4700 : connect remapVecData[11], Queue2_UInt8_11.io.deq.bits connect remapVecValids[11], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_4701 = eq(UInt<4>(0hc), remapindex_11) when _T_4701 : connect remapVecData[11], Queue2_UInt8_12.io.deq.bits connect remapVecValids[11], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_4702 = eq(UInt<4>(0hd), remapindex_11) when _T_4702 : connect remapVecData[11], Queue2_UInt8_13.io.deq.bits connect remapVecValids[11], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_4703 = eq(UInt<4>(0he), remapindex_11) when _T_4703 : connect remapVecData[11], Queue2_UInt8_14.io.deq.bits connect remapVecValids[11], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_4704 = eq(UInt<4>(0hf), remapindex_11) when _T_4704 : connect remapVecData[11], Queue2_UInt8_15.io.deq.bits connect remapVecValids[11], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_4705 = eq(UInt<5>(0h10), remapindex_11) when _T_4705 : connect remapVecData[11], Queue2_UInt8_16.io.deq.bits connect remapVecValids[11], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_4706 = eq(UInt<5>(0h11), remapindex_11) when _T_4706 : connect remapVecData[11], Queue2_UInt8_17.io.deq.bits connect remapVecValids[11], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_4707 = eq(UInt<5>(0h12), remapindex_11) when _T_4707 : connect remapVecData[11], Queue2_UInt8_18.io.deq.bits connect remapVecValids[11], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_4708 = eq(UInt<5>(0h13), remapindex_11) when _T_4708 : connect remapVecData[11], Queue2_UInt8_19.io.deq.bits connect remapVecValids[11], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_4709 = eq(UInt<5>(0h14), remapindex_11) when _T_4709 : connect remapVecData[11], Queue2_UInt8_20.io.deq.bits connect remapVecValids[11], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_4710 = eq(UInt<5>(0h15), remapindex_11) when _T_4710 : connect remapVecData[11], Queue2_UInt8_21.io.deq.bits connect remapVecValids[11], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_4711 = eq(UInt<5>(0h16), remapindex_11) when _T_4711 : connect remapVecData[11], Queue2_UInt8_22.io.deq.bits connect remapVecValids[11], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_4712 = eq(UInt<5>(0h17), remapindex_11) when _T_4712 : connect remapVecData[11], Queue2_UInt8_23.io.deq.bits connect remapVecValids[11], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_4713 = eq(UInt<5>(0h18), remapindex_11) when _T_4713 : connect remapVecData[11], Queue2_UInt8_24.io.deq.bits connect remapVecValids[11], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_4714 = eq(UInt<5>(0h19), remapindex_11) when _T_4714 : connect remapVecData[11], Queue2_UInt8_25.io.deq.bits connect remapVecValids[11], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_4715 = eq(UInt<5>(0h1a), remapindex_11) when _T_4715 : connect remapVecData[11], Queue2_UInt8_26.io.deq.bits connect remapVecValids[11], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_4716 = eq(UInt<5>(0h1b), remapindex_11) when _T_4716 : connect remapVecData[11], Queue2_UInt8_27.io.deq.bits connect remapVecValids[11], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_4717 = eq(UInt<5>(0h1c), remapindex_11) when _T_4717 : connect remapVecData[11], Queue2_UInt8_28.io.deq.bits connect remapVecValids[11], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_4718 = eq(UInt<5>(0h1d), remapindex_11) when _T_4718 : connect remapVecData[11], Queue2_UInt8_29.io.deq.bits connect remapVecValids[11], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_4719 = eq(UInt<5>(0h1e), remapindex_11) when _T_4719 : connect remapVecData[11], Queue2_UInt8_30.io.deq.bits connect remapVecValids[11], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_4720 = eq(UInt<5>(0h1f), remapindex_11) when _T_4720 : connect remapVecData[11], Queue2_UInt8_31.io.deq.bits connect remapVecValids[11], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_4721 = eq(UInt<1>(0h0), remapindex_12) when _T_4721 : connect remapVecData[12], Queue2_UInt8.io.deq.bits connect remapVecValids[12], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[12] node _T_4722 = eq(UInt<1>(0h1), remapindex_12) when _T_4722 : connect remapVecData[12], Queue2_UInt8_1.io.deq.bits connect remapVecValids[12], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_4723 = eq(UInt<2>(0h2), remapindex_12) when _T_4723 : connect remapVecData[12], Queue2_UInt8_2.io.deq.bits connect remapVecValids[12], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_4724 = eq(UInt<2>(0h3), remapindex_12) when _T_4724 : connect remapVecData[12], Queue2_UInt8_3.io.deq.bits connect remapVecValids[12], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_4725 = eq(UInt<3>(0h4), remapindex_12) when _T_4725 : connect remapVecData[12], Queue2_UInt8_4.io.deq.bits connect remapVecValids[12], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_4726 = eq(UInt<3>(0h5), remapindex_12) when _T_4726 : connect remapVecData[12], Queue2_UInt8_5.io.deq.bits connect remapVecValids[12], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_4727 = eq(UInt<3>(0h6), remapindex_12) when _T_4727 : connect remapVecData[12], Queue2_UInt8_6.io.deq.bits connect remapVecValids[12], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_4728 = eq(UInt<3>(0h7), remapindex_12) when _T_4728 : connect remapVecData[12], Queue2_UInt8_7.io.deq.bits connect remapVecValids[12], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_4729 = eq(UInt<4>(0h8), remapindex_12) when _T_4729 : connect remapVecData[12], Queue2_UInt8_8.io.deq.bits connect remapVecValids[12], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_4730 = eq(UInt<4>(0h9), remapindex_12) when _T_4730 : connect remapVecData[12], Queue2_UInt8_9.io.deq.bits connect remapVecValids[12], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_4731 = eq(UInt<4>(0ha), remapindex_12) when _T_4731 : connect remapVecData[12], Queue2_UInt8_10.io.deq.bits connect remapVecValids[12], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_4732 = eq(UInt<4>(0hb), remapindex_12) when _T_4732 : connect remapVecData[12], Queue2_UInt8_11.io.deq.bits connect remapVecValids[12], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_4733 = eq(UInt<4>(0hc), remapindex_12) when _T_4733 : connect remapVecData[12], Queue2_UInt8_12.io.deq.bits connect remapVecValids[12], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_4734 = eq(UInt<4>(0hd), remapindex_12) when _T_4734 : connect remapVecData[12], Queue2_UInt8_13.io.deq.bits connect remapVecValids[12], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_4735 = eq(UInt<4>(0he), remapindex_12) when _T_4735 : connect remapVecData[12], Queue2_UInt8_14.io.deq.bits connect remapVecValids[12], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_4736 = eq(UInt<4>(0hf), remapindex_12) when _T_4736 : connect remapVecData[12], Queue2_UInt8_15.io.deq.bits connect remapVecValids[12], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_4737 = eq(UInt<5>(0h10), remapindex_12) when _T_4737 : connect remapVecData[12], Queue2_UInt8_16.io.deq.bits connect remapVecValids[12], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_4738 = eq(UInt<5>(0h11), remapindex_12) when _T_4738 : connect remapVecData[12], Queue2_UInt8_17.io.deq.bits connect remapVecValids[12], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_4739 = eq(UInt<5>(0h12), remapindex_12) when _T_4739 : connect remapVecData[12], Queue2_UInt8_18.io.deq.bits connect remapVecValids[12], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_4740 = eq(UInt<5>(0h13), remapindex_12) when _T_4740 : connect remapVecData[12], Queue2_UInt8_19.io.deq.bits connect remapVecValids[12], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_4741 = eq(UInt<5>(0h14), remapindex_12) when _T_4741 : connect remapVecData[12], Queue2_UInt8_20.io.deq.bits connect remapVecValids[12], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_4742 = eq(UInt<5>(0h15), remapindex_12) when _T_4742 : connect remapVecData[12], Queue2_UInt8_21.io.deq.bits connect remapVecValids[12], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_4743 = eq(UInt<5>(0h16), remapindex_12) when _T_4743 : connect remapVecData[12], Queue2_UInt8_22.io.deq.bits connect remapVecValids[12], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_4744 = eq(UInt<5>(0h17), remapindex_12) when _T_4744 : connect remapVecData[12], Queue2_UInt8_23.io.deq.bits connect remapVecValids[12], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_4745 = eq(UInt<5>(0h18), remapindex_12) when _T_4745 : connect remapVecData[12], Queue2_UInt8_24.io.deq.bits connect remapVecValids[12], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_4746 = eq(UInt<5>(0h19), remapindex_12) when _T_4746 : connect remapVecData[12], Queue2_UInt8_25.io.deq.bits connect remapVecValids[12], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_4747 = eq(UInt<5>(0h1a), remapindex_12) when _T_4747 : connect remapVecData[12], Queue2_UInt8_26.io.deq.bits connect remapVecValids[12], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_4748 = eq(UInt<5>(0h1b), remapindex_12) when _T_4748 : connect remapVecData[12], Queue2_UInt8_27.io.deq.bits connect remapVecValids[12], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_4749 = eq(UInt<5>(0h1c), remapindex_12) when _T_4749 : connect remapVecData[12], Queue2_UInt8_28.io.deq.bits connect remapVecValids[12], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_4750 = eq(UInt<5>(0h1d), remapindex_12) when _T_4750 : connect remapVecData[12], Queue2_UInt8_29.io.deq.bits connect remapVecValids[12], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_4751 = eq(UInt<5>(0h1e), remapindex_12) when _T_4751 : connect remapVecData[12], Queue2_UInt8_30.io.deq.bits connect remapVecValids[12], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_4752 = eq(UInt<5>(0h1f), remapindex_12) when _T_4752 : connect remapVecData[12], Queue2_UInt8_31.io.deq.bits connect remapVecValids[12], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_4753 = eq(UInt<1>(0h0), remapindex_13) when _T_4753 : connect remapVecData[13], Queue2_UInt8.io.deq.bits connect remapVecValids[13], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[13] node _T_4754 = eq(UInt<1>(0h1), remapindex_13) when _T_4754 : connect remapVecData[13], Queue2_UInt8_1.io.deq.bits connect remapVecValids[13], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_4755 = eq(UInt<2>(0h2), remapindex_13) when _T_4755 : connect remapVecData[13], Queue2_UInt8_2.io.deq.bits connect remapVecValids[13], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_4756 = eq(UInt<2>(0h3), remapindex_13) when _T_4756 : connect remapVecData[13], Queue2_UInt8_3.io.deq.bits connect remapVecValids[13], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_4757 = eq(UInt<3>(0h4), remapindex_13) when _T_4757 : connect remapVecData[13], Queue2_UInt8_4.io.deq.bits connect remapVecValids[13], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_4758 = eq(UInt<3>(0h5), remapindex_13) when _T_4758 : connect remapVecData[13], Queue2_UInt8_5.io.deq.bits connect remapVecValids[13], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_4759 = eq(UInt<3>(0h6), remapindex_13) when _T_4759 : connect remapVecData[13], Queue2_UInt8_6.io.deq.bits connect remapVecValids[13], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_4760 = eq(UInt<3>(0h7), remapindex_13) when _T_4760 : connect remapVecData[13], Queue2_UInt8_7.io.deq.bits connect remapVecValids[13], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_4761 = eq(UInt<4>(0h8), remapindex_13) when _T_4761 : connect remapVecData[13], Queue2_UInt8_8.io.deq.bits connect remapVecValids[13], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_4762 = eq(UInt<4>(0h9), remapindex_13) when _T_4762 : connect remapVecData[13], Queue2_UInt8_9.io.deq.bits connect remapVecValids[13], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_4763 = eq(UInt<4>(0ha), remapindex_13) when _T_4763 : connect remapVecData[13], Queue2_UInt8_10.io.deq.bits connect remapVecValids[13], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_4764 = eq(UInt<4>(0hb), remapindex_13) when _T_4764 : connect remapVecData[13], Queue2_UInt8_11.io.deq.bits connect remapVecValids[13], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_4765 = eq(UInt<4>(0hc), remapindex_13) when _T_4765 : connect remapVecData[13], Queue2_UInt8_12.io.deq.bits connect remapVecValids[13], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_4766 = eq(UInt<4>(0hd), remapindex_13) when _T_4766 : connect remapVecData[13], Queue2_UInt8_13.io.deq.bits connect remapVecValids[13], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_4767 = eq(UInt<4>(0he), remapindex_13) when _T_4767 : connect remapVecData[13], Queue2_UInt8_14.io.deq.bits connect remapVecValids[13], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_4768 = eq(UInt<4>(0hf), remapindex_13) when _T_4768 : connect remapVecData[13], Queue2_UInt8_15.io.deq.bits connect remapVecValids[13], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_4769 = eq(UInt<5>(0h10), remapindex_13) when _T_4769 : connect remapVecData[13], Queue2_UInt8_16.io.deq.bits connect remapVecValids[13], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_4770 = eq(UInt<5>(0h11), remapindex_13) when _T_4770 : connect remapVecData[13], Queue2_UInt8_17.io.deq.bits connect remapVecValids[13], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_4771 = eq(UInt<5>(0h12), remapindex_13) when _T_4771 : connect remapVecData[13], Queue2_UInt8_18.io.deq.bits connect remapVecValids[13], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_4772 = eq(UInt<5>(0h13), remapindex_13) when _T_4772 : connect remapVecData[13], Queue2_UInt8_19.io.deq.bits connect remapVecValids[13], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_4773 = eq(UInt<5>(0h14), remapindex_13) when _T_4773 : connect remapVecData[13], Queue2_UInt8_20.io.deq.bits connect remapVecValids[13], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_4774 = eq(UInt<5>(0h15), remapindex_13) when _T_4774 : connect remapVecData[13], Queue2_UInt8_21.io.deq.bits connect remapVecValids[13], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_4775 = eq(UInt<5>(0h16), remapindex_13) when _T_4775 : connect remapVecData[13], Queue2_UInt8_22.io.deq.bits connect remapVecValids[13], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_4776 = eq(UInt<5>(0h17), remapindex_13) when _T_4776 : connect remapVecData[13], Queue2_UInt8_23.io.deq.bits connect remapVecValids[13], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_4777 = eq(UInt<5>(0h18), remapindex_13) when _T_4777 : connect remapVecData[13], Queue2_UInt8_24.io.deq.bits connect remapVecValids[13], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_4778 = eq(UInt<5>(0h19), remapindex_13) when _T_4778 : connect remapVecData[13], Queue2_UInt8_25.io.deq.bits connect remapVecValids[13], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_4779 = eq(UInt<5>(0h1a), remapindex_13) when _T_4779 : connect remapVecData[13], Queue2_UInt8_26.io.deq.bits connect remapVecValids[13], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_4780 = eq(UInt<5>(0h1b), remapindex_13) when _T_4780 : connect remapVecData[13], Queue2_UInt8_27.io.deq.bits connect remapVecValids[13], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_4781 = eq(UInt<5>(0h1c), remapindex_13) when _T_4781 : connect remapVecData[13], Queue2_UInt8_28.io.deq.bits connect remapVecValids[13], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_4782 = eq(UInt<5>(0h1d), remapindex_13) when _T_4782 : connect remapVecData[13], Queue2_UInt8_29.io.deq.bits connect remapVecValids[13], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_4783 = eq(UInt<5>(0h1e), remapindex_13) when _T_4783 : connect remapVecData[13], Queue2_UInt8_30.io.deq.bits connect remapVecValids[13], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_4784 = eq(UInt<5>(0h1f), remapindex_13) when _T_4784 : connect remapVecData[13], Queue2_UInt8_31.io.deq.bits connect remapVecValids[13], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_4785 = eq(UInt<1>(0h0), remapindex_14) when _T_4785 : connect remapVecData[14], Queue2_UInt8.io.deq.bits connect remapVecValids[14], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[14] node _T_4786 = eq(UInt<1>(0h1), remapindex_14) when _T_4786 : connect remapVecData[14], Queue2_UInt8_1.io.deq.bits connect remapVecValids[14], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_4787 = eq(UInt<2>(0h2), remapindex_14) when _T_4787 : connect remapVecData[14], Queue2_UInt8_2.io.deq.bits connect remapVecValids[14], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_4788 = eq(UInt<2>(0h3), remapindex_14) when _T_4788 : connect remapVecData[14], Queue2_UInt8_3.io.deq.bits connect remapVecValids[14], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_4789 = eq(UInt<3>(0h4), remapindex_14) when _T_4789 : connect remapVecData[14], Queue2_UInt8_4.io.deq.bits connect remapVecValids[14], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_4790 = eq(UInt<3>(0h5), remapindex_14) when _T_4790 : connect remapVecData[14], Queue2_UInt8_5.io.deq.bits connect remapVecValids[14], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_4791 = eq(UInt<3>(0h6), remapindex_14) when _T_4791 : connect remapVecData[14], Queue2_UInt8_6.io.deq.bits connect remapVecValids[14], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_4792 = eq(UInt<3>(0h7), remapindex_14) when _T_4792 : connect remapVecData[14], Queue2_UInt8_7.io.deq.bits connect remapVecValids[14], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_4793 = eq(UInt<4>(0h8), remapindex_14) when _T_4793 : connect remapVecData[14], Queue2_UInt8_8.io.deq.bits connect remapVecValids[14], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_4794 = eq(UInt<4>(0h9), remapindex_14) when _T_4794 : connect remapVecData[14], Queue2_UInt8_9.io.deq.bits connect remapVecValids[14], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_4795 = eq(UInt<4>(0ha), remapindex_14) when _T_4795 : connect remapVecData[14], Queue2_UInt8_10.io.deq.bits connect remapVecValids[14], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_4796 = eq(UInt<4>(0hb), remapindex_14) when _T_4796 : connect remapVecData[14], Queue2_UInt8_11.io.deq.bits connect remapVecValids[14], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_4797 = eq(UInt<4>(0hc), remapindex_14) when _T_4797 : connect remapVecData[14], Queue2_UInt8_12.io.deq.bits connect remapVecValids[14], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_4798 = eq(UInt<4>(0hd), remapindex_14) when _T_4798 : connect remapVecData[14], Queue2_UInt8_13.io.deq.bits connect remapVecValids[14], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_4799 = eq(UInt<4>(0he), remapindex_14) when _T_4799 : connect remapVecData[14], Queue2_UInt8_14.io.deq.bits connect remapVecValids[14], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_4800 = eq(UInt<4>(0hf), remapindex_14) when _T_4800 : connect remapVecData[14], Queue2_UInt8_15.io.deq.bits connect remapVecValids[14], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_4801 = eq(UInt<5>(0h10), remapindex_14) when _T_4801 : connect remapVecData[14], Queue2_UInt8_16.io.deq.bits connect remapVecValids[14], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_4802 = eq(UInt<5>(0h11), remapindex_14) when _T_4802 : connect remapVecData[14], Queue2_UInt8_17.io.deq.bits connect remapVecValids[14], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_4803 = eq(UInt<5>(0h12), remapindex_14) when _T_4803 : connect remapVecData[14], Queue2_UInt8_18.io.deq.bits connect remapVecValids[14], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_4804 = eq(UInt<5>(0h13), remapindex_14) when _T_4804 : connect remapVecData[14], Queue2_UInt8_19.io.deq.bits connect remapVecValids[14], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_4805 = eq(UInt<5>(0h14), remapindex_14) when _T_4805 : connect remapVecData[14], Queue2_UInt8_20.io.deq.bits connect remapVecValids[14], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_4806 = eq(UInt<5>(0h15), remapindex_14) when _T_4806 : connect remapVecData[14], Queue2_UInt8_21.io.deq.bits connect remapVecValids[14], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_4807 = eq(UInt<5>(0h16), remapindex_14) when _T_4807 : connect remapVecData[14], Queue2_UInt8_22.io.deq.bits connect remapVecValids[14], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_4808 = eq(UInt<5>(0h17), remapindex_14) when _T_4808 : connect remapVecData[14], Queue2_UInt8_23.io.deq.bits connect remapVecValids[14], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_4809 = eq(UInt<5>(0h18), remapindex_14) when _T_4809 : connect remapVecData[14], Queue2_UInt8_24.io.deq.bits connect remapVecValids[14], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_4810 = eq(UInt<5>(0h19), remapindex_14) when _T_4810 : connect remapVecData[14], Queue2_UInt8_25.io.deq.bits connect remapVecValids[14], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_4811 = eq(UInt<5>(0h1a), remapindex_14) when _T_4811 : connect remapVecData[14], Queue2_UInt8_26.io.deq.bits connect remapVecValids[14], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_4812 = eq(UInt<5>(0h1b), remapindex_14) when _T_4812 : connect remapVecData[14], Queue2_UInt8_27.io.deq.bits connect remapVecValids[14], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_4813 = eq(UInt<5>(0h1c), remapindex_14) when _T_4813 : connect remapVecData[14], Queue2_UInt8_28.io.deq.bits connect remapVecValids[14], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_4814 = eq(UInt<5>(0h1d), remapindex_14) when _T_4814 : connect remapVecData[14], Queue2_UInt8_29.io.deq.bits connect remapVecValids[14], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_4815 = eq(UInt<5>(0h1e), remapindex_14) when _T_4815 : connect remapVecData[14], Queue2_UInt8_30.io.deq.bits connect remapVecValids[14], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_4816 = eq(UInt<5>(0h1f), remapindex_14) when _T_4816 : connect remapVecData[14], Queue2_UInt8_31.io.deq.bits connect remapVecValids[14], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_4817 = eq(UInt<1>(0h0), remapindex_15) when _T_4817 : connect remapVecData[15], Queue2_UInt8.io.deq.bits connect remapVecValids[15], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[15] node _T_4818 = eq(UInt<1>(0h1), remapindex_15) when _T_4818 : connect remapVecData[15], Queue2_UInt8_1.io.deq.bits connect remapVecValids[15], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_4819 = eq(UInt<2>(0h2), remapindex_15) when _T_4819 : connect remapVecData[15], Queue2_UInt8_2.io.deq.bits connect remapVecValids[15], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_4820 = eq(UInt<2>(0h3), remapindex_15) when _T_4820 : connect remapVecData[15], Queue2_UInt8_3.io.deq.bits connect remapVecValids[15], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_4821 = eq(UInt<3>(0h4), remapindex_15) when _T_4821 : connect remapVecData[15], Queue2_UInt8_4.io.deq.bits connect remapVecValids[15], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_4822 = eq(UInt<3>(0h5), remapindex_15) when _T_4822 : connect remapVecData[15], Queue2_UInt8_5.io.deq.bits connect remapVecValids[15], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_4823 = eq(UInt<3>(0h6), remapindex_15) when _T_4823 : connect remapVecData[15], Queue2_UInt8_6.io.deq.bits connect remapVecValids[15], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_4824 = eq(UInt<3>(0h7), remapindex_15) when _T_4824 : connect remapVecData[15], Queue2_UInt8_7.io.deq.bits connect remapVecValids[15], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_4825 = eq(UInt<4>(0h8), remapindex_15) when _T_4825 : connect remapVecData[15], Queue2_UInt8_8.io.deq.bits connect remapVecValids[15], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_4826 = eq(UInt<4>(0h9), remapindex_15) when _T_4826 : connect remapVecData[15], Queue2_UInt8_9.io.deq.bits connect remapVecValids[15], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_4827 = eq(UInt<4>(0ha), remapindex_15) when _T_4827 : connect remapVecData[15], Queue2_UInt8_10.io.deq.bits connect remapVecValids[15], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_4828 = eq(UInt<4>(0hb), remapindex_15) when _T_4828 : connect remapVecData[15], Queue2_UInt8_11.io.deq.bits connect remapVecValids[15], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_4829 = eq(UInt<4>(0hc), remapindex_15) when _T_4829 : connect remapVecData[15], Queue2_UInt8_12.io.deq.bits connect remapVecValids[15], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_4830 = eq(UInt<4>(0hd), remapindex_15) when _T_4830 : connect remapVecData[15], Queue2_UInt8_13.io.deq.bits connect remapVecValids[15], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_4831 = eq(UInt<4>(0he), remapindex_15) when _T_4831 : connect remapVecData[15], Queue2_UInt8_14.io.deq.bits connect remapVecValids[15], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_4832 = eq(UInt<4>(0hf), remapindex_15) when _T_4832 : connect remapVecData[15], Queue2_UInt8_15.io.deq.bits connect remapVecValids[15], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_4833 = eq(UInt<5>(0h10), remapindex_15) when _T_4833 : connect remapVecData[15], Queue2_UInt8_16.io.deq.bits connect remapVecValids[15], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_4834 = eq(UInt<5>(0h11), remapindex_15) when _T_4834 : connect remapVecData[15], Queue2_UInt8_17.io.deq.bits connect remapVecValids[15], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_4835 = eq(UInt<5>(0h12), remapindex_15) when _T_4835 : connect remapVecData[15], Queue2_UInt8_18.io.deq.bits connect remapVecValids[15], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_4836 = eq(UInt<5>(0h13), remapindex_15) when _T_4836 : connect remapVecData[15], Queue2_UInt8_19.io.deq.bits connect remapVecValids[15], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_4837 = eq(UInt<5>(0h14), remapindex_15) when _T_4837 : connect remapVecData[15], Queue2_UInt8_20.io.deq.bits connect remapVecValids[15], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_4838 = eq(UInt<5>(0h15), remapindex_15) when _T_4838 : connect remapVecData[15], Queue2_UInt8_21.io.deq.bits connect remapVecValids[15], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_4839 = eq(UInt<5>(0h16), remapindex_15) when _T_4839 : connect remapVecData[15], Queue2_UInt8_22.io.deq.bits connect remapVecValids[15], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_4840 = eq(UInt<5>(0h17), remapindex_15) when _T_4840 : connect remapVecData[15], Queue2_UInt8_23.io.deq.bits connect remapVecValids[15], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_4841 = eq(UInt<5>(0h18), remapindex_15) when _T_4841 : connect remapVecData[15], Queue2_UInt8_24.io.deq.bits connect remapVecValids[15], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_4842 = eq(UInt<5>(0h19), remapindex_15) when _T_4842 : connect remapVecData[15], Queue2_UInt8_25.io.deq.bits connect remapVecValids[15], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_4843 = eq(UInt<5>(0h1a), remapindex_15) when _T_4843 : connect remapVecData[15], Queue2_UInt8_26.io.deq.bits connect remapVecValids[15], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_4844 = eq(UInt<5>(0h1b), remapindex_15) when _T_4844 : connect remapVecData[15], Queue2_UInt8_27.io.deq.bits connect remapVecValids[15], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_4845 = eq(UInt<5>(0h1c), remapindex_15) when _T_4845 : connect remapVecData[15], Queue2_UInt8_28.io.deq.bits connect remapVecValids[15], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_4846 = eq(UInt<5>(0h1d), remapindex_15) when _T_4846 : connect remapVecData[15], Queue2_UInt8_29.io.deq.bits connect remapVecValids[15], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_4847 = eq(UInt<5>(0h1e), remapindex_15) when _T_4847 : connect remapVecData[15], Queue2_UInt8_30.io.deq.bits connect remapVecValids[15], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_4848 = eq(UInt<5>(0h1f), remapindex_15) when _T_4848 : connect remapVecData[15], Queue2_UInt8_31.io.deq.bits connect remapVecValids[15], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_4849 = eq(UInt<1>(0h0), remapindex_16) when _T_4849 : connect remapVecData[16], Queue2_UInt8.io.deq.bits connect remapVecValids[16], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[16] node _T_4850 = eq(UInt<1>(0h1), remapindex_16) when _T_4850 : connect remapVecData[16], Queue2_UInt8_1.io.deq.bits connect remapVecValids[16], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_4851 = eq(UInt<2>(0h2), remapindex_16) when _T_4851 : connect remapVecData[16], Queue2_UInt8_2.io.deq.bits connect remapVecValids[16], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_4852 = eq(UInt<2>(0h3), remapindex_16) when _T_4852 : connect remapVecData[16], Queue2_UInt8_3.io.deq.bits connect remapVecValids[16], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_4853 = eq(UInt<3>(0h4), remapindex_16) when _T_4853 : connect remapVecData[16], Queue2_UInt8_4.io.deq.bits connect remapVecValids[16], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_4854 = eq(UInt<3>(0h5), remapindex_16) when _T_4854 : connect remapVecData[16], Queue2_UInt8_5.io.deq.bits connect remapVecValids[16], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_4855 = eq(UInt<3>(0h6), remapindex_16) when _T_4855 : connect remapVecData[16], Queue2_UInt8_6.io.deq.bits connect remapVecValids[16], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_4856 = eq(UInt<3>(0h7), remapindex_16) when _T_4856 : connect remapVecData[16], Queue2_UInt8_7.io.deq.bits connect remapVecValids[16], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_4857 = eq(UInt<4>(0h8), remapindex_16) when _T_4857 : connect remapVecData[16], Queue2_UInt8_8.io.deq.bits connect remapVecValids[16], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_4858 = eq(UInt<4>(0h9), remapindex_16) when _T_4858 : connect remapVecData[16], Queue2_UInt8_9.io.deq.bits connect remapVecValids[16], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_4859 = eq(UInt<4>(0ha), remapindex_16) when _T_4859 : connect remapVecData[16], Queue2_UInt8_10.io.deq.bits connect remapVecValids[16], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_4860 = eq(UInt<4>(0hb), remapindex_16) when _T_4860 : connect remapVecData[16], Queue2_UInt8_11.io.deq.bits connect remapVecValids[16], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_4861 = eq(UInt<4>(0hc), remapindex_16) when _T_4861 : connect remapVecData[16], Queue2_UInt8_12.io.deq.bits connect remapVecValids[16], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_4862 = eq(UInt<4>(0hd), remapindex_16) when _T_4862 : connect remapVecData[16], Queue2_UInt8_13.io.deq.bits connect remapVecValids[16], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_4863 = eq(UInt<4>(0he), remapindex_16) when _T_4863 : connect remapVecData[16], Queue2_UInt8_14.io.deq.bits connect remapVecValids[16], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_4864 = eq(UInt<4>(0hf), remapindex_16) when _T_4864 : connect remapVecData[16], Queue2_UInt8_15.io.deq.bits connect remapVecValids[16], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_4865 = eq(UInt<5>(0h10), remapindex_16) when _T_4865 : connect remapVecData[16], Queue2_UInt8_16.io.deq.bits connect remapVecValids[16], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_4866 = eq(UInt<5>(0h11), remapindex_16) when _T_4866 : connect remapVecData[16], Queue2_UInt8_17.io.deq.bits connect remapVecValids[16], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_4867 = eq(UInt<5>(0h12), remapindex_16) when _T_4867 : connect remapVecData[16], Queue2_UInt8_18.io.deq.bits connect remapVecValids[16], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_4868 = eq(UInt<5>(0h13), remapindex_16) when _T_4868 : connect remapVecData[16], Queue2_UInt8_19.io.deq.bits connect remapVecValids[16], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_4869 = eq(UInt<5>(0h14), remapindex_16) when _T_4869 : connect remapVecData[16], Queue2_UInt8_20.io.deq.bits connect remapVecValids[16], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_4870 = eq(UInt<5>(0h15), remapindex_16) when _T_4870 : connect remapVecData[16], Queue2_UInt8_21.io.deq.bits connect remapVecValids[16], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_4871 = eq(UInt<5>(0h16), remapindex_16) when _T_4871 : connect remapVecData[16], Queue2_UInt8_22.io.deq.bits connect remapVecValids[16], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_4872 = eq(UInt<5>(0h17), remapindex_16) when _T_4872 : connect remapVecData[16], Queue2_UInt8_23.io.deq.bits connect remapVecValids[16], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_4873 = eq(UInt<5>(0h18), remapindex_16) when _T_4873 : connect remapVecData[16], Queue2_UInt8_24.io.deq.bits connect remapVecValids[16], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_4874 = eq(UInt<5>(0h19), remapindex_16) when _T_4874 : connect remapVecData[16], Queue2_UInt8_25.io.deq.bits connect remapVecValids[16], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_4875 = eq(UInt<5>(0h1a), remapindex_16) when _T_4875 : connect remapVecData[16], Queue2_UInt8_26.io.deq.bits connect remapVecValids[16], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_4876 = eq(UInt<5>(0h1b), remapindex_16) when _T_4876 : connect remapVecData[16], Queue2_UInt8_27.io.deq.bits connect remapVecValids[16], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_4877 = eq(UInt<5>(0h1c), remapindex_16) when _T_4877 : connect remapVecData[16], Queue2_UInt8_28.io.deq.bits connect remapVecValids[16], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_4878 = eq(UInt<5>(0h1d), remapindex_16) when _T_4878 : connect remapVecData[16], Queue2_UInt8_29.io.deq.bits connect remapVecValids[16], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_4879 = eq(UInt<5>(0h1e), remapindex_16) when _T_4879 : connect remapVecData[16], Queue2_UInt8_30.io.deq.bits connect remapVecValids[16], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_4880 = eq(UInt<5>(0h1f), remapindex_16) when _T_4880 : connect remapVecData[16], Queue2_UInt8_31.io.deq.bits connect remapVecValids[16], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_4881 = eq(UInt<1>(0h0), remapindex_17) when _T_4881 : connect remapVecData[17], Queue2_UInt8.io.deq.bits connect remapVecValids[17], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[17] node _T_4882 = eq(UInt<1>(0h1), remapindex_17) when _T_4882 : connect remapVecData[17], Queue2_UInt8_1.io.deq.bits connect remapVecValids[17], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_4883 = eq(UInt<2>(0h2), remapindex_17) when _T_4883 : connect remapVecData[17], Queue2_UInt8_2.io.deq.bits connect remapVecValids[17], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_4884 = eq(UInt<2>(0h3), remapindex_17) when _T_4884 : connect remapVecData[17], Queue2_UInt8_3.io.deq.bits connect remapVecValids[17], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_4885 = eq(UInt<3>(0h4), remapindex_17) when _T_4885 : connect remapVecData[17], Queue2_UInt8_4.io.deq.bits connect remapVecValids[17], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_4886 = eq(UInt<3>(0h5), remapindex_17) when _T_4886 : connect remapVecData[17], Queue2_UInt8_5.io.deq.bits connect remapVecValids[17], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_4887 = eq(UInt<3>(0h6), remapindex_17) when _T_4887 : connect remapVecData[17], Queue2_UInt8_6.io.deq.bits connect remapVecValids[17], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_4888 = eq(UInt<3>(0h7), remapindex_17) when _T_4888 : connect remapVecData[17], Queue2_UInt8_7.io.deq.bits connect remapVecValids[17], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_4889 = eq(UInt<4>(0h8), remapindex_17) when _T_4889 : connect remapVecData[17], Queue2_UInt8_8.io.deq.bits connect remapVecValids[17], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_4890 = eq(UInt<4>(0h9), remapindex_17) when _T_4890 : connect remapVecData[17], Queue2_UInt8_9.io.deq.bits connect remapVecValids[17], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_4891 = eq(UInt<4>(0ha), remapindex_17) when _T_4891 : connect remapVecData[17], Queue2_UInt8_10.io.deq.bits connect remapVecValids[17], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_4892 = eq(UInt<4>(0hb), remapindex_17) when _T_4892 : connect remapVecData[17], Queue2_UInt8_11.io.deq.bits connect remapVecValids[17], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_4893 = eq(UInt<4>(0hc), remapindex_17) when _T_4893 : connect remapVecData[17], Queue2_UInt8_12.io.deq.bits connect remapVecValids[17], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_4894 = eq(UInt<4>(0hd), remapindex_17) when _T_4894 : connect remapVecData[17], Queue2_UInt8_13.io.deq.bits connect remapVecValids[17], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_4895 = eq(UInt<4>(0he), remapindex_17) when _T_4895 : connect remapVecData[17], Queue2_UInt8_14.io.deq.bits connect remapVecValids[17], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_4896 = eq(UInt<4>(0hf), remapindex_17) when _T_4896 : connect remapVecData[17], Queue2_UInt8_15.io.deq.bits connect remapVecValids[17], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_4897 = eq(UInt<5>(0h10), remapindex_17) when _T_4897 : connect remapVecData[17], Queue2_UInt8_16.io.deq.bits connect remapVecValids[17], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_4898 = eq(UInt<5>(0h11), remapindex_17) when _T_4898 : connect remapVecData[17], Queue2_UInt8_17.io.deq.bits connect remapVecValids[17], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_4899 = eq(UInt<5>(0h12), remapindex_17) when _T_4899 : connect remapVecData[17], Queue2_UInt8_18.io.deq.bits connect remapVecValids[17], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_4900 = eq(UInt<5>(0h13), remapindex_17) when _T_4900 : connect remapVecData[17], Queue2_UInt8_19.io.deq.bits connect remapVecValids[17], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_4901 = eq(UInt<5>(0h14), remapindex_17) when _T_4901 : connect remapVecData[17], Queue2_UInt8_20.io.deq.bits connect remapVecValids[17], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_4902 = eq(UInt<5>(0h15), remapindex_17) when _T_4902 : connect remapVecData[17], Queue2_UInt8_21.io.deq.bits connect remapVecValids[17], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_4903 = eq(UInt<5>(0h16), remapindex_17) when _T_4903 : connect remapVecData[17], Queue2_UInt8_22.io.deq.bits connect remapVecValids[17], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_4904 = eq(UInt<5>(0h17), remapindex_17) when _T_4904 : connect remapVecData[17], Queue2_UInt8_23.io.deq.bits connect remapVecValids[17], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_4905 = eq(UInt<5>(0h18), remapindex_17) when _T_4905 : connect remapVecData[17], Queue2_UInt8_24.io.deq.bits connect remapVecValids[17], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_4906 = eq(UInt<5>(0h19), remapindex_17) when _T_4906 : connect remapVecData[17], Queue2_UInt8_25.io.deq.bits connect remapVecValids[17], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_4907 = eq(UInt<5>(0h1a), remapindex_17) when _T_4907 : connect remapVecData[17], Queue2_UInt8_26.io.deq.bits connect remapVecValids[17], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_4908 = eq(UInt<5>(0h1b), remapindex_17) when _T_4908 : connect remapVecData[17], Queue2_UInt8_27.io.deq.bits connect remapVecValids[17], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_4909 = eq(UInt<5>(0h1c), remapindex_17) when _T_4909 : connect remapVecData[17], Queue2_UInt8_28.io.deq.bits connect remapVecValids[17], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_4910 = eq(UInt<5>(0h1d), remapindex_17) when _T_4910 : connect remapVecData[17], Queue2_UInt8_29.io.deq.bits connect remapVecValids[17], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_4911 = eq(UInt<5>(0h1e), remapindex_17) when _T_4911 : connect remapVecData[17], Queue2_UInt8_30.io.deq.bits connect remapVecValids[17], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_4912 = eq(UInt<5>(0h1f), remapindex_17) when _T_4912 : connect remapVecData[17], Queue2_UInt8_31.io.deq.bits connect remapVecValids[17], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_4913 = eq(UInt<1>(0h0), remapindex_18) when _T_4913 : connect remapVecData[18], Queue2_UInt8.io.deq.bits connect remapVecValids[18], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[18] node _T_4914 = eq(UInt<1>(0h1), remapindex_18) when _T_4914 : connect remapVecData[18], Queue2_UInt8_1.io.deq.bits connect remapVecValids[18], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_4915 = eq(UInt<2>(0h2), remapindex_18) when _T_4915 : connect remapVecData[18], Queue2_UInt8_2.io.deq.bits connect remapVecValids[18], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_4916 = eq(UInt<2>(0h3), remapindex_18) when _T_4916 : connect remapVecData[18], Queue2_UInt8_3.io.deq.bits connect remapVecValids[18], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_4917 = eq(UInt<3>(0h4), remapindex_18) when _T_4917 : connect remapVecData[18], Queue2_UInt8_4.io.deq.bits connect remapVecValids[18], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_4918 = eq(UInt<3>(0h5), remapindex_18) when _T_4918 : connect remapVecData[18], Queue2_UInt8_5.io.deq.bits connect remapVecValids[18], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_4919 = eq(UInt<3>(0h6), remapindex_18) when _T_4919 : connect remapVecData[18], Queue2_UInt8_6.io.deq.bits connect remapVecValids[18], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_4920 = eq(UInt<3>(0h7), remapindex_18) when _T_4920 : connect remapVecData[18], Queue2_UInt8_7.io.deq.bits connect remapVecValids[18], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_4921 = eq(UInt<4>(0h8), remapindex_18) when _T_4921 : connect remapVecData[18], Queue2_UInt8_8.io.deq.bits connect remapVecValids[18], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_4922 = eq(UInt<4>(0h9), remapindex_18) when _T_4922 : connect remapVecData[18], Queue2_UInt8_9.io.deq.bits connect remapVecValids[18], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_4923 = eq(UInt<4>(0ha), remapindex_18) when _T_4923 : connect remapVecData[18], Queue2_UInt8_10.io.deq.bits connect remapVecValids[18], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_4924 = eq(UInt<4>(0hb), remapindex_18) when _T_4924 : connect remapVecData[18], Queue2_UInt8_11.io.deq.bits connect remapVecValids[18], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_4925 = eq(UInt<4>(0hc), remapindex_18) when _T_4925 : connect remapVecData[18], Queue2_UInt8_12.io.deq.bits connect remapVecValids[18], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_4926 = eq(UInt<4>(0hd), remapindex_18) when _T_4926 : connect remapVecData[18], Queue2_UInt8_13.io.deq.bits connect remapVecValids[18], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_4927 = eq(UInt<4>(0he), remapindex_18) when _T_4927 : connect remapVecData[18], Queue2_UInt8_14.io.deq.bits connect remapVecValids[18], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_4928 = eq(UInt<4>(0hf), remapindex_18) when _T_4928 : connect remapVecData[18], Queue2_UInt8_15.io.deq.bits connect remapVecValids[18], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_4929 = eq(UInt<5>(0h10), remapindex_18) when _T_4929 : connect remapVecData[18], Queue2_UInt8_16.io.deq.bits connect remapVecValids[18], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_4930 = eq(UInt<5>(0h11), remapindex_18) when _T_4930 : connect remapVecData[18], Queue2_UInt8_17.io.deq.bits connect remapVecValids[18], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_4931 = eq(UInt<5>(0h12), remapindex_18) when _T_4931 : connect remapVecData[18], Queue2_UInt8_18.io.deq.bits connect remapVecValids[18], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_4932 = eq(UInt<5>(0h13), remapindex_18) when _T_4932 : connect remapVecData[18], Queue2_UInt8_19.io.deq.bits connect remapVecValids[18], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_4933 = eq(UInt<5>(0h14), remapindex_18) when _T_4933 : connect remapVecData[18], Queue2_UInt8_20.io.deq.bits connect remapVecValids[18], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_4934 = eq(UInt<5>(0h15), remapindex_18) when _T_4934 : connect remapVecData[18], Queue2_UInt8_21.io.deq.bits connect remapVecValids[18], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_4935 = eq(UInt<5>(0h16), remapindex_18) when _T_4935 : connect remapVecData[18], Queue2_UInt8_22.io.deq.bits connect remapVecValids[18], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_4936 = eq(UInt<5>(0h17), remapindex_18) when _T_4936 : connect remapVecData[18], Queue2_UInt8_23.io.deq.bits connect remapVecValids[18], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_4937 = eq(UInt<5>(0h18), remapindex_18) when _T_4937 : connect remapVecData[18], Queue2_UInt8_24.io.deq.bits connect remapVecValids[18], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_4938 = eq(UInt<5>(0h19), remapindex_18) when _T_4938 : connect remapVecData[18], Queue2_UInt8_25.io.deq.bits connect remapVecValids[18], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_4939 = eq(UInt<5>(0h1a), remapindex_18) when _T_4939 : connect remapVecData[18], Queue2_UInt8_26.io.deq.bits connect remapVecValids[18], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_4940 = eq(UInt<5>(0h1b), remapindex_18) when _T_4940 : connect remapVecData[18], Queue2_UInt8_27.io.deq.bits connect remapVecValids[18], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_4941 = eq(UInt<5>(0h1c), remapindex_18) when _T_4941 : connect remapVecData[18], Queue2_UInt8_28.io.deq.bits connect remapVecValids[18], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_4942 = eq(UInt<5>(0h1d), remapindex_18) when _T_4942 : connect remapVecData[18], Queue2_UInt8_29.io.deq.bits connect remapVecValids[18], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_4943 = eq(UInt<5>(0h1e), remapindex_18) when _T_4943 : connect remapVecData[18], Queue2_UInt8_30.io.deq.bits connect remapVecValids[18], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_4944 = eq(UInt<5>(0h1f), remapindex_18) when _T_4944 : connect remapVecData[18], Queue2_UInt8_31.io.deq.bits connect remapVecValids[18], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_4945 = eq(UInt<1>(0h0), remapindex_19) when _T_4945 : connect remapVecData[19], Queue2_UInt8.io.deq.bits connect remapVecValids[19], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[19] node _T_4946 = eq(UInt<1>(0h1), remapindex_19) when _T_4946 : connect remapVecData[19], Queue2_UInt8_1.io.deq.bits connect remapVecValids[19], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_4947 = eq(UInt<2>(0h2), remapindex_19) when _T_4947 : connect remapVecData[19], Queue2_UInt8_2.io.deq.bits connect remapVecValids[19], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_4948 = eq(UInt<2>(0h3), remapindex_19) when _T_4948 : connect remapVecData[19], Queue2_UInt8_3.io.deq.bits connect remapVecValids[19], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_4949 = eq(UInt<3>(0h4), remapindex_19) when _T_4949 : connect remapVecData[19], Queue2_UInt8_4.io.deq.bits connect remapVecValids[19], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_4950 = eq(UInt<3>(0h5), remapindex_19) when _T_4950 : connect remapVecData[19], Queue2_UInt8_5.io.deq.bits connect remapVecValids[19], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_4951 = eq(UInt<3>(0h6), remapindex_19) when _T_4951 : connect remapVecData[19], Queue2_UInt8_6.io.deq.bits connect remapVecValids[19], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_4952 = eq(UInt<3>(0h7), remapindex_19) when _T_4952 : connect remapVecData[19], Queue2_UInt8_7.io.deq.bits connect remapVecValids[19], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_4953 = eq(UInt<4>(0h8), remapindex_19) when _T_4953 : connect remapVecData[19], Queue2_UInt8_8.io.deq.bits connect remapVecValids[19], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_4954 = eq(UInt<4>(0h9), remapindex_19) when _T_4954 : connect remapVecData[19], Queue2_UInt8_9.io.deq.bits connect remapVecValids[19], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_4955 = eq(UInt<4>(0ha), remapindex_19) when _T_4955 : connect remapVecData[19], Queue2_UInt8_10.io.deq.bits connect remapVecValids[19], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_4956 = eq(UInt<4>(0hb), remapindex_19) when _T_4956 : connect remapVecData[19], Queue2_UInt8_11.io.deq.bits connect remapVecValids[19], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_4957 = eq(UInt<4>(0hc), remapindex_19) when _T_4957 : connect remapVecData[19], Queue2_UInt8_12.io.deq.bits connect remapVecValids[19], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_4958 = eq(UInt<4>(0hd), remapindex_19) when _T_4958 : connect remapVecData[19], Queue2_UInt8_13.io.deq.bits connect remapVecValids[19], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_4959 = eq(UInt<4>(0he), remapindex_19) when _T_4959 : connect remapVecData[19], Queue2_UInt8_14.io.deq.bits connect remapVecValids[19], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_4960 = eq(UInt<4>(0hf), remapindex_19) when _T_4960 : connect remapVecData[19], Queue2_UInt8_15.io.deq.bits connect remapVecValids[19], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_4961 = eq(UInt<5>(0h10), remapindex_19) when _T_4961 : connect remapVecData[19], Queue2_UInt8_16.io.deq.bits connect remapVecValids[19], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_4962 = eq(UInt<5>(0h11), remapindex_19) when _T_4962 : connect remapVecData[19], Queue2_UInt8_17.io.deq.bits connect remapVecValids[19], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_4963 = eq(UInt<5>(0h12), remapindex_19) when _T_4963 : connect remapVecData[19], Queue2_UInt8_18.io.deq.bits connect remapVecValids[19], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_4964 = eq(UInt<5>(0h13), remapindex_19) when _T_4964 : connect remapVecData[19], Queue2_UInt8_19.io.deq.bits connect remapVecValids[19], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_4965 = eq(UInt<5>(0h14), remapindex_19) when _T_4965 : connect remapVecData[19], Queue2_UInt8_20.io.deq.bits connect remapVecValids[19], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_4966 = eq(UInt<5>(0h15), remapindex_19) when _T_4966 : connect remapVecData[19], Queue2_UInt8_21.io.deq.bits connect remapVecValids[19], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_4967 = eq(UInt<5>(0h16), remapindex_19) when _T_4967 : connect remapVecData[19], Queue2_UInt8_22.io.deq.bits connect remapVecValids[19], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_4968 = eq(UInt<5>(0h17), remapindex_19) when _T_4968 : connect remapVecData[19], Queue2_UInt8_23.io.deq.bits connect remapVecValids[19], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_4969 = eq(UInt<5>(0h18), remapindex_19) when _T_4969 : connect remapVecData[19], Queue2_UInt8_24.io.deq.bits connect remapVecValids[19], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_4970 = eq(UInt<5>(0h19), remapindex_19) when _T_4970 : connect remapVecData[19], Queue2_UInt8_25.io.deq.bits connect remapVecValids[19], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_4971 = eq(UInt<5>(0h1a), remapindex_19) when _T_4971 : connect remapVecData[19], Queue2_UInt8_26.io.deq.bits connect remapVecValids[19], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_4972 = eq(UInt<5>(0h1b), remapindex_19) when _T_4972 : connect remapVecData[19], Queue2_UInt8_27.io.deq.bits connect remapVecValids[19], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_4973 = eq(UInt<5>(0h1c), remapindex_19) when _T_4973 : connect remapVecData[19], Queue2_UInt8_28.io.deq.bits connect remapVecValids[19], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_4974 = eq(UInt<5>(0h1d), remapindex_19) when _T_4974 : connect remapVecData[19], Queue2_UInt8_29.io.deq.bits connect remapVecValids[19], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_4975 = eq(UInt<5>(0h1e), remapindex_19) when _T_4975 : connect remapVecData[19], Queue2_UInt8_30.io.deq.bits connect remapVecValids[19], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_4976 = eq(UInt<5>(0h1f), remapindex_19) when _T_4976 : connect remapVecData[19], Queue2_UInt8_31.io.deq.bits connect remapVecValids[19], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_4977 = eq(UInt<1>(0h0), remapindex_20) when _T_4977 : connect remapVecData[20], Queue2_UInt8.io.deq.bits connect remapVecValids[20], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[20] node _T_4978 = eq(UInt<1>(0h1), remapindex_20) when _T_4978 : connect remapVecData[20], Queue2_UInt8_1.io.deq.bits connect remapVecValids[20], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_4979 = eq(UInt<2>(0h2), remapindex_20) when _T_4979 : connect remapVecData[20], Queue2_UInt8_2.io.deq.bits connect remapVecValids[20], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_4980 = eq(UInt<2>(0h3), remapindex_20) when _T_4980 : connect remapVecData[20], Queue2_UInt8_3.io.deq.bits connect remapVecValids[20], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_4981 = eq(UInt<3>(0h4), remapindex_20) when _T_4981 : connect remapVecData[20], Queue2_UInt8_4.io.deq.bits connect remapVecValids[20], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_4982 = eq(UInt<3>(0h5), remapindex_20) when _T_4982 : connect remapVecData[20], Queue2_UInt8_5.io.deq.bits connect remapVecValids[20], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_4983 = eq(UInt<3>(0h6), remapindex_20) when _T_4983 : connect remapVecData[20], Queue2_UInt8_6.io.deq.bits connect remapVecValids[20], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_4984 = eq(UInt<3>(0h7), remapindex_20) when _T_4984 : connect remapVecData[20], Queue2_UInt8_7.io.deq.bits connect remapVecValids[20], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_4985 = eq(UInt<4>(0h8), remapindex_20) when _T_4985 : connect remapVecData[20], Queue2_UInt8_8.io.deq.bits connect remapVecValids[20], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_4986 = eq(UInt<4>(0h9), remapindex_20) when _T_4986 : connect remapVecData[20], Queue2_UInt8_9.io.deq.bits connect remapVecValids[20], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_4987 = eq(UInt<4>(0ha), remapindex_20) when _T_4987 : connect remapVecData[20], Queue2_UInt8_10.io.deq.bits connect remapVecValids[20], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_4988 = eq(UInt<4>(0hb), remapindex_20) when _T_4988 : connect remapVecData[20], Queue2_UInt8_11.io.deq.bits connect remapVecValids[20], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_4989 = eq(UInt<4>(0hc), remapindex_20) when _T_4989 : connect remapVecData[20], Queue2_UInt8_12.io.deq.bits connect remapVecValids[20], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_4990 = eq(UInt<4>(0hd), remapindex_20) when _T_4990 : connect remapVecData[20], Queue2_UInt8_13.io.deq.bits connect remapVecValids[20], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_4991 = eq(UInt<4>(0he), remapindex_20) when _T_4991 : connect remapVecData[20], Queue2_UInt8_14.io.deq.bits connect remapVecValids[20], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_4992 = eq(UInt<4>(0hf), remapindex_20) when _T_4992 : connect remapVecData[20], Queue2_UInt8_15.io.deq.bits connect remapVecValids[20], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_4993 = eq(UInt<5>(0h10), remapindex_20) when _T_4993 : connect remapVecData[20], Queue2_UInt8_16.io.deq.bits connect remapVecValids[20], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_4994 = eq(UInt<5>(0h11), remapindex_20) when _T_4994 : connect remapVecData[20], Queue2_UInt8_17.io.deq.bits connect remapVecValids[20], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_4995 = eq(UInt<5>(0h12), remapindex_20) when _T_4995 : connect remapVecData[20], Queue2_UInt8_18.io.deq.bits connect remapVecValids[20], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_4996 = eq(UInt<5>(0h13), remapindex_20) when _T_4996 : connect remapVecData[20], Queue2_UInt8_19.io.deq.bits connect remapVecValids[20], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_4997 = eq(UInt<5>(0h14), remapindex_20) when _T_4997 : connect remapVecData[20], Queue2_UInt8_20.io.deq.bits connect remapVecValids[20], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_4998 = eq(UInt<5>(0h15), remapindex_20) when _T_4998 : connect remapVecData[20], Queue2_UInt8_21.io.deq.bits connect remapVecValids[20], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_4999 = eq(UInt<5>(0h16), remapindex_20) when _T_4999 : connect remapVecData[20], Queue2_UInt8_22.io.deq.bits connect remapVecValids[20], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_5000 = eq(UInt<5>(0h17), remapindex_20) when _T_5000 : connect remapVecData[20], Queue2_UInt8_23.io.deq.bits connect remapVecValids[20], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_5001 = eq(UInt<5>(0h18), remapindex_20) when _T_5001 : connect remapVecData[20], Queue2_UInt8_24.io.deq.bits connect remapVecValids[20], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_5002 = eq(UInt<5>(0h19), remapindex_20) when _T_5002 : connect remapVecData[20], Queue2_UInt8_25.io.deq.bits connect remapVecValids[20], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_5003 = eq(UInt<5>(0h1a), remapindex_20) when _T_5003 : connect remapVecData[20], Queue2_UInt8_26.io.deq.bits connect remapVecValids[20], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_5004 = eq(UInt<5>(0h1b), remapindex_20) when _T_5004 : connect remapVecData[20], Queue2_UInt8_27.io.deq.bits connect remapVecValids[20], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_5005 = eq(UInt<5>(0h1c), remapindex_20) when _T_5005 : connect remapVecData[20], Queue2_UInt8_28.io.deq.bits connect remapVecValids[20], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_5006 = eq(UInt<5>(0h1d), remapindex_20) when _T_5006 : connect remapVecData[20], Queue2_UInt8_29.io.deq.bits connect remapVecValids[20], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_5007 = eq(UInt<5>(0h1e), remapindex_20) when _T_5007 : connect remapVecData[20], Queue2_UInt8_30.io.deq.bits connect remapVecValids[20], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_5008 = eq(UInt<5>(0h1f), remapindex_20) when _T_5008 : connect remapVecData[20], Queue2_UInt8_31.io.deq.bits connect remapVecValids[20], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_5009 = eq(UInt<1>(0h0), remapindex_21) when _T_5009 : connect remapVecData[21], Queue2_UInt8.io.deq.bits connect remapVecValids[21], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[21] node _T_5010 = eq(UInt<1>(0h1), remapindex_21) when _T_5010 : connect remapVecData[21], Queue2_UInt8_1.io.deq.bits connect remapVecValids[21], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_5011 = eq(UInt<2>(0h2), remapindex_21) when _T_5011 : connect remapVecData[21], Queue2_UInt8_2.io.deq.bits connect remapVecValids[21], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_5012 = eq(UInt<2>(0h3), remapindex_21) when _T_5012 : connect remapVecData[21], Queue2_UInt8_3.io.deq.bits connect remapVecValids[21], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_5013 = eq(UInt<3>(0h4), remapindex_21) when _T_5013 : connect remapVecData[21], Queue2_UInt8_4.io.deq.bits connect remapVecValids[21], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_5014 = eq(UInt<3>(0h5), remapindex_21) when _T_5014 : connect remapVecData[21], Queue2_UInt8_5.io.deq.bits connect remapVecValids[21], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_5015 = eq(UInt<3>(0h6), remapindex_21) when _T_5015 : connect remapVecData[21], Queue2_UInt8_6.io.deq.bits connect remapVecValids[21], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_5016 = eq(UInt<3>(0h7), remapindex_21) when _T_5016 : connect remapVecData[21], Queue2_UInt8_7.io.deq.bits connect remapVecValids[21], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_5017 = eq(UInt<4>(0h8), remapindex_21) when _T_5017 : connect remapVecData[21], Queue2_UInt8_8.io.deq.bits connect remapVecValids[21], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_5018 = eq(UInt<4>(0h9), remapindex_21) when _T_5018 : connect remapVecData[21], Queue2_UInt8_9.io.deq.bits connect remapVecValids[21], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_5019 = eq(UInt<4>(0ha), remapindex_21) when _T_5019 : connect remapVecData[21], Queue2_UInt8_10.io.deq.bits connect remapVecValids[21], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_5020 = eq(UInt<4>(0hb), remapindex_21) when _T_5020 : connect remapVecData[21], Queue2_UInt8_11.io.deq.bits connect remapVecValids[21], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_5021 = eq(UInt<4>(0hc), remapindex_21) when _T_5021 : connect remapVecData[21], Queue2_UInt8_12.io.deq.bits connect remapVecValids[21], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_5022 = eq(UInt<4>(0hd), remapindex_21) when _T_5022 : connect remapVecData[21], Queue2_UInt8_13.io.deq.bits connect remapVecValids[21], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_5023 = eq(UInt<4>(0he), remapindex_21) when _T_5023 : connect remapVecData[21], Queue2_UInt8_14.io.deq.bits connect remapVecValids[21], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_5024 = eq(UInt<4>(0hf), remapindex_21) when _T_5024 : connect remapVecData[21], Queue2_UInt8_15.io.deq.bits connect remapVecValids[21], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_5025 = eq(UInt<5>(0h10), remapindex_21) when _T_5025 : connect remapVecData[21], Queue2_UInt8_16.io.deq.bits connect remapVecValids[21], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_5026 = eq(UInt<5>(0h11), remapindex_21) when _T_5026 : connect remapVecData[21], Queue2_UInt8_17.io.deq.bits connect remapVecValids[21], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_5027 = eq(UInt<5>(0h12), remapindex_21) when _T_5027 : connect remapVecData[21], Queue2_UInt8_18.io.deq.bits connect remapVecValids[21], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_5028 = eq(UInt<5>(0h13), remapindex_21) when _T_5028 : connect remapVecData[21], Queue2_UInt8_19.io.deq.bits connect remapVecValids[21], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_5029 = eq(UInt<5>(0h14), remapindex_21) when _T_5029 : connect remapVecData[21], Queue2_UInt8_20.io.deq.bits connect remapVecValids[21], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_5030 = eq(UInt<5>(0h15), remapindex_21) when _T_5030 : connect remapVecData[21], Queue2_UInt8_21.io.deq.bits connect remapVecValids[21], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_5031 = eq(UInt<5>(0h16), remapindex_21) when _T_5031 : connect remapVecData[21], Queue2_UInt8_22.io.deq.bits connect remapVecValids[21], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_5032 = eq(UInt<5>(0h17), remapindex_21) when _T_5032 : connect remapVecData[21], Queue2_UInt8_23.io.deq.bits connect remapVecValids[21], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_5033 = eq(UInt<5>(0h18), remapindex_21) when _T_5033 : connect remapVecData[21], Queue2_UInt8_24.io.deq.bits connect remapVecValids[21], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_5034 = eq(UInt<5>(0h19), remapindex_21) when _T_5034 : connect remapVecData[21], Queue2_UInt8_25.io.deq.bits connect remapVecValids[21], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_5035 = eq(UInt<5>(0h1a), remapindex_21) when _T_5035 : connect remapVecData[21], Queue2_UInt8_26.io.deq.bits connect remapVecValids[21], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_5036 = eq(UInt<5>(0h1b), remapindex_21) when _T_5036 : connect remapVecData[21], Queue2_UInt8_27.io.deq.bits connect remapVecValids[21], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_5037 = eq(UInt<5>(0h1c), remapindex_21) when _T_5037 : connect remapVecData[21], Queue2_UInt8_28.io.deq.bits connect remapVecValids[21], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_5038 = eq(UInt<5>(0h1d), remapindex_21) when _T_5038 : connect remapVecData[21], Queue2_UInt8_29.io.deq.bits connect remapVecValids[21], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_5039 = eq(UInt<5>(0h1e), remapindex_21) when _T_5039 : connect remapVecData[21], Queue2_UInt8_30.io.deq.bits connect remapVecValids[21], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_5040 = eq(UInt<5>(0h1f), remapindex_21) when _T_5040 : connect remapVecData[21], Queue2_UInt8_31.io.deq.bits connect remapVecValids[21], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_5041 = eq(UInt<1>(0h0), remapindex_22) when _T_5041 : connect remapVecData[22], Queue2_UInt8.io.deq.bits connect remapVecValids[22], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[22] node _T_5042 = eq(UInt<1>(0h1), remapindex_22) when _T_5042 : connect remapVecData[22], Queue2_UInt8_1.io.deq.bits connect remapVecValids[22], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_5043 = eq(UInt<2>(0h2), remapindex_22) when _T_5043 : connect remapVecData[22], Queue2_UInt8_2.io.deq.bits connect remapVecValids[22], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_5044 = eq(UInt<2>(0h3), remapindex_22) when _T_5044 : connect remapVecData[22], Queue2_UInt8_3.io.deq.bits connect remapVecValids[22], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_5045 = eq(UInt<3>(0h4), remapindex_22) when _T_5045 : connect remapVecData[22], Queue2_UInt8_4.io.deq.bits connect remapVecValids[22], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_5046 = eq(UInt<3>(0h5), remapindex_22) when _T_5046 : connect remapVecData[22], Queue2_UInt8_5.io.deq.bits connect remapVecValids[22], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_5047 = eq(UInt<3>(0h6), remapindex_22) when _T_5047 : connect remapVecData[22], Queue2_UInt8_6.io.deq.bits connect remapVecValids[22], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_5048 = eq(UInt<3>(0h7), remapindex_22) when _T_5048 : connect remapVecData[22], Queue2_UInt8_7.io.deq.bits connect remapVecValids[22], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_5049 = eq(UInt<4>(0h8), remapindex_22) when _T_5049 : connect remapVecData[22], Queue2_UInt8_8.io.deq.bits connect remapVecValids[22], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_5050 = eq(UInt<4>(0h9), remapindex_22) when _T_5050 : connect remapVecData[22], Queue2_UInt8_9.io.deq.bits connect remapVecValids[22], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_5051 = eq(UInt<4>(0ha), remapindex_22) when _T_5051 : connect remapVecData[22], Queue2_UInt8_10.io.deq.bits connect remapVecValids[22], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_5052 = eq(UInt<4>(0hb), remapindex_22) when _T_5052 : connect remapVecData[22], Queue2_UInt8_11.io.deq.bits connect remapVecValids[22], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_5053 = eq(UInt<4>(0hc), remapindex_22) when _T_5053 : connect remapVecData[22], Queue2_UInt8_12.io.deq.bits connect remapVecValids[22], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_5054 = eq(UInt<4>(0hd), remapindex_22) when _T_5054 : connect remapVecData[22], Queue2_UInt8_13.io.deq.bits connect remapVecValids[22], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_5055 = eq(UInt<4>(0he), remapindex_22) when _T_5055 : connect remapVecData[22], Queue2_UInt8_14.io.deq.bits connect remapVecValids[22], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_5056 = eq(UInt<4>(0hf), remapindex_22) when _T_5056 : connect remapVecData[22], Queue2_UInt8_15.io.deq.bits connect remapVecValids[22], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_5057 = eq(UInt<5>(0h10), remapindex_22) when _T_5057 : connect remapVecData[22], Queue2_UInt8_16.io.deq.bits connect remapVecValids[22], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_5058 = eq(UInt<5>(0h11), remapindex_22) when _T_5058 : connect remapVecData[22], Queue2_UInt8_17.io.deq.bits connect remapVecValids[22], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_5059 = eq(UInt<5>(0h12), remapindex_22) when _T_5059 : connect remapVecData[22], Queue2_UInt8_18.io.deq.bits connect remapVecValids[22], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_5060 = eq(UInt<5>(0h13), remapindex_22) when _T_5060 : connect remapVecData[22], Queue2_UInt8_19.io.deq.bits connect remapVecValids[22], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_5061 = eq(UInt<5>(0h14), remapindex_22) when _T_5061 : connect remapVecData[22], Queue2_UInt8_20.io.deq.bits connect remapVecValids[22], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_5062 = eq(UInt<5>(0h15), remapindex_22) when _T_5062 : connect remapVecData[22], Queue2_UInt8_21.io.deq.bits connect remapVecValids[22], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_5063 = eq(UInt<5>(0h16), remapindex_22) when _T_5063 : connect remapVecData[22], Queue2_UInt8_22.io.deq.bits connect remapVecValids[22], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_5064 = eq(UInt<5>(0h17), remapindex_22) when _T_5064 : connect remapVecData[22], Queue2_UInt8_23.io.deq.bits connect remapVecValids[22], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_5065 = eq(UInt<5>(0h18), remapindex_22) when _T_5065 : connect remapVecData[22], Queue2_UInt8_24.io.deq.bits connect remapVecValids[22], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_5066 = eq(UInt<5>(0h19), remapindex_22) when _T_5066 : connect remapVecData[22], Queue2_UInt8_25.io.deq.bits connect remapVecValids[22], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_5067 = eq(UInt<5>(0h1a), remapindex_22) when _T_5067 : connect remapVecData[22], Queue2_UInt8_26.io.deq.bits connect remapVecValids[22], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_5068 = eq(UInt<5>(0h1b), remapindex_22) when _T_5068 : connect remapVecData[22], Queue2_UInt8_27.io.deq.bits connect remapVecValids[22], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_5069 = eq(UInt<5>(0h1c), remapindex_22) when _T_5069 : connect remapVecData[22], Queue2_UInt8_28.io.deq.bits connect remapVecValids[22], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_5070 = eq(UInt<5>(0h1d), remapindex_22) when _T_5070 : connect remapVecData[22], Queue2_UInt8_29.io.deq.bits connect remapVecValids[22], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_5071 = eq(UInt<5>(0h1e), remapindex_22) when _T_5071 : connect remapVecData[22], Queue2_UInt8_30.io.deq.bits connect remapVecValids[22], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_5072 = eq(UInt<5>(0h1f), remapindex_22) when _T_5072 : connect remapVecData[22], Queue2_UInt8_31.io.deq.bits connect remapVecValids[22], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_5073 = eq(UInt<1>(0h0), remapindex_23) when _T_5073 : connect remapVecData[23], Queue2_UInt8.io.deq.bits connect remapVecValids[23], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[23] node _T_5074 = eq(UInt<1>(0h1), remapindex_23) when _T_5074 : connect remapVecData[23], Queue2_UInt8_1.io.deq.bits connect remapVecValids[23], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_5075 = eq(UInt<2>(0h2), remapindex_23) when _T_5075 : connect remapVecData[23], Queue2_UInt8_2.io.deq.bits connect remapVecValids[23], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_5076 = eq(UInt<2>(0h3), remapindex_23) when _T_5076 : connect remapVecData[23], Queue2_UInt8_3.io.deq.bits connect remapVecValids[23], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_5077 = eq(UInt<3>(0h4), remapindex_23) when _T_5077 : connect remapVecData[23], Queue2_UInt8_4.io.deq.bits connect remapVecValids[23], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_5078 = eq(UInt<3>(0h5), remapindex_23) when _T_5078 : connect remapVecData[23], Queue2_UInt8_5.io.deq.bits connect remapVecValids[23], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_5079 = eq(UInt<3>(0h6), remapindex_23) when _T_5079 : connect remapVecData[23], Queue2_UInt8_6.io.deq.bits connect remapVecValids[23], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_5080 = eq(UInt<3>(0h7), remapindex_23) when _T_5080 : connect remapVecData[23], Queue2_UInt8_7.io.deq.bits connect remapVecValids[23], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_5081 = eq(UInt<4>(0h8), remapindex_23) when _T_5081 : connect remapVecData[23], Queue2_UInt8_8.io.deq.bits connect remapVecValids[23], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_5082 = eq(UInt<4>(0h9), remapindex_23) when _T_5082 : connect remapVecData[23], Queue2_UInt8_9.io.deq.bits connect remapVecValids[23], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_5083 = eq(UInt<4>(0ha), remapindex_23) when _T_5083 : connect remapVecData[23], Queue2_UInt8_10.io.deq.bits connect remapVecValids[23], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_5084 = eq(UInt<4>(0hb), remapindex_23) when _T_5084 : connect remapVecData[23], Queue2_UInt8_11.io.deq.bits connect remapVecValids[23], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_5085 = eq(UInt<4>(0hc), remapindex_23) when _T_5085 : connect remapVecData[23], Queue2_UInt8_12.io.deq.bits connect remapVecValids[23], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_5086 = eq(UInt<4>(0hd), remapindex_23) when _T_5086 : connect remapVecData[23], Queue2_UInt8_13.io.deq.bits connect remapVecValids[23], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_5087 = eq(UInt<4>(0he), remapindex_23) when _T_5087 : connect remapVecData[23], Queue2_UInt8_14.io.deq.bits connect remapVecValids[23], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_5088 = eq(UInt<4>(0hf), remapindex_23) when _T_5088 : connect remapVecData[23], Queue2_UInt8_15.io.deq.bits connect remapVecValids[23], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_5089 = eq(UInt<5>(0h10), remapindex_23) when _T_5089 : connect remapVecData[23], Queue2_UInt8_16.io.deq.bits connect remapVecValids[23], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_5090 = eq(UInt<5>(0h11), remapindex_23) when _T_5090 : connect remapVecData[23], Queue2_UInt8_17.io.deq.bits connect remapVecValids[23], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_5091 = eq(UInt<5>(0h12), remapindex_23) when _T_5091 : connect remapVecData[23], Queue2_UInt8_18.io.deq.bits connect remapVecValids[23], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_5092 = eq(UInt<5>(0h13), remapindex_23) when _T_5092 : connect remapVecData[23], Queue2_UInt8_19.io.deq.bits connect remapVecValids[23], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_5093 = eq(UInt<5>(0h14), remapindex_23) when _T_5093 : connect remapVecData[23], Queue2_UInt8_20.io.deq.bits connect remapVecValids[23], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_5094 = eq(UInt<5>(0h15), remapindex_23) when _T_5094 : connect remapVecData[23], Queue2_UInt8_21.io.deq.bits connect remapVecValids[23], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_5095 = eq(UInt<5>(0h16), remapindex_23) when _T_5095 : connect remapVecData[23], Queue2_UInt8_22.io.deq.bits connect remapVecValids[23], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_5096 = eq(UInt<5>(0h17), remapindex_23) when _T_5096 : connect remapVecData[23], Queue2_UInt8_23.io.deq.bits connect remapVecValids[23], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_5097 = eq(UInt<5>(0h18), remapindex_23) when _T_5097 : connect remapVecData[23], Queue2_UInt8_24.io.deq.bits connect remapVecValids[23], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_5098 = eq(UInt<5>(0h19), remapindex_23) when _T_5098 : connect remapVecData[23], Queue2_UInt8_25.io.deq.bits connect remapVecValids[23], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_5099 = eq(UInt<5>(0h1a), remapindex_23) when _T_5099 : connect remapVecData[23], Queue2_UInt8_26.io.deq.bits connect remapVecValids[23], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_5100 = eq(UInt<5>(0h1b), remapindex_23) when _T_5100 : connect remapVecData[23], Queue2_UInt8_27.io.deq.bits connect remapVecValids[23], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_5101 = eq(UInt<5>(0h1c), remapindex_23) when _T_5101 : connect remapVecData[23], Queue2_UInt8_28.io.deq.bits connect remapVecValids[23], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_5102 = eq(UInt<5>(0h1d), remapindex_23) when _T_5102 : connect remapVecData[23], Queue2_UInt8_29.io.deq.bits connect remapVecValids[23], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_5103 = eq(UInt<5>(0h1e), remapindex_23) when _T_5103 : connect remapVecData[23], Queue2_UInt8_30.io.deq.bits connect remapVecValids[23], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_5104 = eq(UInt<5>(0h1f), remapindex_23) when _T_5104 : connect remapVecData[23], Queue2_UInt8_31.io.deq.bits connect remapVecValids[23], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_5105 = eq(UInt<1>(0h0), remapindex_24) when _T_5105 : connect remapVecData[24], Queue2_UInt8.io.deq.bits connect remapVecValids[24], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[24] node _T_5106 = eq(UInt<1>(0h1), remapindex_24) when _T_5106 : connect remapVecData[24], Queue2_UInt8_1.io.deq.bits connect remapVecValids[24], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_5107 = eq(UInt<2>(0h2), remapindex_24) when _T_5107 : connect remapVecData[24], Queue2_UInt8_2.io.deq.bits connect remapVecValids[24], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_5108 = eq(UInt<2>(0h3), remapindex_24) when _T_5108 : connect remapVecData[24], Queue2_UInt8_3.io.deq.bits connect remapVecValids[24], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_5109 = eq(UInt<3>(0h4), remapindex_24) when _T_5109 : connect remapVecData[24], Queue2_UInt8_4.io.deq.bits connect remapVecValids[24], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_5110 = eq(UInt<3>(0h5), remapindex_24) when _T_5110 : connect remapVecData[24], Queue2_UInt8_5.io.deq.bits connect remapVecValids[24], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_5111 = eq(UInt<3>(0h6), remapindex_24) when _T_5111 : connect remapVecData[24], Queue2_UInt8_6.io.deq.bits connect remapVecValids[24], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_5112 = eq(UInt<3>(0h7), remapindex_24) when _T_5112 : connect remapVecData[24], Queue2_UInt8_7.io.deq.bits connect remapVecValids[24], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_5113 = eq(UInt<4>(0h8), remapindex_24) when _T_5113 : connect remapVecData[24], Queue2_UInt8_8.io.deq.bits connect remapVecValids[24], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_5114 = eq(UInt<4>(0h9), remapindex_24) when _T_5114 : connect remapVecData[24], Queue2_UInt8_9.io.deq.bits connect remapVecValids[24], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_5115 = eq(UInt<4>(0ha), remapindex_24) when _T_5115 : connect remapVecData[24], Queue2_UInt8_10.io.deq.bits connect remapVecValids[24], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_5116 = eq(UInt<4>(0hb), remapindex_24) when _T_5116 : connect remapVecData[24], Queue2_UInt8_11.io.deq.bits connect remapVecValids[24], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_5117 = eq(UInt<4>(0hc), remapindex_24) when _T_5117 : connect remapVecData[24], Queue2_UInt8_12.io.deq.bits connect remapVecValids[24], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_5118 = eq(UInt<4>(0hd), remapindex_24) when _T_5118 : connect remapVecData[24], Queue2_UInt8_13.io.deq.bits connect remapVecValids[24], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_5119 = eq(UInt<4>(0he), remapindex_24) when _T_5119 : connect remapVecData[24], Queue2_UInt8_14.io.deq.bits connect remapVecValids[24], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_5120 = eq(UInt<4>(0hf), remapindex_24) when _T_5120 : connect remapVecData[24], Queue2_UInt8_15.io.deq.bits connect remapVecValids[24], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_5121 = eq(UInt<5>(0h10), remapindex_24) when _T_5121 : connect remapVecData[24], Queue2_UInt8_16.io.deq.bits connect remapVecValids[24], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_5122 = eq(UInt<5>(0h11), remapindex_24) when _T_5122 : connect remapVecData[24], Queue2_UInt8_17.io.deq.bits connect remapVecValids[24], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_5123 = eq(UInt<5>(0h12), remapindex_24) when _T_5123 : connect remapVecData[24], Queue2_UInt8_18.io.deq.bits connect remapVecValids[24], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_5124 = eq(UInt<5>(0h13), remapindex_24) when _T_5124 : connect remapVecData[24], Queue2_UInt8_19.io.deq.bits connect remapVecValids[24], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_5125 = eq(UInt<5>(0h14), remapindex_24) when _T_5125 : connect remapVecData[24], Queue2_UInt8_20.io.deq.bits connect remapVecValids[24], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_5126 = eq(UInt<5>(0h15), remapindex_24) when _T_5126 : connect remapVecData[24], Queue2_UInt8_21.io.deq.bits connect remapVecValids[24], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_5127 = eq(UInt<5>(0h16), remapindex_24) when _T_5127 : connect remapVecData[24], Queue2_UInt8_22.io.deq.bits connect remapVecValids[24], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_5128 = eq(UInt<5>(0h17), remapindex_24) when _T_5128 : connect remapVecData[24], Queue2_UInt8_23.io.deq.bits connect remapVecValids[24], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_5129 = eq(UInt<5>(0h18), remapindex_24) when _T_5129 : connect remapVecData[24], Queue2_UInt8_24.io.deq.bits connect remapVecValids[24], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_5130 = eq(UInt<5>(0h19), remapindex_24) when _T_5130 : connect remapVecData[24], Queue2_UInt8_25.io.deq.bits connect remapVecValids[24], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_5131 = eq(UInt<5>(0h1a), remapindex_24) when _T_5131 : connect remapVecData[24], Queue2_UInt8_26.io.deq.bits connect remapVecValids[24], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_5132 = eq(UInt<5>(0h1b), remapindex_24) when _T_5132 : connect remapVecData[24], Queue2_UInt8_27.io.deq.bits connect remapVecValids[24], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_5133 = eq(UInt<5>(0h1c), remapindex_24) when _T_5133 : connect remapVecData[24], Queue2_UInt8_28.io.deq.bits connect remapVecValids[24], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_5134 = eq(UInt<5>(0h1d), remapindex_24) when _T_5134 : connect remapVecData[24], Queue2_UInt8_29.io.deq.bits connect remapVecValids[24], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_5135 = eq(UInt<5>(0h1e), remapindex_24) when _T_5135 : connect remapVecData[24], Queue2_UInt8_30.io.deq.bits connect remapVecValids[24], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_5136 = eq(UInt<5>(0h1f), remapindex_24) when _T_5136 : connect remapVecData[24], Queue2_UInt8_31.io.deq.bits connect remapVecValids[24], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_5137 = eq(UInt<1>(0h0), remapindex_25) when _T_5137 : connect remapVecData[25], Queue2_UInt8.io.deq.bits connect remapVecValids[25], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[25] node _T_5138 = eq(UInt<1>(0h1), remapindex_25) when _T_5138 : connect remapVecData[25], Queue2_UInt8_1.io.deq.bits connect remapVecValids[25], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_5139 = eq(UInt<2>(0h2), remapindex_25) when _T_5139 : connect remapVecData[25], Queue2_UInt8_2.io.deq.bits connect remapVecValids[25], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_5140 = eq(UInt<2>(0h3), remapindex_25) when _T_5140 : connect remapVecData[25], Queue2_UInt8_3.io.deq.bits connect remapVecValids[25], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_5141 = eq(UInt<3>(0h4), remapindex_25) when _T_5141 : connect remapVecData[25], Queue2_UInt8_4.io.deq.bits connect remapVecValids[25], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_5142 = eq(UInt<3>(0h5), remapindex_25) when _T_5142 : connect remapVecData[25], Queue2_UInt8_5.io.deq.bits connect remapVecValids[25], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_5143 = eq(UInt<3>(0h6), remapindex_25) when _T_5143 : connect remapVecData[25], Queue2_UInt8_6.io.deq.bits connect remapVecValids[25], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_5144 = eq(UInt<3>(0h7), remapindex_25) when _T_5144 : connect remapVecData[25], Queue2_UInt8_7.io.deq.bits connect remapVecValids[25], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_5145 = eq(UInt<4>(0h8), remapindex_25) when _T_5145 : connect remapVecData[25], Queue2_UInt8_8.io.deq.bits connect remapVecValids[25], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_5146 = eq(UInt<4>(0h9), remapindex_25) when _T_5146 : connect remapVecData[25], Queue2_UInt8_9.io.deq.bits connect remapVecValids[25], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_5147 = eq(UInt<4>(0ha), remapindex_25) when _T_5147 : connect remapVecData[25], Queue2_UInt8_10.io.deq.bits connect remapVecValids[25], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_5148 = eq(UInt<4>(0hb), remapindex_25) when _T_5148 : connect remapVecData[25], Queue2_UInt8_11.io.deq.bits connect remapVecValids[25], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_5149 = eq(UInt<4>(0hc), remapindex_25) when _T_5149 : connect remapVecData[25], Queue2_UInt8_12.io.deq.bits connect remapVecValids[25], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_5150 = eq(UInt<4>(0hd), remapindex_25) when _T_5150 : connect remapVecData[25], Queue2_UInt8_13.io.deq.bits connect remapVecValids[25], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_5151 = eq(UInt<4>(0he), remapindex_25) when _T_5151 : connect remapVecData[25], Queue2_UInt8_14.io.deq.bits connect remapVecValids[25], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_5152 = eq(UInt<4>(0hf), remapindex_25) when _T_5152 : connect remapVecData[25], Queue2_UInt8_15.io.deq.bits connect remapVecValids[25], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_5153 = eq(UInt<5>(0h10), remapindex_25) when _T_5153 : connect remapVecData[25], Queue2_UInt8_16.io.deq.bits connect remapVecValids[25], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_5154 = eq(UInt<5>(0h11), remapindex_25) when _T_5154 : connect remapVecData[25], Queue2_UInt8_17.io.deq.bits connect remapVecValids[25], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_5155 = eq(UInt<5>(0h12), remapindex_25) when _T_5155 : connect remapVecData[25], Queue2_UInt8_18.io.deq.bits connect remapVecValids[25], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_5156 = eq(UInt<5>(0h13), remapindex_25) when _T_5156 : connect remapVecData[25], Queue2_UInt8_19.io.deq.bits connect remapVecValids[25], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_5157 = eq(UInt<5>(0h14), remapindex_25) when _T_5157 : connect remapVecData[25], Queue2_UInt8_20.io.deq.bits connect remapVecValids[25], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_5158 = eq(UInt<5>(0h15), remapindex_25) when _T_5158 : connect remapVecData[25], Queue2_UInt8_21.io.deq.bits connect remapVecValids[25], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_5159 = eq(UInt<5>(0h16), remapindex_25) when _T_5159 : connect remapVecData[25], Queue2_UInt8_22.io.deq.bits connect remapVecValids[25], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_5160 = eq(UInt<5>(0h17), remapindex_25) when _T_5160 : connect remapVecData[25], Queue2_UInt8_23.io.deq.bits connect remapVecValids[25], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_5161 = eq(UInt<5>(0h18), remapindex_25) when _T_5161 : connect remapVecData[25], Queue2_UInt8_24.io.deq.bits connect remapVecValids[25], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_5162 = eq(UInt<5>(0h19), remapindex_25) when _T_5162 : connect remapVecData[25], Queue2_UInt8_25.io.deq.bits connect remapVecValids[25], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_5163 = eq(UInt<5>(0h1a), remapindex_25) when _T_5163 : connect remapVecData[25], Queue2_UInt8_26.io.deq.bits connect remapVecValids[25], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_5164 = eq(UInt<5>(0h1b), remapindex_25) when _T_5164 : connect remapVecData[25], Queue2_UInt8_27.io.deq.bits connect remapVecValids[25], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_5165 = eq(UInt<5>(0h1c), remapindex_25) when _T_5165 : connect remapVecData[25], Queue2_UInt8_28.io.deq.bits connect remapVecValids[25], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_5166 = eq(UInt<5>(0h1d), remapindex_25) when _T_5166 : connect remapVecData[25], Queue2_UInt8_29.io.deq.bits connect remapVecValids[25], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_5167 = eq(UInt<5>(0h1e), remapindex_25) when _T_5167 : connect remapVecData[25], Queue2_UInt8_30.io.deq.bits connect remapVecValids[25], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_5168 = eq(UInt<5>(0h1f), remapindex_25) when _T_5168 : connect remapVecData[25], Queue2_UInt8_31.io.deq.bits connect remapVecValids[25], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_5169 = eq(UInt<1>(0h0), remapindex_26) when _T_5169 : connect remapVecData[26], Queue2_UInt8.io.deq.bits connect remapVecValids[26], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[26] node _T_5170 = eq(UInt<1>(0h1), remapindex_26) when _T_5170 : connect remapVecData[26], Queue2_UInt8_1.io.deq.bits connect remapVecValids[26], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_5171 = eq(UInt<2>(0h2), remapindex_26) when _T_5171 : connect remapVecData[26], Queue2_UInt8_2.io.deq.bits connect remapVecValids[26], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_5172 = eq(UInt<2>(0h3), remapindex_26) when _T_5172 : connect remapVecData[26], Queue2_UInt8_3.io.deq.bits connect remapVecValids[26], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_5173 = eq(UInt<3>(0h4), remapindex_26) when _T_5173 : connect remapVecData[26], Queue2_UInt8_4.io.deq.bits connect remapVecValids[26], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_5174 = eq(UInt<3>(0h5), remapindex_26) when _T_5174 : connect remapVecData[26], Queue2_UInt8_5.io.deq.bits connect remapVecValids[26], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_5175 = eq(UInt<3>(0h6), remapindex_26) when _T_5175 : connect remapVecData[26], Queue2_UInt8_6.io.deq.bits connect remapVecValids[26], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_5176 = eq(UInt<3>(0h7), remapindex_26) when _T_5176 : connect remapVecData[26], Queue2_UInt8_7.io.deq.bits connect remapVecValids[26], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_5177 = eq(UInt<4>(0h8), remapindex_26) when _T_5177 : connect remapVecData[26], Queue2_UInt8_8.io.deq.bits connect remapVecValids[26], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_5178 = eq(UInt<4>(0h9), remapindex_26) when _T_5178 : connect remapVecData[26], Queue2_UInt8_9.io.deq.bits connect remapVecValids[26], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_5179 = eq(UInt<4>(0ha), remapindex_26) when _T_5179 : connect remapVecData[26], Queue2_UInt8_10.io.deq.bits connect remapVecValids[26], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_5180 = eq(UInt<4>(0hb), remapindex_26) when _T_5180 : connect remapVecData[26], Queue2_UInt8_11.io.deq.bits connect remapVecValids[26], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_5181 = eq(UInt<4>(0hc), remapindex_26) when _T_5181 : connect remapVecData[26], Queue2_UInt8_12.io.deq.bits connect remapVecValids[26], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_5182 = eq(UInt<4>(0hd), remapindex_26) when _T_5182 : connect remapVecData[26], Queue2_UInt8_13.io.deq.bits connect remapVecValids[26], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_5183 = eq(UInt<4>(0he), remapindex_26) when _T_5183 : connect remapVecData[26], Queue2_UInt8_14.io.deq.bits connect remapVecValids[26], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_5184 = eq(UInt<4>(0hf), remapindex_26) when _T_5184 : connect remapVecData[26], Queue2_UInt8_15.io.deq.bits connect remapVecValids[26], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_5185 = eq(UInt<5>(0h10), remapindex_26) when _T_5185 : connect remapVecData[26], Queue2_UInt8_16.io.deq.bits connect remapVecValids[26], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_5186 = eq(UInt<5>(0h11), remapindex_26) when _T_5186 : connect remapVecData[26], Queue2_UInt8_17.io.deq.bits connect remapVecValids[26], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_5187 = eq(UInt<5>(0h12), remapindex_26) when _T_5187 : connect remapVecData[26], Queue2_UInt8_18.io.deq.bits connect remapVecValids[26], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_5188 = eq(UInt<5>(0h13), remapindex_26) when _T_5188 : connect remapVecData[26], Queue2_UInt8_19.io.deq.bits connect remapVecValids[26], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_5189 = eq(UInt<5>(0h14), remapindex_26) when _T_5189 : connect remapVecData[26], Queue2_UInt8_20.io.deq.bits connect remapVecValids[26], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_5190 = eq(UInt<5>(0h15), remapindex_26) when _T_5190 : connect remapVecData[26], Queue2_UInt8_21.io.deq.bits connect remapVecValids[26], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_5191 = eq(UInt<5>(0h16), remapindex_26) when _T_5191 : connect remapVecData[26], Queue2_UInt8_22.io.deq.bits connect remapVecValids[26], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_5192 = eq(UInt<5>(0h17), remapindex_26) when _T_5192 : connect remapVecData[26], Queue2_UInt8_23.io.deq.bits connect remapVecValids[26], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_5193 = eq(UInt<5>(0h18), remapindex_26) when _T_5193 : connect remapVecData[26], Queue2_UInt8_24.io.deq.bits connect remapVecValids[26], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_5194 = eq(UInt<5>(0h19), remapindex_26) when _T_5194 : connect remapVecData[26], Queue2_UInt8_25.io.deq.bits connect remapVecValids[26], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_5195 = eq(UInt<5>(0h1a), remapindex_26) when _T_5195 : connect remapVecData[26], Queue2_UInt8_26.io.deq.bits connect remapVecValids[26], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_5196 = eq(UInt<5>(0h1b), remapindex_26) when _T_5196 : connect remapVecData[26], Queue2_UInt8_27.io.deq.bits connect remapVecValids[26], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_5197 = eq(UInt<5>(0h1c), remapindex_26) when _T_5197 : connect remapVecData[26], Queue2_UInt8_28.io.deq.bits connect remapVecValids[26], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_5198 = eq(UInt<5>(0h1d), remapindex_26) when _T_5198 : connect remapVecData[26], Queue2_UInt8_29.io.deq.bits connect remapVecValids[26], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_5199 = eq(UInt<5>(0h1e), remapindex_26) when _T_5199 : connect remapVecData[26], Queue2_UInt8_30.io.deq.bits connect remapVecValids[26], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_5200 = eq(UInt<5>(0h1f), remapindex_26) when _T_5200 : connect remapVecData[26], Queue2_UInt8_31.io.deq.bits connect remapVecValids[26], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_5201 = eq(UInt<1>(0h0), remapindex_27) when _T_5201 : connect remapVecData[27], Queue2_UInt8.io.deq.bits connect remapVecValids[27], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[27] node _T_5202 = eq(UInt<1>(0h1), remapindex_27) when _T_5202 : connect remapVecData[27], Queue2_UInt8_1.io.deq.bits connect remapVecValids[27], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_5203 = eq(UInt<2>(0h2), remapindex_27) when _T_5203 : connect remapVecData[27], Queue2_UInt8_2.io.deq.bits connect remapVecValids[27], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_5204 = eq(UInt<2>(0h3), remapindex_27) when _T_5204 : connect remapVecData[27], Queue2_UInt8_3.io.deq.bits connect remapVecValids[27], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_5205 = eq(UInt<3>(0h4), remapindex_27) when _T_5205 : connect remapVecData[27], Queue2_UInt8_4.io.deq.bits connect remapVecValids[27], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_5206 = eq(UInt<3>(0h5), remapindex_27) when _T_5206 : connect remapVecData[27], Queue2_UInt8_5.io.deq.bits connect remapVecValids[27], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_5207 = eq(UInt<3>(0h6), remapindex_27) when _T_5207 : connect remapVecData[27], Queue2_UInt8_6.io.deq.bits connect remapVecValids[27], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_5208 = eq(UInt<3>(0h7), remapindex_27) when _T_5208 : connect remapVecData[27], Queue2_UInt8_7.io.deq.bits connect remapVecValids[27], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_5209 = eq(UInt<4>(0h8), remapindex_27) when _T_5209 : connect remapVecData[27], Queue2_UInt8_8.io.deq.bits connect remapVecValids[27], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_5210 = eq(UInt<4>(0h9), remapindex_27) when _T_5210 : connect remapVecData[27], Queue2_UInt8_9.io.deq.bits connect remapVecValids[27], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_5211 = eq(UInt<4>(0ha), remapindex_27) when _T_5211 : connect remapVecData[27], Queue2_UInt8_10.io.deq.bits connect remapVecValids[27], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_5212 = eq(UInt<4>(0hb), remapindex_27) when _T_5212 : connect remapVecData[27], Queue2_UInt8_11.io.deq.bits connect remapVecValids[27], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_5213 = eq(UInt<4>(0hc), remapindex_27) when _T_5213 : connect remapVecData[27], Queue2_UInt8_12.io.deq.bits connect remapVecValids[27], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_5214 = eq(UInt<4>(0hd), remapindex_27) when _T_5214 : connect remapVecData[27], Queue2_UInt8_13.io.deq.bits connect remapVecValids[27], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_5215 = eq(UInt<4>(0he), remapindex_27) when _T_5215 : connect remapVecData[27], Queue2_UInt8_14.io.deq.bits connect remapVecValids[27], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_5216 = eq(UInt<4>(0hf), remapindex_27) when _T_5216 : connect remapVecData[27], Queue2_UInt8_15.io.deq.bits connect remapVecValids[27], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_5217 = eq(UInt<5>(0h10), remapindex_27) when _T_5217 : connect remapVecData[27], Queue2_UInt8_16.io.deq.bits connect remapVecValids[27], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_5218 = eq(UInt<5>(0h11), remapindex_27) when _T_5218 : connect remapVecData[27], Queue2_UInt8_17.io.deq.bits connect remapVecValids[27], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_5219 = eq(UInt<5>(0h12), remapindex_27) when _T_5219 : connect remapVecData[27], Queue2_UInt8_18.io.deq.bits connect remapVecValids[27], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_5220 = eq(UInt<5>(0h13), remapindex_27) when _T_5220 : connect remapVecData[27], Queue2_UInt8_19.io.deq.bits connect remapVecValids[27], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_5221 = eq(UInt<5>(0h14), remapindex_27) when _T_5221 : connect remapVecData[27], Queue2_UInt8_20.io.deq.bits connect remapVecValids[27], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_5222 = eq(UInt<5>(0h15), remapindex_27) when _T_5222 : connect remapVecData[27], Queue2_UInt8_21.io.deq.bits connect remapVecValids[27], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_5223 = eq(UInt<5>(0h16), remapindex_27) when _T_5223 : connect remapVecData[27], Queue2_UInt8_22.io.deq.bits connect remapVecValids[27], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_5224 = eq(UInt<5>(0h17), remapindex_27) when _T_5224 : connect remapVecData[27], Queue2_UInt8_23.io.deq.bits connect remapVecValids[27], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_5225 = eq(UInt<5>(0h18), remapindex_27) when _T_5225 : connect remapVecData[27], Queue2_UInt8_24.io.deq.bits connect remapVecValids[27], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_5226 = eq(UInt<5>(0h19), remapindex_27) when _T_5226 : connect remapVecData[27], Queue2_UInt8_25.io.deq.bits connect remapVecValids[27], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_5227 = eq(UInt<5>(0h1a), remapindex_27) when _T_5227 : connect remapVecData[27], Queue2_UInt8_26.io.deq.bits connect remapVecValids[27], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_5228 = eq(UInt<5>(0h1b), remapindex_27) when _T_5228 : connect remapVecData[27], Queue2_UInt8_27.io.deq.bits connect remapVecValids[27], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_5229 = eq(UInt<5>(0h1c), remapindex_27) when _T_5229 : connect remapVecData[27], Queue2_UInt8_28.io.deq.bits connect remapVecValids[27], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_5230 = eq(UInt<5>(0h1d), remapindex_27) when _T_5230 : connect remapVecData[27], Queue2_UInt8_29.io.deq.bits connect remapVecValids[27], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_5231 = eq(UInt<5>(0h1e), remapindex_27) when _T_5231 : connect remapVecData[27], Queue2_UInt8_30.io.deq.bits connect remapVecValids[27], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_5232 = eq(UInt<5>(0h1f), remapindex_27) when _T_5232 : connect remapVecData[27], Queue2_UInt8_31.io.deq.bits connect remapVecValids[27], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_5233 = eq(UInt<1>(0h0), remapindex_28) when _T_5233 : connect remapVecData[28], Queue2_UInt8.io.deq.bits connect remapVecValids[28], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[28] node _T_5234 = eq(UInt<1>(0h1), remapindex_28) when _T_5234 : connect remapVecData[28], Queue2_UInt8_1.io.deq.bits connect remapVecValids[28], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_5235 = eq(UInt<2>(0h2), remapindex_28) when _T_5235 : connect remapVecData[28], Queue2_UInt8_2.io.deq.bits connect remapVecValids[28], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_5236 = eq(UInt<2>(0h3), remapindex_28) when _T_5236 : connect remapVecData[28], Queue2_UInt8_3.io.deq.bits connect remapVecValids[28], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_5237 = eq(UInt<3>(0h4), remapindex_28) when _T_5237 : connect remapVecData[28], Queue2_UInt8_4.io.deq.bits connect remapVecValids[28], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_5238 = eq(UInt<3>(0h5), remapindex_28) when _T_5238 : connect remapVecData[28], Queue2_UInt8_5.io.deq.bits connect remapVecValids[28], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_5239 = eq(UInt<3>(0h6), remapindex_28) when _T_5239 : connect remapVecData[28], Queue2_UInt8_6.io.deq.bits connect remapVecValids[28], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_5240 = eq(UInt<3>(0h7), remapindex_28) when _T_5240 : connect remapVecData[28], Queue2_UInt8_7.io.deq.bits connect remapVecValids[28], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_5241 = eq(UInt<4>(0h8), remapindex_28) when _T_5241 : connect remapVecData[28], Queue2_UInt8_8.io.deq.bits connect remapVecValids[28], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_5242 = eq(UInt<4>(0h9), remapindex_28) when _T_5242 : connect remapVecData[28], Queue2_UInt8_9.io.deq.bits connect remapVecValids[28], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_5243 = eq(UInt<4>(0ha), remapindex_28) when _T_5243 : connect remapVecData[28], Queue2_UInt8_10.io.deq.bits connect remapVecValids[28], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_5244 = eq(UInt<4>(0hb), remapindex_28) when _T_5244 : connect remapVecData[28], Queue2_UInt8_11.io.deq.bits connect remapVecValids[28], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_5245 = eq(UInt<4>(0hc), remapindex_28) when _T_5245 : connect remapVecData[28], Queue2_UInt8_12.io.deq.bits connect remapVecValids[28], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_5246 = eq(UInt<4>(0hd), remapindex_28) when _T_5246 : connect remapVecData[28], Queue2_UInt8_13.io.deq.bits connect remapVecValids[28], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_5247 = eq(UInt<4>(0he), remapindex_28) when _T_5247 : connect remapVecData[28], Queue2_UInt8_14.io.deq.bits connect remapVecValids[28], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_5248 = eq(UInt<4>(0hf), remapindex_28) when _T_5248 : connect remapVecData[28], Queue2_UInt8_15.io.deq.bits connect remapVecValids[28], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_5249 = eq(UInt<5>(0h10), remapindex_28) when _T_5249 : connect remapVecData[28], Queue2_UInt8_16.io.deq.bits connect remapVecValids[28], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_5250 = eq(UInt<5>(0h11), remapindex_28) when _T_5250 : connect remapVecData[28], Queue2_UInt8_17.io.deq.bits connect remapVecValids[28], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_5251 = eq(UInt<5>(0h12), remapindex_28) when _T_5251 : connect remapVecData[28], Queue2_UInt8_18.io.deq.bits connect remapVecValids[28], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_5252 = eq(UInt<5>(0h13), remapindex_28) when _T_5252 : connect remapVecData[28], Queue2_UInt8_19.io.deq.bits connect remapVecValids[28], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_5253 = eq(UInt<5>(0h14), remapindex_28) when _T_5253 : connect remapVecData[28], Queue2_UInt8_20.io.deq.bits connect remapVecValids[28], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_5254 = eq(UInt<5>(0h15), remapindex_28) when _T_5254 : connect remapVecData[28], Queue2_UInt8_21.io.deq.bits connect remapVecValids[28], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_5255 = eq(UInt<5>(0h16), remapindex_28) when _T_5255 : connect remapVecData[28], Queue2_UInt8_22.io.deq.bits connect remapVecValids[28], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_5256 = eq(UInt<5>(0h17), remapindex_28) when _T_5256 : connect remapVecData[28], Queue2_UInt8_23.io.deq.bits connect remapVecValids[28], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_5257 = eq(UInt<5>(0h18), remapindex_28) when _T_5257 : connect remapVecData[28], Queue2_UInt8_24.io.deq.bits connect remapVecValids[28], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_5258 = eq(UInt<5>(0h19), remapindex_28) when _T_5258 : connect remapVecData[28], Queue2_UInt8_25.io.deq.bits connect remapVecValids[28], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_5259 = eq(UInt<5>(0h1a), remapindex_28) when _T_5259 : connect remapVecData[28], Queue2_UInt8_26.io.deq.bits connect remapVecValids[28], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_5260 = eq(UInt<5>(0h1b), remapindex_28) when _T_5260 : connect remapVecData[28], Queue2_UInt8_27.io.deq.bits connect remapVecValids[28], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_5261 = eq(UInt<5>(0h1c), remapindex_28) when _T_5261 : connect remapVecData[28], Queue2_UInt8_28.io.deq.bits connect remapVecValids[28], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_5262 = eq(UInt<5>(0h1d), remapindex_28) when _T_5262 : connect remapVecData[28], Queue2_UInt8_29.io.deq.bits connect remapVecValids[28], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_5263 = eq(UInt<5>(0h1e), remapindex_28) when _T_5263 : connect remapVecData[28], Queue2_UInt8_30.io.deq.bits connect remapVecValids[28], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_5264 = eq(UInt<5>(0h1f), remapindex_28) when _T_5264 : connect remapVecData[28], Queue2_UInt8_31.io.deq.bits connect remapVecValids[28], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_5265 = eq(UInt<1>(0h0), remapindex_29) when _T_5265 : connect remapVecData[29], Queue2_UInt8.io.deq.bits connect remapVecValids[29], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[29] node _T_5266 = eq(UInt<1>(0h1), remapindex_29) when _T_5266 : connect remapVecData[29], Queue2_UInt8_1.io.deq.bits connect remapVecValids[29], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_5267 = eq(UInt<2>(0h2), remapindex_29) when _T_5267 : connect remapVecData[29], Queue2_UInt8_2.io.deq.bits connect remapVecValids[29], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_5268 = eq(UInt<2>(0h3), remapindex_29) when _T_5268 : connect remapVecData[29], Queue2_UInt8_3.io.deq.bits connect remapVecValids[29], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_5269 = eq(UInt<3>(0h4), remapindex_29) when _T_5269 : connect remapVecData[29], Queue2_UInt8_4.io.deq.bits connect remapVecValids[29], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_5270 = eq(UInt<3>(0h5), remapindex_29) when _T_5270 : connect remapVecData[29], Queue2_UInt8_5.io.deq.bits connect remapVecValids[29], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_5271 = eq(UInt<3>(0h6), remapindex_29) when _T_5271 : connect remapVecData[29], Queue2_UInt8_6.io.deq.bits connect remapVecValids[29], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_5272 = eq(UInt<3>(0h7), remapindex_29) when _T_5272 : connect remapVecData[29], Queue2_UInt8_7.io.deq.bits connect remapVecValids[29], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_5273 = eq(UInt<4>(0h8), remapindex_29) when _T_5273 : connect remapVecData[29], Queue2_UInt8_8.io.deq.bits connect remapVecValids[29], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_5274 = eq(UInt<4>(0h9), remapindex_29) when _T_5274 : connect remapVecData[29], Queue2_UInt8_9.io.deq.bits connect remapVecValids[29], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_5275 = eq(UInt<4>(0ha), remapindex_29) when _T_5275 : connect remapVecData[29], Queue2_UInt8_10.io.deq.bits connect remapVecValids[29], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_5276 = eq(UInt<4>(0hb), remapindex_29) when _T_5276 : connect remapVecData[29], Queue2_UInt8_11.io.deq.bits connect remapVecValids[29], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_5277 = eq(UInt<4>(0hc), remapindex_29) when _T_5277 : connect remapVecData[29], Queue2_UInt8_12.io.deq.bits connect remapVecValids[29], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_5278 = eq(UInt<4>(0hd), remapindex_29) when _T_5278 : connect remapVecData[29], Queue2_UInt8_13.io.deq.bits connect remapVecValids[29], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_5279 = eq(UInt<4>(0he), remapindex_29) when _T_5279 : connect remapVecData[29], Queue2_UInt8_14.io.deq.bits connect remapVecValids[29], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_5280 = eq(UInt<4>(0hf), remapindex_29) when _T_5280 : connect remapVecData[29], Queue2_UInt8_15.io.deq.bits connect remapVecValids[29], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_5281 = eq(UInt<5>(0h10), remapindex_29) when _T_5281 : connect remapVecData[29], Queue2_UInt8_16.io.deq.bits connect remapVecValids[29], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_5282 = eq(UInt<5>(0h11), remapindex_29) when _T_5282 : connect remapVecData[29], Queue2_UInt8_17.io.deq.bits connect remapVecValids[29], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_5283 = eq(UInt<5>(0h12), remapindex_29) when _T_5283 : connect remapVecData[29], Queue2_UInt8_18.io.deq.bits connect remapVecValids[29], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_5284 = eq(UInt<5>(0h13), remapindex_29) when _T_5284 : connect remapVecData[29], Queue2_UInt8_19.io.deq.bits connect remapVecValids[29], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_5285 = eq(UInt<5>(0h14), remapindex_29) when _T_5285 : connect remapVecData[29], Queue2_UInt8_20.io.deq.bits connect remapVecValids[29], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_5286 = eq(UInt<5>(0h15), remapindex_29) when _T_5286 : connect remapVecData[29], Queue2_UInt8_21.io.deq.bits connect remapVecValids[29], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_5287 = eq(UInt<5>(0h16), remapindex_29) when _T_5287 : connect remapVecData[29], Queue2_UInt8_22.io.deq.bits connect remapVecValids[29], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_5288 = eq(UInt<5>(0h17), remapindex_29) when _T_5288 : connect remapVecData[29], Queue2_UInt8_23.io.deq.bits connect remapVecValids[29], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_5289 = eq(UInt<5>(0h18), remapindex_29) when _T_5289 : connect remapVecData[29], Queue2_UInt8_24.io.deq.bits connect remapVecValids[29], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_5290 = eq(UInt<5>(0h19), remapindex_29) when _T_5290 : connect remapVecData[29], Queue2_UInt8_25.io.deq.bits connect remapVecValids[29], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_5291 = eq(UInt<5>(0h1a), remapindex_29) when _T_5291 : connect remapVecData[29], Queue2_UInt8_26.io.deq.bits connect remapVecValids[29], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_5292 = eq(UInt<5>(0h1b), remapindex_29) when _T_5292 : connect remapVecData[29], Queue2_UInt8_27.io.deq.bits connect remapVecValids[29], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_5293 = eq(UInt<5>(0h1c), remapindex_29) when _T_5293 : connect remapVecData[29], Queue2_UInt8_28.io.deq.bits connect remapVecValids[29], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_5294 = eq(UInt<5>(0h1d), remapindex_29) when _T_5294 : connect remapVecData[29], Queue2_UInt8_29.io.deq.bits connect remapVecValids[29], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_5295 = eq(UInt<5>(0h1e), remapindex_29) when _T_5295 : connect remapVecData[29], Queue2_UInt8_30.io.deq.bits connect remapVecValids[29], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_5296 = eq(UInt<5>(0h1f), remapindex_29) when _T_5296 : connect remapVecData[29], Queue2_UInt8_31.io.deq.bits connect remapVecValids[29], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_5297 = eq(UInt<1>(0h0), remapindex_30) when _T_5297 : connect remapVecData[30], Queue2_UInt8.io.deq.bits connect remapVecValids[30], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[30] node _T_5298 = eq(UInt<1>(0h1), remapindex_30) when _T_5298 : connect remapVecData[30], Queue2_UInt8_1.io.deq.bits connect remapVecValids[30], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_5299 = eq(UInt<2>(0h2), remapindex_30) when _T_5299 : connect remapVecData[30], Queue2_UInt8_2.io.deq.bits connect remapVecValids[30], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_5300 = eq(UInt<2>(0h3), remapindex_30) when _T_5300 : connect remapVecData[30], Queue2_UInt8_3.io.deq.bits connect remapVecValids[30], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_5301 = eq(UInt<3>(0h4), remapindex_30) when _T_5301 : connect remapVecData[30], Queue2_UInt8_4.io.deq.bits connect remapVecValids[30], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_5302 = eq(UInt<3>(0h5), remapindex_30) when _T_5302 : connect remapVecData[30], Queue2_UInt8_5.io.deq.bits connect remapVecValids[30], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_5303 = eq(UInt<3>(0h6), remapindex_30) when _T_5303 : connect remapVecData[30], Queue2_UInt8_6.io.deq.bits connect remapVecValids[30], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_5304 = eq(UInt<3>(0h7), remapindex_30) when _T_5304 : connect remapVecData[30], Queue2_UInt8_7.io.deq.bits connect remapVecValids[30], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_5305 = eq(UInt<4>(0h8), remapindex_30) when _T_5305 : connect remapVecData[30], Queue2_UInt8_8.io.deq.bits connect remapVecValids[30], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_5306 = eq(UInt<4>(0h9), remapindex_30) when _T_5306 : connect remapVecData[30], Queue2_UInt8_9.io.deq.bits connect remapVecValids[30], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_5307 = eq(UInt<4>(0ha), remapindex_30) when _T_5307 : connect remapVecData[30], Queue2_UInt8_10.io.deq.bits connect remapVecValids[30], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_5308 = eq(UInt<4>(0hb), remapindex_30) when _T_5308 : connect remapVecData[30], Queue2_UInt8_11.io.deq.bits connect remapVecValids[30], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_5309 = eq(UInt<4>(0hc), remapindex_30) when _T_5309 : connect remapVecData[30], Queue2_UInt8_12.io.deq.bits connect remapVecValids[30], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_5310 = eq(UInt<4>(0hd), remapindex_30) when _T_5310 : connect remapVecData[30], Queue2_UInt8_13.io.deq.bits connect remapVecValids[30], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_5311 = eq(UInt<4>(0he), remapindex_30) when _T_5311 : connect remapVecData[30], Queue2_UInt8_14.io.deq.bits connect remapVecValids[30], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_5312 = eq(UInt<4>(0hf), remapindex_30) when _T_5312 : connect remapVecData[30], Queue2_UInt8_15.io.deq.bits connect remapVecValids[30], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_5313 = eq(UInt<5>(0h10), remapindex_30) when _T_5313 : connect remapVecData[30], Queue2_UInt8_16.io.deq.bits connect remapVecValids[30], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_5314 = eq(UInt<5>(0h11), remapindex_30) when _T_5314 : connect remapVecData[30], Queue2_UInt8_17.io.deq.bits connect remapVecValids[30], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_5315 = eq(UInt<5>(0h12), remapindex_30) when _T_5315 : connect remapVecData[30], Queue2_UInt8_18.io.deq.bits connect remapVecValids[30], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_5316 = eq(UInt<5>(0h13), remapindex_30) when _T_5316 : connect remapVecData[30], Queue2_UInt8_19.io.deq.bits connect remapVecValids[30], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_5317 = eq(UInt<5>(0h14), remapindex_30) when _T_5317 : connect remapVecData[30], Queue2_UInt8_20.io.deq.bits connect remapVecValids[30], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_5318 = eq(UInt<5>(0h15), remapindex_30) when _T_5318 : connect remapVecData[30], Queue2_UInt8_21.io.deq.bits connect remapVecValids[30], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_5319 = eq(UInt<5>(0h16), remapindex_30) when _T_5319 : connect remapVecData[30], Queue2_UInt8_22.io.deq.bits connect remapVecValids[30], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_5320 = eq(UInt<5>(0h17), remapindex_30) when _T_5320 : connect remapVecData[30], Queue2_UInt8_23.io.deq.bits connect remapVecValids[30], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_5321 = eq(UInt<5>(0h18), remapindex_30) when _T_5321 : connect remapVecData[30], Queue2_UInt8_24.io.deq.bits connect remapVecValids[30], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_5322 = eq(UInt<5>(0h19), remapindex_30) when _T_5322 : connect remapVecData[30], Queue2_UInt8_25.io.deq.bits connect remapVecValids[30], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_5323 = eq(UInt<5>(0h1a), remapindex_30) when _T_5323 : connect remapVecData[30], Queue2_UInt8_26.io.deq.bits connect remapVecValids[30], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_5324 = eq(UInt<5>(0h1b), remapindex_30) when _T_5324 : connect remapVecData[30], Queue2_UInt8_27.io.deq.bits connect remapVecValids[30], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_5325 = eq(UInt<5>(0h1c), remapindex_30) when _T_5325 : connect remapVecData[30], Queue2_UInt8_28.io.deq.bits connect remapVecValids[30], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_5326 = eq(UInt<5>(0h1d), remapindex_30) when _T_5326 : connect remapVecData[30], Queue2_UInt8_29.io.deq.bits connect remapVecValids[30], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_5327 = eq(UInt<5>(0h1e), remapindex_30) when _T_5327 : connect remapVecData[30], Queue2_UInt8_30.io.deq.bits connect remapVecValids[30], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_5328 = eq(UInt<5>(0h1f), remapindex_30) when _T_5328 : connect remapVecData[30], Queue2_UInt8_31.io.deq.bits connect remapVecValids[30], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_5329 = eq(UInt<1>(0h0), remapindex_31) when _T_5329 : connect remapVecData[31], Queue2_UInt8.io.deq.bits connect remapVecValids[31], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[31] node _T_5330 = eq(UInt<1>(0h1), remapindex_31) when _T_5330 : connect remapVecData[31], Queue2_UInt8_1.io.deq.bits connect remapVecValids[31], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_5331 = eq(UInt<2>(0h2), remapindex_31) when _T_5331 : connect remapVecData[31], Queue2_UInt8_2.io.deq.bits connect remapVecValids[31], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_5332 = eq(UInt<2>(0h3), remapindex_31) when _T_5332 : connect remapVecData[31], Queue2_UInt8_3.io.deq.bits connect remapVecValids[31], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_5333 = eq(UInt<3>(0h4), remapindex_31) when _T_5333 : connect remapVecData[31], Queue2_UInt8_4.io.deq.bits connect remapVecValids[31], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_5334 = eq(UInt<3>(0h5), remapindex_31) when _T_5334 : connect remapVecData[31], Queue2_UInt8_5.io.deq.bits connect remapVecValids[31], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_5335 = eq(UInt<3>(0h6), remapindex_31) when _T_5335 : connect remapVecData[31], Queue2_UInt8_6.io.deq.bits connect remapVecValids[31], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_5336 = eq(UInt<3>(0h7), remapindex_31) when _T_5336 : connect remapVecData[31], Queue2_UInt8_7.io.deq.bits connect remapVecValids[31], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_5337 = eq(UInt<4>(0h8), remapindex_31) when _T_5337 : connect remapVecData[31], Queue2_UInt8_8.io.deq.bits connect remapVecValids[31], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_5338 = eq(UInt<4>(0h9), remapindex_31) when _T_5338 : connect remapVecData[31], Queue2_UInt8_9.io.deq.bits connect remapVecValids[31], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_5339 = eq(UInt<4>(0ha), remapindex_31) when _T_5339 : connect remapVecData[31], Queue2_UInt8_10.io.deq.bits connect remapVecValids[31], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_5340 = eq(UInt<4>(0hb), remapindex_31) when _T_5340 : connect remapVecData[31], Queue2_UInt8_11.io.deq.bits connect remapVecValids[31], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_5341 = eq(UInt<4>(0hc), remapindex_31) when _T_5341 : connect remapVecData[31], Queue2_UInt8_12.io.deq.bits connect remapVecValids[31], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_5342 = eq(UInt<4>(0hd), remapindex_31) when _T_5342 : connect remapVecData[31], Queue2_UInt8_13.io.deq.bits connect remapVecValids[31], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_5343 = eq(UInt<4>(0he), remapindex_31) when _T_5343 : connect remapVecData[31], Queue2_UInt8_14.io.deq.bits connect remapVecValids[31], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_5344 = eq(UInt<4>(0hf), remapindex_31) when _T_5344 : connect remapVecData[31], Queue2_UInt8_15.io.deq.bits connect remapVecValids[31], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_5345 = eq(UInt<5>(0h10), remapindex_31) when _T_5345 : connect remapVecData[31], Queue2_UInt8_16.io.deq.bits connect remapVecValids[31], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_5346 = eq(UInt<5>(0h11), remapindex_31) when _T_5346 : connect remapVecData[31], Queue2_UInt8_17.io.deq.bits connect remapVecValids[31], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_5347 = eq(UInt<5>(0h12), remapindex_31) when _T_5347 : connect remapVecData[31], Queue2_UInt8_18.io.deq.bits connect remapVecValids[31], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_5348 = eq(UInt<5>(0h13), remapindex_31) when _T_5348 : connect remapVecData[31], Queue2_UInt8_19.io.deq.bits connect remapVecValids[31], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_5349 = eq(UInt<5>(0h14), remapindex_31) when _T_5349 : connect remapVecData[31], Queue2_UInt8_20.io.deq.bits connect remapVecValids[31], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_5350 = eq(UInt<5>(0h15), remapindex_31) when _T_5350 : connect remapVecData[31], Queue2_UInt8_21.io.deq.bits connect remapVecValids[31], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_5351 = eq(UInt<5>(0h16), remapindex_31) when _T_5351 : connect remapVecData[31], Queue2_UInt8_22.io.deq.bits connect remapVecValids[31], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_5352 = eq(UInt<5>(0h17), remapindex_31) when _T_5352 : connect remapVecData[31], Queue2_UInt8_23.io.deq.bits connect remapVecValids[31], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_5353 = eq(UInt<5>(0h18), remapindex_31) when _T_5353 : connect remapVecData[31], Queue2_UInt8_24.io.deq.bits connect remapVecValids[31], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_5354 = eq(UInt<5>(0h19), remapindex_31) when _T_5354 : connect remapVecData[31], Queue2_UInt8_25.io.deq.bits connect remapVecValids[31], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_5355 = eq(UInt<5>(0h1a), remapindex_31) when _T_5355 : connect remapVecData[31], Queue2_UInt8_26.io.deq.bits connect remapVecValids[31], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_5356 = eq(UInt<5>(0h1b), remapindex_31) when _T_5356 : connect remapVecData[31], Queue2_UInt8_27.io.deq.bits connect remapVecValids[31], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_5357 = eq(UInt<5>(0h1c), remapindex_31) when _T_5357 : connect remapVecData[31], Queue2_UInt8_28.io.deq.bits connect remapVecValids[31], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_5358 = eq(UInt<5>(0h1d), remapindex_31) when _T_5358 : connect remapVecData[31], Queue2_UInt8_29.io.deq.bits connect remapVecValids[31], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_5359 = eq(UInt<5>(0h1e), remapindex_31) when _T_5359 : connect remapVecData[31], Queue2_UInt8_30.io.deq.bits connect remapVecValids[31], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_5360 = eq(UInt<5>(0h1f), remapindex_31) when _T_5360 : connect remapVecData[31], Queue2_UInt8_31.io.deq.bits connect remapVecValids[31], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[31] node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) regreset backend_bytes_written : UInt<64>, clock, reset, UInt<64>(0h0) node _backend_next_write_addr_T = add(dest_info_Q.io.deq.bits.op, backend_bytes_written) node backend_next_write_addr = tail(_backend_next_write_addr_T, 1) node _throttle_end_T = sub(buf_lens_Q.io.deq.bits, backend_bytes_written) node _throttle_end_T_1 = tail(_throttle_end_T, 1) node throttle_end = mux(buf_lens_Q.io.deq.valid, _throttle_end_T_1, UInt<6>(0h20)) node _throttle_end_writeable_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_T_6 = mux(_throttle_end_writeable_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _throttle_end_writeable_T_7 = mux(_throttle_end_writeable_T_4, UInt<2>(0h2), _throttle_end_writeable_T_6) node _throttle_end_writeable_T_8 = mux(_throttle_end_writeable_T_3, UInt<3>(0h4), _throttle_end_writeable_T_7) node _throttle_end_writeable_T_9 = mux(_throttle_end_writeable_T_2, UInt<4>(0h8), _throttle_end_writeable_T_8) node _throttle_end_writeable_T_10 = mux(_throttle_end_writeable_T_1, UInt<5>(0h10), _throttle_end_writeable_T_9) node throttle_end_writeable = mux(_throttle_end_writeable_T, UInt<6>(0h20), _throttle_end_writeable_T_10) node _throttle_end_writeable_log2_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_log2_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_log2_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_log2_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_log2_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_log2_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_log2_T_6 = mux(_throttle_end_writeable_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _throttle_end_writeable_log2_T_7 = mux(_throttle_end_writeable_log2_T_4, UInt<1>(0h1), _throttle_end_writeable_log2_T_6) node _throttle_end_writeable_log2_T_8 = mux(_throttle_end_writeable_log2_T_3, UInt<2>(0h2), _throttle_end_writeable_log2_T_7) node _throttle_end_writeable_log2_T_9 = mux(_throttle_end_writeable_log2_T_2, UInt<2>(0h3), _throttle_end_writeable_log2_T_8) node _throttle_end_writeable_log2_T_10 = mux(_throttle_end_writeable_log2_T_1, UInt<3>(0h4), _throttle_end_writeable_log2_T_9) node throttle_end_writeable_log2 = mux(_throttle_end_writeable_log2_T, UInt<3>(0h5), _throttle_end_writeable_log2_T_10) node _ptr_align_max_bytes_writeable_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_T_5 = mux(_ptr_align_max_bytes_writeable_T_4, UInt<5>(0h10), UInt<6>(0h20)) node _ptr_align_max_bytes_writeable_T_6 = mux(_ptr_align_max_bytes_writeable_T_3, UInt<4>(0h8), _ptr_align_max_bytes_writeable_T_5) node _ptr_align_max_bytes_writeable_T_7 = mux(_ptr_align_max_bytes_writeable_T_2, UInt<3>(0h4), _ptr_align_max_bytes_writeable_T_6) node _ptr_align_max_bytes_writeable_T_8 = mux(_ptr_align_max_bytes_writeable_T_1, UInt<2>(0h2), _ptr_align_max_bytes_writeable_T_7) node ptr_align_max_bytes_writeable = mux(_ptr_align_max_bytes_writeable_T, UInt<1>(0h1), _ptr_align_max_bytes_writeable_T_8) node _ptr_align_max_bytes_writeable_log2_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_log2_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_log2_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_log2_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_log2_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_log2_T_5 = mux(_ptr_align_max_bytes_writeable_log2_T_4, UInt<3>(0h4), UInt<3>(0h5)) node _ptr_align_max_bytes_writeable_log2_T_6 = mux(_ptr_align_max_bytes_writeable_log2_T_3, UInt<2>(0h3), _ptr_align_max_bytes_writeable_log2_T_5) node _ptr_align_max_bytes_writeable_log2_T_7 = mux(_ptr_align_max_bytes_writeable_log2_T_2, UInt<2>(0h2), _ptr_align_max_bytes_writeable_log2_T_6) node _ptr_align_max_bytes_writeable_log2_T_8 = mux(_ptr_align_max_bytes_writeable_log2_T_1, UInt<1>(0h1), _ptr_align_max_bytes_writeable_log2_T_7) node ptr_align_max_bytes_writeable_log2 = mux(_ptr_align_max_bytes_writeable_log2_T, UInt<1>(0h0), _ptr_align_max_bytes_writeable_log2_T_8) node _count_valids_largest_aligned_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_T_6 = mux(_count_valids_largest_aligned_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _count_valids_largest_aligned_T_7 = mux(_count_valids_largest_aligned_T_4, UInt<2>(0h2), _count_valids_largest_aligned_T_6) node _count_valids_largest_aligned_T_8 = mux(_count_valids_largest_aligned_T_3, UInt<3>(0h4), _count_valids_largest_aligned_T_7) node _count_valids_largest_aligned_T_9 = mux(_count_valids_largest_aligned_T_2, UInt<4>(0h8), _count_valids_largest_aligned_T_8) node _count_valids_largest_aligned_T_10 = mux(_count_valids_largest_aligned_T_1, UInt<5>(0h10), _count_valids_largest_aligned_T_9) node count_valids_largest_aligned = mux(_count_valids_largest_aligned_T, UInt<6>(0h20), _count_valids_largest_aligned_T_10) node _count_valids_largest_aligned_log2_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_log2_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_log2_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_log2_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_log2_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_log2_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_log2_T_6 = mux(_count_valids_largest_aligned_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _count_valids_largest_aligned_log2_T_7 = mux(_count_valids_largest_aligned_log2_T_4, UInt<1>(0h1), _count_valids_largest_aligned_log2_T_6) node _count_valids_largest_aligned_log2_T_8 = mux(_count_valids_largest_aligned_log2_T_3, UInt<2>(0h2), _count_valids_largest_aligned_log2_T_7) node _count_valids_largest_aligned_log2_T_9 = mux(_count_valids_largest_aligned_log2_T_2, UInt<2>(0h3), _count_valids_largest_aligned_log2_T_8) node _count_valids_largest_aligned_log2_T_10 = mux(_count_valids_largest_aligned_log2_T_1, UInt<3>(0h4), _count_valids_largest_aligned_log2_T_9) node count_valids_largest_aligned_log2 = mux(_count_valids_largest_aligned_log2_T, UInt<3>(0h5), _count_valids_largest_aligned_log2_T_10) node _bytes_to_write_T = lt(ptr_align_max_bytes_writeable, count_valids_largest_aligned) node _bytes_to_write_T_1 = lt(ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_2 = mux(_bytes_to_write_T_1, ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_3 = lt(count_valids_largest_aligned, throttle_end_writeable) node _bytes_to_write_T_4 = mux(_bytes_to_write_T_3, count_valids_largest_aligned, throttle_end_writeable) node bytes_to_write = mux(_bytes_to_write_T, _bytes_to_write_T_2, _bytes_to_write_T_4) node remapped_write_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node remapped_write_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node remapped_write_data_lo_lo_lo = cat(remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo) node remapped_write_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node remapped_write_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node remapped_write_data_lo_lo_hi = cat(remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo) node remapped_write_data_lo_lo = cat(remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo) node remapped_write_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node remapped_write_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node remapped_write_data_lo_hi_lo = cat(remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo) node remapped_write_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node remapped_write_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node remapped_write_data_lo_hi_hi = cat(remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo) node remapped_write_data_lo_hi = cat(remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo) node remapped_write_data_lo = cat(remapped_write_data_lo_hi, remapped_write_data_lo_lo) node remapped_write_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node remapped_write_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node remapped_write_data_hi_lo_lo = cat(remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo) node remapped_write_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node remapped_write_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node remapped_write_data_hi_lo_hi = cat(remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo) node remapped_write_data_hi_lo = cat(remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo) node remapped_write_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node remapped_write_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node remapped_write_data_hi_hi_lo = cat(remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo) node remapped_write_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node remapped_write_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node remapped_write_data_hi_hi_hi = cat(remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo) node remapped_write_data_hi_hi = cat(remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo) node remapped_write_data_hi = cat(remapped_write_data_hi_hi, remapped_write_data_hi_lo) node remapped_write_data = cat(remapped_write_data_hi, remapped_write_data_lo) node enough_data = neq(bytes_to_write, UInt<1>(0h0)) node _bytes_to_write_log2_T = lt(ptr_align_max_bytes_writeable_log2, count_valids_largest_aligned_log2) node _bytes_to_write_log2_T_1 = lt(ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_2 = mux(_bytes_to_write_log2_T_1, ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_3 = lt(count_valids_largest_aligned_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_4 = mux(_bytes_to_write_log2_T_3, count_valids_largest_aligned_log2, throttle_end_writeable_log2) node bytes_to_write_log2 = mux(_bytes_to_write_log2_T, _bytes_to_write_log2_T_2, _bytes_to_write_log2_T_4) node _write_ptr_override_T = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node write_ptr_override = and(buf_lens_Q.io.deq.valid, _write_ptr_override_T) node _T_5361 = eq(write_ptr_override, UInt<1>(0h0)) node _T_5362 = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node _remapVecReadys_0_T = lt(UInt<1>(0h0), bytes_to_write) node _remapVecReadys_0_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, _T_5361) node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_0_T_4 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_3) connect remapVecReadys[0], _remapVecReadys_0_T_4 node _remapVecReadys_1_T = lt(UInt<1>(0h1), bytes_to_write) node _remapVecReadys_1_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, _T_5361) node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_1_T_4 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_3) connect remapVecReadys[1], _remapVecReadys_1_T_4 node _remapVecReadys_2_T = lt(UInt<2>(0h2), bytes_to_write) node _remapVecReadys_2_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, _T_5361) node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_2_T_4 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_3) connect remapVecReadys[2], _remapVecReadys_2_T_4 node _remapVecReadys_3_T = lt(UInt<2>(0h3), bytes_to_write) node _remapVecReadys_3_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, _T_5361) node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_3_T_4 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_3) connect remapVecReadys[3], _remapVecReadys_3_T_4 node _remapVecReadys_4_T = lt(UInt<3>(0h4), bytes_to_write) node _remapVecReadys_4_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, _T_5361) node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_4_T_4 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_3) connect remapVecReadys[4], _remapVecReadys_4_T_4 node _remapVecReadys_5_T = lt(UInt<3>(0h5), bytes_to_write) node _remapVecReadys_5_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, _T_5361) node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_5_T_4 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_3) connect remapVecReadys[5], _remapVecReadys_5_T_4 node _remapVecReadys_6_T = lt(UInt<3>(0h6), bytes_to_write) node _remapVecReadys_6_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, _T_5361) node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_6_T_4 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_3) connect remapVecReadys[6], _remapVecReadys_6_T_4 node _remapVecReadys_7_T = lt(UInt<3>(0h7), bytes_to_write) node _remapVecReadys_7_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, _T_5361) node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_7_T_4 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_3) connect remapVecReadys[7], _remapVecReadys_7_T_4 node _remapVecReadys_8_T = lt(UInt<4>(0h8), bytes_to_write) node _remapVecReadys_8_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, _T_5361) node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_8_T_4 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_3) connect remapVecReadys[8], _remapVecReadys_8_T_4 node _remapVecReadys_9_T = lt(UInt<4>(0h9), bytes_to_write) node _remapVecReadys_9_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, _T_5361) node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_9_T_4 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_3) connect remapVecReadys[9], _remapVecReadys_9_T_4 node _remapVecReadys_10_T = lt(UInt<4>(0ha), bytes_to_write) node _remapVecReadys_10_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, _T_5361) node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_10_T_4 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_3) connect remapVecReadys[10], _remapVecReadys_10_T_4 node _remapVecReadys_11_T = lt(UInt<4>(0hb), bytes_to_write) node _remapVecReadys_11_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, _T_5361) node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_11_T_4 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_3) connect remapVecReadys[11], _remapVecReadys_11_T_4 node _remapVecReadys_12_T = lt(UInt<4>(0hc), bytes_to_write) node _remapVecReadys_12_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, _T_5361) node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_12_T_4 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_3) connect remapVecReadys[12], _remapVecReadys_12_T_4 node _remapVecReadys_13_T = lt(UInt<4>(0hd), bytes_to_write) node _remapVecReadys_13_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, _T_5361) node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_13_T_4 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_3) connect remapVecReadys[13], _remapVecReadys_13_T_4 node _remapVecReadys_14_T = lt(UInt<4>(0he), bytes_to_write) node _remapVecReadys_14_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, _T_5361) node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_14_T_4 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_3) connect remapVecReadys[14], _remapVecReadys_14_T_4 node _remapVecReadys_15_T = lt(UInt<4>(0hf), bytes_to_write) node _remapVecReadys_15_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, _T_5361) node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_15_T_4 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_3) connect remapVecReadys[15], _remapVecReadys_15_T_4 node _remapVecReadys_16_T = lt(UInt<5>(0h10), bytes_to_write) node _remapVecReadys_16_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, _T_5361) node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_16_T_4 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_3) connect remapVecReadys[16], _remapVecReadys_16_T_4 node _remapVecReadys_17_T = lt(UInt<5>(0h11), bytes_to_write) node _remapVecReadys_17_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, _T_5361) node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_17_T_4 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_3) connect remapVecReadys[17], _remapVecReadys_17_T_4 node _remapVecReadys_18_T = lt(UInt<5>(0h12), bytes_to_write) node _remapVecReadys_18_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, _T_5361) node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_18_T_4 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_3) connect remapVecReadys[18], _remapVecReadys_18_T_4 node _remapVecReadys_19_T = lt(UInt<5>(0h13), bytes_to_write) node _remapVecReadys_19_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, _T_5361) node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_19_T_4 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_3) connect remapVecReadys[19], _remapVecReadys_19_T_4 node _remapVecReadys_20_T = lt(UInt<5>(0h14), bytes_to_write) node _remapVecReadys_20_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, _T_5361) node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_20_T_4 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_3) connect remapVecReadys[20], _remapVecReadys_20_T_4 node _remapVecReadys_21_T = lt(UInt<5>(0h15), bytes_to_write) node _remapVecReadys_21_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, _T_5361) node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_21_T_4 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_3) connect remapVecReadys[21], _remapVecReadys_21_T_4 node _remapVecReadys_22_T = lt(UInt<5>(0h16), bytes_to_write) node _remapVecReadys_22_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, _T_5361) node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_22_T_4 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_3) connect remapVecReadys[22], _remapVecReadys_22_T_4 node _remapVecReadys_23_T = lt(UInt<5>(0h17), bytes_to_write) node _remapVecReadys_23_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, _T_5361) node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_23_T_4 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_3) connect remapVecReadys[23], _remapVecReadys_23_T_4 node _remapVecReadys_24_T = lt(UInt<5>(0h18), bytes_to_write) node _remapVecReadys_24_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, _T_5361) node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_24_T_4 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_3) connect remapVecReadys[24], _remapVecReadys_24_T_4 node _remapVecReadys_25_T = lt(UInt<5>(0h19), bytes_to_write) node _remapVecReadys_25_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, _T_5361) node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_25_T_4 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_3) connect remapVecReadys[25], _remapVecReadys_25_T_4 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), bytes_to_write) node _remapVecReadys_26_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, _T_5361) node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_26_T_4 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_3) connect remapVecReadys[26], _remapVecReadys_26_T_4 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), bytes_to_write) node _remapVecReadys_27_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, _T_5361) node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_27_T_4 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_3) connect remapVecReadys[27], _remapVecReadys_27_T_4 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), bytes_to_write) node _remapVecReadys_28_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, _T_5361) node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_28_T_4 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_3) connect remapVecReadys[28], _remapVecReadys_28_T_4 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), bytes_to_write) node _remapVecReadys_29_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, _T_5361) node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_29_T_4 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_3) connect remapVecReadys[29], _remapVecReadys_29_T_4 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), bytes_to_write) node _remapVecReadys_30_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, _T_5361) node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_30_T_4 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_3) connect remapVecReadys[30], _remapVecReadys_30_T_4 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), bytes_to_write) node _remapVecReadys_31_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, _T_5361) node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_31_T_4 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_3) connect remapVecReadys[31], _remapVecReadys_31_T_4 node _T_5363 = and(io.l2io.req.ready, enough_data) node _T_5364 = and(_T_5363, _T_5361) node _T_5365 = and(_T_5364, dest_info_Q.io.deq.valid) when _T_5365 : node _read_start_index_T = add(read_start_index, bytes_to_write) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1 node _backend_bytes_written_T = add(backend_bytes_written, bytes_to_write) node _backend_bytes_written_T_1 = tail(_backend_bytes_written_T, 1) connect backend_bytes_written, _backend_bytes_written_T_1 regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_5366 = asUInt(reset) node _T_5367 = eq(_T_5366, UInt<1>(0h0)) when _T_5367 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70 node _T_5368 = asUInt(reset) node _T_5369 = eq(_T_5368, UInt<1>(0h0)) when _T_5369 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] writefire: addr: 0x%x, data 0x%x, size %d\n", io.l2io.req.bits.addr, io.l2io.req.bits.data, io.l2io.req.bits.size) : printf_71 node _io_l2io_req_valid_T = and(enough_data, _T_5361) node _io_l2io_req_valid_T_1 = and(_io_l2io_req_valid_T, dest_info_Q.io.deq.valid) node _io_l2io_req_valid_T_2 = and(buf_lens_Q.io.deq.valid, _T_5362) node _io_l2io_req_valid_T_3 = and(_io_l2io_req_valid_T_2, dest_info_Q.io.deq.valid) node _io_l2io_req_valid_T_4 = or(_io_l2io_req_valid_T_1, _io_l2io_req_valid_T_3) connect io.l2io.req.valid, _io_l2io_req_valid_T_4 node _io_l2io_req_bits_size_T = mux(write_ptr_override, UInt<2>(0h2), bytes_to_write_log2) connect io.l2io.req.bits.size, _io_l2io_req_bits_size_T node _io_l2io_req_bits_addr_T = mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr) connect io.l2io.req.bits.addr, _io_l2io_req_bits_addr_T node _io_l2io_req_bits_data_T = mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpval, remapped_write_data) connect io.l2io.req.bits.data, _io_l2io_req_bits_data_T connect io.l2io.req.bits.cmd, UInt<1>(0h1) node _buf_lens_Q_io_deq_ready_T = and(io.l2io.req.ready, _T_5362) node _buf_lens_Q_io_deq_ready_T_1 = and(_buf_lens_Q_io_deq_ready_T, dest_info_Q.io.deq.valid) connect buf_lens_Q.io.deq.ready, _buf_lens_Q_io_deq_ready_T_1 node _dest_info_Q_io_deq_ready_T = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _dest_info_Q_io_deq_ready_T_1 = and(_dest_info_Q_io_deq_ready_T, _T_5362) connect dest_info_Q.io.deq.ready, _dest_info_Q_io_deq_ready_T_1 regreset bufs_completed : UInt<64>, clock, reset, UInt<64>(0h0) connect io.bufs_completed, bufs_completed connect io.l2io.resp.ready, UInt<1>(0h1) connect io.no_writes_inflight, io.l2io.no_memops_inflight node _T_5370 = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _T_5371 = and(_T_5370, _T_5362) node _T_5372 = and(_T_5371, dest_info_Q.io.deq.valid) when _T_5372 : node _bufs_completed_T = add(bufs_completed, UInt<1>(0h1)) node _bufs_completed_T_1 = tail(_bufs_completed_T, 1) connect bufs_completed, _bufs_completed_T_1 connect backend_bytes_written, UInt<1>(0h0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_5373 = asUInt(reset) node _T_5374 = eq(_T_5373, UInt<1>(0h0)) when _T_5374 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72 node _T_5375 = asUInt(reset) node _T_5376 = eq(_T_5375, UInt<1>(0h0)) when _T_5376 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] write cmpflag addr: 0x%x, write ptr val 0x%x\n", dest_info_Q.io.deq.bits.cmpflag, dest_info_Q.io.deq.bits.cmpval) : printf_73 node _T_5377 = neq(count_valids, UInt<1>(0h0)) when _T_5377 : regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_5378 = asUInt(reset) node _T_5379 = eq(_T_5378, UInt<1>(0h0)) when _T_5379 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74 node _T_5380 = asUInt(reset) node _T_5381 = eq(_T_5380, UInt<1>(0h0)) when _T_5381 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d\n", read_start_index, backend_bytes_written, count_valids, ptr_align_max_bytes_writeable, bytes_to_write, bytes_to_write_log2) : printf_75	module ZstdCompressorMemWriter_1( // @[ZstdCompressorMemWriter.scala:23:7] input clock, // @[ZstdCompressorMemWriter.scala:23:7] input reset, // @[ZstdCompressorMemWriter.scala:23:7] output io_memwrites_in_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_memwrites_in_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_req_ready, // @[ZstdCompressorMemWriter.scala:26:14] output io_l2io_req_valid, // @[ZstdCompressorMemWriter.scala:26:14] output [63:0] io_l2io_req_bits_addr, // @[ZstdCompressorMemWriter.scala:26:14] output [2:0] io_l2io_req_bits_size, // @[ZstdCompressorMemWriter.scala:26:14] output [255:0] io_l2io_req_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_resp_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_l2io_resp_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_no_memops_inflight, // @[ZstdCompressorMemWriter.scala:26:14] output io_dest_info_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_dest_info_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_op, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpflag, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpval // @[ZstdCompressorMemWriter.scala:26:14] ); wire _Queue2_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_31_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_31_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_30_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_30_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_29_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_29_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_28_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_28_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_27_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_27_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_26_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_26_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_25_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_25_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_24_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_24_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_23_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_23_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_22_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_22_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_21_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_21_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_20_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_20_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_19_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_19_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_18_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_18_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_17_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_17_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_16_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_16_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_15_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_15_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_14_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_14_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_13_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_13_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_12_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_12_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_11_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_11_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_10_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_10_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_9_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_9_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_7_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_7_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_6_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_6_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_5_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_5_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_4_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_4_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_3_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_3_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_2_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_2_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_1_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_1_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:52:26] wire _buf_lens_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:52:26] wire [63:0] _buf_lens_Q_io_deq_bits; // @[ZstdCompressorMemWriter.scala:52:26] wire _dest_info_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_op; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpval; // @[ZstdCompressorMemWriter.scala:39:27] wire _incoming_writes_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:35:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdCompressorMemWriter.scala:35:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdCompressorMemWriter.scala:35:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_valid_0 = io_dest_info_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_op_0 = io_dest_info_bits_op; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpflag_0 = io_dest_info_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpval_0 = io_dest_info_bits_cmpval; // @[ZstdCompressorMemWriter.scala:23:7] wire [5:0] io_memwrites_in_bits_validbytes = 6'h3; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_bits_end_of_message = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_bits_cmd = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_ready = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:187:50] wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:218:56] wire _io_l2io_req_valid_T_4; // @[ZstdCompressorMemWriter.scala:278:65] wire [63:0] _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:283:31] wire [2:0] _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:282:31] wire [255:0] _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:284:31] wire io_no_writes_inflight = io_l2io_no_memops_inflight_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_l2io_req_bits_addr_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [2:0] io_l2io_req_bits_size_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_req_bits_data_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_valid_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7] wire _dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53] wire _decompress_dest_last_fire_T = _dest_info_Q_io_deq_ready_T_1 & _dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35] reg decompress_dest_last_fire; // @[ZstdCompressorMemWriter.scala:42:42] reg decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43] wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43, :44:94] wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire \| _decompress_dest_printhelp_T; // @[ZstdCompressorMemWriter.scala:42:42, :44:{90,94}] wire decompress_dest_printhelp = _dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[ZstdCompressorMemWriter.scala:39:27, :44:{60,90}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] buf_len_tracker; // @[ZstdCompressorMemWriter.scala:57:32] wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53] wire _T_10 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35] wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :57:32, :62:42] wire [64:0] _buf_len_tracker_T; // @[ZstdCompressorMemWriter.scala:62:42] assign _buf_len_tracker_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42] wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[ZstdCompressorMemWriter.scala:112:45] assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42, :112:45] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdCompressorMemWriter.scala:76:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdCompressorMemWriter.scala:76:34, :86:34] wire [6:0] _GEN_0 = _idx_T % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx = _GEN_0[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_1 = _idx_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_1 = _GEN_1[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_2 = _idx_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_2 = _GEN_2[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_3 = _idx_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_3 = _GEN_3[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_4 = _idx_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_4 = _GEN_4[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_5 = _idx_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_5 = _GEN_5[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_6 = _idx_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_6 = _GEN_6[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_7 = _idx_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_7 = _GEN_7[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_8 = _idx_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_8 = _GEN_8[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_9 = _idx_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_9 = _GEN_9[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_10 = _idx_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_10 = _GEN_10[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_11 = _idx_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_11 = _GEN_11[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_12 = _idx_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_12 = _GEN_12[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_13 = _idx_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_13 = _GEN_13[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_14 = _idx_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_14 = _GEN_14[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_15 = _idx_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_15 = _GEN_15[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_16 = _idx_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_16 = _GEN_16[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_17 = _idx_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_17 = _GEN_17[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_18 = _idx_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_18 = _GEN_18[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_19 = _idx_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_19 = _GEN_19[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_20 = _idx_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_20 = _GEN_20[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_21 = _idx_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_21 = _GEN_21[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_22 = _idx_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_22 = _GEN_22[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_23 = _idx_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_23 = _GEN_23[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_24 = _idx_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_24 = _GEN_24[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_25 = _idx_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_25 = _GEN_25[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_26 = _idx_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_26 = _GEN_26[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_27 = _idx_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_27 = _GEN_27[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_28 = _idx_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_28 = _GEN_28[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_29 = _idx_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_29 = _GEN_29[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_30 = _idx_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_30 = _GEN_30[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_31 = _idx_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_31 = _GEN_31[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :86:34, :95:47] wire [6:0] _GEN_32 = wrap_len_index_wide % 7'h20; // @[ZstdCompressorMemWriter.scala:95:47, :96:48] wire [5:0] wrap_len_index_end = _GEN_32[5:0]; // @[ZstdCompressorMemWriter.scala:96:48] wire wrapped = \|(wrap_len_index_wide[6:5]); // @[ZstdCompressorMemWriter.scala:95:47, :97:37] wire _all_queues_ready_T = _Queue2_UInt8_io_enq_ready & _Queue2_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue2_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue2_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue2_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue2_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue2_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue2_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue2_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue2_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue2_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue2_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue2_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue2_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue2_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue2_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue2_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue2_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue2_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue2_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue2_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue2_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue2_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue2_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue2_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue2_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue2_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue2_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue2_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue2_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue2_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue2_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33, :103:33] wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:35:33, :52:26, :103:61] wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T \| _account_for_buf_lens_Q_T_1; // @[ZstdCompressorMemWriter.scala:103:{33,46,61}] wire _buf_lens_Q_io_enq_valid_T = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53] assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53] wire _GEN_33 = write_start_index == 6'h0; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_3; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_3 = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_1 = \|wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_2 = _use_this_queue_T \| _use_this_queue_T_1; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_4 = \|wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_34 = write_start_index < 6'h2; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_6; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_6 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_9; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_9 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_7 = \|(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 \| _use_this_queue_T_7; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_10 = \|(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_35 = write_start_index < 6'h3; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_12; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_12 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_15; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_15 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_36 = wrap_len_index_end > 6'h2; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_13 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_16 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 \| _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_37 = write_start_index < 6'h4; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_18; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_18 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_21; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_21 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_19 = \|(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 \| _use_this_queue_T_19; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_22 = \|(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_38 = write_start_index < 6'h5; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_24; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_24 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_27; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_27 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_39 = wrap_len_index_end > 6'h4; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_25 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_28 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 \| _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_40 = write_start_index < 6'h6; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_30; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_30 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_33; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_33 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_41 = wrap_len_index_end > 6'h5; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_31 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_34 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 \| _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_42 = write_start_index < 6'h7; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_36; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_36 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_39; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_39 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_43 = wrap_len_index_end > 6'h6; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_37 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_40 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 \| _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_44 = write_start_index < 6'h8; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_42; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_42 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_45; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_45 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_43 = \|(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 \| _use_this_queue_T_43; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_46 = \|(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_45 = write_start_index < 6'h9; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_48; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_48 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_51; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_51 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_46 = wrap_len_index_end > 6'h8; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_49 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_52 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 \| _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_47 = write_start_index < 6'hA; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_54; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_54 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_57; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_57 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_48 = wrap_len_index_end > 6'h9; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_55 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_58 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 \| _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_49 = write_start_index < 6'hB; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_60; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_60 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_63; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_63 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_50 = wrap_len_index_end > 6'hA; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_61 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_64 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 \| _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_51 = write_start_index < 6'hC; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_66; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_66 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_69; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_69 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_52 = wrap_len_index_end > 6'hB; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_67 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_70 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 \| _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_53 = write_start_index < 6'hD; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_72; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_72 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_75; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_75 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_54 = wrap_len_index_end > 6'hC; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_73 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_76 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 \| _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_55 = write_start_index < 6'hE; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_78; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_78 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_81; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_81 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_56 = wrap_len_index_end > 6'hD; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_79 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_82 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 \| _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_57 = write_start_index < 6'hF; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_84; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_84 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_87; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_87 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_58 = wrap_len_index_end > 6'hE; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_85 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_88 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 \| _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_59 = write_start_index < 6'h10; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_90; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_90 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_93; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_93 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_91 = \|(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 \| _use_this_queue_T_91; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_94 = \|(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_60 = write_start_index < 6'h11; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_96; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_96 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_99; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_99 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_61 = wrap_len_index_end > 6'h10; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_97 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_100 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 \| _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_62 = write_start_index < 6'h12; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_102; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_102 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_105; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_105 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_63 = wrap_len_index_end > 6'h11; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_103 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_106 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 \| _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_64 = write_start_index < 6'h13; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_108; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_108 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_111; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_111 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_65 = wrap_len_index_end > 6'h12; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_109 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_112 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 \| _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_66 = write_start_index < 6'h14; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_114; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_114 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_117; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_117 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_67 = wrap_len_index_end > 6'h13; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_115 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_118 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 \| _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_68 = write_start_index < 6'h15; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_120; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_120 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_123; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_123 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_69 = wrap_len_index_end > 6'h14; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_121 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_124 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 \| _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_70 = write_start_index < 6'h16; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_126; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_126 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_129; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_129 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_71 = wrap_len_index_end > 6'h15; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_127 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_130 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 \| _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_72 = write_start_index < 6'h17; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_132; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_132 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_135; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_135 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_73 = wrap_len_index_end > 6'h16; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_133 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_136 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 \| _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_74 = write_start_index < 6'h18; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_138; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_138 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_141; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_141 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_75 = wrap_len_index_end > 6'h17; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_139 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_142 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 \| _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_76 = write_start_index < 6'h19; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_144; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_144 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_147; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_147 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_77 = wrap_len_index_end > 6'h18; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_145 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_148 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 \| _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_78 = write_start_index < 6'h1A; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_150; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_150 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_153; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_153 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_79 = wrap_len_index_end > 6'h19; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_151 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_154 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 \| _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_80 = write_start_index < 6'h1B; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_156; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_156 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_159; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_159 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_81 = wrap_len_index_end > 6'h1A; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_157 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_160 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 \| _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_82 = write_start_index < 6'h1C; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_162; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_162 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_165; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_165 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_83 = wrap_len_index_end > 6'h1B; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_163 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_166 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 \| _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_84 = write_start_index < 6'h1D; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_168; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_168 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_171; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_171 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_85 = wrap_len_index_end > 6'h1C; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_169 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_172 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 \| _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_86 = write_start_index < 6'h1E; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_174; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_174 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_177; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_177 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_87 = wrap_len_index_end > 6'h1D; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_175 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_178 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 \| _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_88 = write_start_index < 6'h1F; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_180; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_180 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_183; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_183 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_89 = wrap_len_index_end > 6'h1E; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_181 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_184 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 \| _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 \| _use_this_queue_T_187; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41, :125:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdCompressorMemWriter.scala:139:33] wire [7:0] remapVecData_0; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_1; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_2; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_3; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_4; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_5; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_6; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_7; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_8; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_9; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_10; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_11; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_12; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_13; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_14; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_15; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_16; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_17; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_18; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_19; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_20; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_21; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_22; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_23; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_24; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_25; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_26; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_27; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_28; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_29; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_30; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_31; // @[ZstdCompressorMemWriter.scala:141:26] wire remapVecValids_0; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_1; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_2; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_3; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_4; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_5; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_6; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_7; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_8; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_9; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_10; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_11; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_12; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_13; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_14; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_15; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_16; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_17; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_18; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_19; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_20; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_21; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_22; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_23; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_24; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_25; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_26; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_27; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_28; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_29; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_30; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_31; // @[ZstdCompressorMemWriter.scala:142:28] wire _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire remapVecReadys_0; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_1; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_2; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_3; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_4; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_5; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_6; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_7; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_8; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_9; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_10; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_11; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_12; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_13; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_14; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_15; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_16; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_17; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_18; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_19; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_20; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_21; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_22; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_23; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_24; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_25; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_26; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_27; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_28; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_29; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_30; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_31; // @[ZstdCompressorMemWriter.scala:143:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdCompressorMemWriter.scala:139:33, :153:33] wire [6:0] _GEN_90 = _remapindex_T % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex = _GEN_90[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4337 = remapindex == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4338 = remapindex == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4339 = remapindex == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4340 = remapindex == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4341 = remapindex == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4342 = remapindex == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4343 = remapindex == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4344 = remapindex == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4345 = remapindex == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4346 = remapindex == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4347 = remapindex == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4348 = remapindex == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4349 = remapindex == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4350 = remapindex == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4351 = remapindex == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4352 = remapindex == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4353 = remapindex == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4354 = remapindex == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4355 = remapindex == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4356 = remapindex == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4357 = remapindex == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4358 = remapindex == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4359 = remapindex == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4360 = remapindex == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4361 = remapindex == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4362 = remapindex == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4363 = remapindex == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4364 = remapindex == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4365 = remapindex == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4366 = remapindex == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4367 = remapindex == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4368 = remapindex == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_0 = _T_4368 ? _Queue2_UInt8_31_io_deq_bits : _T_4367 ? _Queue2_UInt8_30_io_deq_bits : _T_4366 ? _Queue2_UInt8_29_io_deq_bits : _T_4365 ? _Queue2_UInt8_28_io_deq_bits : _T_4364 ? _Queue2_UInt8_27_io_deq_bits : _T_4363 ? _Queue2_UInt8_26_io_deq_bits : _T_4362 ? _Queue2_UInt8_25_io_deq_bits : _T_4361 ? _Queue2_UInt8_24_io_deq_bits : _T_4360 ? _Queue2_UInt8_23_io_deq_bits : _T_4359 ? _Queue2_UInt8_22_io_deq_bits : _T_4358 ? _Queue2_UInt8_21_io_deq_bits : _T_4357 ? _Queue2_UInt8_20_io_deq_bits : _T_4356 ? _Queue2_UInt8_19_io_deq_bits : _T_4355 ? _Queue2_UInt8_18_io_deq_bits : _T_4354 ? _Queue2_UInt8_17_io_deq_bits : _T_4353 ? _Queue2_UInt8_16_io_deq_bits : _T_4352 ? _Queue2_UInt8_15_io_deq_bits : _T_4351 ? _Queue2_UInt8_14_io_deq_bits : _T_4350 ? _Queue2_UInt8_13_io_deq_bits : _T_4349 ? _Queue2_UInt8_12_io_deq_bits : _T_4348 ? _Queue2_UInt8_11_io_deq_bits : _T_4347 ? _Queue2_UInt8_10_io_deq_bits : _T_4346 ? _Queue2_UInt8_9_io_deq_bits : _T_4345 ? _Queue2_UInt8_8_io_deq_bits : _T_4344 ? _Queue2_UInt8_7_io_deq_bits : _T_4343 ? _Queue2_UInt8_6_io_deq_bits : _T_4342 ? _Queue2_UInt8_5_io_deq_bits : _T_4341 ? _Queue2_UInt8_4_io_deq_bits : _T_4340 ? _Queue2_UInt8_3_io_deq_bits : _T_4339 ? _Queue2_UInt8_2_io_deq_bits : _T_4338 ? _Queue2_UInt8_1_io_deq_bits : _T_4337 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_0 = _T_4368 ? _Queue2_UInt8_31_io_deq_valid : _T_4367 ? _Queue2_UInt8_30_io_deq_valid : _T_4366 ? _Queue2_UInt8_29_io_deq_valid : _T_4365 ? _Queue2_UInt8_28_io_deq_valid : _T_4364 ? _Queue2_UInt8_27_io_deq_valid : _T_4363 ? _Queue2_UInt8_26_io_deq_valid : _T_4362 ? _Queue2_UInt8_25_io_deq_valid : _T_4361 ? _Queue2_UInt8_24_io_deq_valid : _T_4360 ? _Queue2_UInt8_23_io_deq_valid : _T_4359 ? _Queue2_UInt8_22_io_deq_valid : _T_4358 ? _Queue2_UInt8_21_io_deq_valid : _T_4357 ? _Queue2_UInt8_20_io_deq_valid : _T_4356 ? _Queue2_UInt8_19_io_deq_valid : _T_4355 ? _Queue2_UInt8_18_io_deq_valid : _T_4354 ? _Queue2_UInt8_17_io_deq_valid : _T_4353 ? _Queue2_UInt8_16_io_deq_valid : _T_4352 ? _Queue2_UInt8_15_io_deq_valid : _T_4351 ? _Queue2_UInt8_14_io_deq_valid : _T_4350 ? _Queue2_UInt8_13_io_deq_valid : _T_4349 ? _Queue2_UInt8_12_io_deq_valid : _T_4348 ? _Queue2_UInt8_11_io_deq_valid : _T_4347 ? _Queue2_UInt8_10_io_deq_valid : _T_4346 ? _Queue2_UInt8_9_io_deq_valid : _T_4345 ? _Queue2_UInt8_8_io_deq_valid : _T_4344 ? _Queue2_UInt8_7_io_deq_valid : _T_4343 ? _Queue2_UInt8_6_io_deq_valid : _T_4342 ? _Queue2_UInt8_5_io_deq_valid : _T_4341 ? _Queue2_UInt8_4_io_deq_valid : _T_4340 ? _Queue2_UInt8_3_io_deq_valid : _T_4339 ? _Queue2_UInt8_2_io_deq_valid : _T_4338 ? _Queue2_UInt8_1_io_deq_valid : _T_4337 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_91 = _remapindex_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_1 = _GEN_91[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4369 = remapindex_1 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4370 = remapindex_1 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4371 = remapindex_1 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4372 = remapindex_1 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4373 = remapindex_1 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4374 = remapindex_1 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4375 = remapindex_1 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4376 = remapindex_1 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4377 = remapindex_1 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4378 = remapindex_1 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4379 = remapindex_1 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4380 = remapindex_1 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4381 = remapindex_1 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4382 = remapindex_1 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4383 = remapindex_1 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4384 = remapindex_1 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4385 = remapindex_1 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4386 = remapindex_1 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4387 = remapindex_1 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4388 = remapindex_1 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4389 = remapindex_1 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4390 = remapindex_1 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4391 = remapindex_1 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4392 = remapindex_1 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4393 = remapindex_1 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4394 = remapindex_1 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4395 = remapindex_1 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4396 = remapindex_1 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4397 = remapindex_1 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4398 = remapindex_1 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4399 = remapindex_1 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4400 = remapindex_1 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_1 = _T_4400 ? _Queue2_UInt8_31_io_deq_bits : _T_4399 ? _Queue2_UInt8_30_io_deq_bits : _T_4398 ? _Queue2_UInt8_29_io_deq_bits : _T_4397 ? _Queue2_UInt8_28_io_deq_bits : _T_4396 ? _Queue2_UInt8_27_io_deq_bits : _T_4395 ? _Queue2_UInt8_26_io_deq_bits : _T_4394 ? _Queue2_UInt8_25_io_deq_bits : _T_4393 ? _Queue2_UInt8_24_io_deq_bits : _T_4392 ? _Queue2_UInt8_23_io_deq_bits : _T_4391 ? _Queue2_UInt8_22_io_deq_bits : _T_4390 ? _Queue2_UInt8_21_io_deq_bits : _T_4389 ? _Queue2_UInt8_20_io_deq_bits : _T_4388 ? _Queue2_UInt8_19_io_deq_bits : _T_4387 ? _Queue2_UInt8_18_io_deq_bits : _T_4386 ? _Queue2_UInt8_17_io_deq_bits : _T_4385 ? _Queue2_UInt8_16_io_deq_bits : _T_4384 ? _Queue2_UInt8_15_io_deq_bits : _T_4383 ? _Queue2_UInt8_14_io_deq_bits : _T_4382 ? _Queue2_UInt8_13_io_deq_bits : _T_4381 ? _Queue2_UInt8_12_io_deq_bits : _T_4380 ? _Queue2_UInt8_11_io_deq_bits : _T_4379 ? _Queue2_UInt8_10_io_deq_bits : _T_4378 ? _Queue2_UInt8_9_io_deq_bits : _T_4377 ? _Queue2_UInt8_8_io_deq_bits : _T_4376 ? _Queue2_UInt8_7_io_deq_bits : _T_4375 ? _Queue2_UInt8_6_io_deq_bits : _T_4374 ? _Queue2_UInt8_5_io_deq_bits : _T_4373 ? _Queue2_UInt8_4_io_deq_bits : _T_4372 ? _Queue2_UInt8_3_io_deq_bits : _T_4371 ? _Queue2_UInt8_2_io_deq_bits : _T_4370 ? _Queue2_UInt8_1_io_deq_bits : _T_4369 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_1 = _T_4400 ? _Queue2_UInt8_31_io_deq_valid : _T_4399 ? _Queue2_UInt8_30_io_deq_valid : _T_4398 ? _Queue2_UInt8_29_io_deq_valid : _T_4397 ? _Queue2_UInt8_28_io_deq_valid : _T_4396 ? _Queue2_UInt8_27_io_deq_valid : _T_4395 ? _Queue2_UInt8_26_io_deq_valid : _T_4394 ? _Queue2_UInt8_25_io_deq_valid : _T_4393 ? _Queue2_UInt8_24_io_deq_valid : _T_4392 ? _Queue2_UInt8_23_io_deq_valid : _T_4391 ? _Queue2_UInt8_22_io_deq_valid : _T_4390 ? _Queue2_UInt8_21_io_deq_valid : _T_4389 ? _Queue2_UInt8_20_io_deq_valid : _T_4388 ? _Queue2_UInt8_19_io_deq_valid : _T_4387 ? _Queue2_UInt8_18_io_deq_valid : _T_4386 ? _Queue2_UInt8_17_io_deq_valid : _T_4385 ? _Queue2_UInt8_16_io_deq_valid : _T_4384 ? _Queue2_UInt8_15_io_deq_valid : _T_4383 ? _Queue2_UInt8_14_io_deq_valid : _T_4382 ? _Queue2_UInt8_13_io_deq_valid : _T_4381 ? _Queue2_UInt8_12_io_deq_valid : _T_4380 ? _Queue2_UInt8_11_io_deq_valid : _T_4379 ? _Queue2_UInt8_10_io_deq_valid : _T_4378 ? _Queue2_UInt8_9_io_deq_valid : _T_4377 ? _Queue2_UInt8_8_io_deq_valid : _T_4376 ? _Queue2_UInt8_7_io_deq_valid : _T_4375 ? _Queue2_UInt8_6_io_deq_valid : _T_4374 ? _Queue2_UInt8_5_io_deq_valid : _T_4373 ? _Queue2_UInt8_4_io_deq_valid : _T_4372 ? _Queue2_UInt8_3_io_deq_valid : _T_4371 ? _Queue2_UInt8_2_io_deq_valid : _T_4370 ? _Queue2_UInt8_1_io_deq_valid : _T_4369 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_92 = _remapindex_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_2 = _GEN_92[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4401 = remapindex_2 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4402 = remapindex_2 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4403 = remapindex_2 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4404 = remapindex_2 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4405 = remapindex_2 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4406 = remapindex_2 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4407 = remapindex_2 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4408 = remapindex_2 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4409 = remapindex_2 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4410 = remapindex_2 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4411 = remapindex_2 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4412 = remapindex_2 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4413 = remapindex_2 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4414 = remapindex_2 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4415 = remapindex_2 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4416 = remapindex_2 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4417 = remapindex_2 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4418 = remapindex_2 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4419 = remapindex_2 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4420 = remapindex_2 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4421 = remapindex_2 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4422 = remapindex_2 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4423 = remapindex_2 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4424 = remapindex_2 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4425 = remapindex_2 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4426 = remapindex_2 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4427 = remapindex_2 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4428 = remapindex_2 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4429 = remapindex_2 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4430 = remapindex_2 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4431 = remapindex_2 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4432 = remapindex_2 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_2 = _T_4432 ? _Queue2_UInt8_31_io_deq_bits : _T_4431 ? _Queue2_UInt8_30_io_deq_bits : _T_4430 ? _Queue2_UInt8_29_io_deq_bits : _T_4429 ? _Queue2_UInt8_28_io_deq_bits : _T_4428 ? _Queue2_UInt8_27_io_deq_bits : _T_4427 ? _Queue2_UInt8_26_io_deq_bits : _T_4426 ? _Queue2_UInt8_25_io_deq_bits : _T_4425 ? _Queue2_UInt8_24_io_deq_bits : _T_4424 ? _Queue2_UInt8_23_io_deq_bits : _T_4423 ? _Queue2_UInt8_22_io_deq_bits : _T_4422 ? _Queue2_UInt8_21_io_deq_bits : _T_4421 ? _Queue2_UInt8_20_io_deq_bits : _T_4420 ? _Queue2_UInt8_19_io_deq_bits : _T_4419 ? _Queue2_UInt8_18_io_deq_bits : _T_4418 ? _Queue2_UInt8_17_io_deq_bits : _T_4417 ? _Queue2_UInt8_16_io_deq_bits : _T_4416 ? _Queue2_UInt8_15_io_deq_bits : _T_4415 ? _Queue2_UInt8_14_io_deq_bits : _T_4414 ? _Queue2_UInt8_13_io_deq_bits : _T_4413 ? _Queue2_UInt8_12_io_deq_bits : _T_4412 ? _Queue2_UInt8_11_io_deq_bits : _T_4411 ? _Queue2_UInt8_10_io_deq_bits : _T_4410 ? _Queue2_UInt8_9_io_deq_bits : _T_4409 ? _Queue2_UInt8_8_io_deq_bits : _T_4408 ? _Queue2_UInt8_7_io_deq_bits : _T_4407 ? _Queue2_UInt8_6_io_deq_bits : _T_4406 ? _Queue2_UInt8_5_io_deq_bits : _T_4405 ? _Queue2_UInt8_4_io_deq_bits : _T_4404 ? _Queue2_UInt8_3_io_deq_bits : _T_4403 ? _Queue2_UInt8_2_io_deq_bits : _T_4402 ? _Queue2_UInt8_1_io_deq_bits : _T_4401 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_2 = _T_4432 ? _Queue2_UInt8_31_io_deq_valid : _T_4431 ? _Queue2_UInt8_30_io_deq_valid : _T_4430 ? _Queue2_UInt8_29_io_deq_valid : _T_4429 ? _Queue2_UInt8_28_io_deq_valid : _T_4428 ? _Queue2_UInt8_27_io_deq_valid : _T_4427 ? _Queue2_UInt8_26_io_deq_valid : _T_4426 ? _Queue2_UInt8_25_io_deq_valid : _T_4425 ? _Queue2_UInt8_24_io_deq_valid : _T_4424 ? _Queue2_UInt8_23_io_deq_valid : _T_4423 ? _Queue2_UInt8_22_io_deq_valid : _T_4422 ? _Queue2_UInt8_21_io_deq_valid : _T_4421 ? _Queue2_UInt8_20_io_deq_valid : _T_4420 ? _Queue2_UInt8_19_io_deq_valid : _T_4419 ? _Queue2_UInt8_18_io_deq_valid : _T_4418 ? _Queue2_UInt8_17_io_deq_valid : _T_4417 ? _Queue2_UInt8_16_io_deq_valid : _T_4416 ? _Queue2_UInt8_15_io_deq_valid : _T_4415 ? _Queue2_UInt8_14_io_deq_valid : _T_4414 ? _Queue2_UInt8_13_io_deq_valid : _T_4413 ? _Queue2_UInt8_12_io_deq_valid : _T_4412 ? _Queue2_UInt8_11_io_deq_valid : _T_4411 ? _Queue2_UInt8_10_io_deq_valid : _T_4410 ? _Queue2_UInt8_9_io_deq_valid : _T_4409 ? _Queue2_UInt8_8_io_deq_valid : _T_4408 ? _Queue2_UInt8_7_io_deq_valid : _T_4407 ? _Queue2_UInt8_6_io_deq_valid : _T_4406 ? _Queue2_UInt8_5_io_deq_valid : _T_4405 ? _Queue2_UInt8_4_io_deq_valid : _T_4404 ? _Queue2_UInt8_3_io_deq_valid : _T_4403 ? _Queue2_UInt8_2_io_deq_valid : _T_4402 ? _Queue2_UInt8_1_io_deq_valid : _T_4401 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_93 = _remapindex_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_3 = _GEN_93[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4433 = remapindex_3 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4434 = remapindex_3 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4435 = remapindex_3 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4436 = remapindex_3 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4437 = remapindex_3 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4438 = remapindex_3 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4439 = remapindex_3 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4440 = remapindex_3 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4441 = remapindex_3 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4442 = remapindex_3 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4443 = remapindex_3 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4444 = remapindex_3 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4445 = remapindex_3 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4446 = remapindex_3 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4447 = remapindex_3 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4448 = remapindex_3 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4449 = remapindex_3 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4450 = remapindex_3 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4451 = remapindex_3 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4452 = remapindex_3 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4453 = remapindex_3 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4454 = remapindex_3 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4455 = remapindex_3 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4456 = remapindex_3 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4457 = remapindex_3 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4458 = remapindex_3 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4459 = remapindex_3 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4460 = remapindex_3 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4461 = remapindex_3 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4462 = remapindex_3 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4463 = remapindex_3 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4464 = remapindex_3 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_3 = _T_4464 ? _Queue2_UInt8_31_io_deq_bits : _T_4463 ? _Queue2_UInt8_30_io_deq_bits : _T_4462 ? _Queue2_UInt8_29_io_deq_bits : _T_4461 ? _Queue2_UInt8_28_io_deq_bits : _T_4460 ? _Queue2_UInt8_27_io_deq_bits : _T_4459 ? _Queue2_UInt8_26_io_deq_bits : _T_4458 ? _Queue2_UInt8_25_io_deq_bits : _T_4457 ? _Queue2_UInt8_24_io_deq_bits : _T_4456 ? _Queue2_UInt8_23_io_deq_bits : _T_4455 ? _Queue2_UInt8_22_io_deq_bits : _T_4454 ? _Queue2_UInt8_21_io_deq_bits : _T_4453 ? _Queue2_UInt8_20_io_deq_bits : _T_4452 ? _Queue2_UInt8_19_io_deq_bits : _T_4451 ? _Queue2_UInt8_18_io_deq_bits : _T_4450 ? _Queue2_UInt8_17_io_deq_bits : _T_4449 ? _Queue2_UInt8_16_io_deq_bits : _T_4448 ? _Queue2_UInt8_15_io_deq_bits : _T_4447 ? _Queue2_UInt8_14_io_deq_bits : _T_4446 ? _Queue2_UInt8_13_io_deq_bits : _T_4445 ? _Queue2_UInt8_12_io_deq_bits : _T_4444 ? _Queue2_UInt8_11_io_deq_bits : _T_4443 ? _Queue2_UInt8_10_io_deq_bits : _T_4442 ? _Queue2_UInt8_9_io_deq_bits : _T_4441 ? _Queue2_UInt8_8_io_deq_bits : _T_4440 ? _Queue2_UInt8_7_io_deq_bits : _T_4439 ? _Queue2_UInt8_6_io_deq_bits : _T_4438 ? _Queue2_UInt8_5_io_deq_bits : _T_4437 ? _Queue2_UInt8_4_io_deq_bits : _T_4436 ? _Queue2_UInt8_3_io_deq_bits : _T_4435 ? _Queue2_UInt8_2_io_deq_bits : _T_4434 ? _Queue2_UInt8_1_io_deq_bits : _T_4433 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_3 = _T_4464 ? _Queue2_UInt8_31_io_deq_valid : _T_4463 ? _Queue2_UInt8_30_io_deq_valid : _T_4462 ? _Queue2_UInt8_29_io_deq_valid : _T_4461 ? _Queue2_UInt8_28_io_deq_valid : _T_4460 ? _Queue2_UInt8_27_io_deq_valid : _T_4459 ? _Queue2_UInt8_26_io_deq_valid : _T_4458 ? _Queue2_UInt8_25_io_deq_valid : _T_4457 ? _Queue2_UInt8_24_io_deq_valid : _T_4456 ? _Queue2_UInt8_23_io_deq_valid : _T_4455 ? _Queue2_UInt8_22_io_deq_valid : _T_4454 ? _Queue2_UInt8_21_io_deq_valid : _T_4453 ? _Queue2_UInt8_20_io_deq_valid : _T_4452 ? _Queue2_UInt8_19_io_deq_valid : _T_4451 ? _Queue2_UInt8_18_io_deq_valid : _T_4450 ? _Queue2_UInt8_17_io_deq_valid : _T_4449 ? _Queue2_UInt8_16_io_deq_valid : _T_4448 ? _Queue2_UInt8_15_io_deq_valid : _T_4447 ? _Queue2_UInt8_14_io_deq_valid : _T_4446 ? _Queue2_UInt8_13_io_deq_valid : _T_4445 ? _Queue2_UInt8_12_io_deq_valid : _T_4444 ? _Queue2_UInt8_11_io_deq_valid : _T_4443 ? _Queue2_UInt8_10_io_deq_valid : _T_4442 ? _Queue2_UInt8_9_io_deq_valid : _T_4441 ? _Queue2_UInt8_8_io_deq_valid : _T_4440 ? _Queue2_UInt8_7_io_deq_valid : _T_4439 ? _Queue2_UInt8_6_io_deq_valid : _T_4438 ? _Queue2_UInt8_5_io_deq_valid : _T_4437 ? _Queue2_UInt8_4_io_deq_valid : _T_4436 ? _Queue2_UInt8_3_io_deq_valid : _T_4435 ? _Queue2_UInt8_2_io_deq_valid : _T_4434 ? _Queue2_UInt8_1_io_deq_valid : _T_4433 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_94 = _remapindex_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_4 = _GEN_94[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4465 = remapindex_4 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4466 = remapindex_4 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4467 = remapindex_4 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4468 = remapindex_4 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4469 = remapindex_4 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4470 = remapindex_4 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4471 = remapindex_4 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4472 = remapindex_4 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4473 = remapindex_4 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4474 = remapindex_4 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4475 = remapindex_4 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4476 = remapindex_4 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4477 = remapindex_4 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4478 = remapindex_4 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4479 = remapindex_4 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4480 = remapindex_4 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4481 = remapindex_4 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4482 = remapindex_4 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4483 = remapindex_4 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4484 = remapindex_4 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4485 = remapindex_4 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4486 = remapindex_4 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4487 = remapindex_4 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4488 = remapindex_4 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4489 = remapindex_4 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4490 = remapindex_4 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4491 = remapindex_4 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4492 = remapindex_4 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4493 = remapindex_4 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4494 = remapindex_4 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4495 = remapindex_4 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4496 = remapindex_4 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_4 = _T_4496 ? _Queue2_UInt8_31_io_deq_bits : _T_4495 ? _Queue2_UInt8_30_io_deq_bits : _T_4494 ? _Queue2_UInt8_29_io_deq_bits : _T_4493 ? _Queue2_UInt8_28_io_deq_bits : _T_4492 ? _Queue2_UInt8_27_io_deq_bits : _T_4491 ? _Queue2_UInt8_26_io_deq_bits : _T_4490 ? _Queue2_UInt8_25_io_deq_bits : _T_4489 ? _Queue2_UInt8_24_io_deq_bits : _T_4488 ? _Queue2_UInt8_23_io_deq_bits : _T_4487 ? _Queue2_UInt8_22_io_deq_bits : _T_4486 ? _Queue2_UInt8_21_io_deq_bits : _T_4485 ? _Queue2_UInt8_20_io_deq_bits : _T_4484 ? _Queue2_UInt8_19_io_deq_bits : _T_4483 ? _Queue2_UInt8_18_io_deq_bits : _T_4482 ? _Queue2_UInt8_17_io_deq_bits : _T_4481 ? _Queue2_UInt8_16_io_deq_bits : _T_4480 ? _Queue2_UInt8_15_io_deq_bits : _T_4479 ? _Queue2_UInt8_14_io_deq_bits : _T_4478 ? _Queue2_UInt8_13_io_deq_bits : _T_4477 ? _Queue2_UInt8_12_io_deq_bits : _T_4476 ? _Queue2_UInt8_11_io_deq_bits : _T_4475 ? _Queue2_UInt8_10_io_deq_bits : _T_4474 ? _Queue2_UInt8_9_io_deq_bits : _T_4473 ? _Queue2_UInt8_8_io_deq_bits : _T_4472 ? _Queue2_UInt8_7_io_deq_bits : _T_4471 ? _Queue2_UInt8_6_io_deq_bits : _T_4470 ? _Queue2_UInt8_5_io_deq_bits : _T_4469 ? _Queue2_UInt8_4_io_deq_bits : _T_4468 ? _Queue2_UInt8_3_io_deq_bits : _T_4467 ? _Queue2_UInt8_2_io_deq_bits : _T_4466 ? _Queue2_UInt8_1_io_deq_bits : _T_4465 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_4 = _T_4496 ? _Queue2_UInt8_31_io_deq_valid : _T_4495 ? _Queue2_UInt8_30_io_deq_valid : _T_4494 ? _Queue2_UInt8_29_io_deq_valid : _T_4493 ? _Queue2_UInt8_28_io_deq_valid : _T_4492 ? _Queue2_UInt8_27_io_deq_valid : _T_4491 ? _Queue2_UInt8_26_io_deq_valid : _T_4490 ? _Queue2_UInt8_25_io_deq_valid : _T_4489 ? _Queue2_UInt8_24_io_deq_valid : _T_4488 ? _Queue2_UInt8_23_io_deq_valid : _T_4487 ? _Queue2_UInt8_22_io_deq_valid : _T_4486 ? _Queue2_UInt8_21_io_deq_valid : _T_4485 ? _Queue2_UInt8_20_io_deq_valid : _T_4484 ? _Queue2_UInt8_19_io_deq_valid : _T_4483 ? _Queue2_UInt8_18_io_deq_valid : _T_4482 ? _Queue2_UInt8_17_io_deq_valid : _T_4481 ? _Queue2_UInt8_16_io_deq_valid : _T_4480 ? _Queue2_UInt8_15_io_deq_valid : _T_4479 ? _Queue2_UInt8_14_io_deq_valid : _T_4478 ? _Queue2_UInt8_13_io_deq_valid : _T_4477 ? _Queue2_UInt8_12_io_deq_valid : _T_4476 ? _Queue2_UInt8_11_io_deq_valid : _T_4475 ? _Queue2_UInt8_10_io_deq_valid : _T_4474 ? _Queue2_UInt8_9_io_deq_valid : _T_4473 ? _Queue2_UInt8_8_io_deq_valid : _T_4472 ? _Queue2_UInt8_7_io_deq_valid : _T_4471 ? _Queue2_UInt8_6_io_deq_valid : _T_4470 ? _Queue2_UInt8_5_io_deq_valid : _T_4469 ? _Queue2_UInt8_4_io_deq_valid : _T_4468 ? _Queue2_UInt8_3_io_deq_valid : _T_4467 ? _Queue2_UInt8_2_io_deq_valid : _T_4466 ? _Queue2_UInt8_1_io_deq_valid : _T_4465 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_95 = _remapindex_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_5 = _GEN_95[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4497 = remapindex_5 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4498 = remapindex_5 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4499 = remapindex_5 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4500 = remapindex_5 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4501 = remapindex_5 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4502 = remapindex_5 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4503 = remapindex_5 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4504 = remapindex_5 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4505 = remapindex_5 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4506 = remapindex_5 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4507 = remapindex_5 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4508 = remapindex_5 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4509 = remapindex_5 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4510 = remapindex_5 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4511 = remapindex_5 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4512 = remapindex_5 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4513 = remapindex_5 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4514 = remapindex_5 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4515 = remapindex_5 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4516 = remapindex_5 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4517 = remapindex_5 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4518 = remapindex_5 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4519 = remapindex_5 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4520 = remapindex_5 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4521 = remapindex_5 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4522 = remapindex_5 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4523 = remapindex_5 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4524 = remapindex_5 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4525 = remapindex_5 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4526 = remapindex_5 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4527 = remapindex_5 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4528 = remapindex_5 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_5 = _T_4528 ? _Queue2_UInt8_31_io_deq_bits : _T_4527 ? _Queue2_UInt8_30_io_deq_bits : _T_4526 ? _Queue2_UInt8_29_io_deq_bits : _T_4525 ? _Queue2_UInt8_28_io_deq_bits : _T_4524 ? _Queue2_UInt8_27_io_deq_bits : _T_4523 ? _Queue2_UInt8_26_io_deq_bits : _T_4522 ? _Queue2_UInt8_25_io_deq_bits : _T_4521 ? _Queue2_UInt8_24_io_deq_bits : _T_4520 ? _Queue2_UInt8_23_io_deq_bits : _T_4519 ? _Queue2_UInt8_22_io_deq_bits : _T_4518 ? _Queue2_UInt8_21_io_deq_bits : _T_4517 ? _Queue2_UInt8_20_io_deq_bits : _T_4516 ? _Queue2_UInt8_19_io_deq_bits : _T_4515 ? _Queue2_UInt8_18_io_deq_bits : _T_4514 ? _Queue2_UInt8_17_io_deq_bits : _T_4513 ? _Queue2_UInt8_16_io_deq_bits : _T_4512 ? _Queue2_UInt8_15_io_deq_bits : _T_4511 ? _Queue2_UInt8_14_io_deq_bits : _T_4510 ? _Queue2_UInt8_13_io_deq_bits : _T_4509 ? _Queue2_UInt8_12_io_deq_bits : _T_4508 ? _Queue2_UInt8_11_io_deq_bits : _T_4507 ? _Queue2_UInt8_10_io_deq_bits : _T_4506 ? _Queue2_UInt8_9_io_deq_bits : _T_4505 ? _Queue2_UInt8_8_io_deq_bits : _T_4504 ? _Queue2_UInt8_7_io_deq_bits : _T_4503 ? _Queue2_UInt8_6_io_deq_bits : _T_4502 ? _Queue2_UInt8_5_io_deq_bits : _T_4501 ? _Queue2_UInt8_4_io_deq_bits : _T_4500 ? _Queue2_UInt8_3_io_deq_bits : _T_4499 ? _Queue2_UInt8_2_io_deq_bits : _T_4498 ? _Queue2_UInt8_1_io_deq_bits : _T_4497 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_5 = _T_4528 ? _Queue2_UInt8_31_io_deq_valid : _T_4527 ? _Queue2_UInt8_30_io_deq_valid : _T_4526 ? _Queue2_UInt8_29_io_deq_valid : _T_4525 ? _Queue2_UInt8_28_io_deq_valid : _T_4524 ? _Queue2_UInt8_27_io_deq_valid : _T_4523 ? _Queue2_UInt8_26_io_deq_valid : _T_4522 ? _Queue2_UInt8_25_io_deq_valid : _T_4521 ? _Queue2_UInt8_24_io_deq_valid : _T_4520 ? _Queue2_UInt8_23_io_deq_valid : _T_4519 ? _Queue2_UInt8_22_io_deq_valid : _T_4518 ? _Queue2_UInt8_21_io_deq_valid : _T_4517 ? _Queue2_UInt8_20_io_deq_valid : _T_4516 ? _Queue2_UInt8_19_io_deq_valid : _T_4515 ? _Queue2_UInt8_18_io_deq_valid : _T_4514 ? _Queue2_UInt8_17_io_deq_valid : _T_4513 ? _Queue2_UInt8_16_io_deq_valid : _T_4512 ? _Queue2_UInt8_15_io_deq_valid : _T_4511 ? _Queue2_UInt8_14_io_deq_valid : _T_4510 ? _Queue2_UInt8_13_io_deq_valid : _T_4509 ? _Queue2_UInt8_12_io_deq_valid : _T_4508 ? _Queue2_UInt8_11_io_deq_valid : _T_4507 ? _Queue2_UInt8_10_io_deq_valid : _T_4506 ? _Queue2_UInt8_9_io_deq_valid : _T_4505 ? _Queue2_UInt8_8_io_deq_valid : _T_4504 ? _Queue2_UInt8_7_io_deq_valid : _T_4503 ? _Queue2_UInt8_6_io_deq_valid : _T_4502 ? _Queue2_UInt8_5_io_deq_valid : _T_4501 ? _Queue2_UInt8_4_io_deq_valid : _T_4500 ? _Queue2_UInt8_3_io_deq_valid : _T_4499 ? _Queue2_UInt8_2_io_deq_valid : _T_4498 ? _Queue2_UInt8_1_io_deq_valid : _T_4497 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_96 = _remapindex_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_6 = _GEN_96[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4529 = remapindex_6 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4530 = remapindex_6 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4531 = remapindex_6 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4532 = remapindex_6 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4533 = remapindex_6 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4534 = remapindex_6 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4535 = remapindex_6 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4536 = remapindex_6 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4537 = remapindex_6 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4538 = remapindex_6 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4539 = remapindex_6 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4540 = remapindex_6 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4541 = remapindex_6 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4542 = remapindex_6 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4543 = remapindex_6 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4544 = remapindex_6 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4545 = remapindex_6 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4546 = remapindex_6 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4547 = remapindex_6 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4548 = remapindex_6 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4549 = remapindex_6 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4550 = remapindex_6 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4551 = remapindex_6 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4552 = remapindex_6 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4553 = remapindex_6 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4554 = remapindex_6 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4555 = remapindex_6 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4556 = remapindex_6 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4557 = remapindex_6 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4558 = remapindex_6 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4559 = remapindex_6 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4560 = remapindex_6 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_6 = _T_4560 ? _Queue2_UInt8_31_io_deq_bits : _T_4559 ? _Queue2_UInt8_30_io_deq_bits : _T_4558 ? _Queue2_UInt8_29_io_deq_bits : _T_4557 ? _Queue2_UInt8_28_io_deq_bits : _T_4556 ? _Queue2_UInt8_27_io_deq_bits : _T_4555 ? _Queue2_UInt8_26_io_deq_bits : _T_4554 ? _Queue2_UInt8_25_io_deq_bits : _T_4553 ? _Queue2_UInt8_24_io_deq_bits : _T_4552 ? _Queue2_UInt8_23_io_deq_bits : _T_4551 ? _Queue2_UInt8_22_io_deq_bits : _T_4550 ? _Queue2_UInt8_21_io_deq_bits : _T_4549 ? _Queue2_UInt8_20_io_deq_bits : _T_4548 ? _Queue2_UInt8_19_io_deq_bits : _T_4547 ? _Queue2_UInt8_18_io_deq_bits : _T_4546 ? _Queue2_UInt8_17_io_deq_bits : _T_4545 ? _Queue2_UInt8_16_io_deq_bits : _T_4544 ? _Queue2_UInt8_15_io_deq_bits : _T_4543 ? _Queue2_UInt8_14_io_deq_bits : _T_4542 ? _Queue2_UInt8_13_io_deq_bits : _T_4541 ? _Queue2_UInt8_12_io_deq_bits : _T_4540 ? _Queue2_UInt8_11_io_deq_bits : _T_4539 ? _Queue2_UInt8_10_io_deq_bits : _T_4538 ? _Queue2_UInt8_9_io_deq_bits : _T_4537 ? _Queue2_UInt8_8_io_deq_bits : _T_4536 ? _Queue2_UInt8_7_io_deq_bits : _T_4535 ? _Queue2_UInt8_6_io_deq_bits : _T_4534 ? _Queue2_UInt8_5_io_deq_bits : _T_4533 ? _Queue2_UInt8_4_io_deq_bits : _T_4532 ? _Queue2_UInt8_3_io_deq_bits : _T_4531 ? _Queue2_UInt8_2_io_deq_bits : _T_4530 ? _Queue2_UInt8_1_io_deq_bits : _T_4529 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_6 = _T_4560 ? _Queue2_UInt8_31_io_deq_valid : _T_4559 ? _Queue2_UInt8_30_io_deq_valid : _T_4558 ? _Queue2_UInt8_29_io_deq_valid : _T_4557 ? _Queue2_UInt8_28_io_deq_valid : _T_4556 ? _Queue2_UInt8_27_io_deq_valid : _T_4555 ? _Queue2_UInt8_26_io_deq_valid : _T_4554 ? _Queue2_UInt8_25_io_deq_valid : _T_4553 ? _Queue2_UInt8_24_io_deq_valid : _T_4552 ? _Queue2_UInt8_23_io_deq_valid : _T_4551 ? _Queue2_UInt8_22_io_deq_valid : _T_4550 ? _Queue2_UInt8_21_io_deq_valid : _T_4549 ? _Queue2_UInt8_20_io_deq_valid : _T_4548 ? _Queue2_UInt8_19_io_deq_valid : _T_4547 ? _Queue2_UInt8_18_io_deq_valid : _T_4546 ? _Queue2_UInt8_17_io_deq_valid : _T_4545 ? _Queue2_UInt8_16_io_deq_valid : _T_4544 ? _Queue2_UInt8_15_io_deq_valid : _T_4543 ? _Queue2_UInt8_14_io_deq_valid : _T_4542 ? _Queue2_UInt8_13_io_deq_valid : _T_4541 ? _Queue2_UInt8_12_io_deq_valid : _T_4540 ? _Queue2_UInt8_11_io_deq_valid : _T_4539 ? _Queue2_UInt8_10_io_deq_valid : _T_4538 ? _Queue2_UInt8_9_io_deq_valid : _T_4537 ? _Queue2_UInt8_8_io_deq_valid : _T_4536 ? _Queue2_UInt8_7_io_deq_valid : _T_4535 ? _Queue2_UInt8_6_io_deq_valid : _T_4534 ? _Queue2_UInt8_5_io_deq_valid : _T_4533 ? _Queue2_UInt8_4_io_deq_valid : _T_4532 ? _Queue2_UInt8_3_io_deq_valid : _T_4531 ? _Queue2_UInt8_2_io_deq_valid : _T_4530 ? _Queue2_UInt8_1_io_deq_valid : _T_4529 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_97 = _remapindex_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_7 = _GEN_97[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4561 = remapindex_7 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4562 = remapindex_7 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4563 = remapindex_7 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4564 = remapindex_7 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4565 = remapindex_7 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4566 = remapindex_7 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4567 = remapindex_7 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4568 = remapindex_7 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4569 = remapindex_7 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4570 = remapindex_7 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4571 = remapindex_7 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4572 = remapindex_7 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4573 = remapindex_7 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4574 = remapindex_7 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4575 = remapindex_7 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4576 = remapindex_7 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4577 = remapindex_7 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4578 = remapindex_7 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4579 = remapindex_7 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4580 = remapindex_7 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4581 = remapindex_7 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4582 = remapindex_7 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4583 = remapindex_7 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4584 = remapindex_7 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4585 = remapindex_7 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4586 = remapindex_7 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4587 = remapindex_7 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4588 = remapindex_7 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4589 = remapindex_7 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4590 = remapindex_7 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4591 = remapindex_7 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4592 = remapindex_7 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_7 = _T_4592 ? _Queue2_UInt8_31_io_deq_bits : _T_4591 ? _Queue2_UInt8_30_io_deq_bits : _T_4590 ? _Queue2_UInt8_29_io_deq_bits : _T_4589 ? _Queue2_UInt8_28_io_deq_bits : _T_4588 ? _Queue2_UInt8_27_io_deq_bits : _T_4587 ? _Queue2_UInt8_26_io_deq_bits : _T_4586 ? _Queue2_UInt8_25_io_deq_bits : _T_4585 ? _Queue2_UInt8_24_io_deq_bits : _T_4584 ? _Queue2_UInt8_23_io_deq_bits : _T_4583 ? _Queue2_UInt8_22_io_deq_bits : _T_4582 ? _Queue2_UInt8_21_io_deq_bits : _T_4581 ? _Queue2_UInt8_20_io_deq_bits : _T_4580 ? _Queue2_UInt8_19_io_deq_bits : _T_4579 ? _Queue2_UInt8_18_io_deq_bits : _T_4578 ? _Queue2_UInt8_17_io_deq_bits : _T_4577 ? _Queue2_UInt8_16_io_deq_bits : _T_4576 ? _Queue2_UInt8_15_io_deq_bits : _T_4575 ? _Queue2_UInt8_14_io_deq_bits : _T_4574 ? _Queue2_UInt8_13_io_deq_bits : _T_4573 ? _Queue2_UInt8_12_io_deq_bits : _T_4572 ? _Queue2_UInt8_11_io_deq_bits : _T_4571 ? _Queue2_UInt8_10_io_deq_bits : _T_4570 ? _Queue2_UInt8_9_io_deq_bits : _T_4569 ? _Queue2_UInt8_8_io_deq_bits : _T_4568 ? _Queue2_UInt8_7_io_deq_bits : _T_4567 ? _Queue2_UInt8_6_io_deq_bits : _T_4566 ? _Queue2_UInt8_5_io_deq_bits : _T_4565 ? _Queue2_UInt8_4_io_deq_bits : _T_4564 ? _Queue2_UInt8_3_io_deq_bits : _T_4563 ? _Queue2_UInt8_2_io_deq_bits : _T_4562 ? _Queue2_UInt8_1_io_deq_bits : _T_4561 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_7 = _T_4592 ? _Queue2_UInt8_31_io_deq_valid : _T_4591 ? _Queue2_UInt8_30_io_deq_valid : _T_4590 ? _Queue2_UInt8_29_io_deq_valid : _T_4589 ? _Queue2_UInt8_28_io_deq_valid : _T_4588 ? _Queue2_UInt8_27_io_deq_valid : _T_4587 ? _Queue2_UInt8_26_io_deq_valid : _T_4586 ? _Queue2_UInt8_25_io_deq_valid : _T_4585 ? _Queue2_UInt8_24_io_deq_valid : _T_4584 ? _Queue2_UInt8_23_io_deq_valid : _T_4583 ? _Queue2_UInt8_22_io_deq_valid : _T_4582 ? _Queue2_UInt8_21_io_deq_valid : _T_4581 ? _Queue2_UInt8_20_io_deq_valid : _T_4580 ? _Queue2_UInt8_19_io_deq_valid : _T_4579 ? _Queue2_UInt8_18_io_deq_valid : _T_4578 ? _Queue2_UInt8_17_io_deq_valid : _T_4577 ? _Queue2_UInt8_16_io_deq_valid : _T_4576 ? _Queue2_UInt8_15_io_deq_valid : _T_4575 ? _Queue2_UInt8_14_io_deq_valid : _T_4574 ? _Queue2_UInt8_13_io_deq_valid : _T_4573 ? _Queue2_UInt8_12_io_deq_valid : _T_4572 ? _Queue2_UInt8_11_io_deq_valid : _T_4571 ? _Queue2_UInt8_10_io_deq_valid : _T_4570 ? _Queue2_UInt8_9_io_deq_valid : _T_4569 ? _Queue2_UInt8_8_io_deq_valid : _T_4568 ? _Queue2_UInt8_7_io_deq_valid : _T_4567 ? _Queue2_UInt8_6_io_deq_valid : _T_4566 ? _Queue2_UInt8_5_io_deq_valid : _T_4565 ? _Queue2_UInt8_4_io_deq_valid : _T_4564 ? _Queue2_UInt8_3_io_deq_valid : _T_4563 ? _Queue2_UInt8_2_io_deq_valid : _T_4562 ? _Queue2_UInt8_1_io_deq_valid : _T_4561 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_98 = _remapindex_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_8 = _GEN_98[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4593 = remapindex_8 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4594 = remapindex_8 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4595 = remapindex_8 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4596 = remapindex_8 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4597 = remapindex_8 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4598 = remapindex_8 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4599 = remapindex_8 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4600 = remapindex_8 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4601 = remapindex_8 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4602 = remapindex_8 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4603 = remapindex_8 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4604 = remapindex_8 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4605 = remapindex_8 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4606 = remapindex_8 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4607 = remapindex_8 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4608 = remapindex_8 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4609 = remapindex_8 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4610 = remapindex_8 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4611 = remapindex_8 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4612 = remapindex_8 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4613 = remapindex_8 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4614 = remapindex_8 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4615 = remapindex_8 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4616 = remapindex_8 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4617 = remapindex_8 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4618 = remapindex_8 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4619 = remapindex_8 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4620 = remapindex_8 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4621 = remapindex_8 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4622 = remapindex_8 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4623 = remapindex_8 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4624 = remapindex_8 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_8 = _T_4624 ? _Queue2_UInt8_31_io_deq_bits : _T_4623 ? _Queue2_UInt8_30_io_deq_bits : _T_4622 ? _Queue2_UInt8_29_io_deq_bits : _T_4621 ? _Queue2_UInt8_28_io_deq_bits : _T_4620 ? _Queue2_UInt8_27_io_deq_bits : _T_4619 ? _Queue2_UInt8_26_io_deq_bits : _T_4618 ? _Queue2_UInt8_25_io_deq_bits : _T_4617 ? _Queue2_UInt8_24_io_deq_bits : _T_4616 ? _Queue2_UInt8_23_io_deq_bits : _T_4615 ? _Queue2_UInt8_22_io_deq_bits : _T_4614 ? _Queue2_UInt8_21_io_deq_bits : _T_4613 ? _Queue2_UInt8_20_io_deq_bits : _T_4612 ? _Queue2_UInt8_19_io_deq_bits : _T_4611 ? _Queue2_UInt8_18_io_deq_bits : _T_4610 ? _Queue2_UInt8_17_io_deq_bits : _T_4609 ? _Queue2_UInt8_16_io_deq_bits : _T_4608 ? _Queue2_UInt8_15_io_deq_bits : _T_4607 ? _Queue2_UInt8_14_io_deq_bits : _T_4606 ? _Queue2_UInt8_13_io_deq_bits : _T_4605 ? _Queue2_UInt8_12_io_deq_bits : _T_4604 ? _Queue2_UInt8_11_io_deq_bits : _T_4603 ? _Queue2_UInt8_10_io_deq_bits : _T_4602 ? _Queue2_UInt8_9_io_deq_bits : _T_4601 ? _Queue2_UInt8_8_io_deq_bits : _T_4600 ? _Queue2_UInt8_7_io_deq_bits : _T_4599 ? _Queue2_UInt8_6_io_deq_bits : _T_4598 ? _Queue2_UInt8_5_io_deq_bits : _T_4597 ? _Queue2_UInt8_4_io_deq_bits : _T_4596 ? _Queue2_UInt8_3_io_deq_bits : _T_4595 ? _Queue2_UInt8_2_io_deq_bits : _T_4594 ? _Queue2_UInt8_1_io_deq_bits : _T_4593 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_8 = _T_4624 ? _Queue2_UInt8_31_io_deq_valid : _T_4623 ? _Queue2_UInt8_30_io_deq_valid : _T_4622 ? _Queue2_UInt8_29_io_deq_valid : _T_4621 ? _Queue2_UInt8_28_io_deq_valid : _T_4620 ? _Queue2_UInt8_27_io_deq_valid : _T_4619 ? _Queue2_UInt8_26_io_deq_valid : _T_4618 ? _Queue2_UInt8_25_io_deq_valid : _T_4617 ? _Queue2_UInt8_24_io_deq_valid : _T_4616 ? _Queue2_UInt8_23_io_deq_valid : _T_4615 ? _Queue2_UInt8_22_io_deq_valid : _T_4614 ? _Queue2_UInt8_21_io_deq_valid : _T_4613 ? _Queue2_UInt8_20_io_deq_valid : _T_4612 ? _Queue2_UInt8_19_io_deq_valid : _T_4611 ? _Queue2_UInt8_18_io_deq_valid : _T_4610 ? _Queue2_UInt8_17_io_deq_valid : _T_4609 ? _Queue2_UInt8_16_io_deq_valid : _T_4608 ? _Queue2_UInt8_15_io_deq_valid : _T_4607 ? _Queue2_UInt8_14_io_deq_valid : _T_4606 ? _Queue2_UInt8_13_io_deq_valid : _T_4605 ? _Queue2_UInt8_12_io_deq_valid : _T_4604 ? _Queue2_UInt8_11_io_deq_valid : _T_4603 ? _Queue2_UInt8_10_io_deq_valid : _T_4602 ? _Queue2_UInt8_9_io_deq_valid : _T_4601 ? _Queue2_UInt8_8_io_deq_valid : _T_4600 ? _Queue2_UInt8_7_io_deq_valid : _T_4599 ? _Queue2_UInt8_6_io_deq_valid : _T_4598 ? _Queue2_UInt8_5_io_deq_valid : _T_4597 ? _Queue2_UInt8_4_io_deq_valid : _T_4596 ? _Queue2_UInt8_3_io_deq_valid : _T_4595 ? _Queue2_UInt8_2_io_deq_valid : _T_4594 ? _Queue2_UInt8_1_io_deq_valid : _T_4593 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_99 = _remapindex_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_9 = _GEN_99[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4625 = remapindex_9 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4626 = remapindex_9 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4627 = remapindex_9 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4628 = remapindex_9 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4629 = remapindex_9 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4630 = remapindex_9 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4631 = remapindex_9 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4632 = remapindex_9 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4633 = remapindex_9 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4634 = remapindex_9 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4635 = remapindex_9 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4636 = remapindex_9 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4637 = remapindex_9 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4638 = remapindex_9 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4639 = remapindex_9 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4640 = remapindex_9 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4641 = remapindex_9 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4642 = remapindex_9 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4643 = remapindex_9 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4644 = remapindex_9 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4645 = remapindex_9 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4646 = remapindex_9 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4647 = remapindex_9 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4648 = remapindex_9 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4649 = remapindex_9 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4650 = remapindex_9 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4651 = remapindex_9 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4652 = remapindex_9 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4653 = remapindex_9 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4654 = remapindex_9 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4655 = remapindex_9 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4656 = remapindex_9 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_9 = _T_4656 ? _Queue2_UInt8_31_io_deq_bits : _T_4655 ? _Queue2_UInt8_30_io_deq_bits : _T_4654 ? _Queue2_UInt8_29_io_deq_bits : _T_4653 ? _Queue2_UInt8_28_io_deq_bits : _T_4652 ? _Queue2_UInt8_27_io_deq_bits : _T_4651 ? _Queue2_UInt8_26_io_deq_bits : _T_4650 ? _Queue2_UInt8_25_io_deq_bits : _T_4649 ? _Queue2_UInt8_24_io_deq_bits : _T_4648 ? _Queue2_UInt8_23_io_deq_bits : _T_4647 ? _Queue2_UInt8_22_io_deq_bits : _T_4646 ? _Queue2_UInt8_21_io_deq_bits : _T_4645 ? _Queue2_UInt8_20_io_deq_bits : _T_4644 ? _Queue2_UInt8_19_io_deq_bits : _T_4643 ? _Queue2_UInt8_18_io_deq_bits : _T_4642 ? _Queue2_UInt8_17_io_deq_bits : _T_4641 ? _Queue2_UInt8_16_io_deq_bits : _T_4640 ? _Queue2_UInt8_15_io_deq_bits : _T_4639 ? _Queue2_UInt8_14_io_deq_bits : _T_4638 ? _Queue2_UInt8_13_io_deq_bits : _T_4637 ? _Queue2_UInt8_12_io_deq_bits : _T_4636 ? _Queue2_UInt8_11_io_deq_bits : _T_4635 ? _Queue2_UInt8_10_io_deq_bits : _T_4634 ? _Queue2_UInt8_9_io_deq_bits : _T_4633 ? _Queue2_UInt8_8_io_deq_bits : _T_4632 ? _Queue2_UInt8_7_io_deq_bits : _T_4631 ? _Queue2_UInt8_6_io_deq_bits : _T_4630 ? _Queue2_UInt8_5_io_deq_bits : _T_4629 ? _Queue2_UInt8_4_io_deq_bits : _T_4628 ? _Queue2_UInt8_3_io_deq_bits : _T_4627 ? _Queue2_UInt8_2_io_deq_bits : _T_4626 ? _Queue2_UInt8_1_io_deq_bits : _T_4625 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_9 = _T_4656 ? _Queue2_UInt8_31_io_deq_valid : _T_4655 ? _Queue2_UInt8_30_io_deq_valid : _T_4654 ? _Queue2_UInt8_29_io_deq_valid : _T_4653 ? _Queue2_UInt8_28_io_deq_valid : _T_4652 ? _Queue2_UInt8_27_io_deq_valid : _T_4651 ? _Queue2_UInt8_26_io_deq_valid : _T_4650 ? _Queue2_UInt8_25_io_deq_valid : _T_4649 ? _Queue2_UInt8_24_io_deq_valid : _T_4648 ? _Queue2_UInt8_23_io_deq_valid : _T_4647 ? _Queue2_UInt8_22_io_deq_valid : _T_4646 ? _Queue2_UInt8_21_io_deq_valid : _T_4645 ? _Queue2_UInt8_20_io_deq_valid : _T_4644 ? _Queue2_UInt8_19_io_deq_valid : _T_4643 ? _Queue2_UInt8_18_io_deq_valid : _T_4642 ? _Queue2_UInt8_17_io_deq_valid : _T_4641 ? _Queue2_UInt8_16_io_deq_valid : _T_4640 ? _Queue2_UInt8_15_io_deq_valid : _T_4639 ? _Queue2_UInt8_14_io_deq_valid : _T_4638 ? _Queue2_UInt8_13_io_deq_valid : _T_4637 ? _Queue2_UInt8_12_io_deq_valid : _T_4636 ? _Queue2_UInt8_11_io_deq_valid : _T_4635 ? _Queue2_UInt8_10_io_deq_valid : _T_4634 ? _Queue2_UInt8_9_io_deq_valid : _T_4633 ? _Queue2_UInt8_8_io_deq_valid : _T_4632 ? _Queue2_UInt8_7_io_deq_valid : _T_4631 ? _Queue2_UInt8_6_io_deq_valid : _T_4630 ? _Queue2_UInt8_5_io_deq_valid : _T_4629 ? _Queue2_UInt8_4_io_deq_valid : _T_4628 ? _Queue2_UInt8_3_io_deq_valid : _T_4627 ? _Queue2_UInt8_2_io_deq_valid : _T_4626 ? _Queue2_UInt8_1_io_deq_valid : _T_4625 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_100 = _remapindex_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_10 = _GEN_100[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4657 = remapindex_10 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4658 = remapindex_10 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4659 = remapindex_10 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4660 = remapindex_10 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4661 = remapindex_10 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4662 = remapindex_10 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4663 = remapindex_10 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4664 = remapindex_10 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4665 = remapindex_10 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4666 = remapindex_10 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4667 = remapindex_10 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4668 = remapindex_10 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4669 = remapindex_10 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4670 = remapindex_10 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4671 = remapindex_10 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4672 = remapindex_10 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4673 = remapindex_10 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4674 = remapindex_10 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4675 = remapindex_10 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4676 = remapindex_10 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4677 = remapindex_10 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4678 = remapindex_10 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4679 = remapindex_10 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4680 = remapindex_10 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4681 = remapindex_10 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4682 = remapindex_10 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4683 = remapindex_10 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4684 = remapindex_10 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4685 = remapindex_10 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4686 = remapindex_10 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4687 = remapindex_10 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4688 = remapindex_10 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_10 = _T_4688 ? _Queue2_UInt8_31_io_deq_bits : _T_4687 ? _Queue2_UInt8_30_io_deq_bits : _T_4686 ? _Queue2_UInt8_29_io_deq_bits : _T_4685 ? _Queue2_UInt8_28_io_deq_bits : _T_4684 ? _Queue2_UInt8_27_io_deq_bits : _T_4683 ? _Queue2_UInt8_26_io_deq_bits : _T_4682 ? _Queue2_UInt8_25_io_deq_bits : _T_4681 ? _Queue2_UInt8_24_io_deq_bits : _T_4680 ? _Queue2_UInt8_23_io_deq_bits : _T_4679 ? _Queue2_UInt8_22_io_deq_bits : _T_4678 ? _Queue2_UInt8_21_io_deq_bits : _T_4677 ? _Queue2_UInt8_20_io_deq_bits : _T_4676 ? _Queue2_UInt8_19_io_deq_bits : _T_4675 ? _Queue2_UInt8_18_io_deq_bits : _T_4674 ? _Queue2_UInt8_17_io_deq_bits : _T_4673 ? _Queue2_UInt8_16_io_deq_bits : _T_4672 ? _Queue2_UInt8_15_io_deq_bits : _T_4671 ? _Queue2_UInt8_14_io_deq_bits : _T_4670 ? _Queue2_UInt8_13_io_deq_bits : _T_4669 ? _Queue2_UInt8_12_io_deq_bits : _T_4668 ? _Queue2_UInt8_11_io_deq_bits : _T_4667 ? _Queue2_UInt8_10_io_deq_bits : _T_4666 ? _Queue2_UInt8_9_io_deq_bits : _T_4665 ? _Queue2_UInt8_8_io_deq_bits : _T_4664 ? _Queue2_UInt8_7_io_deq_bits : _T_4663 ? _Queue2_UInt8_6_io_deq_bits : _T_4662 ? _Queue2_UInt8_5_io_deq_bits : _T_4661 ? _Queue2_UInt8_4_io_deq_bits : _T_4660 ? _Queue2_UInt8_3_io_deq_bits : _T_4659 ? _Queue2_UInt8_2_io_deq_bits : _T_4658 ? _Queue2_UInt8_1_io_deq_bits : _T_4657 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_10 = _T_4688 ? _Queue2_UInt8_31_io_deq_valid : _T_4687 ? _Queue2_UInt8_30_io_deq_valid : _T_4686 ? _Queue2_UInt8_29_io_deq_valid : _T_4685 ? _Queue2_UInt8_28_io_deq_valid : _T_4684 ? _Queue2_UInt8_27_io_deq_valid : _T_4683 ? _Queue2_UInt8_26_io_deq_valid : _T_4682 ? _Queue2_UInt8_25_io_deq_valid : _T_4681 ? _Queue2_UInt8_24_io_deq_valid : _T_4680 ? _Queue2_UInt8_23_io_deq_valid : _T_4679 ? _Queue2_UInt8_22_io_deq_valid : _T_4678 ? _Queue2_UInt8_21_io_deq_valid : _T_4677 ? _Queue2_UInt8_20_io_deq_valid : _T_4676 ? _Queue2_UInt8_19_io_deq_valid : _T_4675 ? _Queue2_UInt8_18_io_deq_valid : _T_4674 ? _Queue2_UInt8_17_io_deq_valid : _T_4673 ? _Queue2_UInt8_16_io_deq_valid : _T_4672 ? _Queue2_UInt8_15_io_deq_valid : _T_4671 ? _Queue2_UInt8_14_io_deq_valid : _T_4670 ? _Queue2_UInt8_13_io_deq_valid : _T_4669 ? _Queue2_UInt8_12_io_deq_valid : _T_4668 ? _Queue2_UInt8_11_io_deq_valid : _T_4667 ? _Queue2_UInt8_10_io_deq_valid : _T_4666 ? _Queue2_UInt8_9_io_deq_valid : _T_4665 ? _Queue2_UInt8_8_io_deq_valid : _T_4664 ? _Queue2_UInt8_7_io_deq_valid : _T_4663 ? _Queue2_UInt8_6_io_deq_valid : _T_4662 ? _Queue2_UInt8_5_io_deq_valid : _T_4661 ? _Queue2_UInt8_4_io_deq_valid : _T_4660 ? _Queue2_UInt8_3_io_deq_valid : _T_4659 ? _Queue2_UInt8_2_io_deq_valid : _T_4658 ? _Queue2_UInt8_1_io_deq_valid : _T_4657 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_101 = _remapindex_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_11 = _GEN_101[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4689 = remapindex_11 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4690 = remapindex_11 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4691 = remapindex_11 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4692 = remapindex_11 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4693 = remapindex_11 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4694 = remapindex_11 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4695 = remapindex_11 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4696 = remapindex_11 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4697 = remapindex_11 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4698 = remapindex_11 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4699 = remapindex_11 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4700 = remapindex_11 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4701 = remapindex_11 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4702 = remapindex_11 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4703 = remapindex_11 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4704 = remapindex_11 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4705 = remapindex_11 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4706 = remapindex_11 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4707 = remapindex_11 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4708 = remapindex_11 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4709 = remapindex_11 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4710 = remapindex_11 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4711 = remapindex_11 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4712 = remapindex_11 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4713 = remapindex_11 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4714 = remapindex_11 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4715 = remapindex_11 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4716 = remapindex_11 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4717 = remapindex_11 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4718 = remapindex_11 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4719 = remapindex_11 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4720 = remapindex_11 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_11 = _T_4720 ? _Queue2_UInt8_31_io_deq_bits : _T_4719 ? _Queue2_UInt8_30_io_deq_bits : _T_4718 ? _Queue2_UInt8_29_io_deq_bits : _T_4717 ? _Queue2_UInt8_28_io_deq_bits : _T_4716 ? _Queue2_UInt8_27_io_deq_bits : _T_4715 ? _Queue2_UInt8_26_io_deq_bits : _T_4714 ? _Queue2_UInt8_25_io_deq_bits : _T_4713 ? _Queue2_UInt8_24_io_deq_bits : _T_4712 ? _Queue2_UInt8_23_io_deq_bits : _T_4711 ? _Queue2_UInt8_22_io_deq_bits : _T_4710 ? _Queue2_UInt8_21_io_deq_bits : _T_4709 ? _Queue2_UInt8_20_io_deq_bits : _T_4708 ? _Queue2_UInt8_19_io_deq_bits : _T_4707 ? _Queue2_UInt8_18_io_deq_bits : _T_4706 ? _Queue2_UInt8_17_io_deq_bits : _T_4705 ? _Queue2_UInt8_16_io_deq_bits : _T_4704 ? _Queue2_UInt8_15_io_deq_bits : _T_4703 ? _Queue2_UInt8_14_io_deq_bits : _T_4702 ? _Queue2_UInt8_13_io_deq_bits : _T_4701 ? _Queue2_UInt8_12_io_deq_bits : _T_4700 ? _Queue2_UInt8_11_io_deq_bits : _T_4699 ? _Queue2_UInt8_10_io_deq_bits : _T_4698 ? _Queue2_UInt8_9_io_deq_bits : _T_4697 ? _Queue2_UInt8_8_io_deq_bits : _T_4696 ? _Queue2_UInt8_7_io_deq_bits : _T_4695 ? _Queue2_UInt8_6_io_deq_bits : _T_4694 ? _Queue2_UInt8_5_io_deq_bits : _T_4693 ? _Queue2_UInt8_4_io_deq_bits : _T_4692 ? _Queue2_UInt8_3_io_deq_bits : _T_4691 ? _Queue2_UInt8_2_io_deq_bits : _T_4690 ? _Queue2_UInt8_1_io_deq_bits : _T_4689 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_11 = _T_4720 ? _Queue2_UInt8_31_io_deq_valid : _T_4719 ? _Queue2_UInt8_30_io_deq_valid : _T_4718 ? _Queue2_UInt8_29_io_deq_valid : _T_4717 ? _Queue2_UInt8_28_io_deq_valid : _T_4716 ? _Queue2_UInt8_27_io_deq_valid : _T_4715 ? _Queue2_UInt8_26_io_deq_valid : _T_4714 ? _Queue2_UInt8_25_io_deq_valid : _T_4713 ? _Queue2_UInt8_24_io_deq_valid : _T_4712 ? _Queue2_UInt8_23_io_deq_valid : _T_4711 ? _Queue2_UInt8_22_io_deq_valid : _T_4710 ? _Queue2_UInt8_21_io_deq_valid : _T_4709 ? _Queue2_UInt8_20_io_deq_valid : _T_4708 ? _Queue2_UInt8_19_io_deq_valid : _T_4707 ? _Queue2_UInt8_18_io_deq_valid : _T_4706 ? _Queue2_UInt8_17_io_deq_valid : _T_4705 ? _Queue2_UInt8_16_io_deq_valid : _T_4704 ? _Queue2_UInt8_15_io_deq_valid : _T_4703 ? _Queue2_UInt8_14_io_deq_valid : _T_4702 ? _Queue2_UInt8_13_io_deq_valid : _T_4701 ? _Queue2_UInt8_12_io_deq_valid : _T_4700 ? _Queue2_UInt8_11_io_deq_valid : _T_4699 ? _Queue2_UInt8_10_io_deq_valid : _T_4698 ? _Queue2_UInt8_9_io_deq_valid : _T_4697 ? _Queue2_UInt8_8_io_deq_valid : _T_4696 ? _Queue2_UInt8_7_io_deq_valid : _T_4695 ? _Queue2_UInt8_6_io_deq_valid : _T_4694 ? _Queue2_UInt8_5_io_deq_valid : _T_4693 ? _Queue2_UInt8_4_io_deq_valid : _T_4692 ? _Queue2_UInt8_3_io_deq_valid : _T_4691 ? _Queue2_UInt8_2_io_deq_valid : _T_4690 ? _Queue2_UInt8_1_io_deq_valid : _T_4689 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_102 = _remapindex_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_12 = _GEN_102[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4721 = remapindex_12 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4722 = remapindex_12 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4723 = remapindex_12 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4724 = remapindex_12 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4725 = remapindex_12 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4726 = remapindex_12 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4727 = remapindex_12 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4728 = remapindex_12 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4729 = remapindex_12 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4730 = remapindex_12 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4731 = remapindex_12 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4732 = remapindex_12 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4733 = remapindex_12 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4734 = remapindex_12 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4735 = remapindex_12 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4736 = remapindex_12 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4737 = remapindex_12 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4738 = remapindex_12 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4739 = remapindex_12 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4740 = remapindex_12 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4741 = remapindex_12 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4742 = remapindex_12 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4743 = remapindex_12 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4744 = remapindex_12 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4745 = remapindex_12 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4746 = remapindex_12 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4747 = remapindex_12 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4748 = remapindex_12 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4749 = remapindex_12 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4750 = remapindex_12 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4751 = remapindex_12 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4752 = remapindex_12 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_12 = _T_4752 ? _Queue2_UInt8_31_io_deq_bits : _T_4751 ? _Queue2_UInt8_30_io_deq_bits : _T_4750 ? _Queue2_UInt8_29_io_deq_bits : _T_4749 ? _Queue2_UInt8_28_io_deq_bits : _T_4748 ? _Queue2_UInt8_27_io_deq_bits : _T_4747 ? _Queue2_UInt8_26_io_deq_bits : _T_4746 ? _Queue2_UInt8_25_io_deq_bits : _T_4745 ? _Queue2_UInt8_24_io_deq_bits : _T_4744 ? _Queue2_UInt8_23_io_deq_bits : _T_4743 ? _Queue2_UInt8_22_io_deq_bits : _T_4742 ? _Queue2_UInt8_21_io_deq_bits : _T_4741 ? _Queue2_UInt8_20_io_deq_bits : _T_4740 ? _Queue2_UInt8_19_io_deq_bits : _T_4739 ? _Queue2_UInt8_18_io_deq_bits : _T_4738 ? _Queue2_UInt8_17_io_deq_bits : _T_4737 ? _Queue2_UInt8_16_io_deq_bits : _T_4736 ? _Queue2_UInt8_15_io_deq_bits : _T_4735 ? _Queue2_UInt8_14_io_deq_bits : _T_4734 ? _Queue2_UInt8_13_io_deq_bits : _T_4733 ? _Queue2_UInt8_12_io_deq_bits : _T_4732 ? _Queue2_UInt8_11_io_deq_bits : _T_4731 ? _Queue2_UInt8_10_io_deq_bits : _T_4730 ? _Queue2_UInt8_9_io_deq_bits : _T_4729 ? _Queue2_UInt8_8_io_deq_bits : _T_4728 ? _Queue2_UInt8_7_io_deq_bits : _T_4727 ? _Queue2_UInt8_6_io_deq_bits : _T_4726 ? _Queue2_UInt8_5_io_deq_bits : _T_4725 ? _Queue2_UInt8_4_io_deq_bits : _T_4724 ? _Queue2_UInt8_3_io_deq_bits : _T_4723 ? _Queue2_UInt8_2_io_deq_bits : _T_4722 ? _Queue2_UInt8_1_io_deq_bits : _T_4721 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_12 = _T_4752 ? _Queue2_UInt8_31_io_deq_valid : _T_4751 ? _Queue2_UInt8_30_io_deq_valid : _T_4750 ? _Queue2_UInt8_29_io_deq_valid : _T_4749 ? _Queue2_UInt8_28_io_deq_valid : _T_4748 ? _Queue2_UInt8_27_io_deq_valid : _T_4747 ? _Queue2_UInt8_26_io_deq_valid : _T_4746 ? _Queue2_UInt8_25_io_deq_valid : _T_4745 ? _Queue2_UInt8_24_io_deq_valid : _T_4744 ? _Queue2_UInt8_23_io_deq_valid : _T_4743 ? _Queue2_UInt8_22_io_deq_valid : _T_4742 ? _Queue2_UInt8_21_io_deq_valid : _T_4741 ? _Queue2_UInt8_20_io_deq_valid : _T_4740 ? _Queue2_UInt8_19_io_deq_valid : _T_4739 ? _Queue2_UInt8_18_io_deq_valid : _T_4738 ? _Queue2_UInt8_17_io_deq_valid : _T_4737 ? _Queue2_UInt8_16_io_deq_valid : _T_4736 ? _Queue2_UInt8_15_io_deq_valid : _T_4735 ? _Queue2_UInt8_14_io_deq_valid : _T_4734 ? _Queue2_UInt8_13_io_deq_valid : _T_4733 ? _Queue2_UInt8_12_io_deq_valid : _T_4732 ? _Queue2_UInt8_11_io_deq_valid : _T_4731 ? _Queue2_UInt8_10_io_deq_valid : _T_4730 ? _Queue2_UInt8_9_io_deq_valid : _T_4729 ? _Queue2_UInt8_8_io_deq_valid : _T_4728 ? _Queue2_UInt8_7_io_deq_valid : _T_4727 ? _Queue2_UInt8_6_io_deq_valid : _T_4726 ? _Queue2_UInt8_5_io_deq_valid : _T_4725 ? _Queue2_UInt8_4_io_deq_valid : _T_4724 ? _Queue2_UInt8_3_io_deq_valid : _T_4723 ? _Queue2_UInt8_2_io_deq_valid : _T_4722 ? _Queue2_UInt8_1_io_deq_valid : _T_4721 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_103 = _remapindex_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_13 = _GEN_103[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4753 = remapindex_13 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4754 = remapindex_13 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4755 = remapindex_13 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4756 = remapindex_13 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4757 = remapindex_13 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4758 = remapindex_13 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4759 = remapindex_13 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4760 = remapindex_13 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4761 = remapindex_13 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4762 = remapindex_13 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4763 = remapindex_13 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4764 = remapindex_13 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4765 = remapindex_13 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4766 = remapindex_13 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4767 = remapindex_13 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4768 = remapindex_13 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4769 = remapindex_13 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4770 = remapindex_13 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4771 = remapindex_13 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4772 = remapindex_13 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4773 = remapindex_13 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4774 = remapindex_13 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4775 = remapindex_13 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4776 = remapindex_13 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4777 = remapindex_13 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4778 = remapindex_13 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4779 = remapindex_13 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4780 = remapindex_13 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4781 = remapindex_13 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4782 = remapindex_13 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4783 = remapindex_13 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4784 = remapindex_13 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_13 = _T_4784 ? _Queue2_UInt8_31_io_deq_bits : _T_4783 ? _Queue2_UInt8_30_io_deq_bits : _T_4782 ? _Queue2_UInt8_29_io_deq_bits : _T_4781 ? _Queue2_UInt8_28_io_deq_bits : _T_4780 ? _Queue2_UInt8_27_io_deq_bits : _T_4779 ? _Queue2_UInt8_26_io_deq_bits : _T_4778 ? _Queue2_UInt8_25_io_deq_bits : _T_4777 ? _Queue2_UInt8_24_io_deq_bits : _T_4776 ? _Queue2_UInt8_23_io_deq_bits : _T_4775 ? _Queue2_UInt8_22_io_deq_bits : _T_4774 ? _Queue2_UInt8_21_io_deq_bits : _T_4773 ? _Queue2_UInt8_20_io_deq_bits : _T_4772 ? _Queue2_UInt8_19_io_deq_bits : _T_4771 ? _Queue2_UInt8_18_io_deq_bits : _T_4770 ? _Queue2_UInt8_17_io_deq_bits : _T_4769 ? _Queue2_UInt8_16_io_deq_bits : _T_4768 ? _Queue2_UInt8_15_io_deq_bits : _T_4767 ? _Queue2_UInt8_14_io_deq_bits : _T_4766 ? _Queue2_UInt8_13_io_deq_bits : _T_4765 ? _Queue2_UInt8_12_io_deq_bits : _T_4764 ? _Queue2_UInt8_11_io_deq_bits : _T_4763 ? _Queue2_UInt8_10_io_deq_bits : _T_4762 ? _Queue2_UInt8_9_io_deq_bits : _T_4761 ? _Queue2_UInt8_8_io_deq_bits : _T_4760 ? _Queue2_UInt8_7_io_deq_bits : _T_4759 ? _Queue2_UInt8_6_io_deq_bits : _T_4758 ? _Queue2_UInt8_5_io_deq_bits : _T_4757 ? _Queue2_UInt8_4_io_deq_bits : _T_4756 ? _Queue2_UInt8_3_io_deq_bits : _T_4755 ? _Queue2_UInt8_2_io_deq_bits : _T_4754 ? _Queue2_UInt8_1_io_deq_bits : _T_4753 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_13 = _T_4784 ? _Queue2_UInt8_31_io_deq_valid : _T_4783 ? _Queue2_UInt8_30_io_deq_valid : _T_4782 ? _Queue2_UInt8_29_io_deq_valid : _T_4781 ? _Queue2_UInt8_28_io_deq_valid : _T_4780 ? _Queue2_UInt8_27_io_deq_valid : _T_4779 ? _Queue2_UInt8_26_io_deq_valid : _T_4778 ? _Queue2_UInt8_25_io_deq_valid : _T_4777 ? _Queue2_UInt8_24_io_deq_valid : _T_4776 ? _Queue2_UInt8_23_io_deq_valid : _T_4775 ? _Queue2_UInt8_22_io_deq_valid : _T_4774 ? _Queue2_UInt8_21_io_deq_valid : _T_4773 ? _Queue2_UInt8_20_io_deq_valid : _T_4772 ? _Queue2_UInt8_19_io_deq_valid : _T_4771 ? _Queue2_UInt8_18_io_deq_valid : _T_4770 ? _Queue2_UInt8_17_io_deq_valid : _T_4769 ? _Queue2_UInt8_16_io_deq_valid : _T_4768 ? _Queue2_UInt8_15_io_deq_valid : _T_4767 ? _Queue2_UInt8_14_io_deq_valid : _T_4766 ? _Queue2_UInt8_13_io_deq_valid : _T_4765 ? _Queue2_UInt8_12_io_deq_valid : _T_4764 ? _Queue2_UInt8_11_io_deq_valid : _T_4763 ? _Queue2_UInt8_10_io_deq_valid : _T_4762 ? _Queue2_UInt8_9_io_deq_valid : _T_4761 ? _Queue2_UInt8_8_io_deq_valid : _T_4760 ? _Queue2_UInt8_7_io_deq_valid : _T_4759 ? _Queue2_UInt8_6_io_deq_valid : _T_4758 ? _Queue2_UInt8_5_io_deq_valid : _T_4757 ? _Queue2_UInt8_4_io_deq_valid : _T_4756 ? _Queue2_UInt8_3_io_deq_valid : _T_4755 ? _Queue2_UInt8_2_io_deq_valid : _T_4754 ? _Queue2_UInt8_1_io_deq_valid : _T_4753 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_104 = _remapindex_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_14 = _GEN_104[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4785 = remapindex_14 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4786 = remapindex_14 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4787 = remapindex_14 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4788 = remapindex_14 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4789 = remapindex_14 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4790 = remapindex_14 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4791 = remapindex_14 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4792 = remapindex_14 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4793 = remapindex_14 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4794 = remapindex_14 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4795 = remapindex_14 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4796 = remapindex_14 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4797 = remapindex_14 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4798 = remapindex_14 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4799 = remapindex_14 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4800 = remapindex_14 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4801 = remapindex_14 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4802 = remapindex_14 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4803 = remapindex_14 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4804 = remapindex_14 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4805 = remapindex_14 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4806 = remapindex_14 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4807 = remapindex_14 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4808 = remapindex_14 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4809 = remapindex_14 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4810 = remapindex_14 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4811 = remapindex_14 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4812 = remapindex_14 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4813 = remapindex_14 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4814 = remapindex_14 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4815 = remapindex_14 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4816 = remapindex_14 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_14 = _T_4816 ? _Queue2_UInt8_31_io_deq_bits : _T_4815 ? _Queue2_UInt8_30_io_deq_bits : _T_4814 ? _Queue2_UInt8_29_io_deq_bits : _T_4813 ? _Queue2_UInt8_28_io_deq_bits : _T_4812 ? _Queue2_UInt8_27_io_deq_bits : _T_4811 ? _Queue2_UInt8_26_io_deq_bits : _T_4810 ? _Queue2_UInt8_25_io_deq_bits : _T_4809 ? _Queue2_UInt8_24_io_deq_bits : _T_4808 ? _Queue2_UInt8_23_io_deq_bits : _T_4807 ? _Queue2_UInt8_22_io_deq_bits : _T_4806 ? _Queue2_UInt8_21_io_deq_bits : _T_4805 ? _Queue2_UInt8_20_io_deq_bits : _T_4804 ? _Queue2_UInt8_19_io_deq_bits : _T_4803 ? _Queue2_UInt8_18_io_deq_bits : _T_4802 ? _Queue2_UInt8_17_io_deq_bits : _T_4801 ? _Queue2_UInt8_16_io_deq_bits : _T_4800 ? _Queue2_UInt8_15_io_deq_bits : _T_4799 ? _Queue2_UInt8_14_io_deq_bits : _T_4798 ? _Queue2_UInt8_13_io_deq_bits : _T_4797 ? _Queue2_UInt8_12_io_deq_bits : _T_4796 ? _Queue2_UInt8_11_io_deq_bits : _T_4795 ? _Queue2_UInt8_10_io_deq_bits : _T_4794 ? _Queue2_UInt8_9_io_deq_bits : _T_4793 ? _Queue2_UInt8_8_io_deq_bits : _T_4792 ? _Queue2_UInt8_7_io_deq_bits : _T_4791 ? _Queue2_UInt8_6_io_deq_bits : _T_4790 ? _Queue2_UInt8_5_io_deq_bits : _T_4789 ? _Queue2_UInt8_4_io_deq_bits : _T_4788 ? _Queue2_UInt8_3_io_deq_bits : _T_4787 ? _Queue2_UInt8_2_io_deq_bits : _T_4786 ? _Queue2_UInt8_1_io_deq_bits : _T_4785 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_14 = _T_4816 ? _Queue2_UInt8_31_io_deq_valid : _T_4815 ? _Queue2_UInt8_30_io_deq_valid : _T_4814 ? _Queue2_UInt8_29_io_deq_valid : _T_4813 ? _Queue2_UInt8_28_io_deq_valid : _T_4812 ? _Queue2_UInt8_27_io_deq_valid : _T_4811 ? _Queue2_UInt8_26_io_deq_valid : _T_4810 ? _Queue2_UInt8_25_io_deq_valid : _T_4809 ? _Queue2_UInt8_24_io_deq_valid : _T_4808 ? _Queue2_UInt8_23_io_deq_valid : _T_4807 ? _Queue2_UInt8_22_io_deq_valid : _T_4806 ? _Queue2_UInt8_21_io_deq_valid : _T_4805 ? _Queue2_UInt8_20_io_deq_valid : _T_4804 ? _Queue2_UInt8_19_io_deq_valid : _T_4803 ? _Queue2_UInt8_18_io_deq_valid : _T_4802 ? _Queue2_UInt8_17_io_deq_valid : _T_4801 ? _Queue2_UInt8_16_io_deq_valid : _T_4800 ? _Queue2_UInt8_15_io_deq_valid : _T_4799 ? _Queue2_UInt8_14_io_deq_valid : _T_4798 ? _Queue2_UInt8_13_io_deq_valid : _T_4797 ? _Queue2_UInt8_12_io_deq_valid : _T_4796 ? _Queue2_UInt8_11_io_deq_valid : _T_4795 ? _Queue2_UInt8_10_io_deq_valid : _T_4794 ? _Queue2_UInt8_9_io_deq_valid : _T_4793 ? _Queue2_UInt8_8_io_deq_valid : _T_4792 ? _Queue2_UInt8_7_io_deq_valid : _T_4791 ? _Queue2_UInt8_6_io_deq_valid : _T_4790 ? _Queue2_UInt8_5_io_deq_valid : _T_4789 ? _Queue2_UInt8_4_io_deq_valid : _T_4788 ? _Queue2_UInt8_3_io_deq_valid : _T_4787 ? _Queue2_UInt8_2_io_deq_valid : _T_4786 ? _Queue2_UInt8_1_io_deq_valid : _T_4785 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_105 = _remapindex_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_15 = _GEN_105[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4817 = remapindex_15 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4818 = remapindex_15 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4819 = remapindex_15 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4820 = remapindex_15 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4821 = remapindex_15 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4822 = remapindex_15 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4823 = remapindex_15 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4824 = remapindex_15 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4825 = remapindex_15 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4826 = remapindex_15 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4827 = remapindex_15 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4828 = remapindex_15 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4829 = remapindex_15 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4830 = remapindex_15 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4831 = remapindex_15 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4832 = remapindex_15 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4833 = remapindex_15 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4834 = remapindex_15 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4835 = remapindex_15 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4836 = remapindex_15 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4837 = remapindex_15 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4838 = remapindex_15 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4839 = remapindex_15 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4840 = remapindex_15 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4841 = remapindex_15 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4842 = remapindex_15 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4843 = remapindex_15 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4844 = remapindex_15 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4845 = remapindex_15 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4846 = remapindex_15 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4847 = remapindex_15 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4848 = remapindex_15 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_15 = _T_4848 ? _Queue2_UInt8_31_io_deq_bits : _T_4847 ? _Queue2_UInt8_30_io_deq_bits : _T_4846 ? _Queue2_UInt8_29_io_deq_bits : _T_4845 ? _Queue2_UInt8_28_io_deq_bits : _T_4844 ? _Queue2_UInt8_27_io_deq_bits : _T_4843 ? _Queue2_UInt8_26_io_deq_bits : _T_4842 ? _Queue2_UInt8_25_io_deq_bits : _T_4841 ? _Queue2_UInt8_24_io_deq_bits : _T_4840 ? _Queue2_UInt8_23_io_deq_bits : _T_4839 ? _Queue2_UInt8_22_io_deq_bits : _T_4838 ? _Queue2_UInt8_21_io_deq_bits : _T_4837 ? _Queue2_UInt8_20_io_deq_bits : _T_4836 ? _Queue2_UInt8_19_io_deq_bits : _T_4835 ? _Queue2_UInt8_18_io_deq_bits : _T_4834 ? _Queue2_UInt8_17_io_deq_bits : _T_4833 ? _Queue2_UInt8_16_io_deq_bits : _T_4832 ? _Queue2_UInt8_15_io_deq_bits : _T_4831 ? _Queue2_UInt8_14_io_deq_bits : _T_4830 ? _Queue2_UInt8_13_io_deq_bits : _T_4829 ? _Queue2_UInt8_12_io_deq_bits : _T_4828 ? _Queue2_UInt8_11_io_deq_bits : _T_4827 ? _Queue2_UInt8_10_io_deq_bits : _T_4826 ? _Queue2_UInt8_9_io_deq_bits : _T_4825 ? _Queue2_UInt8_8_io_deq_bits : _T_4824 ? _Queue2_UInt8_7_io_deq_bits : _T_4823 ? _Queue2_UInt8_6_io_deq_bits : _T_4822 ? _Queue2_UInt8_5_io_deq_bits : _T_4821 ? _Queue2_UInt8_4_io_deq_bits : _T_4820 ? _Queue2_UInt8_3_io_deq_bits : _T_4819 ? _Queue2_UInt8_2_io_deq_bits : _T_4818 ? _Queue2_UInt8_1_io_deq_bits : _T_4817 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_15 = _T_4848 ? _Queue2_UInt8_31_io_deq_valid : _T_4847 ? _Queue2_UInt8_30_io_deq_valid : _T_4846 ? _Queue2_UInt8_29_io_deq_valid : _T_4845 ? _Queue2_UInt8_28_io_deq_valid : _T_4844 ? _Queue2_UInt8_27_io_deq_valid : _T_4843 ? _Queue2_UInt8_26_io_deq_valid : _T_4842 ? _Queue2_UInt8_25_io_deq_valid : _T_4841 ? _Queue2_UInt8_24_io_deq_valid : _T_4840 ? _Queue2_UInt8_23_io_deq_valid : _T_4839 ? _Queue2_UInt8_22_io_deq_valid : _T_4838 ? _Queue2_UInt8_21_io_deq_valid : _T_4837 ? _Queue2_UInt8_20_io_deq_valid : _T_4836 ? _Queue2_UInt8_19_io_deq_valid : _T_4835 ? _Queue2_UInt8_18_io_deq_valid : _T_4834 ? _Queue2_UInt8_17_io_deq_valid : _T_4833 ? _Queue2_UInt8_16_io_deq_valid : _T_4832 ? _Queue2_UInt8_15_io_deq_valid : _T_4831 ? _Queue2_UInt8_14_io_deq_valid : _T_4830 ? _Queue2_UInt8_13_io_deq_valid : _T_4829 ? _Queue2_UInt8_12_io_deq_valid : _T_4828 ? _Queue2_UInt8_11_io_deq_valid : _T_4827 ? _Queue2_UInt8_10_io_deq_valid : _T_4826 ? _Queue2_UInt8_9_io_deq_valid : _T_4825 ? _Queue2_UInt8_8_io_deq_valid : _T_4824 ? _Queue2_UInt8_7_io_deq_valid : _T_4823 ? _Queue2_UInt8_6_io_deq_valid : _T_4822 ? _Queue2_UInt8_5_io_deq_valid : _T_4821 ? _Queue2_UInt8_4_io_deq_valid : _T_4820 ? _Queue2_UInt8_3_io_deq_valid : _T_4819 ? _Queue2_UInt8_2_io_deq_valid : _T_4818 ? _Queue2_UInt8_1_io_deq_valid : _T_4817 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_106 = _remapindex_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_16 = _GEN_106[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4849 = remapindex_16 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4850 = remapindex_16 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4851 = remapindex_16 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4852 = remapindex_16 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4853 = remapindex_16 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4854 = remapindex_16 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4855 = remapindex_16 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4856 = remapindex_16 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4857 = remapindex_16 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4858 = remapindex_16 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4859 = remapindex_16 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4860 = remapindex_16 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4861 = remapindex_16 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4862 = remapindex_16 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4863 = remapindex_16 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4864 = remapindex_16 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4865 = remapindex_16 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4866 = remapindex_16 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4867 = remapindex_16 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4868 = remapindex_16 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4869 = remapindex_16 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4870 = remapindex_16 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4871 = remapindex_16 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4872 = remapindex_16 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4873 = remapindex_16 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4874 = remapindex_16 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4875 = remapindex_16 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4876 = remapindex_16 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4877 = remapindex_16 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4878 = remapindex_16 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4879 = remapindex_16 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4880 = remapindex_16 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_16 = _T_4880 ? _Queue2_UInt8_31_io_deq_bits : _T_4879 ? _Queue2_UInt8_30_io_deq_bits : _T_4878 ? _Queue2_UInt8_29_io_deq_bits : _T_4877 ? _Queue2_UInt8_28_io_deq_bits : _T_4876 ? _Queue2_UInt8_27_io_deq_bits : _T_4875 ? _Queue2_UInt8_26_io_deq_bits : _T_4874 ? _Queue2_UInt8_25_io_deq_bits : _T_4873 ? _Queue2_UInt8_24_io_deq_bits : _T_4872 ? _Queue2_UInt8_23_io_deq_bits : _T_4871 ? _Queue2_UInt8_22_io_deq_bits : _T_4870 ? _Queue2_UInt8_21_io_deq_bits : _T_4869 ? _Queue2_UInt8_20_io_deq_bits : _T_4868 ? _Queue2_UInt8_19_io_deq_bits : _T_4867 ? _Queue2_UInt8_18_io_deq_bits : _T_4866 ? _Queue2_UInt8_17_io_deq_bits : _T_4865 ? _Queue2_UInt8_16_io_deq_bits : _T_4864 ? _Queue2_UInt8_15_io_deq_bits : _T_4863 ? _Queue2_UInt8_14_io_deq_bits : _T_4862 ? _Queue2_UInt8_13_io_deq_bits : _T_4861 ? _Queue2_UInt8_12_io_deq_bits : _T_4860 ? _Queue2_UInt8_11_io_deq_bits : _T_4859 ? _Queue2_UInt8_10_io_deq_bits : _T_4858 ? _Queue2_UInt8_9_io_deq_bits : _T_4857 ? _Queue2_UInt8_8_io_deq_bits : _T_4856 ? _Queue2_UInt8_7_io_deq_bits : _T_4855 ? _Queue2_UInt8_6_io_deq_bits : _T_4854 ? _Queue2_UInt8_5_io_deq_bits : _T_4853 ? _Queue2_UInt8_4_io_deq_bits : _T_4852 ? _Queue2_UInt8_3_io_deq_bits : _T_4851 ? _Queue2_UInt8_2_io_deq_bits : _T_4850 ? _Queue2_UInt8_1_io_deq_bits : _T_4849 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_16 = _T_4880 ? _Queue2_UInt8_31_io_deq_valid : _T_4879 ? _Queue2_UInt8_30_io_deq_valid : _T_4878 ? _Queue2_UInt8_29_io_deq_valid : _T_4877 ? _Queue2_UInt8_28_io_deq_valid : _T_4876 ? _Queue2_UInt8_27_io_deq_valid : _T_4875 ? _Queue2_UInt8_26_io_deq_valid : _T_4874 ? _Queue2_UInt8_25_io_deq_valid : _T_4873 ? _Queue2_UInt8_24_io_deq_valid : _T_4872 ? _Queue2_UInt8_23_io_deq_valid : _T_4871 ? _Queue2_UInt8_22_io_deq_valid : _T_4870 ? _Queue2_UInt8_21_io_deq_valid : _T_4869 ? _Queue2_UInt8_20_io_deq_valid : _T_4868 ? _Queue2_UInt8_19_io_deq_valid : _T_4867 ? _Queue2_UInt8_18_io_deq_valid : _T_4866 ? _Queue2_UInt8_17_io_deq_valid : _T_4865 ? _Queue2_UInt8_16_io_deq_valid : _T_4864 ? _Queue2_UInt8_15_io_deq_valid : _T_4863 ? _Queue2_UInt8_14_io_deq_valid : _T_4862 ? _Queue2_UInt8_13_io_deq_valid : _T_4861 ? _Queue2_UInt8_12_io_deq_valid : _T_4860 ? _Queue2_UInt8_11_io_deq_valid : _T_4859 ? _Queue2_UInt8_10_io_deq_valid : _T_4858 ? _Queue2_UInt8_9_io_deq_valid : _T_4857 ? _Queue2_UInt8_8_io_deq_valid : _T_4856 ? _Queue2_UInt8_7_io_deq_valid : _T_4855 ? _Queue2_UInt8_6_io_deq_valid : _T_4854 ? _Queue2_UInt8_5_io_deq_valid : _T_4853 ? _Queue2_UInt8_4_io_deq_valid : _T_4852 ? _Queue2_UInt8_3_io_deq_valid : _T_4851 ? _Queue2_UInt8_2_io_deq_valid : _T_4850 ? _Queue2_UInt8_1_io_deq_valid : _T_4849 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_107 = _remapindex_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_17 = _GEN_107[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4881 = remapindex_17 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4882 = remapindex_17 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4883 = remapindex_17 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4884 = remapindex_17 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4885 = remapindex_17 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4886 = remapindex_17 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4887 = remapindex_17 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4888 = remapindex_17 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4889 = remapindex_17 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4890 = remapindex_17 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4891 = remapindex_17 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4892 = remapindex_17 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4893 = remapindex_17 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4894 = remapindex_17 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4895 = remapindex_17 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4896 = remapindex_17 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4897 = remapindex_17 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4898 = remapindex_17 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4899 = remapindex_17 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4900 = remapindex_17 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4901 = remapindex_17 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4902 = remapindex_17 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4903 = remapindex_17 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4904 = remapindex_17 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4905 = remapindex_17 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4906 = remapindex_17 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4907 = remapindex_17 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4908 = remapindex_17 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4909 = remapindex_17 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4910 = remapindex_17 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4911 = remapindex_17 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4912 = remapindex_17 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_17 = _T_4912 ? _Queue2_UInt8_31_io_deq_bits : _T_4911 ? _Queue2_UInt8_30_io_deq_bits : _T_4910 ? _Queue2_UInt8_29_io_deq_bits : _T_4909 ? _Queue2_UInt8_28_io_deq_bits : _T_4908 ? _Queue2_UInt8_27_io_deq_bits : _T_4907 ? _Queue2_UInt8_26_io_deq_bits : _T_4906 ? _Queue2_UInt8_25_io_deq_bits : _T_4905 ? _Queue2_UInt8_24_io_deq_bits : _T_4904 ? _Queue2_UInt8_23_io_deq_bits : _T_4903 ? _Queue2_UInt8_22_io_deq_bits : _T_4902 ? _Queue2_UInt8_21_io_deq_bits : _T_4901 ? _Queue2_UInt8_20_io_deq_bits : _T_4900 ? _Queue2_UInt8_19_io_deq_bits : _T_4899 ? _Queue2_UInt8_18_io_deq_bits : _T_4898 ? _Queue2_UInt8_17_io_deq_bits : _T_4897 ? _Queue2_UInt8_16_io_deq_bits : _T_4896 ? _Queue2_UInt8_15_io_deq_bits : _T_4895 ? _Queue2_UInt8_14_io_deq_bits : _T_4894 ? _Queue2_UInt8_13_io_deq_bits : _T_4893 ? _Queue2_UInt8_12_io_deq_bits : _T_4892 ? _Queue2_UInt8_11_io_deq_bits : _T_4891 ? _Queue2_UInt8_10_io_deq_bits : _T_4890 ? _Queue2_UInt8_9_io_deq_bits : _T_4889 ? _Queue2_UInt8_8_io_deq_bits : _T_4888 ? _Queue2_UInt8_7_io_deq_bits : _T_4887 ? _Queue2_UInt8_6_io_deq_bits : _T_4886 ? _Queue2_UInt8_5_io_deq_bits : _T_4885 ? _Queue2_UInt8_4_io_deq_bits : _T_4884 ? _Queue2_UInt8_3_io_deq_bits : _T_4883 ? _Queue2_UInt8_2_io_deq_bits : _T_4882 ? _Queue2_UInt8_1_io_deq_bits : _T_4881 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_17 = _T_4912 ? _Queue2_UInt8_31_io_deq_valid : _T_4911 ? _Queue2_UInt8_30_io_deq_valid : _T_4910 ? _Queue2_UInt8_29_io_deq_valid : _T_4909 ? _Queue2_UInt8_28_io_deq_valid : _T_4908 ? _Queue2_UInt8_27_io_deq_valid : _T_4907 ? _Queue2_UInt8_26_io_deq_valid : _T_4906 ? _Queue2_UInt8_25_io_deq_valid : _T_4905 ? _Queue2_UInt8_24_io_deq_valid : _T_4904 ? _Queue2_UInt8_23_io_deq_valid : _T_4903 ? _Queue2_UInt8_22_io_deq_valid : _T_4902 ? _Queue2_UInt8_21_io_deq_valid : _T_4901 ? _Queue2_UInt8_20_io_deq_valid : _T_4900 ? _Queue2_UInt8_19_io_deq_valid : _T_4899 ? _Queue2_UInt8_18_io_deq_valid : _T_4898 ? _Queue2_UInt8_17_io_deq_valid : _T_4897 ? _Queue2_UInt8_16_io_deq_valid : _T_4896 ? _Queue2_UInt8_15_io_deq_valid : _T_4895 ? _Queue2_UInt8_14_io_deq_valid : _T_4894 ? _Queue2_UInt8_13_io_deq_valid : _T_4893 ? _Queue2_UInt8_12_io_deq_valid : _T_4892 ? _Queue2_UInt8_11_io_deq_valid : _T_4891 ? _Queue2_UInt8_10_io_deq_valid : _T_4890 ? _Queue2_UInt8_9_io_deq_valid : _T_4889 ? _Queue2_UInt8_8_io_deq_valid : _T_4888 ? _Queue2_UInt8_7_io_deq_valid : _T_4887 ? _Queue2_UInt8_6_io_deq_valid : _T_4886 ? _Queue2_UInt8_5_io_deq_valid : _T_4885 ? _Queue2_UInt8_4_io_deq_valid : _T_4884 ? _Queue2_UInt8_3_io_deq_valid : _T_4883 ? _Queue2_UInt8_2_io_deq_valid : _T_4882 ? _Queue2_UInt8_1_io_deq_valid : _T_4881 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_108 = _remapindex_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_18 = _GEN_108[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4913 = remapindex_18 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4914 = remapindex_18 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4915 = remapindex_18 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4916 = remapindex_18 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4917 = remapindex_18 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4918 = remapindex_18 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4919 = remapindex_18 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4920 = remapindex_18 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4921 = remapindex_18 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4922 = remapindex_18 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4923 = remapindex_18 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4924 = remapindex_18 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4925 = remapindex_18 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4926 = remapindex_18 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4927 = remapindex_18 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4928 = remapindex_18 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4929 = remapindex_18 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4930 = remapindex_18 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4931 = remapindex_18 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4932 = remapindex_18 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4933 = remapindex_18 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4934 = remapindex_18 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4935 = remapindex_18 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4936 = remapindex_18 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4937 = remapindex_18 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4938 = remapindex_18 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4939 = remapindex_18 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4940 = remapindex_18 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4941 = remapindex_18 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4942 = remapindex_18 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4943 = remapindex_18 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4944 = remapindex_18 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_18 = _T_4944 ? _Queue2_UInt8_31_io_deq_bits : _T_4943 ? _Queue2_UInt8_30_io_deq_bits : _T_4942 ? _Queue2_UInt8_29_io_deq_bits : _T_4941 ? _Queue2_UInt8_28_io_deq_bits : _T_4940 ? _Queue2_UInt8_27_io_deq_bits : _T_4939 ? _Queue2_UInt8_26_io_deq_bits : _T_4938 ? _Queue2_UInt8_25_io_deq_bits : _T_4937 ? _Queue2_UInt8_24_io_deq_bits : _T_4936 ? _Queue2_UInt8_23_io_deq_bits : _T_4935 ? _Queue2_UInt8_22_io_deq_bits : _T_4934 ? _Queue2_UInt8_21_io_deq_bits : _T_4933 ? _Queue2_UInt8_20_io_deq_bits : _T_4932 ? _Queue2_UInt8_19_io_deq_bits : _T_4931 ? _Queue2_UInt8_18_io_deq_bits : _T_4930 ? _Queue2_UInt8_17_io_deq_bits : _T_4929 ? _Queue2_UInt8_16_io_deq_bits : _T_4928 ? _Queue2_UInt8_15_io_deq_bits : _T_4927 ? _Queue2_UInt8_14_io_deq_bits : _T_4926 ? _Queue2_UInt8_13_io_deq_bits : _T_4925 ? _Queue2_UInt8_12_io_deq_bits : _T_4924 ? _Queue2_UInt8_11_io_deq_bits : _T_4923 ? _Queue2_UInt8_10_io_deq_bits : _T_4922 ? _Queue2_UInt8_9_io_deq_bits : _T_4921 ? _Queue2_UInt8_8_io_deq_bits : _T_4920 ? _Queue2_UInt8_7_io_deq_bits : _T_4919 ? _Queue2_UInt8_6_io_deq_bits : _T_4918 ? _Queue2_UInt8_5_io_deq_bits : _T_4917 ? _Queue2_UInt8_4_io_deq_bits : _T_4916 ? _Queue2_UInt8_3_io_deq_bits : _T_4915 ? _Queue2_UInt8_2_io_deq_bits : _T_4914 ? _Queue2_UInt8_1_io_deq_bits : _T_4913 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_18 = _T_4944 ? _Queue2_UInt8_31_io_deq_valid : _T_4943 ? _Queue2_UInt8_30_io_deq_valid : _T_4942 ? _Queue2_UInt8_29_io_deq_valid : _T_4941 ? _Queue2_UInt8_28_io_deq_valid : _T_4940 ? _Queue2_UInt8_27_io_deq_valid : _T_4939 ? _Queue2_UInt8_26_io_deq_valid : _T_4938 ? _Queue2_UInt8_25_io_deq_valid : _T_4937 ? _Queue2_UInt8_24_io_deq_valid : _T_4936 ? _Queue2_UInt8_23_io_deq_valid : _T_4935 ? _Queue2_UInt8_22_io_deq_valid : _T_4934 ? _Queue2_UInt8_21_io_deq_valid : _T_4933 ? _Queue2_UInt8_20_io_deq_valid : _T_4932 ? _Queue2_UInt8_19_io_deq_valid : _T_4931 ? _Queue2_UInt8_18_io_deq_valid : _T_4930 ? _Queue2_UInt8_17_io_deq_valid : _T_4929 ? _Queue2_UInt8_16_io_deq_valid : _T_4928 ? _Queue2_UInt8_15_io_deq_valid : _T_4927 ? _Queue2_UInt8_14_io_deq_valid : _T_4926 ? _Queue2_UInt8_13_io_deq_valid : _T_4925 ? _Queue2_UInt8_12_io_deq_valid : _T_4924 ? _Queue2_UInt8_11_io_deq_valid : _T_4923 ? _Queue2_UInt8_10_io_deq_valid : _T_4922 ? _Queue2_UInt8_9_io_deq_valid : _T_4921 ? _Queue2_UInt8_8_io_deq_valid : _T_4920 ? _Queue2_UInt8_7_io_deq_valid : _T_4919 ? _Queue2_UInt8_6_io_deq_valid : _T_4918 ? _Queue2_UInt8_5_io_deq_valid : _T_4917 ? _Queue2_UInt8_4_io_deq_valid : _T_4916 ? _Queue2_UInt8_3_io_deq_valid : _T_4915 ? _Queue2_UInt8_2_io_deq_valid : _T_4914 ? _Queue2_UInt8_1_io_deq_valid : _T_4913 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_109 = _remapindex_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_19 = _GEN_109[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4945 = remapindex_19 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4946 = remapindex_19 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4947 = remapindex_19 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4948 = remapindex_19 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4949 = remapindex_19 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4950 = remapindex_19 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4951 = remapindex_19 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4952 = remapindex_19 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4953 = remapindex_19 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4954 = remapindex_19 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4955 = remapindex_19 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4956 = remapindex_19 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4957 = remapindex_19 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4958 = remapindex_19 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4959 = remapindex_19 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4960 = remapindex_19 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4961 = remapindex_19 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4962 = remapindex_19 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4963 = remapindex_19 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4964 = remapindex_19 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4965 = remapindex_19 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4966 = remapindex_19 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4967 = remapindex_19 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4968 = remapindex_19 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4969 = remapindex_19 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4970 = remapindex_19 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4971 = remapindex_19 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4972 = remapindex_19 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4973 = remapindex_19 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4974 = remapindex_19 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4975 = remapindex_19 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4976 = remapindex_19 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_19 = _T_4976 ? _Queue2_UInt8_31_io_deq_bits : _T_4975 ? _Queue2_UInt8_30_io_deq_bits : _T_4974 ? _Queue2_UInt8_29_io_deq_bits : _T_4973 ? _Queue2_UInt8_28_io_deq_bits : _T_4972 ? _Queue2_UInt8_27_io_deq_bits : _T_4971 ? _Queue2_UInt8_26_io_deq_bits : _T_4970 ? _Queue2_UInt8_25_io_deq_bits : _T_4969 ? _Queue2_UInt8_24_io_deq_bits : _T_4968 ? _Queue2_UInt8_23_io_deq_bits : _T_4967 ? _Queue2_UInt8_22_io_deq_bits : _T_4966 ? _Queue2_UInt8_21_io_deq_bits : _T_4965 ? _Queue2_UInt8_20_io_deq_bits : _T_4964 ? _Queue2_UInt8_19_io_deq_bits : _T_4963 ? _Queue2_UInt8_18_io_deq_bits : _T_4962 ? _Queue2_UInt8_17_io_deq_bits : _T_4961 ? _Queue2_UInt8_16_io_deq_bits : _T_4960 ? _Queue2_UInt8_15_io_deq_bits : _T_4959 ? _Queue2_UInt8_14_io_deq_bits : _T_4958 ? _Queue2_UInt8_13_io_deq_bits : _T_4957 ? _Queue2_UInt8_12_io_deq_bits : _T_4956 ? _Queue2_UInt8_11_io_deq_bits : _T_4955 ? _Queue2_UInt8_10_io_deq_bits : _T_4954 ? _Queue2_UInt8_9_io_deq_bits : _T_4953 ? _Queue2_UInt8_8_io_deq_bits : _T_4952 ? _Queue2_UInt8_7_io_deq_bits : _T_4951 ? _Queue2_UInt8_6_io_deq_bits : _T_4950 ? _Queue2_UInt8_5_io_deq_bits : _T_4949 ? _Queue2_UInt8_4_io_deq_bits : _T_4948 ? _Queue2_UInt8_3_io_deq_bits : _T_4947 ? _Queue2_UInt8_2_io_deq_bits : _T_4946 ? _Queue2_UInt8_1_io_deq_bits : _T_4945 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_19 = _T_4976 ? _Queue2_UInt8_31_io_deq_valid : _T_4975 ? _Queue2_UInt8_30_io_deq_valid : _T_4974 ? _Queue2_UInt8_29_io_deq_valid : _T_4973 ? _Queue2_UInt8_28_io_deq_valid : _T_4972 ? _Queue2_UInt8_27_io_deq_valid : _T_4971 ? _Queue2_UInt8_26_io_deq_valid : _T_4970 ? _Queue2_UInt8_25_io_deq_valid : _T_4969 ? _Queue2_UInt8_24_io_deq_valid : _T_4968 ? _Queue2_UInt8_23_io_deq_valid : _T_4967 ? _Queue2_UInt8_22_io_deq_valid : _T_4966 ? _Queue2_UInt8_21_io_deq_valid : _T_4965 ? _Queue2_UInt8_20_io_deq_valid : _T_4964 ? _Queue2_UInt8_19_io_deq_valid : _T_4963 ? _Queue2_UInt8_18_io_deq_valid : _T_4962 ? _Queue2_UInt8_17_io_deq_valid : _T_4961 ? _Queue2_UInt8_16_io_deq_valid : _T_4960 ? _Queue2_UInt8_15_io_deq_valid : _T_4959 ? _Queue2_UInt8_14_io_deq_valid : _T_4958 ? _Queue2_UInt8_13_io_deq_valid : _T_4957 ? _Queue2_UInt8_12_io_deq_valid : _T_4956 ? _Queue2_UInt8_11_io_deq_valid : _T_4955 ? _Queue2_UInt8_10_io_deq_valid : _T_4954 ? _Queue2_UInt8_9_io_deq_valid : _T_4953 ? _Queue2_UInt8_8_io_deq_valid : _T_4952 ? _Queue2_UInt8_7_io_deq_valid : _T_4951 ? _Queue2_UInt8_6_io_deq_valid : _T_4950 ? _Queue2_UInt8_5_io_deq_valid : _T_4949 ? _Queue2_UInt8_4_io_deq_valid : _T_4948 ? _Queue2_UInt8_3_io_deq_valid : _T_4947 ? _Queue2_UInt8_2_io_deq_valid : _T_4946 ? _Queue2_UInt8_1_io_deq_valid : _T_4945 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_110 = _remapindex_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_20 = _GEN_110[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4977 = remapindex_20 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4978 = remapindex_20 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4979 = remapindex_20 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4980 = remapindex_20 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4981 = remapindex_20 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4982 = remapindex_20 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4983 = remapindex_20 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4984 = remapindex_20 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4985 = remapindex_20 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4986 = remapindex_20 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4987 = remapindex_20 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4988 = remapindex_20 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4989 = remapindex_20 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4990 = remapindex_20 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4991 = remapindex_20 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4992 = remapindex_20 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4993 = remapindex_20 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4994 = remapindex_20 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4995 = remapindex_20 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4996 = remapindex_20 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4997 = remapindex_20 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4998 = remapindex_20 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4999 = remapindex_20 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5000 = remapindex_20 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5001 = remapindex_20 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5002 = remapindex_20 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5003 = remapindex_20 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5004 = remapindex_20 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5005 = remapindex_20 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5006 = remapindex_20 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5007 = remapindex_20 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5008 = remapindex_20 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_20 = _T_5008 ? _Queue2_UInt8_31_io_deq_bits : _T_5007 ? _Queue2_UInt8_30_io_deq_bits : _T_5006 ? _Queue2_UInt8_29_io_deq_bits : _T_5005 ? _Queue2_UInt8_28_io_deq_bits : _T_5004 ? _Queue2_UInt8_27_io_deq_bits : _T_5003 ? _Queue2_UInt8_26_io_deq_bits : _T_5002 ? _Queue2_UInt8_25_io_deq_bits : _T_5001 ? _Queue2_UInt8_24_io_deq_bits : _T_5000 ? _Queue2_UInt8_23_io_deq_bits : _T_4999 ? _Queue2_UInt8_22_io_deq_bits : _T_4998 ? _Queue2_UInt8_21_io_deq_bits : _T_4997 ? _Queue2_UInt8_20_io_deq_bits : _T_4996 ? _Queue2_UInt8_19_io_deq_bits : _T_4995 ? _Queue2_UInt8_18_io_deq_bits : _T_4994 ? _Queue2_UInt8_17_io_deq_bits : _T_4993 ? _Queue2_UInt8_16_io_deq_bits : _T_4992 ? _Queue2_UInt8_15_io_deq_bits : _T_4991 ? _Queue2_UInt8_14_io_deq_bits : _T_4990 ? _Queue2_UInt8_13_io_deq_bits : _T_4989 ? _Queue2_UInt8_12_io_deq_bits : _T_4988 ? _Queue2_UInt8_11_io_deq_bits : _T_4987 ? _Queue2_UInt8_10_io_deq_bits : _T_4986 ? _Queue2_UInt8_9_io_deq_bits : _T_4985 ? _Queue2_UInt8_8_io_deq_bits : _T_4984 ? _Queue2_UInt8_7_io_deq_bits : _T_4983 ? _Queue2_UInt8_6_io_deq_bits : _T_4982 ? _Queue2_UInt8_5_io_deq_bits : _T_4981 ? _Queue2_UInt8_4_io_deq_bits : _T_4980 ? _Queue2_UInt8_3_io_deq_bits : _T_4979 ? _Queue2_UInt8_2_io_deq_bits : _T_4978 ? _Queue2_UInt8_1_io_deq_bits : _T_4977 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_20 = _T_5008 ? _Queue2_UInt8_31_io_deq_valid : _T_5007 ? _Queue2_UInt8_30_io_deq_valid : _T_5006 ? _Queue2_UInt8_29_io_deq_valid : _T_5005 ? _Queue2_UInt8_28_io_deq_valid : _T_5004 ? _Queue2_UInt8_27_io_deq_valid : _T_5003 ? _Queue2_UInt8_26_io_deq_valid : _T_5002 ? _Queue2_UInt8_25_io_deq_valid : _T_5001 ? _Queue2_UInt8_24_io_deq_valid : _T_5000 ? _Queue2_UInt8_23_io_deq_valid : _T_4999 ? _Queue2_UInt8_22_io_deq_valid : _T_4998 ? _Queue2_UInt8_21_io_deq_valid : _T_4997 ? _Queue2_UInt8_20_io_deq_valid : _T_4996 ? _Queue2_UInt8_19_io_deq_valid : _T_4995 ? _Queue2_UInt8_18_io_deq_valid : _T_4994 ? _Queue2_UInt8_17_io_deq_valid : _T_4993 ? _Queue2_UInt8_16_io_deq_valid : _T_4992 ? _Queue2_UInt8_15_io_deq_valid : _T_4991 ? _Queue2_UInt8_14_io_deq_valid : _T_4990 ? _Queue2_UInt8_13_io_deq_valid : _T_4989 ? _Queue2_UInt8_12_io_deq_valid : _T_4988 ? _Queue2_UInt8_11_io_deq_valid : _T_4987 ? _Queue2_UInt8_10_io_deq_valid : _T_4986 ? _Queue2_UInt8_9_io_deq_valid : _T_4985 ? _Queue2_UInt8_8_io_deq_valid : _T_4984 ? _Queue2_UInt8_7_io_deq_valid : _T_4983 ? _Queue2_UInt8_6_io_deq_valid : _T_4982 ? _Queue2_UInt8_5_io_deq_valid : _T_4981 ? _Queue2_UInt8_4_io_deq_valid : _T_4980 ? _Queue2_UInt8_3_io_deq_valid : _T_4979 ? _Queue2_UInt8_2_io_deq_valid : _T_4978 ? _Queue2_UInt8_1_io_deq_valid : _T_4977 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_111 = _remapindex_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_21 = _GEN_111[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5009 = remapindex_21 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5010 = remapindex_21 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5011 = remapindex_21 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5012 = remapindex_21 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5013 = remapindex_21 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5014 = remapindex_21 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5015 = remapindex_21 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5016 = remapindex_21 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5017 = remapindex_21 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5018 = remapindex_21 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5019 = remapindex_21 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5020 = remapindex_21 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5021 = remapindex_21 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5022 = remapindex_21 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5023 = remapindex_21 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5024 = remapindex_21 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5025 = remapindex_21 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5026 = remapindex_21 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5027 = remapindex_21 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5028 = remapindex_21 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5029 = remapindex_21 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5030 = remapindex_21 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5031 = remapindex_21 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5032 = remapindex_21 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5033 = remapindex_21 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5034 = remapindex_21 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5035 = remapindex_21 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5036 = remapindex_21 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5037 = remapindex_21 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5038 = remapindex_21 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5039 = remapindex_21 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5040 = remapindex_21 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_21 = _T_5040 ? _Queue2_UInt8_31_io_deq_bits : _T_5039 ? _Queue2_UInt8_30_io_deq_bits : _T_5038 ? _Queue2_UInt8_29_io_deq_bits : _T_5037 ? _Queue2_UInt8_28_io_deq_bits : _T_5036 ? _Queue2_UInt8_27_io_deq_bits : _T_5035 ? _Queue2_UInt8_26_io_deq_bits : _T_5034 ? _Queue2_UInt8_25_io_deq_bits : _T_5033 ? _Queue2_UInt8_24_io_deq_bits : _T_5032 ? _Queue2_UInt8_23_io_deq_bits : _T_5031 ? _Queue2_UInt8_22_io_deq_bits : _T_5030 ? _Queue2_UInt8_21_io_deq_bits : _T_5029 ? _Queue2_UInt8_20_io_deq_bits : _T_5028 ? _Queue2_UInt8_19_io_deq_bits : _T_5027 ? _Queue2_UInt8_18_io_deq_bits : _T_5026 ? _Queue2_UInt8_17_io_deq_bits : _T_5025 ? _Queue2_UInt8_16_io_deq_bits : _T_5024 ? _Queue2_UInt8_15_io_deq_bits : _T_5023 ? _Queue2_UInt8_14_io_deq_bits : _T_5022 ? _Queue2_UInt8_13_io_deq_bits : _T_5021 ? _Queue2_UInt8_12_io_deq_bits : _T_5020 ? _Queue2_UInt8_11_io_deq_bits : _T_5019 ? _Queue2_UInt8_10_io_deq_bits : _T_5018 ? _Queue2_UInt8_9_io_deq_bits : _T_5017 ? _Queue2_UInt8_8_io_deq_bits : _T_5016 ? _Queue2_UInt8_7_io_deq_bits : _T_5015 ? _Queue2_UInt8_6_io_deq_bits : _T_5014 ? _Queue2_UInt8_5_io_deq_bits : _T_5013 ? _Queue2_UInt8_4_io_deq_bits : _T_5012 ? _Queue2_UInt8_3_io_deq_bits : _T_5011 ? _Queue2_UInt8_2_io_deq_bits : _T_5010 ? _Queue2_UInt8_1_io_deq_bits : _T_5009 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_21 = _T_5040 ? _Queue2_UInt8_31_io_deq_valid : _T_5039 ? _Queue2_UInt8_30_io_deq_valid : _T_5038 ? _Queue2_UInt8_29_io_deq_valid : _T_5037 ? _Queue2_UInt8_28_io_deq_valid : _T_5036 ? _Queue2_UInt8_27_io_deq_valid : _T_5035 ? _Queue2_UInt8_26_io_deq_valid : _T_5034 ? _Queue2_UInt8_25_io_deq_valid : _T_5033 ? _Queue2_UInt8_24_io_deq_valid : _T_5032 ? _Queue2_UInt8_23_io_deq_valid : _T_5031 ? _Queue2_UInt8_22_io_deq_valid : _T_5030 ? _Queue2_UInt8_21_io_deq_valid : _T_5029 ? _Queue2_UInt8_20_io_deq_valid : _T_5028 ? _Queue2_UInt8_19_io_deq_valid : _T_5027 ? _Queue2_UInt8_18_io_deq_valid : _T_5026 ? _Queue2_UInt8_17_io_deq_valid : _T_5025 ? _Queue2_UInt8_16_io_deq_valid : _T_5024 ? _Queue2_UInt8_15_io_deq_valid : _T_5023 ? _Queue2_UInt8_14_io_deq_valid : _T_5022 ? _Queue2_UInt8_13_io_deq_valid : _T_5021 ? _Queue2_UInt8_12_io_deq_valid : _T_5020 ? _Queue2_UInt8_11_io_deq_valid : _T_5019 ? _Queue2_UInt8_10_io_deq_valid : _T_5018 ? _Queue2_UInt8_9_io_deq_valid : _T_5017 ? _Queue2_UInt8_8_io_deq_valid : _T_5016 ? _Queue2_UInt8_7_io_deq_valid : _T_5015 ? _Queue2_UInt8_6_io_deq_valid : _T_5014 ? _Queue2_UInt8_5_io_deq_valid : _T_5013 ? _Queue2_UInt8_4_io_deq_valid : _T_5012 ? _Queue2_UInt8_3_io_deq_valid : _T_5011 ? _Queue2_UInt8_2_io_deq_valid : _T_5010 ? _Queue2_UInt8_1_io_deq_valid : _T_5009 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_112 = _remapindex_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_22 = _GEN_112[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5041 = remapindex_22 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5042 = remapindex_22 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5043 = remapindex_22 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5044 = remapindex_22 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5045 = remapindex_22 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5046 = remapindex_22 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5047 = remapindex_22 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5048 = remapindex_22 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5049 = remapindex_22 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5050 = remapindex_22 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5051 = remapindex_22 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5052 = remapindex_22 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5053 = remapindex_22 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5054 = remapindex_22 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5055 = remapindex_22 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5056 = remapindex_22 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5057 = remapindex_22 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5058 = remapindex_22 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5059 = remapindex_22 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5060 = remapindex_22 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5061 = remapindex_22 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5062 = remapindex_22 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5063 = remapindex_22 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5064 = remapindex_22 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5065 = remapindex_22 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5066 = remapindex_22 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5067 = remapindex_22 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5068 = remapindex_22 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5069 = remapindex_22 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5070 = remapindex_22 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5071 = remapindex_22 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5072 = remapindex_22 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_22 = _T_5072 ? _Queue2_UInt8_31_io_deq_bits : _T_5071 ? _Queue2_UInt8_30_io_deq_bits : _T_5070 ? _Queue2_UInt8_29_io_deq_bits : _T_5069 ? _Queue2_UInt8_28_io_deq_bits : _T_5068 ? _Queue2_UInt8_27_io_deq_bits : _T_5067 ? _Queue2_UInt8_26_io_deq_bits : _T_5066 ? _Queue2_UInt8_25_io_deq_bits : _T_5065 ? _Queue2_UInt8_24_io_deq_bits : _T_5064 ? _Queue2_UInt8_23_io_deq_bits : _T_5063 ? _Queue2_UInt8_22_io_deq_bits : _T_5062 ? _Queue2_UInt8_21_io_deq_bits : _T_5061 ? _Queue2_UInt8_20_io_deq_bits : _T_5060 ? _Queue2_UInt8_19_io_deq_bits : _T_5059 ? _Queue2_UInt8_18_io_deq_bits : _T_5058 ? _Queue2_UInt8_17_io_deq_bits : _T_5057 ? _Queue2_UInt8_16_io_deq_bits : _T_5056 ? _Queue2_UInt8_15_io_deq_bits : _T_5055 ? _Queue2_UInt8_14_io_deq_bits : _T_5054 ? _Queue2_UInt8_13_io_deq_bits : _T_5053 ? _Queue2_UInt8_12_io_deq_bits : _T_5052 ? _Queue2_UInt8_11_io_deq_bits : _T_5051 ? _Queue2_UInt8_10_io_deq_bits : _T_5050 ? _Queue2_UInt8_9_io_deq_bits : _T_5049 ? _Queue2_UInt8_8_io_deq_bits : _T_5048 ? _Queue2_UInt8_7_io_deq_bits : _T_5047 ? _Queue2_UInt8_6_io_deq_bits : _T_5046 ? _Queue2_UInt8_5_io_deq_bits : _T_5045 ? _Queue2_UInt8_4_io_deq_bits : _T_5044 ? _Queue2_UInt8_3_io_deq_bits : _T_5043 ? _Queue2_UInt8_2_io_deq_bits : _T_5042 ? _Queue2_UInt8_1_io_deq_bits : _T_5041 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_22 = _T_5072 ? _Queue2_UInt8_31_io_deq_valid : _T_5071 ? _Queue2_UInt8_30_io_deq_valid : _T_5070 ? _Queue2_UInt8_29_io_deq_valid : _T_5069 ? _Queue2_UInt8_28_io_deq_valid : _T_5068 ? _Queue2_UInt8_27_io_deq_valid : _T_5067 ? _Queue2_UInt8_26_io_deq_valid : _T_5066 ? _Queue2_UInt8_25_io_deq_valid : _T_5065 ? _Queue2_UInt8_24_io_deq_valid : _T_5064 ? _Queue2_UInt8_23_io_deq_valid : _T_5063 ? _Queue2_UInt8_22_io_deq_valid : _T_5062 ? _Queue2_UInt8_21_io_deq_valid : _T_5061 ? _Queue2_UInt8_20_io_deq_valid : _T_5060 ? _Queue2_UInt8_19_io_deq_valid : _T_5059 ? _Queue2_UInt8_18_io_deq_valid : _T_5058 ? _Queue2_UInt8_17_io_deq_valid : _T_5057 ? _Queue2_UInt8_16_io_deq_valid : _T_5056 ? _Queue2_UInt8_15_io_deq_valid : _T_5055 ? _Queue2_UInt8_14_io_deq_valid : _T_5054 ? _Queue2_UInt8_13_io_deq_valid : _T_5053 ? _Queue2_UInt8_12_io_deq_valid : _T_5052 ? _Queue2_UInt8_11_io_deq_valid : _T_5051 ? _Queue2_UInt8_10_io_deq_valid : _T_5050 ? _Queue2_UInt8_9_io_deq_valid : _T_5049 ? _Queue2_UInt8_8_io_deq_valid : _T_5048 ? _Queue2_UInt8_7_io_deq_valid : _T_5047 ? _Queue2_UInt8_6_io_deq_valid : _T_5046 ? _Queue2_UInt8_5_io_deq_valid : _T_5045 ? _Queue2_UInt8_4_io_deq_valid : _T_5044 ? _Queue2_UInt8_3_io_deq_valid : _T_5043 ? _Queue2_UInt8_2_io_deq_valid : _T_5042 ? _Queue2_UInt8_1_io_deq_valid : _T_5041 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_113 = _remapindex_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_23 = _GEN_113[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5073 = remapindex_23 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5074 = remapindex_23 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5075 = remapindex_23 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5076 = remapindex_23 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5077 = remapindex_23 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5078 = remapindex_23 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5079 = remapindex_23 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5080 = remapindex_23 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5081 = remapindex_23 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5082 = remapindex_23 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5083 = remapindex_23 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5084 = remapindex_23 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5085 = remapindex_23 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5086 = remapindex_23 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5087 = remapindex_23 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5088 = remapindex_23 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5089 = remapindex_23 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5090 = remapindex_23 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5091 = remapindex_23 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5092 = remapindex_23 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5093 = remapindex_23 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5094 = remapindex_23 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5095 = remapindex_23 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5096 = remapindex_23 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5097 = remapindex_23 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5098 = remapindex_23 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5099 = remapindex_23 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5100 = remapindex_23 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5101 = remapindex_23 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5102 = remapindex_23 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5103 = remapindex_23 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5104 = remapindex_23 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_23 = _T_5104 ? _Queue2_UInt8_31_io_deq_bits : _T_5103 ? _Queue2_UInt8_30_io_deq_bits : _T_5102 ? _Queue2_UInt8_29_io_deq_bits : _T_5101 ? _Queue2_UInt8_28_io_deq_bits : _T_5100 ? _Queue2_UInt8_27_io_deq_bits : _T_5099 ? _Queue2_UInt8_26_io_deq_bits : _T_5098 ? _Queue2_UInt8_25_io_deq_bits : _T_5097 ? _Queue2_UInt8_24_io_deq_bits : _T_5096 ? _Queue2_UInt8_23_io_deq_bits : _T_5095 ? _Queue2_UInt8_22_io_deq_bits : _T_5094 ? _Queue2_UInt8_21_io_deq_bits : _T_5093 ? _Queue2_UInt8_20_io_deq_bits : _T_5092 ? _Queue2_UInt8_19_io_deq_bits : _T_5091 ? _Queue2_UInt8_18_io_deq_bits : _T_5090 ? _Queue2_UInt8_17_io_deq_bits : _T_5089 ? _Queue2_UInt8_16_io_deq_bits : _T_5088 ? _Queue2_UInt8_15_io_deq_bits : _T_5087 ? _Queue2_UInt8_14_io_deq_bits : _T_5086 ? _Queue2_UInt8_13_io_deq_bits : _T_5085 ? _Queue2_UInt8_12_io_deq_bits : _T_5084 ? _Queue2_UInt8_11_io_deq_bits : _T_5083 ? _Queue2_UInt8_10_io_deq_bits : _T_5082 ? _Queue2_UInt8_9_io_deq_bits : _T_5081 ? _Queue2_UInt8_8_io_deq_bits : _T_5080 ? _Queue2_UInt8_7_io_deq_bits : _T_5079 ? _Queue2_UInt8_6_io_deq_bits : _T_5078 ? _Queue2_UInt8_5_io_deq_bits : _T_5077 ? _Queue2_UInt8_4_io_deq_bits : _T_5076 ? _Queue2_UInt8_3_io_deq_bits : _T_5075 ? _Queue2_UInt8_2_io_deq_bits : _T_5074 ? _Queue2_UInt8_1_io_deq_bits : _T_5073 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_23 = _T_5104 ? _Queue2_UInt8_31_io_deq_valid : _T_5103 ? _Queue2_UInt8_30_io_deq_valid : _T_5102 ? _Queue2_UInt8_29_io_deq_valid : _T_5101 ? _Queue2_UInt8_28_io_deq_valid : _T_5100 ? _Queue2_UInt8_27_io_deq_valid : _T_5099 ? _Queue2_UInt8_26_io_deq_valid : _T_5098 ? _Queue2_UInt8_25_io_deq_valid : _T_5097 ? _Queue2_UInt8_24_io_deq_valid : _T_5096 ? _Queue2_UInt8_23_io_deq_valid : _T_5095 ? _Queue2_UInt8_22_io_deq_valid : _T_5094 ? _Queue2_UInt8_21_io_deq_valid : _T_5093 ? _Queue2_UInt8_20_io_deq_valid : _T_5092 ? _Queue2_UInt8_19_io_deq_valid : _T_5091 ? _Queue2_UInt8_18_io_deq_valid : _T_5090 ? _Queue2_UInt8_17_io_deq_valid : _T_5089 ? _Queue2_UInt8_16_io_deq_valid : _T_5088 ? _Queue2_UInt8_15_io_deq_valid : _T_5087 ? _Queue2_UInt8_14_io_deq_valid : _T_5086 ? _Queue2_UInt8_13_io_deq_valid : _T_5085 ? _Queue2_UInt8_12_io_deq_valid : _T_5084 ? _Queue2_UInt8_11_io_deq_valid : _T_5083 ? _Queue2_UInt8_10_io_deq_valid : _T_5082 ? _Queue2_UInt8_9_io_deq_valid : _T_5081 ? _Queue2_UInt8_8_io_deq_valid : _T_5080 ? _Queue2_UInt8_7_io_deq_valid : _T_5079 ? _Queue2_UInt8_6_io_deq_valid : _T_5078 ? _Queue2_UInt8_5_io_deq_valid : _T_5077 ? _Queue2_UInt8_4_io_deq_valid : _T_5076 ? _Queue2_UInt8_3_io_deq_valid : _T_5075 ? _Queue2_UInt8_2_io_deq_valid : _T_5074 ? _Queue2_UInt8_1_io_deq_valid : _T_5073 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_114 = _remapindex_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_24 = _GEN_114[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5105 = remapindex_24 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5106 = remapindex_24 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5107 = remapindex_24 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5108 = remapindex_24 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5109 = remapindex_24 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5110 = remapindex_24 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5111 = remapindex_24 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5112 = remapindex_24 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5113 = remapindex_24 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5114 = remapindex_24 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5115 = remapindex_24 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5116 = remapindex_24 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5117 = remapindex_24 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5118 = remapindex_24 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5119 = remapindex_24 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5120 = remapindex_24 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5121 = remapindex_24 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5122 = remapindex_24 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5123 = remapindex_24 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5124 = remapindex_24 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5125 = remapindex_24 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5126 = remapindex_24 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5127 = remapindex_24 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5128 = remapindex_24 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5129 = remapindex_24 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5130 = remapindex_24 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5131 = remapindex_24 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5132 = remapindex_24 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5133 = remapindex_24 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5134 = remapindex_24 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5135 = remapindex_24 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5136 = remapindex_24 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_24 = _T_5136 ? _Queue2_UInt8_31_io_deq_bits : _T_5135 ? _Queue2_UInt8_30_io_deq_bits : _T_5134 ? _Queue2_UInt8_29_io_deq_bits : _T_5133 ? _Queue2_UInt8_28_io_deq_bits : _T_5132 ? _Queue2_UInt8_27_io_deq_bits : _T_5131 ? _Queue2_UInt8_26_io_deq_bits : _T_5130 ? _Queue2_UInt8_25_io_deq_bits : _T_5129 ? _Queue2_UInt8_24_io_deq_bits : _T_5128 ? _Queue2_UInt8_23_io_deq_bits : _T_5127 ? _Queue2_UInt8_22_io_deq_bits : _T_5126 ? _Queue2_UInt8_21_io_deq_bits : _T_5125 ? _Queue2_UInt8_20_io_deq_bits : _T_5124 ? _Queue2_UInt8_19_io_deq_bits : _T_5123 ? _Queue2_UInt8_18_io_deq_bits : _T_5122 ? _Queue2_UInt8_17_io_deq_bits : _T_5121 ? _Queue2_UInt8_16_io_deq_bits : _T_5120 ? _Queue2_UInt8_15_io_deq_bits : _T_5119 ? _Queue2_UInt8_14_io_deq_bits : _T_5118 ? _Queue2_UInt8_13_io_deq_bits : _T_5117 ? _Queue2_UInt8_12_io_deq_bits : _T_5116 ? _Queue2_UInt8_11_io_deq_bits : _T_5115 ? _Queue2_UInt8_10_io_deq_bits : _T_5114 ? _Queue2_UInt8_9_io_deq_bits : _T_5113 ? _Queue2_UInt8_8_io_deq_bits : _T_5112 ? _Queue2_UInt8_7_io_deq_bits : _T_5111 ? _Queue2_UInt8_6_io_deq_bits : _T_5110 ? _Queue2_UInt8_5_io_deq_bits : _T_5109 ? _Queue2_UInt8_4_io_deq_bits : _T_5108 ? _Queue2_UInt8_3_io_deq_bits : _T_5107 ? _Queue2_UInt8_2_io_deq_bits : _T_5106 ? _Queue2_UInt8_1_io_deq_bits : _T_5105 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_24 = _T_5136 ? _Queue2_UInt8_31_io_deq_valid : _T_5135 ? _Queue2_UInt8_30_io_deq_valid : _T_5134 ? _Queue2_UInt8_29_io_deq_valid : _T_5133 ? _Queue2_UInt8_28_io_deq_valid : _T_5132 ? _Queue2_UInt8_27_io_deq_valid : _T_5131 ? _Queue2_UInt8_26_io_deq_valid : _T_5130 ? _Queue2_UInt8_25_io_deq_valid : _T_5129 ? _Queue2_UInt8_24_io_deq_valid : _T_5128 ? _Queue2_UInt8_23_io_deq_valid : _T_5127 ? _Queue2_UInt8_22_io_deq_valid : _T_5126 ? _Queue2_UInt8_21_io_deq_valid : _T_5125 ? _Queue2_UInt8_20_io_deq_valid : _T_5124 ? _Queue2_UInt8_19_io_deq_valid : _T_5123 ? _Queue2_UInt8_18_io_deq_valid : _T_5122 ? _Queue2_UInt8_17_io_deq_valid : _T_5121 ? _Queue2_UInt8_16_io_deq_valid : _T_5120 ? _Queue2_UInt8_15_io_deq_valid : _T_5119 ? _Queue2_UInt8_14_io_deq_valid : _T_5118 ? _Queue2_UInt8_13_io_deq_valid : _T_5117 ? _Queue2_UInt8_12_io_deq_valid : _T_5116 ? _Queue2_UInt8_11_io_deq_valid : _T_5115 ? _Queue2_UInt8_10_io_deq_valid : _T_5114 ? _Queue2_UInt8_9_io_deq_valid : _T_5113 ? _Queue2_UInt8_8_io_deq_valid : _T_5112 ? _Queue2_UInt8_7_io_deq_valid : _T_5111 ? _Queue2_UInt8_6_io_deq_valid : _T_5110 ? _Queue2_UInt8_5_io_deq_valid : _T_5109 ? _Queue2_UInt8_4_io_deq_valid : _T_5108 ? _Queue2_UInt8_3_io_deq_valid : _T_5107 ? _Queue2_UInt8_2_io_deq_valid : _T_5106 ? _Queue2_UInt8_1_io_deq_valid : _T_5105 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_115 = _remapindex_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_25 = _GEN_115[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5137 = remapindex_25 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5138 = remapindex_25 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5139 = remapindex_25 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5140 = remapindex_25 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5141 = remapindex_25 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5142 = remapindex_25 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5143 = remapindex_25 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5144 = remapindex_25 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5145 = remapindex_25 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5146 = remapindex_25 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5147 = remapindex_25 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5148 = remapindex_25 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5149 = remapindex_25 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5150 = remapindex_25 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5151 = remapindex_25 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5152 = remapindex_25 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5153 = remapindex_25 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5154 = remapindex_25 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5155 = remapindex_25 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5156 = remapindex_25 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5157 = remapindex_25 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5158 = remapindex_25 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5159 = remapindex_25 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5160 = remapindex_25 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5161 = remapindex_25 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5162 = remapindex_25 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5163 = remapindex_25 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5164 = remapindex_25 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5165 = remapindex_25 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5166 = remapindex_25 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5167 = remapindex_25 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5168 = remapindex_25 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_25 = _T_5168 ? _Queue2_UInt8_31_io_deq_bits : _T_5167 ? _Queue2_UInt8_30_io_deq_bits : _T_5166 ? _Queue2_UInt8_29_io_deq_bits : _T_5165 ? _Queue2_UInt8_28_io_deq_bits : _T_5164 ? _Queue2_UInt8_27_io_deq_bits : _T_5163 ? _Queue2_UInt8_26_io_deq_bits : _T_5162 ? _Queue2_UInt8_25_io_deq_bits : _T_5161 ? _Queue2_UInt8_24_io_deq_bits : _T_5160 ? _Queue2_UInt8_23_io_deq_bits : _T_5159 ? _Queue2_UInt8_22_io_deq_bits : _T_5158 ? _Queue2_UInt8_21_io_deq_bits : _T_5157 ? _Queue2_UInt8_20_io_deq_bits : _T_5156 ? _Queue2_UInt8_19_io_deq_bits : _T_5155 ? _Queue2_UInt8_18_io_deq_bits : _T_5154 ? _Queue2_UInt8_17_io_deq_bits : _T_5153 ? _Queue2_UInt8_16_io_deq_bits : _T_5152 ? _Queue2_UInt8_15_io_deq_bits : _T_5151 ? _Queue2_UInt8_14_io_deq_bits : _T_5150 ? _Queue2_UInt8_13_io_deq_bits : _T_5149 ? _Queue2_UInt8_12_io_deq_bits : _T_5148 ? _Queue2_UInt8_11_io_deq_bits : _T_5147 ? _Queue2_UInt8_10_io_deq_bits : _T_5146 ? _Queue2_UInt8_9_io_deq_bits : _T_5145 ? _Queue2_UInt8_8_io_deq_bits : _T_5144 ? _Queue2_UInt8_7_io_deq_bits : _T_5143 ? _Queue2_UInt8_6_io_deq_bits : _T_5142 ? _Queue2_UInt8_5_io_deq_bits : _T_5141 ? _Queue2_UInt8_4_io_deq_bits : _T_5140 ? _Queue2_UInt8_3_io_deq_bits : _T_5139 ? _Queue2_UInt8_2_io_deq_bits : _T_5138 ? _Queue2_UInt8_1_io_deq_bits : _T_5137 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_25 = _T_5168 ? _Queue2_UInt8_31_io_deq_valid : _T_5167 ? _Queue2_UInt8_30_io_deq_valid : _T_5166 ? _Queue2_UInt8_29_io_deq_valid : _T_5165 ? _Queue2_UInt8_28_io_deq_valid : _T_5164 ? _Queue2_UInt8_27_io_deq_valid : _T_5163 ? _Queue2_UInt8_26_io_deq_valid : _T_5162 ? _Queue2_UInt8_25_io_deq_valid : _T_5161 ? _Queue2_UInt8_24_io_deq_valid : _T_5160 ? _Queue2_UInt8_23_io_deq_valid : _T_5159 ? _Queue2_UInt8_22_io_deq_valid : _T_5158 ? _Queue2_UInt8_21_io_deq_valid : _T_5157 ? _Queue2_UInt8_20_io_deq_valid : _T_5156 ? _Queue2_UInt8_19_io_deq_valid : _T_5155 ? _Queue2_UInt8_18_io_deq_valid : _T_5154 ? _Queue2_UInt8_17_io_deq_valid : _T_5153 ? _Queue2_UInt8_16_io_deq_valid : _T_5152 ? _Queue2_UInt8_15_io_deq_valid : _T_5151 ? _Queue2_UInt8_14_io_deq_valid : _T_5150 ? _Queue2_UInt8_13_io_deq_valid : _T_5149 ? _Queue2_UInt8_12_io_deq_valid : _T_5148 ? _Queue2_UInt8_11_io_deq_valid : _T_5147 ? _Queue2_UInt8_10_io_deq_valid : _T_5146 ? _Queue2_UInt8_9_io_deq_valid : _T_5145 ? _Queue2_UInt8_8_io_deq_valid : _T_5144 ? _Queue2_UInt8_7_io_deq_valid : _T_5143 ? _Queue2_UInt8_6_io_deq_valid : _T_5142 ? _Queue2_UInt8_5_io_deq_valid : _T_5141 ? _Queue2_UInt8_4_io_deq_valid : _T_5140 ? _Queue2_UInt8_3_io_deq_valid : _T_5139 ? _Queue2_UInt8_2_io_deq_valid : _T_5138 ? _Queue2_UInt8_1_io_deq_valid : _T_5137 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_116 = _remapindex_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_26 = _GEN_116[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5169 = remapindex_26 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5170 = remapindex_26 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5171 = remapindex_26 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5172 = remapindex_26 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5173 = remapindex_26 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5174 = remapindex_26 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5175 = remapindex_26 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5176 = remapindex_26 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5177 = remapindex_26 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5178 = remapindex_26 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5179 = remapindex_26 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5180 = remapindex_26 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5181 = remapindex_26 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5182 = remapindex_26 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5183 = remapindex_26 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5184 = remapindex_26 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5185 = remapindex_26 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5186 = remapindex_26 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5187 = remapindex_26 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5188 = remapindex_26 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5189 = remapindex_26 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5190 = remapindex_26 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5191 = remapindex_26 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5192 = remapindex_26 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5193 = remapindex_26 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5194 = remapindex_26 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5195 = remapindex_26 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5196 = remapindex_26 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5197 = remapindex_26 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5198 = remapindex_26 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5199 = remapindex_26 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5200 = remapindex_26 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_26 = _T_5200 ? _Queue2_UInt8_31_io_deq_bits : _T_5199 ? _Queue2_UInt8_30_io_deq_bits : _T_5198 ? _Queue2_UInt8_29_io_deq_bits : _T_5197 ? _Queue2_UInt8_28_io_deq_bits : _T_5196 ? _Queue2_UInt8_27_io_deq_bits : _T_5195 ? _Queue2_UInt8_26_io_deq_bits : _T_5194 ? _Queue2_UInt8_25_io_deq_bits : _T_5193 ? _Queue2_UInt8_24_io_deq_bits : _T_5192 ? _Queue2_UInt8_23_io_deq_bits : _T_5191 ? _Queue2_UInt8_22_io_deq_bits : _T_5190 ? _Queue2_UInt8_21_io_deq_bits : _T_5189 ? _Queue2_UInt8_20_io_deq_bits : _T_5188 ? _Queue2_UInt8_19_io_deq_bits : _T_5187 ? _Queue2_UInt8_18_io_deq_bits : _T_5186 ? _Queue2_UInt8_17_io_deq_bits : _T_5185 ? _Queue2_UInt8_16_io_deq_bits : _T_5184 ? _Queue2_UInt8_15_io_deq_bits : _T_5183 ? _Queue2_UInt8_14_io_deq_bits : _T_5182 ? _Queue2_UInt8_13_io_deq_bits : _T_5181 ? _Queue2_UInt8_12_io_deq_bits : _T_5180 ? _Queue2_UInt8_11_io_deq_bits : _T_5179 ? _Queue2_UInt8_10_io_deq_bits : _T_5178 ? _Queue2_UInt8_9_io_deq_bits : _T_5177 ? _Queue2_UInt8_8_io_deq_bits : _T_5176 ? _Queue2_UInt8_7_io_deq_bits : _T_5175 ? _Queue2_UInt8_6_io_deq_bits : _T_5174 ? _Queue2_UInt8_5_io_deq_bits : _T_5173 ? _Queue2_UInt8_4_io_deq_bits : _T_5172 ? _Queue2_UInt8_3_io_deq_bits : _T_5171 ? _Queue2_UInt8_2_io_deq_bits : _T_5170 ? _Queue2_UInt8_1_io_deq_bits : _T_5169 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_26 = _T_5200 ? _Queue2_UInt8_31_io_deq_valid : _T_5199 ? _Queue2_UInt8_30_io_deq_valid : _T_5198 ? _Queue2_UInt8_29_io_deq_valid : _T_5197 ? _Queue2_UInt8_28_io_deq_valid : _T_5196 ? _Queue2_UInt8_27_io_deq_valid : _T_5195 ? _Queue2_UInt8_26_io_deq_valid : _T_5194 ? _Queue2_UInt8_25_io_deq_valid : _T_5193 ? _Queue2_UInt8_24_io_deq_valid : _T_5192 ? _Queue2_UInt8_23_io_deq_valid : _T_5191 ? _Queue2_UInt8_22_io_deq_valid : _T_5190 ? _Queue2_UInt8_21_io_deq_valid : _T_5189 ? _Queue2_UInt8_20_io_deq_valid : _T_5188 ? _Queue2_UInt8_19_io_deq_valid : _T_5187 ? _Queue2_UInt8_18_io_deq_valid : _T_5186 ? _Queue2_UInt8_17_io_deq_valid : _T_5185 ? _Queue2_UInt8_16_io_deq_valid : _T_5184 ? _Queue2_UInt8_15_io_deq_valid : _T_5183 ? _Queue2_UInt8_14_io_deq_valid : _T_5182 ? _Queue2_UInt8_13_io_deq_valid : _T_5181 ? _Queue2_UInt8_12_io_deq_valid : _T_5180 ? _Queue2_UInt8_11_io_deq_valid : _T_5179 ? _Queue2_UInt8_10_io_deq_valid : _T_5178 ? _Queue2_UInt8_9_io_deq_valid : _T_5177 ? _Queue2_UInt8_8_io_deq_valid : _T_5176 ? _Queue2_UInt8_7_io_deq_valid : _T_5175 ? _Queue2_UInt8_6_io_deq_valid : _T_5174 ? _Queue2_UInt8_5_io_deq_valid : _T_5173 ? _Queue2_UInt8_4_io_deq_valid : _T_5172 ? _Queue2_UInt8_3_io_deq_valid : _T_5171 ? _Queue2_UInt8_2_io_deq_valid : _T_5170 ? _Queue2_UInt8_1_io_deq_valid : _T_5169 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_117 = _remapindex_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_27 = _GEN_117[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5201 = remapindex_27 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5202 = remapindex_27 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5203 = remapindex_27 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5204 = remapindex_27 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5205 = remapindex_27 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5206 = remapindex_27 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5207 = remapindex_27 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5208 = remapindex_27 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5209 = remapindex_27 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5210 = remapindex_27 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5211 = remapindex_27 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5212 = remapindex_27 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5213 = remapindex_27 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5214 = remapindex_27 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5215 = remapindex_27 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5216 = remapindex_27 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5217 = remapindex_27 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5218 = remapindex_27 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5219 = remapindex_27 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5220 = remapindex_27 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5221 = remapindex_27 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5222 = remapindex_27 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5223 = remapindex_27 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5224 = remapindex_27 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5225 = remapindex_27 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5226 = remapindex_27 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5227 = remapindex_27 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5228 = remapindex_27 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5229 = remapindex_27 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5230 = remapindex_27 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5231 = remapindex_27 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5232 = remapindex_27 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_27 = _T_5232 ? _Queue2_UInt8_31_io_deq_bits : _T_5231 ? _Queue2_UInt8_30_io_deq_bits : _T_5230 ? _Queue2_UInt8_29_io_deq_bits : _T_5229 ? _Queue2_UInt8_28_io_deq_bits : _T_5228 ? _Queue2_UInt8_27_io_deq_bits : _T_5227 ? _Queue2_UInt8_26_io_deq_bits : _T_5226 ? _Queue2_UInt8_25_io_deq_bits : _T_5225 ? _Queue2_UInt8_24_io_deq_bits : _T_5224 ? _Queue2_UInt8_23_io_deq_bits : _T_5223 ? _Queue2_UInt8_22_io_deq_bits : _T_5222 ? _Queue2_UInt8_21_io_deq_bits : _T_5221 ? _Queue2_UInt8_20_io_deq_bits : _T_5220 ? _Queue2_UInt8_19_io_deq_bits : _T_5219 ? _Queue2_UInt8_18_io_deq_bits : _T_5218 ? _Queue2_UInt8_17_io_deq_bits : _T_5217 ? _Queue2_UInt8_16_io_deq_bits : _T_5216 ? _Queue2_UInt8_15_io_deq_bits : _T_5215 ? _Queue2_UInt8_14_io_deq_bits : _T_5214 ? _Queue2_UInt8_13_io_deq_bits : _T_5213 ? _Queue2_UInt8_12_io_deq_bits : _T_5212 ? _Queue2_UInt8_11_io_deq_bits : _T_5211 ? _Queue2_UInt8_10_io_deq_bits : _T_5210 ? _Queue2_UInt8_9_io_deq_bits : _T_5209 ? _Queue2_UInt8_8_io_deq_bits : _T_5208 ? _Queue2_UInt8_7_io_deq_bits : _T_5207 ? _Queue2_UInt8_6_io_deq_bits : _T_5206 ? _Queue2_UInt8_5_io_deq_bits : _T_5205 ? _Queue2_UInt8_4_io_deq_bits : _T_5204 ? _Queue2_UInt8_3_io_deq_bits : _T_5203 ? _Queue2_UInt8_2_io_deq_bits : _T_5202 ? _Queue2_UInt8_1_io_deq_bits : _T_5201 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_27 = _T_5232 ? _Queue2_UInt8_31_io_deq_valid : _T_5231 ? _Queue2_UInt8_30_io_deq_valid : _T_5230 ? _Queue2_UInt8_29_io_deq_valid : _T_5229 ? _Queue2_UInt8_28_io_deq_valid : _T_5228 ? _Queue2_UInt8_27_io_deq_valid : _T_5227 ? _Queue2_UInt8_26_io_deq_valid : _T_5226 ? _Queue2_UInt8_25_io_deq_valid : _T_5225 ? _Queue2_UInt8_24_io_deq_valid : _T_5224 ? _Queue2_UInt8_23_io_deq_valid : _T_5223 ? _Queue2_UInt8_22_io_deq_valid : _T_5222 ? _Queue2_UInt8_21_io_deq_valid : _T_5221 ? _Queue2_UInt8_20_io_deq_valid : _T_5220 ? _Queue2_UInt8_19_io_deq_valid : _T_5219 ? _Queue2_UInt8_18_io_deq_valid : _T_5218 ? _Queue2_UInt8_17_io_deq_valid : _T_5217 ? _Queue2_UInt8_16_io_deq_valid : _T_5216 ? _Queue2_UInt8_15_io_deq_valid : _T_5215 ? _Queue2_UInt8_14_io_deq_valid : _T_5214 ? _Queue2_UInt8_13_io_deq_valid : _T_5213 ? _Queue2_UInt8_12_io_deq_valid : _T_5212 ? _Queue2_UInt8_11_io_deq_valid : _T_5211 ? _Queue2_UInt8_10_io_deq_valid : _T_5210 ? _Queue2_UInt8_9_io_deq_valid : _T_5209 ? _Queue2_UInt8_8_io_deq_valid : _T_5208 ? _Queue2_UInt8_7_io_deq_valid : _T_5207 ? _Queue2_UInt8_6_io_deq_valid : _T_5206 ? _Queue2_UInt8_5_io_deq_valid : _T_5205 ? _Queue2_UInt8_4_io_deq_valid : _T_5204 ? _Queue2_UInt8_3_io_deq_valid : _T_5203 ? _Queue2_UInt8_2_io_deq_valid : _T_5202 ? _Queue2_UInt8_1_io_deq_valid : _T_5201 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_118 = _remapindex_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_28 = _GEN_118[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5233 = remapindex_28 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5234 = remapindex_28 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5235 = remapindex_28 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5236 = remapindex_28 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5237 = remapindex_28 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5238 = remapindex_28 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5239 = remapindex_28 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5240 = remapindex_28 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5241 = remapindex_28 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5242 = remapindex_28 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5243 = remapindex_28 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5244 = remapindex_28 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5245 = remapindex_28 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5246 = remapindex_28 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5247 = remapindex_28 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5248 = remapindex_28 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5249 = remapindex_28 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5250 = remapindex_28 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5251 = remapindex_28 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5252 = remapindex_28 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5253 = remapindex_28 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5254 = remapindex_28 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5255 = remapindex_28 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5256 = remapindex_28 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5257 = remapindex_28 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5258 = remapindex_28 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5259 = remapindex_28 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5260 = remapindex_28 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5261 = remapindex_28 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5262 = remapindex_28 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5263 = remapindex_28 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5264 = remapindex_28 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_28 = _T_5264 ? _Queue2_UInt8_31_io_deq_bits : _T_5263 ? _Queue2_UInt8_30_io_deq_bits : _T_5262 ? _Queue2_UInt8_29_io_deq_bits : _T_5261 ? _Queue2_UInt8_28_io_deq_bits : _T_5260 ? _Queue2_UInt8_27_io_deq_bits : _T_5259 ? _Queue2_UInt8_26_io_deq_bits : _T_5258 ? _Queue2_UInt8_25_io_deq_bits : _T_5257 ? _Queue2_UInt8_24_io_deq_bits : _T_5256 ? _Queue2_UInt8_23_io_deq_bits : _T_5255 ? _Queue2_UInt8_22_io_deq_bits : _T_5254 ? _Queue2_UInt8_21_io_deq_bits : _T_5253 ? _Queue2_UInt8_20_io_deq_bits : _T_5252 ? _Queue2_UInt8_19_io_deq_bits : _T_5251 ? _Queue2_UInt8_18_io_deq_bits : _T_5250 ? _Queue2_UInt8_17_io_deq_bits : _T_5249 ? _Queue2_UInt8_16_io_deq_bits : _T_5248 ? _Queue2_UInt8_15_io_deq_bits : _T_5247 ? _Queue2_UInt8_14_io_deq_bits : _T_5246 ? _Queue2_UInt8_13_io_deq_bits : _T_5245 ? _Queue2_UInt8_12_io_deq_bits : _T_5244 ? _Queue2_UInt8_11_io_deq_bits : _T_5243 ? _Queue2_UInt8_10_io_deq_bits : _T_5242 ? _Queue2_UInt8_9_io_deq_bits : _T_5241 ? _Queue2_UInt8_8_io_deq_bits : _T_5240 ? _Queue2_UInt8_7_io_deq_bits : _T_5239 ? _Queue2_UInt8_6_io_deq_bits : _T_5238 ? _Queue2_UInt8_5_io_deq_bits : _T_5237 ? _Queue2_UInt8_4_io_deq_bits : _T_5236 ? _Queue2_UInt8_3_io_deq_bits : _T_5235 ? _Queue2_UInt8_2_io_deq_bits : _T_5234 ? _Queue2_UInt8_1_io_deq_bits : _T_5233 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_28 = _T_5264 ? _Queue2_UInt8_31_io_deq_valid : _T_5263 ? _Queue2_UInt8_30_io_deq_valid : _T_5262 ? _Queue2_UInt8_29_io_deq_valid : _T_5261 ? _Queue2_UInt8_28_io_deq_valid : _T_5260 ? _Queue2_UInt8_27_io_deq_valid : _T_5259 ? _Queue2_UInt8_26_io_deq_valid : _T_5258 ? _Queue2_UInt8_25_io_deq_valid : _T_5257 ? _Queue2_UInt8_24_io_deq_valid : _T_5256 ? _Queue2_UInt8_23_io_deq_valid : _T_5255 ? _Queue2_UInt8_22_io_deq_valid : _T_5254 ? _Queue2_UInt8_21_io_deq_valid : _T_5253 ? _Queue2_UInt8_20_io_deq_valid : _T_5252 ? _Queue2_UInt8_19_io_deq_valid : _T_5251 ? _Queue2_UInt8_18_io_deq_valid : _T_5250 ? _Queue2_UInt8_17_io_deq_valid : _T_5249 ? _Queue2_UInt8_16_io_deq_valid : _T_5248 ? _Queue2_UInt8_15_io_deq_valid : _T_5247 ? _Queue2_UInt8_14_io_deq_valid : _T_5246 ? _Queue2_UInt8_13_io_deq_valid : _T_5245 ? _Queue2_UInt8_12_io_deq_valid : _T_5244 ? _Queue2_UInt8_11_io_deq_valid : _T_5243 ? _Queue2_UInt8_10_io_deq_valid : _T_5242 ? _Queue2_UInt8_9_io_deq_valid : _T_5241 ? _Queue2_UInt8_8_io_deq_valid : _T_5240 ? _Queue2_UInt8_7_io_deq_valid : _T_5239 ? _Queue2_UInt8_6_io_deq_valid : _T_5238 ? _Queue2_UInt8_5_io_deq_valid : _T_5237 ? _Queue2_UInt8_4_io_deq_valid : _T_5236 ? _Queue2_UInt8_3_io_deq_valid : _T_5235 ? _Queue2_UInt8_2_io_deq_valid : _T_5234 ? _Queue2_UInt8_1_io_deq_valid : _T_5233 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_119 = _remapindex_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_29 = _GEN_119[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5265 = remapindex_29 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5266 = remapindex_29 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5267 = remapindex_29 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5268 = remapindex_29 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5269 = remapindex_29 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5270 = remapindex_29 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5271 = remapindex_29 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5272 = remapindex_29 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5273 = remapindex_29 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5274 = remapindex_29 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5275 = remapindex_29 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5276 = remapindex_29 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5277 = remapindex_29 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5278 = remapindex_29 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5279 = remapindex_29 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5280 = remapindex_29 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5281 = remapindex_29 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5282 = remapindex_29 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5283 = remapindex_29 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5284 = remapindex_29 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5285 = remapindex_29 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5286 = remapindex_29 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5287 = remapindex_29 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5288 = remapindex_29 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5289 = remapindex_29 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5290 = remapindex_29 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5291 = remapindex_29 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5292 = remapindex_29 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5293 = remapindex_29 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5294 = remapindex_29 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5295 = remapindex_29 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5296 = remapindex_29 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_29 = _T_5296 ? _Queue2_UInt8_31_io_deq_bits : _T_5295 ? _Queue2_UInt8_30_io_deq_bits : _T_5294 ? _Queue2_UInt8_29_io_deq_bits : _T_5293 ? _Queue2_UInt8_28_io_deq_bits : _T_5292 ? _Queue2_UInt8_27_io_deq_bits : _T_5291 ? _Queue2_UInt8_26_io_deq_bits : _T_5290 ? _Queue2_UInt8_25_io_deq_bits : _T_5289 ? _Queue2_UInt8_24_io_deq_bits : _T_5288 ? _Queue2_UInt8_23_io_deq_bits : _T_5287 ? _Queue2_UInt8_22_io_deq_bits : _T_5286 ? _Queue2_UInt8_21_io_deq_bits : _T_5285 ? _Queue2_UInt8_20_io_deq_bits : _T_5284 ? _Queue2_UInt8_19_io_deq_bits : _T_5283 ? _Queue2_UInt8_18_io_deq_bits : _T_5282 ? _Queue2_UInt8_17_io_deq_bits : _T_5281 ? _Queue2_UInt8_16_io_deq_bits : _T_5280 ? _Queue2_UInt8_15_io_deq_bits : _T_5279 ? _Queue2_UInt8_14_io_deq_bits : _T_5278 ? _Queue2_UInt8_13_io_deq_bits : _T_5277 ? _Queue2_UInt8_12_io_deq_bits : _T_5276 ? _Queue2_UInt8_11_io_deq_bits : _T_5275 ? _Queue2_UInt8_10_io_deq_bits : _T_5274 ? _Queue2_UInt8_9_io_deq_bits : _T_5273 ? _Queue2_UInt8_8_io_deq_bits : _T_5272 ? _Queue2_UInt8_7_io_deq_bits : _T_5271 ? _Queue2_UInt8_6_io_deq_bits : _T_5270 ? _Queue2_UInt8_5_io_deq_bits : _T_5269 ? _Queue2_UInt8_4_io_deq_bits : _T_5268 ? _Queue2_UInt8_3_io_deq_bits : _T_5267 ? _Queue2_UInt8_2_io_deq_bits : _T_5266 ? _Queue2_UInt8_1_io_deq_bits : _T_5265 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_29 = _T_5296 ? _Queue2_UInt8_31_io_deq_valid : _T_5295 ? _Queue2_UInt8_30_io_deq_valid : _T_5294 ? _Queue2_UInt8_29_io_deq_valid : _T_5293 ? _Queue2_UInt8_28_io_deq_valid : _T_5292 ? _Queue2_UInt8_27_io_deq_valid : _T_5291 ? _Queue2_UInt8_26_io_deq_valid : _T_5290 ? _Queue2_UInt8_25_io_deq_valid : _T_5289 ? _Queue2_UInt8_24_io_deq_valid : _T_5288 ? _Queue2_UInt8_23_io_deq_valid : _T_5287 ? _Queue2_UInt8_22_io_deq_valid : _T_5286 ? _Queue2_UInt8_21_io_deq_valid : _T_5285 ? _Queue2_UInt8_20_io_deq_valid : _T_5284 ? _Queue2_UInt8_19_io_deq_valid : _T_5283 ? _Queue2_UInt8_18_io_deq_valid : _T_5282 ? _Queue2_UInt8_17_io_deq_valid : _T_5281 ? _Queue2_UInt8_16_io_deq_valid : _T_5280 ? _Queue2_UInt8_15_io_deq_valid : _T_5279 ? _Queue2_UInt8_14_io_deq_valid : _T_5278 ? _Queue2_UInt8_13_io_deq_valid : _T_5277 ? _Queue2_UInt8_12_io_deq_valid : _T_5276 ? _Queue2_UInt8_11_io_deq_valid : _T_5275 ? _Queue2_UInt8_10_io_deq_valid : _T_5274 ? _Queue2_UInt8_9_io_deq_valid : _T_5273 ? _Queue2_UInt8_8_io_deq_valid : _T_5272 ? _Queue2_UInt8_7_io_deq_valid : _T_5271 ? _Queue2_UInt8_6_io_deq_valid : _T_5270 ? _Queue2_UInt8_5_io_deq_valid : _T_5269 ? _Queue2_UInt8_4_io_deq_valid : _T_5268 ? _Queue2_UInt8_3_io_deq_valid : _T_5267 ? _Queue2_UInt8_2_io_deq_valid : _T_5266 ? _Queue2_UInt8_1_io_deq_valid : _T_5265 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_120 = _remapindex_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_30 = _GEN_120[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5297 = remapindex_30 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5298 = remapindex_30 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5299 = remapindex_30 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5300 = remapindex_30 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5301 = remapindex_30 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5302 = remapindex_30 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5303 = remapindex_30 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5304 = remapindex_30 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5305 = remapindex_30 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5306 = remapindex_30 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5307 = remapindex_30 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5308 = remapindex_30 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5309 = remapindex_30 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5310 = remapindex_30 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5311 = remapindex_30 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5312 = remapindex_30 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5313 = remapindex_30 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5314 = remapindex_30 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5315 = remapindex_30 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5316 = remapindex_30 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5317 = remapindex_30 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5318 = remapindex_30 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5319 = remapindex_30 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5320 = remapindex_30 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5321 = remapindex_30 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5322 = remapindex_30 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5323 = remapindex_30 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5324 = remapindex_30 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5325 = remapindex_30 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5326 = remapindex_30 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5327 = remapindex_30 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5328 = remapindex_30 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_30 = _T_5328 ? _Queue2_UInt8_31_io_deq_bits : _T_5327 ? _Queue2_UInt8_30_io_deq_bits : _T_5326 ? _Queue2_UInt8_29_io_deq_bits : _T_5325 ? _Queue2_UInt8_28_io_deq_bits : _T_5324 ? _Queue2_UInt8_27_io_deq_bits : _T_5323 ? _Queue2_UInt8_26_io_deq_bits : _T_5322 ? _Queue2_UInt8_25_io_deq_bits : _T_5321 ? _Queue2_UInt8_24_io_deq_bits : _T_5320 ? _Queue2_UInt8_23_io_deq_bits : _T_5319 ? _Queue2_UInt8_22_io_deq_bits : _T_5318 ? _Queue2_UInt8_21_io_deq_bits : _T_5317 ? _Queue2_UInt8_20_io_deq_bits : _T_5316 ? _Queue2_UInt8_19_io_deq_bits : _T_5315 ? _Queue2_UInt8_18_io_deq_bits : _T_5314 ? _Queue2_UInt8_17_io_deq_bits : _T_5313 ? _Queue2_UInt8_16_io_deq_bits : _T_5312 ? _Queue2_UInt8_15_io_deq_bits : _T_5311 ? _Queue2_UInt8_14_io_deq_bits : _T_5310 ? _Queue2_UInt8_13_io_deq_bits : _T_5309 ? _Queue2_UInt8_12_io_deq_bits : _T_5308 ? _Queue2_UInt8_11_io_deq_bits : _T_5307 ? _Queue2_UInt8_10_io_deq_bits : _T_5306 ? _Queue2_UInt8_9_io_deq_bits : _T_5305 ? _Queue2_UInt8_8_io_deq_bits : _T_5304 ? _Queue2_UInt8_7_io_deq_bits : _T_5303 ? _Queue2_UInt8_6_io_deq_bits : _T_5302 ? _Queue2_UInt8_5_io_deq_bits : _T_5301 ? _Queue2_UInt8_4_io_deq_bits : _T_5300 ? _Queue2_UInt8_3_io_deq_bits : _T_5299 ? _Queue2_UInt8_2_io_deq_bits : _T_5298 ? _Queue2_UInt8_1_io_deq_bits : _T_5297 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_30 = _T_5328 ? _Queue2_UInt8_31_io_deq_valid : _T_5327 ? _Queue2_UInt8_30_io_deq_valid : _T_5326 ? _Queue2_UInt8_29_io_deq_valid : _T_5325 ? _Queue2_UInt8_28_io_deq_valid : _T_5324 ? _Queue2_UInt8_27_io_deq_valid : _T_5323 ? _Queue2_UInt8_26_io_deq_valid : _T_5322 ? _Queue2_UInt8_25_io_deq_valid : _T_5321 ? _Queue2_UInt8_24_io_deq_valid : _T_5320 ? _Queue2_UInt8_23_io_deq_valid : _T_5319 ? _Queue2_UInt8_22_io_deq_valid : _T_5318 ? _Queue2_UInt8_21_io_deq_valid : _T_5317 ? _Queue2_UInt8_20_io_deq_valid : _T_5316 ? _Queue2_UInt8_19_io_deq_valid : _T_5315 ? _Queue2_UInt8_18_io_deq_valid : _T_5314 ? _Queue2_UInt8_17_io_deq_valid : _T_5313 ? _Queue2_UInt8_16_io_deq_valid : _T_5312 ? _Queue2_UInt8_15_io_deq_valid : _T_5311 ? _Queue2_UInt8_14_io_deq_valid : _T_5310 ? _Queue2_UInt8_13_io_deq_valid : _T_5309 ? _Queue2_UInt8_12_io_deq_valid : _T_5308 ? _Queue2_UInt8_11_io_deq_valid : _T_5307 ? _Queue2_UInt8_10_io_deq_valid : _T_5306 ? _Queue2_UInt8_9_io_deq_valid : _T_5305 ? _Queue2_UInt8_8_io_deq_valid : _T_5304 ? _Queue2_UInt8_7_io_deq_valid : _T_5303 ? _Queue2_UInt8_6_io_deq_valid : _T_5302 ? _Queue2_UInt8_5_io_deq_valid : _T_5301 ? _Queue2_UInt8_4_io_deq_valid : _T_5300 ? _Queue2_UInt8_3_io_deq_valid : _T_5299 ? _Queue2_UInt8_2_io_deq_valid : _T_5298 ? _Queue2_UInt8_1_io_deq_valid : _T_5297 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_121 = _remapindex_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_31 = _GEN_121[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5329 = remapindex_31 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5330 = remapindex_31 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5331 = remapindex_31 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5332 = remapindex_31 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5333 = remapindex_31 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5334 = remapindex_31 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5335 = remapindex_31 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5336 = remapindex_31 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5337 = remapindex_31 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5338 = remapindex_31 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5339 = remapindex_31 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5340 = remapindex_31 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5341 = remapindex_31 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5342 = remapindex_31 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5343 = remapindex_31 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5344 = remapindex_31 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5345 = remapindex_31 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5346 = remapindex_31 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5347 = remapindex_31 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5348 = remapindex_31 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5349 = remapindex_31 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5350 = remapindex_31 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5351 = remapindex_31 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5352 = remapindex_31 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5353 = remapindex_31 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5354 = remapindex_31 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5355 = remapindex_31 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5356 = remapindex_31 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5357 = remapindex_31 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5358 = remapindex_31 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5359 = remapindex_31 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5360 = remapindex_31 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_31 = _T_5360 ? _Queue2_UInt8_31_io_deq_bits : _T_5359 ? _Queue2_UInt8_30_io_deq_bits : _T_5358 ? _Queue2_UInt8_29_io_deq_bits : _T_5357 ? _Queue2_UInt8_28_io_deq_bits : _T_5356 ? _Queue2_UInt8_27_io_deq_bits : _T_5355 ? _Queue2_UInt8_26_io_deq_bits : _T_5354 ? _Queue2_UInt8_25_io_deq_bits : _T_5353 ? _Queue2_UInt8_24_io_deq_bits : _T_5352 ? _Queue2_UInt8_23_io_deq_bits : _T_5351 ? _Queue2_UInt8_22_io_deq_bits : _T_5350 ? _Queue2_UInt8_21_io_deq_bits : _T_5349 ? _Queue2_UInt8_20_io_deq_bits : _T_5348 ? _Queue2_UInt8_19_io_deq_bits : _T_5347 ? _Queue2_UInt8_18_io_deq_bits : _T_5346 ? _Queue2_UInt8_17_io_deq_bits : _T_5345 ? _Queue2_UInt8_16_io_deq_bits : _T_5344 ? _Queue2_UInt8_15_io_deq_bits : _T_5343 ? _Queue2_UInt8_14_io_deq_bits : _T_5342 ? _Queue2_UInt8_13_io_deq_bits : _T_5341 ? _Queue2_UInt8_12_io_deq_bits : _T_5340 ? _Queue2_UInt8_11_io_deq_bits : _T_5339 ? _Queue2_UInt8_10_io_deq_bits : _T_5338 ? _Queue2_UInt8_9_io_deq_bits : _T_5337 ? _Queue2_UInt8_8_io_deq_bits : _T_5336 ? _Queue2_UInt8_7_io_deq_bits : _T_5335 ? _Queue2_UInt8_6_io_deq_bits : _T_5334 ? _Queue2_UInt8_5_io_deq_bits : _T_5333 ? _Queue2_UInt8_4_io_deq_bits : _T_5332 ? _Queue2_UInt8_3_io_deq_bits : _T_5331 ? _Queue2_UInt8_2_io_deq_bits : _T_5330 ? _Queue2_UInt8_1_io_deq_bits : _T_5329 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_31 = _T_5360 ? _Queue2_UInt8_31_io_deq_valid : _T_5359 ? _Queue2_UInt8_30_io_deq_valid : _T_5358 ? _Queue2_UInt8_29_io_deq_valid : _T_5357 ? _Queue2_UInt8_28_io_deq_valid : _T_5356 ? _Queue2_UInt8_27_io_deq_valid : _T_5355 ? _Queue2_UInt8_26_io_deq_valid : _T_5354 ? _Queue2_UInt8_25_io_deq_valid : _T_5353 ? _Queue2_UInt8_24_io_deq_valid : _T_5352 ? _Queue2_UInt8_23_io_deq_valid : _T_5351 ? _Queue2_UInt8_22_io_deq_valid : _T_5350 ? _Queue2_UInt8_21_io_deq_valid : _T_5349 ? _Queue2_UInt8_20_io_deq_valid : _T_5348 ? _Queue2_UInt8_19_io_deq_valid : _T_5347 ? _Queue2_UInt8_18_io_deq_valid : _T_5346 ? _Queue2_UInt8_17_io_deq_valid : _T_5345 ? _Queue2_UInt8_16_io_deq_valid : _T_5344 ? _Queue2_UInt8_15_io_deq_valid : _T_5343 ? _Queue2_UInt8_14_io_deq_valid : _T_5342 ? _Queue2_UInt8_13_io_deq_valid : _T_5341 ? _Queue2_UInt8_12_io_deq_valid : _T_5340 ? _Queue2_UInt8_11_io_deq_valid : _T_5339 ? _Queue2_UInt8_10_io_deq_valid : _T_5338 ? _Queue2_UInt8_9_io_deq_valid : _T_5337 ? _Queue2_UInt8_8_io_deq_valid : _T_5336 ? _Queue2_UInt8_7_io_deq_valid : _T_5335 ? _Queue2_UInt8_6_io_deq_valid : _T_5334 ? _Queue2_UInt8_5_io_deq_valid : _T_5333 ? _Queue2_UInt8_4_io_deq_valid : _T_5332 ? _Queue2_UInt8_3_io_deq_valid : _T_5331 ? _Queue2_UInt8_2_io_deq_valid : _T_5330 ? _Queue2_UInt8_1_io_deq_valid : _T_5329 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] reg [63:0] backend_bytes_written; // @[ZstdCompressorMemWriter.scala:167:38] wire [64:0] _GEN_122 = {1'h0, backend_bytes_written}; // @[ZstdCompressorMemWriter.scala:167:38, :168:60] wire [64:0] _backend_next_write_addr_T = {1'h0, _dest_info_Q_io_deq_bits_op} + _GEN_122; // @[ZstdCompressorMemWriter.scala:39:27, :168:60] wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[ZstdCompressorMemWriter.scala:168:60] wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_122; // @[ZstdCompressorMemWriter.scala:52:26, :168:60, :171:28] wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[ZstdCompressorMemWriter.scala:171:28] wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[ZstdCompressorMemWriter.scala:52:26, :170:25, :171:28] wire _throttle_end_writeable_T = \|(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49] wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53] wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53, :183:55] wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55] wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55, :184:57] wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57] wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57, :185:59] wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59] wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59, :186:61] wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61] wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61, :187:63] wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[ZstdCompressorMemWriter.scala:179:{48,61}] wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[ZstdCompressorMemWriter.scala:178:{46,59}, :179:48] wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[ZstdCompressorMemWriter.scala:177:{44,57}, :178:46] wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[ZstdCompressorMemWriter.scala:176:{42,55}, :177:44] wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[ZstdCompressorMemWriter.scala:175:{40,53}, :176:42] wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[ZstdCompressorMemWriter.scala:174:{35,49}, :175:40] wire _throttle_end_writeable_log2_T = \|(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49, :182:54] wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[ZstdCompressorMemWriter.scala:186:{48,61}] wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[ZstdCompressorMemWriter.scala:185:{46,59}, :186:48] wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:184:{44,57}, :185:46] wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[ZstdCompressorMemWriter.scala:183:{42,55}, :184:44] wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[ZstdCompressorMemWriter.scala:182:{40,54}, :183:42] wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66] wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66, :198:71] wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68] wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68, :199:72] wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70] wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70, :200:74] wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72] wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72, :201:76] wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74] wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74, :202:78] wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[ZstdCompressorMemWriter.scala:195:{50,74}] wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[ZstdCompressorMemWriter.scala:194:{48,72}, :195:50] wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[ZstdCompressorMemWriter.scala:193:{46,70}, :194:48] wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[ZstdCompressorMemWriter.scala:192:{44,68}, :193:46] wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[ZstdCompressorMemWriter.scala:191:{42,66}, :192:44] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[ZstdCompressorMemWriter.scala:202:{54,78}] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[ZstdCompressorMemWriter.scala:201:{52,76}, :202:54] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[ZstdCompressorMemWriter.scala:200:{50,74}, :201:52] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[ZstdCompressorMemWriter.scala:199:{48,72}, :200:50] wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:198:{47,71}, :199:48] wire _count_valids_largest_aligned_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54] wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54, :213:59] wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55] wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55, :214:61] wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57] wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57, :215:63] wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59] wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59, :216:65] wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61] wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61, :217:67] wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63] wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63, :218:69] wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[ZstdCompressorMemWriter.scala:210:{50,63}] wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[ZstdCompressorMemWriter.scala:209:{48,61}, :210:50] wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[ZstdCompressorMemWriter.scala:208:{46,59}, :209:48] wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[ZstdCompressorMemWriter.scala:207:{44,57}, :208:46] wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[ZstdCompressorMemWriter.scala:206:{42,55}, :207:44] wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[ZstdCompressorMemWriter.scala:205:{41,54}, :206:42] wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[ZstdCompressorMemWriter.scala:217:{54,67}] wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[ZstdCompressorMemWriter.scala:216:{52,65}, :217:54] wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[ZstdCompressorMemWriter.scala:215:{50,63}, :216:52] wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[ZstdCompressorMemWriter.scala:214:{48,61}, :215:50] wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[ZstdCompressorMemWriter.scala:213:{46,59}, :214:48] wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[ZstdCompressorMemWriter.scala:191:42, :205:41, :225:35] wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:39] wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:{8,39}] wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:38] wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:{8,38}] wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[ZstdCompressorMemWriter.scala:224:27, :225:35, :226:8, :229:8] wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire enough_data = \|bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36] wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[ZstdCompressorMemWriter.scala:198:47, :213:46, :238:40] wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:44] wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:{8,44}] wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:43] wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:{8,43}] wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[ZstdCompressorMemWriter.scala:237:32, :238:40, :239:8, :242:8] wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[ZstdCompressorMemWriter.scala:52:26, :167:38, :247:79] wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[ZstdCompressorMemWriter.scala:52:26, :247:{52,79}] wire _remapVecReadys_0_T = \|bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36, :264:43] wire _T_5363 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_1_T = \|(bytes_to_write[5:1]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_3_T = \|(bytes_to_write[5:2]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_7_T = \|(bytes_to_write[5:3]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_15_T = \|(bytes_to_write[5:4]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_31_T = bytes_to_write[5]; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _T_5365 = _T_5363 & ~write_ptr_override & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:153:33, :224:27, :268:43] wire [6:0] _GEN_123 = _read_start_index_T % 7'h20; // @[ZstdCompressorMemWriter.scala:268:{43,62}] wire [5:0] _read_start_index_T_1 = _GEN_123[5:0]; // @[ZstdCompressorMemWriter.scala:268:62] wire [64:0] _backend_bytes_written_T = _GEN_122 + {59'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:168:60, :224:27, :269:52] wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[ZstdCompressorMemWriter.scala:269:52] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53] wire _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _io_l2io_req_valid_T_2 = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[Misc.scala:26:53] wire _io_l2io_req_valid_T_3 = _io_l2io_req_valid_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] assign _io_l2io_req_valid_T_4 = _io_l2io_req_valid_T_1 \| _io_l2io_req_valid_T_3; // @[Misc.scala:26:53] assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_4; // @[ZstdCompressorMemWriter.scala:23:7, :278:65] assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h2 : bytes_to_write_log2; // @[ZstdCompressorMemWriter.scala:237:32, :247:52, :282:31] assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:23:7, :282:31] assign _io_l2io_req_bits_addr_T = write_ptr_override ? _dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[ZstdCompressorMemWriter.scala:39:27, :168:60, :247:52, :283:31] assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:23:7, :283:31] assign _io_l2io_req_bits_data_T = write_ptr_override ? {192'h0, _dest_info_Q_io_deq_bits_cmpval} : remapped_write_data; // @[ZstdCompressorMemWriter.scala:39:27, :89:{76,90}, :233:32, :247:52, :284:31] assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:23:7, :284:31] wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53] wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53] assign _dest_info_Q_io_deq_ready_T_1 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53] reg [63:0] bufs_completed; // @[ZstdCompressorMemWriter.scala:290:31] assign io_bufs_completed = bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7, :290:31] wire _T_5372 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18] wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[ZstdCompressorMemWriter.scala:290:31, :298:38] wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[ZstdCompressorMemWriter.scala:298:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module IDPool_7 : input clock : Clock input reset : Reset output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}} regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff) regreset select : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid : UInt<1>, clock, reset, UInt<1>(0h1) connect io.alloc.valid, valid connect io.alloc.bits, select node taken_shiftAmount = bits(io.alloc.bits, 2, 0) node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount) node _taken_T_1 = bits(_taken_T, 7, 0) node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0)) node allocated_shiftAmount = bits(io.free.bits, 2, 0) node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount) node _allocated_T_1 = bits(_allocated_T, 7, 0) node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0)) node _bitmap1_T = not(taken) node _bitmap1_T_1 = and(bitmap, _bitmap1_T) node bitmap1 = or(_bitmap1_T_1, allocated) node _select1_T = bits(bitmap1, 0, 0) node _select1_T_1 = bits(bitmap1, 1, 1) node _select1_T_2 = bits(bitmap1, 2, 2) node _select1_T_3 = bits(bitmap1, 3, 3) node _select1_T_4 = bits(bitmap1, 4, 4) node _select1_T_5 = bits(bitmap1, 5, 5) node _select1_T_6 = bits(bitmap1, 6, 6) node _select1_T_7 = bits(bitmap1, 7, 7) node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8) node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9) node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10) node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11) node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12) node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13) node _valid1_T = orr(bitmap) node _valid1_T_1 = bits(bitmap, 0, 0) node _valid1_T_2 = bits(bitmap, 1, 1) node _valid1_T_3 = bits(bitmap, 2, 2) node _valid1_T_4 = bits(bitmap, 3, 3) node _valid1_T_5 = bits(bitmap, 4, 4) node _valid1_T_6 = bits(bitmap, 5, 5) node _valid1_T_7 = bits(bitmap, 6, 6) node _valid1_T_8 = bits(bitmap, 7, 7) node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2) node _valid1_T_10 = bits(_valid1_T_9, 1, 0) node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4) node _valid1_T_12 = bits(_valid1_T_11, 1, 0) node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12) node _valid1_T_14 = bits(_valid1_T_13, 2, 0) node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6) node _valid1_T_16 = bits(_valid1_T_15, 1, 0) node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8) node _valid1_T_18 = bits(_valid1_T_17, 1, 0) node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18) node _valid1_T_20 = bits(_valid1_T_19, 2, 0) node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20) node _valid1_T_22 = bits(_valid1_T_21, 3, 0) node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1)) node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready) node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0)) node _valid1_T_26 = and(_valid1_T, _valid1_T_25) node valid1 = or(_valid1_T_26, io.free.valid) node _T = or(io.alloc.ready, io.free.valid) when _T : connect bitmap, bitmap1 connect valid, valid1 node _T_1 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_2 = and(_T_1, io.free.valid) node _T_3 = or(io.alloc.ready, _T_2) when _T_3 : connect select, select1 node _T_4 = eq(io.free.valid, UInt<1>(0h0)) node _T_5 = not(taken) node _T_6 = and(bitmap, _T_5) node _T_7 = dshr(_T_6, io.free.bits) node _T_8 = bits(_T_7, 0, 0) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_4, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid \|\| !(bitmap & ~taken)(io.free.bits))\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = orr(bitmap) node _T_15 = eq(valid, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node _T_19 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_20 = and(_T_19, io.free.valid) node _T_21 = or(io.alloc.ready, _T_20) reg REG : UInt<1>, clock connect REG, _T_21 node _T_22 = and(io.alloc.valid, REG) when _T_22 : node _T_23 = bits(bitmap, 0, 0) node _T_24 = bits(bitmap, 1, 1) node _T_25 = bits(bitmap, 2, 2) node _T_26 = bits(bitmap, 3, 3) node _T_27 = bits(bitmap, 4, 4) node _T_28 = bits(bitmap, 5, 5) node _T_29 = bits(bitmap, 6, 6) node _T_30 = bits(bitmap, 7, 7) node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7)) node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31) node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32) node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33) node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34) node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35) node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36) node _T_38 = eq(select, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2 assert(clock, _T_38, UInt<1>(0h1), "") : assert_2	module IDPool_7( // @[IDPool.scala:8:7] input clock, // @[IDPool.scala:8:7] input reset, // @[IDPool.scala:8:7] input io_free_valid, // @[IDPool.scala:12:14] input [2:0] io_free_bits, // @[IDPool.scala:12:14] input io_alloc_ready, // @[IDPool.scala:12:14] output io_alloc_valid, // @[IDPool.scala:12:14] output [2:0] io_alloc_bits // @[IDPool.scala:12:14] ); wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7] wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7] wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7] wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7] wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49] wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49] wire io_alloc_valid_0; // @[IDPool.scala:8:7] reg [7:0] bitmap; // @[IDPool.scala:18:23] reg [2:0] select; // @[IDPool.scala:19:23] assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23] reg valid; // @[IDPool.scala:20:23] assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23] wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}] wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}] wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27] wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}] wire [7:0] bitmap1 = _bitmap1_T_1 \| allocated; // @[IDPool.scala:26:22, :27:{25,35}] wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45] wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45] wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45] wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45] wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45] wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45] wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45] wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45] wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45] wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45] wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45] wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45] wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45] wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45] wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45] wire _valid1_T = \|bitmap; // @[IDPool.scala:18:23, :29:28] wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46] wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46] wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}] wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}] wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}] wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}] wire valid1 = _valid1_T_26 \| io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17] reg REG; // @[IDPool.scala:51:36]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_6 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 connect _source_ok_WIRE[9], _source_ok_T_44 connect _source_ok_WIRE[10], _source_ok_T_45 node _source_ok_T_46 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[2]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[3]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[4]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[5]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[6]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[7]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[8]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_54, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h3)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<2>(0h2)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<4>(0h8)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_112 = eq(_T_111, UInt<1>(0h0)) node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_114 = cvt(_T_113) node _T_115 = and(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = asSInt(_T_115) node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0))) node _T_118 = or(_T_112, _T_117) node _T_119 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _T_127 = and(_T_11, _T_24) node _T_128 = and(_T_127, _T_37) node _T_129 = and(_T_128, _T_50) node _T_130 = and(_T_129, _T_63) node _T_131 = and(_T_130, _T_76) node _T_132 = and(_T_131, _T_89) node _T_133 = and(_T_132, _T_102) node _T_134 = and(_T_133, _T_110) node _T_135 = and(_T_134, _T_118) node _T_136 = and(_T_135, _T_126) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_136, UInt<1>(0h1), "") : assert_1 node _T_140 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_140 : node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_7) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<1>(0h1)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_8) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h2)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_9) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<2>(0h3)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_10) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_169 = shr(io.in.a.bits.source, 3) node _T_170 = eq(_T_169, UInt<2>(0h3)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_11) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_175 = shr(io.in.a.bits.source, 3) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_12) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_181 = shr(io.in.a.bits.source, 3) node _T_182 = eq(_T_181, UInt<4>(0h8)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_188 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_190 = or(_T_144, _T_150) node _T_191 = or(_T_190, _T_156) node _T_192 = or(_T_191, _T_162) node _T_193 = or(_T_192, _T_168) node _T_194 = or(_T_193, _T_174) node _T_195 = or(_T_194, _T_180) node _T_196 = or(_T_195, _T_186) node _T_197 = or(_T_196, _T_187) node _T_198 = or(_T_197, _T_188) node _T_199 = or(_T_198, _T_189) node _T_200 = and(_T_143, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = or(_T_207, _T_212) node _T_219 = or(_T_218, _T_217) node _T_220 = and(_T_202, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_201, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_222, UInt<1>(0h1), "") : assert_2 node _T_226 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_227 = shr(io.in.a.bits.source, 2) node _T_228 = eq(_T_227, UInt<1>(0h0)) node _T_229 = leq(UInt<1>(0h0), uncommonBits_14) node _T_230 = and(_T_228, _T_229) node _T_231 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<1>(0h1)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_15) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_239 = shr(io.in.a.bits.source, 2) node _T_240 = eq(_T_239, UInt<2>(0h2)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_16) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_245 = shr(io.in.a.bits.source, 2) node _T_246 = eq(_T_245, UInt<2>(0h3)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_17) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_251 = shr(io.in.a.bits.source, 3) node _T_252 = eq(_T_251, UInt<2>(0h3)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_18) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_257 = shr(io.in.a.bits.source, 3) node _T_258 = eq(_T_257, UInt<2>(0h2)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_19) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_263 = shr(io.in.a.bits.source, 3) node _T_264 = eq(_T_263, UInt<4>(0h8)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_20) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_20, UInt<3>(0h4)) node _T_268 = and(_T_266, _T_267) node _T_269 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_270 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_271 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_226 connect _WIRE[1], _T_232 connect _WIRE[2], _T_238 connect _WIRE[3], _T_244 connect _WIRE[4], _T_250 connect _WIRE[5], _T_256 connect _WIRE[6], _T_262 connect _WIRE[7], _T_268 connect _WIRE[8], _T_269 connect _WIRE[9], _T_270 connect _WIRE[10], _T_271 node _T_272 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_273 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_274 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_275 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_276 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_278 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_279 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_280 = mux(_WIRE[7], _T_272, UInt<1>(0h0)) node _T_281 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_282 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_284 = or(_T_273, _T_274) node _T_285 = or(_T_284, _T_275) node _T_286 = or(_T_285, _T_276) node _T_287 = or(_T_286, _T_277) node _T_288 = or(_T_287, _T_278) node _T_289 = or(_T_288, _T_279) node _T_290 = or(_T_289, _T_280) node _T_291 = or(_T_290, _T_281) node _T_292 = or(_T_291, _T_282) node _T_293 = or(_T_292, _T_283) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_293 node _T_294 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_295 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_296 = and(_T_294, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_302, _T_307) node _T_314 = or(_T_313, _T_312) node _T_315 = and(_T_297, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_WIRE_1, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_317, UInt<1>(0h1), "") : assert_3 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(source_ok, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_324 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_324, UInt<1>(0h1), "") : assert_5 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(is_aligned, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_331 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_331, UInt<1>(0h1), "") : assert_7 node _T_335 = not(io.in.a.bits.mask) node _T_336 = eq(_T_335, UInt<1>(0h0)) node _T_337 = asUInt(reset) node _T_338 = eq(_T_337, UInt<1>(0h0)) when _T_338 : node _T_339 = eq(_T_336, UInt<1>(0h0)) when _T_339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_336, UInt<1>(0h1), "") : assert_8 node _T_340 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_T_340, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_340, UInt<1>(0h1), "") : assert_9 node _T_344 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_344 : node _T_345 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_346 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_349 = shr(io.in.a.bits.source, 2) node _T_350 = eq(_T_349, UInt<1>(0h0)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_21) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_355 = shr(io.in.a.bits.source, 2) node _T_356 = eq(_T_355, UInt<1>(0h1)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_22) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_361 = shr(io.in.a.bits.source, 2) node _T_362 = eq(_T_361, UInt<2>(0h2)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_23) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_366 = and(_T_364, _T_365) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_367 = shr(io.in.a.bits.source, 2) node _T_368 = eq(_T_367, UInt<2>(0h3)) node _T_369 = leq(UInt<1>(0h0), uncommonBits_24) node _T_370 = and(_T_368, _T_369) node _T_371 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_372 = and(_T_370, _T_371) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_373 = shr(io.in.a.bits.source, 3) node _T_374 = eq(_T_373, UInt<2>(0h3)) node _T_375 = leq(UInt<1>(0h0), uncommonBits_25) node _T_376 = and(_T_374, _T_375) node _T_377 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_378 = and(_T_376, _T_377) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_379 = shr(io.in.a.bits.source, 3) node _T_380 = eq(_T_379, UInt<2>(0h2)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_26) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_385 = shr(io.in.a.bits.source, 3) node _T_386 = eq(_T_385, UInt<4>(0h8)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_27) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_27, UInt<3>(0h4)) node _T_390 = and(_T_388, _T_389) node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_392 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_393 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_394 = or(_T_348, _T_354) node _T_395 = or(_T_394, _T_360) node _T_396 = or(_T_395, _T_366) node _T_397 = or(_T_396, _T_372) node _T_398 = or(_T_397, _T_378) node _T_399 = or(_T_398, _T_384) node _T_400 = or(_T_399, _T_390) node _T_401 = or(_T_400, _T_391) node _T_402 = or(_T_401, _T_392) node _T_403 = or(_T_402, _T_393) node _T_404 = and(_T_347, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_407 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = or(_T_411, _T_416) node _T_423 = or(_T_422, _T_421) node _T_424 = and(_T_406, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_405, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_426, UInt<1>(0h1), "") : assert_10 node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_431 = shr(io.in.a.bits.source, 2) node _T_432 = eq(_T_431, UInt<1>(0h0)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_28) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_436 = and(_T_434, _T_435) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_437 = shr(io.in.a.bits.source, 2) node _T_438 = eq(_T_437, UInt<1>(0h1)) node _T_439 = leq(UInt<1>(0h0), uncommonBits_29) node _T_440 = and(_T_438, _T_439) node _T_441 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_442 = and(_T_440, _T_441) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_443 = shr(io.in.a.bits.source, 2) node _T_444 = eq(_T_443, UInt<2>(0h2)) node _T_445 = leq(UInt<1>(0h0), uncommonBits_30) node _T_446 = and(_T_444, _T_445) node _T_447 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_448 = and(_T_446, _T_447) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_449 = shr(io.in.a.bits.source, 2) node _T_450 = eq(_T_449, UInt<2>(0h3)) node _T_451 = leq(UInt<1>(0h0), uncommonBits_31) node _T_452 = and(_T_450, _T_451) node _T_453 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_454 = and(_T_452, _T_453) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_455 = shr(io.in.a.bits.source, 3) node _T_456 = eq(_T_455, UInt<2>(0h3)) node _T_457 = leq(UInt<1>(0h0), uncommonBits_32) node _T_458 = and(_T_456, _T_457) node _T_459 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_460 = and(_T_458, _T_459) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_461 = shr(io.in.a.bits.source, 3) node _T_462 = eq(_T_461, UInt<2>(0h2)) node _T_463 = leq(UInt<1>(0h0), uncommonBits_33) node _T_464 = and(_T_462, _T_463) node _T_465 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_466 = and(_T_464, _T_465) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_467 = shr(io.in.a.bits.source, 3) node _T_468 = eq(_T_467, UInt<4>(0h8)) node _T_469 = leq(UInt<1>(0h0), uncommonBits_34) node _T_470 = and(_T_468, _T_469) node _T_471 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_474 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_475 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_430 connect _WIRE_2[1], _T_436 connect _WIRE_2[2], _T_442 connect _WIRE_2[3], _T_448 connect _WIRE_2[4], _T_454 connect _WIRE_2[5], _T_460 connect _WIRE_2[6], _T_466 connect _WIRE_2[7], _T_472 connect _WIRE_2[8], _T_473 connect _WIRE_2[9], _T_474 connect _WIRE_2[10], _T_475 node _T_476 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_477 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_478 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_481 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_482 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_483 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_484 = mux(_WIRE_2[7], _T_476, UInt<1>(0h0)) node _T_485 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_486 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_487 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_488 = or(_T_477, _T_478) node _T_489 = or(_T_488, _T_479) node _T_490 = or(_T_489, _T_480) node _T_491 = or(_T_490, _T_481) node _T_492 = or(_T_491, _T_482) node _T_493 = or(_T_492, _T_483) node _T_494 = or(_T_493, _T_484) node _T_495 = or(_T_494, _T_485) node _T_496 = or(_T_495, _T_486) node _T_497 = or(_T_496, _T_487) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_497 node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<13>(0h1000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<13>(0h1000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_506, _T_511) node _T_518 = or(_T_517, _T_516) node _T_519 = and(_T_501, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_WIRE_3, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_521, UInt<1>(0h1), "") : assert_11 node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(source_ok, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_528, UInt<1>(0h1), "") : assert_13 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(is_aligned, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_535, UInt<1>(0h1), "") : assert_15 node _T_539 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_540 = asUInt(reset) node _T_541 = eq(_T_540, UInt<1>(0h0)) when _T_541 : node _T_542 = eq(_T_539, UInt<1>(0h0)) when _T_542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_539, UInt<1>(0h1), "") : assert_16 node _T_543 = not(io.in.a.bits.mask) node _T_544 = eq(_T_543, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_544, UInt<1>(0h1), "") : assert_17 node _T_548 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_548, UInt<1>(0h1), "") : assert_18 node _T_552 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_552 : node _T_553 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_554 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_35) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_563 = shr(io.in.a.bits.source, 2) node _T_564 = eq(_T_563, UInt<1>(0h1)) node _T_565 = leq(UInt<1>(0h0), uncommonBits_36) node _T_566 = and(_T_564, _T_565) node _T_567 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_568 = and(_T_566, _T_567) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<2>(0h2)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_37) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<2>(0h3)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_38) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_581 = shr(io.in.a.bits.source, 3) node _T_582 = eq(_T_581, UInt<2>(0h3)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_39) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_587 = shr(io.in.a.bits.source, 3) node _T_588 = eq(_T_587, UInt<2>(0h2)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_40) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_593 = shr(io.in.a.bits.source, 3) node _T_594 = eq(_T_593, UInt<4>(0h8)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_41) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_601 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_602 = or(_T_556, _T_562) node _T_603 = or(_T_602, _T_568) node _T_604 = or(_T_603, _T_574) node _T_605 = or(_T_604, _T_580) node _T_606 = or(_T_605, _T_586) node _T_607 = or(_T_606, _T_592) node _T_608 = or(_T_607, _T_598) node _T_609 = or(_T_608, _T_599) node _T_610 = or(_T_609, _T_600) node _T_611 = or(_T_610, _T_601) node _T_612 = and(_T_555, _T_611) node _T_613 = or(UInt<1>(0h0), _T_612) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_613, UInt<1>(0h1), "") : assert_19 node _T_617 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_618 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_619 = and(_T_617, _T_618) node _T_620 = or(UInt<1>(0h0), _T_619) node _T_621 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_622 = cvt(_T_621) node _T_623 = and(_T_622, asSInt(UInt<13>(0h1000))) node _T_624 = asSInt(_T_623) node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0))) node _T_626 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_627 = cvt(_T_626) node _T_628 = and(_T_627, asSInt(UInt<13>(0h1000))) node _T_629 = asSInt(_T_628) node _T_630 = eq(_T_629, asSInt(UInt<1>(0h0))) node _T_631 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_632 = cvt(_T_631) node _T_633 = and(_T_632, asSInt(UInt<13>(0h1000))) node _T_634 = asSInt(_T_633) node _T_635 = eq(_T_634, asSInt(UInt<1>(0h0))) node _T_636 = or(_T_625, _T_630) node _T_637 = or(_T_636, _T_635) node _T_638 = and(_T_620, _T_637) node _T_639 = or(UInt<1>(0h0), _T_638) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_639, UInt<1>(0h1), "") : assert_20 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(source_ok, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(is_aligned, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(_T_649, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_649, UInt<1>(0h1), "") : assert_23 node _T_653 = eq(io.in.a.bits.mask, mask) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_653, UInt<1>(0h1), "") : assert_24 node _T_657 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(_T_657, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_657, UInt<1>(0h1), "") : assert_25 node _T_661 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_661 : node _T_662 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_663 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h0)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_42) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<1>(0h1)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_43) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h2)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_44) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_684 = shr(io.in.a.bits.source, 2) node _T_685 = eq(_T_684, UInt<2>(0h3)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_45) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_689 = and(_T_687, _T_688) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_690 = shr(io.in.a.bits.source, 3) node _T_691 = eq(_T_690, UInt<2>(0h3)) node _T_692 = leq(UInt<1>(0h0), uncommonBits_46) node _T_693 = and(_T_691, _T_692) node _T_694 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_695 = and(_T_693, _T_694) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_696 = shr(io.in.a.bits.source, 3) node _T_697 = eq(_T_696, UInt<2>(0h2)) node _T_698 = leq(UInt<1>(0h0), uncommonBits_47) node _T_699 = and(_T_697, _T_698) node _T_700 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_701 = and(_T_699, _T_700) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_702 = shr(io.in.a.bits.source, 3) node _T_703 = eq(_T_702, UInt<4>(0h8)) node _T_704 = leq(UInt<1>(0h0), uncommonBits_48) node _T_705 = and(_T_703, _T_704) node _T_706 = leq(uncommonBits_48, UInt<3>(0h4)) node _T_707 = and(_T_705, _T_706) node _T_708 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_709 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_710 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_711 = or(_T_665, _T_671) node _T_712 = or(_T_711, _T_677) node _T_713 = or(_T_712, _T_683) node _T_714 = or(_T_713, _T_689) node _T_715 = or(_T_714, _T_695) node _T_716 = or(_T_715, _T_701) node _T_717 = or(_T_716, _T_707) node _T_718 = or(_T_717, _T_708) node _T_719 = or(_T_718, _T_709) node _T_720 = or(_T_719, _T_710) node _T_721 = and(_T_664, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_725 = and(_T_723, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_728 = cvt(_T_727) node _T_729 = and(_T_728, asSInt(UInt<13>(0h1000))) node _T_730 = asSInt(_T_729) node _T_731 = eq(_T_730, asSInt(UInt<1>(0h0))) node _T_732 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_733 = cvt(_T_732) node _T_734 = and(_T_733, asSInt(UInt<13>(0h1000))) node _T_735 = asSInt(_T_734) node _T_736 = eq(_T_735, asSInt(UInt<1>(0h0))) node _T_737 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_738 = cvt(_T_737) node _T_739 = and(_T_738, asSInt(UInt<13>(0h1000))) node _T_740 = asSInt(_T_739) node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0))) node _T_742 = or(_T_731, _T_736) node _T_743 = or(_T_742, _T_741) node _T_744 = and(_T_726, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = and(_T_722, _T_745) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_746, UInt<1>(0h1), "") : assert_26 node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(source_ok, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(is_aligned, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_756 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(_T_756, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_756, UInt<1>(0h1), "") : assert_29 node _T_760 = eq(io.in.a.bits.mask, mask) node _T_761 = asUInt(reset) node _T_762 = eq(_T_761, UInt<1>(0h0)) when _T_762 : node _T_763 = eq(_T_760, UInt<1>(0h0)) when _T_763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_760, UInt<1>(0h1), "") : assert_30 node _T_764 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_764 : node _T_765 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_766 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_769 = shr(io.in.a.bits.source, 2) node _T_770 = eq(_T_769, UInt<1>(0h0)) node _T_771 = leq(UInt<1>(0h0), uncommonBits_49) node _T_772 = and(_T_770, _T_771) node _T_773 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_774 = and(_T_772, _T_773) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_775 = shr(io.in.a.bits.source, 2) node _T_776 = eq(_T_775, UInt<1>(0h1)) node _T_777 = leq(UInt<1>(0h0), uncommonBits_50) node _T_778 = and(_T_776, _T_777) node _T_779 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_780 = and(_T_778, _T_779) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_781 = shr(io.in.a.bits.source, 2) node _T_782 = eq(_T_781, UInt<2>(0h2)) node _T_783 = leq(UInt<1>(0h0), uncommonBits_51) node _T_784 = and(_T_782, _T_783) node _T_785 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_786 = and(_T_784, _T_785) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_787 = shr(io.in.a.bits.source, 2) node _T_788 = eq(_T_787, UInt<2>(0h3)) node _T_789 = leq(UInt<1>(0h0), uncommonBits_52) node _T_790 = and(_T_788, _T_789) node _T_791 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_792 = and(_T_790, _T_791) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_793 = shr(io.in.a.bits.source, 3) node _T_794 = eq(_T_793, UInt<2>(0h3)) node _T_795 = leq(UInt<1>(0h0), uncommonBits_53) node _T_796 = and(_T_794, _T_795) node _T_797 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_798 = and(_T_796, _T_797) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_799 = shr(io.in.a.bits.source, 3) node _T_800 = eq(_T_799, UInt<2>(0h2)) node _T_801 = leq(UInt<1>(0h0), uncommonBits_54) node _T_802 = and(_T_800, _T_801) node _T_803 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_804 = and(_T_802, _T_803) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_805 = shr(io.in.a.bits.source, 3) node _T_806 = eq(_T_805, UInt<4>(0h8)) node _T_807 = leq(UInt<1>(0h0), uncommonBits_55) node _T_808 = and(_T_806, _T_807) node _T_809 = leq(uncommonBits_55, UInt<3>(0h4)) node _T_810 = and(_T_808, _T_809) node _T_811 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_812 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_813 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_814 = or(_T_768, _T_774) node _T_815 = or(_T_814, _T_780) node _T_816 = or(_T_815, _T_786) node _T_817 = or(_T_816, _T_792) node _T_818 = or(_T_817, _T_798) node _T_819 = or(_T_818, _T_804) node _T_820 = or(_T_819, _T_810) node _T_821 = or(_T_820, _T_811) node _T_822 = or(_T_821, _T_812) node _T_823 = or(_T_822, _T_813) node _T_824 = and(_T_767, _T_823) node _T_825 = or(UInt<1>(0h0), _T_824) node _T_826 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_827 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_828 = and(_T_826, _T_827) node _T_829 = or(UInt<1>(0h0), _T_828) node _T_830 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<13>(0h1000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = or(_T_834, _T_839) node _T_846 = or(_T_845, _T_844) node _T_847 = and(_T_829, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = and(_T_825, _T_848) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_849, UInt<1>(0h1), "") : assert_31 node _T_853 = asUInt(reset) node _T_854 = eq(_T_853, UInt<1>(0h0)) when _T_854 : node _T_855 = eq(source_ok, UInt<1>(0h0)) when _T_855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(is_aligned, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_859 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_859, UInt<1>(0h1), "") : assert_34 node _T_863 = not(mask) node _T_864 = and(io.in.a.bits.mask, _T_863) node _T_865 = eq(_T_864, UInt<1>(0h0)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_865, UInt<1>(0h1), "") : assert_35 node _T_869 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_869 : node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_872 = and(_T_870, _T_871) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<1>(0h0)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_56) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h1)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_57) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_886 = shr(io.in.a.bits.source, 2) node _T_887 = eq(_T_886, UInt<2>(0h2)) node _T_888 = leq(UInt<1>(0h0), uncommonBits_58) node _T_889 = and(_T_887, _T_888) node _T_890 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_891 = and(_T_889, _T_890) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_892 = shr(io.in.a.bits.source, 2) node _T_893 = eq(_T_892, UInt<2>(0h3)) node _T_894 = leq(UInt<1>(0h0), uncommonBits_59) node _T_895 = and(_T_893, _T_894) node _T_896 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_897 = and(_T_895, _T_896) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_898 = shr(io.in.a.bits.source, 3) node _T_899 = eq(_T_898, UInt<2>(0h3)) node _T_900 = leq(UInt<1>(0h0), uncommonBits_60) node _T_901 = and(_T_899, _T_900) node _T_902 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_903 = and(_T_901, _T_902) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_904 = shr(io.in.a.bits.source, 3) node _T_905 = eq(_T_904, UInt<2>(0h2)) node _T_906 = leq(UInt<1>(0h0), uncommonBits_61) node _T_907 = and(_T_905, _T_906) node _T_908 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_909 = and(_T_907, _T_908) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_910 = shr(io.in.a.bits.source, 3) node _T_911 = eq(_T_910, UInt<4>(0h8)) node _T_912 = leq(UInt<1>(0h0), uncommonBits_62) node _T_913 = and(_T_911, _T_912) node _T_914 = leq(uncommonBits_62, UInt<3>(0h4)) node _T_915 = and(_T_913, _T_914) node _T_916 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_917 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_918 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_919 = or(_T_873, _T_879) node _T_920 = or(_T_919, _T_885) node _T_921 = or(_T_920, _T_891) node _T_922 = or(_T_921, _T_897) node _T_923 = or(_T_922, _T_903) node _T_924 = or(_T_923, _T_909) node _T_925 = or(_T_924, _T_915) node _T_926 = or(_T_925, _T_916) node _T_927 = or(_T_926, _T_917) node _T_928 = or(_T_927, _T_918) node _T_929 = and(_T_872, _T_928) node _T_930 = or(UInt<1>(0h0), _T_929) node _T_931 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_932 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_933 = and(_T_931, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_936 = cvt(_T_935) node _T_937 = and(_T_936, asSInt(UInt<13>(0h1000))) node _T_938 = asSInt(_T_937) node _T_939 = eq(_T_938, asSInt(UInt<1>(0h0))) node _T_940 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<13>(0h1000))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<13>(0h1000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_939, _T_944) node _T_951 = or(_T_950, _T_949) node _T_952 = and(_T_934, _T_951) node _T_953 = or(UInt<1>(0h0), _T_952) node _T_954 = and(_T_930, _T_953) node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(_T_954, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_954, UInt<1>(0h1), "") : assert_36 node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(source_ok, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(is_aligned, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_964 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_964, UInt<1>(0h1), "") : assert_39 node _T_968 = eq(io.in.a.bits.mask, mask) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_968, UInt<1>(0h1), "") : assert_40 node _T_972 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_972 : node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_974 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_975 = and(_T_973, _T_974) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_977 = shr(io.in.a.bits.source, 2) node _T_978 = eq(_T_977, UInt<1>(0h0)) node _T_979 = leq(UInt<1>(0h0), uncommonBits_63) node _T_980 = and(_T_978, _T_979) node _T_981 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_982 = and(_T_980, _T_981) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_983 = shr(io.in.a.bits.source, 2) node _T_984 = eq(_T_983, UInt<1>(0h1)) node _T_985 = leq(UInt<1>(0h0), uncommonBits_64) node _T_986 = and(_T_984, _T_985) node _T_987 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_988 = and(_T_986, _T_987) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_989 = shr(io.in.a.bits.source, 2) node _T_990 = eq(_T_989, UInt<2>(0h2)) node _T_991 = leq(UInt<1>(0h0), uncommonBits_65) node _T_992 = and(_T_990, _T_991) node _T_993 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_994 = and(_T_992, _T_993) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_995 = shr(io.in.a.bits.source, 2) node _T_996 = eq(_T_995, UInt<2>(0h3)) node _T_997 = leq(UInt<1>(0h0), uncommonBits_66) node _T_998 = and(_T_996, _T_997) node _T_999 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1000 = and(_T_998, _T_999) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_1001 = shr(io.in.a.bits.source, 3) node _T_1002 = eq(_T_1001, UInt<2>(0h3)) node _T_1003 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1004 = and(_T_1002, _T_1003) node _T_1005 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_1006 = and(_T_1004, _T_1005) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_1007 = shr(io.in.a.bits.source, 3) node _T_1008 = eq(_T_1007, UInt<2>(0h2)) node _T_1009 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1010 = and(_T_1008, _T_1009) node _T_1011 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_1012 = and(_T_1010, _T_1011) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1013 = shr(io.in.a.bits.source, 3) node _T_1014 = eq(_T_1013, UInt<4>(0h8)) node _T_1015 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1016 = and(_T_1014, _T_1015) node _T_1017 = leq(uncommonBits_69, UInt<3>(0h4)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1020 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1021 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1022 = or(_T_976, _T_982) node _T_1023 = or(_T_1022, _T_988) node _T_1024 = or(_T_1023, _T_994) node _T_1025 = or(_T_1024, _T_1000) node _T_1026 = or(_T_1025, _T_1006) node _T_1027 = or(_T_1026, _T_1012) node _T_1028 = or(_T_1027, _T_1018) node _T_1029 = or(_T_1028, _T_1019) node _T_1030 = or(_T_1029, _T_1020) node _T_1031 = or(_T_1030, _T_1021) node _T_1032 = and(_T_975, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1035 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = or(UInt<1>(0h0), _T_1036) node _T_1038 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<13>(0h1000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1044 = cvt(_T_1043) node _T_1045 = and(_T_1044, asSInt(UInt<13>(0h1000))) node _T_1046 = asSInt(_T_1045) node _T_1047 = eq(_T_1046, asSInt(UInt<1>(0h0))) node _T_1048 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1049 = cvt(_T_1048) node _T_1050 = and(_T_1049, asSInt(UInt<13>(0h1000))) node _T_1051 = asSInt(_T_1050) node _T_1052 = eq(_T_1051, asSInt(UInt<1>(0h0))) node _T_1053 = or(_T_1042, _T_1047) node _T_1054 = or(_T_1053, _T_1052) node _T_1055 = and(_T_1037, _T_1054) node _T_1056 = or(UInt<1>(0h0), _T_1055) node _T_1057 = and(_T_1033, _T_1056) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_41 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(source_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(is_aligned, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_44 node _T_1071 = eq(io.in.a.bits.mask, mask) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_45 node _T_1075 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1075 : node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1080 = shr(io.in.a.bits.source, 2) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) node _T_1082 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1085 = and(_T_1083, _T_1084) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1086 = shr(io.in.a.bits.source, 2) node _T_1087 = eq(_T_1086, UInt<1>(0h1)) node _T_1088 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1091 = and(_T_1089, _T_1090) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1092 = shr(io.in.a.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1098 = shr(io.in.a.bits.source, 2) node _T_1099 = eq(_T_1098, UInt<2>(0h3)) node _T_1100 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1103 = and(_T_1101, _T_1102) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1104 = shr(io.in.a.bits.source, 3) node _T_1105 = eq(_T_1104, UInt<2>(0h3)) node _T_1106 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1109 = and(_T_1107, _T_1108) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_1110 = shr(io.in.a.bits.source, 3) node _T_1111 = eq(_T_1110, UInt<2>(0h2)) node _T_1112 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1113 = and(_T_1111, _T_1112) node _T_1114 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1115 = and(_T_1113, _T_1114) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1116 = shr(io.in.a.bits.source, 3) node _T_1117 = eq(_T_1116, UInt<4>(0h8)) node _T_1118 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1119 = and(_T_1117, _T_1118) node _T_1120 = leq(uncommonBits_76, UInt<3>(0h4)) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1123 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1124 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1125 = or(_T_1079, _T_1085) node _T_1126 = or(_T_1125, _T_1091) node _T_1127 = or(_T_1126, _T_1097) node _T_1128 = or(_T_1127, _T_1103) node _T_1129 = or(_T_1128, _T_1109) node _T_1130 = or(_T_1129, _T_1115) node _T_1131 = or(_T_1130, _T_1121) node _T_1132 = or(_T_1131, _T_1122) node _T_1133 = or(_T_1132, _T_1123) node _T_1134 = or(_T_1133, _T_1124) node _T_1135 = and(_T_1078, _T_1134) node _T_1136 = or(UInt<1>(0h0), _T_1135) node _T_1137 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1138 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1139 = cvt(_T_1138) node _T_1140 = and(_T_1139, asSInt(UInt<13>(0h1000))) node _T_1141 = asSInt(_T_1140) node _T_1142 = eq(_T_1141, asSInt(UInt<1>(0h0))) node _T_1143 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1144 = cvt(_T_1143) node _T_1145 = and(_T_1144, asSInt(UInt<13>(0h1000))) node _T_1146 = asSInt(_T_1145) node _T_1147 = eq(_T_1146, asSInt(UInt<1>(0h0))) node _T_1148 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<13>(0h1000))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = or(_T_1142, _T_1147) node _T_1154 = or(_T_1153, _T_1152) node _T_1155 = and(_T_1137, _T_1154) node _T_1156 = or(UInt<1>(0h0), _T_1155) node _T_1157 = and(_T_1136, _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_46 node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(source_ok, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(is_aligned, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1167 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_49 node _T_1171 = eq(io.in.a.bits.mask, mask) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_50 node _T_1175 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1179 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_52 node _source_ok_T_55 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<1>(0h0)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<1>(0h1)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 2) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<2>(0h2)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_74 = shr(io.in.d.bits.source, 2) node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h3)) node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_T_78 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_80 = shr(io.in.d.bits.source, 3) node _source_ok_T_81 = eq(_source_ok_T_80, UInt<2>(0h3)) node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_T_84 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_86 = shr(io.in.d.bits.source, 3) node _source_ok_T_87 = eq(_source_ok_T_86, UInt<2>(0h2)) node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_T_90 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_92 = shr(io.in.d.bits.source, 3) node _source_ok_T_93 = eq(_source_ok_T_92, UInt<4>(0h8)) node _source_ok_T_94 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_T_96 = leq(source_ok_uncommonBits_13, UInt<3>(0h4)) node _source_ok_T_97 = and(_source_ok_T_95, _source_ok_T_96) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_55 connect _source_ok_WIRE_1[1], _source_ok_T_61 connect _source_ok_WIRE_1[2], _source_ok_T_67 connect _source_ok_WIRE_1[3], _source_ok_T_73 connect _source_ok_WIRE_1[4], _source_ok_T_79 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_91 connect _source_ok_WIRE_1[7], _source_ok_T_97 connect _source_ok_WIRE_1[8], _source_ok_T_98 connect _source_ok_WIRE_1[9], _source_ok_T_99 connect _source_ok_WIRE_1[10], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1183 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1183 : node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(source_ok_1, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1187 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_54 node _T_1191 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_55 node _T_1195 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_56 node _T_1199 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_57 node _T_1203 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1203 : node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(source_ok_1, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(sink_ok, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1210 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_60 node _T_1214 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_61 node _T_1218 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_62 node _T_1222 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(_T_1222, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1222, UInt<1>(0h1), "") : assert_63 node _T_1226 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1227 = or(UInt<1>(0h0), _T_1226) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_64 node _T_1231 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1231 : node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(source_ok_1, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(sink_ok, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1238 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_67 node _T_1242 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_68 node _T_1246 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_69 node _T_1250 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1251 = or(_T_1250, io.in.d.bits.corrupt) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_70 node _T_1255 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1256 = or(UInt<1>(0h0), _T_1255) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_71 node _T_1260 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1260 : node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(source_ok_1, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1264 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_73 node _T_1268 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_74 node _T_1272 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1273 = or(UInt<1>(0h0), _T_1272) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_75 node _T_1277 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1277 : node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(source_ok_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1281 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_77 node _T_1285 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1286 = or(_T_1285, io.in.d.bits.corrupt) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_78 node _T_1290 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1291 = or(UInt<1>(0h0), _T_1290) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_79 node _T_1295 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1295 : node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(source_ok_1, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1299 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_81 node _T_1303 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_82 node _T_1307 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1308 = or(UInt<1>(0h0), _T_1307) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1312 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1316 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1320 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1324 = eq(a_first, UInt<1>(0h0)) node _T_1325 = and(io.in.a.valid, _T_1324) when _T_1325 : node _T_1326 = eq(io.in.a.bits.opcode, opcode) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_87 node _T_1330 = eq(io.in.a.bits.param, param) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_88 node _T_1334 = eq(io.in.a.bits.size, size) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_89 node _T_1338 = eq(io.in.a.bits.source, source) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_90 node _T_1342 = eq(io.in.a.bits.address, address) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_91 node _T_1346 = and(io.in.a.ready, io.in.a.valid) node _T_1347 = and(_T_1346, a_first) when _T_1347 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1348 = eq(d_first, UInt<1>(0h0)) node _T_1349 = and(io.in.d.valid, _T_1348) when _T_1349 : node _T_1350 = eq(io.in.d.bits.opcode, opcode_1) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_92 node _T_1354 = eq(io.in.d.bits.param, param_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_93 node _T_1358 = eq(io.in.d.bits.size, size_1) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_94 node _T_1362 = eq(io.in.d.bits.source, source_1) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_95 node _T_1366 = eq(io.in.d.bits.sink, sink) node _T_1367 = asUInt(reset) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) when _T_1368 : node _T_1369 = eq(_T_1366, UInt<1>(0h0)) when _T_1369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1366, UInt<1>(0h1), "") : assert_96 node _T_1370 = eq(io.in.d.bits.denied, denied) node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(_T_1370, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1370, UInt<1>(0h1), "") : assert_97 node _T_1374 = and(io.in.d.ready, io.in.d.valid) node _T_1375 = and(_T_1374, d_first) when _T_1375 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1376 = and(io.in.a.valid, a_first_1) node _T_1377 = and(_T_1376, UInt<1>(0h1)) when _T_1377 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1378 = and(io.in.a.ready, io.in.a.valid) node _T_1379 = and(_T_1378, a_first_1) node _T_1380 = and(_T_1379, UInt<1>(0h1)) when _T_1380 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1381 = dshr(inflight, io.in.a.bits.source) node _T_1382 = bits(_T_1381, 0, 0) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1387 = and(io.in.d.valid, d_first_1) node _T_1388 = and(_T_1387, UInt<1>(0h1)) node _T_1389 = eq(d_release_ack, UInt<1>(0h0)) node _T_1390 = and(_T_1388, _T_1389) when _T_1390 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1391 = and(io.in.d.ready, io.in.d.valid) node _T_1392 = and(_T_1391, d_first_1) node _T_1393 = and(_T_1392, UInt<1>(0h1)) node _T_1394 = eq(d_release_ack, UInt<1>(0h0)) node _T_1395 = and(_T_1393, _T_1394) when _T_1395 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1396 = and(io.in.d.valid, d_first_1) node _T_1397 = and(_T_1396, UInt<1>(0h1)) node _T_1398 = eq(d_release_ack, UInt<1>(0h0)) node _T_1399 = and(_T_1397, _T_1398) when _T_1399 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1400 = dshr(inflight, io.in.d.bits.source) node _T_1401 = bits(_T_1400, 0, 0) node _T_1402 = or(_T_1401, same_cycle_resp) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1406 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1407 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1408 = or(_T_1406, _T_1407) node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(_T_1408, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1408, UInt<1>(0h1), "") : assert_100 node _T_1412 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_101 else : node _T_1416 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1417 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1418 = or(_T_1416, _T_1417) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_102 node _T_1422 = eq(io.in.d.bits.size, a_size_lookup) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_103 node _T_1426 = and(io.in.d.valid, d_first_1) node _T_1427 = and(_T_1426, a_first_1) node _T_1428 = and(_T_1427, io.in.a.valid) node _T_1429 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1430 = and(_T_1428, _T_1429) node _T_1431 = eq(d_release_ack, UInt<1>(0h0)) node _T_1432 = and(_T_1430, _T_1431) when _T_1432 : node _T_1433 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1434 = or(_T_1433, io.in.a.ready) node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(_T_1434, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1434, UInt<1>(0h1), "") : assert_104 node _T_1438 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1439 = orr(a_set_wo_ready) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) node _T_1441 = or(_T_1438, _T_1440) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_12 node _T_1445 = orr(inflight) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) node _T_1447 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1448 = or(_T_1446, _T_1447) node _T_1449 = lt(watchdog, plusarg_reader.out) node _T_1450 = or(_T_1448, _T_1449) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1454 = and(io.in.a.ready, io.in.a.valid) node _T_1455 = and(io.in.d.ready, io.in.d.valid) node _T_1456 = or(_T_1454, _T_1455) when _T_1456 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1457 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1458 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1459 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1460 = and(_T_1458, _T_1459) node _T_1461 = and(_T_1457, _T_1460) when _T_1461 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1462 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1463 = and(_T_1462, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1464 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1465 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1466 = and(_T_1464, _T_1465) node _T_1467 = and(_T_1463, _T_1466) when _T_1467 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1468 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1469 = bits(_T_1468, 0, 0) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1474 = and(io.in.d.valid, d_first_2) node _T_1475 = and(_T_1474, UInt<1>(0h1)) node _T_1476 = and(_T_1475, d_release_ack_1) when _T_1476 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1477 = and(io.in.d.ready, io.in.d.valid) node _T_1478 = and(_T_1477, d_first_2) node _T_1479 = and(_T_1478, UInt<1>(0h1)) node _T_1480 = and(_T_1479, d_release_ack_1) when _T_1480 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1481 = and(io.in.d.valid, d_first_2) node _T_1482 = and(_T_1481, UInt<1>(0h1)) node _T_1483 = and(_T_1482, d_release_ack_1) when _T_1483 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1484 = dshr(inflight_1, io.in.d.bits.source) node _T_1485 = bits(_T_1484, 0, 0) node _T_1486 = or(_T_1485, same_cycle_resp_1) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1490 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(_T_1490, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1490, UInt<1>(0h1), "") : assert_109 else : node _T_1494 = eq(io.in.d.bits.size, c_size_lookup) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_110 node _T_1498 = and(io.in.d.valid, d_first_2) node _T_1499 = and(_T_1498, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1500 = and(_T_1499, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1501 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1502 = and(_T_1500, _T_1501) node _T_1503 = and(_T_1502, d_release_ack_1) node _T_1504 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1505 = and(_T_1503, _T_1504) when _T_1505 : node _T_1506 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1507 = or(_T_1506, _WIRE_27.ready) node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(_T_1507, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1507, UInt<1>(0h1), "") : assert_111 node _T_1511 = orr(c_set_wo_ready) when _T_1511 : node _T_1512 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_13 node _T_1516 = orr(inflight_1) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) node _T_1518 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1519 = or(_T_1517, _T_1518) node _T_1520 = lt(watchdog_1, plusarg_reader_1.out) node _T_1521 = or(_T_1519, _T_1520) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1525 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1526 = and(io.in.d.ready, io.in.d.valid) node _T_1527 = or(_T_1525, _T_1526) when _T_1527 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_54 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_109 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1454 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1454; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1454; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1527 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1527; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1527; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1527; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1380 = _T_1454 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1380 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1380 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1380 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1380 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1380 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1426 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1426 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1395 = _T_1527 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1395 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1395 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1395 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1498 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1498 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1480 = _T_1527 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1480 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1480 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1480 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_139 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_154 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_139( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_154 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module LatencyInjectionQueue_1 : input clock : Clock input reset : Reset output io : { flip latency_cycles : UInt<64>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst queue of Queue8_TLBundleD_a32d256s2k3z4u connect queue.clock, clock connect queue.reset, reset inst release_ready_cycle_q of Queue8_UInt64_1 connect release_ready_cycle_q.clock, clock connect release_ready_cycle_q.reset, reset node _release_ready_cycle_q_io_enq_bits_T = add(cur_cycle, io.latency_cycles) node _release_ready_cycle_q_io_enq_bits_T_1 = tail(_release_ready_cycle_q_io_enq_bits_T, 1) connect release_ready_cycle_q.io.enq.bits, _release_ready_cycle_q_io_enq_bits_T_1 connect queue.io.enq.bits.corrupt, io.enq.bits.corrupt connect queue.io.enq.bits.data, io.enq.bits.data connect queue.io.enq.bits.denied, io.enq.bits.denied connect queue.io.enq.bits.sink, io.enq.bits.sink connect queue.io.enq.bits.source, io.enq.bits.source connect queue.io.enq.bits.size, io.enq.bits.size connect queue.io.enq.bits.param, io.enq.bits.param connect queue.io.enq.bits.opcode, io.enq.bits.opcode connect io.deq.bits, queue.io.deq.bits node _queue_io_enq_valid_T = and(release_ready_cycle_q.io.enq.ready, io.enq.valid) connect queue.io.enq.valid, _queue_io_enq_valid_T node _release_ready_cycle_q_io_enq_valid_T = and(queue.io.enq.ready, io.enq.valid) connect release_ready_cycle_q.io.enq.valid, _release_ready_cycle_q_io_enq_valid_T node _io_enq_ready_T = and(queue.io.enq.ready, release_ready_cycle_q.io.enq.ready) connect io.enq.ready, _io_enq_ready_T node _T = leq(release_ready_cycle_q.io.deq.bits, cur_cycle) node _queue_io_deq_ready_T = and(release_ready_cycle_q.io.deq.valid, _T) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, io.deq.ready) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _release_ready_cycle_q_io_deq_ready_T = and(queue.io.deq.valid, _T) node _release_ready_cycle_q_io_deq_ready_T_1 = and(_release_ready_cycle_q_io_deq_ready_T, io.deq.ready) connect release_ready_cycle_q.io.deq.ready, _release_ready_cycle_q_io_deq_ready_T_1 node _io_deq_valid_T = and(queue.io.deq.valid, release_ready_cycle_q.io.deq.valid) node _io_deq_valid_T_1 = and(_io_deq_valid_T, _T) connect io.deq.valid, _io_deq_valid_T_1	module LatencyInjectionQueue_1( // @[LatencyInjectionQueue.scala:9:7] input clock, // @[LatencyInjectionQueue.scala:9:7] input reset, // @[LatencyInjectionQueue.scala:9:7] input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14] output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14] input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14] input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14] input [1:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14] input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14] input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14] output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14] output [1:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14] output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14] ); wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37] wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37] wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37] wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21] wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21] wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7] wire _io_enq_ready_T; // @[Misc.scala:26:53] wire _io_deq_valid_T_1; // @[Misc.scala:26:53] wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26] wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26] wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26] wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50] wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50] wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53] assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53] wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39] wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53] always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7] if (reset) // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26] else // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26] always @(posedge) Queue8_TLBundleD_a32d256s2k3z4u queue ( // @[LatencyInjectionQueue.scala:18:21] .clock (clock), .reset (reset), .io_enq_ready (_queue_io_enq_ready), .io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7] .io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits_opcode (io_deq_bits_opcode), .io_deq_bits_param (io_deq_bits_param), .io_deq_bits_size (io_deq_bits_size), .io_deq_bits_source (io_deq_bits_source_0), .io_deq_bits_sink (io_deq_bits_sink), .io_deq_bits_denied (io_deq_bits_denied), .io_deq_bits_data (io_deq_bits_data_0), .io_deq_bits_corrupt (io_deq_bits_corrupt) ); // @[LatencyInjectionQueue.scala:18:21] Queue8_UInt64_1 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37] .clock (clock), .reset (reset), .io_enq_ready (_release_ready_cycle_q_io_enq_ready), .io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50] .io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_release_ready_cycle_q_io_deq_valid), .io_deq_bits (_release_ready_cycle_q_io_deq_bits) ); // @[LatencyInjectionQueue.scala:19:37] assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_95 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_valid, slot_uop.iw_issued) when _T_40 : connect next_valid, rebusied	module IssueSlot_95( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_15 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} [16] wire _valids_WIRE : UInt<1>[16] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) connect _valids_WIRE[15], UInt<1>(0h0) regreset valids : UInt<1>[16], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = and(valids[3], _valids_3_T_2) node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0)) node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5) connect valids[3], _valids_3_T_6 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = and(valids[4], _valids_4_T_2) node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0)) node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5) connect valids[4], _valids_4_T_6 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = and(valids[5], _valids_5_T_2) node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0)) node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5) connect valids[5], _valids_5_T_6 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = and(valids[6], _valids_6_T_2) node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0)) node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5) connect valids[6], _valids_6_T_6 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = and(valids[7], _valids_7_T_2) node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0)) node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5) connect valids[7], _valids_7_T_6 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = and(valids[8], _valids_8_T_2) node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0)) node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5) connect valids[8], _valids_8_T_6 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = and(valids[9], _valids_9_T_2) node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0)) node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5) connect valids[9], _valids_9_T_6 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = and(valids[10], _valids_10_T_2) node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0)) node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5) connect valids[10], _valids_10_T_6 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = and(valids[11], _valids_11_T_2) node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0)) node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5) connect valids[11], _valids_11_T_6 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = and(valids[12], _valids_12_T_2) node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0)) node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5) connect valids[12], _valids_12_T_6 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = and(valids[13], _valids_13_T_2) node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0)) node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5) connect valids[13], _valids_13_T_6 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = and(valids[14], _valids_14_T_2) node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0)) node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5) connect valids[14], _valids_14_T_6 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask) node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0)) node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0)) node _valids_15_T_3 = and(valids[15], _valids_15_T_2) node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq) node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0)) node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5) connect valids[15], _valids_15_T_6 when valids[15] : node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T) connect uops[15].br_mask, _uops_15_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0hf)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = cat(_io_count_T, ptr_diff) connect io.count, _io_count_T_1	module BranchKillableQueue_15( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [33:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [1:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [33:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [3:0] out_uop_br_mask; // @[util.scala:506:17] wire [130:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire _valids_0_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_0_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_1_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_1_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_2_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_2_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_3_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_3_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_4_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_4_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_5_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_5_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_6_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_6_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_7_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_7_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_8_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_8_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_9_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_9_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_10_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_10_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_11_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_11_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_12_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_12_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_13_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_13_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_14_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_14_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_15_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_15_T_5 = 1'h1; // @[util.scala:481:72] wire _io_deq_valid_T_4 = 1'h1; // @[util.scala:509:68] wire _io_deq_valid_T_7 = 1'h1; // @[util.scala:509:111] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_15_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _io_deq_bits_uop_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[util.scala:448:7, :453:14] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:448:7, :453:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:448:7, :453:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:448:7, :453:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_valid = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:448:7] wire io_flush = 1'h0; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _valids_0_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_0_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_1_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_1_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_2_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_2_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_3_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_3_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_4_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_4_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_5_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_5_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_6_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_6_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_7_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_7_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_8_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_8_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_9_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_9_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_10_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_10_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_11_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_11_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_12_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_12_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_13_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_13_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_14_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_14_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_15_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_15_T_4 = 1'h0; // @[util.scala:481:83] wire _io_deq_valid_T_3 = 1'h0; // @[util.scala:118:59] wire _io_deq_valid_T_6 = 1'h0; // @[util.scala:509:122] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[util.scala:448:7, :453:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:448:7] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_15_T = 4'h0; // @[util.scala:118:51] wire _io_enq_ready_T; // @[util.scala:504:19] wire [3:0] _io_deq_valid_T_2 = 4'h0; // @[util.scala:118:51] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:85:25, :448:7] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [33:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [3:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [1:0] out_uop_br_tag; // @[util.scala:506:17] wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [5:0] out_uop_rob_idx; // @[util.scala:506:17] wire [3:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [3:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [3:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [33:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [21:0] out_old_meta_tag; // @[util.scala:506:17] wire [1:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] wire _valids_0_T_3 = valids_0; // @[util.scala:465:24, :481:29] reg valids_1; // @[util.scala:465:24] wire _valids_1_T_3 = valids_1; // @[util.scala:465:24, :481:29] reg valids_2; // @[util.scala:465:24] wire _valids_2_T_3 = valids_2; // @[util.scala:465:24, :481:29] reg valids_3; // @[util.scala:465:24] wire _valids_3_T_3 = valids_3; // @[util.scala:465:24, :481:29] reg valids_4; // @[util.scala:465:24] wire _valids_4_T_3 = valids_4; // @[util.scala:465:24, :481:29] reg valids_5; // @[util.scala:465:24] wire _valids_5_T_3 = valids_5; // @[util.scala:465:24, :481:29] reg valids_6; // @[util.scala:465:24] wire _valids_6_T_3 = valids_6; // @[util.scala:465:24, :481:29] reg valids_7; // @[util.scala:465:24] wire _valids_7_T_3 = valids_7; // @[util.scala:465:24, :481:29] reg valids_8; // @[util.scala:465:24] wire _valids_8_T_3 = valids_8; // @[util.scala:465:24, :481:29] reg valids_9; // @[util.scala:465:24] wire _valids_9_T_3 = valids_9; // @[util.scala:465:24, :481:29] reg valids_10; // @[util.scala:465:24] wire _valids_10_T_3 = valids_10; // @[util.scala:465:24, :481:29] reg valids_11; // @[util.scala:465:24] wire _valids_11_T_3 = valids_11; // @[util.scala:465:24, :481:29] reg valids_12; // @[util.scala:465:24] wire _valids_12_T_3 = valids_12; // @[util.scala:465:24, :481:29] reg valids_13; // @[util.scala:465:24] wire _valids_13_T_3 = valids_13; // @[util.scala:465:24, :481:29] reg valids_14; // @[util.scala:465:24] wire _valids_14_T_3 = valids_14; // @[util.scala:465:24, :481:29] reg valids_15; // @[util.scala:465:24] wire _valids_15_T_3 = valids_15; // @[util.scala:465:24, :481:29] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [33:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [3:0] uops_0_br_mask; // @[util.scala:466:20] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_0_br_tag; // @[util.scala:466:20] reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [5:0] uops_0_rob_idx; // @[util.scala:466:20] reg [3:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [3:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [33:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [3:0] uops_1_br_mask; // @[util.scala:466:20] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_1_br_tag; // @[util.scala:466:20] reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [5:0] uops_1_rob_idx; // @[util.scala:466:20] reg [3:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [3:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [33:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [3:0] uops_2_br_mask; // @[util.scala:466:20] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_2_br_tag; // @[util.scala:466:20] reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [5:0] uops_2_rob_idx; // @[util.scala:466:20] reg [3:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [3:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [33:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [3:0] uops_3_br_mask; // @[util.scala:466:20] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_3_br_tag; // @[util.scala:466:20] reg [3:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [5:0] uops_3_rob_idx; // @[util.scala:466:20] reg [3:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [3:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [33:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [3:0] uops_4_br_mask; // @[util.scala:466:20] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_4_br_tag; // @[util.scala:466:20] reg [3:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [5:0] uops_4_rob_idx; // @[util.scala:466:20] reg [3:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [3:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [33:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [3:0] uops_5_br_mask; // @[util.scala:466:20] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_5_br_tag; // @[util.scala:466:20] reg [3:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [5:0] uops_5_rob_idx; // @[util.scala:466:20] reg [3:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [3:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [33:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [3:0] uops_6_br_mask; // @[util.scala:466:20] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_6_br_tag; // @[util.scala:466:20] reg [3:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [5:0] uops_6_rob_idx; // @[util.scala:466:20] reg [3:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [3:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [33:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [3:0] uops_7_br_mask; // @[util.scala:466:20] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_7_br_tag; // @[util.scala:466:20] reg [3:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [5:0] uops_7_rob_idx; // @[util.scala:466:20] reg [3:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [3:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [33:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [3:0] uops_8_br_mask; // @[util.scala:466:20] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_8_br_tag; // @[util.scala:466:20] reg [3:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [5:0] uops_8_rob_idx; // @[util.scala:466:20] reg [3:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [3:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [33:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [3:0] uops_9_br_mask; // @[util.scala:466:20] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_9_br_tag; // @[util.scala:466:20] reg [3:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [5:0] uops_9_rob_idx; // @[util.scala:466:20] reg [3:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [3:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [33:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [3:0] uops_10_br_mask; // @[util.scala:466:20] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_10_br_tag; // @[util.scala:466:20] reg [3:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [5:0] uops_10_rob_idx; // @[util.scala:466:20] reg [3:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [3:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [33:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [3:0] uops_11_br_mask; // @[util.scala:466:20] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_11_br_tag; // @[util.scala:466:20] reg [3:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [5:0] uops_11_rob_idx; // @[util.scala:466:20] reg [3:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [3:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [33:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [3:0] uops_12_br_mask; // @[util.scala:466:20] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_12_br_tag; // @[util.scala:466:20] reg [3:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [5:0] uops_12_rob_idx; // @[util.scala:466:20] reg [3:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [3:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [33:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [3:0] uops_13_br_mask; // @[util.scala:466:20] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_13_br_tag; // @[util.scala:466:20] reg [3:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [5:0] uops_13_rob_idx; // @[util.scala:466:20] reg [3:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [3:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [33:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [3:0] uops_14_br_mask; // @[util.scala:466:20] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_14_br_tag; // @[util.scala:466:20] reg [3:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [5:0] uops_14_rob_idx; // @[util.scala:466:20] reg [3:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [3:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [33:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [3:0] uops_15_br_mask; // @[util.scala:466:20] wire [3:0] _uops_15_br_mask_T_1 = uops_15_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_15_br_tag; // @[util.scala:466:20] reg [3:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [5:0] uops_15_rob_idx; // @[util.scala:466:20] reg [3:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [3:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 \| _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire _valids_0_T_6 = _valids_0_T_3; // @[util.scala:481:{29,69}] wire _valids_1_T_6 = _valids_1_T_3; // @[util.scala:481:{29,69}] wire _valids_2_T_6 = _valids_2_T_3; // @[util.scala:481:{29,69}] wire _valids_3_T_6 = _valids_3_T_3; // @[util.scala:481:{29,69}] wire _valids_4_T_6 = _valids_4_T_3; // @[util.scala:481:{29,69}] wire _valids_5_T_6 = _valids_5_T_3; // @[util.scala:481:{29,69}] wire _valids_6_T_6 = _valids_6_T_3; // @[util.scala:481:{29,69}] wire _valids_7_T_6 = _valids_7_T_3; // @[util.scala:481:{29,69}] wire _valids_8_T_6 = _valids_8_T_3; // @[util.scala:481:{29,69}] wire _valids_9_T_6 = _valids_9_T_3; // @[util.scala:481:{29,69}] wire _valids_10_T_6 = _valids_10_T_3; // @[util.scala:481:{29,69}] wire _valids_11_T_6 = _valids_11_T_3; // @[util.scala:481:{29,69}] wire _valids_12_T_6 = _valids_12_T_3; // @[util.scala:481:{29,69}] wire _valids_13_T_6 = _valids_13_T_3; // @[util.scala:481:{29,69}] wire _valids_14_T_6 = _valids_14_T_3; // @[util.scala:481:{29,69}] wire _valids_15_T_6 = _valids_15_T_3; // @[util.scala:481:{29,69}] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask; // @[util.scala:85:25, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire _io_deq_valid_T_5 = _io_deq_valid_T_1; // @[util.scala:509:{40,65}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5; // @[util.scala:509:{65,108}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 \| _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 \| _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 \| _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 \| _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 \| _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 \| _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 \| _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 \| _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 \| _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 \| _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 \| _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 \| _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 \| _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 \| _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 \| _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 \| _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x131 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_9 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<18>(0h20000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<18>(0h21000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<18>(0h22000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<18>(0h23000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<18>(0h24000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<17>(0h10000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) node _legal_address_T_60 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_61 = cvt(_legal_address_T_60) node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000))) node _legal_address_T_63 = asSInt(_legal_address_T_62) node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0))) node _legal_address_T_65 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_66 = cvt(_legal_address_T_65) node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<17>(0h10000))) node _legal_address_T_68 = asSInt(_legal_address_T_67) node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0))) node _legal_address_T_70 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_71 = cvt(_legal_address_T_70) node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<27>(0h4000000))) node _legal_address_T_73 = asSInt(_legal_address_T_72) node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0))) node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_76 = cvt(_legal_address_T_75) node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000))) node _legal_address_T_78 = asSInt(_legal_address_T_77) node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0))) node _legal_address_T_80 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_81 = cvt(_legal_address_T_80) node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<29>(0h10000000))) node _legal_address_T_83 = asSInt(_legal_address_T_82) node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[17] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 connect _legal_address_WIRE[12], _legal_address_T_64 connect _legal_address_WIRE[13], _legal_address_T_69 connect _legal_address_WIRE[14], _legal_address_T_74 connect _legal_address_WIRE[15], _legal_address_T_79 connect _legal_address_WIRE[16], _legal_address_T_84 node _legal_address_T_85 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_86 = or(_legal_address_T_85, _legal_address_WIRE[2]) node _legal_address_T_87 = or(_legal_address_T_86, _legal_address_WIRE[3]) node _legal_address_T_88 = or(_legal_address_T_87, _legal_address_WIRE[4]) node _legal_address_T_89 = or(_legal_address_T_88, _legal_address_WIRE[5]) node _legal_address_T_90 = or(_legal_address_T_89, _legal_address_WIRE[6]) node _legal_address_T_91 = or(_legal_address_T_90, _legal_address_WIRE[7]) node _legal_address_T_92 = or(_legal_address_T_91, _legal_address_WIRE[8]) node _legal_address_T_93 = or(_legal_address_T_92, _legal_address_WIRE[9]) node _legal_address_T_94 = or(_legal_address_T_93, _legal_address_WIRE[10]) node _legal_address_T_95 = or(_legal_address_T_94, _legal_address_WIRE[11]) node _legal_address_T_96 = or(_legal_address_T_95, _legal_address_WIRE[12]) node _legal_address_T_97 = or(_legal_address_T_96, _legal_address_WIRE[13]) node _legal_address_T_98 = or(_legal_address_T_97, _legal_address_WIRE[14]) node _legal_address_T_99 = or(_legal_address_T_98, _legal_address_WIRE[15]) node legal_address = or(_legal_address_T_99, _legal_address_WIRE[16]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c020000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c031000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<18>(0h20000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c030000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_16 = cvt(_io_resp_cacheable_T_15) node _io_resp_cacheable_T_17 = and(_io_resp_cacheable_T_16, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_18 = asSInt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = eq(_io_resp_cacheable_T_18, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_20 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_21 = or(_io_resp_cacheable_T_20, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_22 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_19) node _io_resp_cacheable_T_23 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_24 = cvt(_io_resp_cacheable_T_23) node _io_resp_cacheable_T_25 = and(_io_resp_cacheable_T_24, asSInt(UInt<33>(0h8c030000))) node _io_resp_cacheable_T_26 = asSInt(_io_resp_cacheable_T_25) node _io_resp_cacheable_T_27 = eq(_io_resp_cacheable_T_26, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_28 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_29 = cvt(_io_resp_cacheable_T_28) node _io_resp_cacheable_T_30 = and(_io_resp_cacheable_T_29, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_31 = asSInt(_io_resp_cacheable_T_30) node _io_resp_cacheable_T_32 = eq(_io_resp_cacheable_T_31, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_33 = or(_io_resp_cacheable_T_27, _io_resp_cacheable_T_32) node _io_resp_cacheable_T_34 = mux(_io_resp_cacheable_T_22, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_35 = mux(_io_resp_cacheable_T_33, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_36 = or(_io_resp_cacheable_T_34, _io_resp_cacheable_T_35) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_36 node _io_resp_cacheable_T_37 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_37 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_36 = cvt(_io_resp_w_T_35) node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37) node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0))) node _io_resp_w_T_40 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_41 = or(_io_resp_w_T_40, _io_resp_w_T_14) node _io_resp_w_T_42 = or(_io_resp_w_T_41, _io_resp_w_T_19) node _io_resp_w_T_43 = or(_io_resp_w_T_42, _io_resp_w_T_24) node _io_resp_w_T_44 = or(_io_resp_w_T_43, _io_resp_w_T_29) node _io_resp_w_T_45 = or(_io_resp_w_T_44, _io_resp_w_T_34) node _io_resp_w_T_46 = or(_io_resp_w_T_45, _io_resp_w_T_39) node _io_resp_w_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_48 = cvt(_io_resp_w_T_47) node _io_resp_w_T_49 = and(_io_resp_w_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_w_T_50 = asSInt(_io_resp_w_T_49) node _io_resp_w_T_51 = eq(_io_resp_w_T_50, asSInt(UInt<1>(0h0))) node _io_resp_w_T_52 = mux(_io_resp_w_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_53 = mux(_io_resp_w_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_54 = or(_io_resp_w_T_52, _io_resp_w_T_53) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_54 node _io_resp_w_T_55 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_55 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35) node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37) node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_40 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_41 = or(_io_resp_pp_T_40, _io_resp_pp_T_14) node _io_resp_pp_T_42 = or(_io_resp_pp_T_41, _io_resp_pp_T_19) node _io_resp_pp_T_43 = or(_io_resp_pp_T_42, _io_resp_pp_T_24) node _io_resp_pp_T_44 = or(_io_resp_pp_T_43, _io_resp_pp_T_29) node _io_resp_pp_T_45 = or(_io_resp_pp_T_44, _io_resp_pp_T_34) node _io_resp_pp_T_46 = or(_io_resp_pp_T_45, _io_resp_pp_T_39) node _io_resp_pp_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_48 = cvt(_io_resp_pp_T_47) node _io_resp_pp_T_49 = and(_io_resp_pp_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_pp_T_50 = asSInt(_io_resp_pp_T_49) node _io_resp_pp_T_51 = eq(_io_resp_pp_T_50, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_52 = mux(_io_resp_pp_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_53 = mux(_io_resp_pp_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_54 = or(_io_resp_pp_T_52, _io_resp_pp_T_53) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_54 node _io_resp_pp_T_55 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_55 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_36 = cvt(_io_resp_al_T_35) node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37) node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0))) node _io_resp_al_T_40 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_41 = or(_io_resp_al_T_40, _io_resp_al_T_14) node _io_resp_al_T_42 = or(_io_resp_al_T_41, _io_resp_al_T_19) node _io_resp_al_T_43 = or(_io_resp_al_T_42, _io_resp_al_T_24) node _io_resp_al_T_44 = or(_io_resp_al_T_43, _io_resp_al_T_29) node _io_resp_al_T_45 = or(_io_resp_al_T_44, _io_resp_al_T_34) node _io_resp_al_T_46 = or(_io_resp_al_T_45, _io_resp_al_T_39) node _io_resp_al_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_48 = cvt(_io_resp_al_T_47) node _io_resp_al_T_49 = and(_io_resp_al_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_al_T_50 = asSInt(_io_resp_al_T_49) node _io_resp_al_T_51 = eq(_io_resp_al_T_50, asSInt(UInt<1>(0h0))) node _io_resp_al_T_52 = mux(_io_resp_al_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_53 = mux(_io_resp_al_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_54 = or(_io_resp_al_T_52, _io_resp_al_T_53) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_54 node _io_resp_al_T_55 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_55 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35) node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37) node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_40 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_41 = or(_io_resp_aa_T_40, _io_resp_aa_T_14) node _io_resp_aa_T_42 = or(_io_resp_aa_T_41, _io_resp_aa_T_19) node _io_resp_aa_T_43 = or(_io_resp_aa_T_42, _io_resp_aa_T_24) node _io_resp_aa_T_44 = or(_io_resp_aa_T_43, _io_resp_aa_T_29) node _io_resp_aa_T_45 = or(_io_resp_aa_T_44, _io_resp_aa_T_34) node _io_resp_aa_T_46 = or(_io_resp_aa_T_45, _io_resp_aa_T_39) node _io_resp_aa_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_48 = cvt(_io_resp_aa_T_47) node _io_resp_aa_T_49 = and(_io_resp_aa_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_aa_T_50 = asSInt(_io_resp_aa_T_49) node _io_resp_aa_T_51 = eq(_io_resp_aa_T_50, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_52 = mux(_io_resp_aa_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_53 = mux(_io_resp_aa_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_54 = or(_io_resp_aa_T_52, _io_resp_aa_T_53) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_54 node _io_resp_aa_T_55 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_55 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0hffff0000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0hf0000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<18>(0h20000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0hffffc000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<18>(0h24000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0hfffef000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0hffff0000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_60 = cvt(_io_resp_x_T_59) node _io_resp_x_T_61 = and(_io_resp_x_T_60, asSInt(UInt<33>(0hfc000000))) node _io_resp_x_T_62 = asSInt(_io_resp_x_T_61) node _io_resp_x_T_63 = eq(_io_resp_x_T_62, asSInt(UInt<1>(0h0))) node _io_resp_x_T_64 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_x_T_65 = cvt(_io_resp_x_T_64) node _io_resp_x_T_66 = and(_io_resp_x_T_65, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_67 = asSInt(_io_resp_x_T_66) node _io_resp_x_T_68 = eq(_io_resp_x_T_67, asSInt(UInt<1>(0h0))) node _io_resp_x_T_69 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_70 = or(_io_resp_x_T_69, _io_resp_x_T_43) node _io_resp_x_T_71 = or(_io_resp_x_T_70, _io_resp_x_T_48) node _io_resp_x_T_72 = or(_io_resp_x_T_71, _io_resp_x_T_53) node _io_resp_x_T_73 = or(_io_resp_x_T_72, _io_resp_x_T_58) node _io_resp_x_T_74 = or(_io_resp_x_T_73, _io_resp_x_T_63) node _io_resp_x_T_75 = or(_io_resp_x_T_74, _io_resp_x_T_68) node _io_resp_x_T_76 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_77 = mux(_io_resp_x_T_75, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_78 = or(_io_resp_x_T_76, _io_resp_x_T_77) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_78 node _io_resp_x_T_79 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_79 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hffffa000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<18>(0h20000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hffff8000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hfffeb000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hffff0000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hffffb000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30) node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hffffb000))) node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32) node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14) node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19) node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24) node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29) node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34) node _io_resp_eff_T_41 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41) node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hffffb000))) node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43) node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46) node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hffff0000))) node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48) node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_51 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51) node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hffff0000))) node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53) node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_56 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_57 = cvt(_io_resp_eff_T_56) node _io_resp_eff_T_58 = and(_io_resp_eff_T_57, asSInt(UInt<33>(0hf0000000))) node _io_resp_eff_T_59 = asSInt(_io_resp_eff_T_58) node _io_resp_eff_T_60 = eq(_io_resp_eff_T_59, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_61 = or(_io_resp_eff_T_45, _io_resp_eff_T_50) node _io_resp_eff_T_62 = or(_io_resp_eff_T_61, _io_resp_eff_T_55) node _io_resp_eff_T_63 = or(_io_resp_eff_T_62, _io_resp_eff_T_60) node _io_resp_eff_T_64 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_65 = mux(_io_resp_eff_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_66 = or(_io_resp_eff_T_64, _io_resp_eff_T_65) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_66 node _io_resp_eff_T_67 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_67	module PMAChecker_9( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_37; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_55; // @[PMA.scala:39:19] wire _io_resp_pp_T_55; // @[PMA.scala:39:19] wire _io_resp_al_T_55; // @[PMA.scala:39:19] wire _io_resp_aa_T_55; // @[PMA.scala:39:19] wire _io_resp_x_T_79; // @[PMA.scala:39:19] wire _io_resp_eff_T_67; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31] assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_47; // @[Parameters.scala:137:31] assign _io_resp_w_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_47; // @[Parameters.scala:137:31] assign _io_resp_pp_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_47; // @[Parameters.scala:137:31] assign _io_resp_al_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_47; // @[Parameters.scala:137:31] assign _io_resp_aa_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31] assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h20000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h21000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_30 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h22000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_35 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h23000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h24000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31] assign _legal_address_T_60 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46] wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_65; // @[Parameters.scala:137:31] assign _legal_address_T_65 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_23; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_23 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31] assign _io_resp_eff_T_51 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46] wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40] wire [39:0] _GEN_8 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_70; // @[Parameters.scala:137:31] assign _legal_address_T_70 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_15; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_15 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31] assign _io_resp_x_T_59 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46] wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40] wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_75; // @[Parameters.scala:137:31] assign _legal_address_T_75 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_64; // @[Parameters.scala:137:31] assign _io_resp_x_T_64 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31] assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46] wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40] wire [39:0] _GEN_10 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31] assign _legal_address_T_80 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_28; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_28 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31] assign _io_resp_w_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31] assign _io_resp_pp_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31] assign _io_resp_al_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31] assign _io_resp_aa_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31] assign _io_resp_eff_T_56 = _GEN_10; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46] wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40] wire _legal_address_T_85 = _legal_address_WIRE_0 \| _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_86 = _legal_address_T_85 \| _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_87 = _legal_address_T_86 \| _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_88 = _legal_address_T_87 \| _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_89 = _legal_address_T_88 \| _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_90 = _legal_address_T_89 \| _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_91 = _legal_address_T_90 \| _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_92 = _legal_address_T_91 \| _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_93 = _legal_address_T_92 \| _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_94 = _legal_address_T_93 \| _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire _legal_address_T_95 = _legal_address_T_94 \| _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire _legal_address_T_96 = _legal_address_T_95 \| _legal_address_WIRE_12; // @[Parameters.scala:612:40] wire _legal_address_T_97 = _legal_address_T_96 \| _legal_address_WIRE_13; // @[Parameters.scala:612:40] wire _legal_address_T_98 = _legal_address_T_97 \| _legal_address_WIRE_14; // @[Parameters.scala:612:40] wire _legal_address_T_99 = _legal_address_T_98 \| _legal_address_WIRE_15; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_99 \| _legal_address_WIRE_16; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C020000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C031000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_16 = {1'h0, _io_resp_cacheable_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_17 = _io_resp_cacheable_T_16 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_4 \| _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 \| _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_22 = _io_resp_cacheable_T_21 \| _io_resp_cacheable_T_19; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_24 = {1'h0, _io_resp_cacheable_T_23}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_26 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_29 = {1'h0, _io_resp_cacheable_T_28}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_31 = _io_resp_cacheable_T_30; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_32 = _io_resp_cacheable_T_31 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_33 = _io_resp_cacheable_T_27 \| _io_resp_cacheable_T_32; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_35 = _io_resp_cacheable_T_33; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_36 = _io_resp_cacheable_T_35; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_36; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_37 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_37; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46] wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_40 = _io_resp_w_T_4 \| _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_41 = _io_resp_w_T_40 \| _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_42 = _io_resp_w_T_41 \| _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_43 = _io_resp_w_T_42 \| _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_44 = _io_resp_w_T_43 \| _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_45 = _io_resp_w_T_44 \| _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_45 \| _io_resp_w_T_39; // @[Parameters.scala:629:89] wire _io_resp_w_T_52 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_48 = {1'h0, _io_resp_w_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_49 = _io_resp_w_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_50 = _io_resp_w_T_49; // @[Parameters.scala:137:46] wire _io_resp_w_T_51 = _io_resp_w_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_54 = _io_resp_w_T_52; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_54; // @[Mux.scala:30:73] assign _io_resp_w_T_55 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_40 = _io_resp_pp_T_4 \| _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_41 = _io_resp_pp_T_40 \| _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_42 = _io_resp_pp_T_41 \| _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_43 = _io_resp_pp_T_42 \| _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_44 = _io_resp_pp_T_43 \| _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 \| _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_45 \| _io_resp_pp_T_39; // @[Parameters.scala:629:89] wire _io_resp_pp_T_52 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_48 = {1'h0, _io_resp_pp_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_49 = _io_resp_pp_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_50 = _io_resp_pp_T_49; // @[Parameters.scala:137:46] wire _io_resp_pp_T_51 = _io_resp_pp_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_54 = _io_resp_pp_T_52; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_54; // @[Mux.scala:30:73] assign _io_resp_pp_T_55 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46] wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_40 = _io_resp_al_T_4 \| _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_41 = _io_resp_al_T_40 \| _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_42 = _io_resp_al_T_41 \| _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_43 = _io_resp_al_T_42 \| _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_44 = _io_resp_al_T_43 \| _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_45 = _io_resp_al_T_44 \| _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_45 \| _io_resp_al_T_39; // @[Parameters.scala:629:89] wire _io_resp_al_T_52 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_48 = {1'h0, _io_resp_al_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_49 = _io_resp_al_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_50 = _io_resp_al_T_49; // @[Parameters.scala:137:46] wire _io_resp_al_T_51 = _io_resp_al_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_54 = _io_resp_al_T_52; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_54; // @[Mux.scala:30:73] assign _io_resp_al_T_55 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_40 = _io_resp_aa_T_4 \| _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_41 = _io_resp_aa_T_40 \| _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_42 = _io_resp_aa_T_41 \| _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_43 = _io_resp_aa_T_42 \| _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_44 = _io_resp_aa_T_43 \| _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 \| _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_45 \| _io_resp_aa_T_39; // @[Parameters.scala:629:89] wire _io_resp_aa_T_52 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_48 = {1'h0, _io_resp_aa_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_49 = _io_resp_aa_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_50 = _io_resp_aa_T_49; // @[Parameters.scala:137:46] wire _io_resp_aa_T_51 = _io_resp_aa_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_54 = _io_resp_aa_T_52; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_54; // @[Mux.scala:30:73] assign _io_resp_aa_T_55 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 \| _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 \| _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 \| _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 \| _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_76 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFFC000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46] wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_65 = {1'h0, _io_resp_x_T_64}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_66 = _io_resp_x_T_65 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_67 = _io_resp_x_T_66; // @[Parameters.scala:137:46] wire _io_resp_x_T_68 = _io_resp_x_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_69 = _io_resp_x_T_33 \| _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_70 = _io_resp_x_T_69 \| _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_71 = _io_resp_x_T_70 \| _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_72 = _io_resp_x_T_71 \| _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_73 = _io_resp_x_T_72 \| _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_74 = _io_resp_x_T_73 \| _io_resp_x_T_63; // @[Parameters.scala:629:89] wire _io_resp_x_T_75 = _io_resp_x_T_74 \| _io_resp_x_T_68; // @[Parameters.scala:629:89] wire _io_resp_x_T_78 = _io_resp_x_T_76; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_78; // @[Mux.scala:30:73] assign _io_resp_x_T_79 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_79; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_35 = _io_resp_eff_T_4 \| _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_36 = _io_resp_eff_T_35 \| _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_37 = _io_resp_eff_T_36 \| _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_38 = _io_resp_eff_T_37 \| _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 \| _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_40 = _io_resp_eff_T_39 \| _io_resp_eff_T_34; // @[Parameters.scala:629:89] wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46] wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46] wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46] wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46] wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_61 = _io_resp_eff_T_45 \| _io_resp_eff_T_50; // @[Parameters.scala:629:89] wire _io_resp_eff_T_62 = _io_resp_eff_T_61 \| _io_resp_eff_T_55; // @[Parameters.scala:629:89] wire _io_resp_eff_T_63 = _io_resp_eff_T_62 \| _io_resp_eff_T_60; // @[Parameters.scala:629:89] wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73] assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_11 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_22 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_23 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_11( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_207 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_207( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module FlitToPhit_f32_p32_9 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}} reg data : UInt<32>[0], clock regreset beat : UInt<0>, clock, reset, UInt<0>(0h0) node _io_in_ready_T = eq(beat, UInt<1>(0h0)) node _io_in_ready_T_1 = and(io.out.ready, _io_in_ready_T) connect io.in.ready, _io_in_ready_T_1 node _io_out_valid_T = neq(beat, UInt<1>(0h0)) node _io_out_valid_T_1 = or(io.in.valid, _io_out_valid_T) connect io.out.valid, _io_out_valid_T_1 connect io.out.bits.phit, io.in.bits.flit node _T = and(io.out.ready, io.out.valid) when _T : node _beat_T = eq(beat, UInt<1>(0h0)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = eq(beat, UInt<1>(0h0)) when _T_1 : wire _WIRE : UInt<32>[1] wire _WIRE_1 : UInt<32> connect _WIRE_1, io.in.bits.flit node _T_2 = bits(_WIRE_1, 31, 0) connect _WIRE[0], _T_2	module FlitToPhit_f32_p32_9( // @[Serdes.scala:71:7] input clock, // @[Serdes.scala:71:7] input reset, // @[Serdes.scala:71:7] output io_in_ready, // @[Serdes.scala:73:14] input io_in_valid, // @[Serdes.scala:73:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:73:14] input io_out_ready, // @[Serdes.scala:73:14] output io_out_valid, // @[Serdes.scala:73:14] output [31:0] io_out_bits_phit // @[Serdes.scala:73:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:71:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:71:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:71:7] wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T = 1'h1; // @[Serdes.scala:83:39] wire _beat_T = 1'h1; // @[Serdes.scala:88:22] wire _beat_T_2 = 1'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T_1; // @[Serdes.scala:83:31] wire _io_out_valid_T = 1'h0; // @[Serdes.scala:84:39] wire _beat_T_3 = 1'h0; // @[Serdes.scala:88:16] wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:71:7, :84:31] wire [31:0] io_out_bits_phit_0 = io_in_bits_flit_0; // @[Serdes.scala:71:7] assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:71:7, :83:31] wire io_in_ready_0; // @[Serdes.scala:71:7] wire io_out_valid_0; // @[Serdes.scala:71:7] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:71:7, :83:31] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:71:7, :84:31] assign io_in_ready = io_in_ready_0; // @[Serdes.scala:71:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:71:7] assign io_out_bits_phit = io_out_bits_phit_0; // @[Serdes.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_8 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_24 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_25 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_26 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[5], sa_stall : UInt[5]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.sa_stall[4] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] invalidate debugNodeOut.va_stall[4] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_4 of InputUnit_24 connect input_unit_0_from_4.clock, clock connect input_unit_0_from_4.reset, reset inst input_unit_1_from_9 of InputUnit_25 connect input_unit_1_from_9.clock, clock connect input_unit_1_from_9.reset, reset inst input_unit_2_from_12 of InputUnit_26 connect input_unit_2_from_12.clock, clock connect input_unit_2_from_12.reset, reset inst ingress_unit_3_from_14 of IngressUnit_17 connect ingress_unit_3_from_14.clock, clock connect ingress_unit_3_from_14.reset, reset inst ingress_unit_4_from_15 of IngressUnit_18 connect ingress_unit_4_from_15.clock, clock connect ingress_unit_4_from_15.reset, reset inst output_unit_0_to_4 of OutputUnit_24 connect output_unit_0_to_4.clock, clock connect output_unit_0_to_4.reset, reset inst output_unit_1_to_9 of OutputUnit_25 connect output_unit_1_to_9.clock, clock connect output_unit_1_to_9.reset, reset inst output_unit_2_to_12 of OutputUnit_26 connect output_unit_2_to_12.clock, clock connect output_unit_2_to_12.reset, reset inst egress_unit_3_to_7 of EgressUnit_13 connect egress_unit_3_to_7.clock, clock connect egress_unit_3_to_7.reset, reset inst switch of Switch_8 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_8 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_8 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_8 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = and(vc_allocator.io.req.`4`.ready, vc_allocator.io.req.`4`.valid) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) node _fires_count_T_7 = add(_fires_count_T_3, _fires_count_T_4) node _fires_count_T_8 = bits(_fires_count_T_7, 1, 0) node _fires_count_T_9 = add(_fires_count_T_2, _fires_count_T_8) node _fires_count_T_10 = bits(_fires_count_T_9, 1, 0) node _fires_count_T_11 = add(_fires_count_T_6, _fires_count_T_10) node _fires_count_T_12 = bits(_fires_count_T_11, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_12 connect input_unit_0_from_4.io.in, destNodesIn connect input_unit_1_from_9.io.in, destNodesIn_1 connect input_unit_2_from_12.io.in, destNodesIn_2 connect ingress_unit_3_from_14.io.in, ingressNodesIn.flit connect ingress_unit_4_from_15.io.in, ingressNodesIn_1.flit connect output_unit_0_to_4.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_4.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_4.io.out.flit connect output_unit_1_to_9.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_9.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_9.io.out.flit connect output_unit_2_to_12.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_12.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_12.io.out.flit connect egressNodesOut.flit.bits, egress_unit_3_to_7.io.out.bits connect egressNodesOut.flit.valid, egress_unit_3_to_7.io.out.valid connect egress_unit_3_to_7.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_4.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_9.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_12.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_14.io.router_req connect route_computer.io.req.`4`, ingress_unit_4_from_15.io.router_req connect input_unit_0_from_4.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_9.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_12.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_14.io.router_resp, route_computer.io.resp.`3` connect ingress_unit_4_from_15.io.router_resp, route_computer.io.resp.`4` connect vc_allocator.io.req.`0`, input_unit_0_from_4.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_9.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_12.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_14.io.vcalloc_req connect vc_allocator.io.req.`4`, ingress_unit_4_from_15.io.vcalloc_req connect input_unit_0_from_4.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_9.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_12.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_14.io.vcalloc_resp, vc_allocator.io.resp.`3` connect ingress_unit_4_from_15.io.vcalloc_resp, vc_allocator.io.resp.`4` connect output_unit_0_to_4.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_9.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_12.io.allocs, vc_allocator.io.out_allocs.`2` connect egress_unit_3_to_7.io.allocs, vc_allocator.io.out_allocs.`3` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_4.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_4.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_4.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_4.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_4.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_4.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_4.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_4.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_4.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_4.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_4.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_4.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_4.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_4.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_4.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_9.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_9.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_9.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_9.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_9.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_9.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_9.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_9.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_9.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_9.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_9.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_9.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_9.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_9.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_9.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_9.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_9.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_9.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_12.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_12.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_12.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_12.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_12.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_12.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_12.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_12.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_12.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_12.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_12.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_7.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_7.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_7.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_7.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_7.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_7.io.channel_status[0].occupied connect input_unit_0_from_4.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_1_from_9.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_1_from_9.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect input_unit_1_from_9.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect input_unit_1_from_9.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_1_from_9.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_1_from_9.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect ingress_unit_4_from_15.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect ingress_unit_4_from_15.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect ingress_unit_4_from_15.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect ingress_unit_4_from_15.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect ingress_unit_4_from_15.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect ingress_unit_4_from_15.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_4.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_9.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_12.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_14.io.salloc_req[0] connect switch_allocator.io.req.`4`[0], ingress_unit_4_from_15.io.salloc_req[0] connect output_unit_0_to_4.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_4.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_4.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_4.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_4.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_4.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_1_to_9.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_9.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_9.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_9.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_9.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_9.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_2_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect egress_unit_3_to_7.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail connect egress_unit_3_to_7.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_4.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_9.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_12.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_14.io.out[0] connect switch.io.in.`4`[0], ingress_unit_4_from_15.io.out[0] connect output_unit_0_to_4.io.in, switch.io.out.`0` connect output_unit_1_to_9.io.in, switch.io.out.`1` connect output_unit_2_to_12.io.in, switch.io.out.`2` connect egress_unit_3_to_7.io.in, switch.io.out.`3` connect switch.io.sel.`0`[0].`0`[0], switch_allocator.io.switch_sel.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], switch_allocator.io.switch_sel.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], switch_allocator.io.switch_sel.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], switch_allocator.io.switch_sel.`0`[0].`3`[0] connect switch.io.sel.`0`[0].`4`[0], switch_allocator.io.switch_sel.`0`[0].`4`[0] connect switch.io.sel.`1`[0].`0`[0], switch_allocator.io.switch_sel.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], switch_allocator.io.switch_sel.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], switch_allocator.io.switch_sel.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], switch_allocator.io.switch_sel.`1`[0].`3`[0] connect switch.io.sel.`1`[0].`4`[0], switch_allocator.io.switch_sel.`1`[0].`4`[0] connect switch.io.sel.`2`[0].`0`[0], switch_allocator.io.switch_sel.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], switch_allocator.io.switch_sel.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], switch_allocator.io.switch_sel.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], switch_allocator.io.switch_sel.`2`[0].`3`[0] connect switch.io.sel.`2`[0].`4`[0], switch_allocator.io.switch_sel.`2`[0].`4`[0] connect switch.io.sel.`3`[0].`0`[0], switch_allocator.io.switch_sel.`3`[0].`0`[0] connect switch.io.sel.`3`[0].`1`[0], switch_allocator.io.switch_sel.`3`[0].`1`[0] connect switch.io.sel.`3`[0].`2`[0], switch_allocator.io.switch_sel.`3`[0].`2`[0] connect switch.io.sel.`3`[0].`3`[0], switch_allocator.io.switch_sel.`3`[0].`3`[0] connect switch.io.sel.`3`[0].`4`[0], switch_allocator.io.switch_sel.`3`[0].`4`[0] connect input_unit_0_from_4.io.block, UInt<1>(0h0) connect input_unit_1_from_9.io.block, UInt<1>(0h0) connect input_unit_2_from_12.io.block, UInt<1>(0h0) connect ingress_unit_3_from_14.io.block, UInt<1>(0h0) connect ingress_unit_4_from_15.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_4.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_9.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_12.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_14.io.debug.va_stall connect debugNodeOut.va_stall[4], ingress_unit_4_from_15.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_4.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_9.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_12.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_14.io.debug.sa_stall connect debugNodeOut.sa_stall[4], ingress_unit_4_from_15.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_34 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 4 8 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 9 8 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 12 8 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid node _T_27 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_27) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_27) connect fired_3, _fired_T_3 node _T_28 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_29 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_30 = tail(_T_29, 1) node _T_31 = eq(debug_sample, _T_30) node _T_32 = and(_T_28, _T_31) node _T_33 = and(_T_32, fired_3) when _T_33 : node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "nocsample %d i14 8 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_27 node _T_36 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_36) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_36) connect fired_4, _fired_T_4 node _T_37 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_38 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_39 = tail(_T_38, 1) node _T_40 = eq(debug_sample, _T_39) node _T_41 = and(_T_37, _T_40) node _T_42 = and(_T_41, fired_4) when _T_42 : node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "nocsample %d i15 8 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_36 node _T_45 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_45) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_45) connect fired_5, _fired_T_5 node _T_46 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_47 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_48 = tail(_T_47, 1) node _T_49 = eq(debug_sample, _T_48) node _T_50 = and(_T_46, _T_49) node _T_51 = and(_T_50, fired_5) when _T_51 : node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "nocsample %d 8 e7 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_45	module Router_8( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_3_to_7_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_3_to_7_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_3_to_7_io_out_valid; // @[Router.scala:125:13] wire _output_unit_2_to_12_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_2_to_12_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _ingress_unit_4_from_15_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_4_from_15_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_in_ready; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_3_from_14_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_2_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_9_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_1_from_9_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_0_from_4_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_9_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_14_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_15_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module RegisterReadDecode_2 : input clock : Clock input reset : Reset output io : { flip iss_valid : UInt<1>, flip iss_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rrd_valid : UInt<1>, rrd_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}} connect io.rrd_uop, io.iss_uop wire rrd_cs : { br_type : UInt<4>, use_alupipe : UInt<1>, use_muldivpipe : UInt<1>, use_mempipe : UInt<1>, op_fcn : UInt<5>, fcn_dw : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, rf_wen : UInt<1>, csr_cmd : UInt<3>} wire rrd_cs_decoder_decoded_plaInput : UInt<7> node rrd_cs_decoder_decoded_invInputs = not(rrd_cs_decoder_decoded_plaInput) wire rrd_cs_decoder_decoded : UInt<24> node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo) node rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1) node rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2) node rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3) node rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4) node rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5) node rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6) node rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_6) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7) node rrd_cs_decoder_decoded_andMatrixOutputs_66_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_7) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8) node rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_8) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9) node rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_9) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10) node rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_10) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11) node rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_11) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12) node rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_12) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13) node rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_13) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14) node rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_14) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15) node rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_15) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16) node rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_16) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17) node rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_17) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18) node rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_18) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19) node rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_19) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20) node rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_20) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21) node rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_21) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22) node rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_22) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23) node rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_23) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24) node rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_24) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24) node rrd_cs_decoder_decoded_andMatrixOutputs_71_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_25) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26) node rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_26) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25) node rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_27) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26) node rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_28) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27) node rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_29) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28) node rrd_cs_decoder_decoded_andMatrixOutputs_68_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_30) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29) node rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_31) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30) node rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_32) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31) node rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_33) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32) node rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_34) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33) node rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_35) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34) node rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_36) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35) node rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_37) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36) node rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_38) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37) node rrd_cs_decoder_decoded_andMatrixOutputs_67_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_39) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38) node rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_40) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39) node rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_41) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40) node rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_42) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41) node rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_43) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42) node rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_44) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43) node rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_45) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44) node rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_46) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45) node rrd_cs_decoder_decoded_andMatrixOutputs_70_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_47) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46) node rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_48) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47) node rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_49) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48) node rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_50) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49) node rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_51) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50) node rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_52) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51) node rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_53) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52) node rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_54) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53) node rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_55) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54) node rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_56) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_57) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55) node rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_58) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56) node rrd_cs_decoder_decoded_andMatrixOutputs_69_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_59) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57) node rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_60) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58) node rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_61) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59) node rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60) node rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_63) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61) node rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_64) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62) node rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_65) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_66 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_66 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_66, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63) node rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_66) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_67 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_67 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_67, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64) node rrd_cs_decoder_decoded_andMatrixOutputs_72_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_67) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_68 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_68 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_68, rrd_cs_decoder_decoded_andMatrixOutputs_lo_65) node rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_68) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_66 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_69 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_69 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_69, rrd_cs_decoder_decoded_andMatrixOutputs_lo_66) node rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_69) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_67 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_70 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_70 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_70, rrd_cs_decoder_decoded_andMatrixOutputs_lo_67) node rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_70) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_68 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_71 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_71 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_71, rrd_cs_decoder_decoded_andMatrixOutputs_lo_68) node rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_71) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_69 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_72 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_72 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_72, rrd_cs_decoder_decoded_andMatrixOutputs_lo_69) node rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_72) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_53_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_29_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_45_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_2_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_63_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_22_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_15_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_7) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_9) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_5_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_0_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_69_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_60_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_13) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_69_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_35_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_49_2, rrd_cs_decoder_decoded_andMatrixOutputs_1_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_48_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_66_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_15) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_10_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_26_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_39_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_17) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_43_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_72_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_68_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_37_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_19) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_51_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_57_2, rrd_cs_decoder_decoded_andMatrixOutputs_71_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_21) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_23) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_25) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_70_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_67_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_27) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_70_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_29) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_70_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_31) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_13_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_6) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_12, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_18, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_14) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_22) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_28, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_24) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_32) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_30) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7) node rrd_cs_decoder_decoded_orMatrixOutputs = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 0, 0) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 1, 1) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 2, 2) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 3, 3) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 4, 4) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 5, 5) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 6, 6) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 7, 7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 8, 8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 9, 9) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 10, 10) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 11, 11) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 12, 12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 13, 13) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 14, 14) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 15, 15) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 16, 16) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 17, 17) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 18, 18) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 19, 19) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 20, 20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 21, 21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 22, 22) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 23, 23) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_21) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_25, _rrd_cs_decoder_decoded_invMatrixOutputs_T_24) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo) connect rrd_cs_decoder_decoded, rrd_cs_decoder_decoded_invMatrixOutputs connect rrd_cs_decoder_decoded_plaInput, io.rrd_uop.uopc node rrd_cs_decoder_0 = bits(rrd_cs_decoder_decoded, 23, 20) node rrd_cs_decoder_1 = bits(rrd_cs_decoder_decoded, 19, 19) node rrd_cs_decoder_2 = bits(rrd_cs_decoder_decoded, 18, 18) node rrd_cs_decoder_3 = bits(rrd_cs_decoder_decoded, 17, 17) node rrd_cs_decoder_4 = bits(rrd_cs_decoder_decoded, 16, 13) node rrd_cs_decoder_5 = bits(rrd_cs_decoder_decoded, 12, 12) node rrd_cs_decoder_6 = bits(rrd_cs_decoder_decoded, 11, 10) node rrd_cs_decoder_7 = bits(rrd_cs_decoder_decoded, 9, 7) node rrd_cs_decoder_8 = bits(rrd_cs_decoder_decoded, 6, 4) node rrd_cs_decoder_9 = bits(rrd_cs_decoder_decoded, 3, 3) node rrd_cs_decoder_10 = bits(rrd_cs_decoder_decoded, 2, 0) connect rrd_cs.br_type, rrd_cs_decoder_0 connect rrd_cs.use_alupipe, rrd_cs_decoder_1 connect rrd_cs.use_muldivpipe, rrd_cs_decoder_2 connect rrd_cs.use_mempipe, rrd_cs_decoder_3 connect rrd_cs.op_fcn, rrd_cs_decoder_4 connect rrd_cs.fcn_dw, rrd_cs_decoder_5 connect rrd_cs.op1_sel, rrd_cs_decoder_6 connect rrd_cs.op2_sel, rrd_cs_decoder_7 connect rrd_cs.imm_sel, rrd_cs_decoder_8 connect rrd_cs.rf_wen, rrd_cs_decoder_9 connect rrd_cs.csr_cmd, rrd_cs_decoder_10 connect io.rrd_uop.ctrl.br_type, rrd_cs.br_type connect io.rrd_uop.ctrl.op1_sel, rrd_cs.op1_sel connect io.rrd_uop.ctrl.op2_sel, rrd_cs.op2_sel connect io.rrd_uop.ctrl.imm_sel, rrd_cs.imm_sel connect io.rrd_uop.ctrl.op_fcn, rrd_cs.op_fcn connect io.rrd_uop.ctrl.fcn_dw, rrd_cs.fcn_dw node _io_rrd_uop_ctrl_is_load_T = eq(io.rrd_uop.uopc, UInt<7>(0h1)) connect io.rrd_uop.ctrl.is_load, _io_rrd_uop_ctrl_is_load_T node _io_rrd_uop_ctrl_is_sta_T = eq(io.rrd_uop.uopc, UInt<7>(0h2)) node _io_rrd_uop_ctrl_is_sta_T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _io_rrd_uop_ctrl_is_sta_T_2 = or(_io_rrd_uop_ctrl_is_sta_T, _io_rrd_uop_ctrl_is_sta_T_1) connect io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_sta_T_2 node _io_rrd_uop_ctrl_is_std_T = eq(io.rrd_uop.uopc, UInt<7>(0h3)) node _io_rrd_uop_ctrl_is_std_T_1 = eq(io.rrd_uop.lrs2_rtype, UInt<2>(0h0)) node _io_rrd_uop_ctrl_is_std_T_2 = and(io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_std_T_1) node _io_rrd_uop_ctrl_is_std_T_3 = or(_io_rrd_uop_ctrl_is_std_T, _io_rrd_uop_ctrl_is_std_T_2) connect io.rrd_uop.ctrl.is_std, _io_rrd_uop_ctrl_is_std_T_3 node _T = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h1)) node _T_2 = eq(io.rrd_uop.mem_cmd, UInt<3>(0h6)) node _T_3 = and(_T_1, _T_2) node _T_4 = or(_T, _T_3) when _T_4 : connect io.rrd_uop.imm_packed, UInt<1>(0h0) node _csr_ren_T = eq(rrd_cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(io.rrd_uop.prs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node _io_rrd_uop_ctrl_csr_cmd_T = mux(csr_ren, UInt<3>(0h2), rrd_cs.csr_cmd) connect io.rrd_uop.ctrl.csr_cmd, _io_rrd_uop_ctrl_csr_cmd_T connect io.rrd_valid, io.iss_valid	module RegisterReadDecode_2( // @[func-unit-decode.scala:307:7] input clock, // @[func-unit-decode.scala:307:7] input reset, // @[func-unit-decode.scala:307:7] input io_iss_valid, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_uopc, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_inst, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_debug_inst, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_rvc, // @[func-unit-decode.scala:310:14] input [39:0] io_iss_uop_debug_pc, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_iq_type, // @[func-unit-decode.scala:310:14] input [9:0] io_iss_uop_fu_code, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_iw_state, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_br, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jalr, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jal, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sfb, // @[func-unit-decode.scala:310:14] input [15:0] io_iss_uop_br_mask, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_br_tag, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ftq_idx, // @[func-unit-decode.scala:310:14] input io_iss_uop_edge_inst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pc_lob, // @[func-unit-decode.scala:310:14] input io_iss_uop_taken, // @[func-unit-decode.scala:310:14] input [19:0] io_iss_uop_imm_packed, // @[func-unit-decode.scala:310:14] input [11:0] io_iss_uop_csr_addr, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_rob_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ldq_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_stq_idx, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_rxq_idx, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_pdst, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs1, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs2, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs3, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ppred, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs1_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs2_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs3_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_ppred_busy, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_stale_pdst, // @[func-unit-decode.scala:310:14] input io_iss_uop_exception, // @[func-unit-decode.scala:310:14] input [63:0] io_iss_uop_exc_cause, // @[func-unit-decode.scala:310:14] input io_iss_uop_bypassable, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_mem_cmd, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_mem_size, // @[func-unit-decode.scala:310:14] input io_iss_uop_mem_signed, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fence, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fencei, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_amo, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_ldq, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_stq, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_unique, // @[func-unit-decode.scala:310:14] input io_iss_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_ldst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs3, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_val, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_dst_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] input io_iss_uop_frs3_en, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_val, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_single, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_tsrc, // @[func-unit-decode.scala:310:14] output io_rrd_valid, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_uopc, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_inst, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_debug_inst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_rvc, // @[func-unit-decode.scala:310:14] output [39:0] io_rrd_uop_debug_pc, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_iq_type, // @[func-unit-decode.scala:310:14] output [9:0] io_rrd_uop_fu_code, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_iw_state, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_br, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jalr, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jal, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sfb, // @[func-unit-decode.scala:310:14] output [15:0] io_rrd_uop_br_mask, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_br_tag, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ftq_idx, // @[func-unit-decode.scala:310:14] output io_rrd_uop_edge_inst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pc_lob, // @[func-unit-decode.scala:310:14] output io_rrd_uop_taken, // @[func-unit-decode.scala:310:14] output [19:0] io_rrd_uop_imm_packed, // @[func-unit-decode.scala:310:14] output [11:0] io_rrd_uop_csr_addr, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_rob_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ldq_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_stq_idx, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_rxq_idx, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_pdst, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs1, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs2, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs3, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ppred, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs1_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs2_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs3_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ppred_busy, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_stale_pdst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_exception, // @[func-unit-decode.scala:310:14] output [63:0] io_rrd_uop_exc_cause, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bypassable, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_mem_cmd, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_mem_size, // @[func-unit-decode.scala:310:14] output io_rrd_uop_mem_signed, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fence, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fencei, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_amo, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_ldq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_stq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_unique, // @[func-unit-decode.scala:310:14] output io_rrd_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_ldst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs3, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_val, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_dst_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] output io_rrd_uop_frs3_en, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_val, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_single, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_tsrc // @[func-unit-decode.scala:310:14] ); wire io_iss_valid_0 = io_iss_valid; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_uopc_0 = io_iss_uop_uopc; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_inst_0 = io_iss_uop_inst; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_debug_inst_0 = io_iss_uop_debug_inst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_rvc_0 = io_iss_uop_is_rvc; // @[func-unit-decode.scala:307:7] wire [39:0] io_iss_uop_debug_pc_0 = io_iss_uop_debug_pc; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_iq_type_0 = io_iss_uop_iq_type; // @[func-unit-decode.scala:307:7] wire [9:0] io_iss_uop_fu_code_0 = io_iss_uop_fu_code; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ctrl_br_type_0 = io_iss_uop_ctrl_br_type; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_ctrl_op1_sel_0 = io_iss_uop_ctrl_op1_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_op2_sel_0 = io_iss_uop_ctrl_op2_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_imm_sel_0 = io_iss_uop_ctrl_imm_sel; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ctrl_op_fcn_0 = io_iss_uop_ctrl_op_fcn; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_fcn_dw_0 = io_iss_uop_ctrl_fcn_dw; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_csr_cmd_0 = io_iss_uop_ctrl_csr_cmd; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_load_0 = io_iss_uop_ctrl_is_load; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_sta_0 = io_iss_uop_ctrl_is_sta; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_std_0 = io_iss_uop_ctrl_is_std; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_iw_state_0 = io_iss_uop_iw_state; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_br_0 = io_iss_uop_is_br; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jalr_0 = io_iss_uop_is_jalr; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jal_0 = io_iss_uop_is_jal; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sfb_0 = io_iss_uop_is_sfb; // @[func-unit-decode.scala:307:7] wire [15:0] io_iss_uop_br_mask_0 = io_iss_uop_br_mask; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_br_tag_0 = io_iss_uop_br_tag; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ftq_idx_0 = io_iss_uop_ftq_idx; // @[func-unit-decode.scala:307:7] wire io_iss_uop_edge_inst_0 = io_iss_uop_edge_inst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pc_lob_0 = io_iss_uop_pc_lob; // @[func-unit-decode.scala:307:7] wire io_iss_uop_taken_0 = io_iss_uop_taken; // @[func-unit-decode.scala:307:7] wire [19:0] io_iss_uop_imm_packed_0 = io_iss_uop_imm_packed; // @[func-unit-decode.scala:307:7] wire [11:0] io_iss_uop_csr_addr_0 = io_iss_uop_csr_addr; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_rob_idx_0 = io_iss_uop_rob_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ldq_idx_0 = io_iss_uop_ldq_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_stq_idx_0 = io_iss_uop_stq_idx; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_rxq_idx_0 = io_iss_uop_rxq_idx; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_pdst_0 = io_iss_uop_pdst; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs1_0 = io_iss_uop_prs1; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs2; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs3_0 = io_iss_uop_prs3; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ppred_0 = io_iss_uop_ppred; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs1_busy_0 = io_iss_uop_prs1_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs2_busy_0 = io_iss_uop_prs2_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs3_busy_0 = io_iss_uop_prs3_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ppred_busy_0 = io_iss_uop_ppred_busy; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_stale_pdst_0 = io_iss_uop_stale_pdst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_exception_0 = io_iss_uop_exception; // @[func-unit-decode.scala:307:7] wire [63:0] io_iss_uop_exc_cause_0 = io_iss_uop_exc_cause; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bypassable_0 = io_iss_uop_bypassable; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_mem_cmd_0 = io_iss_uop_mem_cmd; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_mem_size_0 = io_iss_uop_mem_size; // @[func-unit-decode.scala:307:7] wire io_iss_uop_mem_signed_0 = io_iss_uop_mem_signed; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fence_0 = io_iss_uop_is_fence; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fencei_0 = io_iss_uop_is_fencei; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_amo_0 = io_iss_uop_is_amo; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_ldq_0 = io_iss_uop_uses_ldq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_stq_0 = io_iss_uop_uses_stq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_unique_0 = io_iss_uop_is_unique; // @[func-unit-decode.scala:307:7] wire io_iss_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_ldst_0 = io_iss_uop_ldst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs1_0 = io_iss_uop_lrs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs2_0 = io_iss_uop_lrs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs3_0 = io_iss_uop_lrs3; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_val_0 = io_iss_uop_ldst_val; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_dst_rtype_0 = io_iss_uop_dst_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype; // @[func-unit-decode.scala:307:7] wire io_iss_uop_frs3_en_0 = io_iss_uop_frs3_en; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_val_0 = io_iss_uop_fp_val; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_single_0 = io_iss_uop_fp_single; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc; // @[func-unit-decode.scala:307:7] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = 2'h0; // @[pla.scala:102:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = 3'h0; // @[pla.scala:102:36] wire io_iss_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_iss_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_valid_0 = io_iss_valid_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_uopc_0 = io_iss_uop_uopc_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_inst_0 = io_iss_uop_inst_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_debug_inst_0 = io_iss_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_rvc_0 = io_iss_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] wire [39:0] io_rrd_uop_debug_pc_0 = io_iss_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_iq_type_0 = io_iss_uop_iq_type_0; // @[func-unit-decode.scala:307:7] wire [9:0] io_rrd_uop_fu_code_0 = io_iss_uop_fu_code_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_iw_state_0 = io_iss_uop_iw_state_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_br_0 = io_iss_uop_is_br_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jalr_0 = io_iss_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jal_0 = io_iss_uop_is_jal_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sfb_0 = io_iss_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] wire [15:0] io_rrd_uop_br_mask_0 = io_iss_uop_br_mask_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_br_tag_0 = io_iss_uop_br_tag_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ftq_idx_0 = io_iss_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_edge_inst_0 = io_iss_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pc_lob_0 = io_iss_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_taken_0 = io_iss_uop_taken_0; // @[func-unit-decode.scala:307:7] wire [11:0] io_rrd_uop_csr_addr_0 = io_iss_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_rob_idx_0 = io_iss_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ldq_idx_0 = io_iss_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_stq_idx_0 = io_iss_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_rxq_idx_0 = io_iss_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_pdst_0 = io_iss_uop_pdst_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs1_0 = io_iss_uop_prs1_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs2_0 = io_iss_uop_prs2_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs3_0 = io_iss_uop_prs3_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ppred_0 = io_iss_uop_ppred_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs1_busy_0 = io_iss_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs2_busy_0 = io_iss_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs3_busy_0 = io_iss_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ppred_busy_0 = io_iss_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_stale_pdst_0 = io_iss_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_exception_0 = io_iss_uop_exception_0; // @[func-unit-decode.scala:307:7] wire [63:0] io_rrd_uop_exc_cause_0 = io_iss_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bypassable_0 = io_iss_uop_bypassable_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_mem_cmd_0 = io_iss_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_mem_size_0 = io_iss_uop_mem_size_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_mem_signed_0 = io_iss_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fence_0 = io_iss_uop_is_fence_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fencei_0 = io_iss_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_amo_0 = io_iss_uop_is_amo_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_ldq_0 = io_iss_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_stq_0 = io_iss_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_unique_0 = io_iss_uop_is_unique_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_ldst_0 = io_iss_uop_ldst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs1_0 = io_iss_uop_lrs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs2_0 = io_iss_uop_lrs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs3_0 = io_iss_uop_lrs3_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_val_0 = io_iss_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_dst_rtype_0 = io_iss_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_frs3_en_0 = io_iss_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_val_0 = io_iss_uop_fp_val_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_single_0 = io_iss_uop_fp_single_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] wire [6:0] rrd_cs_decoder_decoded_plaInput = io_rrd_uop_uopc_0; // @[pla.scala:77:22] wire [3:0] rrd_cs_br_type; // @[func-unit-decode.scala:330:20] wire [1:0] rrd_cs_op1_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_op2_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_imm_sel; // @[func-unit-decode.scala:330:20] wire [4:0] rrd_cs_op_fcn; // @[func-unit-decode.scala:330:20] wire rrd_cs_fcn_dw; // @[func-unit-decode.scala:330:20] wire [2:0] _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:349:33] wire _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:339:46] wire _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:340:57] wire _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:341:57] wire [3:0] io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] wire [19:0] io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] wire [3:0] rrd_cs_decoder_0; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_br_type_0 = rrd_cs_br_type; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_1; // @[Decode.scala:50:77] wire rrd_cs_decoder_2; // @[Decode.scala:50:77] wire rrd_cs_decoder_3; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op_fcn_0 = rrd_cs_op_fcn; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_5; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_fcn_dw_0 = rrd_cs_fcn_dw; // @[func-unit-decode.scala:307:7, :330:20] wire [1:0] rrd_cs_decoder_6; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op1_sel_0 = rrd_cs_op1_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_7; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op2_sel_0 = rrd_cs_op2_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_8; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_imm_sel_0 = rrd_cs_imm_sel; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_9; // @[Decode.scala:50:77] wire [2:0] rrd_cs_decoder_10; // @[Decode.scala:50:77] wire rrd_cs_use_alupipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_muldivpipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_mempipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_rf_wen; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20] wire [6:0] rrd_cs_decoder_decoded_invInputs = ~rrd_cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [23:0] rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [23:0] rrd_cs_decoder_decoded; // @[pla.scala:81:23] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T = {rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = rrd_cs_decoder_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_66_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_71_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_68_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_67_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = rrd_cs_decoder_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = rrd_cs_decoder_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_70_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = rrd_cs_decoder_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_69_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_66 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_66 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_66, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_67 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_67 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_67, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_72_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_68 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_68 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_68, rrd_cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_66 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_69 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_69 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_69, rrd_cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_67 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_70 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_70 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_70, rrd_cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_68 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_71 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_71 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_71, rrd_cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_69 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_72 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_72 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_72, rrd_cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_53_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_29_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_45_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [8:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T = {rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_15_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_7; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_69_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_49_2, rrd_cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_66_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [10:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_43_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_72_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_51_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_57_2, rrd_cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [7:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_8; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = _GEN; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_9; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = _GEN; // @[pla.scala:114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_67_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, 3'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_12, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, 1'h0}; // @[pla.scala:102:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_18, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_14}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_28, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:102:36] wire [23:0] rrd_cs_decoder_decoded_orMatrixOutputs = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:102:36] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T = rrd_cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = rrd_cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = rrd_cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = rrd_cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = rrd_cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = rrd_cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = rrd_cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = rrd_cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = rrd_cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = rrd_cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = rrd_cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = rrd_cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = rrd_cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_12; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = rrd_cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = rrd_cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = rrd_cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = rrd_cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = rrd_cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = rrd_cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = rrd_cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_20; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = rrd_cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = rrd_cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = rrd_cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = rrd_cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :123:40] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_25, _rrd_cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded_invMatrixOutputs = {rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded = rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign rrd_cs_decoder_0 = rrd_cs_decoder_decoded[23:20]; // @[pla.scala:81:23] assign rrd_cs_br_type = rrd_cs_decoder_0; // @[Decode.scala:50:77] assign rrd_cs_decoder_1 = rrd_cs_decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_cs_use_alupipe = rrd_cs_decoder_1; // @[Decode.scala:50:77] assign rrd_cs_decoder_2 = rrd_cs_decoder_decoded[18]; // @[pla.scala:81:23] assign rrd_cs_use_muldivpipe = rrd_cs_decoder_2; // @[Decode.scala:50:77] assign rrd_cs_decoder_3 = rrd_cs_decoder_decoded[17]; // @[pla.scala:81:23] assign rrd_cs_use_mempipe = rrd_cs_decoder_3; // @[Decode.scala:50:77] wire [3:0] rrd_cs_decoder_4 = rrd_cs_decoder_decoded[16:13]; // @[pla.scala:81:23] assign rrd_cs_decoder_5 = rrd_cs_decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_cs_fcn_dw = rrd_cs_decoder_5; // @[Decode.scala:50:77] assign rrd_cs_decoder_6 = rrd_cs_decoder_decoded[11:10]; // @[pla.scala:81:23] assign rrd_cs_op1_sel = rrd_cs_decoder_6; // @[Decode.scala:50:77] assign rrd_cs_decoder_7 = rrd_cs_decoder_decoded[9:7]; // @[pla.scala:81:23] assign rrd_cs_op2_sel = rrd_cs_decoder_7; // @[Decode.scala:50:77] assign rrd_cs_decoder_8 = rrd_cs_decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_cs_imm_sel = rrd_cs_decoder_8; // @[Decode.scala:50:77] assign rrd_cs_decoder_9 = rrd_cs_decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_cs_rf_wen = rrd_cs_decoder_9; // @[Decode.scala:50:77] assign rrd_cs_decoder_10 = rrd_cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign rrd_cs_csr_cmd = rrd_cs_decoder_10; // @[Decode.scala:50:77] assign rrd_cs_op_fcn = {1'h0, rrd_cs_decoder_4}; // @[Decode.scala:50:77] assign _io_rrd_uop_ctrl_is_load_T = io_rrd_uop_uopc_0 == 7'h1; // @[func-unit-decode.scala:307:7, :339:46] assign io_rrd_uop_ctrl_is_load_0 = _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:307:7, :339:46] wire _io_rrd_uop_ctrl_is_sta_T = io_rrd_uop_uopc_0 == 7'h2; // @[func-unit-decode.scala:307:7, :340:46] wire _io_rrd_uop_ctrl_is_sta_T_1 = io_rrd_uop_uopc_0 == 7'h43; // @[func-unit-decode.scala:307:7, :340:76] assign _io_rrd_uop_ctrl_is_sta_T_2 = _io_rrd_uop_ctrl_is_sta_T \| _io_rrd_uop_ctrl_is_sta_T_1; // @[func-unit-decode.scala:340:{46,57,76}] assign io_rrd_uop_ctrl_is_sta_0 = _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:307:7, :340:57] wire _io_rrd_uop_ctrl_is_std_T = io_rrd_uop_uopc_0 == 7'h3; // @[func-unit-decode.scala:307:7, :341:46] wire _io_rrd_uop_ctrl_is_std_T_1 = io_rrd_uop_lrs2_rtype_0 == 2'h0; // @[func-unit-decode.scala:307:7, :341:109] wire _io_rrd_uop_ctrl_is_std_T_2 = io_rrd_uop_ctrl_is_sta_0 & _io_rrd_uop_ctrl_is_std_T_1; // @[func-unit-decode.scala:307:7, :341:{84,109}] assign _io_rrd_uop_ctrl_is_std_T_3 = _io_rrd_uop_ctrl_is_std_T \| _io_rrd_uop_ctrl_is_std_T_2; // @[func-unit-decode.scala:341:{46,57,84}] assign io_rrd_uop_ctrl_is_std_0 = _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:307:7, :341:57] assign io_rrd_uop_imm_packed_0 = _io_rrd_uop_ctrl_is_sta_T_1 \| _io_rrd_uop_ctrl_is_load_T & io_rrd_uop_mem_cmd_0 == 5'h6 ? 20'h0 : io_iss_uop_imm_packed_0; // @[func-unit-decode.scala:307:7, :320:16, :339:46, :340:76, :343:{39,69,91,103}, :344:27] wire _csr_ren_T = rrd_cs_csr_cmd == 3'h6; // @[func-unit-decode.scala:330:20, :348:33] wire _csr_ren_T_1 = &rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:61] wire _csr_ren_T_2 = _csr_ren_T \| _csr_ren_T_1; // @[func-unit-decode.scala:348:{33,43,61}] wire _csr_ren_T_3 = io_rrd_uop_prs1_0 == 7'h0; // @[pla.scala:114:36] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[func-unit-decode.scala:348:{43,72,82}] assign _io_rrd_uop_ctrl_csr_cmd_T = csr_ren ? 3'h2 : rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:72, :349:33] assign io_rrd_uop_ctrl_csr_cmd_0 = _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:307:7, :349:33] assign io_rrd_valid = io_rrd_valid_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uopc = io_rrd_uop_uopc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_inst = io_rrd_uop_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_inst = io_rrd_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_rvc = io_rrd_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_pc = io_rrd_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iq_type = io_rrd_uop_iq_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fu_code = io_rrd_uop_fu_code_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_br_type = io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op1_sel = io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op2_sel = io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_imm_sel = io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op_fcn = io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_fcn_dw = io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_csr_cmd = io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_std = io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iw_state = io_rrd_uop_iw_state_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_br = io_rrd_uop_is_br_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jalr = io_rrd_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jal = io_rrd_uop_is_jal_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sfb = io_rrd_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_mask = io_rrd_uop_br_mask_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_tag = io_rrd_uop_br_tag_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ftq_idx = io_rrd_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_edge_inst = io_rrd_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pc_lob = io_rrd_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_taken = io_rrd_uop_taken_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_imm_packed = io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_csr_addr = io_rrd_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rob_idx = io_rrd_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldq_idx = io_rrd_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stq_idx = io_rrd_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rxq_idx = io_rrd_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pdst = io_rrd_uop_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1 = io_rrd_uop_prs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2 = io_rrd_uop_prs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3 = io_rrd_uop_prs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred = io_rrd_uop_ppred_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1_busy = io_rrd_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2_busy = io_rrd_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3_busy = io_rrd_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred_busy = io_rrd_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stale_pdst = io_rrd_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exception = io_rrd_uop_exception_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exc_cause = io_rrd_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bypassable = io_rrd_uop_bypassable_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_cmd = io_rrd_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_size = io_rrd_uop_mem_size_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_signed = io_rrd_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fence = io_rrd_uop_is_fence_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fencei = io_rrd_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_amo = io_rrd_uop_is_amo_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_ldq = io_rrd_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_stq = io_rrd_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sys_pc2epc = io_rrd_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_unique = io_rrd_uop_is_unique_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_flush_on_commit = io_rrd_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_is_rs1 = io_rrd_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst = io_rrd_uop_ldst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1 = io_rrd_uop_lrs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2 = io_rrd_uop_lrs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs3 = io_rrd_uop_lrs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_val = io_rrd_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_dst_rtype = io_rrd_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1_rtype = io_rrd_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2_rtype = io_rrd_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_frs3_en = io_rrd_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_val = io_rrd_uop_fp_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_single = io_rrd_uop_fp_single_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_pf_if = io_rrd_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ae_if = io_rrd_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ma_if = io_rrd_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_debug_if = io_rrd_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_xcpt_if = io_rrd_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_fsrc = io_rrd_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_tsrc = io_rrd_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_8 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_8 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_8 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_8 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d	module TLMasterACDToNoC_8( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [72:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_8 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_8 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_6 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<12>(0h780))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 11, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 64, 10) node _adjustedSig_T_1 = bits(io.in.sig, 9, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<12> wire common_fractOut : UInt<52> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<53>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 53) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 11, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 52, 1) node _common_fractOut_T_1 = bits(roundedSig, 51, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 54, 54) node _roundCarry_T_1 = bits(roundedSig, 53, 53) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<12>(0h3ce)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_6( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [53:0] _roundMask_T = 54'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [55:0] roundMask = 56'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [56:0] _shiftedRoundMask_T = 57'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [55:0] shiftedRoundMask = 56'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [55:0] _roundPosMask_T = 56'hFFFFFFFFFFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [55:0] roundPosMask = 56'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [55:0] _roundedSig_T_10 = 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [54:0] _roundedSig_T_6 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [54:0] _roundedSig_T_14 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [11:0] _expOut_T_6 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_9 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_12 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_5 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [11:0] _expOut_T_8 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [11:0] _expOut_T_11 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [11:0] _expOut_T_14 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [11:0] _expOut_T_16 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [11:0] _expOut_T_18 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [11:0] _expOut_T_20 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [51:0] _fractOut_T_2 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [51:0] _fractOut_T_4 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [12:0] _sAdjustedExp_T = {{4{io_in_sExp_0[8]}}, io_in_sExp_0} + 13'h780; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [11:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[11:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [12:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [54:0] _adjustedSig_T = io_in_sig_0[64:10]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [9:0] _adjustedSig_T_1 = io_in_sig_0[9:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = \|_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [55:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [55:0] _roundPosBit_T = adjustedSig & 56'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & 56'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig \| 56'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_7 = {54'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_11 = adjustedSig & 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_15 = {54'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {sAdjustedExp[12], sAdjustedExp} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [11:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [11:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [11:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [11:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [11:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [11:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? 52'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [51:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_273 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_273( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLEToNoC : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<5>, egress_id : UInt}}} inst q of Queue1_TLBundleE_a32d64s6k5z4c connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(UInt<1>(0h0), _head_count_T) when _head_T : node _head_counter_T = mux(head, UInt<1>(0h0), head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(UInt<1>(0h0), _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, UInt<1>(0h0), tail_counter1) connect tail_counter, _tail_counter_T regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 2, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<2>(0h3)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 2, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<2>(0h2)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 2, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<1>(0h1)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 2, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_T = mux(UInt<1>(0h0), UInt<4>(0hc), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hf), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h15), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h18), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, UInt<1>(0h0), q.io.deq.bits.sink) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) connect has_body, UInt<1>(0h0) connect q.io.enq, io.protocol	module TLEToNoC( // @[TilelinkAdapters.scala:191:7] input clock, // @[TilelinkAdapters.scala:191:7] input reset, // @[TilelinkAdapters.scala:191:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] reg is_body; // @[TilelinkAdapters.scala:39:24] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:191:7] if (reset) begin // @[TilelinkAdapters.scala:191:7] head_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :191:7] end else begin // @[TilelinkAdapters.scala:191:7] if (io_flit_ready & _q_io_deq_valid) // @[Decoupled.scala:51:35] head_counter <= head ? 9'h0 : head_counter - 9'h1; // @[Edges.scala:229:27, :230:28, :231:25, :236:21] is_body <= ~_GEN & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_23 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_23 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_23 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_10 : connect states[0].g, UInt<3>(0h2) connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_18 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_19 = and(io.router_req.ready, io.router_req.valid) when _T_19 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_21 = or(_T_20, vcalloc_vals[2]) when _T_21 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16 wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<4> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_21 : UInt<4> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].flow, states[0].flow node _T_22 = bits(vcalloc_sel, 0, 0) node _T_23 = and(vcalloc_vals[0], _T_22) node _T_24 = and(_T_23, io.vcalloc_req.ready) when _T_24 : connect states[0].g, UInt<3>(0h3) node _T_25 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_25 : connect vcalloc_vals[0], UInt<1>(0h1) connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`3`[0] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`3`[0] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_26 : node _T_27 = bits(vcalloc_sel, 0, 0) when _T_27 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_28 = bits(vcalloc_sel, 1, 1) when _T_28 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_29 = bits(vcalloc_sel, 2, 2) when _T_29 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_56 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[0].vc_sel.`2`[2], states[0].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[0].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_3 = cat(states[0].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo) node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0]) node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_30 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_31 = and(_T_30, input_buffer.io.deq[0].bits.tail) when _T_31 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[1] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 connect vc_sel.`3`, _vc_sel_WIRE_12 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16) node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17) node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_21 node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_32 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[0], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`3`[0] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`3`[0] invalidate states[2].g node _T_33 = asUInt(reset) when _T_33 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)	module InputUnit_23( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e11_s53_3 : output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 63, 63) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_3 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i64_e11_s53_3( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [64:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7] wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [64:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53] wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70] wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_3 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_181 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_181( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n0x0_4 : output auto : { } wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset	module IntSyncSyncCrossingSink_n0x0_4(); // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_119 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_136 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_119( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_136 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Queue1_RegMapperInput_i9_m8 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}, count : UInt<1>} cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}} [1] wire enq_ptr_value : UInt connect enq_ptr_value, UInt<1>(0h0) wire deq_ptr_value : UInt connect deq_ptr_value, UInt<1>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _empty_T = eq(maybe_full, UInt<1>(0h0)) node empty = and(ptr_match, _empty_T) node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> connect do_deq, _do_deq_T when do_enq : wire _WIRE : UInt connect _WIRE, UInt<1>(0h0) infer mport MPORT = ram[_WIRE], clock connect MPORT.extra, io.enq.bits.extra connect MPORT.mask, io.enq.bits.mask connect MPORT.data, io.enq.bits.data connect MPORT.index, io.enq.bits.index connect MPORT.read, io.enq.bits.read when do_deq : skip node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq when UInt<1>(0h0) : connect enq_ptr_value, UInt<1>(0h0) connect deq_ptr_value, UInt<1>(0h0) connect maybe_full, UInt<1>(0h0) node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire _io_deq_bits_WIRE : UInt connect _io_deq_bits_WIRE, UInt<1>(0h0) infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock connect io.deq.bits, io_deq_bits_MPORT node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) node _io_count_T_2 = or(_io_count_T_1, ptr_diff) connect io.count, _io_count_T_2	module Queue1_RegMapperInput_i9_m8( // @[RegMapper.scala:71:32] input clock, // @[RegMapper.scala:71:32] input reset, // @[RegMapper.scala:71:32] output io_enq_ready, // @[Decoupled.scala:255:14] input io_enq_valid, // @[Decoupled.scala:255:14] input io_enq_bits_read, // @[Decoupled.scala:255:14] input [8:0] io_enq_bits_index, // @[Decoupled.scala:255:14] input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14] input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14] input [11:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14] input [1:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14] input io_deq_ready, // @[Decoupled.scala:255:14] output io_deq_valid, // @[Decoupled.scala:255:14] output io_deq_bits_read, // @[Decoupled.scala:255:14] output [8:0] io_deq_bits_index, // @[Decoupled.scala:255:14] output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14] output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14] output [11:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14] output [1:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14] ); wire io_enq_valid_0 = io_enq_valid; // @[RegMapper.scala:71:32] wire io_enq_bits_read_0 = io_enq_bits_read; // @[RegMapper.scala:71:32] wire [8:0] io_enq_bits_index_0 = io_enq_bits_index; // @[RegMapper.scala:71:32] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[RegMapper.scala:71:32] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[RegMapper.scala:71:32] wire [11:0] io_enq_bits_extra_tlrr_extra_source_0 = io_enq_bits_extra_tlrr_extra_source; // @[RegMapper.scala:71:32] wire [1:0] io_enq_bits_extra_tlrr_extra_size_0 = io_enq_bits_extra_tlrr_extra_size; // @[RegMapper.scala:71:32] wire io_deq_ready_0 = io_deq_ready; // @[RegMapper.scala:71:32] wire ptr_match = 1'h1; // @[Decoupled.scala:260:33] wire [1:0] _ptr_diff_T = 2'h0; // @[Decoupled.scala:309:32] wire enq_ptr_value = 1'h0; // @[Counter.scala:61:73] wire deq_ptr_value = 1'h0; // @[Counter.scala:61:73] wire _io_enq_ready_T; // @[Decoupled.scala:286:19] wire _io_deq_bits_WIRE = 1'h0; // @[Decoupled.scala:293:23] wire ptr_diff = 1'h0; // @[Decoupled.scala:309:32] wire _io_deq_valid_T; // @[Decoupled.scala:285:19] wire _io_count_T_2; // @[Decoupled.scala:312:62] wire io_enq_ready_0; // @[RegMapper.scala:71:32] wire [11:0] io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32] wire [1:0] io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32] wire io_deq_bits_read_0; // @[RegMapper.scala:71:32] wire [8:0] io_deq_bits_index_0; // @[RegMapper.scala:71:32] wire [63:0] io_deq_bits_data_0; // @[RegMapper.scala:71:32] wire [7:0] io_deq_bits_mask_0; // @[RegMapper.scala:71:32] wire io_deq_valid_0; // @[RegMapper.scala:71:32] wire io_count; // @[RegMapper.scala:71:32] reg [95:0] ram; // @[Decoupled.scala:256:91] assign io_deq_bits_read_0 = ram[0]; // @[Decoupled.scala:256:91] assign io_deq_bits_index_0 = ram[9:1]; // @[Decoupled.scala:256:91] assign io_deq_bits_data_0 = ram[73:10]; // @[Decoupled.scala:256:91] assign io_deq_bits_mask_0 = ram[81:74]; // @[Decoupled.scala:256:91] assign io_deq_bits_extra_tlrr_extra_source_0 = ram[93:82]; // @[Decoupled.scala:256:91] assign io_deq_bits_extra_tlrr_extra_size_0 = ram[95:94]; // @[Decoupled.scala:256:91] reg maybe_full; // @[Decoupled.scala:259:27] wire full = maybe_full; // @[Decoupled.scala:259:27, :262:24] wire _io_count_T = maybe_full; // @[Decoupled.scala:259:27, :312:32] wire _empty_T = ~maybe_full; // @[Decoupled.scala:259:27, :261:28] wire empty = _empty_T; // @[Decoupled.scala:261:{25,28}] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35, :263:27] wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire do_deq = _do_deq_T; // @[Decoupled.scala:51:35, :264:27] assign _io_deq_valid_T = ~empty; // @[Decoupled.scala:261:25, :285:19] assign io_deq_valid_0 = _io_deq_valid_T; // @[Decoupled.scala:285:19] assign _io_enq_ready_T = ~full; // @[Decoupled.scala:262:24, :286:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[Decoupled.scala:286:19] wire _io_count_T_1 = _io_count_T; // @[Decoupled.scala:312:{20,32}] assign _io_count_T_2 = _io_count_T_1; // @[Decoupled.scala:312:{20,62}] assign io_count = _io_count_T_2; // @[Decoupled.scala:312:62] always @(posedge clock) begin // @[RegMapper.scala:71:32] if (do_enq) // @[Decoupled.scala:263:27] ram <= {io_enq_bits_extra_tlrr_extra_size_0, io_enq_bits_extra_tlrr_extra_source_0, io_enq_bits_mask_0, io_enq_bits_data_0, io_enq_bits_index_0, io_enq_bits_read_0}; // @[Decoupled.scala:256:91] if (reset) // @[RegMapper.scala:71:32] maybe_full <= 1'h0; // @[Decoupled.scala:259:27] else if (~(do_enq == do_deq)) // @[Decoupled.scala:259:27, :263:27, :264:27, :276:{15,27}, :277:16] maybe_full <= do_enq; // @[Decoupled.scala:259:27, :263:27] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[RegMapper.scala:71:32] assign io_deq_valid = io_deq_valid_0; // @[RegMapper.scala:71:32] assign io_deq_bits_read = io_deq_bits_read_0; // @[RegMapper.scala:71:32] assign io_deq_bits_index = io_deq_bits_index_0; // @[RegMapper.scala:71:32] assign io_deq_bits_data = io_deq_bits_data_0; // @[RegMapper.scala:71:32] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[RegMapper.scala:71:32] assign io_deq_bits_extra_tlrr_extra_source = io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32] assign io_deq_bits_extra_tlrr_extra_size = io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<13>(0h1000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = and(_T_150, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = and(_T_149, _T_163) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_164, UInt<1>(0h1), "") : assert_2 node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_8) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<1>(0h1)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_9) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h2)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_10) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_187 = shr(io.in.a.bits.source, 2) node _T_188 = eq(_T_187, UInt<2>(0h3)) node _T_189 = leq(UInt<1>(0h0), uncommonBits_11) node _T_190 = and(_T_188, _T_189) node _T_191 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_194 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_195 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_196 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_168 connect _WIRE[1], _T_174 connect _WIRE[2], _T_180 connect _WIRE[3], _T_186 connect _WIRE[4], _T_192 connect _WIRE[5], _T_193 connect _WIRE[6], _T_194 connect _WIRE[7], _T_195 connect _WIRE[8], _T_196 node _T_197 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_198 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_202 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[5], _T_197, UInt<1>(0h0)) node _T_204 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = or(_T_198, _T_199) node _T_208 = or(_T_207, _T_200) node _T_209 = or(_T_208, _T_201) node _T_210 = or(_T_209, _T_202) node _T_211 = or(_T_210, _T_203) node _T_212 = or(_T_211, _T_204) node _T_213 = or(_T_212, _T_205) node _T_214 = or(_T_213, _T_206) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_214 node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<13>(0h1000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = or(_T_223, _T_228) node _T_230 = and(_T_218, _T_229) node _T_231 = or(UInt<1>(0h0), _T_230) node _T_232 = and(_WIRE_1, _T_231) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_232, UInt<1>(0h1), "") : assert_3 node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(source_ok, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_239 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_239, UInt<1>(0h1), "") : assert_5 node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(is_aligned, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_246 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_246, UInt<1>(0h1), "") : assert_7 node _T_250 = not(io.in.a.bits.mask) node _T_251 = eq(_T_250, UInt<1>(0h0)) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_251, UInt<1>(0h1), "") : assert_8 node _T_255 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_255, UInt<1>(0h1), "") : assert_9 node _T_259 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_259 : node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_12) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<1>(0h1)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_13) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_276 = shr(io.in.a.bits.source, 2) node _T_277 = eq(_T_276, UInt<2>(0h2)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_14) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_281 = and(_T_279, _T_280) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_282 = shr(io.in.a.bits.source, 2) node _T_283 = eq(_T_282, UInt<2>(0h3)) node _T_284 = leq(UInt<1>(0h0), uncommonBits_15) node _T_285 = and(_T_283, _T_284) node _T_286 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_287 = and(_T_285, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_289 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_290 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_291 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_292 = or(_T_263, _T_269) node _T_293 = or(_T_292, _T_275) node _T_294 = or(_T_293, _T_281) node _T_295 = or(_T_294, _T_287) node _T_296 = or(_T_295, _T_288) node _T_297 = or(_T_296, _T_289) node _T_298 = or(_T_297, _T_290) node _T_299 = or(_T_298, _T_291) node _T_300 = and(_T_262, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_307, _T_312) node _T_314 = and(_T_302, _T_313) node _T_315 = or(UInt<1>(0h0), _T_314) node _T_316 = and(_T_301, _T_315) node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(_T_316, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_316, UInt<1>(0h1), "") : assert_10 node _T_320 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_16) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_327 = shr(io.in.a.bits.source, 2) node _T_328 = eq(_T_327, UInt<1>(0h1)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_17) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_333 = shr(io.in.a.bits.source, 2) node _T_334 = eq(_T_333, UInt<2>(0h2)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_18) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_338 = and(_T_336, _T_337) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<2>(0h3)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_19) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_320 connect _WIRE_2[1], _T_326 connect _WIRE_2[2], _T_332 connect _WIRE_2[3], _T_338 connect _WIRE_2[4], _T_344 connect _WIRE_2[5], _T_345 connect _WIRE_2[6], _T_346 connect _WIRE_2[7], _T_347 connect _WIRE_2[8], _T_348 node _T_349 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_350 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE_2[5], _T_349, UInt<1>(0h0)) node _T_356 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = or(_T_350, _T_351) node _T_360 = or(_T_359, _T_352) node _T_361 = or(_T_360, _T_353) node _T_362 = or(_T_361, _T_354) node _T_363 = or(_T_362, _T_355) node _T_364 = or(_T_363, _T_356) node _T_365 = or(_T_364, _T_357) node _T_366 = or(_T_365, _T_358) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_366 node _T_367 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_368 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_369 = and(_T_367, _T_368) node _T_370 = or(UInt<1>(0h0), _T_369) node _T_371 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_372 = cvt(_T_371) node _T_373 = and(_T_372, asSInt(UInt<13>(0h1000))) node _T_374 = asSInt(_T_373) node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0))) node _T_376 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_377 = cvt(_T_376) node _T_378 = and(_T_377, asSInt(UInt<13>(0h1000))) node _T_379 = asSInt(_T_378) node _T_380 = eq(_T_379, asSInt(UInt<1>(0h0))) node _T_381 = or(_T_375, _T_380) node _T_382 = and(_T_370, _T_381) node _T_383 = or(UInt<1>(0h0), _T_382) node _T_384 = and(_WIRE_3, _T_383) node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(_T_384, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_384, UInt<1>(0h1), "") : assert_11 node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(source_ok, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_391 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_391, UInt<1>(0h1), "") : assert_13 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(is_aligned, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_398 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_398, UInt<1>(0h1), "") : assert_15 node _T_402 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_402, UInt<1>(0h1), "") : assert_16 node _T_406 = not(io.in.a.bits.mask) node _T_407 = eq(_T_406, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_407, UInt<1>(0h1), "") : assert_17 node _T_411 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_411, UInt<1>(0h1), "") : assert_18 node _T_415 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_417 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_418 = and(_T_416, _T_417) node _T_419 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_420 = shr(io.in.a.bits.source, 2) node _T_421 = eq(_T_420, UInt<1>(0h0)) node _T_422 = leq(UInt<1>(0h0), uncommonBits_20) node _T_423 = and(_T_421, _T_422) node _T_424 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_425 = and(_T_423, _T_424) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_426 = shr(io.in.a.bits.source, 2) node _T_427 = eq(_T_426, UInt<1>(0h1)) node _T_428 = leq(UInt<1>(0h0), uncommonBits_21) node _T_429 = and(_T_427, _T_428) node _T_430 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_431 = and(_T_429, _T_430) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_432 = shr(io.in.a.bits.source, 2) node _T_433 = eq(_T_432, UInt<2>(0h2)) node _T_434 = leq(UInt<1>(0h0), uncommonBits_22) node _T_435 = and(_T_433, _T_434) node _T_436 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_437 = and(_T_435, _T_436) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_438 = shr(io.in.a.bits.source, 2) node _T_439 = eq(_T_438, UInt<2>(0h3)) node _T_440 = leq(UInt<1>(0h0), uncommonBits_23) node _T_441 = and(_T_439, _T_440) node _T_442 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_443 = and(_T_441, _T_442) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_447 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_448 = or(_T_419, _T_425) node _T_449 = or(_T_448, _T_431) node _T_450 = or(_T_449, _T_437) node _T_451 = or(_T_450, _T_443) node _T_452 = or(_T_451, _T_444) node _T_453 = or(_T_452, _T_445) node _T_454 = or(_T_453, _T_446) node _T_455 = or(_T_454, _T_447) node _T_456 = and(_T_418, _T_455) node _T_457 = or(UInt<1>(0h0), _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_457, UInt<1>(0h1), "") : assert_19 node _T_461 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_462 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_463 = and(_T_461, _T_462) node _T_464 = or(UInt<1>(0h0), _T_463) node _T_465 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_466 = cvt(_T_465) node _T_467 = and(_T_466, asSInt(UInt<13>(0h1000))) node _T_468 = asSInt(_T_467) node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0))) node _T_470 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<13>(0h1000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = or(_T_469, _T_474) node _T_476 = and(_T_464, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_24) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_25) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_26) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_27) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_529 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_530 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_531 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_532 = or(_T_503, _T_509) node _T_533 = or(_T_532, _T_515) node _T_534 = or(_T_533, _T_521) node _T_535 = or(_T_534, _T_527) node _T_536 = or(_T_535, _T_528) node _T_537 = or(_T_536, _T_529) node _T_538 = or(_T_537, _T_530) node _T_539 = or(_T_538, _T_531) node _T_540 = and(_T_502, _T_539) node _T_541 = or(UInt<1>(0h0), _T_540) node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_544 = and(_T_542, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<13>(0h1000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = or(_T_550, _T_555) node _T_557 = and(_T_545, _T_556) node _T_558 = or(UInt<1>(0h0), _T_557) node _T_559 = and(_T_541, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_559, UInt<1>(0h1), "") : assert_26 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_569, UInt<1>(0h1), "") : assert_29 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_573, UInt<1>(0h1), "") : assert_30 node _T_577 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_577 : node _T_578 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_579 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_580 = and(_T_578, _T_579) node _T_581 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_28) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<1>(0h1)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_29) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_594 = shr(io.in.a.bits.source, 2) node _T_595 = eq(_T_594, UInt<2>(0h2)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_30) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_599 = and(_T_597, _T_598) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_600 = shr(io.in.a.bits.source, 2) node _T_601 = eq(_T_600, UInt<2>(0h3)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_31) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_605 = and(_T_603, _T_604) node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_609 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_610 = or(_T_581, _T_587) node _T_611 = or(_T_610, _T_593) node _T_612 = or(_T_611, _T_599) node _T_613 = or(_T_612, _T_605) node _T_614 = or(_T_613, _T_606) node _T_615 = or(_T_614, _T_607) node _T_616 = or(_T_615, _T_608) node _T_617 = or(_T_616, _T_609) node _T_618 = and(_T_580, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_621 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<13>(0h1000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<13>(0h1000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_637, UInt<1>(0h1), "") : assert_31 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(source_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(is_aligned, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_647 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_647, UInt<1>(0h1), "") : assert_34 node _T_651 = not(mask) node _T_652 = and(io.in.a.bits.mask, _T_651) node _T_653 = eq(_T_652, UInt<1>(0h0)) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_653, UInt<1>(0h1), "") : assert_35 node _T_657 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_657 : node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_662 = shr(io.in.a.bits.source, 2) node _T_663 = eq(_T_662, UInt<1>(0h0)) node _T_664 = leq(UInt<1>(0h0), uncommonBits_32) node _T_665 = and(_T_663, _T_664) node _T_666 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_667 = and(_T_665, _T_666) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_668 = shr(io.in.a.bits.source, 2) node _T_669 = eq(_T_668, UInt<1>(0h1)) node _T_670 = leq(UInt<1>(0h0), uncommonBits_33) node _T_671 = and(_T_669, _T_670) node _T_672 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_673 = and(_T_671, _T_672) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_674 = shr(io.in.a.bits.source, 2) node _T_675 = eq(_T_674, UInt<2>(0h2)) node _T_676 = leq(UInt<1>(0h0), uncommonBits_34) node _T_677 = and(_T_675, _T_676) node _T_678 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_679 = and(_T_677, _T_678) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_680 = shr(io.in.a.bits.source, 2) node _T_681 = eq(_T_680, UInt<2>(0h3)) node _T_682 = leq(UInt<1>(0h0), uncommonBits_35) node _T_683 = and(_T_681, _T_682) node _T_684 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_689 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_690 = or(_T_661, _T_667) node _T_691 = or(_T_690, _T_673) node _T_692 = or(_T_691, _T_679) node _T_693 = or(_T_692, _T_685) node _T_694 = or(_T_693, _T_686) node _T_695 = or(_T_694, _T_687) node _T_696 = or(_T_695, _T_688) node _T_697 = or(_T_696, _T_689) node _T_698 = and(_T_660, _T_697) node _T_699 = or(UInt<1>(0h0), _T_698) node _T_700 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_701 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_702 = cvt(_T_701) node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000))) node _T_704 = asSInt(_T_703) node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0))) node _T_706 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<13>(0h1000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = or(_T_705, _T_710) node _T_712 = and(_T_700, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = and(_T_699, _T_713) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_714, UInt<1>(0h1), "") : assert_36 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(source_ok, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(is_aligned, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_724 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_724, UInt<1>(0h1), "") : assert_39 node _T_728 = eq(io.in.a.bits.mask, mask) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_728, UInt<1>(0h1), "") : assert_40 node _T_732 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_732 : node _T_733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<1>(0h0)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_36) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<1>(0h1)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_37) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_749 = shr(io.in.a.bits.source, 2) node _T_750 = eq(_T_749, UInt<2>(0h2)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_38) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_755 = shr(io.in.a.bits.source, 2) node _T_756 = eq(_T_755, UInt<2>(0h3)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_39) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_760 = and(_T_758, _T_759) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_764 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_765 = or(_T_736, _T_742) node _T_766 = or(_T_765, _T_748) node _T_767 = or(_T_766, _T_754) node _T_768 = or(_T_767, _T_760) node _T_769 = or(_T_768, _T_761) node _T_770 = or(_T_769, _T_762) node _T_771 = or(_T_770, _T_763) node _T_772 = or(_T_771, _T_764) node _T_773 = and(_T_735, _T_772) node _T_774 = or(UInt<1>(0h0), _T_773) node _T_775 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_776 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<13>(0h1000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = or(_T_780, _T_785) node _T_787 = and(_T_775, _T_786) node _T_788 = or(UInt<1>(0h0), _T_787) node _T_789 = and(_T_774, _T_788) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_789, UInt<1>(0h1), "") : assert_41 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(source_ok, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(is_aligned, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_799 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_799, UInt<1>(0h1), "") : assert_44 node _T_803 = eq(io.in.a.bits.mask, mask) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_803, UInt<1>(0h1), "") : assert_45 node _T_807 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_807 : node _T_808 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_809 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_810 = and(_T_808, _T_809) node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_812 = shr(io.in.a.bits.source, 2) node _T_813 = eq(_T_812, UInt<1>(0h0)) node _T_814 = leq(UInt<1>(0h0), uncommonBits_40) node _T_815 = and(_T_813, _T_814) node _T_816 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_818 = shr(io.in.a.bits.source, 2) node _T_819 = eq(_T_818, UInt<1>(0h1)) node _T_820 = leq(UInt<1>(0h0), uncommonBits_41) node _T_821 = and(_T_819, _T_820) node _T_822 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_823 = and(_T_821, _T_822) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_824 = shr(io.in.a.bits.source, 2) node _T_825 = eq(_T_824, UInt<2>(0h2)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_42) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_829 = and(_T_827, _T_828) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_830 = shr(io.in.a.bits.source, 2) node _T_831 = eq(_T_830, UInt<2>(0h3)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_43) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_835 = and(_T_833, _T_834) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_839 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_840 = or(_T_811, _T_817) node _T_841 = or(_T_840, _T_823) node _T_842 = or(_T_841, _T_829) node _T_843 = or(_T_842, _T_835) node _T_844 = or(_T_843, _T_836) node _T_845 = or(_T_844, _T_837) node _T_846 = or(_T_845, _T_838) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_810, _T_847) node _T_849 = or(UInt<1>(0h0), _T_848) node _T_850 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_851 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<13>(0h1000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = or(_T_855, _T_860) node _T_862 = and(_T_850, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = and(_T_849, _T_863) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_864, UInt<1>(0h1), "") : assert_46 node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(source_ok, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(is_aligned, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_874 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_874, UInt<1>(0h1), "") : assert_49 node _T_878 = eq(io.in.a.bits.mask, mask) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_878, UInt<1>(0h1), "") : assert_50 node _T_882 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_882, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_886 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_886, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_890 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_890 : node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(source_ok_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_894 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_894, UInt<1>(0h1), "") : assert_54 node _T_898 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_898, UInt<1>(0h1), "") : assert_55 node _T_902 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_902, UInt<1>(0h1), "") : assert_56 node _T_906 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_906, UInt<1>(0h1), "") : assert_57 node _T_910 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_910 : node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(source_ok_1, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(sink_ok, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_917 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_917, UInt<1>(0h1), "") : assert_60 node _T_921 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_921, UInt<1>(0h1), "") : assert_61 node _T_925 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_925, UInt<1>(0h1), "") : assert_62 node _T_929 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_929, UInt<1>(0h1), "") : assert_63 node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_934, UInt<1>(0h1), "") : assert_64 node _T_938 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_938 : node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(source_ok_1, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(sink_ok, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_945, UInt<1>(0h1), "") : assert_67 node _T_949 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_949, UInt<1>(0h1), "") : assert_68 node _T_953 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_953, UInt<1>(0h1), "") : assert_69 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = or(_T_957, io.in.d.bits.corrupt) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_958, UInt<1>(0h1), "") : assert_70 node _T_962 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_963 = or(UInt<1>(0h0), _T_962) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_963, UInt<1>(0h1), "") : assert_71 node _T_967 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_967 : node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(source_ok_1, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_971 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_971, UInt<1>(0h1), "") : assert_73 node _T_975 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_975, UInt<1>(0h1), "") : assert_74 node _T_979 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_980 = or(UInt<1>(0h0), _T_979) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_980, UInt<1>(0h1), "") : assert_75 node _T_984 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_984 : node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(source_ok_1, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_988 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_988, UInt<1>(0h1), "") : assert_77 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_993, UInt<1>(0h1), "") : assert_78 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h0), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_998, UInt<1>(0h1), "") : assert_79 node _T_1002 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_81 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_82 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h0), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1019 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1023 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1027 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1031 = eq(a_first, UInt<1>(0h0)) node _T_1032 = and(io.in.a.valid, _T_1031) when _T_1032 : node _T_1033 = eq(io.in.a.bits.opcode, opcode) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_87 node _T_1037 = eq(io.in.a.bits.param, param) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_88 node _T_1041 = eq(io.in.a.bits.size, size) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_89 node _T_1045 = eq(io.in.a.bits.source, source) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_90 node _T_1049 = eq(io.in.a.bits.address, address) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_91 node _T_1053 = and(io.in.a.ready, io.in.a.valid) node _T_1054 = and(_T_1053, a_first) when _T_1054 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1055 = eq(d_first, UInt<1>(0h0)) node _T_1056 = and(io.in.d.valid, _T_1055) when _T_1056 : node _T_1057 = eq(io.in.d.bits.opcode, opcode_1) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_92 node _T_1061 = eq(io.in.d.bits.param, param_1) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_93 node _T_1065 = eq(io.in.d.bits.size, size_1) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_94 node _T_1069 = eq(io.in.d.bits.source, source_1) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_95 node _T_1073 = eq(io.in.d.bits.sink, sink) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_96 node _T_1077 = eq(io.in.d.bits.denied, denied) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_97 node _T_1081 = and(io.in.d.ready, io.in.d.valid) node _T_1082 = and(_T_1081, d_first) when _T_1082 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1083 = and(io.in.a.valid, a_first_1) node _T_1084 = and(_T_1083, UInt<1>(0h1)) when _T_1084 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1085 = and(io.in.a.ready, io.in.a.valid) node _T_1086 = and(_T_1085, a_first_1) node _T_1087 = and(_T_1086, UInt<1>(0h1)) when _T_1087 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1088 = dshr(inflight, io.in.a.bits.source) node _T_1089 = bits(_T_1088, 0, 0) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1094 = and(io.in.d.valid, d_first_1) node _T_1095 = and(_T_1094, UInt<1>(0h1)) node _T_1096 = eq(d_release_ack, UInt<1>(0h0)) node _T_1097 = and(_T_1095, _T_1096) when _T_1097 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1098 = and(io.in.d.ready, io.in.d.valid) node _T_1099 = and(_T_1098, d_first_1) node _T_1100 = and(_T_1099, UInt<1>(0h1)) node _T_1101 = eq(d_release_ack, UInt<1>(0h0)) node _T_1102 = and(_T_1100, _T_1101) when _T_1102 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1103 = and(io.in.d.valid, d_first_1) node _T_1104 = and(_T_1103, UInt<1>(0h1)) node _T_1105 = eq(d_release_ack, UInt<1>(0h0)) node _T_1106 = and(_T_1104, _T_1105) when _T_1106 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1107 = dshr(inflight, io.in.d.bits.source) node _T_1108 = bits(_T_1107, 0, 0) node _T_1109 = or(_T_1108, same_cycle_resp) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1113 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1114 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1115 = or(_T_1113, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_100 node _T_1119 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_101 else : node _T_1123 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1124 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1125 = or(_T_1123, _T_1124) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_102 node _T_1129 = eq(io.in.d.bits.size, a_size_lookup) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_103 node _T_1133 = and(io.in.d.valid, d_first_1) node _T_1134 = and(_T_1133, a_first_1) node _T_1135 = and(_T_1134, io.in.a.valid) node _T_1136 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1137 = and(_T_1135, _T_1136) node _T_1138 = eq(d_release_ack, UInt<1>(0h0)) node _T_1139 = and(_T_1137, _T_1138) when _T_1139 : node _T_1140 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1141 = or(_T_1140, io.in.a.ready) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_104 node _T_1145 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1146 = orr(a_set_wo_ready) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) node _T_1148 = or(_T_1145, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_6 node _T_1152 = orr(inflight) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) node _T_1154 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1155 = or(_T_1153, _T_1154) node _T_1156 = lt(watchdog, plusarg_reader.out) node _T_1157 = or(_T_1155, _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1161 = and(io.in.a.ready, io.in.a.valid) node _T_1162 = and(io.in.d.ready, io.in.d.valid) node _T_1163 = or(_T_1161, _T_1162) when _T_1163 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1164 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1165 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1166 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = and(_T_1164, _T_1167) when _T_1168 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1169 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1170 = and(_T_1169, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1171 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1172 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1173 = and(_T_1171, _T_1172) node _T_1174 = and(_T_1170, _T_1173) when _T_1174 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1175 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1176 = bits(_T_1175, 0, 0) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1181 = and(io.in.d.valid, d_first_2) node _T_1182 = and(_T_1181, UInt<1>(0h1)) node _T_1183 = and(_T_1182, d_release_ack_1) when _T_1183 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1184 = and(io.in.d.ready, io.in.d.valid) node _T_1185 = and(_T_1184, d_first_2) node _T_1186 = and(_T_1185, UInt<1>(0h1)) node _T_1187 = and(_T_1186, d_release_ack_1) when _T_1187 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1188 = and(io.in.d.valid, d_first_2) node _T_1189 = and(_T_1188, UInt<1>(0h1)) node _T_1190 = and(_T_1189, d_release_ack_1) when _T_1190 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1191 = dshr(inflight_1, io.in.d.bits.source) node _T_1192 = bits(_T_1191, 0, 0) node _T_1193 = or(_T_1192, same_cycle_resp_1) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1197 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_109 else : node _T_1201 = eq(io.in.d.bits.size, c_size_lookup) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_110 node _T_1205 = and(io.in.d.valid, d_first_2) node _T_1206 = and(_T_1205, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1207 = and(_T_1206, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1208 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = and(_T_1209, d_release_ack_1) node _T_1211 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1212 = and(_T_1210, _T_1211) when _T_1212 : node _T_1213 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1214 = or(_T_1213, _WIRE_27.ready) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_111 node _T_1218 = orr(c_set_wo_ready) when _T_1218 : node _T_1219 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_7 node _T_1223 = orr(inflight_1) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) node _T_1225 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1226 = or(_T_1224, _T_1225) node _T_1227 = lt(watchdog_1, plusarg_reader_1.out) node _T_1228 = or(_T_1226, _T_1227) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1232 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1233 = and(io.in.d.ready, io.in.d.valid) node _T_1234 = or(_T_1232, _T_1233) when _T_1234 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1161 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1161; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1161; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1234 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1234; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1234; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1234; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1087 = _T_1161 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1087 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1087 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1087 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1087 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1087 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1133 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1133 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1102 = _T_1234 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1102 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1102 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1102 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1205 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1205 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1187 = _T_1234 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1187 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1187 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1187 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_156 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_412 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_156( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_412 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SBToTL : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} input rf_reset : Reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset sbState : UInt, clock, reset, UInt<1>(0h0) inst d_q of Queue2_TLBundleD_a32d8s1k3z4u connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect d_q.io.enq.bits.data, nodeOut.d.bits.data connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect d_q.io.enq.bits.source, nodeOut.d.bits.source connect d_q.io.enq.bits.size, nodeOut.d.bits.size connect d_q.io.enq.bits.param, nodeOut.d.bits.param connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, d_q.io.enq.ready node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 wire muxedData : UInt<8> connect muxedData, UInt<8>(0h0) regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) wire vecData : UInt<8>[8] node _vecData_0_T = bits(io.dataIn, 7, 0) connect vecData[0], _vecData_0_T node _vecData_1_T = bits(io.dataIn, 15, 8) connect vecData[1], _vecData_1_T node _vecData_2_T = bits(io.dataIn, 23, 16) connect vecData[2], _vecData_2_T node _vecData_3_T = bits(io.dataIn, 31, 24) connect vecData[3], _vecData_3_T node _vecData_4_T = bits(io.dataIn, 39, 32) connect vecData[4], _vecData_4_T node _vecData_5_T = bits(io.dataIn, 47, 40) connect vecData[5], _vecData_5_T node _vecData_6_T = bits(io.dataIn, 55, 48) connect vecData[6], _vecData_6_T node _vecData_7_T = bits(io.dataIn, 63, 56) connect vecData[7], _vecData_7_T node _muxedData_T = bits(counter, 2, 0) connect muxedData, vecData[_muxedData_T] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2000)) node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<10>(0h200))) node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<18>(0h2f000))) node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<28>(0hc000000)) node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44) node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<27>(0h4000000))) node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46) node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<29>(0h10020000)) node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49) node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51) node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _rdLegal_addr_T_55 = cvt(_rdLegal_addr_T_54) node _rdLegal_addr_T_56 = and(_rdLegal_addr_T_55, asSInt(UInt<29>(0h10000000))) node _rdLegal_addr_T_57 = asSInt(_rdLegal_addr_T_56) node _rdLegal_addr_T_58 = eq(_rdLegal_addr_T_57, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_59 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) node _rdLegal_addr_T_60 = or(_rdLegal_addr_T_59, _rdLegal_addr_T_18) node _rdLegal_addr_T_61 = or(_rdLegal_addr_T_60, _rdLegal_addr_T_23) node _rdLegal_addr_T_62 = or(_rdLegal_addr_T_61, _rdLegal_addr_T_28) node _rdLegal_addr_T_63 = or(_rdLegal_addr_T_62, _rdLegal_addr_T_33) node _rdLegal_addr_T_64 = or(_rdLegal_addr_T_63, _rdLegal_addr_T_38) node _rdLegal_addr_T_65 = or(_rdLegal_addr_T_64, _rdLegal_addr_T_43) node _rdLegal_addr_T_66 = or(_rdLegal_addr_T_65, _rdLegal_addr_T_48) node _rdLegal_addr_T_67 = or(_rdLegal_addr_T_66, _rdLegal_addr_T_53) node _rdLegal_addr_T_68 = or(_rdLegal_addr_T_67, _rdLegal_addr_T_58) node _rdLegal_addr_T_69 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_68) node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_69) node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2000)) node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<10>(0h200))) node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<18>(0h2f000))) node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2010000)) node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0hc000000)) node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39) node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<27>(0h4000000))) node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41) node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h10020000)) node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44) node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46) node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) node _wrLegal_addr_T_50 = cvt(_wrLegal_addr_T_49) node _wrLegal_addr_T_51 = and(_wrLegal_addr_T_50, asSInt(UInt<29>(0h10000000))) node _wrLegal_addr_T_52 = asSInt(_wrLegal_addr_T_51) node _wrLegal_addr_T_53 = eq(_wrLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_54 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) node _wrLegal_addr_T_55 = or(_wrLegal_addr_T_54, _wrLegal_addr_T_18) node _wrLegal_addr_T_56 = or(_wrLegal_addr_T_55, _wrLegal_addr_T_23) node _wrLegal_addr_T_57 = or(_wrLegal_addr_T_56, _wrLegal_addr_T_28) node _wrLegal_addr_T_58 = or(_wrLegal_addr_T_57, _wrLegal_addr_T_33) node _wrLegal_addr_T_59 = or(_wrLegal_addr_T_58, _wrLegal_addr_T_38) node _wrLegal_addr_T_60 = or(_wrLegal_addr_T_59, _wrLegal_addr_T_43) node _wrLegal_addr_T_61 = or(_wrLegal_addr_T_60, _wrLegal_addr_T_48) node _wrLegal_addr_T_62 = or(_wrLegal_addr_T_61, _wrLegal_addr_T_53) node _wrLegal_addr_T_63 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_62) node _wrLegal_addr_T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) node _wrLegal_addr_T_65 = xor(io.addrIn, UInt<17>(0h10000)) node _wrLegal_addr_T_66 = cvt(_wrLegal_addr_T_65) node _wrLegal_addr_T_67 = and(_wrLegal_addr_T_66, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_68 = asSInt(_wrLegal_addr_T_67) node _wrLegal_addr_T_69 = eq(_wrLegal_addr_T_68, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_70 = and(_wrLegal_addr_T_64, _wrLegal_addr_T_69) node _wrLegal_addr_T_71 = or(UInt<1>(0h0), _wrLegal_addr_T_63) node wrLegal_addr = or(_wrLegal_addr_T_71, _wrLegal_addr_T_70) node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) node _gbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) node _gbits_legal_T_24 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h98013000))) node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) node _gbits_legal_T_29 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) node _gbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2000000)) node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) node _gbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) node _gbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_45 = cvt(_gbits_legal_T_44) node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46) node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0))) node _gbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _gbits_legal_T_50 = cvt(_gbits_legal_T_49) node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51) node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0))) node _gbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _gbits_legal_T_55 = cvt(_gbits_legal_T_54) node _gbits_legal_T_56 = and(_gbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _gbits_legal_T_57 = asSInt(_gbits_legal_T_56) node _gbits_legal_T_58 = eq(_gbits_legal_T_57, asSInt(UInt<1>(0h0))) node _gbits_legal_T_59 = or(_gbits_legal_T_18, _gbits_legal_T_23) node _gbits_legal_T_60 = or(_gbits_legal_T_59, _gbits_legal_T_28) node _gbits_legal_T_61 = or(_gbits_legal_T_60, _gbits_legal_T_33) node _gbits_legal_T_62 = or(_gbits_legal_T_61, _gbits_legal_T_38) node _gbits_legal_T_63 = or(_gbits_legal_T_62, _gbits_legal_T_43) node _gbits_legal_T_64 = or(_gbits_legal_T_63, _gbits_legal_T_48) node _gbits_legal_T_65 = or(_gbits_legal_T_64, _gbits_legal_T_53) node _gbits_legal_T_66 = or(_gbits_legal_T_65, _gbits_legal_T_58) node _gbits_legal_T_67 = and(_gbits_legal_T_13, _gbits_legal_T_66) node _gbits_legal_T_68 = or(UInt<1>(0h0), _gbits_legal_T_9) node gbits_legal = or(_gbits_legal_T_68, _gbits_legal_T_67) wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect gbits.opcode, UInt<3>(0h4) connect gbits.param, UInt<1>(0h0) connect gbits.size, io.sizeIn connect gbits.source, UInt<1>(0h0) connect gbits.address, io.addrIn node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect gbits.mask, UInt<1>(0h1) invalidate gbits.data connect gbits.corrupt, UInt<1>(0h0) node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h9a103000))) node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39) node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41) node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44) node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46) node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _pfbits_legal_T_50 = cvt(_pfbits_legal_T_49) node _pfbits_legal_T_51 = and(_pfbits_legal_T_50, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_52 = asSInt(_pfbits_legal_T_51) node _pfbits_legal_T_53 = eq(_pfbits_legal_T_52, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _pfbits_legal_T_55 = cvt(_pfbits_legal_T_54) node _pfbits_legal_T_56 = and(_pfbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _pfbits_legal_T_57 = asSInt(_pfbits_legal_T_56) node _pfbits_legal_T_58 = eq(_pfbits_legal_T_57, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_59 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) node _pfbits_legal_T_60 = or(_pfbits_legal_T_59, _pfbits_legal_T_28) node _pfbits_legal_T_61 = or(_pfbits_legal_T_60, _pfbits_legal_T_33) node _pfbits_legal_T_62 = or(_pfbits_legal_T_61, _pfbits_legal_T_38) node _pfbits_legal_T_63 = or(_pfbits_legal_T_62, _pfbits_legal_T_43) node _pfbits_legal_T_64 = or(_pfbits_legal_T_63, _pfbits_legal_T_48) node _pfbits_legal_T_65 = or(_pfbits_legal_T_64, _pfbits_legal_T_53) node _pfbits_legal_T_66 = or(_pfbits_legal_T_65, _pfbits_legal_T_58) node _pfbits_legal_T_67 = and(_pfbits_legal_T_13, _pfbits_legal_T_66) node _pfbits_legal_T_68 = or(UInt<1>(0h0), UInt<1>(0h0)) node _pfbits_legal_T_69 = xor(io.addrIn, UInt<17>(0h10000)) node _pfbits_legal_T_70 = cvt(_pfbits_legal_T_69) node _pfbits_legal_T_71 = and(_pfbits_legal_T_70, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_72 = asSInt(_pfbits_legal_T_71) node _pfbits_legal_T_73 = eq(_pfbits_legal_T_72, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_74 = and(_pfbits_legal_T_68, _pfbits_legal_T_73) node _pfbits_legal_T_75 = or(UInt<1>(0h0), _pfbits_legal_T_9) node _pfbits_legal_T_76 = or(_pfbits_legal_T_75, _pfbits_legal_T_67) node pfbits_legal = or(_pfbits_legal_T_76, _pfbits_legal_T_74) wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect pfbits.opcode, UInt<1>(0h0) connect pfbits.param, UInt<1>(0h0) connect pfbits.size, io.sizeIn connect pfbits.source, UInt<1>(0h0) connect pfbits.address, io.addrIn node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect pfbits.mask, UInt<1>(0h1) connect pfbits.data, muxedData connect pfbits.corrupt, UInt<1>(0h0) connect io.rdLegal, rdLegal_addr connect io.wrLegal, wrLegal_addr connect io.sbStateOut, sbState node _T = eq(sbState, UInt<1>(0h1)) when _T : connect nodeOut.a.bits, gbits else : connect nodeOut.a.bits, pfbits node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) connect io.respError, respError node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) node _txLast_T_2 = tail(_txLast_T_1, 1) node txLast = eq(counter, _txLast_T_2) node _counter_T = or(wrTxValid, rdTxValid) node _counter_T_1 = and(_counter_T, txLast) node _counter_T_2 = or(wrTxValid, rdTxValid) node _counter_T_3 = add(counter, UInt<1>(0h1)) node _counter_T_4 = tail(_counter_T_3, 1) node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) connect counter, _counter_T_6 node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) connect io.rdLoad[0], _io_rdLoad_0_T_1 node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) connect io.rdLoad[1], _io_rdLoad_1_T_1 node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) connect io.rdLoad[2], _io_rdLoad_2_T_1 node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) connect io.rdLoad[3], _io_rdLoad_3_T_1 node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) connect io.rdLoad[4], _io_rdLoad_4_T_1 node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) connect io.rdLoad[5], _io_rdLoad_5_T_1 node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) connect io.rdLoad[6], _io_rdLoad_6_T_1 node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) connect io.rdLoad[7], _io_rdLoad_7_T_1 node _T_1 = eq(sbState, UInt<1>(0h0)) when _T_1 : node _sbState_T = and(io.rdEn, io.rdLegal) node _sbState_T_1 = and(io.wrEn, io.wrLegal) node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) connect sbState, _sbState_T_3 else : node _T_2 = eq(sbState, UInt<1>(0h1)) when _T_2 : node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) connect sbState, _sbState_T_5 else : node _T_3 = eq(sbState, UInt<2>(0h2)) when _T_3 : node _sbState_T_6 = and(wrTxValid, txLast) node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) connect sbState, _sbState_T_7 else : node _T_4 = eq(sbState, UInt<2>(0h3)) when _T_4 : node _sbState_T_8 = and(rdTxValid, txLast) node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) connect sbState, _sbState_T_9 else : node _T_5 = eq(sbState, UInt<3>(0h4)) when _T_5 : node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) connect sbState, _sbState_T_11 node _io_rdDone_T = and(rdTxValid, txLast) connect io.rdDone, _io_rdDone_T node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) connect io.wrDone, _io_wrDone_T_2 connect io.dataOut, d_q.io.deq.bits.data node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T_6 = eq(sbState, UInt<1>(0h0)) node _T_7 = eq(sbState, UInt<1>(0h1)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(sbState, UInt<2>(0h2)) node _T_10 = or(_T_8, _T_9) node _T_11 = eq(sbState, UInt<2>(0h3)) node _T_12 = or(_T_10, _T_11) node _T_13 = eq(sbState, UInt<3>(0h4)) node _T_14 = or(_T_12, _T_13) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U \|\|\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert node _T_18 = eq(sbState, UInt<1>(0h0)) node _T_19 = eq(sbState, UInt<1>(0h1)) node _T_20 = eq(sbState, UInt<2>(0h2)) node _T_21 = eq(sbState, UInt<2>(0h3)) node _T_22 = eq(sbState, UInt<3>(0h4)) node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) node _T_24 = and(io.rdEn, _T_23) node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) node _T_26 = and(io.wrEn, _T_25) extmodule plusarg_reader_97 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module SBToTL( // @[SBA.scala:273:9] input clock, // @[SBA.scala:273:9] input reset, // @[SBA.scala:273:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_rdEn, // @[SBA.scala:274:16] input io_wrEn, // @[SBA.scala:274:16] input [127:0] io_addrIn, // @[SBA.scala:274:16] input [127:0] io_dataIn, // @[SBA.scala:274:16] input [2:0] io_sizeIn, // @[SBA.scala:274:16] output io_rdLegal, // @[SBA.scala:274:16] output io_wrLegal, // @[SBA.scala:274:16] output io_rdDone, // @[SBA.scala:274:16] output io_wrDone, // @[SBA.scala:274:16] output io_respError, // @[SBA.scala:274:16] output [7:0] io_dataOut, // @[SBA.scala:274:16] output io_rdLoad_0, // @[SBA.scala:274:16] output io_rdLoad_1, // @[SBA.scala:274:16] output io_rdLoad_2, // @[SBA.scala:274:16] output io_rdLoad_3, // @[SBA.scala:274:16] output io_rdLoad_4, // @[SBA.scala:274:16] output io_rdLoad_5, // @[SBA.scala:274:16] output io_rdLoad_6, // @[SBA.scala:274:16] output io_rdLoad_7, // @[SBA.scala:274:16] output [2:0] io_sbStateOut // @[SBA.scala:274:16] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] reg [2:0] sbState; // @[SBA.scala:295:26] wire _rdTxValid_T = sbState == 3'h3; // @[SBA.scala:295:26, :299:25] wire _io_wrDone_T = sbState == 3'h4; // @[SBA.scala:295:26, :299:62] wire d_q_io_deq_ready = _rdTxValid_T \| _io_wrDone_T; // @[SBA.scala:299:{25,50,62}] reg [3:0] counter; // @[SBA.scala:307:26] wire [7:0][7:0] _GEN = {{io_dataIn[63:56]}, {io_dataIn[55:48]}, {io_dataIn[47:40]}, {io_dataIn[39:32]}, {io_dataIn[31:24]}, {io_dataIn[23:16]}, {io_dataIn[15:8]}, {io_dataIn[7:0]}}; // @[SBA.scala:309:63, :310:15] wire [118:0] _GEN_0 = {io_addrIn[127:14], io_addrIn[13:9] ^ 5'h10}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_1 = {io_addrIn[127:14], ~(io_addrIn[13:12])}; // @[Parameters.scala:137:{31,41,46}] wire [114:0] _GEN_2 = {io_addrIn[127:21], io_addrIn[20:17] ^ 4'h8, io_addrIn[15:12]}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_3 = {io_addrIn[127:26], io_addrIn[25:16] ^ 10'h200}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_4 = {io_addrIn[127:26], io_addrIn[25:12] ^ 14'h2010}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_5 = {io_addrIn[127:28], io_addrIn[27:16] ^ 12'h800}; // @[Parameters.scala:137:{31,41,46}] wire [101:0] _GEN_6 = {io_addrIn[127:28], ~(io_addrIn[27:26])}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_7 = {io_addrIn[127:29], io_addrIn[28:12] ^ 17'h10020}; // @[Parameters.scala:137:{31,41,46}] wire [99:0] _GEN_8 = {io_addrIn[127:32], io_addrIn[31:28] ^ 4'h8}; // @[Parameters.scala:137:{31,41,46}] wire io_rdLegal_0 = ~(\|(io_addrIn[127:13])) \| ~(\|_GEN_0) \| ~(\|_GEN_1) \| {io_addrIn[127:17], ~(io_addrIn[16])} == 112'h0 \| ~(\|_GEN_2) \| ~(\|_GEN_3) \| ~(\|_GEN_4) \| ~(\|_GEN_5) \| ~(\|_GEN_6) \| ~(\|_GEN_7) \| ~(\|_GEN_8); // @[Parameters.scala:685:42] wire io_wrLegal_0 = ~(\|(io_addrIn[127:13])) \| ~(\|_GEN_0) \| ~(\|_GEN_1) \| ~(\|_GEN_2) \| ~(\|_GEN_3) \| ~(\|_GEN_4) \| ~(\|_GEN_5) \| ~(\|_GEN_6) \| ~(\|_GEN_7) \| ~(\|_GEN_8); // @[Parameters.scala:685:42] wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18] wire _nodeOut_a_valid_T_1 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29] wire rdTxValid = _rdTxValid_T & _d_q_io_deq_valid & d_q_io_deq_ready; // @[Decoupled.scala:362:21] wire txLast = {4'h0, counter} == (8'h1 << io_sizeIn) - 8'h1; // @[SBA.scala:307:26, :340:{29,39,53}] wire _GEN_9 = sbState == 3'h0; // @[SBA.scala:295:26, :349:19] wire nodeOut_a_valid = _nodeOut_a_valid_T \| _nodeOut_a_valid_T_1; // @[SBA.scala:322:18, :338:29, :366:52]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e11_s53_4 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<107>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 106, 106) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 105, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 161, 54) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 54, 53) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 159, 55) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 53, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 54, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 107, 50) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 52, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 2) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[14] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 27, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node _CDom_reduced4SigExtra_reducedVec_7_T = bits(_CDom_reduced4SigExtra_T_1, 31, 28) node _CDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_7_T) connect CDom_reduced4SigExtra_reducedVec[7], _CDom_reduced4SigExtra_reducedVec_7_T_1 node _CDom_reduced4SigExtra_reducedVec_8_T = bits(_CDom_reduced4SigExtra_T_1, 35, 32) node _CDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_8_T) connect CDom_reduced4SigExtra_reducedVec[8], _CDom_reduced4SigExtra_reducedVec_8_T_1 node _CDom_reduced4SigExtra_reducedVec_9_T = bits(_CDom_reduced4SigExtra_T_1, 39, 36) node _CDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_9_T) connect CDom_reduced4SigExtra_reducedVec[9], _CDom_reduced4SigExtra_reducedVec_9_T_1 node _CDom_reduced4SigExtra_reducedVec_10_T = bits(_CDom_reduced4SigExtra_T_1, 43, 40) node _CDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_10_T) connect CDom_reduced4SigExtra_reducedVec[10], _CDom_reduced4SigExtra_reducedVec_10_T_1 node _CDom_reduced4SigExtra_reducedVec_11_T = bits(_CDom_reduced4SigExtra_T_1, 47, 44) node _CDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_11_T) connect CDom_reduced4SigExtra_reducedVec[11], _CDom_reduced4SigExtra_reducedVec_11_T_1 node _CDom_reduced4SigExtra_reducedVec_12_T = bits(_CDom_reduced4SigExtra_T_1, 51, 48) node _CDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_12_T) connect CDom_reduced4SigExtra_reducedVec[12], _CDom_reduced4SigExtra_reducedVec_12_T_1 node _CDom_reduced4SigExtra_reducedVec_13_T = bits(_CDom_reduced4SigExtra_T_1, 54, 52) node _CDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_13_T) connect CDom_reduced4SigExtra_reducedVec[13], _CDom_reduced4SigExtra_reducedVec_13_T_1 node CDom_reduced4SigExtra_lo_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo_lo = cat(CDom_reduced4SigExtra_lo_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_lo_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_lo_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_lo_hi_hi, CDom_reduced4SigExtra_lo_hi_lo) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_lo_lo) node CDom_reduced4SigExtra_hi_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[9], CDom_reduced4SigExtra_reducedVec[8]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_hi_lo_hi, CDom_reduced4SigExtra_reducedVec[7]) node CDom_reduced4SigExtra_hi_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[11], CDom_reduced4SigExtra_reducedVec[10]) node CDom_reduced4SigExtra_hi_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[13], CDom_reduced4SigExtra_reducedVec[12]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_hi_hi_hi, CDom_reduced4SigExtra_hi_hi_lo) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 13, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 7, 0) node _CDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) node _CDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _CDom_reduced4SigExtra_T_7) node _CDom_reduced4SigExtra_T_9 = shr(_CDom_reduced4SigExtra_T_6, 4) node _CDom_reduced4SigExtra_T_10 = and(_CDom_reduced4SigExtra_T_9, _CDom_reduced4SigExtra_T_8) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 0) node _CDom_reduced4SigExtra_T_12 = shl(_CDom_reduced4SigExtra_T_11, 4) node _CDom_reduced4SigExtra_T_13 = not(_CDom_reduced4SigExtra_T_8) node _CDom_reduced4SigExtra_T_14 = and(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = or(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_8, 5, 0) node _CDom_reduced4SigExtra_T_17 = shl(_CDom_reduced4SigExtra_T_16, 2) node _CDom_reduced4SigExtra_T_18 = xor(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_17) node _CDom_reduced4SigExtra_T_19 = shr(_CDom_reduced4SigExtra_T_15, 2) node _CDom_reduced4SigExtra_T_20 = and(_CDom_reduced4SigExtra_T_19, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_21 = bits(_CDom_reduced4SigExtra_T_15, 5, 0) node _CDom_reduced4SigExtra_T_22 = shl(_CDom_reduced4SigExtra_T_21, 2) node _CDom_reduced4SigExtra_T_23 = not(_CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_24 = and(_CDom_reduced4SigExtra_T_22, _CDom_reduced4SigExtra_T_23) node _CDom_reduced4SigExtra_T_25 = or(_CDom_reduced4SigExtra_T_20, _CDom_reduced4SigExtra_T_24) node _CDom_reduced4SigExtra_T_26 = bits(_CDom_reduced4SigExtra_T_18, 6, 0) node _CDom_reduced4SigExtra_T_27 = shl(_CDom_reduced4SigExtra_T_26, 1) node _CDom_reduced4SigExtra_T_28 = xor(_CDom_reduced4SigExtra_T_18, _CDom_reduced4SigExtra_T_27) node _CDom_reduced4SigExtra_T_29 = shr(_CDom_reduced4SigExtra_T_25, 1) node _CDom_reduced4SigExtra_T_30 = and(_CDom_reduced4SigExtra_T_29, _CDom_reduced4SigExtra_T_28) node _CDom_reduced4SigExtra_T_31 = bits(_CDom_reduced4SigExtra_T_25, 6, 0) node _CDom_reduced4SigExtra_T_32 = shl(_CDom_reduced4SigExtra_T_31, 1) node _CDom_reduced4SigExtra_T_33 = not(_CDom_reduced4SigExtra_T_28) node _CDom_reduced4SigExtra_T_34 = and(_CDom_reduced4SigExtra_T_32, _CDom_reduced4SigExtra_T_33) node _CDom_reduced4SigExtra_T_35 = or(_CDom_reduced4SigExtra_T_30, _CDom_reduced4SigExtra_T_34) node _CDom_reduced4SigExtra_T_36 = bits(_CDom_reduced4SigExtra_T_5, 12, 8) node _CDom_reduced4SigExtra_T_37 = bits(_CDom_reduced4SigExtra_T_36, 3, 0) node _CDom_reduced4SigExtra_T_38 = bits(_CDom_reduced4SigExtra_T_37, 1, 0) node _CDom_reduced4SigExtra_T_39 = bits(_CDom_reduced4SigExtra_T_38, 0, 0) node _CDom_reduced4SigExtra_T_40 = bits(_CDom_reduced4SigExtra_T_38, 1, 1) node _CDom_reduced4SigExtra_T_41 = cat(_CDom_reduced4SigExtra_T_39, _CDom_reduced4SigExtra_T_40) node _CDom_reduced4SigExtra_T_42 = bits(_CDom_reduced4SigExtra_T_37, 3, 2) node _CDom_reduced4SigExtra_T_43 = bits(_CDom_reduced4SigExtra_T_42, 0, 0) node _CDom_reduced4SigExtra_T_44 = bits(_CDom_reduced4SigExtra_T_42, 1, 1) node _CDom_reduced4SigExtra_T_45 = cat(_CDom_reduced4SigExtra_T_43, _CDom_reduced4SigExtra_T_44) node _CDom_reduced4SigExtra_T_46 = cat(_CDom_reduced4SigExtra_T_41, _CDom_reduced4SigExtra_T_45) node _CDom_reduced4SigExtra_T_47 = bits(_CDom_reduced4SigExtra_T_36, 4, 4) node _CDom_reduced4SigExtra_T_48 = cat(_CDom_reduced4SigExtra_T_46, _CDom_reduced4SigExtra_T_47) node _CDom_reduced4SigExtra_T_49 = cat(_CDom_reduced4SigExtra_T_35, _CDom_reduced4SigExtra_T_48) node _CDom_reduced4SigExtra_T_50 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_49) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_50) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 109, 109) node _notCDom_absSigSum_T = bits(sigSum, 108, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 108, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[55] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 51, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_26_T = bits(notCDom_absSigSum, 53, 52) node _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_26_T) connect notCDom_reduced2AbsSigSum_reducedVec[26], _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_27_T = bits(notCDom_absSigSum, 55, 54) node _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_27_T) connect notCDom_reduced2AbsSigSum_reducedVec[27], _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_28_T = bits(notCDom_absSigSum, 57, 56) node _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_28_T) connect notCDom_reduced2AbsSigSum_reducedVec[28], _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_29_T = bits(notCDom_absSigSum, 59, 58) node _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_29_T) connect notCDom_reduced2AbsSigSum_reducedVec[29], _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_30_T = bits(notCDom_absSigSum, 61, 60) node _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_30_T) connect notCDom_reduced2AbsSigSum_reducedVec[30], _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_31_T = bits(notCDom_absSigSum, 63, 62) node _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_31_T) connect notCDom_reduced2AbsSigSum_reducedVec[31], _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_32_T = bits(notCDom_absSigSum, 65, 64) node _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_32_T) connect notCDom_reduced2AbsSigSum_reducedVec[32], _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_33_T = bits(notCDom_absSigSum, 67, 66) node _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_33_T) connect notCDom_reduced2AbsSigSum_reducedVec[33], _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_34_T = bits(notCDom_absSigSum, 69, 68) node _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_34_T) connect notCDom_reduced2AbsSigSum_reducedVec[34], _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_35_T = bits(notCDom_absSigSum, 71, 70) node _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_35_T) connect notCDom_reduced2AbsSigSum_reducedVec[35], _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_36_T = bits(notCDom_absSigSum, 73, 72) node _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_36_T) connect notCDom_reduced2AbsSigSum_reducedVec[36], _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_37_T = bits(notCDom_absSigSum, 75, 74) node _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_37_T) connect notCDom_reduced2AbsSigSum_reducedVec[37], _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_38_T = bits(notCDom_absSigSum, 77, 76) node _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_38_T) connect notCDom_reduced2AbsSigSum_reducedVec[38], _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_39_T = bits(notCDom_absSigSum, 79, 78) node _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_39_T) connect notCDom_reduced2AbsSigSum_reducedVec[39], _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_40_T = bits(notCDom_absSigSum, 81, 80) node _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_40_T) connect notCDom_reduced2AbsSigSum_reducedVec[40], _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_41_T = bits(notCDom_absSigSum, 83, 82) node _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_41_T) connect notCDom_reduced2AbsSigSum_reducedVec[41], _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_42_T = bits(notCDom_absSigSum, 85, 84) node _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_42_T) connect notCDom_reduced2AbsSigSum_reducedVec[42], _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_43_T = bits(notCDom_absSigSum, 87, 86) node _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_43_T) connect notCDom_reduced2AbsSigSum_reducedVec[43], _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_44_T = bits(notCDom_absSigSum, 89, 88) node _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_44_T) connect notCDom_reduced2AbsSigSum_reducedVec[44], _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_45_T = bits(notCDom_absSigSum, 91, 90) node _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_45_T) connect notCDom_reduced2AbsSigSum_reducedVec[45], _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_46_T = bits(notCDom_absSigSum, 93, 92) node _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_46_T) connect notCDom_reduced2AbsSigSum_reducedVec[46], _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_47_T = bits(notCDom_absSigSum, 95, 94) node _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_47_T) connect notCDom_reduced2AbsSigSum_reducedVec[47], _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_48_T = bits(notCDom_absSigSum, 97, 96) node _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_48_T) connect notCDom_reduced2AbsSigSum_reducedVec[48], _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_49_T = bits(notCDom_absSigSum, 99, 98) node _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_49_T) connect notCDom_reduced2AbsSigSum_reducedVec[49], _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_50_T = bits(notCDom_absSigSum, 101, 100) node _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_50_T) connect notCDom_reduced2AbsSigSum_reducedVec[50], _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_51_T = bits(notCDom_absSigSum, 103, 102) node _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_51_T) connect notCDom_reduced2AbsSigSum_reducedVec[51], _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_52_T = bits(notCDom_absSigSum, 105, 104) node _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_52_T) connect notCDom_reduced2AbsSigSum_reducedVec[52], _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_53_T = bits(notCDom_absSigSum, 107, 106) node _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_53_T) connect notCDom_reduced2AbsSigSum_reducedVec[53], _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_54_T = bits(notCDom_absSigSum, 108, 108) node _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_54_T) connect notCDom_reduced2AbsSigSum_reducedVec[54], _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_lo_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[17], notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[19], notCDom_reduced2AbsSigSum_reducedVec[18]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[22], notCDom_reduced2AbsSigSum_reducedVec[21]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[24], notCDom_reduced2AbsSigSum_reducedVec[23]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[26], notCDom_reduced2AbsSigSum_reducedVec[25]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[29], notCDom_reduced2AbsSigSum_reducedVec[28]) node notCDom_reduced2AbsSigSum_hi_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[27]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[31], notCDom_reduced2AbsSigSum_reducedVec[30]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[33], notCDom_reduced2AbsSigSum_reducedVec[32]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[36], notCDom_reduced2AbsSigSum_reducedVec[35]) node notCDom_reduced2AbsSigSum_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[34]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[38], notCDom_reduced2AbsSigSum_reducedVec[37]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[40], notCDom_reduced2AbsSigSum_reducedVec[39]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[43], notCDom_reduced2AbsSigSum_reducedVec[42]) node notCDom_reduced2AbsSigSum_hi_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[41]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[45], notCDom_reduced2AbsSigSum_reducedVec[44]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[47], notCDom_reduced2AbsSigSum_reducedVec[46]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[50], notCDom_reduced2AbsSigSum_reducedVec[49]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[48]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[52], notCDom_reduced2AbsSigSum_reducedVec[51]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[54], notCDom_reduced2AbsSigSum_reducedVec[53]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = bits(notCDom_reduced2AbsSigSum, 26, 26) node _notCDom_normDistReduced2_T_27 = bits(notCDom_reduced2AbsSigSum, 27, 27) node _notCDom_normDistReduced2_T_28 = bits(notCDom_reduced2AbsSigSum, 28, 28) node _notCDom_normDistReduced2_T_29 = bits(notCDom_reduced2AbsSigSum, 29, 29) node _notCDom_normDistReduced2_T_30 = bits(notCDom_reduced2AbsSigSum, 30, 30) node _notCDom_normDistReduced2_T_31 = bits(notCDom_reduced2AbsSigSum, 31, 31) node _notCDom_normDistReduced2_T_32 = bits(notCDom_reduced2AbsSigSum, 32, 32) node _notCDom_normDistReduced2_T_33 = bits(notCDom_reduced2AbsSigSum, 33, 33) node _notCDom_normDistReduced2_T_34 = bits(notCDom_reduced2AbsSigSum, 34, 34) node _notCDom_normDistReduced2_T_35 = bits(notCDom_reduced2AbsSigSum, 35, 35) node _notCDom_normDistReduced2_T_36 = bits(notCDom_reduced2AbsSigSum, 36, 36) node _notCDom_normDistReduced2_T_37 = bits(notCDom_reduced2AbsSigSum, 37, 37) node _notCDom_normDistReduced2_T_38 = bits(notCDom_reduced2AbsSigSum, 38, 38) node _notCDom_normDistReduced2_T_39 = bits(notCDom_reduced2AbsSigSum, 39, 39) node _notCDom_normDistReduced2_T_40 = bits(notCDom_reduced2AbsSigSum, 40, 40) node _notCDom_normDistReduced2_T_41 = bits(notCDom_reduced2AbsSigSum, 41, 41) node _notCDom_normDistReduced2_T_42 = bits(notCDom_reduced2AbsSigSum, 42, 42) node _notCDom_normDistReduced2_T_43 = bits(notCDom_reduced2AbsSigSum, 43, 43) node _notCDom_normDistReduced2_T_44 = bits(notCDom_reduced2AbsSigSum, 44, 44) node _notCDom_normDistReduced2_T_45 = bits(notCDom_reduced2AbsSigSum, 45, 45) node _notCDom_normDistReduced2_T_46 = bits(notCDom_reduced2AbsSigSum, 46, 46) node _notCDom_normDistReduced2_T_47 = bits(notCDom_reduced2AbsSigSum, 47, 47) node _notCDom_normDistReduced2_T_48 = bits(notCDom_reduced2AbsSigSum, 48, 48) node _notCDom_normDistReduced2_T_49 = bits(notCDom_reduced2AbsSigSum, 49, 49) node _notCDom_normDistReduced2_T_50 = bits(notCDom_reduced2AbsSigSum, 50, 50) node _notCDom_normDistReduced2_T_51 = bits(notCDom_reduced2AbsSigSum, 51, 51) node _notCDom_normDistReduced2_T_52 = bits(notCDom_reduced2AbsSigSum, 52, 52) node _notCDom_normDistReduced2_T_53 = bits(notCDom_reduced2AbsSigSum, 53, 53) node _notCDom_normDistReduced2_T_54 = bits(notCDom_reduced2AbsSigSum, 54, 54) node _notCDom_normDistReduced2_T_55 = mux(_notCDom_normDistReduced2_T_1, UInt<6>(0h35), UInt<6>(0h36)) node _notCDom_normDistReduced2_T_56 = mux(_notCDom_normDistReduced2_T_2, UInt<6>(0h34), _notCDom_normDistReduced2_T_55) node _notCDom_normDistReduced2_T_57 = mux(_notCDom_normDistReduced2_T_3, UInt<6>(0h33), _notCDom_normDistReduced2_T_56) node _notCDom_normDistReduced2_T_58 = mux(_notCDom_normDistReduced2_T_4, UInt<6>(0h32), _notCDom_normDistReduced2_T_57) node _notCDom_normDistReduced2_T_59 = mux(_notCDom_normDistReduced2_T_5, UInt<6>(0h31), _notCDom_normDistReduced2_T_58) node _notCDom_normDistReduced2_T_60 = mux(_notCDom_normDistReduced2_T_6, UInt<6>(0h30), _notCDom_normDistReduced2_T_59) node _notCDom_normDistReduced2_T_61 = mux(_notCDom_normDistReduced2_T_7, UInt<6>(0h2f), _notCDom_normDistReduced2_T_60) node _notCDom_normDistReduced2_T_62 = mux(_notCDom_normDistReduced2_T_8, UInt<6>(0h2e), _notCDom_normDistReduced2_T_61) node _notCDom_normDistReduced2_T_63 = mux(_notCDom_normDistReduced2_T_9, UInt<6>(0h2d), _notCDom_normDistReduced2_T_62) node _notCDom_normDistReduced2_T_64 = mux(_notCDom_normDistReduced2_T_10, UInt<6>(0h2c), _notCDom_normDistReduced2_T_63) node _notCDom_normDistReduced2_T_65 = mux(_notCDom_normDistReduced2_T_11, UInt<6>(0h2b), _notCDom_normDistReduced2_T_64) node _notCDom_normDistReduced2_T_66 = mux(_notCDom_normDistReduced2_T_12, UInt<6>(0h2a), _notCDom_normDistReduced2_T_65) node _notCDom_normDistReduced2_T_67 = mux(_notCDom_normDistReduced2_T_13, UInt<6>(0h29), _notCDom_normDistReduced2_T_66) node _notCDom_normDistReduced2_T_68 = mux(_notCDom_normDistReduced2_T_14, UInt<6>(0h28), _notCDom_normDistReduced2_T_67) node _notCDom_normDistReduced2_T_69 = mux(_notCDom_normDistReduced2_T_15, UInt<6>(0h27), _notCDom_normDistReduced2_T_68) node _notCDom_normDistReduced2_T_70 = mux(_notCDom_normDistReduced2_T_16, UInt<6>(0h26), _notCDom_normDistReduced2_T_69) node _notCDom_normDistReduced2_T_71 = mux(_notCDom_normDistReduced2_T_17, UInt<6>(0h25), _notCDom_normDistReduced2_T_70) node _notCDom_normDistReduced2_T_72 = mux(_notCDom_normDistReduced2_T_18, UInt<6>(0h24), _notCDom_normDistReduced2_T_71) node _notCDom_normDistReduced2_T_73 = mux(_notCDom_normDistReduced2_T_19, UInt<6>(0h23), _notCDom_normDistReduced2_T_72) node _notCDom_normDistReduced2_T_74 = mux(_notCDom_normDistReduced2_T_20, UInt<6>(0h22), _notCDom_normDistReduced2_T_73) node _notCDom_normDistReduced2_T_75 = mux(_notCDom_normDistReduced2_T_21, UInt<6>(0h21), _notCDom_normDistReduced2_T_74) node _notCDom_normDistReduced2_T_76 = mux(_notCDom_normDistReduced2_T_22, UInt<6>(0h20), _notCDom_normDistReduced2_T_75) node _notCDom_normDistReduced2_T_77 = mux(_notCDom_normDistReduced2_T_23, UInt<5>(0h1f), _notCDom_normDistReduced2_T_76) node _notCDom_normDistReduced2_T_78 = mux(_notCDom_normDistReduced2_T_24, UInt<5>(0h1e), _notCDom_normDistReduced2_T_77) node _notCDom_normDistReduced2_T_79 = mux(_notCDom_normDistReduced2_T_25, UInt<5>(0h1d), _notCDom_normDistReduced2_T_78) node _notCDom_normDistReduced2_T_80 = mux(_notCDom_normDistReduced2_T_26, UInt<5>(0h1c), _notCDom_normDistReduced2_T_79) node _notCDom_normDistReduced2_T_81 = mux(_notCDom_normDistReduced2_T_27, UInt<5>(0h1b), _notCDom_normDistReduced2_T_80) node _notCDom_normDistReduced2_T_82 = mux(_notCDom_normDistReduced2_T_28, UInt<5>(0h1a), _notCDom_normDistReduced2_T_81) node _notCDom_normDistReduced2_T_83 = mux(_notCDom_normDistReduced2_T_29, UInt<5>(0h19), _notCDom_normDistReduced2_T_82) node _notCDom_normDistReduced2_T_84 = mux(_notCDom_normDistReduced2_T_30, UInt<5>(0h18), _notCDom_normDistReduced2_T_83) node _notCDom_normDistReduced2_T_85 = mux(_notCDom_normDistReduced2_T_31, UInt<5>(0h17), _notCDom_normDistReduced2_T_84) node _notCDom_normDistReduced2_T_86 = mux(_notCDom_normDistReduced2_T_32, UInt<5>(0h16), _notCDom_normDistReduced2_T_85) node _notCDom_normDistReduced2_T_87 = mux(_notCDom_normDistReduced2_T_33, UInt<5>(0h15), _notCDom_normDistReduced2_T_86) node _notCDom_normDistReduced2_T_88 = mux(_notCDom_normDistReduced2_T_34, UInt<5>(0h14), _notCDom_normDistReduced2_T_87) node _notCDom_normDistReduced2_T_89 = mux(_notCDom_normDistReduced2_T_35, UInt<5>(0h13), _notCDom_normDistReduced2_T_88) node _notCDom_normDistReduced2_T_90 = mux(_notCDom_normDistReduced2_T_36, UInt<5>(0h12), _notCDom_normDistReduced2_T_89) node _notCDom_normDistReduced2_T_91 = mux(_notCDom_normDistReduced2_T_37, UInt<5>(0h11), _notCDom_normDistReduced2_T_90) node _notCDom_normDistReduced2_T_92 = mux(_notCDom_normDistReduced2_T_38, UInt<5>(0h10), _notCDom_normDistReduced2_T_91) node _notCDom_normDistReduced2_T_93 = mux(_notCDom_normDistReduced2_T_39, UInt<4>(0hf), _notCDom_normDistReduced2_T_92) node _notCDom_normDistReduced2_T_94 = mux(_notCDom_normDistReduced2_T_40, UInt<4>(0he), _notCDom_normDistReduced2_T_93) node _notCDom_normDistReduced2_T_95 = mux(_notCDom_normDistReduced2_T_41, UInt<4>(0hd), _notCDom_normDistReduced2_T_94) node _notCDom_normDistReduced2_T_96 = mux(_notCDom_normDistReduced2_T_42, UInt<4>(0hc), _notCDom_normDistReduced2_T_95) node _notCDom_normDistReduced2_T_97 = mux(_notCDom_normDistReduced2_T_43, UInt<4>(0hb), _notCDom_normDistReduced2_T_96) node _notCDom_normDistReduced2_T_98 = mux(_notCDom_normDistReduced2_T_44, UInt<4>(0ha), _notCDom_normDistReduced2_T_97) node _notCDom_normDistReduced2_T_99 = mux(_notCDom_normDistReduced2_T_45, UInt<4>(0h9), _notCDom_normDistReduced2_T_98) node _notCDom_normDistReduced2_T_100 = mux(_notCDom_normDistReduced2_T_46, UInt<4>(0h8), _notCDom_normDistReduced2_T_99) node _notCDom_normDistReduced2_T_101 = mux(_notCDom_normDistReduced2_T_47, UInt<3>(0h7), _notCDom_normDistReduced2_T_100) node _notCDom_normDistReduced2_T_102 = mux(_notCDom_normDistReduced2_T_48, UInt<3>(0h6), _notCDom_normDistReduced2_T_101) node _notCDom_normDistReduced2_T_103 = mux(_notCDom_normDistReduced2_T_49, UInt<3>(0h5), _notCDom_normDistReduced2_T_102) node _notCDom_normDistReduced2_T_104 = mux(_notCDom_normDistReduced2_T_50, UInt<3>(0h4), _notCDom_normDistReduced2_T_103) node _notCDom_normDistReduced2_T_105 = mux(_notCDom_normDistReduced2_T_51, UInt<2>(0h3), _notCDom_normDistReduced2_T_104) node _notCDom_normDistReduced2_T_106 = mux(_notCDom_normDistReduced2_T_52, UInt<2>(0h2), _notCDom_normDistReduced2_T_105) node _notCDom_normDistReduced2_T_107 = mux(_notCDom_normDistReduced2_T_53, UInt<1>(0h1), _notCDom_normDistReduced2_T_106) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_54, UInt<1>(0h0), _notCDom_normDistReduced2_T_107) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 109, 52) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 26, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[14] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 13, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node _notCDom_reduced4SigExtra_reducedVec_7_T = bits(_notCDom_reduced4SigExtra_T_1, 15, 14) node _notCDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_7_T) connect notCDom_reduced4SigExtra_reducedVec[7], _notCDom_reduced4SigExtra_reducedVec_7_T_1 node _notCDom_reduced4SigExtra_reducedVec_8_T = bits(_notCDom_reduced4SigExtra_T_1, 17, 16) node _notCDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_8_T) connect notCDom_reduced4SigExtra_reducedVec[8], _notCDom_reduced4SigExtra_reducedVec_8_T_1 node _notCDom_reduced4SigExtra_reducedVec_9_T = bits(_notCDom_reduced4SigExtra_T_1, 19, 18) node _notCDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_9_T) connect notCDom_reduced4SigExtra_reducedVec[9], _notCDom_reduced4SigExtra_reducedVec_9_T_1 node _notCDom_reduced4SigExtra_reducedVec_10_T = bits(_notCDom_reduced4SigExtra_T_1, 21, 20) node _notCDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_10_T) connect notCDom_reduced4SigExtra_reducedVec[10], _notCDom_reduced4SigExtra_reducedVec_10_T_1 node _notCDom_reduced4SigExtra_reducedVec_11_T = bits(_notCDom_reduced4SigExtra_T_1, 23, 22) node _notCDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_11_T) connect notCDom_reduced4SigExtra_reducedVec[11], _notCDom_reduced4SigExtra_reducedVec_11_T_1 node _notCDom_reduced4SigExtra_reducedVec_12_T = bits(_notCDom_reduced4SigExtra_T_1, 25, 24) node _notCDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_12_T) connect notCDom_reduced4SigExtra_reducedVec[12], _notCDom_reduced4SigExtra_reducedVec_12_T_1 node _notCDom_reduced4SigExtra_reducedVec_13_T = bits(_notCDom_reduced4SigExtra_T_1, 26, 26) node _notCDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_13_T) connect notCDom_reduced4SigExtra_reducedVec[13], _notCDom_reduced4SigExtra_reducedVec_13_T_1 node notCDom_reduced4SigExtra_lo_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo_lo = cat(notCDom_reduced4SigExtra_lo_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_lo_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_lo_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_lo_hi_hi, notCDom_reduced4SigExtra_lo_hi_lo) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_lo_lo) node notCDom_reduced4SigExtra_hi_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[9], notCDom_reduced4SigExtra_reducedVec[8]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_hi_lo_hi, notCDom_reduced4SigExtra_reducedVec[7]) node notCDom_reduced4SigExtra_hi_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[11], notCDom_reduced4SigExtra_reducedVec[10]) node notCDom_reduced4SigExtra_hi_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[13], notCDom_reduced4SigExtra_reducedVec[12]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_hi_hi_hi, notCDom_reduced4SigExtra_hi_hi_lo) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 13, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 7, 0) node _notCDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) node _notCDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _notCDom_reduced4SigExtra_T_7) node _notCDom_reduced4SigExtra_T_9 = shr(_notCDom_reduced4SigExtra_T_6, 4) node _notCDom_reduced4SigExtra_T_10 = and(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_8) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 0) node _notCDom_reduced4SigExtra_T_12 = shl(_notCDom_reduced4SigExtra_T_11, 4) node _notCDom_reduced4SigExtra_T_13 = not(_notCDom_reduced4SigExtra_T_8) node _notCDom_reduced4SigExtra_T_14 = and(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = or(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_8, 5, 0) node _notCDom_reduced4SigExtra_T_17 = shl(_notCDom_reduced4SigExtra_T_16, 2) node _notCDom_reduced4SigExtra_T_18 = xor(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_17) node _notCDom_reduced4SigExtra_T_19 = shr(_notCDom_reduced4SigExtra_T_15, 2) node _notCDom_reduced4SigExtra_T_20 = and(_notCDom_reduced4SigExtra_T_19, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_21 = bits(_notCDom_reduced4SigExtra_T_15, 5, 0) node _notCDom_reduced4SigExtra_T_22 = shl(_notCDom_reduced4SigExtra_T_21, 2) node _notCDom_reduced4SigExtra_T_23 = not(_notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_24 = and(_notCDom_reduced4SigExtra_T_22, _notCDom_reduced4SigExtra_T_23) node _notCDom_reduced4SigExtra_T_25 = or(_notCDom_reduced4SigExtra_T_20, _notCDom_reduced4SigExtra_T_24) node _notCDom_reduced4SigExtra_T_26 = bits(_notCDom_reduced4SigExtra_T_18, 6, 0) node _notCDom_reduced4SigExtra_T_27 = shl(_notCDom_reduced4SigExtra_T_26, 1) node _notCDom_reduced4SigExtra_T_28 = xor(_notCDom_reduced4SigExtra_T_18, _notCDom_reduced4SigExtra_T_27) node _notCDom_reduced4SigExtra_T_29 = shr(_notCDom_reduced4SigExtra_T_25, 1) node _notCDom_reduced4SigExtra_T_30 = and(_notCDom_reduced4SigExtra_T_29, _notCDom_reduced4SigExtra_T_28) node _notCDom_reduced4SigExtra_T_31 = bits(_notCDom_reduced4SigExtra_T_25, 6, 0) node _notCDom_reduced4SigExtra_T_32 = shl(_notCDom_reduced4SigExtra_T_31, 1) node _notCDom_reduced4SigExtra_T_33 = not(_notCDom_reduced4SigExtra_T_28) node _notCDom_reduced4SigExtra_T_34 = and(_notCDom_reduced4SigExtra_T_32, _notCDom_reduced4SigExtra_T_33) node _notCDom_reduced4SigExtra_T_35 = or(_notCDom_reduced4SigExtra_T_30, _notCDom_reduced4SigExtra_T_34) node _notCDom_reduced4SigExtra_T_36 = bits(_notCDom_reduced4SigExtra_T_5, 12, 8) node _notCDom_reduced4SigExtra_T_37 = bits(_notCDom_reduced4SigExtra_T_36, 3, 0) node _notCDom_reduced4SigExtra_T_38 = bits(_notCDom_reduced4SigExtra_T_37, 1, 0) node _notCDom_reduced4SigExtra_T_39 = bits(_notCDom_reduced4SigExtra_T_38, 0, 0) node _notCDom_reduced4SigExtra_T_40 = bits(_notCDom_reduced4SigExtra_T_38, 1, 1) node _notCDom_reduced4SigExtra_T_41 = cat(_notCDom_reduced4SigExtra_T_39, _notCDom_reduced4SigExtra_T_40) node _notCDom_reduced4SigExtra_T_42 = bits(_notCDom_reduced4SigExtra_T_37, 3, 2) node _notCDom_reduced4SigExtra_T_43 = bits(_notCDom_reduced4SigExtra_T_42, 0, 0) node _notCDom_reduced4SigExtra_T_44 = bits(_notCDom_reduced4SigExtra_T_42, 1, 1) node _notCDom_reduced4SigExtra_T_45 = cat(_notCDom_reduced4SigExtra_T_43, _notCDom_reduced4SigExtra_T_44) node _notCDom_reduced4SigExtra_T_46 = cat(_notCDom_reduced4SigExtra_T_41, _notCDom_reduced4SigExtra_T_45) node _notCDom_reduced4SigExtra_T_47 = bits(_notCDom_reduced4SigExtra_T_36, 4, 4) node _notCDom_reduced4SigExtra_T_48 = cat(_notCDom_reduced4SigExtra_T_46, _notCDom_reduced4SigExtra_T_47) node _notCDom_reduced4SigExtra_T_49 = cat(_notCDom_reduced4SigExtra_T_35, _notCDom_reduced4SigExtra_T_48) node _notCDom_reduced4SigExtra_T_50 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_49) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_50) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 55, 54) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e11_s53_4( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [5:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [54:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [106:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [12:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [55:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [12:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [5:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [54:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [106:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire [7:0] _CDom_reduced4SigExtra_T_8 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_8 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_7 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_13 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_7 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_13 = 8'hF0; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_16 = 6'hF; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_16 = 6'hF; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_17 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_17 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_18 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_18 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_23 = 8'hCC; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_23 = 8'hCC; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_26 = 7'h33; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_26 = 7'h33; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_27 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_27 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_28 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_28 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_33 = 8'hAA; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_33 = 8'hAA; // @[primitives.scala:77:20] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [12:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [55:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [12:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [55:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[106]; // @[MulAddRecFN.scala:169:7, :192:32] wire [55:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 56'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [54:0] _sigSum_T_2 = _sigSum_T_1[54:0]; // @[MulAddRecFN.scala:193:47] wire [54:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [105:0] _sigSum_T_4 = io_mulAddResult_0[105:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [160:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [161:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [13:0] _GEN = {io_fromPreMul_sExpSum_0[12], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [13:0] _CDom_sExp_T_1 = _GEN - {{12{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [12:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[12:0]; // @[MulAddRecFN.scala:203:43] wire [12:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [107:0] _CDom_absSigSum_T = sigSum[161:54]; // @[MulAddRecFN.scala:192:12, :206:20] wire [107:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[54:53]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [104:0] _CDom_absSigSum_T_4 = sigSum[159:55]; // @[MulAddRecFN.scala:192:12, :210:23] wire [107:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [107:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [52:0] _CDom_absSigSumExtra_T = sigSum[53:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [52:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [53:0] _CDom_absSigSumExtra_T_3 = sigSum[54:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [57:0] CDom_mainSig = _CDom_mainSig_T[107:50]; // @[MulAddRecFN.scala:219:{24,56}] wire [52:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[52:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [54:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 2'h0}; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_7; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_8; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_9; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_10; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_11; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_12; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_13; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[27:24]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_7_T = _CDom_reduced4SigExtra_T_1[31:28]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_7_T_1 = \|_CDom_reduced4SigExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_7 = _CDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_8_T = _CDom_reduced4SigExtra_T_1[35:32]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_8_T_1 = \|_CDom_reduced4SigExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_8 = _CDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_9_T = _CDom_reduced4SigExtra_T_1[39:36]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_9_T_1 = \|_CDom_reduced4SigExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_9 = _CDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_10_T = _CDom_reduced4SigExtra_T_1[43:40]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_10_T_1 = \|_CDom_reduced4SigExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_10 = _CDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_11_T = _CDom_reduced4SigExtra_T_1[47:44]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_11_T_1 = \|_CDom_reduced4SigExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_11 = _CDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_12_T = _CDom_reduced4SigExtra_T_1[51:48]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_12_T_1 = \|_CDom_reduced4SigExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_12 = _CDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_13_T = _CDom_reduced4SigExtra_T_1[54:52]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_13_T_1 = \|_CDom_reduced4SigExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_13 = _CDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo_lo = {CDom_reduced4SigExtra_lo_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_lo_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_lo_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_lo_hi_hi, CDom_reduced4SigExtra_lo_hi_lo}; // @[primitives.scala:124:20] wire [6:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_lo_lo}; // @[primitives.scala:124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo_hi = {CDom_reduced4SigExtra_reducedVec_9, CDom_reduced4SigExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_hi_lo_hi, CDom_reduced4SigExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi_lo = {CDom_reduced4SigExtra_reducedVec_11, CDom_reduced4SigExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi_hi = {CDom_reduced4SigExtra_reducedVec_13, CDom_reduced4SigExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_hi_hi_hi, CDom_reduced4SigExtra_hi_hi_lo}; // @[primitives.scala:124:20] wire [6:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [13:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [3:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[5:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [3:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] CDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [12:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[13:1]; // @[primitives.scala:76:56, :78:22] wire [7:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_6[7:4]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_10 = {4'h0, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20, :120:54] wire [3:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:0]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_12 = {_CDom_reduced4SigExtra_T_11, 4'h0}; // @[primitives.scala:77:20, :120:54] wire [7:0] _CDom_reduced4SigExtra_T_14 = _CDom_reduced4SigExtra_T_12 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_15 = _CDom_reduced4SigExtra_T_10 \| _CDom_reduced4SigExtra_T_14; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_19 = _CDom_reduced4SigExtra_T_15[7:2]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_20 = {2'h0, _CDom_reduced4SigExtra_T_19 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_21 = _CDom_reduced4SigExtra_T_15[5:0]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_22 = {_CDom_reduced4SigExtra_T_21, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_24 = _CDom_reduced4SigExtra_T_22 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_25 = _CDom_reduced4SigExtra_T_20 \| _CDom_reduced4SigExtra_T_24; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_29 = _CDom_reduced4SigExtra_T_25[7:1]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_30 = {1'h0, _CDom_reduced4SigExtra_T_29 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_31 = _CDom_reduced4SigExtra_T_25[6:0]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_32 = {_CDom_reduced4SigExtra_T_31, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_34 = _CDom_reduced4SigExtra_T_32 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_35 = _CDom_reduced4SigExtra_T_30 \| _CDom_reduced4SigExtra_T_34; // @[primitives.scala:77:20] wire [4:0] _CDom_reduced4SigExtra_T_36 = _CDom_reduced4SigExtra_T_5[12:8]; // @[primitives.scala:77:20, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_37 = _CDom_reduced4SigExtra_T_36[3:0]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_38 = _CDom_reduced4SigExtra_T_37[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_39 = _CDom_reduced4SigExtra_T_38[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_40 = _CDom_reduced4SigExtra_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_41 = {_CDom_reduced4SigExtra_T_39, _CDom_reduced4SigExtra_T_40}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_42 = _CDom_reduced4SigExtra_T_37[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_43 = _CDom_reduced4SigExtra_T_42[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_44 = _CDom_reduced4SigExtra_T_42[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_45 = {_CDom_reduced4SigExtra_T_43, _CDom_reduced4SigExtra_T_44}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_46 = {_CDom_reduced4SigExtra_T_41, _CDom_reduced4SigExtra_T_45}; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_47 = _CDom_reduced4SigExtra_T_36[4]; // @[primitives.scala:77:20] wire [4:0] _CDom_reduced4SigExtra_T_48 = {_CDom_reduced4SigExtra_T_46, _CDom_reduced4SigExtra_T_47}; // @[primitives.scala:77:20] wire [12:0] _CDom_reduced4SigExtra_T_49 = {_CDom_reduced4SigExtra_T_35, _CDom_reduced4SigExtra_T_48}; // @[primitives.scala:77:20] wire [13:0] _CDom_reduced4SigExtra_T_50 = {1'h0, _CDom_reduced4SigExtra_T_2[12:0] & _CDom_reduced4SigExtra_T_49}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_50; // @[MulAddRecFN.scala:222:72, :223:73] wire [54:0] _CDom_sig_T = CDom_mainSig[57:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [55:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[109]; // @[MulAddRecFN.scala:192:12, :232:36] wire [108:0] _notCDom_absSigSum_T = sigSum[108:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [108:0] _notCDom_absSigSum_T_2 = sigSum[108:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [108:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [109:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {109'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [108:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[108:0]; // @[MulAddRecFN.scala:236:41] wire [108:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_26_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_27_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_28_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_29_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_30_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_31_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_32_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_33_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_34_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_35_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_36_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_37_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_38_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_39_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_40_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_41_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_42_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_43_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_44_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_45_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_46_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_47_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_48_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_49_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_50_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_51_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_52_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_53_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_54_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_26; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_27; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_28; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_29; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_30; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_31; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_32; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_33; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_34; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_35; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_36; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_37; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_38; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_39; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_40; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_41; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_42; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_43; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_44; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_45; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_46; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_47; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_48; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_49; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_50; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_51; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_52; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_53; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_54; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[51:50]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_26_T = notCDom_absSigSum[53:52]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_26_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_26 = _notCDom_reduced2AbsSigSum_reducedVec_26_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_27_T = notCDom_absSigSum[55:54]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_27_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_27 = _notCDom_reduced2AbsSigSum_reducedVec_27_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_28_T = notCDom_absSigSum[57:56]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_28_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_28 = _notCDom_reduced2AbsSigSum_reducedVec_28_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_29_T = notCDom_absSigSum[59:58]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_29_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_29 = _notCDom_reduced2AbsSigSum_reducedVec_29_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_30_T = notCDom_absSigSum[61:60]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_30_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_30 = _notCDom_reduced2AbsSigSum_reducedVec_30_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_31_T = notCDom_absSigSum[63:62]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_31_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_31 = _notCDom_reduced2AbsSigSum_reducedVec_31_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_32_T = notCDom_absSigSum[65:64]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_32_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_32 = _notCDom_reduced2AbsSigSum_reducedVec_32_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_33_T = notCDom_absSigSum[67:66]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_33_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_33 = _notCDom_reduced2AbsSigSum_reducedVec_33_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_34_T = notCDom_absSigSum[69:68]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_34_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_34 = _notCDom_reduced2AbsSigSum_reducedVec_34_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_35_T = notCDom_absSigSum[71:70]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_35_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_35 = _notCDom_reduced2AbsSigSum_reducedVec_35_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_36_T = notCDom_absSigSum[73:72]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_36_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_36 = _notCDom_reduced2AbsSigSum_reducedVec_36_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_37_T = notCDom_absSigSum[75:74]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_37_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_37 = _notCDom_reduced2AbsSigSum_reducedVec_37_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_38_T = notCDom_absSigSum[77:76]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_38_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_38 = _notCDom_reduced2AbsSigSum_reducedVec_38_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_39_T = notCDom_absSigSum[79:78]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_39_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_39 = _notCDom_reduced2AbsSigSum_reducedVec_39_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_40_T = notCDom_absSigSum[81:80]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_40_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_40 = _notCDom_reduced2AbsSigSum_reducedVec_40_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_41_T = notCDom_absSigSum[83:82]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_41_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_41 = _notCDom_reduced2AbsSigSum_reducedVec_41_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_42_T = notCDom_absSigSum[85:84]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_42_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_42 = _notCDom_reduced2AbsSigSum_reducedVec_42_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_43_T = notCDom_absSigSum[87:86]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_43_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_43 = _notCDom_reduced2AbsSigSum_reducedVec_43_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_44_T = notCDom_absSigSum[89:88]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_44_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_44 = _notCDom_reduced2AbsSigSum_reducedVec_44_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_45_T = notCDom_absSigSum[91:90]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_45_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_45 = _notCDom_reduced2AbsSigSum_reducedVec_45_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_46_T = notCDom_absSigSum[93:92]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_46_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_46 = _notCDom_reduced2AbsSigSum_reducedVec_46_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_47_T = notCDom_absSigSum[95:94]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_47_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_47 = _notCDom_reduced2AbsSigSum_reducedVec_47_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_48_T = notCDom_absSigSum[97:96]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_48_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_48 = _notCDom_reduced2AbsSigSum_reducedVec_48_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_49_T = notCDom_absSigSum[99:98]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_49_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_49 = _notCDom_reduced2AbsSigSum_reducedVec_49_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_50_T = notCDom_absSigSum[101:100]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_50_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_50 = _notCDom_reduced2AbsSigSum_reducedVec_50_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_51_T = notCDom_absSigSum[103:102]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_51_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_51 = _notCDom_reduced2AbsSigSum_reducedVec_51_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_52_T = notCDom_absSigSum[105:104]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_52_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_52 = _notCDom_reduced2AbsSigSum_reducedVec_52_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_53_T = notCDom_absSigSum[107:106]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_53_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_53 = _notCDom_reduced2AbsSigSum_reducedVec_53_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_54_T = notCDom_absSigSum[108]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_54_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_54 = _notCDom_reduced2AbsSigSum_reducedVec_54_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_17, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_19, notCDom_reduced2AbsSigSum_reducedVec_18}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_22, notCDom_reduced2AbsSigSum_reducedVec_21}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_24, notCDom_reduced2AbsSigSum_reducedVec_23}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_26, notCDom_reduced2AbsSigSum_reducedVec_25}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [13:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [26:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_29, notCDom_reduced2AbsSigSum_reducedVec_28}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_27}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_31, notCDom_reduced2AbsSigSum_reducedVec_30}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_33, notCDom_reduced2AbsSigSum_reducedVec_32}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_36, notCDom_reduced2AbsSigSum_reducedVec_35}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_34}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_38, notCDom_reduced2AbsSigSum_reducedVec_37}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_40, notCDom_reduced2AbsSigSum_reducedVec_39}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_lo}; // @[primitives.scala:107:20] wire [13:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_43, notCDom_reduced2AbsSigSum_reducedVec_42}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_41}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_45, notCDom_reduced2AbsSigSum_reducedVec_44}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_47, notCDom_reduced2AbsSigSum_reducedVec_46}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_50, notCDom_reduced2AbsSigSum_reducedVec_49}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_48}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_52, notCDom_reduced2AbsSigSum_reducedVec_51}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_54, notCDom_reduced2AbsSigSum_reducedVec_53}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [13:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [27:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [54:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_26 = notCDom_reduced2AbsSigSum[26]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_27 = notCDom_reduced2AbsSigSum[27]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_28 = notCDom_reduced2AbsSigSum[28]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_29 = notCDom_reduced2AbsSigSum[29]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_30 = notCDom_reduced2AbsSigSum[30]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_31 = notCDom_reduced2AbsSigSum[31]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_32 = notCDom_reduced2AbsSigSum[32]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_33 = notCDom_reduced2AbsSigSum[33]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_34 = notCDom_reduced2AbsSigSum[34]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_35 = notCDom_reduced2AbsSigSum[35]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_36 = notCDom_reduced2AbsSigSum[36]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_37 = notCDom_reduced2AbsSigSum[37]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_38 = notCDom_reduced2AbsSigSum[38]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_39 = notCDom_reduced2AbsSigSum[39]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_40 = notCDom_reduced2AbsSigSum[40]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_41 = notCDom_reduced2AbsSigSum[41]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_42 = notCDom_reduced2AbsSigSum[42]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_43 = notCDom_reduced2AbsSigSum[43]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_44 = notCDom_reduced2AbsSigSum[44]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_45 = notCDom_reduced2AbsSigSum[45]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_46 = notCDom_reduced2AbsSigSum[46]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_47 = notCDom_reduced2AbsSigSum[47]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_48 = notCDom_reduced2AbsSigSum[48]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_49 = notCDom_reduced2AbsSigSum[49]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_50 = notCDom_reduced2AbsSigSum[50]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_51 = notCDom_reduced2AbsSigSum[51]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_52 = notCDom_reduced2AbsSigSum[52]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_53 = notCDom_reduced2AbsSigSum[53]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_54 = notCDom_reduced2AbsSigSum[54]; // @[primitives.scala:91:52, :107:20] wire [5:0] _notCDom_normDistReduced2_T_55 = _notCDom_normDistReduced2_T_1 ? 6'h35 : 6'h36; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_56 = _notCDom_normDistReduced2_T_2 ? 6'h34 : _notCDom_normDistReduced2_T_55; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_57 = _notCDom_normDistReduced2_T_3 ? 6'h33 : _notCDom_normDistReduced2_T_56; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_58 = _notCDom_normDistReduced2_T_4 ? 6'h32 : _notCDom_normDistReduced2_T_57; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_59 = _notCDom_normDistReduced2_T_5 ? 6'h31 : _notCDom_normDistReduced2_T_58; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_60 = _notCDom_normDistReduced2_T_6 ? 6'h30 : _notCDom_normDistReduced2_T_59; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_61 = _notCDom_normDistReduced2_T_7 ? 6'h2F : _notCDom_normDistReduced2_T_60; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_62 = _notCDom_normDistReduced2_T_8 ? 6'h2E : _notCDom_normDistReduced2_T_61; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_63 = _notCDom_normDistReduced2_T_9 ? 6'h2D : _notCDom_normDistReduced2_T_62; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_64 = _notCDom_normDistReduced2_T_10 ? 6'h2C : _notCDom_normDistReduced2_T_63; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_65 = _notCDom_normDistReduced2_T_11 ? 6'h2B : _notCDom_normDistReduced2_T_64; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_66 = _notCDom_normDistReduced2_T_12 ? 6'h2A : _notCDom_normDistReduced2_T_65; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_67 = _notCDom_normDistReduced2_T_13 ? 6'h29 : _notCDom_normDistReduced2_T_66; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_68 = _notCDom_normDistReduced2_T_14 ? 6'h28 : _notCDom_normDistReduced2_T_67; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_69 = _notCDom_normDistReduced2_T_15 ? 6'h27 : _notCDom_normDistReduced2_T_68; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_70 = _notCDom_normDistReduced2_T_16 ? 6'h26 : _notCDom_normDistReduced2_T_69; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_71 = _notCDom_normDistReduced2_T_17 ? 6'h25 : _notCDom_normDistReduced2_T_70; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_72 = _notCDom_normDistReduced2_T_18 ? 6'h24 : _notCDom_normDistReduced2_T_71; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_73 = _notCDom_normDistReduced2_T_19 ? 6'h23 : _notCDom_normDistReduced2_T_72; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_74 = _notCDom_normDistReduced2_T_20 ? 6'h22 : _notCDom_normDistReduced2_T_73; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_75 = _notCDom_normDistReduced2_T_21 ? 6'h21 : _notCDom_normDistReduced2_T_74; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_76 = _notCDom_normDistReduced2_T_22 ? 6'h20 : _notCDom_normDistReduced2_T_75; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_77 = _notCDom_normDistReduced2_T_23 ? 6'h1F : _notCDom_normDistReduced2_T_76; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_78 = _notCDom_normDistReduced2_T_24 ? 6'h1E : _notCDom_normDistReduced2_T_77; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_79 = _notCDom_normDistReduced2_T_25 ? 6'h1D : _notCDom_normDistReduced2_T_78; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_80 = _notCDom_normDistReduced2_T_26 ? 6'h1C : _notCDom_normDistReduced2_T_79; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_81 = _notCDom_normDistReduced2_T_27 ? 6'h1B : _notCDom_normDistReduced2_T_80; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_82 = _notCDom_normDistReduced2_T_28 ? 6'h1A : _notCDom_normDistReduced2_T_81; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_83 = _notCDom_normDistReduced2_T_29 ? 6'h19 : _notCDom_normDistReduced2_T_82; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_84 = _notCDom_normDistReduced2_T_30 ? 6'h18 : _notCDom_normDistReduced2_T_83; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_85 = _notCDom_normDistReduced2_T_31 ? 6'h17 : _notCDom_normDistReduced2_T_84; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_86 = _notCDom_normDistReduced2_T_32 ? 6'h16 : _notCDom_normDistReduced2_T_85; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_87 = _notCDom_normDistReduced2_T_33 ? 6'h15 : _notCDom_normDistReduced2_T_86; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_88 = _notCDom_normDistReduced2_T_34 ? 6'h14 : _notCDom_normDistReduced2_T_87; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_89 = _notCDom_normDistReduced2_T_35 ? 6'h13 : _notCDom_normDistReduced2_T_88; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_90 = _notCDom_normDistReduced2_T_36 ? 6'h12 : _notCDom_normDistReduced2_T_89; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_91 = _notCDom_normDistReduced2_T_37 ? 6'h11 : _notCDom_normDistReduced2_T_90; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_92 = _notCDom_normDistReduced2_T_38 ? 6'h10 : _notCDom_normDistReduced2_T_91; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_93 = _notCDom_normDistReduced2_T_39 ? 6'hF : _notCDom_normDistReduced2_T_92; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_94 = _notCDom_normDistReduced2_T_40 ? 6'hE : _notCDom_normDistReduced2_T_93; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_95 = _notCDom_normDistReduced2_T_41 ? 6'hD : _notCDom_normDistReduced2_T_94; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_96 = _notCDom_normDistReduced2_T_42 ? 6'hC : _notCDom_normDistReduced2_T_95; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_97 = _notCDom_normDistReduced2_T_43 ? 6'hB : _notCDom_normDistReduced2_T_96; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_98 = _notCDom_normDistReduced2_T_44 ? 6'hA : _notCDom_normDistReduced2_T_97; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_99 = _notCDom_normDistReduced2_T_45 ? 6'h9 : _notCDom_normDistReduced2_T_98; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_100 = _notCDom_normDistReduced2_T_46 ? 6'h8 : _notCDom_normDistReduced2_T_99; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_101 = _notCDom_normDistReduced2_T_47 ? 6'h7 : _notCDom_normDistReduced2_T_100; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_102 = _notCDom_normDistReduced2_T_48 ? 6'h6 : _notCDom_normDistReduced2_T_101; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_103 = _notCDom_normDistReduced2_T_49 ? 6'h5 : _notCDom_normDistReduced2_T_102; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_104 = _notCDom_normDistReduced2_T_50 ? 6'h4 : _notCDom_normDistReduced2_T_103; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_105 = _notCDom_normDistReduced2_T_51 ? 6'h3 : _notCDom_normDistReduced2_T_104; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_106 = _notCDom_normDistReduced2_T_52 ? 6'h2 : _notCDom_normDistReduced2_T_105; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_107 = _notCDom_normDistReduced2_T_53 ? 6'h1 : _notCDom_normDistReduced2_T_106; // @[Mux.scala:50:70] wire [5:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_54 ? 6'h0 : _notCDom_normDistReduced2_T_107; // @[Mux.scala:50:70] wire [6:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [7:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [13:0] _notCDom_sExp_T_1 = _GEN - {{6{_notCDom_sExp_T[7]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [12:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[12:0]; // @[MulAddRecFN.scala:241:46] wire [12:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [235:0] _notCDom_mainSig_T = {127'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [57:0] notCDom_mainSig = _notCDom_mainSig_T[109:52]; // @[MulAddRecFN.scala:243:{27,50}] wire [26:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[26:0]; // @[primitives.scala:107:20] wire [26:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_13; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_7_T = _notCDom_reduced4SigExtra_T_1[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_7_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_7 = _notCDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_8_T = _notCDom_reduced4SigExtra_T_1[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_8_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_8 = _notCDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_9_T = _notCDom_reduced4SigExtra_T_1[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_9_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_9 = _notCDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_10_T = _notCDom_reduced4SigExtra_T_1[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_10_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_10 = _notCDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_11_T = _notCDom_reduced4SigExtra_T_1[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_11_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_11 = _notCDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_12_T = _notCDom_reduced4SigExtra_T_1[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_12_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_12 = _notCDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_13_T = _notCDom_reduced4SigExtra_T_1[26]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_13_T_1 = _notCDom_reduced4SigExtra_reducedVec_13_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_13 = _notCDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo_lo = {notCDom_reduced4SigExtra_lo_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_lo_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_lo_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_lo_hi_hi, notCDom_reduced4SigExtra_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo_hi = {notCDom_reduced4SigExtra_reducedVec_9, notCDom_reduced4SigExtra_reducedVec_8}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_hi_lo_hi, notCDom_reduced4SigExtra_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi_lo = {notCDom_reduced4SigExtra_reducedVec_11, notCDom_reduced4SigExtra_reducedVec_10}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi_hi = {notCDom_reduced4SigExtra_reducedVec_13, notCDom_reduced4SigExtra_reducedVec_12}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_hi_hi_hi, notCDom_reduced4SigExtra_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [13:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [4:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[5:1]; // @[Mux.scala:50:70] wire [4:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [32:0] notCDom_reduced4SigExtra_shift = $signed(33'sh100000000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [12:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[13:1]; // @[primitives.scala:76:56, :78:22] wire [7:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_6[7:4]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_10 = {4'h0, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20, :120:54] wire [3:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:0]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_12 = {_notCDom_reduced4SigExtra_T_11, 4'h0}; // @[primitives.scala:77:20, :120:54] wire [7:0] _notCDom_reduced4SigExtra_T_14 = _notCDom_reduced4SigExtra_T_12 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_15 = _notCDom_reduced4SigExtra_T_10 \| _notCDom_reduced4SigExtra_T_14; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_19 = _notCDom_reduced4SigExtra_T_15[7:2]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_20 = {2'h0, _notCDom_reduced4SigExtra_T_19 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_21 = _notCDom_reduced4SigExtra_T_15[5:0]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_22 = {_notCDom_reduced4SigExtra_T_21, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_24 = _notCDom_reduced4SigExtra_T_22 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_25 = _notCDom_reduced4SigExtra_T_20 \| _notCDom_reduced4SigExtra_T_24; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_29 = _notCDom_reduced4SigExtra_T_25[7:1]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_30 = {1'h0, _notCDom_reduced4SigExtra_T_29 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_31 = _notCDom_reduced4SigExtra_T_25[6:0]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_32 = {_notCDom_reduced4SigExtra_T_31, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_34 = _notCDom_reduced4SigExtra_T_32 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_35 = _notCDom_reduced4SigExtra_T_30 \| _notCDom_reduced4SigExtra_T_34; // @[primitives.scala:77:20] wire [4:0] _notCDom_reduced4SigExtra_T_36 = _notCDom_reduced4SigExtra_T_5[12:8]; // @[primitives.scala:77:20, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_37 = _notCDom_reduced4SigExtra_T_36[3:0]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_38 = _notCDom_reduced4SigExtra_T_37[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_39 = _notCDom_reduced4SigExtra_T_38[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_40 = _notCDom_reduced4SigExtra_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_41 = {_notCDom_reduced4SigExtra_T_39, _notCDom_reduced4SigExtra_T_40}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_42 = _notCDom_reduced4SigExtra_T_37[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_43 = _notCDom_reduced4SigExtra_T_42[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_44 = _notCDom_reduced4SigExtra_T_42[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_45 = {_notCDom_reduced4SigExtra_T_43, _notCDom_reduced4SigExtra_T_44}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_46 = {_notCDom_reduced4SigExtra_T_41, _notCDom_reduced4SigExtra_T_45}; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_47 = _notCDom_reduced4SigExtra_T_36[4]; // @[primitives.scala:77:20] wire [4:0] _notCDom_reduced4SigExtra_T_48 = {_notCDom_reduced4SigExtra_T_46, _notCDom_reduced4SigExtra_T_47}; // @[primitives.scala:77:20] wire [12:0] _notCDom_reduced4SigExtra_T_49 = {_notCDom_reduced4SigExtra_T_35, _notCDom_reduced4SigExtra_T_48}; // @[primitives.scala:77:20] wire [13:0] _notCDom_reduced4SigExtra_T_50 = {1'h0, _notCDom_reduced4SigExtra_T_2[12:0] & _notCDom_reduced4SigExtra_T_49}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_50; // @[MulAddRecFN.scala:247:78, :249:11] wire [54:0] _notCDom_sig_T = notCDom_mainSig[57:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [55:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[55:54]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[MulAddRecFN.scala:222:53, :255:{21,50}] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 \| _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PTW : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<36>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<48>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<49>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<49>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<49>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<48>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) wire l2_refill_wire : UInt<1> inst arb of Arbiter2_Valid_PTWReq connect arb.clock, clock connect arb.reset, reset connect arb.io.in[0], io.requestor[0].req connect arb.io.in[1], io.requestor[1].req node _arb_io_out_ready_T = eq(state, UInt<3>(0h0)) node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0)) node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1) connect arb.io.out.ready, _arb_io_out_ready_T_2 wire _resp_valid_WIRE : UInt<1>[2] connect _resp_valid_WIRE[0], UInt<1>(0h0) connect _resp_valid_WIRE[1], UInt<1>(0h0) reg resp_valid : UInt<1>[2], clock connect resp_valid, _resp_valid_WIRE node _clock_en_T = neq(state, UInt<3>(0h0)) node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire) node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid) node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid) node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0) node clock_en = or(_clock_en_T_3, _clock_en_T_4) node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en) connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T reg invalidated : UInt<1>, clock reg count : UInt<2>, clock reg resp_ae_ptw : UInt<1>, clock reg resp_ae_final : UInt<1>, clock reg resp_pf : UInt<1>, clock reg resp_gf : UInt<1>, clock reg resp_hr : UInt<1>, clock reg resp_hw : UInt<1>, clock reg resp_hx : UInt<1>, clock reg resp_fragmented_superpage : UInt<1>, clock reg r_req : { addr : UInt<36>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock reg r_req_dest : UInt, clock reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg aux_count : UInt<2>, clock reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg gpa_pgoff : UInt<12>, clock reg stage2 : UInt<1>, clock reg stage2_final : UInt<1>, clock node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) node _r_hgatp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1) node _r_hgatp_initial_count_T_2 = bits(r_hgatp.mode, 0, 0) node _r_hgatp_initial_count_T_3 = sub(_r_hgatp_initial_count_T_1, _r_hgatp_initial_count_T_2) node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_3, 1) node do_both_stages = and(r_req.vstage1, r_req.stage2) node _max_count_T = lt(count, aux_count) node max_count = mux(_max_count_T, aux_count, count) node _vpn_T = and(r_req.vstage1, stage2) node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr) reg mem_resp_valid : UInt<1>, clock connect mem_resp_valid, io.mem.resp.valid reg mem_resp_data : UInt, clock connect mem_resp_data, io.mem.resp.bits.data wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} wire _tmp_WIRE : UInt<64> connect _tmp_WIRE, mem_resp_data node _tmp_T = bits(_tmp_WIRE, 0, 0) connect tmp.v, _tmp_T node _tmp_T_1 = bits(_tmp_WIRE, 1, 1) connect tmp.r, _tmp_T_1 node _tmp_T_2 = bits(_tmp_WIRE, 2, 2) connect tmp.w, _tmp_T_2 node _tmp_T_3 = bits(_tmp_WIRE, 3, 3) connect tmp.x, _tmp_T_3 node _tmp_T_4 = bits(_tmp_WIRE, 4, 4) connect tmp.u, _tmp_T_4 node _tmp_T_5 = bits(_tmp_WIRE, 5, 5) connect tmp.g, _tmp_T_5 node _tmp_T_6 = bits(_tmp_WIRE, 6, 6) connect tmp.a, _tmp_T_6 node _tmp_T_7 = bits(_tmp_WIRE, 7, 7) connect tmp.d, _tmp_T_7 node _tmp_T_8 = bits(_tmp_WIRE, 9, 8) connect tmp.reserved_for_software, _tmp_T_8 node _tmp_T_9 = bits(_tmp_WIRE, 53, 10) connect tmp.ppn, _tmp_T_9 node _tmp_T_10 = bits(_tmp_WIRE, 63, 54) connect tmp.reserved_for_future, _tmp_T_10 wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect pte, tmp node _res_ppn_T = eq(stage2, UInt<1>(0h0)) node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T) node _res_ppn_T_2 = bits(tmp.ppn, 35, 0) node _res_ppn_T_3 = bits(tmp.ppn, 19, 0) node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3) connect pte.ppn, _res_ppn_T_4 node _T = or(tmp.r, tmp.w) node _T_1 = or(_T, tmp.x) when _T_1 : node _T_2 = leq(count, UInt<1>(0h0)) node _T_3 = bits(tmp.ppn, 26, 18) node _T_4 = neq(_T_3, UInt<1>(0h0)) node _T_5 = and(_T_2, _T_4) when _T_5 : connect pte.v, UInt<1>(0h0) node _T_6 = leq(count, UInt<1>(0h1)) node _T_7 = bits(tmp.ppn, 17, 9) node _T_8 = neq(_T_7, UInt<1>(0h0)) node _T_9 = and(_T_6, _T_8) when _T_9 : connect pte.v, UInt<1>(0h0) node _T_10 = leq(count, UInt<2>(0h2)) node _T_11 = bits(tmp.ppn, 8, 0) node _T_12 = neq(_T_11, UInt<1>(0h0)) node _T_13 = and(_T_10, _T_12) when _T_13 : connect pte.v, UInt<1>(0h0) node _T_14 = eq(stage2, UInt<1>(0h0)) node _T_15 = and(do_both_stages, _T_14) node _T_16 = shr(tmp.ppn, 36) node _T_17 = neq(_T_16, UInt<1>(0h0)) node _T_18 = shr(tmp.ppn, 20) node _T_19 = neq(_T_18, UInt<1>(0h0)) node invalid_paddr = mux(_T_15, _T_17, _T_19) node _T_20 = eq(stage2, UInt<1>(0h0)) node _T_21 = and(do_both_stages, _T_20) node _count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _count_T_1 = tail(_count_T, 1) node _count_T_2 = bits(r_hgatp.mode, 0, 0) node _count_T_3 = sub(_count_T_1, _count_T_2) node count_1 = tail(_count_T_3, 1) node idxs_0 = shr(tmp.ppn, 38) node idxs_1 = shr(tmp.ppn, 29) wire _WIRE : UInt<15>[2] connect _WIRE[0], idxs_0 connect _WIRE[1], idxs_1 node _T_22 = or(count_1, UInt<1>(0h0)) node _T_23 = bits(_T_22, 0, 0) node _T_24 = neq(_WIRE[_T_23], UInt<1>(0h0)) node invalid_gpa = and(_T_21, _T_24) node _traverse_T = eq(pte.r, UInt<1>(0h0)) node _traverse_T_1 = and(pte.v, _traverse_T) node _traverse_T_2 = eq(pte.w, UInt<1>(0h0)) node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2) node _traverse_T_4 = eq(pte.x, UInt<1>(0h0)) node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4) node _traverse_T_6 = eq(pte.d, UInt<1>(0h0)) node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6) node _traverse_T_8 = eq(pte.a, UInt<1>(0h0)) node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8) node _traverse_T_10 = eq(pte.u, UInt<1>(0h0)) node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10) node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12) node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0)) node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14) node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0)) node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16) node _traverse_T_18 = lt(count, UInt<2>(0h3)) node traverse = and(_traverse_T_17, _traverse_T_18) node _pte_addr_vpn_idxs_T = shr(vpn, 27) node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0) node _pte_addr_vpn_idxs_T_1 = shr(vpn, 18) node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0) node _pte_addr_vpn_idxs_T_2 = shr(vpn, 9) node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0) node _pte_addr_vpn_idxs_T_3 = shr(vpn, 0) node pte_addr_vpn_idxs_3 = bits(_pte_addr_vpn_idxs_T_3, 8, 0) node _pte_addr_mask_T = eq(count, r_hgatp_initial_count) node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T) node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff)) node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1)) node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0) node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2)) node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1) node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3)) node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_3, _pte_addr_vpn_idx_T_3) node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask) node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9) node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx) node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3) node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) regreset valid : UInt<8>, clock, reset, UInt<8>(0h0) reg tags : UInt<32>[8], clock reg data : UInt<20>[8], clock node _can_hit_T = lt(count, UInt<2>(0h3)) node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0)) node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1) node can_hit = and(_can_hit_T, _can_hit_T_2) node tag = cat(r_req.vstage1, pte_addr) node _hits_T = eq(tags[0], tag) node _hits_T_1 = eq(tags[1], tag) node _hits_T_2 = eq(tags[2], tag) node _hits_T_3 = eq(tags[3], tag) node _hits_T_4 = eq(tags[4], tag) node _hits_T_5 = eq(tags[5], tag) node _hits_T_6 = eq(tags[6], tag) node _hits_T_7 = eq(tags[7], tag) node hits_lo_lo = cat(_hits_T_1, _hits_T) node hits_lo_hi = cat(_hits_T_3, _hits_T_2) node hits_lo = cat(hits_lo_hi, hits_lo_lo) node hits_hi_lo = cat(_hits_T_5, _hits_T_4) node hits_hi_hi = cat(_hits_T_7, _hits_T_6) node hits_hi = cat(hits_hi_hi, hits_hi_lo) node _hits_T_8 = cat(hits_hi, hits_lo) node hits = and(_hits_T_8, valid) node _hit_T = orr(hits) node pte_cache_hit = and(_hit_T, can_hit) node _T_25 = and(mem_resp_valid, traverse) node _T_26 = and(_T_25, can_hit) node _T_27 = orr(hits) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = and(_T_26, _T_28) node _T_30 = eq(invalidated, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : node _r_T = andr(valid) node r_left_subtree_older = bits(state_reg, 6, 6) node r_left_subtree_state = bits(state_reg, 5, 3) node r_right_subtree_state = bits(state_reg, 2, 0) node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2) node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1) node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0) node _r_T_1 = bits(r_left_subtree_state_1, 0, 0) node _r_T_2 = bits(r_right_subtree_state_1, 0, 0) node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2) node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3) node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2) node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1) node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0) node _r_T_5 = bits(r_left_subtree_state_2, 0, 0) node _r_T_6 = bits(r_right_subtree_state_2, 0, 0) node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6) node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7) node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8) node _r_T_10 = cat(r_left_subtree_older, _r_T_9) node _r_T_11 = not(valid) node _r_T_12 = bits(_r_T_11, 0, 0) node _r_T_13 = bits(_r_T_11, 1, 1) node _r_T_14 = bits(_r_T_11, 2, 2) node _r_T_15 = bits(_r_T_11, 3, 3) node _r_T_16 = bits(_r_T_11, 4, 4) node _r_T_17 = bits(_r_T_11, 5, 5) node _r_T_18 = bits(_r_T_11, 6, 6) node _r_T_19 = bits(_r_T_11, 7, 7) node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20) node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21) node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22) node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23) node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24) node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25) node r = mux(_r_T, _r_T_10, _r_T_26) node _valid_T = dshl(UInt<1>(0h1), r) node _valid_T_1 = or(valid, _valid_T) connect valid, _valid_T_1 connect tags[r], tag connect data[r], pte.ppn node state_reg_touch_way_sized = bits(r, 2, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg, 5, 3) node state_reg_right_subtree_state = bits(state_reg, 2, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1) node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1) node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0)) node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3) node _state_reg_T_5 = bits(_state_reg_T, 0, 0) node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0) node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0)) node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1) node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4) node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8) node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9) node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1) node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1) node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0) node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0) node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0)) node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14) node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0) node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0)) node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2) node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15) node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19) node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state) node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10) node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21) connect state_reg, _state_reg_T_22 node _T_32 = eq(state, UInt<3>(0h1)) node _T_33 = and(pte_cache_hit, _T_32) when _T_33 : node hi = bits(hits, 7, 4) node lo = bits(hits, 3, 0) node _T_34 = orr(hi) node _T_35 = or(hi, lo) node hi_1 = bits(_T_35, 3, 2) node lo_1 = bits(_T_35, 1, 0) node _T_36 = orr(hi_1) node _T_37 = or(hi_1, lo_1) node _T_38 = bits(_T_37, 1, 1) node _T_39 = cat(_T_36, _T_38) node _T_40 = cat(_T_34, _T_39) node state_reg_touch_way_sized_1 = bits(_T_40, 2, 0) node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2) node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3) node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0) node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0) node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1) node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0)) node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1) node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0) node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0) node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0)) node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26) node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0) node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0)) node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4) node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27) node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31) node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32) node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0) node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1) node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0)) node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1) node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0) node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0) node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0) node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0)) node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37) node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0) node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0) node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0)) node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5) node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38) node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42) node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3) node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33) node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44) connect state_reg, _state_reg_T_45 node _T_41 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) node _T_42 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _T_43 = or(_T_41, _T_42) node _T_44 = and(io.dpath.sfence.valid, _T_43) when _T_44 : connect valid, UInt<1>(0h0) node _T_45 = eq(state, UInt<3>(0h1)) node _T_46 = and(pte_cache_hit, _T_45) node _T_47 = eq(count, UInt<1>(0h0)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(state, UInt<3>(0h1)) node _T_50 = and(pte_cache_hit, _T_49) node _T_51 = eq(count, UInt<1>(0h1)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(state, UInt<3>(0h1)) node _T_54 = and(pte_cache_hit, _T_53) node _T_55 = eq(count, UInt<2>(0h2)) node _T_56 = and(_T_54, _T_55) node _T_57 = bits(hits, 0, 0) node _T_58 = bits(hits, 1, 1) node _T_59 = bits(hits, 2, 2) node _T_60 = bits(hits, 3, 3) node _T_61 = bits(hits, 4, 4) node _T_62 = bits(hits, 5, 5) node _T_63 = bits(hits, 6, 6) node _T_64 = bits(hits, 7, 7) node _T_65 = mux(_T_57, data[0], UInt<1>(0h0)) node _T_66 = mux(_T_58, data[1], UInt<1>(0h0)) node _T_67 = mux(_T_59, data[2], UInt<1>(0h0)) node _T_68 = mux(_T_60, data[3], UInt<1>(0h0)) node _T_69 = mux(_T_61, data[4], UInt<1>(0h0)) node _T_70 = mux(_T_62, data[5], UInt<1>(0h0)) node _T_71 = mux(_T_63, data[6], UInt<1>(0h0)) node _T_72 = mux(_T_64, data[7], UInt<1>(0h0)) node _T_73 = or(_T_65, _T_66) node _T_74 = or(_T_73, _T_67) node _T_75 = or(_T_74, _T_68) node _T_76 = or(_T_75, _T_69) node _T_77 = or(_T_76, _T_70) node _T_78 = or(_T_77, _T_71) node _T_79 = or(_T_78, _T_72) wire pte_cache_data : UInt<20> connect pte_cache_data, _T_79 regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0) regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0) reg tags_1 : UInt<32>[8], clock reg data_1 : UInt<20>[8], clock node _can_hit_T_3 = eq(count, r_hgatp_initial_count) node _can_hit_T_4 = lt(aux_count, UInt<2>(0h3)) node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4) node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1) node _can_hit_T_7 = and(_can_hit_T_6, stage2) node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0)) node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8) node _can_refill_T = eq(stage2, UInt<1>(0h0)) node _can_refill_T_1 = and(do_both_stages, _can_refill_T) node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0)) node can_refill = and(_can_refill_T_1, _can_refill_T_2) node _tag_T = cat(UInt<47>(0h0), UInt<1>(0h0)) node tag_1 = cat(UInt<1>(0h1), _tag_T) node _hits_T_9 = eq(tags_1[0], tag_1) node _hits_T_10 = eq(tags_1[1], tag_1) node _hits_T_11 = eq(tags_1[2], tag_1) node _hits_T_12 = eq(tags_1[3], tag_1) node _hits_T_13 = eq(tags_1[4], tag_1) node _hits_T_14 = eq(tags_1[5], tag_1) node _hits_T_15 = eq(tags_1[6], tag_1) node _hits_T_16 = eq(tags_1[7], tag_1) node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9) node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11) node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1) node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13) node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15) node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1) node _hits_T_17 = cat(hits_hi_1, hits_lo_1) node hits_1 = and(_hits_T_17, valid_1) node _hit_T_1 = orr(hits_1) node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1) node _T_80 = and(mem_resp_valid, traverse) node _T_81 = and(_T_80, can_refill) node _T_82 = orr(hits_1) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = and(_T_81, _T_83) node _T_85 = eq(invalidated, UInt<1>(0h0)) node _T_86 = and(_T_84, _T_85) when _T_86 : node _r_T_27 = andr(valid_1) node r_left_subtree_older_3 = bits(state_reg_1, 6, 6) node r_left_subtree_state_3 = bits(state_reg_1, 5, 3) node r_right_subtree_state_3 = bits(state_reg_1, 2, 0) node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2) node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1) node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0) node _r_T_28 = bits(r_left_subtree_state_4, 0, 0) node _r_T_29 = bits(r_right_subtree_state_4, 0, 0) node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29) node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30) node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2) node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1) node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0) node _r_T_32 = bits(r_left_subtree_state_5, 0, 0) node _r_T_33 = bits(r_right_subtree_state_5, 0, 0) node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33) node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34) node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35) node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36) node _r_T_38 = not(valid_1) node _r_T_39 = bits(_r_T_38, 0, 0) node _r_T_40 = bits(_r_T_38, 1, 1) node _r_T_41 = bits(_r_T_38, 2, 2) node _r_T_42 = bits(_r_T_38, 3, 3) node _r_T_43 = bits(_r_T_38, 4, 4) node _r_T_44 = bits(_r_T_38, 5, 5) node _r_T_45 = bits(_r_T_38, 6, 6) node _r_T_46 = bits(_r_T_38, 7, 7) node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7)) node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47) node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48) node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49) node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50) node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51) node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52) node r_1 = mux(_r_T_27, _r_T_37, _r_T_53) node _valid_T_2 = dshl(UInt<1>(0h1), r_1) node _valid_T_3 = or(valid_1, _valid_T_2) connect valid_1, _valid_T_3 connect tags_1[r_1], tag_1 connect data_1[r_1], pte.ppn node state_reg_touch_way_sized_2 = bits(r_1, 2, 0) node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2) node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0)) node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3) node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0) node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0) node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1) node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0)) node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1) node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0) node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0) node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0)) node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49) node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0) node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0)) node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7) node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50) node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54) node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55) node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0) node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1) node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0)) node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1) node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0) node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0) node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0)) node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60) node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0) node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0)) node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8) node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61) node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65) node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6) node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56) node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67) connect state_reg_1, _state_reg_T_68 node _T_87 = eq(state, UInt<3>(0h1)) node _T_88 = and(stage2_pte_cache_hit, _T_87) when _T_88 : node hi_2 = bits(hits_1, 7, 4) node lo_2 = bits(hits_1, 3, 0) node _T_89 = orr(hi_2) node _T_90 = or(hi_2, lo_2) node hi_3 = bits(_T_90, 3, 2) node lo_3 = bits(_T_90, 1, 0) node _T_91 = orr(hi_3) node _T_92 = or(hi_3, lo_3) node _T_93 = bits(_T_92, 1, 1) node _T_94 = cat(_T_91, _T_93) node _T_95 = cat(_T_89, _T_94) node state_reg_touch_way_sized_3 = bits(_T_95, 2, 0) node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2) node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0)) node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3) node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0) node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0) node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1) node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0)) node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1) node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0) node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0) node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0) node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0)) node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72) node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0) node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0) node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0)) node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10) node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73) node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77) node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78) node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0) node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1) node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0)) node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1) node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0) node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0) node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0) node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0)) node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83) node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0) node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0) node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0)) node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11) node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84) node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88) node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9) node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79) node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90) connect state_reg_1, _state_reg_T_91 node _T_96 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) node _T_97 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _T_98 = or(_T_96, _T_97) node _T_99 = and(io.dpath.sfence.valid, _T_98) when _T_99 : connect valid_1, UInt<1>(0h0) node _T_100 = eq(state, UInt<3>(0h1)) node _T_101 = and(stage2_pte_cache_hit, _T_100) node _T_102 = eq(aux_count, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(state, UInt<3>(0h1)) node _T_105 = and(stage2_pte_cache_hit, _T_104) node _T_106 = eq(aux_count, UInt<1>(0h1)) node _T_107 = and(_T_105, _T_106) node _T_108 = eq(state, UInt<3>(0h1)) node _T_109 = and(stage2_pte_cache_hit, _T_108) node _T_110 = eq(aux_count, UInt<2>(0h2)) node _T_111 = and(_T_109, _T_110) node _T_112 = bits(hits_1, 0, 0) node _T_113 = bits(hits_1, 1, 1) node _T_114 = bits(hits_1, 2, 2) node _T_115 = bits(hits_1, 3, 3) node _T_116 = bits(hits_1, 4, 4) node _T_117 = bits(hits_1, 5, 5) node _T_118 = bits(hits_1, 6, 6) node _T_119 = bits(hits_1, 7, 7) node _T_120 = mux(_T_112, data_1[0], UInt<1>(0h0)) node _T_121 = mux(_T_113, data_1[1], UInt<1>(0h0)) node _T_122 = mux(_T_114, data_1[2], UInt<1>(0h0)) node _T_123 = mux(_T_115, data_1[3], UInt<1>(0h0)) node _T_124 = mux(_T_116, data_1[4], UInt<1>(0h0)) node _T_125 = mux(_T_117, data_1[5], UInt<1>(0h0)) node _T_126 = mux(_T_118, data_1[6], UInt<1>(0h0)) node _T_127 = mux(_T_119, data_1[7], UInt<1>(0h0)) node _T_128 = or(_T_120, _T_121) node _T_129 = or(_T_128, _T_122) node _T_130 = or(_T_129, _T_123) node _T_131 = or(_T_130, _T_124) node _T_132 = or(_T_131, _T_125) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) wire stage2_pte_cache_data : UInt<20> connect stage2_pte_cache_data, _T_134 reg pte_hit : UInt<1>, clock connect pte_hit, UInt<1>(0h0) connect io.dpath.perf.pte_miss, UInt<1>(0h0) node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1)) node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T) node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0)) node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2) connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3 node _T_135 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit) node _T_136 = and(io.dpath.perf.l2hit, _T_135) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)),\n") : printf assert(clock, _T_137, UInt<1>(0h1), "") : assert reg l2_refill : UInt<1>, clock connect l2_refill, UInt<1>(0h0) connect l2_refill_wire, l2_refill connect io.dpath.perf.l2miss, UInt<1>(0h0) connect io.dpath.perf.l2hit, UInt<1>(0h0) wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect _WIRE_1.v, UInt<1>(0h0) connect _WIRE_1.r, UInt<1>(0h0) connect _WIRE_1.w, UInt<1>(0h0) connect _WIRE_1.x, UInt<1>(0h0) connect _WIRE_1.u, UInt<1>(0h0) connect _WIRE_1.g, UInt<1>(0h0) connect _WIRE_1.a, UInt<1>(0h0) connect _WIRE_1.d, UInt<1>(0h0) connect _WIRE_1.reserved_for_software, UInt<2>(0h0) connect _WIRE_1.ppn, UInt<44>(0h0) connect _WIRE_1.reserved_for_future, UInt<10>(0h0) wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect l2_pte, _WIRE_1 node _invalidated_T = neq(state, UInt<3>(0h0)) node _invalidated_T_1 = and(invalidated, _invalidated_T) node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1) connect invalidated, _invalidated_T_2 connect io.mem.keep_clock_enabled, UInt<1>(0h0) node _io_mem_req_valid_T = eq(state, UInt<3>(0h1)) node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3)) node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1) connect io.mem.req.valid, _io_mem_req_valid_T_2 connect io.mem.req.bits.phys, UInt<1>(0h1) connect io.mem.req.bits.cmd, UInt<1>(0h0) connect io.mem.req.bits.size, UInt<2>(0h3) connect io.mem.req.bits.signed, UInt<1>(0h0) connect io.mem.req.bits.addr, pte_addr connect io.mem.req.bits.dprv, UInt<1>(0h1) node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0)) node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T) connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1 invalidate io.mem.req.bits.tag connect io.mem.req.bits.no_resp, UInt<1>(0h0) invalidate io.mem.req.bits.no_alloc invalidate io.mem.req.bits.no_xcpt invalidate io.mem.req.bits.data invalidate io.mem.req.bits.mask node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2)) node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T) node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf) connect io.mem.s1_kill, _io_mem_s1_kill_T_2 invalidate io.mem.s1_data.mask invalidate io.mem.s1_data.data connect io.mem.s2_kill, UInt<1>(0h0) node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_10 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_13 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_14 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_15 = xor(_pmaPgLevelHomogeneous_T_14, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_16 = cvt(_pmaPgLevelHomogeneous_T_15) node _pmaPgLevelHomogeneous_T_17 = and(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_18 = asSInt(_pmaPgLevelHomogeneous_T_17) node _pmaPgLevelHomogeneous_T_19 = eq(_pmaPgLevelHomogeneous_T_18, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_20 = xor(_pmaPgLevelHomogeneous_T_14, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_21 = cvt(_pmaPgLevelHomogeneous_T_20) node _pmaPgLevelHomogeneous_T_22 = and(_pmaPgLevelHomogeneous_T_21, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_23 = asSInt(_pmaPgLevelHomogeneous_T_22) node _pmaPgLevelHomogeneous_T_24 = eq(_pmaPgLevelHomogeneous_T_23, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_25 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_19) node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_25, _pmaPgLevelHomogeneous_T_24) node _pmaPgLevelHomogeneous_T_26 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_27 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_14, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28) node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30) node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32) node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_35 = xor(_pmaPgLevelHomogeneous_T_14, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_36 = cvt(_pmaPgLevelHomogeneous_T_35) node _pmaPgLevelHomogeneous_T_37 = and(_pmaPgLevelHomogeneous_T_36, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_38 = asSInt(_pmaPgLevelHomogeneous_T_37) node _pmaPgLevelHomogeneous_T_39 = eq(_pmaPgLevelHomogeneous_T_38, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_40 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_39) node _pmaPgLevelHomogeneous_T_41 = eq(_pmaPgLevelHomogeneous_T_40, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_42 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_43 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_44 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_45 = xor(_pmaPgLevelHomogeneous_T_44, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_46 = cvt(_pmaPgLevelHomogeneous_T_45) node _pmaPgLevelHomogeneous_T_47 = and(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<14>(0h2000))) node _pmaPgLevelHomogeneous_T_48 = asSInt(_pmaPgLevelHomogeneous_T_47) node _pmaPgLevelHomogeneous_T_49 = eq(_pmaPgLevelHomogeneous_T_48, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_50 = xor(_pmaPgLevelHomogeneous_T_44, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_51 = cvt(_pmaPgLevelHomogeneous_T_50) node _pmaPgLevelHomogeneous_T_52 = and(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_53 = asSInt(_pmaPgLevelHomogeneous_T_52) node _pmaPgLevelHomogeneous_T_54 = eq(_pmaPgLevelHomogeneous_T_53, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_55 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_56 = cvt(_pmaPgLevelHomogeneous_T_55) node _pmaPgLevelHomogeneous_T_57 = and(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_58 = asSInt(_pmaPgLevelHomogeneous_T_57) node _pmaPgLevelHomogeneous_T_59 = eq(_pmaPgLevelHomogeneous_T_58, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_60 = xor(_pmaPgLevelHomogeneous_T_44, UInt<21>(0h100000)) node _pmaPgLevelHomogeneous_T_61 = cvt(_pmaPgLevelHomogeneous_T_60) node _pmaPgLevelHomogeneous_T_62 = and(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<18>(0h2f000))) node _pmaPgLevelHomogeneous_T_63 = asSInt(_pmaPgLevelHomogeneous_T_62) node _pmaPgLevelHomogeneous_T_64 = eq(_pmaPgLevelHomogeneous_T_63, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_65 = xor(_pmaPgLevelHomogeneous_T_44, UInt<26>(0h2000000)) node _pmaPgLevelHomogeneous_T_66 = cvt(_pmaPgLevelHomogeneous_T_65) node _pmaPgLevelHomogeneous_T_67 = and(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_68 = asSInt(_pmaPgLevelHomogeneous_T_67) node _pmaPgLevelHomogeneous_T_69 = eq(_pmaPgLevelHomogeneous_T_68, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_70 = xor(_pmaPgLevelHomogeneous_T_44, UInt<26>(0h2010000)) node _pmaPgLevelHomogeneous_T_71 = cvt(_pmaPgLevelHomogeneous_T_70) node _pmaPgLevelHomogeneous_T_72 = and(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_73 = asSInt(_pmaPgLevelHomogeneous_T_72) node _pmaPgLevelHomogeneous_T_74 = eq(_pmaPgLevelHomogeneous_T_73, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_75 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_76 = cvt(_pmaPgLevelHomogeneous_T_75) node _pmaPgLevelHomogeneous_T_77 = and(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_78 = asSInt(_pmaPgLevelHomogeneous_T_77) node _pmaPgLevelHomogeneous_T_79 = eq(_pmaPgLevelHomogeneous_T_78, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_80 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_81 = cvt(_pmaPgLevelHomogeneous_T_80) node _pmaPgLevelHomogeneous_T_82 = and(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_83 = asSInt(_pmaPgLevelHomogeneous_T_82) node _pmaPgLevelHomogeneous_T_84 = eq(_pmaPgLevelHomogeneous_T_83, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_85 = xor(_pmaPgLevelHomogeneous_T_44, UInt<29>(0h10020000)) node _pmaPgLevelHomogeneous_T_86 = cvt(_pmaPgLevelHomogeneous_T_85) node _pmaPgLevelHomogeneous_T_87 = and(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_88 = asSInt(_pmaPgLevelHomogeneous_T_87) node _pmaPgLevelHomogeneous_T_89 = eq(_pmaPgLevelHomogeneous_T_88, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_90 = xor(_pmaPgLevelHomogeneous_T_44, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_91 = cvt(_pmaPgLevelHomogeneous_T_90) node _pmaPgLevelHomogeneous_T_92 = and(_pmaPgLevelHomogeneous_T_91, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_93 = asSInt(_pmaPgLevelHomogeneous_T_92) node _pmaPgLevelHomogeneous_T_94 = eq(_pmaPgLevelHomogeneous_T_93, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_95 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_49) node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_54) node _pmaPgLevelHomogeneous_T_97 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_59) node _pmaPgLevelHomogeneous_T_98 = or(_pmaPgLevelHomogeneous_T_97, _pmaPgLevelHomogeneous_T_64) node _pmaPgLevelHomogeneous_T_99 = or(_pmaPgLevelHomogeneous_T_98, _pmaPgLevelHomogeneous_T_69) node _pmaPgLevelHomogeneous_T_100 = or(_pmaPgLevelHomogeneous_T_99, _pmaPgLevelHomogeneous_T_74) node _pmaPgLevelHomogeneous_T_101 = or(_pmaPgLevelHomogeneous_T_100, _pmaPgLevelHomogeneous_T_79) node _pmaPgLevelHomogeneous_T_102 = or(_pmaPgLevelHomogeneous_T_101, _pmaPgLevelHomogeneous_T_84) node _pmaPgLevelHomogeneous_T_103 = or(_pmaPgLevelHomogeneous_T_102, _pmaPgLevelHomogeneous_T_89) node pmaPgLevelHomogeneous_3 = or(_pmaPgLevelHomogeneous_T_103, _pmaPgLevelHomogeneous_T_94) node _pmaPgLevelHomogeneous_T_104 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105) node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107) node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_110 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109) node _pmaPgLevelHomogeneous_T_111 = eq(_pmaPgLevelHomogeneous_T_110, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_112 = xor(_pmaPgLevelHomogeneous_T_44, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_113 = cvt(_pmaPgLevelHomogeneous_T_112) node _pmaPgLevelHomogeneous_T_114 = and(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_115 = asSInt(_pmaPgLevelHomogeneous_T_114) node _pmaPgLevelHomogeneous_T_116 = eq(_pmaPgLevelHomogeneous_T_115, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_117 = xor(_pmaPgLevelHomogeneous_T_44, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_118 = cvt(_pmaPgLevelHomogeneous_T_117) node _pmaPgLevelHomogeneous_T_119 = and(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_120 = asSInt(_pmaPgLevelHomogeneous_T_119) node _pmaPgLevelHomogeneous_T_121 = eq(_pmaPgLevelHomogeneous_T_120, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_122 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_123 = cvt(_pmaPgLevelHomogeneous_T_122) node _pmaPgLevelHomogeneous_T_124 = and(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_125 = asSInt(_pmaPgLevelHomogeneous_T_124) node _pmaPgLevelHomogeneous_T_126 = eq(_pmaPgLevelHomogeneous_T_125, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_127 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_128 = cvt(_pmaPgLevelHomogeneous_T_127) node _pmaPgLevelHomogeneous_T_129 = and(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_130 = asSInt(_pmaPgLevelHomogeneous_T_129) node _pmaPgLevelHomogeneous_T_131 = eq(_pmaPgLevelHomogeneous_T_130, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_132 = xor(_pmaPgLevelHomogeneous_T_44, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_133 = cvt(_pmaPgLevelHomogeneous_T_132) node _pmaPgLevelHomogeneous_T_134 = and(_pmaPgLevelHomogeneous_T_133, asSInt(UInt<33>(0h90000000))) node _pmaPgLevelHomogeneous_T_135 = asSInt(_pmaPgLevelHomogeneous_T_134) node _pmaPgLevelHomogeneous_T_136 = eq(_pmaPgLevelHomogeneous_T_135, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_137 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_116) node _pmaPgLevelHomogeneous_T_138 = or(_pmaPgLevelHomogeneous_T_137, _pmaPgLevelHomogeneous_T_121) node _pmaPgLevelHomogeneous_T_139 = or(_pmaPgLevelHomogeneous_T_138, _pmaPgLevelHomogeneous_T_126) node _pmaPgLevelHomogeneous_T_140 = or(_pmaPgLevelHomogeneous_T_139, _pmaPgLevelHomogeneous_T_131) node _pmaPgLevelHomogeneous_T_141 = or(_pmaPgLevelHomogeneous_T_140, _pmaPgLevelHomogeneous_T_136) node _pmaPgLevelHomogeneous_T_142 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_143 = cvt(_pmaPgLevelHomogeneous_T_142) node _pmaPgLevelHomogeneous_T_144 = and(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<33>(0h8e000000))) node _pmaPgLevelHomogeneous_T_145 = asSInt(_pmaPgLevelHomogeneous_T_144) node _pmaPgLevelHomogeneous_T_146 = eq(_pmaPgLevelHomogeneous_T_145, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_44, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147) node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149) node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_146) node _pmaPgLevelHomogeneous_T_153 = or(_pmaPgLevelHomogeneous_T_152, _pmaPgLevelHomogeneous_T_151) node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154) node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156) node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158) node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_161 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_162 = cvt(_pmaPgLevelHomogeneous_T_161) node _pmaPgLevelHomogeneous_T_163 = and(_pmaPgLevelHomogeneous_T_162, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_164 = asSInt(_pmaPgLevelHomogeneous_T_163) node _pmaPgLevelHomogeneous_T_165 = eq(_pmaPgLevelHomogeneous_T_164, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_166 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_165) node _pmaPgLevelHomogeneous_T_167 = eq(_pmaPgLevelHomogeneous_T_166, UInt<1>(0h0)) node _pmaHomogeneous_T = eq(count, UInt<1>(0h1)) node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, UInt<1>(0h0), UInt<1>(0h0)) node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2)) node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1) node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3)) node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_3, _pmaHomogeneous_T_3) node _pmpHomogeneous_T = shl(r_pte.ppn, 12) wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0) connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0) connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0) node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T_4) node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6) node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2) node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3)) node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4) node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5) node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 39) node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0)) node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9) node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3)) node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11) node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12) node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 30) node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0)) node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16) node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3)) node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18) node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19) node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 21) node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0)) node _pmpHomogeneous_T_23 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_24 = not(_pmpHomogeneous_T_23) node _pmpHomogeneous_T_25 = or(_pmpHomogeneous_T_24, UInt<2>(0h3)) node _pmpHomogeneous_T_26 = not(_pmpHomogeneous_T_25) node _pmpHomogeneous_T_27 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_26) node _pmpHomogeneous_T_28 = shr(_pmpHomogeneous_T_27, 12) node _pmpHomogeneous_T_29 = neq(_pmpHomogeneous_T_28, UInt<1>(0h0)) node _pmpHomogeneous_T_30 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_31 = mux(_pmpHomogeneous_T_30, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8) node _pmpHomogeneous_T_32 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_33 = mux(_pmpHomogeneous_T_32, _pmpHomogeneous_T_22, _pmpHomogeneous_T_31) node _pmpHomogeneous_T_34 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_35 = mux(_pmpHomogeneous_T_34, _pmpHomogeneous_T_29, _pmpHomogeneous_T_33) node _pmpHomogeneous_T_36 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_35) node _pmpHomogeneous_T_37 = bits(io.dpath.pmp[0].cfg.a, 0, 0) node _pmpHomogeneous_T_38 = eq(_pmpHomogeneous_T_37, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T) node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2) node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3) node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T) node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2) node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3) node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_1) node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3) node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1) node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3) node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5) node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1) node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3) node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5) node _pmpHomogeneous_T_39 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper) node _pmpHomogeneous_T_40 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper) node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_39, _pmpHomogeneous_T_40) node _pmpHomogeneous_T_42 = or(_pmpHomogeneous_T_38, _pmpHomogeneous_T_41) node _pmpHomogeneous_T_43 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_36, _pmpHomogeneous_T_42) node _pmpHomogeneous_T_44 = and(UInt<1>(0h1), _pmpHomogeneous_T_43) node _pmpHomogeneous_T_45 = bits(io.dpath.pmp[1].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_8, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_12) node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14) node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46) node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3)) node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48) node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49) node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 39) node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0)) node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53) node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3)) node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55) node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56) node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 30) node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0)) node _pmpHomogeneous_T_60 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_61 = not(_pmpHomogeneous_T_60) node _pmpHomogeneous_T_62 = or(_pmpHomogeneous_T_61, UInt<2>(0h3)) node _pmpHomogeneous_T_63 = not(_pmpHomogeneous_T_62) node _pmpHomogeneous_T_64 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_63) node _pmpHomogeneous_T_65 = shr(_pmpHomogeneous_T_64, 21) node _pmpHomogeneous_T_66 = neq(_pmpHomogeneous_T_65, UInt<1>(0h0)) node _pmpHomogeneous_T_67 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_68 = not(_pmpHomogeneous_T_67) node _pmpHomogeneous_T_69 = or(_pmpHomogeneous_T_68, UInt<2>(0h3)) node _pmpHomogeneous_T_70 = not(_pmpHomogeneous_T_69) node _pmpHomogeneous_T_71 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_70) node _pmpHomogeneous_T_72 = shr(_pmpHomogeneous_T_71, 12) node _pmpHomogeneous_T_73 = neq(_pmpHomogeneous_T_72, UInt<1>(0h0)) node _pmpHomogeneous_T_74 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_75 = mux(_pmpHomogeneous_T_74, _pmpHomogeneous_T_59, _pmpHomogeneous_T_52) node _pmpHomogeneous_T_76 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_77 = mux(_pmpHomogeneous_T_76, _pmpHomogeneous_T_66, _pmpHomogeneous_T_75) node _pmpHomogeneous_T_78 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_79 = mux(_pmpHomogeneous_T_78, _pmpHomogeneous_T_73, _pmpHomogeneous_T_77) node _pmpHomogeneous_T_80 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_79) node _pmpHomogeneous_T_81 = bits(io.dpath.pmp[1].cfg.a, 0, 0) node _pmpHomogeneous_T_82 = eq(_pmpHomogeneous_T_81, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5) node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7) node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8) node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5) node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7) node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8) node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_6) node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8) node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7) node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9) node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11) node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7) node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9) node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11) node _pmpHomogeneous_T_83 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1) node _pmpHomogeneous_T_84 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1) node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_83, _pmpHomogeneous_T_84) node _pmpHomogeneous_T_86 = or(_pmpHomogeneous_T_82, _pmpHomogeneous_T_85) node _pmpHomogeneous_T_87 = mux(_pmpHomogeneous_T_45, _pmpHomogeneous_T_80, _pmpHomogeneous_T_86) node _pmpHomogeneous_T_88 = and(_pmpHomogeneous_T_44, _pmpHomogeneous_T_87) node _pmpHomogeneous_T_89 = bits(io.dpath.pmp[2].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_16, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_20) node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22) node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90) node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3)) node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92) node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93) node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 39) node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0)) node _pmpHomogeneous_T_97 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_98 = not(_pmpHomogeneous_T_97) node _pmpHomogeneous_T_99 = or(_pmpHomogeneous_T_98, UInt<2>(0h3)) node _pmpHomogeneous_T_100 = not(_pmpHomogeneous_T_99) node _pmpHomogeneous_T_101 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_100) node _pmpHomogeneous_T_102 = shr(_pmpHomogeneous_T_101, 30) node _pmpHomogeneous_T_103 = neq(_pmpHomogeneous_T_102, UInt<1>(0h0)) node _pmpHomogeneous_T_104 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_105 = not(_pmpHomogeneous_T_104) node _pmpHomogeneous_T_106 = or(_pmpHomogeneous_T_105, UInt<2>(0h3)) node _pmpHomogeneous_T_107 = not(_pmpHomogeneous_T_106) node _pmpHomogeneous_T_108 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_107) node _pmpHomogeneous_T_109 = shr(_pmpHomogeneous_T_108, 21) node _pmpHomogeneous_T_110 = neq(_pmpHomogeneous_T_109, UInt<1>(0h0)) node _pmpHomogeneous_T_111 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_112 = not(_pmpHomogeneous_T_111) node _pmpHomogeneous_T_113 = or(_pmpHomogeneous_T_112, UInt<2>(0h3)) node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113) node _pmpHomogeneous_T_115 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_114) node _pmpHomogeneous_T_116 = shr(_pmpHomogeneous_T_115, 12) node _pmpHomogeneous_T_117 = neq(_pmpHomogeneous_T_116, UInt<1>(0h0)) node _pmpHomogeneous_T_118 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_119 = mux(_pmpHomogeneous_T_118, _pmpHomogeneous_T_103, _pmpHomogeneous_T_96) node _pmpHomogeneous_T_120 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_121 = mux(_pmpHomogeneous_T_120, _pmpHomogeneous_T_110, _pmpHomogeneous_T_119) node _pmpHomogeneous_T_122 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_123 = mux(_pmpHomogeneous_T_122, _pmpHomogeneous_T_117, _pmpHomogeneous_T_121) node _pmpHomogeneous_T_124 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_123) node _pmpHomogeneous_T_125 = bits(io.dpath.pmp[2].cfg.a, 0, 0) node _pmpHomogeneous_T_126 = eq(_pmpHomogeneous_T_125, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10) node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12) node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13) node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10) node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12) node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13) node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_11) node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13) node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13) node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15) node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17) node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13) node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15) node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17) node _pmpHomogeneous_T_127 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2) node _pmpHomogeneous_T_128 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2) node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_127, _pmpHomogeneous_T_128) node _pmpHomogeneous_T_130 = or(_pmpHomogeneous_T_126, _pmpHomogeneous_T_129) node _pmpHomogeneous_T_131 = mux(_pmpHomogeneous_T_89, _pmpHomogeneous_T_124, _pmpHomogeneous_T_130) node _pmpHomogeneous_T_132 = and(_pmpHomogeneous_T_88, _pmpHomogeneous_T_131) node _pmpHomogeneous_T_133 = bits(io.dpath.pmp[3].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_24, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_28) node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30) node _pmpHomogeneous_T_134 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_135 = not(_pmpHomogeneous_T_134) node _pmpHomogeneous_T_136 = or(_pmpHomogeneous_T_135, UInt<2>(0h3)) node _pmpHomogeneous_T_137 = not(_pmpHomogeneous_T_136) node _pmpHomogeneous_T_138 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_137) node _pmpHomogeneous_T_139 = shr(_pmpHomogeneous_T_138, 39) node _pmpHomogeneous_T_140 = neq(_pmpHomogeneous_T_139, UInt<1>(0h0)) node _pmpHomogeneous_T_141 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_142 = not(_pmpHomogeneous_T_141) node _pmpHomogeneous_T_143 = or(_pmpHomogeneous_T_142, UInt<2>(0h3)) node _pmpHomogeneous_T_144 = not(_pmpHomogeneous_T_143) node _pmpHomogeneous_T_145 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_144) node _pmpHomogeneous_T_146 = shr(_pmpHomogeneous_T_145, 30) node _pmpHomogeneous_T_147 = neq(_pmpHomogeneous_T_146, UInt<1>(0h0)) node _pmpHomogeneous_T_148 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_149 = not(_pmpHomogeneous_T_148) node _pmpHomogeneous_T_150 = or(_pmpHomogeneous_T_149, UInt<2>(0h3)) node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150) node _pmpHomogeneous_T_152 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_151) node _pmpHomogeneous_T_153 = shr(_pmpHomogeneous_T_152, 21) node _pmpHomogeneous_T_154 = neq(_pmpHomogeneous_T_153, UInt<1>(0h0)) node _pmpHomogeneous_T_155 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_156 = not(_pmpHomogeneous_T_155) node _pmpHomogeneous_T_157 = or(_pmpHomogeneous_T_156, UInt<2>(0h3)) node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157) node _pmpHomogeneous_T_159 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_158) node _pmpHomogeneous_T_160 = shr(_pmpHomogeneous_T_159, 12) node _pmpHomogeneous_T_161 = neq(_pmpHomogeneous_T_160, UInt<1>(0h0)) node _pmpHomogeneous_T_162 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_163 = mux(_pmpHomogeneous_T_162, _pmpHomogeneous_T_147, _pmpHomogeneous_T_140) node _pmpHomogeneous_T_164 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_165 = mux(_pmpHomogeneous_T_164, _pmpHomogeneous_T_154, _pmpHomogeneous_T_163) node _pmpHomogeneous_T_166 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_167 = mux(_pmpHomogeneous_T_166, _pmpHomogeneous_T_161, _pmpHomogeneous_T_165) node _pmpHomogeneous_T_168 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_167) node _pmpHomogeneous_T_169 = bits(io.dpath.pmp[3].cfg.a, 0, 0) node _pmpHomogeneous_T_170 = eq(_pmpHomogeneous_T_169, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15) node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17) node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18) node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15) node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17) node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18) node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_16) node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18) node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19) node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21) node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23) node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19) node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21) node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23) node _pmpHomogeneous_T_171 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3) node _pmpHomogeneous_T_172 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3) node _pmpHomogeneous_T_173 = or(_pmpHomogeneous_T_171, _pmpHomogeneous_T_172) node _pmpHomogeneous_T_174 = or(_pmpHomogeneous_T_170, _pmpHomogeneous_T_173) node _pmpHomogeneous_T_175 = mux(_pmpHomogeneous_T_133, _pmpHomogeneous_T_168, _pmpHomogeneous_T_174) node _pmpHomogeneous_T_176 = and(_pmpHomogeneous_T_132, _pmpHomogeneous_T_175) node _pmpHomogeneous_T_177 = bits(io.dpath.pmp[4].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_32, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_36) node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38) node _pmpHomogeneous_T_178 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_179 = not(_pmpHomogeneous_T_178) node _pmpHomogeneous_T_180 = or(_pmpHomogeneous_T_179, UInt<2>(0h3)) node _pmpHomogeneous_T_181 = not(_pmpHomogeneous_T_180) node _pmpHomogeneous_T_182 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_181) node _pmpHomogeneous_T_183 = shr(_pmpHomogeneous_T_182, 39) node _pmpHomogeneous_T_184 = neq(_pmpHomogeneous_T_183, UInt<1>(0h0)) node _pmpHomogeneous_T_185 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_186 = not(_pmpHomogeneous_T_185) node _pmpHomogeneous_T_187 = or(_pmpHomogeneous_T_186, UInt<2>(0h3)) node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187) node _pmpHomogeneous_T_189 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_188) node _pmpHomogeneous_T_190 = shr(_pmpHomogeneous_T_189, 30) node _pmpHomogeneous_T_191 = neq(_pmpHomogeneous_T_190, UInt<1>(0h0)) node _pmpHomogeneous_T_192 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_193 = not(_pmpHomogeneous_T_192) node _pmpHomogeneous_T_194 = or(_pmpHomogeneous_T_193, UInt<2>(0h3)) node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194) node _pmpHomogeneous_T_196 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_195) node _pmpHomogeneous_T_197 = shr(_pmpHomogeneous_T_196, 21) node _pmpHomogeneous_T_198 = neq(_pmpHomogeneous_T_197, UInt<1>(0h0)) node _pmpHomogeneous_T_199 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_200 = not(_pmpHomogeneous_T_199) node _pmpHomogeneous_T_201 = or(_pmpHomogeneous_T_200, UInt<2>(0h3)) node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201) node _pmpHomogeneous_T_203 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_202) node _pmpHomogeneous_T_204 = shr(_pmpHomogeneous_T_203, 12) node _pmpHomogeneous_T_205 = neq(_pmpHomogeneous_T_204, UInt<1>(0h0)) node _pmpHomogeneous_T_206 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_207 = mux(_pmpHomogeneous_T_206, _pmpHomogeneous_T_191, _pmpHomogeneous_T_184) node _pmpHomogeneous_T_208 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_198, _pmpHomogeneous_T_207) node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_205, _pmpHomogeneous_T_209) node _pmpHomogeneous_T_212 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_211) node _pmpHomogeneous_T_213 = bits(io.dpath.pmp[4].cfg.a, 0, 0) node _pmpHomogeneous_T_214 = eq(_pmpHomogeneous_T_213, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20) node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22) node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23) node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20) node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22) node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23) node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_21) node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23) node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25) node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27) node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29) node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25) node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27) node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29) node _pmpHomogeneous_T_215 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4) node _pmpHomogeneous_T_216 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4) node _pmpHomogeneous_T_217 = or(_pmpHomogeneous_T_215, _pmpHomogeneous_T_216) node _pmpHomogeneous_T_218 = or(_pmpHomogeneous_T_214, _pmpHomogeneous_T_217) node _pmpHomogeneous_T_219 = mux(_pmpHomogeneous_T_177, _pmpHomogeneous_T_212, _pmpHomogeneous_T_218) node _pmpHomogeneous_T_220 = and(_pmpHomogeneous_T_176, _pmpHomogeneous_T_219) node _pmpHomogeneous_T_221 = bits(io.dpath.pmp[5].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_40, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_44) node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46) node _pmpHomogeneous_T_222 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_223 = not(_pmpHomogeneous_T_222) node _pmpHomogeneous_T_224 = or(_pmpHomogeneous_T_223, UInt<2>(0h3)) node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224) node _pmpHomogeneous_T_226 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_225) node _pmpHomogeneous_T_227 = shr(_pmpHomogeneous_T_226, 39) node _pmpHomogeneous_T_228 = neq(_pmpHomogeneous_T_227, UInt<1>(0h0)) node _pmpHomogeneous_T_229 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_230 = not(_pmpHomogeneous_T_229) node _pmpHomogeneous_T_231 = or(_pmpHomogeneous_T_230, UInt<2>(0h3)) node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231) node _pmpHomogeneous_T_233 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_232) node _pmpHomogeneous_T_234 = shr(_pmpHomogeneous_T_233, 30) node _pmpHomogeneous_T_235 = neq(_pmpHomogeneous_T_234, UInt<1>(0h0)) node _pmpHomogeneous_T_236 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_237 = not(_pmpHomogeneous_T_236) node _pmpHomogeneous_T_238 = or(_pmpHomogeneous_T_237, UInt<2>(0h3)) node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238) node _pmpHomogeneous_T_240 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_239) node _pmpHomogeneous_T_241 = shr(_pmpHomogeneous_T_240, 21) node _pmpHomogeneous_T_242 = neq(_pmpHomogeneous_T_241, UInt<1>(0h0)) node _pmpHomogeneous_T_243 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_244 = not(_pmpHomogeneous_T_243) node _pmpHomogeneous_T_245 = or(_pmpHomogeneous_T_244, UInt<2>(0h3)) node _pmpHomogeneous_T_246 = not(_pmpHomogeneous_T_245) node _pmpHomogeneous_T_247 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_246) node _pmpHomogeneous_T_248 = shr(_pmpHomogeneous_T_247, 12) node _pmpHomogeneous_T_249 = neq(_pmpHomogeneous_T_248, UInt<1>(0h0)) node _pmpHomogeneous_T_250 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_251 = mux(_pmpHomogeneous_T_250, _pmpHomogeneous_T_235, _pmpHomogeneous_T_228) node _pmpHomogeneous_T_252 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_253 = mux(_pmpHomogeneous_T_252, _pmpHomogeneous_T_242, _pmpHomogeneous_T_251) node _pmpHomogeneous_T_254 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_255 = mux(_pmpHomogeneous_T_254, _pmpHomogeneous_T_249, _pmpHomogeneous_T_253) node _pmpHomogeneous_T_256 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_255) node _pmpHomogeneous_T_257 = bits(io.dpath.pmp[5].cfg.a, 0, 0) node _pmpHomogeneous_T_258 = eq(_pmpHomogeneous_T_257, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25) node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27) node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28) node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25) node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27) node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28) node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_26) node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28) node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31) node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33) node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35) node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31) node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33) node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35) node _pmpHomogeneous_T_259 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5) node _pmpHomogeneous_T_260 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5) node _pmpHomogeneous_T_261 = or(_pmpHomogeneous_T_259, _pmpHomogeneous_T_260) node _pmpHomogeneous_T_262 = or(_pmpHomogeneous_T_258, _pmpHomogeneous_T_261) node _pmpHomogeneous_T_263 = mux(_pmpHomogeneous_T_221, _pmpHomogeneous_T_256, _pmpHomogeneous_T_262) node _pmpHomogeneous_T_264 = and(_pmpHomogeneous_T_220, _pmpHomogeneous_T_263) node _pmpHomogeneous_T_265 = bits(io.dpath.pmp[6].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_48, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_52) node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54) node _pmpHomogeneous_T_266 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_267 = not(_pmpHomogeneous_T_266) node _pmpHomogeneous_T_268 = or(_pmpHomogeneous_T_267, UInt<2>(0h3)) node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268) node _pmpHomogeneous_T_270 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_269) node _pmpHomogeneous_T_271 = shr(_pmpHomogeneous_T_270, 39) node _pmpHomogeneous_T_272 = neq(_pmpHomogeneous_T_271, UInt<1>(0h0)) node _pmpHomogeneous_T_273 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_274 = not(_pmpHomogeneous_T_273) node _pmpHomogeneous_T_275 = or(_pmpHomogeneous_T_274, UInt<2>(0h3)) node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275) node _pmpHomogeneous_T_277 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_276) node _pmpHomogeneous_T_278 = shr(_pmpHomogeneous_T_277, 30) node _pmpHomogeneous_T_279 = neq(_pmpHomogeneous_T_278, UInt<1>(0h0)) node _pmpHomogeneous_T_280 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_281 = not(_pmpHomogeneous_T_280) node _pmpHomogeneous_T_282 = or(_pmpHomogeneous_T_281, UInt<2>(0h3)) node _pmpHomogeneous_T_283 = not(_pmpHomogeneous_T_282) node _pmpHomogeneous_T_284 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_283) node _pmpHomogeneous_T_285 = shr(_pmpHomogeneous_T_284, 21) node _pmpHomogeneous_T_286 = neq(_pmpHomogeneous_T_285, UInt<1>(0h0)) node _pmpHomogeneous_T_287 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_288 = not(_pmpHomogeneous_T_287) node _pmpHomogeneous_T_289 = or(_pmpHomogeneous_T_288, UInt<2>(0h3)) node _pmpHomogeneous_T_290 = not(_pmpHomogeneous_T_289) node _pmpHomogeneous_T_291 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_290) node _pmpHomogeneous_T_292 = shr(_pmpHomogeneous_T_291, 12) node _pmpHomogeneous_T_293 = neq(_pmpHomogeneous_T_292, UInt<1>(0h0)) node _pmpHomogeneous_T_294 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_294, _pmpHomogeneous_T_279, _pmpHomogeneous_T_272) node _pmpHomogeneous_T_296 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_297 = mux(_pmpHomogeneous_T_296, _pmpHomogeneous_T_286, _pmpHomogeneous_T_295) node _pmpHomogeneous_T_298 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_299 = mux(_pmpHomogeneous_T_298, _pmpHomogeneous_T_293, _pmpHomogeneous_T_297) node _pmpHomogeneous_T_300 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_299) node _pmpHomogeneous_T_301 = bits(io.dpath.pmp[6].cfg.a, 0, 0) node _pmpHomogeneous_T_302 = eq(_pmpHomogeneous_T_301, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30) node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32) node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33) node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30) node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32) node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33) node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_31) node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33) node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37) node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39) node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41) node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37) node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39) node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41) node _pmpHomogeneous_T_303 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6) node _pmpHomogeneous_T_304 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6) node _pmpHomogeneous_T_305 = or(_pmpHomogeneous_T_303, _pmpHomogeneous_T_304) node _pmpHomogeneous_T_306 = or(_pmpHomogeneous_T_302, _pmpHomogeneous_T_305) node _pmpHomogeneous_T_307 = mux(_pmpHomogeneous_T_265, _pmpHomogeneous_T_300, _pmpHomogeneous_T_306) node _pmpHomogeneous_T_308 = and(_pmpHomogeneous_T_264, _pmpHomogeneous_T_307) node _pmpHomogeneous_T_309 = bits(io.dpath.pmp[7].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_56, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_60) node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62) node _pmpHomogeneous_T_310 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_311 = not(_pmpHomogeneous_T_310) node _pmpHomogeneous_T_312 = or(_pmpHomogeneous_T_311, UInt<2>(0h3)) node _pmpHomogeneous_T_313 = not(_pmpHomogeneous_T_312) node _pmpHomogeneous_T_314 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_313) node _pmpHomogeneous_T_315 = shr(_pmpHomogeneous_T_314, 39) node _pmpHomogeneous_T_316 = neq(_pmpHomogeneous_T_315, UInt<1>(0h0)) node _pmpHomogeneous_T_317 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_318 = not(_pmpHomogeneous_T_317) node _pmpHomogeneous_T_319 = or(_pmpHomogeneous_T_318, UInt<2>(0h3)) node _pmpHomogeneous_T_320 = not(_pmpHomogeneous_T_319) node _pmpHomogeneous_T_321 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_320) node _pmpHomogeneous_T_322 = shr(_pmpHomogeneous_T_321, 30) node _pmpHomogeneous_T_323 = neq(_pmpHomogeneous_T_322, UInt<1>(0h0)) node _pmpHomogeneous_T_324 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_325 = not(_pmpHomogeneous_T_324) node _pmpHomogeneous_T_326 = or(_pmpHomogeneous_T_325, UInt<2>(0h3)) node _pmpHomogeneous_T_327 = not(_pmpHomogeneous_T_326) node _pmpHomogeneous_T_328 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_327) node _pmpHomogeneous_T_329 = shr(_pmpHomogeneous_T_328, 21) node _pmpHomogeneous_T_330 = neq(_pmpHomogeneous_T_329, UInt<1>(0h0)) node _pmpHomogeneous_T_331 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_332 = not(_pmpHomogeneous_T_331) node _pmpHomogeneous_T_333 = or(_pmpHomogeneous_T_332, UInt<2>(0h3)) node _pmpHomogeneous_T_334 = not(_pmpHomogeneous_T_333) node _pmpHomogeneous_T_335 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_334) node _pmpHomogeneous_T_336 = shr(_pmpHomogeneous_T_335, 12) node _pmpHomogeneous_T_337 = neq(_pmpHomogeneous_T_336, UInt<1>(0h0)) node _pmpHomogeneous_T_338 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_339 = mux(_pmpHomogeneous_T_338, _pmpHomogeneous_T_323, _pmpHomogeneous_T_316) node _pmpHomogeneous_T_340 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_341 = mux(_pmpHomogeneous_T_340, _pmpHomogeneous_T_330, _pmpHomogeneous_T_339) node _pmpHomogeneous_T_342 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_343 = mux(_pmpHomogeneous_T_342, _pmpHomogeneous_T_337, _pmpHomogeneous_T_341) node _pmpHomogeneous_T_344 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_343) node _pmpHomogeneous_T_345 = bits(io.dpath.pmp[7].cfg.a, 0, 0) node _pmpHomogeneous_T_346 = eq(_pmpHomogeneous_T_345, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35) node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37) node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38) node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35) node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37) node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38) node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_36) node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38) node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43) node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45) node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47) node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43) node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45) node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47) node _pmpHomogeneous_T_347 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7) node _pmpHomogeneous_T_348 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7) node _pmpHomogeneous_T_349 = or(_pmpHomogeneous_T_347, _pmpHomogeneous_T_348) node _pmpHomogeneous_T_350 = or(_pmpHomogeneous_T_346, _pmpHomogeneous_T_349) node _pmpHomogeneous_T_351 = mux(_pmpHomogeneous_T_309, _pmpHomogeneous_T_344, _pmpHomogeneous_T_350) node pmpHomogeneous = and(_pmpHomogeneous_T_308, _pmpHomogeneous_T_351) node homogeneous = and(pmaHomogeneous, pmpHomogeneous) connect io.requestor[0].resp.valid, resp_valid[0] connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[0].resp.bits.ae_final, resp_ae_final connect io.requestor[0].resp.bits.pf, resp_pf connect io.requestor[0].resp.bits.gf, resp_gf connect io.requestor[0].resp.bits.hr, resp_hr connect io.requestor[0].resp.bits.hw, resp_hw connect io.requestor[0].resp.bits.hx, resp_hx connect io.requestor[0].resp.bits.pte, r_pte connect io.requestor[0].resp.bits.level, max_count node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1) node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3) node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 27) node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 26, 0) node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6) node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 18) node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 17, 0) node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9) node _io_requestor_0_resp_bits_gpa_bits_T_11 = shr(aux_pte.ppn, 9) node _io_requestor_0_resp_bits_gpa_bits_T_12 = bits(r_req.addr, 8, 0) node _io_requestor_0_resp_bits_gpa_bits_T_13 = cat(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_12) node _io_requestor_0_resp_bits_gpa_bits_T_14 = eq(aux_count, UInt<1>(0h1)) node _io_requestor_0_resp_bits_gpa_bits_T_15 = mux(_io_requestor_0_resp_bits_gpa_bits_T_14, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7) node _io_requestor_0_resp_bits_gpa_bits_T_16 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_0_resp_bits_gpa_bits_T_17 = mux(_io_requestor_0_resp_bits_gpa_bits_T_16, _io_requestor_0_resp_bits_gpa_bits_T_13, _io_requestor_0_resp_bits_gpa_bits_T_15) node _io_requestor_0_resp_bits_gpa_bits_T_18 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_0_resp_bits_gpa_bits_T_19 = mux(_io_requestor_0_resp_bits_gpa_bits_T_18, _io_requestor_0_resp_bits_gpa_bits_T_13, _io_requestor_0_resp_bits_gpa_bits_T_17) node _io_requestor_0_resp_bits_gpa_bits_T_20 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_19) node _io_requestor_0_resp_bits_gpa_bits_T_21 = cat(_io_requestor_0_resp_bits_gpa_bits_T_20, gpa_pgoff) connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_21 node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T connect io.requestor[0].ptbr, io.dpath.ptbr connect io.requestor[0].hgatp, io.dpath.hgatp connect io.requestor[0].vsatp, io.dpath.vsatp connect io.requestor[0].customCSRs, io.dpath.customCSRs connect io.requestor[0].status, io.dpath.status connect io.requestor[0].hstatus, io.dpath.hstatus connect io.requestor[0].gstatus, io.dpath.gstatus connect io.requestor[0].pmp, io.dpath.pmp connect io.requestor[1].resp.valid, resp_valid[1] connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[1].resp.bits.ae_final, resp_ae_final connect io.requestor[1].resp.bits.pf, resp_pf connect io.requestor[1].resp.bits.gf, resp_gf connect io.requestor[1].resp.bits.hr, resp_hr connect io.requestor[1].resp.bits.hw, resp_hw connect io.requestor[1].resp.bits.hx, resp_hx connect io.requestor[1].resp.bits.pte, r_pte connect io.requestor[1].resp.bits.level, max_count node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1) node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3) node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 27) node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 26, 0) node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6) node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 18) node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 17, 0) node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9) node _io_requestor_1_resp_bits_gpa_bits_T_11 = shr(aux_pte.ppn, 9) node _io_requestor_1_resp_bits_gpa_bits_T_12 = bits(r_req.addr, 8, 0) node _io_requestor_1_resp_bits_gpa_bits_T_13 = cat(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_12) node _io_requestor_1_resp_bits_gpa_bits_T_14 = eq(aux_count, UInt<1>(0h1)) node _io_requestor_1_resp_bits_gpa_bits_T_15 = mux(_io_requestor_1_resp_bits_gpa_bits_T_14, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7) node _io_requestor_1_resp_bits_gpa_bits_T_16 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_1_resp_bits_gpa_bits_T_17 = mux(_io_requestor_1_resp_bits_gpa_bits_T_16, _io_requestor_1_resp_bits_gpa_bits_T_13, _io_requestor_1_resp_bits_gpa_bits_T_15) node _io_requestor_1_resp_bits_gpa_bits_T_18 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_1_resp_bits_gpa_bits_T_19 = mux(_io_requestor_1_resp_bits_gpa_bits_T_18, _io_requestor_1_resp_bits_gpa_bits_T_13, _io_requestor_1_resp_bits_gpa_bits_T_17) node _io_requestor_1_resp_bits_gpa_bits_T_20 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_19) node _io_requestor_1_resp_bits_gpa_bits_T_21 = cat(_io_requestor_1_resp_bits_gpa_bits_T_20, gpa_pgoff) connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_21 node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T connect io.requestor[1].ptbr, io.dpath.ptbr connect io.requestor[1].hgatp, io.dpath.hgatp connect io.requestor[1].vsatp, io.dpath.vsatp connect io.requestor[1].customCSRs, io.dpath.customCSRs connect io.requestor[1].status, io.dpath.status connect io.requestor[1].hstatus, io.dpath.hstatus connect io.requestor[1].gstatus, io.dpath.gstatus connect io.requestor[1].pmp, io.dpath.pmp wire next_state : UInt connect next_state, state inst state_barrier of OptimizationBarrier_UInt connect state_barrier.clock, clock connect state_barrier.reset, reset connect state_barrier.io.x, next_state connect state, state_barrier.io.y wire do_switch : UInt<1> connect do_switch, UInt<1>(0h0) node _T_141 = eq(UInt<3>(0h0), state) when _T_141 : node _T_142 = and(arb.io.out.ready, arb.io.out.valid) when _T_142 : node _satp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1) node _satp_initial_count_T_2 = bits(satp.mode, 0, 0) node _satp_initial_count_T_3 = sub(_satp_initial_count_T_1, _satp_initial_count_T_2) node satp_initial_count = tail(_satp_initial_count_T_3, 1) node _vsatp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1) node _vsatp_initial_count_T_2 = bits(io.dpath.vsatp.mode, 0, 0) node _vsatp_initial_count_T_3 = sub(_vsatp_initial_count_T_1, _vsatp_initial_count_T_2) node vsatp_initial_count = tail(_vsatp_initial_count_T_3, 1) node _hgatp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1) node _hgatp_initial_count_T_2 = bits(io.dpath.hgatp.mode, 0, 0) node _hgatp_initial_count_T_3 = sub(_hgatp_initial_count_T_1, _hgatp_initial_count_T_2) node hgatp_initial_count = tail(_hgatp_initial_count_T_3, 1) node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) connect r_req, arb.io.out.bits.bits connect r_req_dest, arb.io.chosen node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0)) connect next_state, _next_state_T connect stage2, arb.io.out.bits.bits.stage2 node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0)) node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T) connect stage2_final, _stage2_final_T_1 node _count_T_4 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) connect count, _count_T_4 node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0)) connect aux_count, _aux_count_T connect aux_pte.ppn, aux_ppn connect aux_pte.reserved_for_future, UInt<1>(0h0) connect resp_ae_ptw, UInt<1>(0h0) connect resp_ae_final, UInt<1>(0h0) connect resp_pf, UInt<1>(0h0) node _resp_gf_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1) node _resp_gf_count_T_2 = bits(io.dpath.hgatp.mode, 0, 0) node _resp_gf_count_T_3 = sub(_resp_gf_count_T_1, _resp_gf_count_T_2) node resp_gf_count = tail(_resp_gf_count_T_3, 1) node resp_gf_idxs_0 = shr(aux_ppn, 38) node resp_gf_idxs_1 = shr(aux_ppn, 29) wire _resp_gf_WIRE : UInt<15>[2] connect _resp_gf_WIRE[0], resp_gf_idxs_0 connect _resp_gf_WIRE[1], resp_gf_idxs_1 node _resp_gf_T = or(resp_gf_count, UInt<1>(0h0)) node _resp_gf_T_1 = bits(_resp_gf_T, 0, 0) node _resp_gf_T_2 = neq(_resp_gf_WIRE[_resp_gf_T_1], UInt<1>(0h0)) node _resp_gf_T_3 = and(_resp_gf_T_2, arb.io.out.bits.bits.stage2) connect resp_gf, _resp_gf_T_3 connect resp_hr, UInt<1>(0h1) connect resp_hw, UInt<1>(0h1) connect resp_hx, UInt<1>(0h1) connect resp_fragmented_superpage, UInt<1>(0h0) connect r_hgatp, io.dpath.hgatp node _T_143 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node _T_144 = or(_T_143, arb.io.out.bits.bits.stage2) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2)\n") : printf_1 assert(clock, _T_144, UInt<1>(0h1), "") : assert_1 else : node _T_148 = eq(UInt<3>(0h1), state) when _T_148 : node _T_149 = eq(count, r_hgatp_initial_count) node _T_150 = and(stage2, _T_149) when _T_150 : node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h3)) node _gpa_pgoff_T_1 = shl(r_req.addr, 3) node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0)) connect gpa_pgoff, _gpa_pgoff_T_2 when stage2_pte_cache_hit : node _aux_count_T_1 = add(aux_count, UInt<1>(0h1)) node _aux_count_T_2 = tail(_aux_count_T_1, 1) connect aux_count, _aux_count_T_2 connect aux_pte.ppn, stage2_pte_cache_data connect aux_pte.reserved_for_future, UInt<1>(0h0) connect pte_hit, UInt<1>(0h1) else : when pte_cache_hit : node _count_T_5 = add(count, UInt<1>(0h1)) node _count_T_6 = tail(_count_T_5, 1) connect count, _count_T_6 connect pte_hit, UInt<1>(0h1) else : node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1)) connect next_state, _next_state_T_1 when resp_gf : connect next_state, UInt<3>(0h0) node _T_151 = or(r_req_dest, UInt<1>(0h0)) node _T_152 = bits(_T_151, 0, 0) connect resp_valid[_T_152], UInt<1>(0h1) else : node _T_153 = eq(UInt<3>(0h2), state) when _T_153 : node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4)) connect next_state, _next_state_T_2 else : node _T_154 = eq(UInt<3>(0h4), state) when _T_154 : connect next_state, UInt<3>(0h5) node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h3)) connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T when io.mem.s2_xcpt.ae.ld : connect resp_ae_ptw, UInt<1>(0h1) connect next_state, UInt<3>(0h0) node _T_155 = or(r_req_dest, UInt<1>(0h0)) node _T_156 = bits(_T_155, 0, 0) connect resp_valid[_T_156], UInt<1>(0h1) else : node _T_157 = eq(UInt<3>(0h7), state) when _T_157 : connect next_state, UInt<3>(0h0) node _T_158 = or(r_req_dest, UInt<1>(0h0)) node _T_159 = bits(_T_158, 0, 0) connect resp_valid[_T_159], UInt<1>(0h1) node _T_160 = eq(homogeneous, UInt<1>(0h0)) when _T_160 : connect count, UInt<2>(0h3) connect resp_fragmented_superpage, UInt<1>(0h1) when do_both_stages : connect resp_fragmented_superpage, UInt<1>(0h1) node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h3)) node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1)) node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffc0000), UInt<44>(0hffff8000000)) node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hffffffffe00), _merged_pte_superpage_mask_T_2) node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3)) node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4) node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 27) node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 26, 0) node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1) node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 18) node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 17, 0) node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3) node _merged_pte_stage1_ppns_T_4 = bits(pte.ppn, 43, 9) node _merged_pte_stage1_ppns_T_5 = bits(aux_pte.ppn, 8, 0) node merged_pte_stage1_ppns_2 = cat(_merged_pte_stage1_ppns_T_4, _merged_pte_stage1_ppns_T_5) node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1)) node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0) node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2)) node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, merged_pte_stage1_ppns_2, _merged_pte_stage1_ppn_T_1) node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3)) node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3) node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask) wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect merged_pte, aux_pte connect merged_pte.ppn, _merged_pte_T node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T) node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0)) node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2) node _r_pte_T_4 = eq(state, UInt<3>(0h1)) node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit) node _r_pte_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_pte_count_T_1 = tail(_r_pte_count_T, 1) node _r_pte_count_T_2 = bits(r_hgatp.mode, 0, 0) node _r_pte_count_T_3 = sub(_r_pte_count_T_1, _r_pte_count_T_2) node r_pte_count = tail(_r_pte_count_T_3, 1) node r_pte_idxs_0 = shr(stage2_pte_cache_data, 36) node r_pte_idxs_1 = shr(stage2_pte_cache_data, 27) node _r_pte_lsbs_truncIdx_T = or(r_pte_count, UInt<1>(0h0)) node r_pte_lsbs_truncIdx = bits(_r_pte_lsbs_truncIdx_T, 0, 0) node _r_pte_lsbs_T = eq(r_pte_lsbs_truncIdx, UInt<1>(0h1)) node _r_pte_lsbs_T_1 = mux(_r_pte_lsbs_T, r_pte_idxs_1, r_pte_idxs_0) wire r_pte_lsbs : UInt<2> connect r_pte_lsbs, _r_pte_lsbs_T_1 wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte, l2_pte node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs) connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1 node _r_pte_T_6 = eq(state, UInt<3>(0h1)) node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit) wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_1, l2_pte connect r_pte_pte_1.ppn, pte_cache_data node _r_pte_count_T_4 = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_pte_count_T_5 = tail(_r_pte_count_T_4, 1) node _r_pte_count_T_6 = bits(r_hgatp.mode, 0, 0) node _r_pte_count_T_7 = sub(_r_pte_count_T_5, _r_pte_count_T_6) node r_pte_count_1 = tail(_r_pte_count_T_7, 1) node r_pte_idxs_0_1 = shr(pte.ppn, 36) node r_pte_idxs_1_1 = shr(pte.ppn, 27) node _r_pte_lsbs_truncIdx_T_1 = or(r_pte_count_1, UInt<1>(0h0)) node r_pte_lsbs_truncIdx_1 = bits(_r_pte_lsbs_truncIdx_T_1, 0, 0) node _r_pte_lsbs_T_2 = eq(r_pte_lsbs_truncIdx_1, UInt<1>(0h1)) node _r_pte_lsbs_T_3 = mux(_r_pte_lsbs_T_2, r_pte_idxs_1_1, r_pte_idxs_0_1) wire r_pte_lsbs_1 : UInt<2> connect r_pte_lsbs_1, _r_pte_lsbs_T_3 wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_2, r_pte node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1) connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3 node _r_pte_T_8 = eq(traverse, UInt<1>(0h0)) node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1) node _r_pte_T_10 = and(_r_pte_T_9, stage2) node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte) node _r_pte_T_12 = eq(state, UInt<3>(0h7)) node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0)) node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13) node _r_pte_T_15 = neq(count, UInt<2>(0h3)) node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15) node _r_pte_T_17 = shr(r_pte.ppn, 27) node _r_pte_T_18 = bits(r_req.addr, 26, 0) node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18) node _r_pte_T_20 = shr(r_pte.ppn, 18) node _r_pte_T_21 = bits(r_req.addr, 17, 0) node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21) node _r_pte_T_23 = shr(r_pte.ppn, 9) node _r_pte_T_24 = bits(r_req.addr, 8, 0) node _r_pte_T_25 = cat(_r_pte_T_23, _r_pte_T_24) node _r_pte_T_26 = eq(count, UInt<1>(0h1)) node _r_pte_T_27 = mux(_r_pte_T_26, _r_pte_T_22, _r_pte_T_19) node _r_pte_T_28 = eq(count, UInt<2>(0h2)) node _r_pte_T_29 = mux(_r_pte_T_28, _r_pte_T_25, _r_pte_T_27) node _r_pte_T_30 = eq(count, UInt<2>(0h3)) node _r_pte_T_31 = mux(_r_pte_T_30, _r_pte_T_25, _r_pte_T_29) wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_3, r_pte connect r_pte_pte_3.ppn, _r_pte_T_31 node _r_pte_T_32 = and(arb.io.out.ready, arb.io.out.valid) node _r_pte_count_T_8 = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_pte_count_T_9 = tail(_r_pte_count_T_8, 1) node _r_pte_count_T_10 = bits(io.dpath.hgatp.mode, 0, 0) node _r_pte_count_T_11 = sub(_r_pte_count_T_9, _r_pte_count_T_10) node r_pte_count_2 = tail(_r_pte_count_T_11, 1) node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 36) node r_pte_idxs_1_2 = shr(io.dpath.vsatp.ppn, 27) node _r_pte_lsbs_truncIdx_T_2 = or(r_pte_count_2, UInt<1>(0h0)) node r_pte_lsbs_truncIdx_2 = bits(_r_pte_lsbs_truncIdx_T_2, 0, 0) node _r_pte_lsbs_T_4 = eq(r_pte_lsbs_truncIdx_2, UInt<1>(0h1)) node _r_pte_lsbs_T_5 = mux(_r_pte_lsbs_T_4, r_pte_idxs_1_2, r_pte_idxs_0_2) wire r_pte_lsbs_2 : UInt<2> connect r_pte_lsbs_2, _r_pte_lsbs_T_5 wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_4, r_pte node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2) node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2) connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5 wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_5, r_pte connect r_pte_pte_5.ppn, satp.ppn node _r_pte_T_33 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5) node _r_pte_T_34 = mux(_r_pte_T_32, _r_pte_T_33, r_pte) node _r_pte_T_35 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_34) node _r_pte_T_36 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_35) node _r_pte_T_37 = mux(do_switch, r_pte_pte_2, _r_pte_T_36) node _r_pte_T_38 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_37) node _r_pte_T_39 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_38) node _r_pte_T_40 = mux(_r_pte_T_3, l2_pte, _r_pte_T_39) inst r_pte_barrier of OptimizationBarrier_PTE connect r_pte_barrier.clock, clock connect r_pte_barrier.reset, reset connect r_pte_barrier.io.x.v, _r_pte_T_40.v connect r_pte_barrier.io.x.r, _r_pte_T_40.r connect r_pte_barrier.io.x.w, _r_pte_T_40.w connect r_pte_barrier.io.x.x, _r_pte_T_40.x connect r_pte_barrier.io.x.u, _r_pte_T_40.u connect r_pte_barrier.io.x.g, _r_pte_T_40.g connect r_pte_barrier.io.x.a, _r_pte_T_40.a connect r_pte_barrier.io.x.d, _r_pte_T_40.d connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_40.reserved_for_software connect r_pte_barrier.io.x.ppn, _r_pte_T_40.ppn connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_40.reserved_for_future connect r_pte, r_pte_barrier.io.y node _T_161 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_162 = and(UInt<1>(0h0), _T_161) node _T_163 = eq(resp_gf, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) when _T_164 : node _T_165 = eq(state, UInt<3>(0h1)) node _T_166 = eq(state, UInt<3>(0h2)) node _T_167 = or(_T_165, _T_166) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req \|\| state === s_wait1)\n") : printf_2 assert(clock, _T_167, UInt<1>(0h1), "") : assert_2 connect next_state, UInt<3>(0h0) node _T_171 = or(r_req_dest, UInt<1>(0h0)) node _T_172 = bits(_T_171, 0, 0) connect resp_valid[_T_172], UInt<1>(0h1) connect count, UInt<2>(0h3) when mem_resp_valid : node _T_173 = eq(state, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3 assert(clock, _T_173, UInt<1>(0h1), "") : assert_3 connect next_state, UInt<3>(0h1) when traverse : node _T_177 = eq(stage2, UInt<1>(0h0)) node _T_178 = and(do_both_stages, _T_177) when _T_178 : connect do_switch, UInt<1>(0h1) node _count_T_7 = add(count, UInt<1>(0h1)) node _count_T_8 = tail(_count_T_7, 1) connect count, _count_T_8 else : node _gf_T = eq(stage2_final, UInt<1>(0h0)) node _gf_T_1 = and(stage2, _gf_T) node _gf_T_2 = eq(pte.w, UInt<1>(0h0)) node _gf_T_3 = and(pte.x, _gf_T_2) node _gf_T_4 = or(pte.r, _gf_T_3) node _gf_T_5 = and(pte.v, _gf_T_4) node _gf_T_6 = and(_gf_T_5, pte.a) node _gf_T_7 = and(_gf_T_6, pte.r) node _gf_T_8 = and(_gf_T_7, pte.u) node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0)) node _gf_T_10 = and(_gf_T_1, _gf_T_9) node _gf_T_11 = eq(pte.w, UInt<1>(0h0)) node _gf_T_12 = and(pte.x, _gf_T_11) node _gf_T_13 = or(pte.r, _gf_T_12) node _gf_T_14 = and(pte.v, _gf_T_13) node _gf_T_15 = and(_gf_T_14, pte.a) node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _gf_T_17 = and(_gf_T_15, _gf_T_16) node _gf_T_18 = and(_gf_T_17, invalid_gpa) node gf = or(_gf_T_10, _gf_T_18) node ae = and(pte.v, invalid_paddr) node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0)) node pf = and(pte.v, _pf_T) node _success_T = eq(ae, UInt<1>(0h0)) node _success_T_1 = and(pte.v, _success_T) node _success_T_2 = eq(pf, UInt<1>(0h0)) node _success_T_3 = and(_success_T_1, _success_T_2) node _success_T_4 = eq(gf, UInt<1>(0h0)) node success = and(_success_T_3, _success_T_4) node _T_179 = eq(stage2_final, UInt<1>(0h0)) node _T_180 = and(do_both_stages, _T_179) node _T_181 = and(_T_180, success) when _T_181 : when stage2 : connect stage2, UInt<1>(0h0) connect count, aux_count else : connect stage2_final, UInt<1>(0h1) connect do_switch, UInt<1>(0h1) else : node _l2_refill_T = eq(count, UInt<2>(0h3)) node _l2_refill_T_1 = and(success, _l2_refill_T) node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0)) node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2) node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0)) node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0)) node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5) node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h3)) node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7) node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9) node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10) node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11) node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a) node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w) node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d) node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u) node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17) node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18) node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19) node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a) node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x) node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u) node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23) node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24) node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25) node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26) connect l2_refill, _l2_refill_T_27 connect count, max_count node _T_182 = eq(count, UInt<2>(0h3)) node _T_183 = eq(do_both_stages, UInt<1>(0h0)) node _T_184 = eq(aux_count, UInt<2>(0h3)) node _T_185 = or(_T_183, _T_184) node _T_186 = and(_T_182, _T_185) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = and(UInt<1>(0h0), _T_187) when _T_188 : connect next_state, UInt<3>(0h7) else : connect next_state, UInt<3>(0h0) node _T_189 = or(r_req_dest, UInt<1>(0h0)) node _T_190 = bits(_T_189, 0, 0) connect resp_valid[_T_190], UInt<1>(0h1) node _resp_ae_ptw_T = lt(count, UInt<2>(0h3)) node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T) node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0)) node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2) node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4) node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0)) node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6) node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0)) node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8) node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0)) node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10) node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0)) node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12) node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14) node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15) connect resp_ae_ptw, _resp_ae_ptw_T_16 node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0)) node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T) node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1) node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2) node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a) node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4) connect resp_ae_final, _resp_ae_final_T_5 node _resp_pf_T = eq(stage2, UInt<1>(0h0)) node _resp_pf_T_1 = and(pf, _resp_pf_T) connect resp_pf, _resp_pf_T_1 node _resp_gf_T_4 = and(pf, stage2) node _resp_gf_T_5 = or(gf, _resp_gf_T_4) connect resp_gf, _resp_gf_T_5 node _resp_hr_T = eq(stage2, UInt<1>(0h0)) node _resp_hr_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hr_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2) node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4) node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5) node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6) node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a) node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r) node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u) node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10) node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11) connect resp_hr, _resp_hr_T_12 node _resp_hw_T = eq(stage2, UInt<1>(0h0)) node _resp_hw_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hw_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2) node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4) node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5) node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6) node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a) node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w) node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d) node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u) node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11) node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12) connect resp_hw, _resp_hw_T_13 node _resp_hx_T = eq(stage2, UInt<1>(0h0)) node _resp_hx_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hx_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2) node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4) node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5) node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6) node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a) node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x) node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u) node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10) node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11) connect resp_hx, _resp_hx_T_12 when io.mem.s2_nack : node _T_191 = eq(state, UInt<3>(0h4)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4 assert(clock, _T_191, UInt<1>(0h1), "") : assert_4 connect next_state, UInt<3>(0h1) when do_switch : node _aux_count_T_3 = add(count, UInt<1>(0h1)) node _aux_count_T_4 = tail(_aux_count_T_3, 1) node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count) connect aux_count, _aux_count_T_5 connect count, r_hgatp_initial_count node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 27) node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 26, 0) node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1) node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 18) node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 17, 0) node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3) node _aux_pte_s1_ppns_T_4 = bits(pte.ppn, 43, 9) node _aux_pte_s1_ppns_T_5 = bits(r_req.addr, 8, 0) node aux_pte_s1_ppns_2 = cat(_aux_pte_s1_ppns_T_4, _aux_pte_s1_ppns_T_5) node _aux_pte_T = eq(count, UInt<1>(0h1)) node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0) node _aux_pte_T_2 = eq(count, UInt<2>(0h2)) node _aux_pte_T_3 = mux(_aux_pte_T_2, aux_pte_s1_ppns_2, _aux_pte_T_1) node _aux_pte_T_4 = eq(count, UInt<2>(0h3)) node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3) wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect aux_pte_pte, pte connect aux_pte_pte.ppn, _aux_pte_T_5 node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte) connect aux_pte, _aux_pte_T_6 connect stage2, UInt<1>(0h1) node _leaf_T = eq(traverse, UInt<1>(0h0)) node _leaf_T_1 = and(mem_resp_valid, _leaf_T) node _leaf_T_2 = eq(count, UInt<1>(0h0)) node leaf = and(_leaf_T_1, _leaf_T_2) node _T_195 = and(leaf, pte.v) node _T_196 = eq(invalid_paddr, UInt<1>(0h0)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(invalid_gpa, UInt<1>(0h0)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_201 = and(_T_199, _T_200) node _T_202 = and(leaf, pte.v) node _T_203 = and(_T_202, invalid_paddr) node _T_204 = and(leaf, pte.v) node _T_205 = and(_T_204, invalid_gpa) node _T_206 = and(leaf, pte.v) node _T_207 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_208 = and(_T_206, _T_207) node _T_209 = bits(mem_resp_data, 0, 0) node _T_210 = eq(_T_209, UInt<1>(0h0)) node _T_211 = and(leaf, _T_210) node _T_212 = eq(pte.v, UInt<1>(0h0)) node _T_213 = and(leaf, _T_212) node _T_214 = bits(mem_resp_data, 0, 0) node _T_215 = and(_T_213, _T_214) node _leaf_T_3 = eq(traverse, UInt<1>(0h0)) node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3) node _leaf_T_5 = eq(count, UInt<1>(0h1)) node leaf_1 = and(_leaf_T_4, _leaf_T_5) node _T_216 = and(leaf_1, pte.v) node _T_217 = eq(invalid_paddr, UInt<1>(0h0)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(invalid_gpa, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_222 = and(_T_220, _T_221) node _T_223 = and(leaf_1, pte.v) node _T_224 = and(_T_223, invalid_paddr) node _T_225 = and(leaf_1, pte.v) node _T_226 = and(_T_225, invalid_gpa) node _T_227 = and(leaf_1, pte.v) node _T_228 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_229 = and(_T_227, _T_228) node _T_230 = bits(mem_resp_data, 0, 0) node _T_231 = eq(_T_230, UInt<1>(0h0)) node _T_232 = and(leaf_1, _T_231) node _T_233 = eq(pte.v, UInt<1>(0h0)) node _T_234 = and(leaf_1, _T_233) node _T_235 = bits(mem_resp_data, 0, 0) node _T_236 = and(_T_234, _T_235) node _leaf_T_6 = eq(traverse, UInt<1>(0h0)) node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6) node _leaf_T_8 = eq(count, UInt<2>(0h2)) node leaf_2 = and(_leaf_T_7, _leaf_T_8) node _T_237 = and(leaf_2, pte.v) node _T_238 = eq(invalid_paddr, UInt<1>(0h0)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(invalid_gpa, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_243 = and(_T_241, _T_242) node _T_244 = and(leaf_2, pte.v) node _T_245 = and(_T_244, invalid_paddr) node _T_246 = and(leaf_2, pte.v) node _T_247 = and(_T_246, invalid_gpa) node _T_248 = and(leaf_2, pte.v) node _T_249 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = bits(mem_resp_data, 0, 0) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = and(leaf_2, _T_252) node _T_254 = eq(pte.v, UInt<1>(0h0)) node _T_255 = and(leaf_2, _T_254) node _T_256 = bits(mem_resp_data, 0, 0) node _T_257 = and(_T_255, _T_256) node _leaf_T_9 = eq(traverse, UInt<1>(0h0)) node _leaf_T_10 = and(mem_resp_valid, _leaf_T_9) node _leaf_T_11 = eq(count, UInt<2>(0h3)) node leaf_3 = and(_leaf_T_10, _leaf_T_11) node _T_258 = and(leaf_3, pte.v) node _T_259 = eq(invalid_paddr, UInt<1>(0h0)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(invalid_gpa, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_264 = and(_T_262, _T_263) node _T_265 = and(leaf_3, pte.v) node _T_266 = and(_T_265, invalid_paddr) node _T_267 = and(leaf_3, pte.v) node _T_268 = and(_T_267, invalid_gpa) node _T_269 = and(leaf_3, pte.v) node _T_270 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_271 = and(_T_269, _T_270) node _T_272 = bits(mem_resp_data, 0, 0) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = and(leaf_3, _T_273) node _T_275 = eq(count, UInt<2>(0h3)) node _T_276 = and(mem_resp_valid, _T_275) node _T_277 = eq(pte.r, UInt<1>(0h0)) node _T_278 = and(pte.v, _T_277) node _T_279 = eq(pte.w, UInt<1>(0h0)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(pte.x, UInt<1>(0h0)) node _T_282 = and(_T_280, _T_281) node _T_283 = eq(pte.d, UInt<1>(0h0)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(pte.a, UInt<1>(0h0)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(pte.u, UInt<1>(0h0)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_290 = and(_T_288, _T_289) node _T_291 = and(_T_276, _T_290) node _T_292 = eq(state, UInt<3>(0h4)) node _T_293 = and(_T_292, io.mem.s2_xcpt.ae.ld)	module PTW( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] input io_requestor_0_req_valid, // @[PTW.scala:220:14] input [35:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [47:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_sd, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_v, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sd, // @[PTW.scala:220:14] output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] input io_requestor_1_req_valid, // @[PTW.scala:220:14] input io_requestor_1_req_bits_valid, // @[PTW.scala:220:14] input [35:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [47:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_sd, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_v, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sd, // @[PTW.scala:220:14] output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [48:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_req_bits_dv, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14] input io_mem_s2_uncached, // @[PTW.scala:220:14] input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [48:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14] input [6:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14] input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14] input io_mem_resp_bits_signed, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14] input io_mem_resp_bits_dv, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14] input io_mem_resp_bits_replay, // @[PTW.scala:220:14] input io_mem_resp_bits_has_data, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14] input io_mem_replay_next, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14] input [48:0] io_mem_s2_gpa, // @[PTW.scala:220:14] input io_mem_ordered, // @[PTW.scala:220:14] input io_mem_store_pending, // @[PTW.scala:220:14] input io_mem_perf_acquire, // @[PTW.scala:220:14] input io_mem_perf_release, // @[PTW.scala:220:14] input io_mem_perf_grant, // @[PTW.scala:220:14] input io_mem_perf_tlbMiss, // @[PTW.scala:220:14] input io_mem_perf_blocked, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14] input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [47:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_sd, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_hstatus_spvp, // @[PTW.scala:220:14] input io_dpath_hstatus_spv, // @[PTW.scala:220:14] input io_dpath_hstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_debug, // @[PTW.scala:220:14] input io_dpath_gstatus_cease, // @[PTW.scala:220:14] input io_dpath_gstatus_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14] input io_dpath_gstatus_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14] input io_dpath_gstatus_v, // @[PTW.scala:220:14] input io_dpath_gstatus_sd, // @[PTW.scala:220:14] input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14] input io_dpath_gstatus_mpv, // @[PTW.scala:220:14] input io_dpath_gstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_mbe, // @[PTW.scala:220:14] input io_dpath_gstatus_sbe, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14] input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14] input io_dpath_gstatus_tsr, // @[PTW.scala:220:14] input io_dpath_gstatus_tw, // @[PTW.scala:220:14] input io_dpath_gstatus_tvm, // @[PTW.scala:220:14] input io_dpath_gstatus_mxr, // @[PTW.scala:220:14] input io_dpath_gstatus_sum, // @[PTW.scala:220:14] input io_dpath_gstatus_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14] input io_dpath_gstatus_spp, // @[PTW.scala:220:14] input io_dpath_gstatus_mpie, // @[PTW.scala:220:14] input io_dpath_gstatus_ube, // @[PTW.scala:220:14] input io_dpath_gstatus_spie, // @[PTW.scala:220:14] input io_dpath_gstatus_upie, // @[PTW.scala:220:14] input io_dpath_gstatus_mie, // @[PTW.scala:220:14] input io_dpath_gstatus_hie, // @[PTW.scala:220:14] input io_dpath_gstatus_sie, // @[PTW.scala:220:14] input io_dpath_gstatus_uie, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_perf_pte_hit, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire _arb_io_out_bits_valid; // @[PTW.scala:236:19] wire [35:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7] wire [35:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_valid_0 = io_requestor_1_req_bits_valid; // @[PTW.scala:219:7] wire [35:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [48:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7] wire [48:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7] wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [47:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7] wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_0 = io_dpath_gstatus_sd; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27] wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20] wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24] wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17] wire l2_pte_d = 1'h0; // @[PTW.scala:403:113] wire l2_pte_a = 1'h0; // @[PTW.scala:403:113] wire l2_pte_g = 1'h0; // @[PTW.scala:403:113] wire l2_pte_u = 1'h0; // @[PTW.scala:403:113] wire l2_pte_x = 1'h0; // @[PTW.scala:403:113] wire l2_pte_w = 1'h0; // @[PTW.scala:403:113] wire l2_pte_r = 1'h0; // @[PTW.scala:403:113] wire l2_pte_v = 1'h0; // @[PTW.scala:403:113] wire _pmaHomogeneous_T_1 = 1'h0; // @[package.scala:39:76] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32] wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _vsatp_initial_count_T_2 = 1'h0; // @[package.scala:163:13] wire _hgatp_initial_count_T_2 = 1'h0; // @[package.scala:163:13] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_count_T_2 = 1'h0; // @[package.scala:163:13] wire _resp_gf_T_3 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16] wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire r_pte_idxs_1 = 1'h0; // @[PTW.scala:778:58] wire _r_pte_lsbs_T_1 = 1'h0; // @[package.scala:39:76] wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26] wire _r_pte_count_T_10 = 1'h0; // @[package.scala:163:13] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27] wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43] wire [7:0] r_pte_idxs_0_2 = 8'h0; // @[PTW.scala:778:58] wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13] wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7] wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33] wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16] wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16] wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_8 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_9 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_10 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_11 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_12 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_13 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_26 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_27 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_42 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_43 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_104 = 1'h1; // @[TLBPermissions.scala:87:22] wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire _resp_gf_T_1 = 1'h1; // @[package.scala:163:13] wire _r_pte_T = 1'h1; // @[PTW.scala:670:19] wire r_pte_lsbs_truncIdx_2 = 1'h1; // @[package.scala:38:47] wire _r_pte_lsbs_T_4 = 1'h1; // @[package.scala:39:86] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire [16:0] r_pte_idxs_1_2 = 17'h0; // @[PTW.scala:778:58] wire [16:0] _r_pte_lsbs_T_5 = 17'h0; // @[package.scala:39:76] wire [2:0] _r_hgatp_initial_count_T_1 = 3'h1; // @[PTW.scala:286:42] wire [2:0] _count_T_1 = 3'h1; // @[PTW.scala:786:28] wire [2:0] _satp_initial_count_T_1 = 3'h1; // @[PTW.scala:586:45] wire [2:0] _vsatp_initial_count_T_1 = 3'h1; // @[PTW.scala:587:46] wire [2:0] vsatp_initial_count = 3'h1; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T_1 = 3'h1; // @[PTW.scala:588:46] wire [2:0] hgatp_initial_count = 3'h1; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T_1 = 3'h1; // @[PTW.scala:786:28] wire [2:0] resp_gf_count = 3'h1; // @[PTW.scala:786:44] wire [2:0] _resp_gf_T = 3'h1; // @[package.scala:24:40] wire [2:0] _r_pte_count_T_1 = 3'h1; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h1; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_9 = 3'h1; // @[PTW.scala:777:28] wire [2:0] r_pte_count_2 = 3'h1; // @[PTW.scala:777:44] wire [2:0] _r_pte_lsbs_truncIdx_T_2 = 3'h1; // @[package.scala:38:21] wire [3:0] _r_hgatp_initial_count_T = 4'h1; // @[PTW.scala:286:42] wire [3:0] _count_T = 4'h1; // @[PTW.scala:786:28] wire [3:0] _satp_initial_count_T = 4'h1; // @[PTW.scala:586:45] wire [3:0] _vsatp_initial_count_T = 4'h1; // @[PTW.scala:587:46] wire [3:0] _vsatp_initial_count_T_3 = 4'h1; // @[PTW.scala:587:62] wire [3:0] _hgatp_initial_count_T = 4'h1; // @[PTW.scala:588:46] wire [3:0] _hgatp_initial_count_T_3 = 4'h1; // @[PTW.scala:588:62] wire [3:0] _resp_gf_count_T = 4'h1; // @[PTW.scala:786:28] wire [3:0] _resp_gf_count_T_3 = 4'h1; // @[PTW.scala:786:44] wire [3:0] _r_pte_count_T = 4'h1; // @[PTW.scala:777:28] wire [3:0] _r_pte_count_T_4 = 4'h1; // @[PTW.scala:777:28] wire [3:0] _r_pte_count_T_8 = 4'h1; // @[PTW.scala:777:28] wire [3:0] _r_pte_count_T_11 = 4'h1; // @[PTW.scala:777:44] wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13] wire [2:0] _aux_count_T = 3'h0; // @[PTW.scala:597:27] wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [48:0] tag_1 = 49'h1000000000000; // @[PTW.scala:363:18] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [47:0] _tag_T = 48'h0; // @[package.scala:138:15] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57] wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [47:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [47:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire [48:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(\|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = \|state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T \| l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 \| _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 \| io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61] wire clock_en = _clock_en_T_3 \| _clock_en_T_4; // @[CustomCSRs.scala:43:61] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [35:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20] reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20] reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20] reg [1:0] aux_count; // @[PTW.scala:278:22] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire _r_hgatp_initial_count_T_2 = r_hgatp_mode[0]; // @[package.scala:163:13] wire _count_T_2 = r_hgatp_mode[0]; // @[package.scala:163:13] wire _r_pte_count_T_2 = r_hgatp_mode[0]; // @[package.scala:163:13] wire _r_pte_count_T_6 = r_hgatp_mode[0]; // @[package.scala:163:13] wire [3:0] _r_hgatp_initial_count_T_3 = 4'h1 - {3'h0, _r_hgatp_initial_count_T_2}; // @[package.scala:163:13] wire [2:0] r_hgatp_initial_count = _r_hgatp_initial_count_T_3[2:0]; // @[PTW.scala:286:58] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {8'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_3 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [35:0] _res_ppn_T_2 = tmp_ppn[35:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [35:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {16'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {8'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r \| tmp_w \| tmp_x) & (count != 2'h3 & (\|(tmp_ppn[8:0])) \| ~(count[1]) & (\|(tmp_ppn[17:9])) \| count == 2'h0 & (\|(tmp_ppn[26:18])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (\|(tmp_ppn[43:36])) : (\|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [3:0] _count_T_3 = 4'h1 - {3'h0, _count_T_2}; // @[package.scala:163:13] wire [2:0] count_1 = _count_T_3[2:0]; // @[PTW.scala:786:44] wire [5:0] idxs_0 = tmp_ppn[43:38]; // @[PTW.scala:304:37, :787:58] wire [14:0] idxs_1 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (\|(count_1[0] ? idxs_1 : {9'h0, idxs_0})); // @[package.scala:43:40, :163:13] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(\|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _GEN = count != 2'h3; // @[PTW.scala:259:18, :317:73] wire _traverse_T_18; // @[PTW.scala:317:73] assign _traverse_T_18 = _GEN; // @[PTW.scala:317:73] wire _can_hit_T; // @[PTW.scala:358:18] assign _can_hit_T = _GEN; // @[PTW.scala:317:73, :358:18] wire _io_dpath_perf_pte_miss_T; // @[PTW.scala:640:39] assign _io_dpath_perf_pte_miss_T = _GEN; // @[PTW.scala:317:73, :640:39] wire _r_pte_T_15; // @[PTW.scala:680:65] assign _r_pte_T_15 = _GEN; // @[PTW.scala:317:73, :680:65] wire _resp_ae_ptw_T; // @[PTW.scala:725:36] assign _resp_ae_ptw_T = _GEN; // @[PTW.scala:317:73, :725:36] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [16:0] _pte_addr_vpn_idxs_T = vpn[43:27]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [25:0] _pte_addr_vpn_idxs_T_1 = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_2 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_3 = _pte_addr_vpn_idxs_T_3[8:0]; // @[PTW.scala:322:{12,48}] wire [2:0] _GEN_0 = {1'h0, count}; // @[PTW.scala:259:18, :324:40] wire _T_149 = _GEN_0 == r_hgatp_initial_count; // @[PTW.scala:286:58, :324:40] wire _pte_addr_mask_T; // @[PTW.scala:324:40] assign _pte_addr_mask_T = _T_149; // @[PTW.scala:324:40] wire _can_hit_T_3; // @[PTW.scala:357:21] assign _can_hit_T_3 = _T_149; // @[PTW.scala:324:40, :357:21] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _T_51 = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _T_51; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_T_30 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_74; // @[package.scala:39:86] assign _pmpHomogeneous_T_74 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_5 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_118; // @[package.scala:39:86] assign _pmpHomogeneous_T_118 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_10 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_162; // @[package.scala:39:86] assign _pmpHomogeneous_T_162 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_15 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_206; // @[package.scala:39:86] assign _pmpHomogeneous_T_206 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_20 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_250; // @[package.scala:39:86] assign _pmpHomogeneous_T_250 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_25 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_294; // @[package.scala:39:86] assign _pmpHomogeneous_T_294 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_30 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_338; // @[package.scala:39:86] assign _pmpHomogeneous_T_338 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_35 = _T_51; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _T_51; // @[package.scala:39:86] wire _r_pte_T_26; // @[package.scala:39:86] assign _r_pte_T_26 = _T_51; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _T_51; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _T_51; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_55 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_55; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_T_32 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_2 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_76; // @[package.scala:39:86] assign _pmpHomogeneous_T_76 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_7 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_120; // @[package.scala:39:86] assign _pmpHomogeneous_T_120 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_12 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_164; // @[package.scala:39:86] assign _pmpHomogeneous_T_164 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_17 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_208; // @[package.scala:39:86] assign _pmpHomogeneous_T_208 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_22 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_252; // @[package.scala:39:86] assign _pmpHomogeneous_T_252 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_27 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_296; // @[package.scala:39:86] assign _pmpHomogeneous_T_296 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_32 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_340; // @[package.scala:39:86] assign _pmpHomogeneous_T_340 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_37 = _T_55; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_55; // @[package.scala:39:86] wire _r_pte_T_28; // @[package.scala:39:86] assign _r_pte_T_28 = _T_55; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_55; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_55; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_3 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] \| pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] reg [6:0] state_reg; // @[Replacement.scala:168:70] reg [7:0] valid; // @[PTW.scala:352:24] reg [31:0] tags_0; // @[PTW.scala:353:19] reg [31:0] tags_1; // @[PTW.scala:353:19] reg [31:0] tags_2; // @[PTW.scala:353:19] reg [31:0] tags_3; // @[PTW.scala:353:19] reg [31:0] tags_4; // @[PTW.scala:353:19] reg [31:0] tags_5; // @[PTW.scala:353:19] reg [31:0] tags_6; // @[PTW.scala:353:19] reg [31:0] tags_7; // @[PTW.scala:353:19] reg [19:0] data_0; // @[PTW.scala:355:19] reg [19:0] data_1; // @[PTW.scala:355:19] reg [19:0] data_2; // @[PTW.scala:355:19] reg [19:0] data_3; // @[PTW.scala:355:19] reg [19:0] data_4; // @[PTW.scala:355:19] reg [19:0] data_5; // @[PTW.scala:355:19] reg [19:0] data_6; // @[PTW.scala:355:19] reg [19:0] data_7; // @[PTW.scala:355:19] wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65] wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}] wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}] wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15] wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27] wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27] wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27] wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27] wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27] wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27] wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27] wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27] wire _hit_T = \|hits; // @[PTW.scala:366:43, :367:20] wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}] wire _r_T = &valid; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13] wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13] wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13] wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13] wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13] wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13] wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57] wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45] wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45] wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45] wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45] wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45] wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45] wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45] wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45] wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13] wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35] wire [7:0] _valid_T_1 = valid \| _valid_T; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13] wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13] wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire _T_165 = state == 3'h1; // @[PTW.scala:233:22, :377:24] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_165; // @[PTW.scala:377:24, :394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_165; // @[PTW.scala:377:24, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_165; // @[PTW.scala:377:24, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_165; // @[PTW.scala:377:24, :674:15] wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18] wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18] wire [3:0] _T_35 = hi \| lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_1 = _T_35[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_1 = _T_35[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_reg_touch_way_sized_1 = {\|hi, \|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13] wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13] wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16] wire _leaf_T_2 = count == 2'h0; // @[PTW.scala:259:18, :382:47, :751:53] wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) \| (hits[1] ? data_1 : 20'h0) \| (hits[2] ? data_2 : 20'h0) \| (hits[3] ? data_3 : 20'h0) \| (hits[4] ? data_4 : 20'h0) \| (hits[5] ? data_5 : 20'h0) \| (hits[6] ? data_6 : 20'h0) \| (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36] reg [6:0] state_reg_1; // @[Replacement.scala:168:70] reg [7:0] valid_1; // @[PTW.scala:352:24] reg [19:0] data_1_0; // @[PTW.scala:355:19] reg [19:0] data_1_1; // @[PTW.scala:355:19] reg [19:0] data_1_2; // @[PTW.scala:355:19] reg [19:0] data_1_3; // @[PTW.scala:355:19] reg [19:0] data_1_4; // @[PTW.scala:355:19] reg [19:0] data_1_5; // @[PTW.scala:355:19] reg [19:0] data_1_6; // @[PTW.scala:355:19] reg [19:0] data_1_7; // @[PTW.scala:355:19] wire _can_hit_T_4 = aux_count != 2'h3; // @[PTW.scala:278:22, :357:60] wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}] wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}] wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}] wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107] wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}] wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33] wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}] wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44] wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}] wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13] wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13] wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13] wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13] wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57] wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45] wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45] wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45] wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45] wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45] wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45] wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45] wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45] wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45] wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45] wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45] wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45] wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45] wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45] wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13] wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35] wire [7:0] _valid_T_3 = valid_1 \| _valid_T_2; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13] wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13] wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38] wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13] wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13] wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13] wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13] wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13] wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12] wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38] wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12] wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16] wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16] wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16] wire _T_106 = aux_count == 2'h1; // @[PTW.scala:278:22, :382:47] wire _io_requestor_0_resp_bits_gpa_bits_T_14; // @[package.scala:39:86] assign _io_requestor_0_resp_bits_gpa_bits_T_14 = _T_106; // @[package.scala:39:86] wire _io_requestor_1_resp_bits_gpa_bits_T_14; // @[package.scala:39:86] assign _io_requestor_1_resp_bits_gpa_bits_T_14 = _T_106; // @[package.scala:39:86] wire _T_110 = aux_count == 2'h2; // @[PTW.scala:278:22, :382:47] wire _io_requestor_0_resp_bits_gpa_bits_T_16; // @[package.scala:39:86] assign _io_requestor_0_resp_bits_gpa_bits_T_16 = _T_110; // @[package.scala:39:86] wire _io_requestor_1_resp_bits_gpa_bits_T_16; // @[package.scala:39:86] assign _io_requestor_1_resp_bits_gpa_bits_T_16 = _T_110; // @[package.scala:39:86] reg pte_hit; // @[PTW.scala:392:24] wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}] assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}] assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire _invalidated_T = \|state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 \| _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T \| _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {17'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 \| resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN_1 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_14; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_14 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_44; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_44 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN_1; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_14; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_35 = _pmaPgLevelHomogeneous_T_14; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_15 = {_pmaPgLevelHomogeneous_T_14[55:28], _pmaPgLevelHomogeneous_T_14[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_16 = {1'h0, _pmaPgLevelHomogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_17; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_19 = _pmaPgLevelHomogeneous_T_18 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_19; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_20 = {_pmaPgLevelHomogeneous_T_14[55:32], _pmaPgLevelHomogeneous_T_14[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_21 = {1'h0, _pmaPgLevelHomogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_22 = _pmaPgLevelHomogeneous_T_21 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_25 \| _pmaPgLevelHomogeneous_T_24; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_36 = {1'h0, _pmaPgLevelHomogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_37 = _pmaPgLevelHomogeneous_T_36 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_39 = _pmaPgLevelHomogeneous_T_38 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_41 = ~_pmaPgLevelHomogeneous_T_40; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_44; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_46 = {1'h0, _pmaPgLevelHomogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_48 = _pmaPgLevelHomogeneous_T_47; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_49 = _pmaPgLevelHomogeneous_T_48 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_44[55:14], _pmaPgLevelHomogeneous_T_44[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_50 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_117 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_51 = {1'h0, _pmaPgLevelHomogeneous_T_50}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_53 = _pmaPgLevelHomogeneous_T_52; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_54 = _pmaPgLevelHomogeneous_T_53 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_44[55:17], _pmaPgLevelHomogeneous_T_44[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_55 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_105; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_105 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_122 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_154 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_161; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_161 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_56 = {1'h0, _pmaPgLevelHomogeneous_T_55}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_58 = _pmaPgLevelHomogeneous_T_57; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_59 = _pmaPgLevelHomogeneous_T_58 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_60 = {_pmaPgLevelHomogeneous_T_44[55:21], _pmaPgLevelHomogeneous_T_44[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_61 = {1'h0, _pmaPgLevelHomogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_63 = _pmaPgLevelHomogeneous_T_62; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_64 = _pmaPgLevelHomogeneous_T_63 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_65 = {_pmaPgLevelHomogeneous_T_44[55:26], _pmaPgLevelHomogeneous_T_44[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_66 = {1'h0, _pmaPgLevelHomogeneous_T_65}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_68 = _pmaPgLevelHomogeneous_T_67; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_69 = _pmaPgLevelHomogeneous_T_68 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_70 = {_pmaPgLevelHomogeneous_T_44[55:26], _pmaPgLevelHomogeneous_T_44[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_71 = {1'h0, _pmaPgLevelHomogeneous_T_70}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_73 = _pmaPgLevelHomogeneous_T_72; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_74 = _pmaPgLevelHomogeneous_T_73 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_44[55:28], _pmaPgLevelHomogeneous_T_44[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_75 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_127 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_142 = _GEN_4; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_76 = {1'h0, _pmaPgLevelHomogeneous_T_75}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_78 = _pmaPgLevelHomogeneous_T_77; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_79 = _pmaPgLevelHomogeneous_T_78 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_80 = {_pmaPgLevelHomogeneous_T_44[55:28], _pmaPgLevelHomogeneous_T_44[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_81 = {1'h0, _pmaPgLevelHomogeneous_T_80}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_83 = _pmaPgLevelHomogeneous_T_82; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_84 = _pmaPgLevelHomogeneous_T_83 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_85 = {_pmaPgLevelHomogeneous_T_44[55:29], _pmaPgLevelHomogeneous_T_44[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_86 = {1'h0, _pmaPgLevelHomogeneous_T_85}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_87; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_5 = {_pmaPgLevelHomogeneous_T_44[55:32], _pmaPgLevelHomogeneous_T_44[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_90; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_90 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_132; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_132 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_5; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_91 = {1'h0, _pmaPgLevelHomogeneous_T_90}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 \| _pmaPgLevelHomogeneous_T_54; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_97 = _pmaPgLevelHomogeneous_T_96 \| _pmaPgLevelHomogeneous_T_59; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_98 = _pmaPgLevelHomogeneous_T_97 \| _pmaPgLevelHomogeneous_T_64; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_99 = _pmaPgLevelHomogeneous_T_98 \| _pmaPgLevelHomogeneous_T_69; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 \| _pmaPgLevelHomogeneous_T_74; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100 \| _pmaPgLevelHomogeneous_T_79; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 \| _pmaPgLevelHomogeneous_T_84; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102 \| _pmaPgLevelHomogeneous_T_89; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_3 = _pmaPgLevelHomogeneous_T_103 \| _pmaPgLevelHomogeneous_T_94; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_110 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_111 = ~_pmaPgLevelHomogeneous_T_110; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = {1'h0, _pmaPgLevelHomogeneous_T_112}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_115 = _pmaPgLevelHomogeneous_T_114; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_116 = _pmaPgLevelHomogeneous_T_115 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_116; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_118 = {1'h0, _pmaPgLevelHomogeneous_T_117}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_120 = _pmaPgLevelHomogeneous_T_119; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_121 = _pmaPgLevelHomogeneous_T_120 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_123 = {1'h0, _pmaPgLevelHomogeneous_T_122}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_125 = _pmaPgLevelHomogeneous_T_124; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_126 = _pmaPgLevelHomogeneous_T_125 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = {1'h0, _pmaPgLevelHomogeneous_T_127}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_129; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_133 = {1'h0, _pmaPgLevelHomogeneous_T_132}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 & 57'h90000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_135 = _pmaPgLevelHomogeneous_T_134; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_136 = _pmaPgLevelHomogeneous_T_135 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137 \| _pmaPgLevelHomogeneous_T_121; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 \| _pmaPgLevelHomogeneous_T_126; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_140 = _pmaPgLevelHomogeneous_T_139 \| _pmaPgLevelHomogeneous_T_131; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_141 = _pmaPgLevelHomogeneous_T_140 \| _pmaPgLevelHomogeneous_T_136; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_143 = {1'h0, _pmaPgLevelHomogeneous_T_142}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 & 57'h8E000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_144; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_146; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_153 = _pmaPgLevelHomogeneous_T_152 \| _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_162 = {1'h0, _pmaPgLevelHomogeneous_T_161}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_163 = _pmaPgLevelHomogeneous_T_162 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_164 = _pmaPgLevelHomogeneous_T_163; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_165 = _pmaPgLevelHomogeneous_T_164 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_166 = _pmaPgLevelHomogeneous_T_165; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_167 = ~_pmaPgLevelHomogeneous_T_166; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 & pmaPgLevelHomogeneous_2; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_3 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 & _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}] wire [31:0] _GEN_6 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_2 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_9 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_23; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_23 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_8 = \|_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_15 = \|_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_22 = \|_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_24 = ~_pmpHomogeneous_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_25 = {_pmpHomogeneous_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_26 = ~_pmpHomogeneous_T_25; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_27 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_26}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_29 = \|_pmpHomogeneous_T_28; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_31 = _pmpHomogeneous_T_30 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_33 = _pmpHomogeneous_T_32 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_34 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_34 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_33; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_36 = pmpHomogeneous_maskHomogeneous \| _pmpHomogeneous_T_35; // @[package.scala:39:76] wire _pmpHomogeneous_T_37 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_38 = ~_pmpHomogeneous_T_37; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}] wire _pmpHomogeneous_T_39 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21] wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}] wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T = _GEN_7; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_7; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_40 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62] wire _pmpHomogeneous_T_41 = _pmpHomogeneous_T_39 \| _pmpHomogeneous_T_40; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_42 = _pmpHomogeneous_T_38 \| _pmpHomogeneous_T_41; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_43 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_36 : _pmpHomogeneous_T_42; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_45 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 & _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}] wire [31:0] _GEN_8 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_46 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_53 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_60; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_60 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_67; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_67 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_52 = \|_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_59 = \|_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_61 = ~_pmpHomogeneous_T_60; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_62 = {_pmpHomogeneous_T_61[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_63 = ~_pmpHomogeneous_T_62; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_64 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_63}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_66 = \|_pmpHomogeneous_T_65; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_69 = {_pmpHomogeneous_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_70 = ~_pmpHomogeneous_T_69; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_71 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_70}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_72 = _pmpHomogeneous_T_71[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_73 = \|_pmpHomogeneous_T_72; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_75 = _pmpHomogeneous_T_74 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_77 = _pmpHomogeneous_T_76 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_75; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_78 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_79 = _pmpHomogeneous_T_78 ? _pmpHomogeneous_T_73 : _pmpHomogeneous_T_77; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_80 = pmpHomogeneous_maskHomogeneous_1 \| _pmpHomogeneous_T_79; // @[package.scala:39:76] wire _pmpHomogeneous_T_81 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_82 = ~_pmpHomogeneous_T_81; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}] wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_9; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_9; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_83 = pmpHomogeneous_endsBeforeLower_1 \| pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_84 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_85 = _pmpHomogeneous_T_83 \| _pmpHomogeneous_T_84; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_86 = _pmpHomogeneous_T_82 \| _pmpHomogeneous_T_85; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_87 = _pmpHomogeneous_T_45 ? _pmpHomogeneous_T_80 : _pmpHomogeneous_T_86; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_88 = _pmpHomogeneous_T_44 & _pmpHomogeneous_T_87; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_89 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 & _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}] wire [31:0] _GEN_10 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_90 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_97; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_97 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_104; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_104 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_111; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_111 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_96 = \|_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_98 = ~_pmpHomogeneous_T_97; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_99 = {_pmpHomogeneous_T_98[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_100 = ~_pmpHomogeneous_T_99; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_101 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_100}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_103 = \|_pmpHomogeneous_T_102; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_106 = {_pmpHomogeneous_T_105[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_107 = ~_pmpHomogeneous_T_106; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_108 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_107}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_109 = _pmpHomogeneous_T_108[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_110 = \|_pmpHomogeneous_T_109; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_112 = ~_pmpHomogeneous_T_111; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_113 = {_pmpHomogeneous_T_112[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_114}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_116 = _pmpHomogeneous_T_115[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_117 = \|_pmpHomogeneous_T_116; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_119 = _pmpHomogeneous_T_118 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_96; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_121 = _pmpHomogeneous_T_120 ? _pmpHomogeneous_T_110 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_122 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_123 = _pmpHomogeneous_T_122 ? _pmpHomogeneous_T_117 : _pmpHomogeneous_T_121; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_124 = pmpHomogeneous_maskHomogeneous_2 \| _pmpHomogeneous_T_123; // @[package.scala:39:76] wire _pmpHomogeneous_T_125 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_126 = ~_pmpHomogeneous_T_125; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}] wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_11; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_11; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_127 = pmpHomogeneous_endsBeforeLower_2 \| pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_128 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_129 = _pmpHomogeneous_T_127 \| _pmpHomogeneous_T_128; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_130 = _pmpHomogeneous_T_126 \| _pmpHomogeneous_T_129; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_131 = _pmpHomogeneous_T_89 ? _pmpHomogeneous_T_124 : _pmpHomogeneous_T_130; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_132 = _pmpHomogeneous_T_88 & _pmpHomogeneous_T_131; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_133 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 & _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}] wire [31:0] _GEN_12 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_134; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_134 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_141; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_141 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_148; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_148 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_155; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_155 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_135 = ~_pmpHomogeneous_T_134; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_136 = {_pmpHomogeneous_T_135[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_137 = ~_pmpHomogeneous_T_136; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_138 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_137}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_140 = \|_pmpHomogeneous_T_139; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_143 = {_pmpHomogeneous_T_142[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_144 = ~_pmpHomogeneous_T_143; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_145 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_144}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_146 = _pmpHomogeneous_T_145[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_147 = \|_pmpHomogeneous_T_146; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_149 = ~_pmpHomogeneous_T_148; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_150 = {_pmpHomogeneous_T_149[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_151}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_153 = _pmpHomogeneous_T_152[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_154 = \|_pmpHomogeneous_T_153; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_156 = ~_pmpHomogeneous_T_155; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_157 = {_pmpHomogeneous_T_156[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_158}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_160 = _pmpHomogeneous_T_159[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_161 = \|_pmpHomogeneous_T_160; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_163 = _pmpHomogeneous_T_162 ? _pmpHomogeneous_T_147 : _pmpHomogeneous_T_140; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_165 = _pmpHomogeneous_T_164 ? _pmpHomogeneous_T_154 : _pmpHomogeneous_T_163; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_166 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_167 = _pmpHomogeneous_T_166 ? _pmpHomogeneous_T_161 : _pmpHomogeneous_T_165; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_168 = pmpHomogeneous_maskHomogeneous_3 \| _pmpHomogeneous_T_167; // @[package.scala:39:76] wire _pmpHomogeneous_T_169 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_170 = ~_pmpHomogeneous_T_169; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}] wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_13; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_13; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_171 = pmpHomogeneous_endsBeforeLower_3 \| pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_172 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_173 = _pmpHomogeneous_T_171 \| _pmpHomogeneous_T_172; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_170 \| _pmpHomogeneous_T_173; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_175 = _pmpHomogeneous_T_133 ? _pmpHomogeneous_T_168 : _pmpHomogeneous_T_174; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_132 & _pmpHomogeneous_T_175; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_177 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 & _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}] wire [31:0] _GEN_14 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_178; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_178 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_185; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_185 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_192; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_192 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_199; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_199 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_180 = {_pmpHomogeneous_T_179[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_181 = ~_pmpHomogeneous_T_180; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_182 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_181}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_183 = _pmpHomogeneous_T_182[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_184 = \|_pmpHomogeneous_T_183; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_186 = ~_pmpHomogeneous_T_185; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_187 = {_pmpHomogeneous_T_186[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_188}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_190 = _pmpHomogeneous_T_189[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_191 = \|_pmpHomogeneous_T_190; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_193 = ~_pmpHomogeneous_T_192; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_194 = {_pmpHomogeneous_T_193[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_195}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_197 = _pmpHomogeneous_T_196[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_198 = \|_pmpHomogeneous_T_197; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_200 = ~_pmpHomogeneous_T_199; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_201 = {_pmpHomogeneous_T_200[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_202}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_204 = _pmpHomogeneous_T_203[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_205 = \|_pmpHomogeneous_T_204; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_207 = _pmpHomogeneous_T_206 ? _pmpHomogeneous_T_191 : _pmpHomogeneous_T_184; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_198 : _pmpHomogeneous_T_207; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_210 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_205 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_212 = pmpHomogeneous_maskHomogeneous_4 \| _pmpHomogeneous_T_211; // @[package.scala:39:76] wire _pmpHomogeneous_T_213 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_214 = ~_pmpHomogeneous_T_213; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}] wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_15; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_15; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_215 = pmpHomogeneous_endsBeforeLower_4 \| pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_216 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_217 = _pmpHomogeneous_T_215 \| _pmpHomogeneous_T_216; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_218 = _pmpHomogeneous_T_214 \| _pmpHomogeneous_T_217; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_177 ? _pmpHomogeneous_T_212 : _pmpHomogeneous_T_218; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_176 & _pmpHomogeneous_T_219; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_221 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 & _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}] wire [31:0] _GEN_16 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_222; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_222 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_229; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_229 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_236; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_236 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_243; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_243 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_223 = ~_pmpHomogeneous_T_222; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_224 = {_pmpHomogeneous_T_223[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_225}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_227 = _pmpHomogeneous_T_226[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_228 = \|_pmpHomogeneous_T_227; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_230 = ~_pmpHomogeneous_T_229; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_231 = {_pmpHomogeneous_T_230[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_232}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_234 = _pmpHomogeneous_T_233[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_235 = \|_pmpHomogeneous_T_234; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_237 = ~_pmpHomogeneous_T_236; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_238 = {_pmpHomogeneous_T_237[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_239}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_241 = _pmpHomogeneous_T_240[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_242 = \|_pmpHomogeneous_T_241; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_244 = ~_pmpHomogeneous_T_243; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_245 = {_pmpHomogeneous_T_244[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_246 = ~_pmpHomogeneous_T_245; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_247 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_246}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_249 = \|_pmpHomogeneous_T_248; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_251 = _pmpHomogeneous_T_250 ? _pmpHomogeneous_T_235 : _pmpHomogeneous_T_228; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_253 = _pmpHomogeneous_T_252 ? _pmpHomogeneous_T_242 : _pmpHomogeneous_T_251; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_254 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_255 = _pmpHomogeneous_T_254 ? _pmpHomogeneous_T_249 : _pmpHomogeneous_T_253; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_256 = pmpHomogeneous_maskHomogeneous_5 \| _pmpHomogeneous_T_255; // @[package.scala:39:76] wire _pmpHomogeneous_T_257 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_258 = ~_pmpHomogeneous_T_257; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}] wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_17; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_17; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_259 = pmpHomogeneous_endsBeforeLower_5 \| pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_260 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_261 = _pmpHomogeneous_T_259 \| _pmpHomogeneous_T_260; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_262 = _pmpHomogeneous_T_258 \| _pmpHomogeneous_T_261; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_263 = _pmpHomogeneous_T_221 ? _pmpHomogeneous_T_256 : _pmpHomogeneous_T_262; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_264 = _pmpHomogeneous_T_220 & _pmpHomogeneous_T_263; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_265 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 & _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}] wire [31:0] _GEN_18 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_266; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_266 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_273; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_273 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_280; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_280 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_287; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_287 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_267 = ~_pmpHomogeneous_T_266; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_268 = {_pmpHomogeneous_T_267[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_269}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_271 = _pmpHomogeneous_T_270[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_272 = \|_pmpHomogeneous_T_271; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_274 = ~_pmpHomogeneous_T_273; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_275 = {_pmpHomogeneous_T_274[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_276}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_278 = _pmpHomogeneous_T_277[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_279 = \|_pmpHomogeneous_T_278; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_281 = ~_pmpHomogeneous_T_280; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_282 = {_pmpHomogeneous_T_281[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_283 = ~_pmpHomogeneous_T_282; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_284 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_283}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_286 = \|_pmpHomogeneous_T_285; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_288 = ~_pmpHomogeneous_T_287; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_289 = {_pmpHomogeneous_T_288[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_291 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_290}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_292 = _pmpHomogeneous_T_291[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_293 = \|_pmpHomogeneous_T_292; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_294 ? _pmpHomogeneous_T_279 : _pmpHomogeneous_T_272; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_297 = _pmpHomogeneous_T_296 ? _pmpHomogeneous_T_286 : _pmpHomogeneous_T_295; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_298 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_299 = _pmpHomogeneous_T_298 ? _pmpHomogeneous_T_293 : _pmpHomogeneous_T_297; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_300 = pmpHomogeneous_maskHomogeneous_6 \| _pmpHomogeneous_T_299; // @[package.scala:39:76] wire _pmpHomogeneous_T_301 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_302 = ~_pmpHomogeneous_T_301; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}] wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_19; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_19; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_303 = pmpHomogeneous_endsBeforeLower_6 \| pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_304 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_305 = _pmpHomogeneous_T_303 \| _pmpHomogeneous_T_304; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_306 = _pmpHomogeneous_T_302 \| _pmpHomogeneous_T_305; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_307 = _pmpHomogeneous_T_265 ? _pmpHomogeneous_T_300 : _pmpHomogeneous_T_306; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_308 = _pmpHomogeneous_T_264 & _pmpHomogeneous_T_307; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_309 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 & _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}] wire [31:0] _GEN_20 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_310; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_310 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_317; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_317 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_324; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_324 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_331; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_331 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_311 = ~_pmpHomogeneous_T_310; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_312 = {_pmpHomogeneous_T_311[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_313 = ~_pmpHomogeneous_T_312; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_314 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_313}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_315 = _pmpHomogeneous_T_314[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_316 = \|_pmpHomogeneous_T_315; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_318 = ~_pmpHomogeneous_T_317; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_319 = {_pmpHomogeneous_T_318[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_320 = ~_pmpHomogeneous_T_319; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_321 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_320}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_322 = _pmpHomogeneous_T_321[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_323 = \|_pmpHomogeneous_T_322; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_325 = ~_pmpHomogeneous_T_324; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_326 = {_pmpHomogeneous_T_325[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_327 = ~_pmpHomogeneous_T_326; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_328 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_327}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_329 = _pmpHomogeneous_T_328[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_330 = \|_pmpHomogeneous_T_329; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_332 = ~_pmpHomogeneous_T_331; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_333 = {_pmpHomogeneous_T_332[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_334 = ~_pmpHomogeneous_T_333; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_335 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_334}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_336 = _pmpHomogeneous_T_335[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_337 = \|_pmpHomogeneous_T_336; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_339 = _pmpHomogeneous_T_338 ? _pmpHomogeneous_T_323 : _pmpHomogeneous_T_316; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_341 = _pmpHomogeneous_T_340 ? _pmpHomogeneous_T_330 : _pmpHomogeneous_T_339; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_342 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_343 = _pmpHomogeneous_T_342 ? _pmpHomogeneous_T_337 : _pmpHomogeneous_T_341; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_344 = pmpHomogeneous_maskHomogeneous_7 \| _pmpHomogeneous_T_343; // @[package.scala:39:76] wire _pmpHomogeneous_T_345 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_346 = ~_pmpHomogeneous_T_345; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}] wire [55:0] _GEN_21 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_21; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_21; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_347 = pmpHomogeneous_endsBeforeLower_7 \| pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_348 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_349 = _pmpHomogeneous_T_347 \| _pmpHomogeneous_T_348; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_350 = _pmpHomogeneous_T_346 \| _pmpHomogeneous_T_349; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_351 = _pmpHomogeneous_T_309 ? _pmpHomogeneous_T_344 : _pmpHomogeneous_T_350; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire pmpHomogeneous = _pmpHomogeneous_T_308 & _pmpHomogeneous_T_351; // @[PMP.scala:118:8, :138:10] wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T \| _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_0_resp_bits_gpa_bits_T_3 = &aux_count; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 \| _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [16:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:27]; // @[PTW.scala:280:20, :343:49] wire [16:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:27]; // @[PTW.scala:280:20, :343:49] wire [26:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79] wire [26:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79] wire [26:0] _r_pte_T_18 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79] wire [26:0] _aux_pte_s1_ppns_T_1 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_21 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_3 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_11 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_11 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _r_pte_T_24 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _aux_pte_s1_ppns_T_5 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = {_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_12}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_15 = _io_requestor_0_resp_bits_gpa_bits_T_14 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_17 = _io_requestor_0_resp_bits_gpa_bits_T_16 ? _io_requestor_0_resp_bits_gpa_bits_T_13 : _io_requestor_0_resp_bits_gpa_bits_T_15; // @[package.scala:39:{76,86}] wire _io_requestor_0_resp_bits_gpa_bits_T_18 = &aux_count; // @[package.scala:39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_19 = _io_requestor_0_resp_bits_gpa_bits_T_18 ? _io_requestor_0_resp_bits_gpa_bits_T_13 : _io_requestor_0_resp_bits_gpa_bits_T_17; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_20 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_19; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_21 = {_io_requestor_0_resp_bits_gpa_bits_T_20, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_21[47:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T \| _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_3 = &aux_count; // @[PTW.scala:278:22, :566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 \| _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = {_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_12}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_15 = _io_requestor_1_resp_bits_gpa_bits_T_14 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_17 = _io_requestor_1_resp_bits_gpa_bits_T_16 ? _io_requestor_1_resp_bits_gpa_bits_T_13 : _io_requestor_1_resp_bits_gpa_bits_T_15; // @[package.scala:39:{76,86}] wire _io_requestor_1_resp_bits_gpa_bits_T_18 = &aux_count; // @[package.scala:39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_19 = _io_requestor_1_resp_bits_gpa_bits_T_18 ? _io_requestor_1_resp_bits_gpa_bits_T_13 : _io_requestor_1_resp_bits_gpa_bits_T_17; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_20 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_19; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_21 = {_io_requestor_1_resp_bits_gpa_bits_T_20, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_21[47:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _T_142 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _GEN_22 = ~(\|state) & _T_142; // @[Decoupled.scala:51:35] wire _satp_initial_count_T_2 = satp_mode[0]; // @[package.scala:163:13] wire [3:0] _satp_initial_count_T_3 = 4'h1 - {3'h0, _satp_initial_count_T_2}; // @[package.scala:163:13] wire [2:0] satp_initial_count = _satp_initial_count_T_3[2:0]; // @[PTW.scala:586:61] wire [2:0] _count_T_4 = satp_initial_count; // @[PTW.scala:586:61, :596:27] wire [43:0] aux_ppn = {8'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26] wire [5:0] resp_gf_idxs_0 = aux_ppn[43:38]; // @[PTW.scala:589:38, :787:58] wire [14:0] resp_gf_idxs_1 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_1 = resp_gf_idxs_1; // @[package.scala:43:40] wire [14:0] _resp_gf_WIRE_0 = {9'h0, resp_gf_idxs_0}; // @[package.scala:43:40] wire _resp_gf_T_2 = \|_resp_gf_WIRE_1; // @[package.scala:43:40] wire _gpa_pgoff_T = &aux_count; // @[PTW.scala:278:22, :566:60, :615:36] wire [38:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [38:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 39'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_23 = _GEN_0 + 3'h1; // @[PTW.scala:324:40, :624:24] wire [2:0] _count_T_5; // @[PTW.scala:624:24] assign _count_T_5 = _GEN_23; // @[PTW.scala:624:24] wire [2:0] _count_T_7; // @[PTW.scala:696:22] assign _count_T_7 = _GEN_23; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_23; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_6 = _count_T_5[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_153 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire _T_154 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _GEN_24 = _T_165 \| _T_153; // @[PTW.scala:377:24, :393:26, :583:18] assign io_dpath_perf_pte_miss_0 = ~(~(\|state) \| _GEN_24) & _T_154 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h3; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFC0000 : 44'hFFFF8000000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFE00 : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [16:0] _merged_pte_stage1_ppns_T = pte_ppn[43:27]; // @[PTW.scala:305:26, :663:64] wire [16:0] r_pte_idxs_1_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :663:64, :778:58] wire [16:0] _aux_pte_s1_ppns_T = pte_ppn[43:27]; // @[PTW.scala:305:26, :663:64, :744:62] wire [26:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[26:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [25:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_4 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_4 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_5 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_2 = {_merged_pte_stage1_ppns_T_4, _merged_pte_stage1_ppns_T_5}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? merged_pte_stage1_ppns_2 : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire [3:0] _r_pte_count_T_3 = 4'h1 - {3'h0, _r_pte_count_T_2}; // @[package.scala:163:13] wire [2:0] r_pte_count = _r_pte_count_T_3[2:0]; // @[PTW.scala:777:44] wire [2:0] _r_pte_lsbs_truncIdx_T = r_pte_count; // @[package.scala:38:21] wire r_pte_lsbs_truncIdx = _r_pte_lsbs_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_lsbs_T = r_pte_lsbs_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26] wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}] assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}] wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26] assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73] wire [3:0] _r_pte_count_T_7 = 4'h1 - {3'h0, _r_pte_count_T_6}; // @[package.scala:163:13] wire [2:0] r_pte_count_1 = _r_pte_count_T_7[2:0]; // @[PTW.scala:777:44] wire [2:0] _r_pte_lsbs_truncIdx_T_1 = r_pte_count_1; // @[package.scala:38:21] wire [7:0] r_pte_idxs_0_1 = pte_ppn[43:36]; // @[PTW.scala:305:26, :778:58] wire r_pte_lsbs_truncIdx_1 = _r_pte_lsbs_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _r_pte_lsbs_T_2 = r_pte_lsbs_truncIdx_1; // @[package.scala:38:47, :39:86] wire [16:0] _r_pte_lsbs_T_3 = _r_pte_lsbs_T_2 ? r_pte_idxs_1_1 : {9'h0, r_pte_idxs_0_1}; // @[package.scala:39:{76,86}] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = _r_pte_lsbs_T_3[1:0]; // @[package.scala:39:76] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [16:0] _r_pte_T_17 = r_pte_ppn[43:27]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [25:0] _r_pte_T_20 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_23 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_25 = {_r_pte_T_23, _r_pte_T_24}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _r_pte_T_27 = _r_pte_T_26 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] _r_pte_T_29 = _r_pte_T_28 ? _r_pte_T_25 : _r_pte_T_27; // @[package.scala:39:{76,86}] wire _r_pte_T_30 = &count; // @[package.scala:39:86] wire [43:0] _r_pte_T_31 = _r_pte_T_30 ? _r_pte_T_25 : _r_pte_T_29; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_31; // @[package.scala:39:76] wire _r_pte_T_32 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_33_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_33_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_33_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_34_reserved_for_future = _r_pte_T_32 ? _r_pte_T_33_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_34_ppn = _r_pte_T_32 ? _r_pte_T_33_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_34_reserved_for_software = _r_pte_T_32 ? _r_pte_T_33_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_34_d = _r_pte_T_32 ? _r_pte_T_33_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_34_a = _r_pte_T_32 ? _r_pte_T_33_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_34_g = _r_pte_T_32 ? _r_pte_T_33_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_34_u = _r_pte_T_32 ? _r_pte_T_33_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_34_x = _r_pte_T_32 ? _r_pte_T_33_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_34_w = _r_pte_T_32 ? _r_pte_T_33_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_34_r = _r_pte_T_32 ? _r_pte_T_33_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_34_v = _r_pte_T_32 ? _r_pte_T_33_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_35_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_34_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_35_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_34_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_35_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_34_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_34_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_34_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_34_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_34_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_34_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_34_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_34_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_34_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_36_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_35_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_36_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_35_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_36_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_35_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_35_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_35_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_35_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_35_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_35_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_35_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_35_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_35_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_37_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_36_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_37_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_36_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_37_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_36_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_d = do_switch ? r_pte_pte_2_d : _r_pte_T_36_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_a = do_switch ? r_pte_pte_2_a : _r_pte_T_36_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_g = do_switch ? r_pte_pte_2_g : _r_pte_T_36_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_u = do_switch ? r_pte_pte_2_u : _r_pte_T_36_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_x = do_switch ? r_pte_pte_2_x : _r_pte_T_36_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_w = do_switch ? r_pte_pte_2_w : _r_pte_T_36_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_r = do_switch ? r_pte_pte_2_r : _r_pte_T_36_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_v = do_switch ? r_pte_pte_2_v : _r_pte_T_36_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_38_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_37_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8] wire [43:0] _r_pte_T_38_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_37_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire [1:0] _r_pte_T_38_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_37_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_d = ~_r_pte_T_7 & _r_pte_T_37_d; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_a = ~_r_pte_T_7 & _r_pte_T_37_a; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_g = ~_r_pte_T_7 & _r_pte_T_37_g; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_u = ~_r_pte_T_7 & _r_pte_T_37_u; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_x = ~_r_pte_T_7 & _r_pte_T_37_x; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_w = ~_r_pte_T_7 & _r_pte_T_37_w; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_r = ~_r_pte_T_7 & _r_pte_T_37_r; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_v = ~_r_pte_T_7 & _r_pte_T_37_v; // @[PTW.scala:674:{8,25}, :676:8] wire [9:0] _r_pte_T_39_reserved_for_future = _r_pte_T_38_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_39_ppn = _r_pte_T_38_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_39_reserved_for_software = _r_pte_T_38_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_d = _r_pte_T_38_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_a = _r_pte_T_38_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_g = _r_pte_T_38_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_u = _r_pte_T_38_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_x = _r_pte_T_38_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_w = _r_pte_T_38_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_r = _r_pte_T_38_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_v = _r_pte_T_38_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_40_reserved_for_future = _r_pte_T_39_reserved_for_future; // @[PTW.scala:670:8, :672:8] wire [43:0] _r_pte_T_40_ppn = _r_pte_T_39_ppn; // @[PTW.scala:670:8, :672:8] wire [1:0] _r_pte_T_40_reserved_for_software = _r_pte_T_39_reserved_for_software; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_d = _r_pte_T_39_d; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_a = _r_pte_T_39_a; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_g = _r_pte_T_39_g; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_u = _r_pte_T_39_u; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_x = _r_pte_T_39_x; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_w = _r_pte_T_39_w; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_r = _r_pte_T_39_r; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_v = _r_pte_T_39_v; // @[PTW.scala:670:8, :672:8] wire [1:0] _count_T_8 = _count_T_7[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r \| _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r \| _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(\|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 \| _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = \|pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_181 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_181 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T = &count; // @[package.scala:39:86] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_7 = &aux_count; // @[PTW.scala:278:22, :566:60, :715:40] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r \| _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r \| _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 \| _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_25 = traverse \| _T_181; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(\|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r \| _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_4 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_5 = gf \| _resp_gf_T_4; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r \| _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T \| _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r \| _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T \| _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r \| _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T \| _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_122 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} wire _in_flight_WIRE : UInt<1>[10] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) connect _in_flight_WIRE[8], UInt<1>(0h0) connect _in_flight_WIRE[9], UInt<1>(0h0) regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_22 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_23 = and(_T_21, _T_22) node _T_24 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_25 = and(_T_23, _T_24) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_27 = and(_T_25, _T_26) node _T_28 = or(_T_20, _T_27) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_28, UInt<1>(0h1), "") : assert_4 node _T_32 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(_T_32, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_51 = and(_T_49, _T_50) node _T_52 = or(_T_44, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_52, UInt<1>(0h1), "") : assert_6 node _T_56 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_58 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(_T_56, _T_63) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_64, UInt<1>(0h1), "") : assert_7 node _T_68 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_75 = and(_T_73, _T_74) node _T_76 = or(_T_68, _T_75) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_76, UInt<1>(0h1), "") : assert_8 node _T_80 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_87 = and(_T_85, _T_86) node _T_88 = or(_T_80, _T_87) node _T_89 = asUInt(reset) node _T_90 = eq(_T_89, UInt<1>(0h0)) when _T_90 : node _T_91 = eq(_T_88, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9 assert(clock, _T_88, UInt<1>(0h1), "") : assert_9 node _T_92 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_94 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_92, _T_99) node _T_101 = asUInt(reset) node _T_102 = eq(_T_101, UInt<1>(0h0)) when _T_102 : node _T_103 = eq(_T_100, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10 assert(clock, _T_100, UInt<1>(0h1), "") : assert_10	module NoCMonitor_122( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_78 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_78( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_9 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_18 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_19 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_9( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_17 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock inst q of Queue3_EgressFlit_17 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0hc), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h8), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h6), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0he), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h0), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_32 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h4), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_33 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h2), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_34 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0ha), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_35 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_29) node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_30) node _q_io_enq_bits_ingress_id_T_39 = or(_q_io_enq_bits_ingress_id_T_38, _q_io_enq_bits_ingress_id_T_31) node _q_io_enq_bits_ingress_id_T_40 = or(_q_io_enq_bits_ingress_id_T_39, _q_io_enq_bits_ingress_id_T_32) node _q_io_enq_bits_ingress_id_T_41 = or(_q_io_enq_bits_ingress_id_T_40, _q_io_enq_bits_ingress_id_T_33) node _q_io_enq_bits_ingress_id_T_42 = or(_q_io_enq_bits_ingress_id_T_41, _q_io_enq_bits_ingress_id_T_34) node _q_io_enq_bits_ingress_id_T_43 = or(_q_io_enq_bits_ingress_id_T_42, _q_io_enq_bits_ingress_id_T_35) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_43 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow

module EgressUnit_17( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_25 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to this FIRRTL code module PE_282 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_26 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_282( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_26 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_103 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_113 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_103( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_113 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0h80))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 64, 39) node _adjustedSig_T_1 = bits(io.in.sig, 38, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [9:0] _sAdjustedExp_T = {io_in_sExp_0[8], io_in_sExp_0} + 10'h80; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [25:0] _adjustedSig_T = io_in_sig_0[64:39]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [38:0] _adjustedSig_T_1 = io_in_sig_0[38:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_15 = {25'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ReqGen : input clock : Clock input reset : Reset output io : { flip send_reqs : UInt<1>, sent_done : UInt<1>, req_fire : UInt<1>, flip global_stream_info : { valid : UInt<1>, bits : { stream_cnt : UInt<5>, addr_range : UInt<64>, max_reqs : UInt<64>}}, flip local_stream_info : { valid : UInt<1>, bits : { data : { start_addr : UInt<64>, stride : UInt<64>, stream_type : UInt<3>}, idx : UInt<4>}}, req : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : { addr : UInt, cmd : UInt, size : UInt, data : UInt<128>}, idx : UInt<4>}}} inst rand_val_prng of MaxPeriodFibonacciLFSR_9 connect rand_val_prng.clock, clock connect rand_val_prng.reset, reset connect rand_val_prng.io.seed.valid, UInt<1>(0h0) invalidate rand_val_prng.io.seed.bits[0] invalidate rand_val_prng.io.seed.bits[1] invalidate rand_val_prng.io.seed.bits[2] invalidate rand_val_prng.io.seed.bits[3] invalidate rand_val_prng.io.seed.bits[4] invalidate rand_val_prng.io.seed.bits[5] invalidate rand_val_prng.io.seed.bits[6] invalidate rand_val_prng.io.seed.bits[7] invalidate rand_val_prng.io.seed.bits[8] invalidate rand_val_prng.io.seed.bits[9] invalidate rand_val_prng.io.seed.bits[10] invalidate rand_val_prng.io.seed.bits[11] invalidate rand_val_prng.io.seed.bits[12] invalidate rand_val_prng.io.seed.bits[13] invalidate rand_val_prng.io.seed.bits[14] invalidate rand_val_prng.io.seed.bits[15] invalidate rand_val_prng.io.seed.bits[16] invalidate rand_val_prng.io.seed.bits[17] invalidate rand_val_prng.io.seed.bits[18] invalidate rand_val_prng.io.seed.bits[19] invalidate rand_val_prng.io.seed.bits[20] invalidate rand_val_prng.io.seed.bits[21] invalidate rand_val_prng.io.seed.bits[22] invalidate rand_val_prng.io.seed.bits[23] invalidate rand_val_prng.io.seed.bits[24] invalidate rand_val_prng.io.seed.bits[25] invalidate rand_val_prng.io.seed.bits[26] invalidate rand_val_prng.io.seed.bits[27] invalidate rand_val_prng.io.seed.bits[28] invalidate rand_val_prng.io.seed.bits[29] connect rand_val_prng.io.increment, UInt<1>(0h1) node rand_val_lo_lo_lo_hi = cat(rand_val_prng.io.out[2], rand_val_prng.io.out[1]) node rand_val_lo_lo_lo = cat(rand_val_lo_lo_lo_hi, rand_val_prng.io.out[0]) node rand_val_lo_lo_hi_lo = cat(rand_val_prng.io.out[4], rand_val_prng.io.out[3]) node rand_val_lo_lo_hi_hi = cat(rand_val_prng.io.out[6], rand_val_prng.io.out[5]) node rand_val_lo_lo_hi = cat(rand_val_lo_lo_hi_hi, rand_val_lo_lo_hi_lo) node rand_val_lo_lo = cat(rand_val_lo_lo_hi, rand_val_lo_lo_lo) node rand_val_lo_hi_lo_lo = cat(rand_val_prng.io.out[8], rand_val_prng.io.out[7]) node rand_val_lo_hi_lo_hi = cat(rand_val_prng.io.out[10], rand_val_prng.io.out[9]) node rand_val_lo_hi_lo = cat(rand_val_lo_hi_lo_hi, rand_val_lo_hi_lo_lo) node rand_val_lo_hi_hi_lo = cat(rand_val_prng.io.out[12], rand_val_prng.io.out[11]) node rand_val_lo_hi_hi_hi = cat(rand_val_prng.io.out[14], rand_val_prng.io.out[13]) node rand_val_lo_hi_hi = cat(rand_val_lo_hi_hi_hi, rand_val_lo_hi_hi_lo) node rand_val_lo_hi = cat(rand_val_lo_hi_hi, rand_val_lo_hi_lo) node rand_val_lo = cat(rand_val_lo_hi, rand_val_lo_lo) node rand_val_hi_lo_lo_hi = cat(rand_val_prng.io.out[17], rand_val_prng.io.out[16]) node rand_val_hi_lo_lo = cat(rand_val_hi_lo_lo_hi, rand_val_prng.io.out[15]) node rand_val_hi_lo_hi_lo = cat(rand_val_prng.io.out[19], rand_val_prng.io.out[18]) node rand_val_hi_lo_hi_hi = cat(rand_val_prng.io.out[21], rand_val_prng.io.out[20]) node rand_val_hi_lo_hi = cat(rand_val_hi_lo_hi_hi, rand_val_hi_lo_hi_lo) node rand_val_hi_lo = cat(rand_val_hi_lo_hi, rand_val_hi_lo_lo) node rand_val_hi_hi_lo_lo = cat(rand_val_prng.io.out[23], rand_val_prng.io.out[22]) node rand_val_hi_hi_lo_hi = cat(rand_val_prng.io.out[25], rand_val_prng.io.out[24]) node rand_val_hi_hi_lo = cat(rand_val_hi_hi_lo_hi, rand_val_hi_hi_lo_lo) node rand_val_hi_hi_hi_lo = cat(rand_val_prng.io.out[27], rand_val_prng.io.out[26]) node rand_val_hi_hi_hi_hi = cat(rand_val_prng.io.out[29], rand_val_prng.io.out[28]) node rand_val_hi_hi_hi = cat(rand_val_hi_hi_hi_hi, rand_val_hi_hi_hi_lo) node rand_val_hi_hi = cat(rand_val_hi_hi_hi, rand_val_hi_hi_lo) node rand_val_hi = cat(rand_val_hi_hi, rand_val_hi_lo) node rand_val = cat(rand_val_hi, rand_val_lo) regreset stream_cnt : UInt<5>, clock, reset, UInt<5>(0h0) regreset addr_range : UInt<64>, clock, reset, UInt<64>(0h0) regreset max_reqs : UInt<64>, clock, reset, UInt<64>(0h0) wire _start_addr_WIRE : UInt<64>[16] connect _start_addr_WIRE[0], UInt<64>(0h0) connect _start_addr_WIRE[1], UInt<64>(0h0) connect _start_addr_WIRE[2], UInt<64>(0h0) connect _start_addr_WIRE[3], UInt<64>(0h0) connect _start_addr_WIRE[4], UInt<64>(0h0) connect _start_addr_WIRE[5], UInt<64>(0h0) connect _start_addr_WIRE[6], UInt<64>(0h0) connect _start_addr_WIRE[7], UInt<64>(0h0) connect _start_addr_WIRE[8], UInt<64>(0h0) connect _start_addr_WIRE[9], UInt<64>(0h0) connect _start_addr_WIRE[10], UInt<64>(0h0) connect _start_addr_WIRE[11], UInt<64>(0h0) connect _start_addr_WIRE[12], UInt<64>(0h0) connect _start_addr_WIRE[13], UInt<64>(0h0) connect _start_addr_WIRE[14], UInt<64>(0h0) connect _start_addr_WIRE[15], UInt<64>(0h0) regreset start_addr : UInt<64>[16], clock, reset, _start_addr_WIRE wire _stride_WIRE : UInt<64>[16] connect _stride_WIRE[0], UInt<64>(0h0) connect _stride_WIRE[1], UInt<64>(0h0) connect _stride_WIRE[2], UInt<64>(0h0) connect _stride_WIRE[3], UInt<64>(0h0) connect _stride_WIRE[4], UInt<64>(0h0) connect _stride_WIRE[5], UInt<64>(0h0) connect _stride_WIRE[6], UInt<64>(0h0) connect _stride_WIRE[7], UInt<64>(0h0) connect _stride_WIRE[8], UInt<64>(0h0) connect _stride_WIRE[9], UInt<64>(0h0) connect _stride_WIRE[10], UInt<64>(0h0) connect _stride_WIRE[11], UInt<64>(0h0) connect _stride_WIRE[12], UInt<64>(0h0) connect _stride_WIRE[13], UInt<64>(0h0) connect _stride_WIRE[14], UInt<64>(0h0) connect _stride_WIRE[15], UInt<64>(0h0) regreset stride : UInt<64>[16], clock, reset, _stride_WIRE wire _stream_type_WIRE : UInt<3>[16] connect _stream_type_WIRE[0], UInt<3>(0h0) connect _stream_type_WIRE[1], UInt<3>(0h0) connect _stream_type_WIRE[2], UInt<3>(0h0) connect _stream_type_WIRE[3], UInt<3>(0h0) connect _stream_type_WIRE[4], UInt<3>(0h0) connect _stream_type_WIRE[5], UInt<3>(0h0) connect _stream_type_WIRE[6], UInt<3>(0h0) connect _stream_type_WIRE[7], UInt<3>(0h0) connect _stream_type_WIRE[8], UInt<3>(0h0) connect _stream_type_WIRE[9], UInt<3>(0h0) connect _stream_type_WIRE[10], UInt<3>(0h0) connect _stream_type_WIRE[11], UInt<3>(0h0) connect _stream_type_WIRE[12], UInt<3>(0h0) connect _stream_type_WIRE[13], UInt<3>(0h0) connect _stream_type_WIRE[14], UInt<3>(0h0) connect _stream_type_WIRE[15], UInt<3>(0h0) regreset stream_type : UInt<3>[16], clock, reset, _stream_type_WIRE wire _end_addr_WIRE : UInt<64>[16] connect _end_addr_WIRE[0], UInt<64>(0h0) connect _end_addr_WIRE[1], UInt<64>(0h0) connect _end_addr_WIRE[2], UInt<64>(0h0) connect _end_addr_WIRE[3], UInt<64>(0h0) connect _end_addr_WIRE[4], UInt<64>(0h0) connect _end_addr_WIRE[5], UInt<64>(0h0) connect _end_addr_WIRE[6], UInt<64>(0h0) connect _end_addr_WIRE[7], UInt<64>(0h0) connect _end_addr_WIRE[8], UInt<64>(0h0) connect _end_addr_WIRE[9], UInt<64>(0h0) connect _end_addr_WIRE[10], UInt<64>(0h0) connect _end_addr_WIRE[11], UInt<64>(0h0) connect _end_addr_WIRE[12], UInt<64>(0h0) connect _end_addr_WIRE[13], UInt<64>(0h0) connect _end_addr_WIRE[14], UInt<64>(0h0) connect _end_addr_WIRE[15], UInt<64>(0h0) regreset end_addr : UInt<64>[16], clock, reset, _end_addr_WIRE wire _cur_addr_WIRE : UInt<64>[16] connect _cur_addr_WIRE[0], UInt<64>(0h0) connect _cur_addr_WIRE[1], UInt<64>(0h0) connect _cur_addr_WIRE[2], UInt<64>(0h0) connect _cur_addr_WIRE[3], UInt<64>(0h0) connect _cur_addr_WIRE[4], UInt<64>(0h0) connect _cur_addr_WIRE[5], UInt<64>(0h0) connect _cur_addr_WIRE[6], UInt<64>(0h0) connect _cur_addr_WIRE[7], UInt<64>(0h0) connect _cur_addr_WIRE[8], UInt<64>(0h0) connect _cur_addr_WIRE[9], UInt<64>(0h0) connect _cur_addr_WIRE[10], UInt<64>(0h0) connect _cur_addr_WIRE[11], UInt<64>(0h0) connect _cur_addr_WIRE[12], UInt<64>(0h0) connect _cur_addr_WIRE[13], UInt<64>(0h0) connect _cur_addr_WIRE[14], UInt<64>(0h0) connect _cur_addr_WIRE[15], UInt<64>(0h0) regreset cur_addr : UInt<64>[16], clock, reset, _cur_addr_WIRE node _io_req_fire_T = and(io.req.ready, io.req.valid) connect io.req_fire, _io_req_fire_T connect io.sent_done, UInt<1>(0h0) connect io.req.valid, UInt<1>(0h0) connect io.req.bits.data.addr, UInt<1>(0h0) connect io.req.bits.data.cmd, UInt<1>(0h0) connect io.req.bits.data.size, UInt<3>(0h4) connect io.req.bits.data.data, UInt<1>(0h0) connect io.req.bits.idx, UInt<1>(0h0) when io.global_stream_info.valid : connect stream_cnt, io.global_stream_info.bits.stream_cnt connect addr_range, io.global_stream_info.bits.addr_range connect max_reqs, io.global_stream_info.bits.max_reqs regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Global Stream Info, stream_cnt: %d, addr_range: 0x%x, max_reqs: %d\n", io.global_stream_info.bits.stream_cnt, io.global_stream_info.bits.addr_range, io.global_stream_info.bits.max_reqs) : printf_1 when io.local_stream_info.valid : connect start_addr[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.start_addr connect stride[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.stride connect stream_type[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.stream_type node _end_addr_T = add(io.local_stream_info.bits.data.start_addr, addr_range) node _end_addr_T_1 = tail(_end_addr_T, 1) connect end_addr[io.local_stream_info.bits.idx], _end_addr_T_1 connect cur_addr[io.local_stream_info.bits.idx], io.local_stream_info.bits.data.start_addr regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Local Stream Info[%d], start_addr: 0x%x, stride: 0x%x, stream_type: %d\n", io.local_stream_info.bits.idx, io.local_stream_info.bits.data.start_addr, io.local_stream_info.bits.data.stride, io.local_stream_info.bits.data.stream_type) : printf_3 regreset s_idx : UInt<5>, clock, reset, UInt<5>(0h0) wire _s_sent_WIRE : UInt<64>[16] connect _s_sent_WIRE[0], UInt<64>(0h0) connect _s_sent_WIRE[1], UInt<64>(0h0) connect _s_sent_WIRE[2], UInt<64>(0h0) connect _s_sent_WIRE[3], UInt<64>(0h0) connect _s_sent_WIRE[4], UInt<64>(0h0) connect _s_sent_WIRE[5], UInt<64>(0h0) connect _s_sent_WIRE[6], UInt<64>(0h0) connect _s_sent_WIRE[7], UInt<64>(0h0) connect _s_sent_WIRE[8], UInt<64>(0h0) connect _s_sent_WIRE[9], UInt<64>(0h0) connect _s_sent_WIRE[10], UInt<64>(0h0) connect _s_sent_WIRE[11], UInt<64>(0h0) connect _s_sent_WIRE[12], UInt<64>(0h0) connect _s_sent_WIRE[13], UInt<64>(0h0) connect _s_sent_WIRE[14], UInt<64>(0h0) connect _s_sent_WIRE[15], UInt<64>(0h0) regreset s_sent : UInt<64>[16], clock, reset, _s_sent_WIRE wire _s_sent_done_WIRE : UInt<1>[16] connect _s_sent_done_WIRE[0], UInt<1>(0h0) connect _s_sent_done_WIRE[1], UInt<1>(0h0) connect _s_sent_done_WIRE[2], UInt<1>(0h0) connect _s_sent_done_WIRE[3], UInt<1>(0h0) connect _s_sent_done_WIRE[4], UInt<1>(0h0) connect _s_sent_done_WIRE[5], UInt<1>(0h0) connect _s_sent_done_WIRE[6], UInt<1>(0h0) connect _s_sent_done_WIRE[7], UInt<1>(0h0) connect _s_sent_done_WIRE[8], UInt<1>(0h0) connect _s_sent_done_WIRE[9], UInt<1>(0h0) connect _s_sent_done_WIRE[10], UInt<1>(0h0) connect _s_sent_done_WIRE[11], UInt<1>(0h0) connect _s_sent_done_WIRE[12], UInt<1>(0h0) connect _s_sent_done_WIRE[13], UInt<1>(0h0) connect _s_sent_done_WIRE[14], UInt<1>(0h0) connect _s_sent_done_WIRE[15], UInt<1>(0h0) regreset s_sent_done : UInt<1>[16], clock, reset, _s_sent_done_WIRE when io.send_reqs : node _cur_stream_T = bits(s_idx, 3, 0) wire addr : UInt<64> connect addr, UInt<64>(0h0) node _data_T = dshl(UInt<1>(0h1), UInt<8>(0h80)) node _data_T_1 = sub(_data_T, UInt<1>(0h1)) node _data_T_2 = tail(_data_T_1, 1) node _data_T_3 = dshl(UInt<1>(0h1), s_idx) node data = xor(_data_T_2, _data_T_3) node _T_8 = eq(stream_type[_cur_stream_T], UInt<3>(0h4)) node _T_9 = eq(stream_type[_cur_stream_T], UInt<3>(0h5)) node _T_10 = or(_T_8, _T_9) when _T_10 : node _msb_T = shl(UInt<32>(0hffffffff), 32) node _msb_T_1 = xor(UInt<64>(0hffffffffffffffff), _msb_T) node _msb_T_2 = shr(addr_range, 32) node _msb_T_3 = and(_msb_T_2, _msb_T_1) node _msb_T_4 = bits(addr_range, 31, 0) node _msb_T_5 = shl(_msb_T_4, 32) node _msb_T_6 = not(_msb_T_1) node _msb_T_7 = and(_msb_T_5, _msb_T_6) node _msb_T_8 = or(_msb_T_3, _msb_T_7) node _msb_T_9 = bits(_msb_T_1, 47, 0) node _msb_T_10 = shl(_msb_T_9, 16) node _msb_T_11 = xor(_msb_T_1, _msb_T_10) node _msb_T_12 = shr(_msb_T_8, 16) node _msb_T_13 = and(_msb_T_12, _msb_T_11) node _msb_T_14 = bits(_msb_T_8, 47, 0) node _msb_T_15 = shl(_msb_T_14, 16) node _msb_T_16 = not(_msb_T_11) node _msb_T_17 = and(_msb_T_15, _msb_T_16) node _msb_T_18 = or(_msb_T_13, _msb_T_17) node _msb_T_19 = bits(_msb_T_11, 55, 0) node _msb_T_20 = shl(_msb_T_19, 8) node _msb_T_21 = xor(_msb_T_11, _msb_T_20) node _msb_T_22 = shr(_msb_T_18, 8) node _msb_T_23 = and(_msb_T_22, _msb_T_21) node _msb_T_24 = bits(_msb_T_18, 55, 0) node _msb_T_25 = shl(_msb_T_24, 8) node _msb_T_26 = not(_msb_T_21) node _msb_T_27 = and(_msb_T_25, _msb_T_26) node _msb_T_28 = or(_msb_T_23, _msb_T_27) node _msb_T_29 = bits(_msb_T_21, 59, 0) node _msb_T_30 = shl(_msb_T_29, 4) node _msb_T_31 = xor(_msb_T_21, _msb_T_30) node _msb_T_32 = shr(_msb_T_28, 4) node _msb_T_33 = and(_msb_T_32, _msb_T_31) node _msb_T_34 = bits(_msb_T_28, 59, 0) node _msb_T_35 = shl(_msb_T_34, 4) node _msb_T_36 = not(_msb_T_31) node _msb_T_37 = and(_msb_T_35, _msb_T_36) node _msb_T_38 = or(_msb_T_33, _msb_T_37) node _msb_T_39 = bits(_msb_T_31, 61, 0) node _msb_T_40 = shl(_msb_T_39, 2) node _msb_T_41 = xor(_msb_T_31, _msb_T_40) node _msb_T_42 = shr(_msb_T_38, 2) node _msb_T_43 = and(_msb_T_42, _msb_T_41) node _msb_T_44 = bits(_msb_T_38, 61, 0) node _msb_T_45 = shl(_msb_T_44, 2) node _msb_T_46 = not(_msb_T_41) node _msb_T_47 = and(_msb_T_45, _msb_T_46) node _msb_T_48 = or(_msb_T_43, _msb_T_47) node _msb_T_49 = bits(_msb_T_41, 62, 0) node _msb_T_50 = shl(_msb_T_49, 1) node _msb_T_51 = xor(_msb_T_41, _msb_T_50) node _msb_T_52 = shr(_msb_T_48, 1) node _msb_T_53 = and(_msb_T_52, _msb_T_51) node _msb_T_54 = bits(_msb_T_48, 62, 0) node _msb_T_55 = shl(_msb_T_54, 1) node _msb_T_56 = not(_msb_T_51) node _msb_T_57 = and(_msb_T_55, _msb_T_56) node _msb_T_58 = or(_msb_T_53, _msb_T_57) node _msb_T_59 = bits(_msb_T_58, 0, 0) node _msb_T_60 = bits(_msb_T_58, 1, 1) node _msb_T_61 = bits(_msb_T_58, 2, 2) node _msb_T_62 = bits(_msb_T_58, 3, 3) node _msb_T_63 = bits(_msb_T_58, 4, 4) node _msb_T_64 = bits(_msb_T_58, 5, 5) node _msb_T_65 = bits(_msb_T_58, 6, 6) node _msb_T_66 = bits(_msb_T_58, 7, 7) node _msb_T_67 = bits(_msb_T_58, 8, 8) node _msb_T_68 = bits(_msb_T_58, 9, 9) node _msb_T_69 = bits(_msb_T_58, 10, 10) node _msb_T_70 = bits(_msb_T_58, 11, 11) node _msb_T_71 = bits(_msb_T_58, 12, 12) node _msb_T_72 = bits(_msb_T_58, 13, 13) node _msb_T_73 = bits(_msb_T_58, 14, 14) node _msb_T_74 = bits(_msb_T_58, 15, 15) node _msb_T_75 = bits(_msb_T_58, 16, 16) node _msb_T_76 = bits(_msb_T_58, 17, 17) node _msb_T_77 = bits(_msb_T_58, 18, 18) node _msb_T_78 = bits(_msb_T_58, 19, 19) node _msb_T_79 = bits(_msb_T_58, 20, 20) node _msb_T_80 = bits(_msb_T_58, 21, 21) node _msb_T_81 = bits(_msb_T_58, 22, 22) node _msb_T_82 = bits(_msb_T_58, 23, 23) node _msb_T_83 = bits(_msb_T_58, 24, 24) node _msb_T_84 = bits(_msb_T_58, 25, 25) node _msb_T_85 = bits(_msb_T_58, 26, 26) node _msb_T_86 = bits(_msb_T_58, 27, 27) node _msb_T_87 = bits(_msb_T_58, 28, 28) node _msb_T_88 = bits(_msb_T_58, 29, 29) node _msb_T_89 = bits(_msb_T_58, 30, 30) node _msb_T_90 = bits(_msb_T_58, 31, 31) node _msb_T_91 = bits(_msb_T_58, 32, 32) node _msb_T_92 = bits(_msb_T_58, 33, 33) node _msb_T_93 = bits(_msb_T_58, 34, 34) node _msb_T_94 = bits(_msb_T_58, 35, 35) node _msb_T_95 = bits(_msb_T_58, 36, 36) node _msb_T_96 = bits(_msb_T_58, 37, 37) node _msb_T_97 = bits(_msb_T_58, 38, 38) node _msb_T_98 = bits(_msb_T_58, 39, 39) node _msb_T_99 = bits(_msb_T_58, 40, 40) node _msb_T_100 = bits(_msb_T_58, 41, 41) node _msb_T_101 = bits(_msb_T_58, 42, 42) node _msb_T_102 = bits(_msb_T_58, 43, 43) node _msb_T_103 = bits(_msb_T_58, 44, 44) node _msb_T_104 = bits(_msb_T_58, 45, 45) node _msb_T_105 = bits(_msb_T_58, 46, 46) node _msb_T_106 = bits(_msb_T_58, 47, 47) node _msb_T_107 = bits(_msb_T_58, 48, 48) node _msb_T_108 = bits(_msb_T_58, 49, 49) node _msb_T_109 = bits(_msb_T_58, 50, 50) node _msb_T_110 = bits(_msb_T_58, 51, 51) node _msb_T_111 = bits(_msb_T_58, 52, 52) node _msb_T_112 = bits(_msb_T_58, 53, 53) node _msb_T_113 = bits(_msb_T_58, 54, 54) node _msb_T_114 = bits(_msb_T_58, 55, 55) node _msb_T_115 = bits(_msb_T_58, 56, 56) node _msb_T_116 = bits(_msb_T_58, 57, 57) node _msb_T_117 = bits(_msb_T_58, 58, 58) node _msb_T_118 = bits(_msb_T_58, 59, 59) node _msb_T_119 = bits(_msb_T_58, 60, 60) node _msb_T_120 = bits(_msb_T_58, 61, 61) node _msb_T_121 = bits(_msb_T_58, 62, 62) node _msb_T_122 = bits(_msb_T_58, 63, 63) node _msb_T_123 = mux(_msb_T_121, UInt<6>(0h3e), UInt<6>(0h3f)) node _msb_T_124 = mux(_msb_T_120, UInt<6>(0h3d), _msb_T_123) node _msb_T_125 = mux(_msb_T_119, UInt<6>(0h3c), _msb_T_124) node _msb_T_126 = mux(_msb_T_118, UInt<6>(0h3b), _msb_T_125) node _msb_T_127 = mux(_msb_T_117, UInt<6>(0h3a), _msb_T_126) node _msb_T_128 = mux(_msb_T_116, UInt<6>(0h39), _msb_T_127) node _msb_T_129 = mux(_msb_T_115, UInt<6>(0h38), _msb_T_128) node _msb_T_130 = mux(_msb_T_114, UInt<6>(0h37), _msb_T_129) node _msb_T_131 = mux(_msb_T_113, UInt<6>(0h36), _msb_T_130) node _msb_T_132 = mux(_msb_T_112, UInt<6>(0h35), _msb_T_131) node _msb_T_133 = mux(_msb_T_111, UInt<6>(0h34), _msb_T_132) node _msb_T_134 = mux(_msb_T_110, UInt<6>(0h33), _msb_T_133) node _msb_T_135 = mux(_msb_T_109, UInt<6>(0h32), _msb_T_134) node _msb_T_136 = mux(_msb_T_108, UInt<6>(0h31), _msb_T_135) node _msb_T_137 = mux(_msb_T_107, UInt<6>(0h30), _msb_T_136) node _msb_T_138 = mux(_msb_T_106, UInt<6>(0h2f), _msb_T_137) node _msb_T_139 = mux(_msb_T_105, UInt<6>(0h2e), _msb_T_138) node _msb_T_140 = mux(_msb_T_104, UInt<6>(0h2d), _msb_T_139) node _msb_T_141 = mux(_msb_T_103, UInt<6>(0h2c), _msb_T_140) node _msb_T_142 = mux(_msb_T_102, UInt<6>(0h2b), _msb_T_141) node _msb_T_143 = mux(_msb_T_101, UInt<6>(0h2a), _msb_T_142) node _msb_T_144 = mux(_msb_T_100, UInt<6>(0h29), _msb_T_143) node _msb_T_145 = mux(_msb_T_99, UInt<6>(0h28), _msb_T_144) node _msb_T_146 = mux(_msb_T_98, UInt<6>(0h27), _msb_T_145) node _msb_T_147 = mux(_msb_T_97, UInt<6>(0h26), _msb_T_146) node _msb_T_148 = mux(_msb_T_96, UInt<6>(0h25), _msb_T_147) node _msb_T_149 = mux(_msb_T_95, UInt<6>(0h24), _msb_T_148) node _msb_T_150 = mux(_msb_T_94, UInt<6>(0h23), _msb_T_149) node _msb_T_151 = mux(_msb_T_93, UInt<6>(0h22), _msb_T_150) node _msb_T_152 = mux(_msb_T_92, UInt<6>(0h21), _msb_T_151) node _msb_T_153 = mux(_msb_T_91, UInt<6>(0h20), _msb_T_152) node _msb_T_154 = mux(_msb_T_90, UInt<5>(0h1f), _msb_T_153) node _msb_T_155 = mux(_msb_T_89, UInt<5>(0h1e), _msb_T_154) node _msb_T_156 = mux(_msb_T_88, UInt<5>(0h1d), _msb_T_155) node _msb_T_157 = mux(_msb_T_87, UInt<5>(0h1c), _msb_T_156) node _msb_T_158 = mux(_msb_T_86, UInt<5>(0h1b), _msb_T_157) node _msb_T_159 = mux(_msb_T_85, UInt<5>(0h1a), _msb_T_158) node _msb_T_160 = mux(_msb_T_84, UInt<5>(0h19), _msb_T_159) node _msb_T_161 = mux(_msb_T_83, UInt<5>(0h18), _msb_T_160) node _msb_T_162 = mux(_msb_T_82, UInt<5>(0h17), _msb_T_161) node _msb_T_163 = mux(_msb_T_81, UInt<5>(0h16), _msb_T_162) node _msb_T_164 = mux(_msb_T_80, UInt<5>(0h15), _msb_T_163) node _msb_T_165 = mux(_msb_T_79, UInt<5>(0h14), _msb_T_164) node _msb_T_166 = mux(_msb_T_78, UInt<5>(0h13), _msb_T_165) node _msb_T_167 = mux(_msb_T_77, UInt<5>(0h12), _msb_T_166) node _msb_T_168 = mux(_msb_T_76, UInt<5>(0h11), _msb_T_167) node _msb_T_169 = mux(_msb_T_75, UInt<5>(0h10), _msb_T_168) node _msb_T_170 = mux(_msb_T_74, UInt<4>(0hf), _msb_T_169) node _msb_T_171 = mux(_msb_T_73, UInt<4>(0he), _msb_T_170) node _msb_T_172 = mux(_msb_T_72, UInt<4>(0hd), _msb_T_171) node _msb_T_173 = mux(_msb_T_71, UInt<4>(0hc), _msb_T_172) node _msb_T_174 = mux(_msb_T_70, UInt<4>(0hb), _msb_T_173) node _msb_T_175 = mux(_msb_T_69, UInt<4>(0ha), _msb_T_174) node _msb_T_176 = mux(_msb_T_68, UInt<4>(0h9), _msb_T_175) node _msb_T_177 = mux(_msb_T_67, UInt<4>(0h8), _msb_T_176) node _msb_T_178 = mux(_msb_T_66, UInt<3>(0h7), _msb_T_177) node _msb_T_179 = mux(_msb_T_65, UInt<3>(0h6), _msb_T_178) node _msb_T_180 = mux(_msb_T_64, UInt<3>(0h5), _msb_T_179) node _msb_T_181 = mux(_msb_T_63, UInt<3>(0h4), _msb_T_180) node _msb_T_182 = mux(_msb_T_62, UInt<2>(0h3), _msb_T_181) node _msb_T_183 = mux(_msb_T_61, UInt<2>(0h2), _msb_T_182) node _msb_T_184 = mux(_msb_T_60, UInt<1>(0h1), _msb_T_183) node _msb_T_185 = mux(_msb_T_59, UInt<1>(0h0), _msb_T_184) node _msb_T_186 = sub(UInt<7>(0h40), _msb_T_185) node msb = tail(_msb_T_186, 1) node _addr_T = bits(s_idx, 3, 0) node _addr_T_1 = dshl(rand_val, UInt<3>(0h4)) node _addr_T_2 = dshl(UInt<1>(0h1), msb) node _addr_T_3 = sub(_addr_T_2, UInt<1>(0h1)) node _addr_T_4 = tail(_addr_T_3, 1) node _addr_T_5 = and(_addr_T_1, _addr_T_4) node _addr_T_6 = add(start_addr[_addr_T], _addr_T_5) node _addr_T_7 = tail(_addr_T_6, 1) connect addr, _addr_T_7 else : node _T_11 = eq(stream_type[_cur_stream_T], UInt<3>(0h0)) node _T_12 = eq(stream_type[_cur_stream_T], UInt<3>(0h1)) node _T_13 = or(_T_11, _T_12) when _T_13 : node _nxt_addr_T = bits(s_idx, 3, 0) node _nxt_addr_T_1 = bits(s_idx, 3, 0) node _nxt_addr_T_2 = add(cur_addr[_nxt_addr_T], stride[_nxt_addr_T_1]) node nxt_addr = tail(_nxt_addr_T_2, 1) node _T_14 = bits(s_idx, 3, 0) node _T_15 = geq(nxt_addr, end_addr[_T_14]) when _T_15 : node _addr_T_8 = bits(s_idx, 3, 0) connect addr, start_addr[_addr_T_8] else : connect addr, nxt_addr node _T_16 = bits(s_idx, 3, 0) connect cur_addr[_T_16], addr else : node _T_17 = eq(stream_type[_cur_stream_T], UInt<3>(0h2)) node _T_18 = eq(stream_type[_cur_stream_T], UInt<3>(0h3)) node _T_19 = or(_T_17, _T_18) when _T_19 : node _addr_T_9 = bits(s_idx, 3, 0) connect addr, start_addr[_addr_T_9] wire cur_cmd : UInt connect cur_cmd, UInt<1>(0h0) node _T_20 = eq(stream_type[_cur_stream_T], UInt<3>(0h0)) node _T_21 = eq(stream_type[_cur_stream_T], UInt<3>(0h2)) node _T_22 = or(_T_20, _T_21) node _T_23 = eq(stream_type[_cur_stream_T], UInt<3>(0h4)) node _T_24 = or(_T_22, _T_23) when _T_24 : connect cur_cmd, UInt<1>(0h0) else : connect cur_cmd, UInt<1>(0h1) node _io_req_valid_T = bits(s_idx, 3, 0) node _io_req_valid_T_1 = eq(s_sent_done[_io_req_valid_T], UInt<1>(0h0)) connect io.req.valid, _io_req_valid_T_1 connect io.req.bits.data.addr, addr connect io.req.bits.data.cmd, cur_cmd connect io.req.bits.data.size, UInt<3>(0h4) connect io.req.bits.data.data, data connect io.req.bits.idx, s_idx node _T_25 = and(io.req.ready, io.req.valid) when _T_25 : node _T_26 = bits(s_idx, 3, 0) regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "MemReq -> s_idx: %d, s_sent: %d, addr: 0x%x, data: 0x%x streamtype: %d\n", s_idx, s_sent[_T_26], addr, data, stream_type[_cur_stream_T]) : printf_5 node _T_31 = bits(s_idx, 3, 0) when s_sent_done[_T_31] : node _s_idx_T = sub(stream_cnt, UInt<1>(0h1)) node _s_idx_T_1 = tail(_s_idx_T, 1) node _s_idx_T_2 = eq(s_idx, _s_idx_T_1) node _s_idx_T_3 = add(s_idx, UInt<1>(0h1)) node _s_idx_T_4 = tail(_s_idx_T_3, 1) node _s_idx_T_5 = mux(_s_idx_T_2, UInt<1>(0h0), _s_idx_T_4) connect s_idx, _s_idx_T_5 else : node _T_32 = and(io.req.ready, io.req.valid) when _T_32 : node _s_idx_T_6 = sub(stream_cnt, UInt<1>(0h1)) node _s_idx_T_7 = tail(_s_idx_T_6, 1) node _s_idx_T_8 = eq(s_idx, _s_idx_T_7) node _s_idx_T_9 = add(s_idx, UInt<1>(0h1)) node _s_idx_T_10 = tail(_s_idx_T_9, 1) node _s_idx_T_11 = mux(_s_idx_T_8, UInt<1>(0h0), _s_idx_T_10) connect s_idx, _s_idx_T_11 node _T_33 = bits(s_idx, 3, 0) node _s_sent_T = bits(s_idx, 3, 0) node _s_sent_T_1 = add(s_sent[_s_sent_T], UInt<1>(0h1)) node _s_sent_T_2 = tail(_s_sent_T_1, 1) connect s_sent[_T_33], _s_sent_T_2 node _T_34 = bits(s_idx, 3, 0) node _T_35 = sub(max_reqs, UInt<1>(0h1)) node _T_36 = tail(_T_35, 1) node _T_37 = eq(s_sent[_T_34], _T_36) when _T_37 : node _T_38 = bits(s_idx, 3, 0) connect s_sent_done[_T_38], UInt<1>(0h1) wire sent_done_0 : UInt<1> connect sent_done_0, UInt<1>(0h1) node _sent_done_done_T = lt(UInt<1>(0h0), stream_cnt) when _sent_done_done_T : connect sent_done_0, s_sent_done[0] wire sent_done_1 : UInt<1> connect sent_done_1, UInt<1>(0h1) node _sent_done_done_T_1 = lt(UInt<1>(0h1), stream_cnt) when _sent_done_done_T_1 : connect sent_done_1, s_sent_done[1] wire sent_done_2 : UInt<1> connect sent_done_2, UInt<1>(0h1) node _sent_done_done_T_2 = lt(UInt<2>(0h2), stream_cnt) when _sent_done_done_T_2 : connect sent_done_2, s_sent_done[2] wire sent_done_3 : UInt<1> connect sent_done_3, UInt<1>(0h1) node _sent_done_done_T_3 = lt(UInt<2>(0h3), stream_cnt) when _sent_done_done_T_3 : connect sent_done_3, s_sent_done[3] wire sent_done_4 : UInt<1> connect sent_done_4, UInt<1>(0h1) node _sent_done_done_T_4 = lt(UInt<3>(0h4), stream_cnt) when _sent_done_done_T_4 : connect sent_done_4, s_sent_done[4] wire sent_done_5 : UInt<1> connect sent_done_5, UInt<1>(0h1) node _sent_done_done_T_5 = lt(UInt<3>(0h5), stream_cnt) when _sent_done_done_T_5 : connect sent_done_5, s_sent_done[5] wire sent_done_6 : UInt<1> connect sent_done_6, UInt<1>(0h1) node _sent_done_done_T_6 = lt(UInt<3>(0h6), stream_cnt) when _sent_done_done_T_6 : connect sent_done_6, s_sent_done[6] wire sent_done_7 : UInt<1> connect sent_done_7, UInt<1>(0h1) node _sent_done_done_T_7 = lt(UInt<3>(0h7), stream_cnt) when _sent_done_done_T_7 : connect sent_done_7, s_sent_done[7] wire sent_done_8 : UInt<1> connect sent_done_8, UInt<1>(0h1) node _sent_done_done_T_8 = lt(UInt<4>(0h8), stream_cnt) when _sent_done_done_T_8 : connect sent_done_8, s_sent_done[8] wire sent_done_9 : UInt<1> connect sent_done_9, UInt<1>(0h1) node _sent_done_done_T_9 = lt(UInt<4>(0h9), stream_cnt) when _sent_done_done_T_9 : connect sent_done_9, s_sent_done[9] wire sent_done_10 : UInt<1> connect sent_done_10, UInt<1>(0h1) node _sent_done_done_T_10 = lt(UInt<4>(0ha), stream_cnt) when _sent_done_done_T_10 : connect sent_done_10, s_sent_done[10] wire sent_done_11 : UInt<1> connect sent_done_11, UInt<1>(0h1) node _sent_done_done_T_11 = lt(UInt<4>(0hb), stream_cnt) when _sent_done_done_T_11 : connect sent_done_11, s_sent_done[11] wire sent_done_12 : UInt<1> connect sent_done_12, UInt<1>(0h1) node _sent_done_done_T_12 = lt(UInt<4>(0hc), stream_cnt) when _sent_done_done_T_12 : connect sent_done_12, s_sent_done[12] wire sent_done_13 : UInt<1> connect sent_done_13, UInt<1>(0h1) node _sent_done_done_T_13 = lt(UInt<4>(0hd), stream_cnt) when _sent_done_done_T_13 : connect sent_done_13, s_sent_done[13] wire sent_done_14 : UInt<1> connect sent_done_14, UInt<1>(0h1) node _sent_done_done_T_14 = lt(UInt<4>(0he), stream_cnt) when _sent_done_done_T_14 : connect sent_done_14, s_sent_done[14] wire sent_done_15 : UInt<1> connect sent_done_15, UInt<1>(0h1) node _sent_done_done_T_15 = lt(UInt<4>(0hf), stream_cnt) when _sent_done_done_T_15 : connect sent_done_15, s_sent_done[15] node _T_39 = and(sent_done_0, sent_done_1) node _T_40 = and(_T_39, sent_done_2) node _T_41 = and(_T_40, sent_done_3) node _T_42 = and(_T_41, sent_done_4) node _T_43 = and(_T_42, sent_done_5) node _T_44 = and(_T_43, sent_done_6) node _T_45 = and(_T_44, sent_done_7) node _T_46 = and(_T_45, sent_done_8) node _T_47 = and(_T_46, sent_done_9) node _T_48 = and(_T_47, sent_done_10) node _T_49 = and(_T_48, sent_done_11) node _T_50 = and(_T_49, sent_done_12) node _T_51 = and(_T_50, sent_done_13) node _T_52 = and(_T_51, sent_done_14) node _T_53 = and(_T_52, sent_done_15) when _T_53 : connect io.sent_done, UInt<1>(0h1) else : connect io.req.valid, UInt<1>(0h0)

module ReqGen( // @[reqgen.scala:26:7] input clock, // @[reqgen.scala:26:7] input reset, // @[reqgen.scala:26:7] input io_send_reqs, // @[reqgen.scala:27:14] output io_sent_done, // @[reqgen.scala:27:14] output io_req_fire, // @[reqgen.scala:27:14] input io_global_stream_info_valid, // @[reqgen.scala:27:14] input [4:0] io_global_stream_info_bits_stream_cnt, // @[reqgen.scala:27:14] input [63:0] io_global_stream_info_bits_addr_range, // @[reqgen.scala:27:14] input [63:0] io_global_stream_info_bits_max_reqs, // @[reqgen.scala:27:14] input io_local_stream_info_valid, // @[reqgen.scala:27:14] input [63:0] io_local_stream_info_bits_data_start_addr, // @[reqgen.scala:27:14] input [63:0] io_local_stream_info_bits_data_stride, // @[reqgen.scala:27:14] input [2:0] io_local_stream_info_bits_data_stream_type, // @[reqgen.scala:27:14] input [3:0] io_local_stream_info_bits_idx, // @[reqgen.scala:27:14] input io_req_ready, // @[reqgen.scala:27:14] output io_req_valid, // @[reqgen.scala:27:14] output [63:0] io_req_bits_data_addr, // @[reqgen.scala:27:14] output io_req_bits_data_cmd, // @[reqgen.scala:27:14] output [127:0] io_req_bits_data_data, // @[reqgen.scala:27:14] output [3:0] io_req_bits_idx // @[reqgen.scala:27:14] ); wire _rand_val_prng_io_out_0; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_1; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_2; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_3; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_4; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_5; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_6; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_7; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_8; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_9; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_10; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_11; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_12; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_13; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_14; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_15; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_16; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_17; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_18; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_19; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_20; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_21; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_22; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_23; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_24; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_25; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_26; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_27; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_28; // @[PRNG.scala:91:22] wire _rand_val_prng_io_out_29; // @[PRNG.scala:91:22] wire io_send_reqs_0 = io_send_reqs; // @[reqgen.scala:26:7] wire io_global_stream_info_valid_0 = io_global_stream_info_valid; // @[reqgen.scala:26:7] wire [4:0] io_global_stream_info_bits_stream_cnt_0 = io_global_stream_info_bits_stream_cnt; // @[reqgen.scala:26:7] wire [63:0] io_global_stream_info_bits_addr_range_0 = io_global_stream_info_bits_addr_range; // @[reqgen.scala:26:7] wire [63:0] io_global_stream_info_bits_max_reqs_0 = io_global_stream_info_bits_max_reqs; // @[reqgen.scala:26:7] wire io_local_stream_info_valid_0 = io_local_stream_info_valid; // @[reqgen.scala:26:7] wire [63:0] io_local_stream_info_bits_data_start_addr_0 = io_local_stream_info_bits_data_start_addr; // @[reqgen.scala:26:7] wire [63:0] io_local_stream_info_bits_data_stride_0 = io_local_stream_info_bits_data_stride; // @[reqgen.scala:26:7] wire [2:0] io_local_stream_info_bits_data_stream_type_0 = io_local_stream_info_bits_data_stream_type; // @[reqgen.scala:26:7] wire [3:0] io_local_stream_info_bits_idx_0 = io_local_stream_info_bits_idx; // @[reqgen.scala:26:7] wire io_req_ready_0 = io_req_ready; // @[reqgen.scala:26:7] wire [2:0] io_req_bits_data_size = 3'h4; // @[reqgen.scala:26:7] wire [63:0] _msb_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[reqgen.scala:89:47] wire [63:0] _msb_T_51 = 64'h5555555555555555; // @[reqgen.scala:89:47] wire [63:0] _msb_T_50 = 64'h6666666666666666; // @[reqgen.scala:89:47] wire [62:0] _msb_T_49 = 63'h3333333333333333; // @[reqgen.scala:89:47] wire [63:0] _msb_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[reqgen.scala:89:47] wire [63:0] _msb_T_41 = 64'h3333333333333333; // @[reqgen.scala:89:47] wire [63:0] _msb_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[reqgen.scala:89:47] wire [61:0] _msb_T_39 = 62'hF0F0F0F0F0F0F0F; // @[reqgen.scala:89:47] wire [63:0] _msb_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[reqgen.scala:89:47] wire [63:0] _msb_T_31 = 64'hF0F0F0F0F0F0F0F; // @[reqgen.scala:89:47] wire [63:0] _msb_T_30 = 64'hFF00FF00FF00FF0; // @[reqgen.scala:89:47] wire [59:0] _msb_T_29 = 60'hFF00FF00FF00FF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_26 = 64'hFF00FF00FF00FF00; // @[reqgen.scala:89:47] wire [63:0] _msb_T_21 = 64'hFF00FF00FF00FF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_20 = 64'hFFFF0000FFFF00; // @[reqgen.scala:89:47] wire [55:0] _msb_T_19 = 56'hFFFF0000FFFF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_16 = 64'hFFFF0000FFFF0000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_11 = 64'hFFFF0000FFFF; // @[reqgen.scala:89:47] wire [63:0] _msb_T_10 = 64'hFFFFFFFF0000; // @[reqgen.scala:89:47] wire [47:0] _msb_T_9 = 48'hFFFFFFFF; // @[reqgen.scala:89:47] wire [63:0] _msb_T = 64'hFFFFFFFF00000000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_6 = 64'hFFFFFFFF00000000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_1 = 64'hFFFFFFFF; // @[reqgen.scala:89:47] wire [255:0] _data_T_2 = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[reqgen.scala:86:32] wire [256:0] _data_T_1 = 257'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[reqgen.scala:86:32] wire _s_sent_done_WIRE_0 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_1 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_2 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_3 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_4 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_5 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_6 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_7 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_8 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_9 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_10 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_11 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_12 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_13 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_14 = 1'h0; // @[reqgen.scala:81:36] wire _s_sent_done_WIRE_15 = 1'h0; // @[reqgen.scala:81:36] wire [63:0] _start_addr_WIRE_0 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_1 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_2 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_3 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_4 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_5 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_6 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_7 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_8 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_9 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_10 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_11 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_12 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_13 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_14 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _start_addr_WIRE_15 = 64'h0; // @[reqgen.scala:37:39] wire [63:0] _stride_WIRE_0 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_1 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_2 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_3 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_4 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_5 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_6 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_7 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_8 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_9 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_10 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_11 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_12 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_13 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_14 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _stride_WIRE_15 = 64'h0; // @[reqgen.scala:38:39] wire [63:0] _end_addr_WIRE_0 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_1 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_2 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_3 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_4 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_5 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_6 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_7 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_8 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_9 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_10 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_11 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_12 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_13 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_14 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _end_addr_WIRE_15 = 64'h0; // @[reqgen.scala:40:39] wire [63:0] _cur_addr_WIRE_0 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_1 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_2 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_3 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_4 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_5 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_6 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_7 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_8 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_9 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_10 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_11 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_12 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_13 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_14 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _cur_addr_WIRE_15 = 64'h0; // @[reqgen.scala:41:39] wire [63:0] _s_sent_WIRE_0 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_1 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_2 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_3 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_4 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_5 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_6 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_7 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_8 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_9 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_10 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_11 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_12 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_13 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_14 = 64'h0; // @[reqgen.scala:80:36] wire [63:0] _s_sent_WIRE_15 = 64'h0; // @[reqgen.scala:80:36] wire [2:0] _stream_type_WIRE_0 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_1 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_2 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_3 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_4 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_5 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_6 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_7 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_8 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_9 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_10 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_11 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_12 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_13 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_14 = 3'h0; // @[reqgen.scala:39:39] wire [2:0] _stream_type_WIRE_15 = 3'h0; // @[reqgen.scala:39:39] wire [255:0] _data_T = 256'h100000000000000000000000000000000; // @[reqgen.scala:86:22] wire _io_req_fire_T; // @[Decoupled.scala:51:35] wire [63:0] io_req_bits_data_addr_0; // @[reqgen.scala:26:7] wire io_req_bits_data_cmd_0; // @[reqgen.scala:26:7] wire [127:0] io_req_bits_data_data_0; // @[reqgen.scala:26:7] wire [3:0] io_req_bits_idx_0; // @[reqgen.scala:26:7] wire io_req_valid_0; // @[reqgen.scala:26:7] wire io_sent_done_0; // @[reqgen.scala:26:7] wire io_req_fire_0; // @[reqgen.scala:26:7] wire [1:0] rand_val_lo_lo_lo_hi = {_rand_val_prng_io_out_2, _rand_val_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] rand_val_lo_lo_lo = {rand_val_lo_lo_lo_hi, _rand_val_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_lo_hi_lo = {_rand_val_prng_io_out_4, _rand_val_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_lo_hi_hi = {_rand_val_prng_io_out_6, _rand_val_prng_io_out_5}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_lo_lo_hi = {rand_val_lo_lo_hi_hi, rand_val_lo_lo_hi_lo}; // @[PRNG.scala:95:17] wire [6:0] rand_val_lo_lo = {rand_val_lo_lo_hi, rand_val_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_lo_hi_lo_lo = {_rand_val_prng_io_out_8, _rand_val_prng_io_out_7}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_hi_lo_hi = {_rand_val_prng_io_out_10, _rand_val_prng_io_out_9}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_lo_hi_lo = {rand_val_lo_hi_lo_hi, rand_val_lo_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_lo_hi_hi_lo = {_rand_val_prng_io_out_12, _rand_val_prng_io_out_11}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_lo_hi_hi_hi = {_rand_val_prng_io_out_14, _rand_val_prng_io_out_13}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_lo_hi_hi = {rand_val_lo_hi_hi_hi, rand_val_lo_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] rand_val_lo_hi = {rand_val_lo_hi_hi, rand_val_lo_hi_lo}; // @[PRNG.scala:95:17] wire [14:0] rand_val_lo = {rand_val_lo_hi, rand_val_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_hi_lo_lo_hi = {_rand_val_prng_io_out_17, _rand_val_prng_io_out_16}; // @[PRNG.scala:91:22, :95:17] wire [2:0] rand_val_hi_lo_lo = {rand_val_hi_lo_lo_hi, _rand_val_prng_io_out_15}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_lo_hi_lo = {_rand_val_prng_io_out_19, _rand_val_prng_io_out_18}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_lo_hi_hi = {_rand_val_prng_io_out_21, _rand_val_prng_io_out_20}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_hi_lo_hi = {rand_val_hi_lo_hi_hi, rand_val_hi_lo_hi_lo}; // @[PRNG.scala:95:17] wire [6:0] rand_val_hi_lo = {rand_val_hi_lo_hi, rand_val_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_hi_hi_lo_lo = {_rand_val_prng_io_out_23, _rand_val_prng_io_out_22}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_hi_lo_hi = {_rand_val_prng_io_out_25, _rand_val_prng_io_out_24}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_hi_hi_lo = {rand_val_hi_hi_lo_hi, rand_val_hi_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] rand_val_hi_hi_hi_lo = {_rand_val_prng_io_out_27, _rand_val_prng_io_out_26}; // @[PRNG.scala:91:22, :95:17] wire [1:0] rand_val_hi_hi_hi_hi = {_rand_val_prng_io_out_29, _rand_val_prng_io_out_28}; // @[PRNG.scala:91:22, :95:17] wire [3:0] rand_val_hi_hi_hi = {rand_val_hi_hi_hi_hi, rand_val_hi_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] rand_val_hi_hi = {rand_val_hi_hi_hi, rand_val_hi_hi_lo}; // @[PRNG.scala:95:17] wire [14:0] rand_val_hi = {rand_val_hi_hi, rand_val_hi_lo}; // @[PRNG.scala:95:17] wire [29:0] rand_val = {rand_val_hi, rand_val_lo}; // @[PRNG.scala:95:17] reg [4:0] stream_cnt; // @[reqgen.scala:33:31] reg [63:0] addr_range; // @[reqgen.scala:34:31] reg [63:0] max_reqs; // @[reqgen.scala:35:31] reg [63:0] start_addr_0; // @[reqgen.scala:37:31] reg [63:0] start_addr_1; // @[reqgen.scala:37:31] reg [63:0] start_addr_2; // @[reqgen.scala:37:31] reg [63:0] start_addr_3; // @[reqgen.scala:37:31] reg [63:0] start_addr_4; // @[reqgen.scala:37:31] reg [63:0] start_addr_5; // @[reqgen.scala:37:31] reg [63:0] start_addr_6; // @[reqgen.scala:37:31] reg [63:0] start_addr_7; // @[reqgen.scala:37:31] reg [63:0] start_addr_8; // @[reqgen.scala:37:31] reg [63:0] start_addr_9; // @[reqgen.scala:37:31] reg [63:0] start_addr_10; // @[reqgen.scala:37:31] reg [63:0] start_addr_11; // @[reqgen.scala:37:31] reg [63:0] start_addr_12; // @[reqgen.scala:37:31] reg [63:0] start_addr_13; // @[reqgen.scala:37:31] reg [63:0] start_addr_14; // @[reqgen.scala:37:31] reg [63:0] start_addr_15; // @[reqgen.scala:37:31] reg [63:0] stride_0; // @[reqgen.scala:38:31] reg [63:0] stride_1; // @[reqgen.scala:38:31] reg [63:0] stride_2; // @[reqgen.scala:38:31] reg [63:0] stride_3; // @[reqgen.scala:38:31] reg [63:0] stride_4; // @[reqgen.scala:38:31] reg [63:0] stride_5; // @[reqgen.scala:38:31] reg [63:0] stride_6; // @[reqgen.scala:38:31] reg [63:0] stride_7; // @[reqgen.scala:38:31] reg [63:0] stride_8; // @[reqgen.scala:38:31] reg [63:0] stride_9; // @[reqgen.scala:38:31] reg [63:0] stride_10; // @[reqgen.scala:38:31] reg [63:0] stride_11; // @[reqgen.scala:38:31] reg [63:0] stride_12; // @[reqgen.scala:38:31] reg [63:0] stride_13; // @[reqgen.scala:38:31] reg [63:0] stride_14; // @[reqgen.scala:38:31] reg [63:0] stride_15; // @[reqgen.scala:38:31] reg [2:0] stream_type_0; // @[reqgen.scala:39:31] reg [2:0] stream_type_1; // @[reqgen.scala:39:31] reg [2:0] stream_type_2; // @[reqgen.scala:39:31] reg [2:0] stream_type_3; // @[reqgen.scala:39:31] reg [2:0] stream_type_4; // @[reqgen.scala:39:31] reg [2:0] stream_type_5; // @[reqgen.scala:39:31] reg [2:0] stream_type_6; // @[reqgen.scala:39:31] reg [2:0] stream_type_7; // @[reqgen.scala:39:31] reg [2:0] stream_type_8; // @[reqgen.scala:39:31] reg [2:0] stream_type_9; // @[reqgen.scala:39:31] reg [2:0] stream_type_10; // @[reqgen.scala:39:31] reg [2:0] stream_type_11; // @[reqgen.scala:39:31] reg [2:0] stream_type_12; // @[reqgen.scala:39:31] reg [2:0] stream_type_13; // @[reqgen.scala:39:31] reg [2:0] stream_type_14; // @[reqgen.scala:39:31] reg [2:0] stream_type_15; // @[reqgen.scala:39:31] reg [63:0] end_addr_0; // @[reqgen.scala:40:31] reg [63:0] end_addr_1; // @[reqgen.scala:40:31] reg [63:0] end_addr_2; // @[reqgen.scala:40:31] reg [63:0] end_addr_3; // @[reqgen.scala:40:31] reg [63:0] end_addr_4; // @[reqgen.scala:40:31] reg [63:0] end_addr_5; // @[reqgen.scala:40:31] reg [63:0] end_addr_6; // @[reqgen.scala:40:31] reg [63:0] end_addr_7; // @[reqgen.scala:40:31] reg [63:0] end_addr_8; // @[reqgen.scala:40:31] reg [63:0] end_addr_9; // @[reqgen.scala:40:31] reg [63:0] end_addr_10; // @[reqgen.scala:40:31] reg [63:0] end_addr_11; // @[reqgen.scala:40:31] reg [63:0] end_addr_12; // @[reqgen.scala:40:31] reg [63:0] end_addr_13; // @[reqgen.scala:40:31] reg [63:0] end_addr_14; // @[reqgen.scala:40:31] reg [63:0] end_addr_15; // @[reqgen.scala:40:31] reg [63:0] cur_addr_0; // @[reqgen.scala:41:31] reg [63:0] cur_addr_1; // @[reqgen.scala:41:31] reg [63:0] cur_addr_2; // @[reqgen.scala:41:31] reg [63:0] cur_addr_3; // @[reqgen.scala:41:31] reg [63:0] cur_addr_4; // @[reqgen.scala:41:31] reg [63:0] cur_addr_5; // @[reqgen.scala:41:31] reg [63:0] cur_addr_6; // @[reqgen.scala:41:31] reg [63:0] cur_addr_7; // @[reqgen.scala:41:31] reg [63:0] cur_addr_8; // @[reqgen.scala:41:31] reg [63:0] cur_addr_9; // @[reqgen.scala:41:31] reg [63:0] cur_addr_10; // @[reqgen.scala:41:31] reg [63:0] cur_addr_11; // @[reqgen.scala:41:31] reg [63:0] cur_addr_12; // @[reqgen.scala:41:31] reg [63:0] cur_addr_13; // @[reqgen.scala:41:31] reg [63:0] cur_addr_14; // @[reqgen.scala:41:31] reg [63:0] cur_addr_15; // @[reqgen.scala:41:31] assign _io_req_fire_T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] assign io_req_fire_0 = _io_req_fire_T; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles; // @[util.scala:14:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[util.scala:14:33, :15:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[util.scala:15:38] wire [64:0] _end_addr_T = {1'h0, io_local_stream_info_bits_data_start_addr_0} + {1'h0, addr_range}; // @[reqgen.scala:26:7, :34:31, :72:38] wire [63:0] _end_addr_T_1 = _end_addr_T[63:0]; // @[reqgen.scala:72:38] reg [63:0] loginfo_cycles_1; // @[util.scala:14:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[util.scala:14:33, :15:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[util.scala:15:38] reg [4:0] s_idx; // @[reqgen.scala:79:28] reg [63:0] s_sent_0; // @[reqgen.scala:80:28] reg [63:0] s_sent_1; // @[reqgen.scala:80:28] reg [63:0] s_sent_2; // @[reqgen.scala:80:28] reg [63:0] s_sent_3; // @[reqgen.scala:80:28] reg [63:0] s_sent_4; // @[reqgen.scala:80:28] reg [63:0] s_sent_5; // @[reqgen.scala:80:28] reg [63:0] s_sent_6; // @[reqgen.scala:80:28] reg [63:0] s_sent_7; // @[reqgen.scala:80:28] reg [63:0] s_sent_8; // @[reqgen.scala:80:28] reg [63:0] s_sent_9; // @[reqgen.scala:80:28] reg [63:0] s_sent_10; // @[reqgen.scala:80:28] reg [63:0] s_sent_11; // @[reqgen.scala:80:28] reg [63:0] s_sent_12; // @[reqgen.scala:80:28] reg [63:0] s_sent_13; // @[reqgen.scala:80:28] reg [63:0] s_sent_14; // @[reqgen.scala:80:28] reg [63:0] s_sent_15; // @[reqgen.scala:80:28] reg s_sent_done_0; // @[reqgen.scala:81:28] reg s_sent_done_1; // @[reqgen.scala:81:28] reg s_sent_done_2; // @[reqgen.scala:81:28] reg s_sent_done_3; // @[reqgen.scala:81:28] reg s_sent_done_4; // @[reqgen.scala:81:28] reg s_sent_done_5; // @[reqgen.scala:81:28] reg s_sent_done_6; // @[reqgen.scala:81:28] reg s_sent_done_7; // @[reqgen.scala:81:28] reg s_sent_done_8; // @[reqgen.scala:81:28] reg s_sent_done_9; // @[reqgen.scala:81:28] reg s_sent_done_10; // @[reqgen.scala:81:28] reg s_sent_done_11; // @[reqgen.scala:81:28] reg s_sent_done_12; // @[reqgen.scala:81:28] reg s_sent_done_13; // @[reqgen.scala:81:28] reg s_sent_done_14; // @[reqgen.scala:81:28] reg s_sent_done_15; // @[reqgen.scala:81:28] wire [3:0] _cur_stream_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _addr_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _nxt_addr_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _nxt_addr_T_1 = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _addr_T_8 = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _addr_T_9 = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _io_req_valid_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [3:0] _s_sent_T = s_idx[3:0]; // @[reqgen.scala:79:28] wire [63:0] addr; // @[reqgen.scala:85:24] wire [31:0] _data_T_3 = 32'h1 << s_idx; // @[reqgen.scala:79:28, :86:46] wire [255:0] data = {224'hFFFFFFFFFFFFFFFFFFFFFFFF, ~_data_T_3}; // @[reqgen.scala:86:{39,46}] wire [15:0][2:0] _GEN = {{stream_type_15}, {stream_type_14}, {stream_type_13}, {stream_type_12}, {stream_type_11}, {stream_type_10}, {stream_type_9}, {stream_type_8}, {stream_type_7}, {stream_type_6}, {stream_type_5}, {stream_type_4}, {stream_type_3}, {stream_type_2}, {stream_type_1}, {stream_type_0}}; // @[reqgen.scala:39:31, :88:22] wire _T_23 = _GEN[_cur_stream_T] == 3'h4; // @[reqgen.scala:88:22] wire _T_10 = _T_23 | _GEN[_cur_stream_T] == 3'h5; // @[reqgen.scala:88:{22,41,55}] wire [31:0] _msb_T_2 = addr_range[63:32]; // @[reqgen.scala:34:31, :89:47] wire [63:0] _msb_T_3 = {32'h0, _msb_T_2}; // @[reqgen.scala:89:47] wire [31:0] _msb_T_4 = addr_range[31:0]; // @[reqgen.scala:34:31, :89:47] wire [63:0] _msb_T_5 = {_msb_T_4, 32'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_7 = _msb_T_5 & 64'hFFFFFFFF00000000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_8 = _msb_T_3 | _msb_T_7; // @[reqgen.scala:89:47] wire [47:0] _msb_T_12 = _msb_T_8[63:16]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_13 = {16'h0, _msb_T_12 & 48'hFFFF0000FFFF}; // @[reqgen.scala:89:47] wire [47:0] _msb_T_14 = _msb_T_8[47:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_15 = {_msb_T_14, 16'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_17 = _msb_T_15 & 64'hFFFF0000FFFF0000; // @[reqgen.scala:89:47] wire [63:0] _msb_T_18 = _msb_T_13 | _msb_T_17; // @[reqgen.scala:89:47] wire [55:0] _msb_T_22 = _msb_T_18[63:8]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_23 = {8'h0, _msb_T_22 & 56'hFF00FF00FF00FF}; // @[reqgen.scala:89:47] wire [55:0] _msb_T_24 = _msb_T_18[55:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_25 = {_msb_T_24, 8'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_27 = _msb_T_25 & 64'hFF00FF00FF00FF00; // @[reqgen.scala:89:47] wire [63:0] _msb_T_28 = _msb_T_23 | _msb_T_27; // @[reqgen.scala:89:47] wire [59:0] _msb_T_32 = _msb_T_28[63:4]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_33 = {4'h0, _msb_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[reqgen.scala:89:47] wire [59:0] _msb_T_34 = _msb_T_28[59:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_35 = {_msb_T_34, 4'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_37 = _msb_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[reqgen.scala:89:47] wire [63:0] _msb_T_38 = _msb_T_33 | _msb_T_37; // @[reqgen.scala:89:47] wire [61:0] _msb_T_42 = _msb_T_38[63:2]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_43 = {2'h0, _msb_T_42 & 62'h3333333333333333}; // @[reqgen.scala:89:47] wire [61:0] _msb_T_44 = _msb_T_38[61:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_45 = {_msb_T_44, 2'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_47 = _msb_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[reqgen.scala:89:47] wire [63:0] _msb_T_48 = _msb_T_43 | _msb_T_47; // @[reqgen.scala:89:47] wire [62:0] _msb_T_52 = _msb_T_48[63:1]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_53 = {1'h0, _msb_T_52 & 63'h5555555555555555}; // @[reqgen.scala:89:47] wire [62:0] _msb_T_54 = _msb_T_48[62:0]; // @[reqgen.scala:89:47] wire [63:0] _msb_T_55 = {_msb_T_54, 1'h0}; // @[reqgen.scala:89:47] wire [63:0] _msb_T_57 = _msb_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[reqgen.scala:89:47] wire [63:0] _msb_T_58 = _msb_T_53 | _msb_T_57; // @[reqgen.scala:89:47] wire _msb_T_59 = _msb_T_58[0]; // @[OneHot.scala:48:45] wire _msb_T_60 = _msb_T_58[1]; // @[OneHot.scala:48:45] wire _msb_T_61 = _msb_T_58[2]; // @[OneHot.scala:48:45] wire _msb_T_62 = _msb_T_58[3]; // @[OneHot.scala:48:45] wire _msb_T_63 = _msb_T_58[4]; // @[OneHot.scala:48:45] wire _msb_T_64 = _msb_T_58[5]; // @[OneHot.scala:48:45] wire _msb_T_65 = _msb_T_58[6]; // @[OneHot.scala:48:45] wire _msb_T_66 = _msb_T_58[7]; // @[OneHot.scala:48:45] wire _msb_T_67 = _msb_T_58[8]; // @[OneHot.scala:48:45] wire _msb_T_68 = _msb_T_58[9]; // @[OneHot.scala:48:45] wire _msb_T_69 = _msb_T_58[10]; // @[OneHot.scala:48:45] wire _msb_T_70 = _msb_T_58[11]; // @[OneHot.scala:48:45] wire _msb_T_71 = _msb_T_58[12]; // @[OneHot.scala:48:45] wire _msb_T_72 = _msb_T_58[13]; // @[OneHot.scala:48:45] wire _msb_T_73 = _msb_T_58[14]; // @[OneHot.scala:48:45] wire _msb_T_74 = _msb_T_58[15]; // @[OneHot.scala:48:45] wire _msb_T_75 = _msb_T_58[16]; // @[OneHot.scala:48:45] wire _msb_T_76 = _msb_T_58[17]; // @[OneHot.scala:48:45] wire _msb_T_77 = _msb_T_58[18]; // @[OneHot.scala:48:45] wire _msb_T_78 = _msb_T_58[19]; // @[OneHot.scala:48:45] wire _msb_T_79 = _msb_T_58[20]; // @[OneHot.scala:48:45] wire _msb_T_80 = _msb_T_58[21]; // @[OneHot.scala:48:45] wire _msb_T_81 = _msb_T_58[22]; // @[OneHot.scala:48:45] wire _msb_T_82 = _msb_T_58[23]; // @[OneHot.scala:48:45] wire _msb_T_83 = _msb_T_58[24]; // @[OneHot.scala:48:45] wire _msb_T_84 = _msb_T_58[25]; // @[OneHot.scala:48:45] wire _msb_T_85 = _msb_T_58[26]; // @[OneHot.scala:48:45] wire _msb_T_86 = _msb_T_58[27]; // @[OneHot.scala:48:45] wire _msb_T_87 = _msb_T_58[28]; // @[OneHot.scala:48:45] wire _msb_T_88 = _msb_T_58[29]; // @[OneHot.scala:48:45] wire _msb_T_89 = _msb_T_58[30]; // @[OneHot.scala:48:45] wire _msb_T_90 = _msb_T_58[31]; // @[OneHot.scala:48:45] wire _msb_T_91 = _msb_T_58[32]; // @[OneHot.scala:48:45] wire _msb_T_92 = _msb_T_58[33]; // @[OneHot.scala:48:45] wire _msb_T_93 = _msb_T_58[34]; // @[OneHot.scala:48:45] wire _msb_T_94 = _msb_T_58[35]; // @[OneHot.scala:48:45] wire _msb_T_95 = _msb_T_58[36]; // @[OneHot.scala:48:45] wire _msb_T_96 = _msb_T_58[37]; // @[OneHot.scala:48:45] wire _msb_T_97 = _msb_T_58[38]; // @[OneHot.scala:48:45] wire _msb_T_98 = _msb_T_58[39]; // @[OneHot.scala:48:45] wire _msb_T_99 = _msb_T_58[40]; // @[OneHot.scala:48:45] wire _msb_T_100 = _msb_T_58[41]; // @[OneHot.scala:48:45] wire _msb_T_101 = _msb_T_58[42]; // @[OneHot.scala:48:45] wire _msb_T_102 = _msb_T_58[43]; // @[OneHot.scala:48:45] wire _msb_T_103 = _msb_T_58[44]; // @[OneHot.scala:48:45] wire _msb_T_104 = _msb_T_58[45]; // @[OneHot.scala:48:45] wire _msb_T_105 = _msb_T_58[46]; // @[OneHot.scala:48:45] wire _msb_T_106 = _msb_T_58[47]; // @[OneHot.scala:48:45] wire _msb_T_107 = _msb_T_58[48]; // @[OneHot.scala:48:45] wire _msb_T_108 = _msb_T_58[49]; // @[OneHot.scala:48:45] wire _msb_T_109 = _msb_T_58[50]; // @[OneHot.scala:48:45] wire _msb_T_110 = _msb_T_58[51]; // @[OneHot.scala:48:45] wire _msb_T_111 = _msb_T_58[52]; // @[OneHot.scala:48:45] wire _msb_T_112 = _msb_T_58[53]; // @[OneHot.scala:48:45] wire _msb_T_113 = _msb_T_58[54]; // @[OneHot.scala:48:45] wire _msb_T_114 = _msb_T_58[55]; // @[OneHot.scala:48:45] wire _msb_T_115 = _msb_T_58[56]; // @[OneHot.scala:48:45] wire _msb_T_116 = _msb_T_58[57]; // @[OneHot.scala:48:45] wire _msb_T_117 = _msb_T_58[58]; // @[OneHot.scala:48:45] wire _msb_T_118 = _msb_T_58[59]; // @[OneHot.scala:48:45] wire _msb_T_119 = _msb_T_58[60]; // @[OneHot.scala:48:45] wire _msb_T_120 = _msb_T_58[61]; // @[OneHot.scala:48:45] wire _msb_T_121 = _msb_T_58[62]; // @[OneHot.scala:48:45] wire _msb_T_122 = _msb_T_58[63]; // @[OneHot.scala:48:45] wire [5:0] _msb_T_123 = {5'h1F, ~_msb_T_121}; // @[OneHot.scala:48:45] wire [5:0] _msb_T_124 = _msb_T_120 ? 6'h3D : _msb_T_123; // @[OneHot.scala:48:45] wire [5:0] _msb_T_125 = _msb_T_119 ? 6'h3C : _msb_T_124; // @[OneHot.scala:48:45] wire [5:0] _msb_T_126 = _msb_T_118 ? 6'h3B : _msb_T_125; // @[OneHot.scala:48:45] wire [5:0] _msb_T_127 = _msb_T_117 ? 6'h3A : _msb_T_126; // @[OneHot.scala:48:45] wire [5:0] _msb_T_128 = _msb_T_116 ? 6'h39 : _msb_T_127; // @[OneHot.scala:48:45] wire [5:0] _msb_T_129 = _msb_T_115 ? 6'h38 : _msb_T_128; // @[OneHot.scala:48:45] wire [5:0] _msb_T_130 = _msb_T_114 ? 6'h37 : _msb_T_129; // @[OneHot.scala:48:45] wire [5:0] _msb_T_131 = _msb_T_113 ? 6'h36 : _msb_T_130; // @[OneHot.scala:48:45] wire [5:0] _msb_T_132 = _msb_T_112 ? 6'h35 : _msb_T_131; // @[OneHot.scala:48:45] wire [5:0] _msb_T_133 = _msb_T_111 ? 6'h34 : _msb_T_132; // @[OneHot.scala:48:45] wire [5:0] _msb_T_134 = _msb_T_110 ? 6'h33 : _msb_T_133; // @[OneHot.scala:48:45] wire [5:0] _msb_T_135 = _msb_T_109 ? 6'h32 : _msb_T_134; // @[OneHot.scala:48:45] wire [5:0] _msb_T_136 = _msb_T_108 ? 6'h31 : _msb_T_135; // @[OneHot.scala:48:45] wire [5:0] _msb_T_137 = _msb_T_107 ? 6'h30 : _msb_T_136; // @[OneHot.scala:48:45] wire [5:0] _msb_T_138 = _msb_T_106 ? 6'h2F : _msb_T_137; // @[OneHot.scala:48:45] wire [5:0] _msb_T_139 = _msb_T_105 ? 6'h2E : _msb_T_138; // @[OneHot.scala:48:45] wire [5:0] _msb_T_140 = _msb_T_104 ? 6'h2D : _msb_T_139; // @[OneHot.scala:48:45] wire [5:0] _msb_T_141 = _msb_T_103 ? 6'h2C : _msb_T_140; // @[OneHot.scala:48:45] wire [5:0] _msb_T_142 = _msb_T_102 ? 6'h2B : _msb_T_141; // @[OneHot.scala:48:45] wire [5:0] _msb_T_143 = _msb_T_101 ? 6'h2A : _msb_T_142; // @[OneHot.scala:48:45] wire [5:0] _msb_T_144 = _msb_T_100 ? 6'h29 : _msb_T_143; // @[OneHot.scala:48:45] wire [5:0] _msb_T_145 = _msb_T_99 ? 6'h28 : _msb_T_144; // @[OneHot.scala:48:45] wire [5:0] _msb_T_146 = _msb_T_98 ? 6'h27 : _msb_T_145; // @[OneHot.scala:48:45] wire [5:0] _msb_T_147 = _msb_T_97 ? 6'h26 : _msb_T_146; // @[OneHot.scala:48:45] wire [5:0] _msb_T_148 = _msb_T_96 ? 6'h25 : _msb_T_147; // @[OneHot.scala:48:45] wire [5:0] _msb_T_149 = _msb_T_95 ? 6'h24 : _msb_T_148; // @[OneHot.scala:48:45] wire [5:0] _msb_T_150 = _msb_T_94 ? 6'h23 : _msb_T_149; // @[OneHot.scala:48:45] wire [5:0] _msb_T_151 = _msb_T_93 ? 6'h22 : _msb_T_150; // @[OneHot.scala:48:45] wire [5:0] _msb_T_152 = _msb_T_92 ? 6'h21 : _msb_T_151; // @[OneHot.scala:48:45] wire [5:0] _msb_T_153 = _msb_T_91 ? 6'h20 : _msb_T_152; // @[OneHot.scala:48:45] wire [5:0] _msb_T_154 = _msb_T_90 ? 6'h1F : _msb_T_153; // @[OneHot.scala:48:45] wire [5:0] _msb_T_155 = _msb_T_89 ? 6'h1E : _msb_T_154; // @[OneHot.scala:48:45] wire [5:0] _msb_T_156 = _msb_T_88 ? 6'h1D : _msb_T_155; // @[OneHot.scala:48:45] wire [5:0] _msb_T_157 = _msb_T_87 ? 6'h1C : _msb_T_156; // @[OneHot.scala:48:45] wire [5:0] _msb_T_158 = _msb_T_86 ? 6'h1B : _msb_T_157; // @[OneHot.scala:48:45] wire [5:0] _msb_T_159 = _msb_T_85 ? 6'h1A : _msb_T_158; // @[OneHot.scala:48:45] wire [5:0] _msb_T_160 = _msb_T_84 ? 6'h19 : _msb_T_159; // @[OneHot.scala:48:45] wire [5:0] _msb_T_161 = _msb_T_83 ? 6'h18 : _msb_T_160; // @[OneHot.scala:48:45] wire [5:0] _msb_T_162 = _msb_T_82 ? 6'h17 : _msb_T_161; // @[OneHot.scala:48:45] wire [5:0] _msb_T_163 = _msb_T_81 ? 6'h16 : _msb_T_162; // @[OneHot.scala:48:45] wire [5:0] _msb_T_164 = _msb_T_80 ? 6'h15 : _msb_T_163; // @[OneHot.scala:48:45] wire [5:0] _msb_T_165 = _msb_T_79 ? 6'h14 : _msb_T_164; // @[OneHot.scala:48:45] wire [5:0] _msb_T_166 = _msb_T_78 ? 6'h13 : _msb_T_165; // @[OneHot.scala:48:45] wire [5:0] _msb_T_167 = _msb_T_77 ? 6'h12 : _msb_T_166; // @[OneHot.scala:48:45] wire [5:0] _msb_T_168 = _msb_T_76 ? 6'h11 : _msb_T_167; // @[OneHot.scala:48:45] wire [5:0] _msb_T_169 = _msb_T_75 ? 6'h10 : _msb_T_168; // @[OneHot.scala:48:45] wire [5:0] _msb_T_170 = _msb_T_74 ? 6'hF : _msb_T_169; // @[OneHot.scala:48:45] wire [5:0] _msb_T_171 = _msb_T_73 ? 6'hE : _msb_T_170; // @[OneHot.scala:48:45] wire [5:0] _msb_T_172 = _msb_T_72 ? 6'hD : _msb_T_171; // @[OneHot.scala:48:45] wire [5:0] _msb_T_173 = _msb_T_71 ? 6'hC : _msb_T_172; // @[OneHot.scala:48:45] wire [5:0] _msb_T_174 = _msb_T_70 ? 6'hB : _msb_T_173; // @[OneHot.scala:48:45] wire [5:0] _msb_T_175 = _msb_T_69 ? 6'hA : _msb_T_174; // @[OneHot.scala:48:45] wire [5:0] _msb_T_176 = _msb_T_68 ? 6'h9 : _msb_T_175; // @[OneHot.scala:48:45] wire [5:0] _msb_T_177 = _msb_T_67 ? 6'h8 : _msb_T_176; // @[OneHot.scala:48:45] wire [5:0] _msb_T_178 = _msb_T_66 ? 6'h7 : _msb_T_177; // @[OneHot.scala:48:45] wire [5:0] _msb_T_179 = _msb_T_65 ? 6'h6 : _msb_T_178; // @[OneHot.scala:48:45] wire [5:0] _msb_T_180 = _msb_T_64 ? 6'h5 : _msb_T_179; // @[OneHot.scala:48:45] wire [5:0] _msb_T_181 = _msb_T_63 ? 6'h4 : _msb_T_180; // @[OneHot.scala:48:45] wire [5:0] _msb_T_182 = _msb_T_62 ? 6'h3 : _msb_T_181; // @[OneHot.scala:48:45] wire [5:0] _msb_T_183 = _msb_T_61 ? 6'h2 : _msb_T_182; // @[OneHot.scala:48:45] wire [5:0] _msb_T_184 = _msb_T_60 ? 6'h1 : _msb_T_183; // @[OneHot.scala:48:45] wire [5:0] _msb_T_185 = _msb_T_59 ? 6'h0 : _msb_T_184; // @[OneHot.scala:48:45] wire [7:0] _msb_T_186 = 8'h40 - {2'h0, _msb_T_185}; // @[Mux.scala:50:70] wire [6:0] msb = _msb_T_186[6:0]; // @[reqgen.scala:89:22] wire [36:0] _addr_T_1 = {3'h0, rand_val, 4'h0}; // @[PRNG.scala:95:17] wire [127:0] _addr_T_2 = 128'h1 << msb; // @[reqgen.scala:89:22, :90:62] wire [128:0] _addr_T_3 = {1'h0, _addr_T_2} - 129'h1; // @[reqgen.scala:90:{62,70}] wire [127:0] _addr_T_4 = _addr_T_3[127:0]; // @[reqgen.scala:90:70] wire [127:0] _addr_T_5 = {91'h0, _addr_T_4[36:0] & _addr_T_1}; // @[reqgen.scala:90:{46,54,70}] wire [15:0][63:0] _GEN_0 = {{start_addr_15}, {start_addr_14}, {start_addr_13}, {start_addr_12}, {start_addr_11}, {start_addr_10}, {start_addr_9}, {start_addr_8}, {start_addr_7}, {start_addr_6}, {start_addr_5}, {start_addr_4}, {start_addr_3}, {start_addr_2}, {start_addr_1}, {start_addr_0}}; // @[reqgen.scala:37:31, :90:33] wire [128:0] _addr_T_6 = {65'h0, _GEN_0[_addr_T]} + {1'h0, _addr_T_5}; // @[reqgen.scala:90:{33,54}] wire [127:0] _addr_T_7 = _addr_T_6[127:0]; // @[reqgen.scala:90:33] wire _T_13 = ~(|_GEN[_cur_stream_T]) | _GEN[_cur_stream_T] == 3'h1; // @[reqgen.scala:88:22, :91:{28,49,63}] wire [15:0][63:0] _GEN_1 = {{cur_addr_15}, {cur_addr_14}, {cur_addr_13}, {cur_addr_12}, {cur_addr_11}, {cur_addr_10}, {cur_addr_9}, {cur_addr_8}, {cur_addr_7}, {cur_addr_6}, {cur_addr_5}, {cur_addr_4}, {cur_addr_3}, {cur_addr_2}, {cur_addr_1}, {cur_addr_0}}; // @[reqgen.scala:41:31, :92:38] wire [15:0][63:0] _GEN_2 = {{stride_15}, {stride_14}, {stride_13}, {stride_12}, {stride_11}, {stride_10}, {stride_9}, {stride_8}, {stride_7}, {stride_6}, {stride_5}, {stride_4}, {stride_3}, {stride_2}, {stride_1}, {stride_0}}; // @[reqgen.scala:38:31, :92:38] wire [64:0] _nxt_addr_T_2 = {1'h0, _GEN_1[_nxt_addr_T]} + {1'h0, _GEN_2[_nxt_addr_T_1]}; // @[reqgen.scala:92:38] wire [63:0] nxt_addr = _nxt_addr_T_2[63:0]; // @[reqgen.scala:92:38] wire [15:0][63:0] _GEN_3 = {{end_addr_15}, {end_addr_14}, {end_addr_13}, {end_addr_12}, {end_addr_11}, {end_addr_10}, {end_addr_9}, {end_addr_8}, {end_addr_7}, {end_addr_6}, {end_addr_5}, {end_addr_4}, {end_addr_3}, {end_addr_2}, {end_addr_1}, {end_addr_0}}; // @[reqgen.scala:40:31, :93:22] assign addr = _T_10 ? _addr_T_7[63:0] : _T_13 ? (nxt_addr >= _GEN_3[s_idx[3:0]] ? _GEN_0[_addr_T_8] : nxt_addr) : _GEN[_cur_stream_T] == 3'h2 | _GEN[_cur_stream_T] == 3'h3 ? _GEN_0[_addr_T_9] : 64'h0; // @[reqgen.scala:79:28, :85:24, :88:{22,41,75}, :90:{12,33}, :91:{49,85}, :92:38, :93:{22,42}, :94:14, :96:14, :99:{28,48,62,83}, :103:12] wire cur_cmd; // @[reqgen.scala:106:27] assign cur_cmd = ~(~(|_GEN[_cur_stream_T]) | _GEN[_cur_stream_T] == 3'h2 | _T_23); // @[reqgen.scala:88:22, :91:28, :106:27, :107:{22,43}, :108:{22,42}, :109:42, :110:15, :112:15] wire [15:0] _GEN_4 = {{s_sent_done_15}, {s_sent_done_14}, {s_sent_done_13}, {s_sent_done_12}, {s_sent_done_11}, {s_sent_done_10}, {s_sent_done_9}, {s_sent_done_8}, {s_sent_done_7}, {s_sent_done_6}, {s_sent_done_5}, {s_sent_done_4}, {s_sent_done_3}, {s_sent_done_2}, {s_sent_done_1}, {s_sent_done_0}}; // @[reqgen.scala:81:28, :115:25] wire _io_req_valid_T_1 = ~_GEN_4[_io_req_valid_T]; // @[reqgen.scala:115:25] assign io_req_bits_data_addr_0 = io_send_reqs_0 ? addr : 64'h0; // @[reqgen.scala:26:7, :47:25, :83:23, :85:24, :116:27] assign io_req_bits_data_cmd_0 = io_send_reqs_0 & cur_cmd; // @[reqgen.scala:26:7, :48:25, :83:23, :106:27, :117:27] assign io_req_bits_data_data_0 = io_send_reqs_0 ? data[127:0] : 128'h0; // @[reqgen.scala:26:7, :50:25, :83:23, :86:39, :119:27] assign io_req_bits_idx_0 = io_send_reqs_0 ? s_idx[3:0] : 4'h0; // @[reqgen.scala:26:7, :51:19, :79:28, :83:23, :120:21] reg [63:0] loginfo_cycles_2; // @[util.scala:14:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[util.scala:14:33, :15:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[util.scala:15:38] wire [15:0][63:0] _GEN_5 = {{s_sent_15}, {s_sent_14}, {s_sent_13}, {s_sent_12}, {s_sent_11}, {s_sent_10}, {s_sent_9}, {s_sent_8}, {s_sent_7}, {s_sent_6}, {s_sent_5}, {s_sent_4}, {s_sent_3}, {s_sent_2}, {s_sent_1}, {s_sent_0}}; // @[util.scala:22:13] wire [63:0] _GEN_6 = _GEN_5[s_idx[3:0]]; // @[util.scala:22:13]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_153 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_153( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[1]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of SystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst xbar of IntXbar_i1_o1_1 inst xbar_1 of IntXbar_i1_o1_2 inst xbar_2 of IntXbar_i1_o1_3 inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1 inst broadcast of BundleBridgeNexus_UInt32_1 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_5 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_1 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[1] invalidate tileHaltSinkNodeIn[0] wire tileWFISinkNodeIn : UInt<1>[1] invalidate tileWFISinkNodeIn[0] wire tileCeaseSinkNodeIn : UInt<1>[1] invalidate tileCeaseSinkNodeIn[0] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}} invalidate traceNodesIn.custom.rob_empty invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid invalidate traceNodesIn.insns[1].tval invalidate traceNodesIn.insns[1].cause invalidate traceNodesIn.insns[1].interrupt invalidate traceNodesIn.insns[1].exception invalidate traceNodesIn.insns[1].priv invalidate traceNodesIn.insns[1].insn invalidate traceNodesIn.insns[1].iaddr invalidate traceNodesIn.insns[1].valid invalidate traceNodesIn.insns[2].tval invalidate traceNodesIn.insns[2].cause invalidate traceNodesIn.insns[2].interrupt invalidate traceNodesIn.insns[2].exception invalidate traceNodesIn.insns[2].priv invalidate traceNodesIn.insns[2].insn invalidate traceNodesIn.insns[2].iaddr invalidate traceNodesIn.insns[2].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_boom_tile_hartid_in, tileHartIdNexusNode.auto.out connect tile_prci_domain.auto.element_reset_domain_boom_tile_reset_vector_in, broadcast.auto.out connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect sbus.auto.coupler_from_boom_tile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell

module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9] wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [4:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [10:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [15:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7] wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7] wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7] wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7] wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7] wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7] wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7] wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7] wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7] wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7] wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7] wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [39:0] nexus_auto_in_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_1_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_1_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_2_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_2_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_1_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_1_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_2_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_2_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_nodeIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_1_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_1_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_2_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_2_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_1_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_1_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_2_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_2_tval = 40'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_auto_in_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_1_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_2_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_1_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_2_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_nodeIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_1_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_2_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] nexus_nodeOut_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] nexus_nodeOut_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_insns_1_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_insns_2_cause = 64'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_auto_in_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_1_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_2_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_1_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_2_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_nodeIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_1_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_2_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nexus_nodeOut_insns_1_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nexus_nodeOut_insns_2_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] traceNodesIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceNodesIn_insns_1_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceNodesIn_insns_2_priv = 3'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_auto_in_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_1_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_2_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_1_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_2_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_nodeIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_1_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_2_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_nodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_nodeOut_insns_2_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_1_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_2_insn = 32'h0; // @[MixedNode.scala:551:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_auto_in_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_nodeIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileWFISinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17] wire ioNodeIn_txd; // @[MixedNode.scala:551:17] wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17] wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7] wire debug_ndreset; // @[DigitalTop.scala:47:7] wire debug_dmactive_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] wire uart_0_txd_0; // @[DigitalTop.scala:47:7] wire clockTapIn_clock; // @[MixedNode.scala:551:17] wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9] wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9] wire ibus_childClock; // @[LazyModuleImp.scala:155:31] wire ibus_childReset; // @[LazyModuleImp.scala:158:31] assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17] wire nexus_nodeIn_custom_rob_empty = nexus_auto_in_custom_rob_empty; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17] wire traceNodesIn_custom_rob_empty = nexus_auto_out_custom_rob_empty; // @[MixedNode.scala:551:17] assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_custom_rob_empty = nexus_nodeIn_custom_rob_empty; // @[MixedNode.scala:542:17, :551:17] assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17] assign nexus_auto_out_custom_rob_empty = nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17] wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17] assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire domainIn_clock; // @[MixedNode.scala:551:17] wire domainIn_reset; // @[MixedNode.scala:551:17] wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17] wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17] assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24] wire int_rtc_tick; // @[Counter.scala:117:24] assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24] wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24] wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge) IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27] .auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9] .auto_anon_out_0 (ibus_auto_int_bus_anon_out_0) ); // @[InterruptBus.scala:19:27] SystemBus sbus ( // @[SystemBus.scala:31:26] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), // @[HasTiles.scala:163:38] .auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), .auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset), .auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock), .auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset), .auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), .auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) ); // @[SystemBus.scala:31:26] PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44] .auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset), .auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17] .auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt) ); // @[PeripheryBus.scala:37:26] FrontBus fbus ( // @[FrontBus.scala:23:26] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset), .auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17] .auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26] ); // @[FrontBus.scala:23:26] PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), .auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), .auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26] .auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), .auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), .auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), .auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), .auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), .auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset), .auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), .auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset), .auto_fixedClockNode_anon_out_2_clock (domainIn_clock), .auto_fixedClockNode_anon_out_2_reset (domainIn_reset), .auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), .auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17] .auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), .custom_boot (custom_boot) ); // @[PeripheryBus.scala:37:26] MemoryBus mbus ( // @[MemoryBus.scala:30:26] .auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28] .auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17] .auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset), .auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17] .auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt) ); // @[MemoryBus.scala:30:26] CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), .auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), .auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), .auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), .auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), .auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), .auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), .auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), .auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), .auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), .auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), .auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), .auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), .auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), .auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26] .auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), .auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), .auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), .auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), .auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), .auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), .auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26] .auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26] ); // @[BankedCoherenceParams.scala:56:31] TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38] .auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17] .auto_element_reset_domain_boom_tile_trace_source_out_time (nexus_auto_in_time), .auto_element_reset_domain_boom_tile_trace_source_out_custom_rob_empty (nexus_auto_in_custom_rob_empty), .auto_element_reset_domain_boom_tile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39] .auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28] .auto_tl_master_clock_xing_out_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), .auto_tl_master_clock_xing_out_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), .auto_tl_master_clock_xing_out_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), .auto_tl_master_clock_xing_out_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), .auto_tl_master_clock_xing_out_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), .auto_tl_master_clock_xing_out_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), .auto_tl_master_clock_xing_out_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), .auto_tl_master_clock_xing_out_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), .auto_tl_master_clock_xing_out_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), .auto_tl_master_clock_xing_out_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), .auto_tl_master_clock_xing_out_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), .auto_tl_master_clock_xing_out_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), .auto_tl_master_clock_xing_out_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), .auto_tl_master_clock_xing_out_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), .auto_tl_master_clock_xing_out_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), .auto_tl_master_clock_xing_out_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), .auto_tl_master_clock_xing_out_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), .auto_tl_master_clock_xing_out_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), .auto_tl_master_clock_xing_out_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), .auto_tl_master_clock_xing_out_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), .auto_tl_master_clock_xing_out_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), .auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26] .auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26] ); // @[HasTiles.scala:163:38] IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26] IntXbar_i1_o1_2 xbar_1 (); // @[Xbar.scala:52:26] IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26] BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39] .auto_out (_tileHartIdNexusNode_auto_out) ); // @[HasTiles.scala:75:39] CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28] .auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready), .auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid), .auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), .auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), .auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), .auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), .auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), .auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26] .tick (int_rtc_tick), // @[Counter.scala:117:24] .clock (_clint_domain_clock), .reset (_clint_domain_reset) ); // @[BusWrapper.scala:89:28] PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28] .auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9] .auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready), .auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid), .auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), .auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), .auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), .auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), .auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), .auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] TLDebugModule tlDM ( // @[Periphery.scala:88:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), .auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), .auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), .auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), .auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), .auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), .auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), .auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), .auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0), .io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7] .io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7] .io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17] .io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17] .io_ctrl_ndreset (debug_ndreset), .io_ctrl_dmactive (debug_dmactive_0), .io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7] .io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), .io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), .io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), .io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), .io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:88:26] DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75] BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28] .auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), .auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), .auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), .auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), .auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ScratchpadBank bank ( // @[Scratchpad.scala:65:28] .auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), .auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), .auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), .auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), .auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), .auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26] .auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26] ); // @[Scratchpad.scala:65:28] SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38] .auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), .auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), .auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), .auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), .auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), .auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), .auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), .auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), .auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), .auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), .auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26] .auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26] .serial_tl_0_in_ready (serial_tl_0_in_ready_0), .serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7] .serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_valid (serial_tl_0_out_valid_0), .serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0), .serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7] .serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy), .serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy) ); // @[PeripheryTLSerial.scala:116:38] TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44] .auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0), .auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), .auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), .auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), .auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), .auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), .auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), .auto_uart_0_io_out_txd (ioNodeIn_txd), .auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17] .auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26] ); // @[UART.scala:270:44] IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (ibus_auto_int_bus_anon_in_0) ); // @[Crossing.scala:109:29] ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28] .auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7] .auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7] .auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), .auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), .auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30] .auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock), .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset), .auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock), .auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset), .auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock), .auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset), .auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock), .auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset), .auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock), .auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset), .auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock), .auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset), .auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock), .auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset) ); // @[HasChipyardPRCI.scala:51:30] ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15] .auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock), .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset), .auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset) ); // @[ClockGroupCombiner.scala:19:15] ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40] .auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26] .auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26] ); // @[GlobalNoC.scala:45:40] BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44] DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21] .io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26] .io_dmi_req_valid (_dtm_io_dmi_req_valid), .io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), .io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), .io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), .io_dmi_resp_ready (_dtm_io_dmi_resp_ready), .io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26] .io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26] .io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26] .io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7] .io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7] .io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0), .io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven), .rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:166:21] assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7] assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_73 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_159 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_160 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_73( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PE_23 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_d : { bits : UInt<32>}, out_a : { bits : UInt<32>}, out_b : { bits : UInt<32>}, out_c : { bits : UInt<32>}, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<4>, out_id : UInt<4>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_7 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : { bits : UInt<32>}, clock reg c2 : { bits : UInt<32>}, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a.bits, io.in_a.bits reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node io_out_c_self_rec_rawIn_sign = bits(c1.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn = bits(c1.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn = bits(c1.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn = eq(io_out_c_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn = eq(io_out_c_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T = bits(io_out_c_self_rec_rawIn_fractIn, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_1 = bits(io_out_c_self_rec_rawIn_fractIn, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_2 = bits(io_out_c_self_rec_rawIn_fractIn, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_3 = bits(io_out_c_self_rec_rawIn_fractIn, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_4 = bits(io_out_c_self_rec_rawIn_fractIn, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_5 = bits(io_out_c_self_rec_rawIn_fractIn, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_6 = bits(io_out_c_self_rec_rawIn_fractIn, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_7 = bits(io_out_c_self_rec_rawIn_fractIn, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_8 = bits(io_out_c_self_rec_rawIn_fractIn, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_9 = bits(io_out_c_self_rec_rawIn_fractIn, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_10 = bits(io_out_c_self_rec_rawIn_fractIn, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_11 = bits(io_out_c_self_rec_rawIn_fractIn, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_12 = bits(io_out_c_self_rec_rawIn_fractIn, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_13 = bits(io_out_c_self_rec_rawIn_fractIn, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_14 = bits(io_out_c_self_rec_rawIn_fractIn, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_15 = bits(io_out_c_self_rec_rawIn_fractIn, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_16 = bits(io_out_c_self_rec_rawIn_fractIn, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_17 = bits(io_out_c_self_rec_rawIn_fractIn, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_18 = bits(io_out_c_self_rec_rawIn_fractIn, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_19 = bits(io_out_c_self_rec_rawIn_fractIn, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_20 = bits(io_out_c_self_rec_rawIn_fractIn, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_21 = bits(io_out_c_self_rec_rawIn_fractIn, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_22 = bits(io_out_c_self_rec_rawIn_fractIn, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_23 = mux(_io_out_c_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_24 = mux(_io_out_c_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_23) node _io_out_c_self_rec_rawIn_normDist_T_25 = mux(_io_out_c_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_24) node _io_out_c_self_rec_rawIn_normDist_T_26 = mux(_io_out_c_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_25) node _io_out_c_self_rec_rawIn_normDist_T_27 = mux(_io_out_c_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_26) node _io_out_c_self_rec_rawIn_normDist_T_28 = mux(_io_out_c_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_27) node _io_out_c_self_rec_rawIn_normDist_T_29 = mux(_io_out_c_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_28) node _io_out_c_self_rec_rawIn_normDist_T_30 = mux(_io_out_c_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_29) node _io_out_c_self_rec_rawIn_normDist_T_31 = mux(_io_out_c_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_30) node _io_out_c_self_rec_rawIn_normDist_T_32 = mux(_io_out_c_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_31) node _io_out_c_self_rec_rawIn_normDist_T_33 = mux(_io_out_c_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_32) node _io_out_c_self_rec_rawIn_normDist_T_34 = mux(_io_out_c_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_33) node _io_out_c_self_rec_rawIn_normDist_T_35 = mux(_io_out_c_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_34) node _io_out_c_self_rec_rawIn_normDist_T_36 = mux(_io_out_c_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_35) node _io_out_c_self_rec_rawIn_normDist_T_37 = mux(_io_out_c_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_36) node _io_out_c_self_rec_rawIn_normDist_T_38 = mux(_io_out_c_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_37) node _io_out_c_self_rec_rawIn_normDist_T_39 = mux(_io_out_c_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_38) node _io_out_c_self_rec_rawIn_normDist_T_40 = mux(_io_out_c_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_39) node _io_out_c_self_rec_rawIn_normDist_T_41 = mux(_io_out_c_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_40) node _io_out_c_self_rec_rawIn_normDist_T_42 = mux(_io_out_c_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_41) node _io_out_c_self_rec_rawIn_normDist_T_43 = mux(_io_out_c_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_42) node io_out_c_self_rec_rawIn_normDist = mux(_io_out_c_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_43) node _io_out_c_self_rec_rawIn_subnormFract_T = dshl(io_out_c_self_rec_rawIn_fractIn, io_out_c_self_rec_rawIn_normDist) node _io_out_c_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_self_rec_rawIn_subnormFract = shl(_io_out_c_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T = xor(io_out_c_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, _io_out_c_self_rec_rawIn_adjustedExp_T, io_out_c_self_rec_rawIn_expIn) node _io_out_c_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_1, _io_out_c_self_rec_rawIn_adjustedExp_T_3) node io_out_c_self_rec_rawIn_adjustedExp = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_self_rec_rawIn_isZero = and(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_isZeroFractIn) node _io_out_c_self_rec_rawIn_isSpecial_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 7) node io_out_c_self_rec_rawIn_isSpecial = eq(_io_out_c_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T = eq(io_out_c_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_1 = and(io_out_c_self_rec_rawIn_isSpecial, _io_out_c_self_rec_rawIn_out_isNaN_T) connect io_out_c_self_rec_rawIn.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_1 node _io_out_c_self_rec_rawIn_out_isInf_T = and(io_out_c_self_rec_rawIn_isSpecial, io_out_c_self_rec_rawIn_isZeroFractIn) connect io_out_c_self_rec_rawIn.isInf, _io_out_c_self_rec_rawIn_out_isInf_T connect io_out_c_self_rec_rawIn.isZero, io_out_c_self_rec_rawIn_isZero connect io_out_c_self_rec_rawIn.sign, io_out_c_self_rec_rawIn_sign node _io_out_c_self_rec_rawIn_out_sExp_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T) connect io_out_c_self_rec_rawIn.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_1 node _io_out_c_self_rec_rawIn_out_sig_T = eq(io_out_c_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T) node _io_out_c_self_rec_rawIn_out_sig_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_subnormFract, io_out_c_self_rec_rawIn_fractIn) node _io_out_c_self_rec_rawIn_out_sig_T_3 = cat(_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2) connect io_out_c_self_rec_rawIn.sig, _io_out_c_self_rec_rawIn_out_sig_T_3 node _io_out_c_self_rec_T = bits(io_out_c_self_rec_rawIn.sExp, 8, 6) node _io_out_c_self_rec_T_1 = mux(io_out_c_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_self_rec_T) node _io_out_c_self_rec_T_2 = mux(io_out_c_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_3 = or(_io_out_c_self_rec_T_1, _io_out_c_self_rec_T_2) node _io_out_c_self_rec_T_4 = cat(io_out_c_self_rec_rawIn.sign, _io_out_c_self_rec_T_3) node _io_out_c_self_rec_T_5 = bits(io_out_c_self_rec_rawIn.sExp, 5, 0) node _io_out_c_self_rec_T_6 = cat(_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5) node _io_out_c_self_rec_T_7 = bits(io_out_c_self_rec_rawIn.sig, 22, 0) node io_out_c_self_rec = cat(_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7) wire io_out_c_shift_exp : UInt<8> node _io_out_c_shift_exp_T = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_1 = tail(_io_out_c_shift_exp_T, 1) connect io_out_c_shift_exp, _io_out_c_shift_exp_T_1 node io_out_c_shift_fn_hi = cat(UInt<1>(0h0), io_out_c_shift_exp) node io_out_c_shift_fn = cat(io_out_c_shift_fn_hi, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign = bits(io_out_c_shift_fn, 31, 31) node io_out_c_shift_rec_rawIn_expIn = bits(io_out_c_shift_fn, 30, 23) node io_out_c_shift_rec_rawIn_fractIn = bits(io_out_c_shift_fn, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn = eq(io_out_c_shift_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn = eq(io_out_c_shift_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T = bits(io_out_c_shift_rec_rawIn_fractIn, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_1 = bits(io_out_c_shift_rec_rawIn_fractIn, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_2 = bits(io_out_c_shift_rec_rawIn_fractIn, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_3 = bits(io_out_c_shift_rec_rawIn_fractIn, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_4 = bits(io_out_c_shift_rec_rawIn_fractIn, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_5 = bits(io_out_c_shift_rec_rawIn_fractIn, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_6 = bits(io_out_c_shift_rec_rawIn_fractIn, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_7 = bits(io_out_c_shift_rec_rawIn_fractIn, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_8 = bits(io_out_c_shift_rec_rawIn_fractIn, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_9 = bits(io_out_c_shift_rec_rawIn_fractIn, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_10 = bits(io_out_c_shift_rec_rawIn_fractIn, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_11 = bits(io_out_c_shift_rec_rawIn_fractIn, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_12 = bits(io_out_c_shift_rec_rawIn_fractIn, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_13 = bits(io_out_c_shift_rec_rawIn_fractIn, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_14 = bits(io_out_c_shift_rec_rawIn_fractIn, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_15 = bits(io_out_c_shift_rec_rawIn_fractIn, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_16 = bits(io_out_c_shift_rec_rawIn_fractIn, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_17 = bits(io_out_c_shift_rec_rawIn_fractIn, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_18 = bits(io_out_c_shift_rec_rawIn_fractIn, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_19 = bits(io_out_c_shift_rec_rawIn_fractIn, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_20 = bits(io_out_c_shift_rec_rawIn_fractIn, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_21 = bits(io_out_c_shift_rec_rawIn_fractIn, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_22 = bits(io_out_c_shift_rec_rawIn_fractIn, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_23 = mux(_io_out_c_shift_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_24 = mux(_io_out_c_shift_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_23) node _io_out_c_shift_rec_rawIn_normDist_T_25 = mux(_io_out_c_shift_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_24) node _io_out_c_shift_rec_rawIn_normDist_T_26 = mux(_io_out_c_shift_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_25) node _io_out_c_shift_rec_rawIn_normDist_T_27 = mux(_io_out_c_shift_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_26) node _io_out_c_shift_rec_rawIn_normDist_T_28 = mux(_io_out_c_shift_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_27) node _io_out_c_shift_rec_rawIn_normDist_T_29 = mux(_io_out_c_shift_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_28) node _io_out_c_shift_rec_rawIn_normDist_T_30 = mux(_io_out_c_shift_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_29) node _io_out_c_shift_rec_rawIn_normDist_T_31 = mux(_io_out_c_shift_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_30) node _io_out_c_shift_rec_rawIn_normDist_T_32 = mux(_io_out_c_shift_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_31) node _io_out_c_shift_rec_rawIn_normDist_T_33 = mux(_io_out_c_shift_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_32) node _io_out_c_shift_rec_rawIn_normDist_T_34 = mux(_io_out_c_shift_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_33) node _io_out_c_shift_rec_rawIn_normDist_T_35 = mux(_io_out_c_shift_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_34) node _io_out_c_shift_rec_rawIn_normDist_T_36 = mux(_io_out_c_shift_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_35) node _io_out_c_shift_rec_rawIn_normDist_T_37 = mux(_io_out_c_shift_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_36) node _io_out_c_shift_rec_rawIn_normDist_T_38 = mux(_io_out_c_shift_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_37) node _io_out_c_shift_rec_rawIn_normDist_T_39 = mux(_io_out_c_shift_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_38) node _io_out_c_shift_rec_rawIn_normDist_T_40 = mux(_io_out_c_shift_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_39) node _io_out_c_shift_rec_rawIn_normDist_T_41 = mux(_io_out_c_shift_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_40) node _io_out_c_shift_rec_rawIn_normDist_T_42 = mux(_io_out_c_shift_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_41) node _io_out_c_shift_rec_rawIn_normDist_T_43 = mux(_io_out_c_shift_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_42) node io_out_c_shift_rec_rawIn_normDist = mux(_io_out_c_shift_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_43) node _io_out_c_shift_rec_rawIn_subnormFract_T = dshl(io_out_c_shift_rec_rawIn_fractIn, io_out_c_shift_rec_rawIn_normDist) node _io_out_c_shift_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T = xor(io_out_c_shift_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, _io_out_c_shift_rec_rawIn_adjustedExp_T, io_out_c_shift_rec_rawIn_expIn) node _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_2) node _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_3) node io_out_c_shift_rec_rawIn_adjustedExp = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_shift_rec_rawIn_isZero = and(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_isZeroFractIn) node _io_out_c_shift_rec_rawIn_isSpecial_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial = eq(_io_out_c_shift_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T = eq(io_out_c_shift_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial, _io_out_c_shift_rec_rawIn_out_isNaN_T) connect io_out_c_shift_rec_rawIn.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_1 node _io_out_c_shift_rec_rawIn_out_isInf_T = and(io_out_c_shift_rec_rawIn_isSpecial, io_out_c_shift_rec_rawIn_isZeroFractIn) connect io_out_c_shift_rec_rawIn.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T connect io_out_c_shift_rec_rawIn.isZero, io_out_c_shift_rec_rawIn_isZero connect io_out_c_shift_rec_rawIn.sign, io_out_c_shift_rec_rawIn_sign node _io_out_c_shift_rec_rawIn_out_sExp_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T) connect io_out_c_shift_rec_rawIn.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_1 node _io_out_c_shift_rec_rawIn_out_sig_T = eq(io_out_c_shift_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T) node _io_out_c_shift_rec_rawIn_out_sig_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_subnormFract, io_out_c_shift_rec_rawIn_fractIn) node _io_out_c_shift_rec_rawIn_out_sig_T_3 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2) connect io_out_c_shift_rec_rawIn.sig, _io_out_c_shift_rec_rawIn_out_sig_T_3 node _io_out_c_shift_rec_T = bits(io_out_c_shift_rec_rawIn.sExp, 8, 6) node _io_out_c_shift_rec_T_1 = mux(io_out_c_shift_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T) node _io_out_c_shift_rec_T_2 = mux(io_out_c_shift_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_3 = or(_io_out_c_shift_rec_T_1, _io_out_c_shift_rec_T_2) node _io_out_c_shift_rec_T_4 = cat(io_out_c_shift_rec_rawIn.sign, _io_out_c_shift_rec_T_3) node _io_out_c_shift_rec_T_5 = bits(io_out_c_shift_rec_rawIn.sExp, 5, 0) node _io_out_c_shift_rec_T_6 = cat(_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5) node _io_out_c_shift_rec_T_7 = bits(io_out_c_shift_rec_rawIn.sig, 22, 0) node io_out_c_shift_rec = cat(_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7) node _io_out_c_T = neq(io_out_c_shift_exp, UInt<1>(0h0)) node _io_out_c_T_1 = asUInt(reset) node _io_out_c_T_2 = eq(_io_out_c_T_1, UInt<1>(0h0)) when _io_out_c_T_2 : node _io_out_c_T_3 = eq(_io_out_c_T, UInt<1>(0h0)) when _io_out_c_T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf assert(clock, _io_out_c_T, UInt<1>(0h1), "") : io_out_c_assert inst io_out_c_muladder of MulRecFN_38 connect io_out_c_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder.io.a, io_out_c_self_rec connect io_out_c_muladder.io.b, io_out_c_shift_rec wire io_out_c_result : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp = bits(io_out_c_muladder.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T = bits(io_out_c_result_bits_rawIn_exp, 8, 6) node io_out_c_result_bits_rawIn_isZero = eq(_io_out_c_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T = bits(io_out_c_result_bits_rawIn_exp, 8, 7) node io_out_c_result_bits_rawIn_isSpecial = eq(_io_out_c_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_1 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isNaN_T) connect io_out_c_result_bits_rawIn.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_1 node _io_out_c_result_bits_rawIn_out_isInf_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_1 = eq(_io_out_c_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_2 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isInf_T_1) connect io_out_c_result_bits_rawIn.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_2 connect io_out_c_result_bits_rawIn.isZero, io_out_c_result_bits_rawIn_isZero node _io_out_c_result_bits_rawIn_out_sign_T = bits(io_out_c_muladder.io.out, 32, 32) connect io_out_c_result_bits_rawIn.sign, _io_out_c_result_bits_rawIn_out_sign_T node _io_out_c_result_bits_rawIn_out_sExp_T = cvt(io_out_c_result_bits_rawIn_exp) connect io_out_c_result_bits_rawIn.sExp, _io_out_c_result_bits_rawIn_out_sExp_T node _io_out_c_result_bits_rawIn_out_sig_T = eq(io_out_c_result_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T) node _io_out_c_result_bits_rawIn_out_sig_T_2 = bits(io_out_c_muladder.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_3 = cat(_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2) connect io_out_c_result_bits_rawIn.sig, _io_out_c_result_bits_rawIn_out_sig_T_3 node io_out_c_result_bits_isSubnormal = lt(io_out_c_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T = bits(io_out_c_result_bits_rawIn.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T) node io_out_c_result_bits_denormShiftDist = tail(_io_out_c_result_bits_denormShiftDist_T_1, 1) node _io_out_c_result_bits_denormFract_T = shr(io_out_c_result_bits_rawIn.sig, 1) node _io_out_c_result_bits_denormFract_T_1 = dshr(_io_out_c_result_bits_denormFract_T, io_out_c_result_bits_denormShiftDist) node io_out_c_result_bits_denormFract = bits(_io_out_c_result_bits_denormFract_T_1, 22, 0) node _io_out_c_result_bits_expOut_T = bits(io_out_c_result_bits_rawIn.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_1 = sub(_io_out_c_result_bits_expOut_T, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_2 = tail(_io_out_c_result_bits_expOut_T_1, 1) node _io_out_c_result_bits_expOut_T_3 = mux(io_out_c_result_bits_isSubnormal, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_2) node _io_out_c_result_bits_expOut_T_4 = or(io_out_c_result_bits_rawIn.isNaN, io_out_c_result_bits_rawIn.isInf) node _io_out_c_result_bits_expOut_T_5 = mux(_io_out_c_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut = or(_io_out_c_result_bits_expOut_T_3, _io_out_c_result_bits_expOut_T_5) node _io_out_c_result_bits_fractOut_T = bits(io_out_c_result_bits_rawIn.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_1 = mux(io_out_c_result_bits_rawIn.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T) node io_out_c_result_bits_fractOut = mux(io_out_c_result_bits_isSubnormal, io_out_c_result_bits_denormFract, _io_out_c_result_bits_fractOut_T_1) node io_out_c_result_bits_hi = cat(io_out_c_result_bits_rawIn.sign, io_out_c_result_bits_expOut) node _io_out_c_result_bits_T = cat(io_out_c_result_bits_hi, io_out_c_result_bits_fractOut) connect io_out_c_result.bits, _io_out_c_result_bits_T node io_out_c_self_rec_rawIn_sign_1 = bits(io_out_c_result.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_1 = bits(io_out_c_result.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_1 = bits(io_out_c_result.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_self_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_self_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_44 = bits(io_out_c_self_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_45 = bits(io_out_c_self_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_46 = bits(io_out_c_self_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_47 = bits(io_out_c_self_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_48 = bits(io_out_c_self_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_49 = bits(io_out_c_self_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_50 = bits(io_out_c_self_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_51 = bits(io_out_c_self_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_52 = bits(io_out_c_self_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_53 = bits(io_out_c_self_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_54 = bits(io_out_c_self_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_55 = bits(io_out_c_self_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_56 = bits(io_out_c_self_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_57 = bits(io_out_c_self_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_58 = bits(io_out_c_self_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_59 = bits(io_out_c_self_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_60 = bits(io_out_c_self_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_61 = bits(io_out_c_self_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_62 = bits(io_out_c_self_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_63 = bits(io_out_c_self_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_64 = bits(io_out_c_self_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_65 = bits(io_out_c_self_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_66 = bits(io_out_c_self_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_67 = mux(_io_out_c_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_68 = mux(_io_out_c_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_67) node _io_out_c_self_rec_rawIn_normDist_T_69 = mux(_io_out_c_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_68) node _io_out_c_self_rec_rawIn_normDist_T_70 = mux(_io_out_c_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_69) node _io_out_c_self_rec_rawIn_normDist_T_71 = mux(_io_out_c_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_70) node _io_out_c_self_rec_rawIn_normDist_T_72 = mux(_io_out_c_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_71) node _io_out_c_self_rec_rawIn_normDist_T_73 = mux(_io_out_c_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_72) node _io_out_c_self_rec_rawIn_normDist_T_74 = mux(_io_out_c_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_73) node _io_out_c_self_rec_rawIn_normDist_T_75 = mux(_io_out_c_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_74) node _io_out_c_self_rec_rawIn_normDist_T_76 = mux(_io_out_c_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_75) node _io_out_c_self_rec_rawIn_normDist_T_77 = mux(_io_out_c_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_76) node _io_out_c_self_rec_rawIn_normDist_T_78 = mux(_io_out_c_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_77) node _io_out_c_self_rec_rawIn_normDist_T_79 = mux(_io_out_c_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_78) node _io_out_c_self_rec_rawIn_normDist_T_80 = mux(_io_out_c_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_79) node _io_out_c_self_rec_rawIn_normDist_T_81 = mux(_io_out_c_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_80) node _io_out_c_self_rec_rawIn_normDist_T_82 = mux(_io_out_c_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_81) node _io_out_c_self_rec_rawIn_normDist_T_83 = mux(_io_out_c_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_82) node _io_out_c_self_rec_rawIn_normDist_T_84 = mux(_io_out_c_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_83) node _io_out_c_self_rec_rawIn_normDist_T_85 = mux(_io_out_c_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_84) node _io_out_c_self_rec_rawIn_normDist_T_86 = mux(_io_out_c_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_85) node _io_out_c_self_rec_rawIn_normDist_T_87 = mux(_io_out_c_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_86) node io_out_c_self_rec_rawIn_normDist_1 = mux(_io_out_c_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_87) node _io_out_c_self_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_self_rec_rawIn_fractIn_1, io_out_c_self_rec_rawIn_normDist_1) node _io_out_c_self_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_1 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_self_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, _io_out_c_self_rec_rawIn_adjustedExp_T_5, io_out_c_self_rec_rawIn_expIn_1) node _io_out_c_self_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_7) node _io_out_c_self_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_6, _io_out_c_self_rec_rawIn_adjustedExp_T_8) node io_out_c_self_rec_rawIn_adjustedExp_1 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_self_rec_rawIn_isZero_1 = and(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) node _io_out_c_self_rec_rawIn_isSpecial_T_1 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_1 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_1, _io_out_c_self_rec_rawIn_out_isNaN_T_2) connect io_out_c_self_rec_rawIn_1.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_3 node _io_out_c_self_rec_rawIn_out_isInf_T_1 = and(io_out_c_self_rec_rawIn_isSpecial_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) connect io_out_c_self_rec_rawIn_1.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_1 connect io_out_c_self_rec_rawIn_1.isZero, io_out_c_self_rec_rawIn_isZero_1 connect io_out_c_self_rec_rawIn_1.sign, io_out_c_self_rec_rawIn_sign_1 node _io_out_c_self_rec_rawIn_out_sExp_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_2) connect io_out_c_self_rec_rawIn_1.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_3 node _io_out_c_self_rec_rawIn_out_sig_T_4 = eq(io_out_c_self_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_4) node _io_out_c_self_rec_rawIn_out_sig_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_subnormFract_1, io_out_c_self_rec_rawIn_fractIn_1) node _io_out_c_self_rec_rawIn_out_sig_T_7 = cat(_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6) connect io_out_c_self_rec_rawIn_1.sig, _io_out_c_self_rec_rawIn_out_sig_T_7 node _io_out_c_self_rec_T_8 = bits(io_out_c_self_rec_rawIn_1.sExp, 8, 6) node _io_out_c_self_rec_T_9 = mux(io_out_c_self_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_8) node _io_out_c_self_rec_T_10 = mux(io_out_c_self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_11 = or(_io_out_c_self_rec_T_9, _io_out_c_self_rec_T_10) node _io_out_c_self_rec_T_12 = cat(io_out_c_self_rec_rawIn_1.sign, _io_out_c_self_rec_T_11) node _io_out_c_self_rec_T_13 = bits(io_out_c_self_rec_rawIn_1.sExp, 5, 0) node _io_out_c_self_rec_T_14 = cat(_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13) node _io_out_c_self_rec_T_15 = bits(io_out_c_self_rec_rawIn_1.sig, 22, 0) node io_out_c_self_rec_1 = cat(_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15) inst io_out_c_resizer of RecFNToRecFN_188 connect io_out_c_resizer.io.in, io_out_c_self_rec_1 connect io_out_c_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_1 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_1 = bits(io_out_c_resizer.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 6) node io_out_c_result_bits_rawIn_isZero_1 = eq(_io_out_c_result_bits_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_1 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_2 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_3 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isNaN_T_2) connect io_out_c_result_bits_rawIn_1.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_3 node _io_out_c_result_bits_rawIn_out_isInf_T_3 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_4 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isInf_T_4) connect io_out_c_result_bits_rawIn_1.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_5 connect io_out_c_result_bits_rawIn_1.isZero, io_out_c_result_bits_rawIn_isZero_1 node _io_out_c_result_bits_rawIn_out_sign_T_1 = bits(io_out_c_resizer.io.out, 32, 32) connect io_out_c_result_bits_rawIn_1.sign, _io_out_c_result_bits_rawIn_out_sign_T_1 node _io_out_c_result_bits_rawIn_out_sExp_T_1 = cvt(io_out_c_result_bits_rawIn_exp_1) connect io_out_c_result_bits_rawIn_1.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_1 node _io_out_c_result_bits_rawIn_out_sig_T_4 = eq(io_out_c_result_bits_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_4) node _io_out_c_result_bits_rawIn_out_sig_T_6 = bits(io_out_c_resizer.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_7 = cat(_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6) connect io_out_c_result_bits_rawIn_1.sig, _io_out_c_result_bits_rawIn_out_sig_T_7 node io_out_c_result_bits_isSubnormal_1 = lt(io_out_c_result_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_2 = bits(io_out_c_result_bits_rawIn_1.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_2) node io_out_c_result_bits_denormShiftDist_1 = tail(_io_out_c_result_bits_denormShiftDist_T_3, 1) node _io_out_c_result_bits_denormFract_T_2 = shr(io_out_c_result_bits_rawIn_1.sig, 1) node _io_out_c_result_bits_denormFract_T_3 = dshr(_io_out_c_result_bits_denormFract_T_2, io_out_c_result_bits_denormShiftDist_1) node io_out_c_result_bits_denormFract_1 = bits(_io_out_c_result_bits_denormFract_T_3, 22, 0) node _io_out_c_result_bits_expOut_T_6 = bits(io_out_c_result_bits_rawIn_1.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_7 = sub(_io_out_c_result_bits_expOut_T_6, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_8 = tail(_io_out_c_result_bits_expOut_T_7, 1) node _io_out_c_result_bits_expOut_T_9 = mux(io_out_c_result_bits_isSubnormal_1, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_8) node _io_out_c_result_bits_expOut_T_10 = or(io_out_c_result_bits_rawIn_1.isNaN, io_out_c_result_bits_rawIn_1.isInf) node _io_out_c_result_bits_expOut_T_11 = mux(_io_out_c_result_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_1 = or(_io_out_c_result_bits_expOut_T_9, _io_out_c_result_bits_expOut_T_11) node _io_out_c_result_bits_fractOut_T_2 = bits(io_out_c_result_bits_rawIn_1.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_3 = mux(io_out_c_result_bits_rawIn_1.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_2) node io_out_c_result_bits_fractOut_1 = mux(io_out_c_result_bits_isSubnormal_1, io_out_c_result_bits_denormFract_1, _io_out_c_result_bits_fractOut_T_3) node io_out_c_result_bits_hi_1 = cat(io_out_c_result_bits_rawIn_1.sign, io_out_c_result_bits_expOut_1) node _io_out_c_result_bits_T_1 = cat(io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1) connect io_out_c_result_1.bits, _io_out_c_result_bits_T_1 connect io.out_c, io_out_c_result_1 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_1 : UInt<32> connect _mac_unit_io_in_b_WIRE_1, io.in_b.bits node _mac_unit_io_in_b_T = bits(_mac_unit_io_in_b_WIRE_1, 31, 0) connect _mac_unit_io_in_b_WIRE.bits, _mac_unit_io_in_b_T connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE.bits connect mac_unit.io.in_c.bits, c2.bits connect c2, mac_unit.io.out_d node c1_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c1_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c1_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c1_self_rec_rawIn_isZeroExpIn = eq(c1_self_rec_rawIn_expIn, UInt<1>(0h0)) node c1_self_rec_rawIn_isZeroFractIn = eq(c1_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_normDist_T = bits(c1_self_rec_rawIn_fractIn, 0, 0) node _c1_self_rec_rawIn_normDist_T_1 = bits(c1_self_rec_rawIn_fractIn, 1, 1) node _c1_self_rec_rawIn_normDist_T_2 = bits(c1_self_rec_rawIn_fractIn, 2, 2) node _c1_self_rec_rawIn_normDist_T_3 = bits(c1_self_rec_rawIn_fractIn, 3, 3) node _c1_self_rec_rawIn_normDist_T_4 = bits(c1_self_rec_rawIn_fractIn, 4, 4) node _c1_self_rec_rawIn_normDist_T_5 = bits(c1_self_rec_rawIn_fractIn, 5, 5) node _c1_self_rec_rawIn_normDist_T_6 = bits(c1_self_rec_rawIn_fractIn, 6, 6) node _c1_self_rec_rawIn_normDist_T_7 = bits(c1_self_rec_rawIn_fractIn, 7, 7) node _c1_self_rec_rawIn_normDist_T_8 = bits(c1_self_rec_rawIn_fractIn, 8, 8) node _c1_self_rec_rawIn_normDist_T_9 = bits(c1_self_rec_rawIn_fractIn, 9, 9) node _c1_self_rec_rawIn_normDist_T_10 = bits(c1_self_rec_rawIn_fractIn, 10, 10) node _c1_self_rec_rawIn_normDist_T_11 = bits(c1_self_rec_rawIn_fractIn, 11, 11) node _c1_self_rec_rawIn_normDist_T_12 = bits(c1_self_rec_rawIn_fractIn, 12, 12) node _c1_self_rec_rawIn_normDist_T_13 = bits(c1_self_rec_rawIn_fractIn, 13, 13) node _c1_self_rec_rawIn_normDist_T_14 = bits(c1_self_rec_rawIn_fractIn, 14, 14) node _c1_self_rec_rawIn_normDist_T_15 = bits(c1_self_rec_rawIn_fractIn, 15, 15) node _c1_self_rec_rawIn_normDist_T_16 = bits(c1_self_rec_rawIn_fractIn, 16, 16) node _c1_self_rec_rawIn_normDist_T_17 = bits(c1_self_rec_rawIn_fractIn, 17, 17) node _c1_self_rec_rawIn_normDist_T_18 = bits(c1_self_rec_rawIn_fractIn, 18, 18) node _c1_self_rec_rawIn_normDist_T_19 = bits(c1_self_rec_rawIn_fractIn, 19, 19) node _c1_self_rec_rawIn_normDist_T_20 = bits(c1_self_rec_rawIn_fractIn, 20, 20) node _c1_self_rec_rawIn_normDist_T_21 = bits(c1_self_rec_rawIn_fractIn, 21, 21) node _c1_self_rec_rawIn_normDist_T_22 = bits(c1_self_rec_rawIn_fractIn, 22, 22) node _c1_self_rec_rawIn_normDist_T_23 = mux(_c1_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c1_self_rec_rawIn_normDist_T_24 = mux(_c1_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c1_self_rec_rawIn_normDist_T_23) node _c1_self_rec_rawIn_normDist_T_25 = mux(_c1_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c1_self_rec_rawIn_normDist_T_24) node _c1_self_rec_rawIn_normDist_T_26 = mux(_c1_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c1_self_rec_rawIn_normDist_T_25) node _c1_self_rec_rawIn_normDist_T_27 = mux(_c1_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c1_self_rec_rawIn_normDist_T_26) node _c1_self_rec_rawIn_normDist_T_28 = mux(_c1_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c1_self_rec_rawIn_normDist_T_27) node _c1_self_rec_rawIn_normDist_T_29 = mux(_c1_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c1_self_rec_rawIn_normDist_T_28) node _c1_self_rec_rawIn_normDist_T_30 = mux(_c1_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c1_self_rec_rawIn_normDist_T_29) node _c1_self_rec_rawIn_normDist_T_31 = mux(_c1_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c1_self_rec_rawIn_normDist_T_30) node _c1_self_rec_rawIn_normDist_T_32 = mux(_c1_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c1_self_rec_rawIn_normDist_T_31) node _c1_self_rec_rawIn_normDist_T_33 = mux(_c1_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c1_self_rec_rawIn_normDist_T_32) node _c1_self_rec_rawIn_normDist_T_34 = mux(_c1_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c1_self_rec_rawIn_normDist_T_33) node _c1_self_rec_rawIn_normDist_T_35 = mux(_c1_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c1_self_rec_rawIn_normDist_T_34) node _c1_self_rec_rawIn_normDist_T_36 = mux(_c1_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c1_self_rec_rawIn_normDist_T_35) node _c1_self_rec_rawIn_normDist_T_37 = mux(_c1_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c1_self_rec_rawIn_normDist_T_36) node _c1_self_rec_rawIn_normDist_T_38 = mux(_c1_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c1_self_rec_rawIn_normDist_T_37) node _c1_self_rec_rawIn_normDist_T_39 = mux(_c1_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c1_self_rec_rawIn_normDist_T_38) node _c1_self_rec_rawIn_normDist_T_40 = mux(_c1_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c1_self_rec_rawIn_normDist_T_39) node _c1_self_rec_rawIn_normDist_T_41 = mux(_c1_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c1_self_rec_rawIn_normDist_T_40) node _c1_self_rec_rawIn_normDist_T_42 = mux(_c1_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c1_self_rec_rawIn_normDist_T_41) node _c1_self_rec_rawIn_normDist_T_43 = mux(_c1_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c1_self_rec_rawIn_normDist_T_42) node c1_self_rec_rawIn_normDist = mux(_c1_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c1_self_rec_rawIn_normDist_T_43) node _c1_self_rec_rawIn_subnormFract_T = dshl(c1_self_rec_rawIn_fractIn, c1_self_rec_rawIn_normDist) node _c1_self_rec_rawIn_subnormFract_T_1 = bits(_c1_self_rec_rawIn_subnormFract_T, 21, 0) node c1_self_rec_rawIn_subnormFract = shl(_c1_self_rec_rawIn_subnormFract_T_1, 1) node _c1_self_rec_rawIn_adjustedExp_T = xor(c1_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c1_self_rec_rawIn_adjustedExp_T_1 = mux(c1_self_rec_rawIn_isZeroExpIn, _c1_self_rec_rawIn_adjustedExp_T, c1_self_rec_rawIn_expIn) node _c1_self_rec_rawIn_adjustedExp_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c1_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c1_self_rec_rawIn_adjustedExp_T_2) node _c1_self_rec_rawIn_adjustedExp_T_4 = add(_c1_self_rec_rawIn_adjustedExp_T_1, _c1_self_rec_rawIn_adjustedExp_T_3) node c1_self_rec_rawIn_adjustedExp = tail(_c1_self_rec_rawIn_adjustedExp_T_4, 1) node c1_self_rec_rawIn_isZero = and(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_isZeroFractIn) node _c1_self_rec_rawIn_isSpecial_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 7) node c1_self_rec_rawIn_isSpecial = eq(_c1_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_self_rec_rawIn_out_isNaN_T = eq(c1_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_isNaN_T_1 = and(c1_self_rec_rawIn_isSpecial, _c1_self_rec_rawIn_out_isNaN_T) connect c1_self_rec_rawIn.isNaN, _c1_self_rec_rawIn_out_isNaN_T_1 node _c1_self_rec_rawIn_out_isInf_T = and(c1_self_rec_rawIn_isSpecial, c1_self_rec_rawIn_isZeroFractIn) connect c1_self_rec_rawIn.isInf, _c1_self_rec_rawIn_out_isInf_T connect c1_self_rec_rawIn.isZero, c1_self_rec_rawIn_isZero connect c1_self_rec_rawIn.sign, c1_self_rec_rawIn_sign node _c1_self_rec_rawIn_out_sExp_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 0) node _c1_self_rec_rawIn_out_sExp_T_1 = cvt(_c1_self_rec_rawIn_out_sExp_T) connect c1_self_rec_rawIn.sExp, _c1_self_rec_rawIn_out_sExp_T_1 node _c1_self_rec_rawIn_out_sig_T = eq(c1_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_self_rec_rawIn_out_sig_T) node _c1_self_rec_rawIn_out_sig_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_subnormFract, c1_self_rec_rawIn_fractIn) node _c1_self_rec_rawIn_out_sig_T_3 = cat(_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2) connect c1_self_rec_rawIn.sig, _c1_self_rec_rawIn_out_sig_T_3 node _c1_self_rec_T = bits(c1_self_rec_rawIn.sExp, 8, 6) node _c1_self_rec_T_1 = mux(c1_self_rec_rawIn.isZero, UInt<3>(0h0), _c1_self_rec_T) node _c1_self_rec_T_2 = mux(c1_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c1_self_rec_T_3 = or(_c1_self_rec_T_1, _c1_self_rec_T_2) node _c1_self_rec_T_4 = cat(c1_self_rec_rawIn.sign, _c1_self_rec_T_3) node _c1_self_rec_T_5 = bits(c1_self_rec_rawIn.sExp, 5, 0) node _c1_self_rec_T_6 = cat(_c1_self_rec_T_4, _c1_self_rec_T_5) node _c1_self_rec_T_7 = bits(c1_self_rec_rawIn.sig, 22, 0) node c1_self_rec = cat(_c1_self_rec_T_6, _c1_self_rec_T_7) inst c1_resizer of RecFNToRecFN_189 connect c1_resizer.io.in, c1_self_rec connect c1_resizer.io.roundingMode, UInt<3>(0h0) connect c1_resizer.io.detectTininess, UInt<1>(0h1) wire c1_result : { bits : UInt<32>} node c1_result_bits_rawIn_exp = bits(c1_resizer.io.out, 31, 23) node _c1_result_bits_rawIn_isZero_T = bits(c1_result_bits_rawIn_exp, 8, 6) node c1_result_bits_rawIn_isZero = eq(_c1_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_isSpecial_T = bits(c1_result_bits_rawIn_exp, 8, 7) node c1_result_bits_rawIn_isSpecial = eq(_c1_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_result_bits_rawIn_out_isNaN_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isNaN_T_1 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isNaN_T) connect c1_result_bits_rawIn.isNaN, _c1_result_bits_rawIn_out_isNaN_T_1 node _c1_result_bits_rawIn_out_isInf_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isInf_T_1 = eq(_c1_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_isInf_T_2 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isInf_T_1) connect c1_result_bits_rawIn.isInf, _c1_result_bits_rawIn_out_isInf_T_2 connect c1_result_bits_rawIn.isZero, c1_result_bits_rawIn_isZero node _c1_result_bits_rawIn_out_sign_T = bits(c1_resizer.io.out, 32, 32) connect c1_result_bits_rawIn.sign, _c1_result_bits_rawIn_out_sign_T node _c1_result_bits_rawIn_out_sExp_T = cvt(c1_result_bits_rawIn_exp) connect c1_result_bits_rawIn.sExp, _c1_result_bits_rawIn_out_sExp_T node _c1_result_bits_rawIn_out_sig_T = eq(c1_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_result_bits_rawIn_out_sig_T) node _c1_result_bits_rawIn_out_sig_T_2 = bits(c1_resizer.io.out, 22, 0) node _c1_result_bits_rawIn_out_sig_T_3 = cat(_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2) connect c1_result_bits_rawIn.sig, _c1_result_bits_rawIn_out_sig_T_3 node c1_result_bits_isSubnormal = lt(c1_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c1_result_bits_denormShiftDist_T = bits(c1_result_bits_rawIn.sExp, 4, 0) node _c1_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c1_result_bits_denormShiftDist_T) node c1_result_bits_denormShiftDist = tail(_c1_result_bits_denormShiftDist_T_1, 1) node _c1_result_bits_denormFract_T = shr(c1_result_bits_rawIn.sig, 1) node _c1_result_bits_denormFract_T_1 = dshr(_c1_result_bits_denormFract_T, c1_result_bits_denormShiftDist) node c1_result_bits_denormFract = bits(_c1_result_bits_denormFract_T_1, 22, 0) node _c1_result_bits_expOut_T = bits(c1_result_bits_rawIn.sExp, 7, 0) node _c1_result_bits_expOut_T_1 = sub(_c1_result_bits_expOut_T, UInt<8>(0h81)) node _c1_result_bits_expOut_T_2 = tail(_c1_result_bits_expOut_T_1, 1) node _c1_result_bits_expOut_T_3 = mux(c1_result_bits_isSubnormal, UInt<1>(0h0), _c1_result_bits_expOut_T_2) node _c1_result_bits_expOut_T_4 = or(c1_result_bits_rawIn.isNaN, c1_result_bits_rawIn.isInf) node _c1_result_bits_expOut_T_5 = mux(_c1_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c1_result_bits_expOut = or(_c1_result_bits_expOut_T_3, _c1_result_bits_expOut_T_5) node _c1_result_bits_fractOut_T = bits(c1_result_bits_rawIn.sig, 22, 0) node _c1_result_bits_fractOut_T_1 = mux(c1_result_bits_rawIn.isInf, UInt<1>(0h0), _c1_result_bits_fractOut_T) node c1_result_bits_fractOut = mux(c1_result_bits_isSubnormal, c1_result_bits_denormFract, _c1_result_bits_fractOut_T_1) node c1_result_bits_hi = cat(c1_result_bits_rawIn.sign, c1_result_bits_expOut) node _c1_result_bits_T = cat(c1_result_bits_hi, c1_result_bits_fractOut) connect c1_result.bits, _c1_result_bits_T connect c1, c1_result else : node io_out_c_self_rec_rawIn_sign_2 = bits(c2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_2 = bits(c2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_2 = bits(c2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_2 = eq(io_out_c_self_rec_rawIn_expIn_2, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_2 = eq(io_out_c_self_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_88 = bits(io_out_c_self_rec_rawIn_fractIn_2, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_89 = bits(io_out_c_self_rec_rawIn_fractIn_2, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_90 = bits(io_out_c_self_rec_rawIn_fractIn_2, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_91 = bits(io_out_c_self_rec_rawIn_fractIn_2, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_92 = bits(io_out_c_self_rec_rawIn_fractIn_2, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_93 = bits(io_out_c_self_rec_rawIn_fractIn_2, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_94 = bits(io_out_c_self_rec_rawIn_fractIn_2, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_95 = bits(io_out_c_self_rec_rawIn_fractIn_2, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_96 = bits(io_out_c_self_rec_rawIn_fractIn_2, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_97 = bits(io_out_c_self_rec_rawIn_fractIn_2, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_98 = bits(io_out_c_self_rec_rawIn_fractIn_2, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_99 = bits(io_out_c_self_rec_rawIn_fractIn_2, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_100 = bits(io_out_c_self_rec_rawIn_fractIn_2, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_101 = bits(io_out_c_self_rec_rawIn_fractIn_2, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_102 = bits(io_out_c_self_rec_rawIn_fractIn_2, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_103 = bits(io_out_c_self_rec_rawIn_fractIn_2, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_104 = bits(io_out_c_self_rec_rawIn_fractIn_2, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_105 = bits(io_out_c_self_rec_rawIn_fractIn_2, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_106 = bits(io_out_c_self_rec_rawIn_fractIn_2, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_107 = bits(io_out_c_self_rec_rawIn_fractIn_2, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_108 = bits(io_out_c_self_rec_rawIn_fractIn_2, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_109 = bits(io_out_c_self_rec_rawIn_fractIn_2, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_110 = bits(io_out_c_self_rec_rawIn_fractIn_2, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_111 = mux(_io_out_c_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_112 = mux(_io_out_c_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_111) node _io_out_c_self_rec_rawIn_normDist_T_113 = mux(_io_out_c_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_112) node _io_out_c_self_rec_rawIn_normDist_T_114 = mux(_io_out_c_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_113) node _io_out_c_self_rec_rawIn_normDist_T_115 = mux(_io_out_c_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_114) node _io_out_c_self_rec_rawIn_normDist_T_116 = mux(_io_out_c_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_115) node _io_out_c_self_rec_rawIn_normDist_T_117 = mux(_io_out_c_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_116) node _io_out_c_self_rec_rawIn_normDist_T_118 = mux(_io_out_c_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_117) node _io_out_c_self_rec_rawIn_normDist_T_119 = mux(_io_out_c_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_118) node _io_out_c_self_rec_rawIn_normDist_T_120 = mux(_io_out_c_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_119) node _io_out_c_self_rec_rawIn_normDist_T_121 = mux(_io_out_c_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_120) node _io_out_c_self_rec_rawIn_normDist_T_122 = mux(_io_out_c_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_121) node _io_out_c_self_rec_rawIn_normDist_T_123 = mux(_io_out_c_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_122) node _io_out_c_self_rec_rawIn_normDist_T_124 = mux(_io_out_c_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_123) node _io_out_c_self_rec_rawIn_normDist_T_125 = mux(_io_out_c_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_124) node _io_out_c_self_rec_rawIn_normDist_T_126 = mux(_io_out_c_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_125) node _io_out_c_self_rec_rawIn_normDist_T_127 = mux(_io_out_c_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_126) node _io_out_c_self_rec_rawIn_normDist_T_128 = mux(_io_out_c_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_127) node _io_out_c_self_rec_rawIn_normDist_T_129 = mux(_io_out_c_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_128) node _io_out_c_self_rec_rawIn_normDist_T_130 = mux(_io_out_c_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_129) node _io_out_c_self_rec_rawIn_normDist_T_131 = mux(_io_out_c_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_130) node io_out_c_self_rec_rawIn_normDist_2 = mux(_io_out_c_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_131) node _io_out_c_self_rec_rawIn_subnormFract_T_4 = dshl(io_out_c_self_rec_rawIn_fractIn_2, io_out_c_self_rec_rawIn_normDist_2) node _io_out_c_self_rec_rawIn_subnormFract_T_5 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_4, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_2 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_5, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_10 = xor(io_out_c_self_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_11 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, _io_out_c_self_rec_rawIn_adjustedExp_T_10, io_out_c_self_rec_rawIn_expIn_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_12 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_12) node _io_out_c_self_rec_rawIn_adjustedExp_T_14 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_11, _io_out_c_self_rec_rawIn_adjustedExp_T_13) node io_out_c_self_rec_rawIn_adjustedExp_2 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_14, 1) node io_out_c_self_rec_rawIn_isZero_2 = and(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) node _io_out_c_self_rec_rawIn_isSpecial_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_2 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_4 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_5 = and(io_out_c_self_rec_rawIn_isSpecial_2, _io_out_c_self_rec_rawIn_out_isNaN_T_4) connect io_out_c_self_rec_rawIn_2.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_5 node _io_out_c_self_rec_rawIn_out_isInf_T_2 = and(io_out_c_self_rec_rawIn_isSpecial_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) connect io_out_c_self_rec_rawIn_2.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_2 connect io_out_c_self_rec_rawIn_2.isZero, io_out_c_self_rec_rawIn_isZero_2 connect io_out_c_self_rec_rawIn_2.sign, io_out_c_self_rec_rawIn_sign_2 node _io_out_c_self_rec_rawIn_out_sExp_T_4 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_5 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_4) connect io_out_c_self_rec_rawIn_2.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_5 node _io_out_c_self_rec_rawIn_out_sig_T_8 = eq(io_out_c_self_rec_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_8) node _io_out_c_self_rec_rawIn_out_sig_T_10 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_subnormFract_2, io_out_c_self_rec_rawIn_fractIn_2) node _io_out_c_self_rec_rawIn_out_sig_T_11 = cat(_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10) connect io_out_c_self_rec_rawIn_2.sig, _io_out_c_self_rec_rawIn_out_sig_T_11 node _io_out_c_self_rec_T_16 = bits(io_out_c_self_rec_rawIn_2.sExp, 8, 6) node _io_out_c_self_rec_T_17 = mux(io_out_c_self_rec_rawIn_2.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_16) node _io_out_c_self_rec_T_18 = mux(io_out_c_self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_19 = or(_io_out_c_self_rec_T_17, _io_out_c_self_rec_T_18) node _io_out_c_self_rec_T_20 = cat(io_out_c_self_rec_rawIn_2.sign, _io_out_c_self_rec_T_19) node _io_out_c_self_rec_T_21 = bits(io_out_c_self_rec_rawIn_2.sExp, 5, 0) node _io_out_c_self_rec_T_22 = cat(_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21) node _io_out_c_self_rec_T_23 = bits(io_out_c_self_rec_rawIn_2.sig, 22, 0) node io_out_c_self_rec_2 = cat(_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23) wire io_out_c_shift_exp_1 : UInt<8> node _io_out_c_shift_exp_T_2 = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_3 = tail(_io_out_c_shift_exp_T_2, 1) connect io_out_c_shift_exp_1, _io_out_c_shift_exp_T_3 node io_out_c_shift_fn_hi_1 = cat(UInt<1>(0h0), io_out_c_shift_exp_1) node io_out_c_shift_fn_1 = cat(io_out_c_shift_fn_hi_1, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign_1 = bits(io_out_c_shift_fn_1, 31, 31) node io_out_c_shift_rec_rawIn_expIn_1 = bits(io_out_c_shift_fn_1, 30, 23) node io_out_c_shift_rec_rawIn_fractIn_1 = bits(io_out_c_shift_fn_1, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_shift_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_shift_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T_44 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_45 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_46 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_47 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_48 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_49 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_50 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_51 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_52 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_53 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_54 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_55 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_56 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_57 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_58 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_59 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_60 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_61 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_62 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_63 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_64 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_65 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_66 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_67 = mux(_io_out_c_shift_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_68 = mux(_io_out_c_shift_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_67) node _io_out_c_shift_rec_rawIn_normDist_T_69 = mux(_io_out_c_shift_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_68) node _io_out_c_shift_rec_rawIn_normDist_T_70 = mux(_io_out_c_shift_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_69) node _io_out_c_shift_rec_rawIn_normDist_T_71 = mux(_io_out_c_shift_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_70) node _io_out_c_shift_rec_rawIn_normDist_T_72 = mux(_io_out_c_shift_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_71) node _io_out_c_shift_rec_rawIn_normDist_T_73 = mux(_io_out_c_shift_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_72) node _io_out_c_shift_rec_rawIn_normDist_T_74 = mux(_io_out_c_shift_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_73) node _io_out_c_shift_rec_rawIn_normDist_T_75 = mux(_io_out_c_shift_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_74) node _io_out_c_shift_rec_rawIn_normDist_T_76 = mux(_io_out_c_shift_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_75) node _io_out_c_shift_rec_rawIn_normDist_T_77 = mux(_io_out_c_shift_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_76) node _io_out_c_shift_rec_rawIn_normDist_T_78 = mux(_io_out_c_shift_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_77) node _io_out_c_shift_rec_rawIn_normDist_T_79 = mux(_io_out_c_shift_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_78) node _io_out_c_shift_rec_rawIn_normDist_T_80 = mux(_io_out_c_shift_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_79) node _io_out_c_shift_rec_rawIn_normDist_T_81 = mux(_io_out_c_shift_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_80) node _io_out_c_shift_rec_rawIn_normDist_T_82 = mux(_io_out_c_shift_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_81) node _io_out_c_shift_rec_rawIn_normDist_T_83 = mux(_io_out_c_shift_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_82) node _io_out_c_shift_rec_rawIn_normDist_T_84 = mux(_io_out_c_shift_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_83) node _io_out_c_shift_rec_rawIn_normDist_T_85 = mux(_io_out_c_shift_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_84) node _io_out_c_shift_rec_rawIn_normDist_T_86 = mux(_io_out_c_shift_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_85) node _io_out_c_shift_rec_rawIn_normDist_T_87 = mux(_io_out_c_shift_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_86) node io_out_c_shift_rec_rawIn_normDist_1 = mux(_io_out_c_shift_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_87) node _io_out_c_shift_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_shift_rec_rawIn_fractIn_1, io_out_c_shift_rec_rawIn_normDist_1) node _io_out_c_shift_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract_1 = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_shift_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_5, io_out_c_shift_rec_rawIn_expIn_1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_7) node _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_6, _io_out_c_shift_rec_rawIn_adjustedExp_T_8) node io_out_c_shift_rec_rawIn_adjustedExp_1 = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_shift_rec_rawIn_isZero_1 = and(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) node _io_out_c_shift_rec_rawIn_isSpecial_T_1 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial_1 = eq(_io_out_c_shift_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_shift_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = and(io_out_c_shift_rec_rawIn_isSpecial_1, _io_out_c_shift_rec_rawIn_out_isNaN_T_2) connect io_out_c_shift_rec_rawIn_1.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_3 node _io_out_c_shift_rec_rawIn_out_isInf_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) connect io_out_c_shift_rec_rawIn_1.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T_1 connect io_out_c_shift_rec_rawIn_1.isZero, io_out_c_shift_rec_rawIn_isZero_1 connect io_out_c_shift_rec_rawIn_1.sign, io_out_c_shift_rec_rawIn_sign_1 node _io_out_c_shift_rec_rawIn_out_sExp_T_2 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T_2) connect io_out_c_shift_rec_rawIn_1.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_3 node _io_out_c_shift_rec_rawIn_out_sig_T_4 = eq(io_out_c_shift_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T_4) node _io_out_c_shift_rec_rawIn_out_sig_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_subnormFract_1, io_out_c_shift_rec_rawIn_fractIn_1) node _io_out_c_shift_rec_rawIn_out_sig_T_7 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6) connect io_out_c_shift_rec_rawIn_1.sig, _io_out_c_shift_rec_rawIn_out_sig_T_7 node _io_out_c_shift_rec_T_8 = bits(io_out_c_shift_rec_rawIn_1.sExp, 8, 6) node _io_out_c_shift_rec_T_9 = mux(io_out_c_shift_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T_8) node _io_out_c_shift_rec_T_10 = mux(io_out_c_shift_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_11 = or(_io_out_c_shift_rec_T_9, _io_out_c_shift_rec_T_10) node _io_out_c_shift_rec_T_12 = cat(io_out_c_shift_rec_rawIn_1.sign, _io_out_c_shift_rec_T_11) node _io_out_c_shift_rec_T_13 = bits(io_out_c_shift_rec_rawIn_1.sExp, 5, 0) node _io_out_c_shift_rec_T_14 = cat(_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13) node _io_out_c_shift_rec_T_15 = bits(io_out_c_shift_rec_rawIn_1.sig, 22, 0) node io_out_c_shift_rec_1 = cat(_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15) node _io_out_c_T_4 = neq(io_out_c_shift_exp_1, UInt<1>(0h0)) node _io_out_c_T_5 = asUInt(reset) node _io_out_c_T_6 = eq(_io_out_c_T_5, UInt<1>(0h0)) when _io_out_c_T_6 : node _io_out_c_T_7 = eq(_io_out_c_T_4, UInt<1>(0h0)) when _io_out_c_T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf_1 assert(clock, _io_out_c_T_4, UInt<1>(0h1), "") : io_out_c_assert_1 inst io_out_c_muladder_1 of MulRecFN_39 connect io_out_c_muladder_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder_1.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder_1.io.a, io_out_c_self_rec_2 connect io_out_c_muladder_1.io.b, io_out_c_shift_rec_1 wire io_out_c_result_2 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_2 = bits(io_out_c_muladder_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 6) node io_out_c_result_bits_rawIn_isZero_2 = eq(_io_out_c_result_bits_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_2 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_4 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isNaN_T_4) connect io_out_c_result_bits_rawIn_2.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_5 node _io_out_c_result_bits_rawIn_out_isInf_T_6 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_7 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_8 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isInf_T_7) connect io_out_c_result_bits_rawIn_2.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_8 connect io_out_c_result_bits_rawIn_2.isZero, io_out_c_result_bits_rawIn_isZero_2 node _io_out_c_result_bits_rawIn_out_sign_T_2 = bits(io_out_c_muladder_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_2.sign, _io_out_c_result_bits_rawIn_out_sign_T_2 node _io_out_c_result_bits_rawIn_out_sExp_T_2 = cvt(io_out_c_result_bits_rawIn_exp_2) connect io_out_c_result_bits_rawIn_2.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_2 node _io_out_c_result_bits_rawIn_out_sig_T_8 = eq(io_out_c_result_bits_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_8) node _io_out_c_result_bits_rawIn_out_sig_T_10 = bits(io_out_c_muladder_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_11 = cat(_io_out_c_result_bits_rawIn_out_sig_T_9, _io_out_c_result_bits_rawIn_out_sig_T_10) connect io_out_c_result_bits_rawIn_2.sig, _io_out_c_result_bits_rawIn_out_sig_T_11 node io_out_c_result_bits_isSubnormal_2 = lt(io_out_c_result_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_4 = bits(io_out_c_result_bits_rawIn_2.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_4) node io_out_c_result_bits_denormShiftDist_2 = tail(_io_out_c_result_bits_denormShiftDist_T_5, 1) node _io_out_c_result_bits_denormFract_T_4 = shr(io_out_c_result_bits_rawIn_2.sig, 1) node _io_out_c_result_bits_denormFract_T_5 = dshr(_io_out_c_result_bits_denormFract_T_4, io_out_c_result_bits_denormShiftDist_2) node io_out_c_result_bits_denormFract_2 = bits(_io_out_c_result_bits_denormFract_T_5, 22, 0) node _io_out_c_result_bits_expOut_T_12 = bits(io_out_c_result_bits_rawIn_2.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_13 = sub(_io_out_c_result_bits_expOut_T_12, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_14 = tail(_io_out_c_result_bits_expOut_T_13, 1) node _io_out_c_result_bits_expOut_T_15 = mux(io_out_c_result_bits_isSubnormal_2, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_14) node _io_out_c_result_bits_expOut_T_16 = or(io_out_c_result_bits_rawIn_2.isNaN, io_out_c_result_bits_rawIn_2.isInf) node _io_out_c_result_bits_expOut_T_17 = mux(_io_out_c_result_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_2 = or(_io_out_c_result_bits_expOut_T_15, _io_out_c_result_bits_expOut_T_17) node _io_out_c_result_bits_fractOut_T_4 = bits(io_out_c_result_bits_rawIn_2.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_5 = mux(io_out_c_result_bits_rawIn_2.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_4) node io_out_c_result_bits_fractOut_2 = mux(io_out_c_result_bits_isSubnormal_2, io_out_c_result_bits_denormFract_2, _io_out_c_result_bits_fractOut_T_5) node io_out_c_result_bits_hi_2 = cat(io_out_c_result_bits_rawIn_2.sign, io_out_c_result_bits_expOut_2) node _io_out_c_result_bits_T_2 = cat(io_out_c_result_bits_hi_2, io_out_c_result_bits_fractOut_2) connect io_out_c_result_2.bits, _io_out_c_result_bits_T_2 node io_out_c_self_rec_rawIn_sign_3 = bits(io_out_c_result_2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_3 = bits(io_out_c_result_2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_3 = bits(io_out_c_result_2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_3 = eq(io_out_c_self_rec_rawIn_expIn_3, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_3 = eq(io_out_c_self_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_132 = bits(io_out_c_self_rec_rawIn_fractIn_3, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_133 = bits(io_out_c_self_rec_rawIn_fractIn_3, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_134 = bits(io_out_c_self_rec_rawIn_fractIn_3, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_135 = bits(io_out_c_self_rec_rawIn_fractIn_3, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_136 = bits(io_out_c_self_rec_rawIn_fractIn_3, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_137 = bits(io_out_c_self_rec_rawIn_fractIn_3, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_138 = bits(io_out_c_self_rec_rawIn_fractIn_3, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_139 = bits(io_out_c_self_rec_rawIn_fractIn_3, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_140 = bits(io_out_c_self_rec_rawIn_fractIn_3, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_141 = bits(io_out_c_self_rec_rawIn_fractIn_3, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_142 = bits(io_out_c_self_rec_rawIn_fractIn_3, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_143 = bits(io_out_c_self_rec_rawIn_fractIn_3, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_144 = bits(io_out_c_self_rec_rawIn_fractIn_3, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_145 = bits(io_out_c_self_rec_rawIn_fractIn_3, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_146 = bits(io_out_c_self_rec_rawIn_fractIn_3, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_147 = bits(io_out_c_self_rec_rawIn_fractIn_3, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_148 = bits(io_out_c_self_rec_rawIn_fractIn_3, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_149 = bits(io_out_c_self_rec_rawIn_fractIn_3, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_150 = bits(io_out_c_self_rec_rawIn_fractIn_3, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_151 = bits(io_out_c_self_rec_rawIn_fractIn_3, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_152 = bits(io_out_c_self_rec_rawIn_fractIn_3, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_153 = bits(io_out_c_self_rec_rawIn_fractIn_3, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_154 = bits(io_out_c_self_rec_rawIn_fractIn_3, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_155 = mux(_io_out_c_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_156 = mux(_io_out_c_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_155) node _io_out_c_self_rec_rawIn_normDist_T_157 = mux(_io_out_c_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_156) node _io_out_c_self_rec_rawIn_normDist_T_158 = mux(_io_out_c_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_157) node _io_out_c_self_rec_rawIn_normDist_T_159 = mux(_io_out_c_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_158) node _io_out_c_self_rec_rawIn_normDist_T_160 = mux(_io_out_c_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_159) node _io_out_c_self_rec_rawIn_normDist_T_161 = mux(_io_out_c_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_160) node _io_out_c_self_rec_rawIn_normDist_T_162 = mux(_io_out_c_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_161) node _io_out_c_self_rec_rawIn_normDist_T_163 = mux(_io_out_c_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_162) node _io_out_c_self_rec_rawIn_normDist_T_164 = mux(_io_out_c_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_163) node _io_out_c_self_rec_rawIn_normDist_T_165 = mux(_io_out_c_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_164) node _io_out_c_self_rec_rawIn_normDist_T_166 = mux(_io_out_c_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_165) node _io_out_c_self_rec_rawIn_normDist_T_167 = mux(_io_out_c_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_166) node _io_out_c_self_rec_rawIn_normDist_T_168 = mux(_io_out_c_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_167) node _io_out_c_self_rec_rawIn_normDist_T_169 = mux(_io_out_c_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_168) node _io_out_c_self_rec_rawIn_normDist_T_170 = mux(_io_out_c_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_169) node _io_out_c_self_rec_rawIn_normDist_T_171 = mux(_io_out_c_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_170) node _io_out_c_self_rec_rawIn_normDist_T_172 = mux(_io_out_c_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_171) node _io_out_c_self_rec_rawIn_normDist_T_173 = mux(_io_out_c_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_172) node _io_out_c_self_rec_rawIn_normDist_T_174 = mux(_io_out_c_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_173) node _io_out_c_self_rec_rawIn_normDist_T_175 = mux(_io_out_c_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_174) node io_out_c_self_rec_rawIn_normDist_3 = mux(_io_out_c_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_175) node _io_out_c_self_rec_rawIn_subnormFract_T_6 = dshl(io_out_c_self_rec_rawIn_fractIn_3, io_out_c_self_rec_rawIn_normDist_3) node _io_out_c_self_rec_rawIn_subnormFract_T_7 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_6, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_3 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_7, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_15 = xor(io_out_c_self_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_16 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, _io_out_c_self_rec_rawIn_adjustedExp_T_15, io_out_c_self_rec_rawIn_expIn_3) node _io_out_c_self_rec_rawIn_adjustedExp_T_17 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_17) node _io_out_c_self_rec_rawIn_adjustedExp_T_19 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_16, _io_out_c_self_rec_rawIn_adjustedExp_T_18) node io_out_c_self_rec_rawIn_adjustedExp_3 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_19, 1) node io_out_c_self_rec_rawIn_isZero_3 = and(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) node _io_out_c_self_rec_rawIn_isSpecial_T_3 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_3 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_6 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_7 = and(io_out_c_self_rec_rawIn_isSpecial_3, _io_out_c_self_rec_rawIn_out_isNaN_T_6) connect io_out_c_self_rec_rawIn_3.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_7 node _io_out_c_self_rec_rawIn_out_isInf_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) connect io_out_c_self_rec_rawIn_3.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_3 connect io_out_c_self_rec_rawIn_3.isZero, io_out_c_self_rec_rawIn_isZero_3 connect io_out_c_self_rec_rawIn_3.sign, io_out_c_self_rec_rawIn_sign_3 node _io_out_c_self_rec_rawIn_out_sExp_T_6 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_7 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_6) connect io_out_c_self_rec_rawIn_3.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_7 node _io_out_c_self_rec_rawIn_out_sig_T_12 = eq(io_out_c_self_rec_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_12) node _io_out_c_self_rec_rawIn_out_sig_T_14 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_subnormFract_3, io_out_c_self_rec_rawIn_fractIn_3) node _io_out_c_self_rec_rawIn_out_sig_T_15 = cat(_io_out_c_self_rec_rawIn_out_sig_T_13, _io_out_c_self_rec_rawIn_out_sig_T_14) connect io_out_c_self_rec_rawIn_3.sig, _io_out_c_self_rec_rawIn_out_sig_T_15 node _io_out_c_self_rec_T_24 = bits(io_out_c_self_rec_rawIn_3.sExp, 8, 6) node _io_out_c_self_rec_T_25 = mux(io_out_c_self_rec_rawIn_3.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_24) node _io_out_c_self_rec_T_26 = mux(io_out_c_self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_27 = or(_io_out_c_self_rec_T_25, _io_out_c_self_rec_T_26) node _io_out_c_self_rec_T_28 = cat(io_out_c_self_rec_rawIn_3.sign, _io_out_c_self_rec_T_27) node _io_out_c_self_rec_T_29 = bits(io_out_c_self_rec_rawIn_3.sExp, 5, 0) node _io_out_c_self_rec_T_30 = cat(_io_out_c_self_rec_T_28, _io_out_c_self_rec_T_29) node _io_out_c_self_rec_T_31 = bits(io_out_c_self_rec_rawIn_3.sig, 22, 0) node io_out_c_self_rec_3 = cat(_io_out_c_self_rec_T_30, _io_out_c_self_rec_T_31) inst io_out_c_resizer_1 of RecFNToRecFN_190 connect io_out_c_resizer_1.io.in, io_out_c_self_rec_3 connect io_out_c_resizer_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer_1.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_3 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_3 = bits(io_out_c_resizer_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 6) node io_out_c_result_bits_rawIn_isZero_3 = eq(_io_out_c_result_bits_rawIn_isZero_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_3 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_6 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_7 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isNaN_T_6) connect io_out_c_result_bits_rawIn_3.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_7 node _io_out_c_result_bits_rawIn_out_isInf_T_9 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_10 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_9, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_11 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isInf_T_10) connect io_out_c_result_bits_rawIn_3.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_11 connect io_out_c_result_bits_rawIn_3.isZero, io_out_c_result_bits_rawIn_isZero_3 node _io_out_c_result_bits_rawIn_out_sign_T_3 = bits(io_out_c_resizer_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_3.sign, _io_out_c_result_bits_rawIn_out_sign_T_3 node _io_out_c_result_bits_rawIn_out_sExp_T_3 = cvt(io_out_c_result_bits_rawIn_exp_3) connect io_out_c_result_bits_rawIn_3.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_3 node _io_out_c_result_bits_rawIn_out_sig_T_12 = eq(io_out_c_result_bits_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_12) node _io_out_c_result_bits_rawIn_out_sig_T_14 = bits(io_out_c_resizer_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_15 = cat(_io_out_c_result_bits_rawIn_out_sig_T_13, _io_out_c_result_bits_rawIn_out_sig_T_14) connect io_out_c_result_bits_rawIn_3.sig, _io_out_c_result_bits_rawIn_out_sig_T_15 node io_out_c_result_bits_isSubnormal_3 = lt(io_out_c_result_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_6 = bits(io_out_c_result_bits_rawIn_3.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_6) node io_out_c_result_bits_denormShiftDist_3 = tail(_io_out_c_result_bits_denormShiftDist_T_7, 1) node _io_out_c_result_bits_denormFract_T_6 = shr(io_out_c_result_bits_rawIn_3.sig, 1) node _io_out_c_result_bits_denormFract_T_7 = dshr(_io_out_c_result_bits_denormFract_T_6, io_out_c_result_bits_denormShiftDist_3) node io_out_c_result_bits_denormFract_3 = bits(_io_out_c_result_bits_denormFract_T_7, 22, 0) node _io_out_c_result_bits_expOut_T_18 = bits(io_out_c_result_bits_rawIn_3.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_19 = sub(_io_out_c_result_bits_expOut_T_18, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_20 = tail(_io_out_c_result_bits_expOut_T_19, 1) node _io_out_c_result_bits_expOut_T_21 = mux(io_out_c_result_bits_isSubnormal_3, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_20) node _io_out_c_result_bits_expOut_T_22 = or(io_out_c_result_bits_rawIn_3.isNaN, io_out_c_result_bits_rawIn_3.isInf) node _io_out_c_result_bits_expOut_T_23 = mux(_io_out_c_result_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_3 = or(_io_out_c_result_bits_expOut_T_21, _io_out_c_result_bits_expOut_T_23) node _io_out_c_result_bits_fractOut_T_6 = bits(io_out_c_result_bits_rawIn_3.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_7 = mux(io_out_c_result_bits_rawIn_3.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_6) node io_out_c_result_bits_fractOut_3 = mux(io_out_c_result_bits_isSubnormal_3, io_out_c_result_bits_denormFract_3, _io_out_c_result_bits_fractOut_T_7) node io_out_c_result_bits_hi_3 = cat(io_out_c_result_bits_rawIn_3.sign, io_out_c_result_bits_expOut_3) node _io_out_c_result_bits_T_3 = cat(io_out_c_result_bits_hi_3, io_out_c_result_bits_fractOut_3) connect io_out_c_result_3.bits, _io_out_c_result_bits_T_3 connect io.out_c, io_out_c_result_3 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_2 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_3 : UInt<32> connect _mac_unit_io_in_b_WIRE_3, io.in_b.bits node _mac_unit_io_in_b_T_1 = bits(_mac_unit_io_in_b_WIRE_3, 31, 0) connect _mac_unit_io_in_b_WIRE_2.bits, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_2.bits connect mac_unit.io.in_c.bits, c1.bits connect c1, mac_unit.io.out_d node c2_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c2_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c2_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c2_self_rec_rawIn_isZeroExpIn = eq(c2_self_rec_rawIn_expIn, UInt<1>(0h0)) node c2_self_rec_rawIn_isZeroFractIn = eq(c2_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_normDist_T = bits(c2_self_rec_rawIn_fractIn, 0, 0) node _c2_self_rec_rawIn_normDist_T_1 = bits(c2_self_rec_rawIn_fractIn, 1, 1) node _c2_self_rec_rawIn_normDist_T_2 = bits(c2_self_rec_rawIn_fractIn, 2, 2) node _c2_self_rec_rawIn_normDist_T_3 = bits(c2_self_rec_rawIn_fractIn, 3, 3) node _c2_self_rec_rawIn_normDist_T_4 = bits(c2_self_rec_rawIn_fractIn, 4, 4) node _c2_self_rec_rawIn_normDist_T_5 = bits(c2_self_rec_rawIn_fractIn, 5, 5) node _c2_self_rec_rawIn_normDist_T_6 = bits(c2_self_rec_rawIn_fractIn, 6, 6) node _c2_self_rec_rawIn_normDist_T_7 = bits(c2_self_rec_rawIn_fractIn, 7, 7) node _c2_self_rec_rawIn_normDist_T_8 = bits(c2_self_rec_rawIn_fractIn, 8, 8) node _c2_self_rec_rawIn_normDist_T_9 = bits(c2_self_rec_rawIn_fractIn, 9, 9) node _c2_self_rec_rawIn_normDist_T_10 = bits(c2_self_rec_rawIn_fractIn, 10, 10) node _c2_self_rec_rawIn_normDist_T_11 = bits(c2_self_rec_rawIn_fractIn, 11, 11) node _c2_self_rec_rawIn_normDist_T_12 = bits(c2_self_rec_rawIn_fractIn, 12, 12) node _c2_self_rec_rawIn_normDist_T_13 = bits(c2_self_rec_rawIn_fractIn, 13, 13) node _c2_self_rec_rawIn_normDist_T_14 = bits(c2_self_rec_rawIn_fractIn, 14, 14) node _c2_self_rec_rawIn_normDist_T_15 = bits(c2_self_rec_rawIn_fractIn, 15, 15) node _c2_self_rec_rawIn_normDist_T_16 = bits(c2_self_rec_rawIn_fractIn, 16, 16) node _c2_self_rec_rawIn_normDist_T_17 = bits(c2_self_rec_rawIn_fractIn, 17, 17) node _c2_self_rec_rawIn_normDist_T_18 = bits(c2_self_rec_rawIn_fractIn, 18, 18) node _c2_self_rec_rawIn_normDist_T_19 = bits(c2_self_rec_rawIn_fractIn, 19, 19) node _c2_self_rec_rawIn_normDist_T_20 = bits(c2_self_rec_rawIn_fractIn, 20, 20) node _c2_self_rec_rawIn_normDist_T_21 = bits(c2_self_rec_rawIn_fractIn, 21, 21) node _c2_self_rec_rawIn_normDist_T_22 = bits(c2_self_rec_rawIn_fractIn, 22, 22) node _c2_self_rec_rawIn_normDist_T_23 = mux(_c2_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c2_self_rec_rawIn_normDist_T_24 = mux(_c2_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c2_self_rec_rawIn_normDist_T_23) node _c2_self_rec_rawIn_normDist_T_25 = mux(_c2_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c2_self_rec_rawIn_normDist_T_24) node _c2_self_rec_rawIn_normDist_T_26 = mux(_c2_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c2_self_rec_rawIn_normDist_T_25) node _c2_self_rec_rawIn_normDist_T_27 = mux(_c2_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c2_self_rec_rawIn_normDist_T_26) node _c2_self_rec_rawIn_normDist_T_28 = mux(_c2_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c2_self_rec_rawIn_normDist_T_27) node _c2_self_rec_rawIn_normDist_T_29 = mux(_c2_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c2_self_rec_rawIn_normDist_T_28) node _c2_self_rec_rawIn_normDist_T_30 = mux(_c2_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c2_self_rec_rawIn_normDist_T_29) node _c2_self_rec_rawIn_normDist_T_31 = mux(_c2_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c2_self_rec_rawIn_normDist_T_30) node _c2_self_rec_rawIn_normDist_T_32 = mux(_c2_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c2_self_rec_rawIn_normDist_T_31) node _c2_self_rec_rawIn_normDist_T_33 = mux(_c2_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c2_self_rec_rawIn_normDist_T_32) node _c2_self_rec_rawIn_normDist_T_34 = mux(_c2_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c2_self_rec_rawIn_normDist_T_33) node _c2_self_rec_rawIn_normDist_T_35 = mux(_c2_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c2_self_rec_rawIn_normDist_T_34) node _c2_self_rec_rawIn_normDist_T_36 = mux(_c2_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c2_self_rec_rawIn_normDist_T_35) node _c2_self_rec_rawIn_normDist_T_37 = mux(_c2_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c2_self_rec_rawIn_normDist_T_36) node _c2_self_rec_rawIn_normDist_T_38 = mux(_c2_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c2_self_rec_rawIn_normDist_T_37) node _c2_self_rec_rawIn_normDist_T_39 = mux(_c2_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c2_self_rec_rawIn_normDist_T_38) node _c2_self_rec_rawIn_normDist_T_40 = mux(_c2_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c2_self_rec_rawIn_normDist_T_39) node _c2_self_rec_rawIn_normDist_T_41 = mux(_c2_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c2_self_rec_rawIn_normDist_T_40) node _c2_self_rec_rawIn_normDist_T_42 = mux(_c2_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c2_self_rec_rawIn_normDist_T_41) node _c2_self_rec_rawIn_normDist_T_43 = mux(_c2_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c2_self_rec_rawIn_normDist_T_42) node c2_self_rec_rawIn_normDist = mux(_c2_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c2_self_rec_rawIn_normDist_T_43) node _c2_self_rec_rawIn_subnormFract_T = dshl(c2_self_rec_rawIn_fractIn, c2_self_rec_rawIn_normDist) node _c2_self_rec_rawIn_subnormFract_T_1 = bits(_c2_self_rec_rawIn_subnormFract_T, 21, 0) node c2_self_rec_rawIn_subnormFract = shl(_c2_self_rec_rawIn_subnormFract_T_1, 1) node _c2_self_rec_rawIn_adjustedExp_T = xor(c2_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c2_self_rec_rawIn_adjustedExp_T_1 = mux(c2_self_rec_rawIn_isZeroExpIn, _c2_self_rec_rawIn_adjustedExp_T, c2_self_rec_rawIn_expIn) node _c2_self_rec_rawIn_adjustedExp_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c2_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c2_self_rec_rawIn_adjustedExp_T_2) node _c2_self_rec_rawIn_adjustedExp_T_4 = add(_c2_self_rec_rawIn_adjustedExp_T_1, _c2_self_rec_rawIn_adjustedExp_T_3) node c2_self_rec_rawIn_adjustedExp = tail(_c2_self_rec_rawIn_adjustedExp_T_4, 1) node c2_self_rec_rawIn_isZero = and(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_isZeroFractIn) node _c2_self_rec_rawIn_isSpecial_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 7) node c2_self_rec_rawIn_isSpecial = eq(_c2_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_self_rec_rawIn_out_isNaN_T = eq(c2_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_isNaN_T_1 = and(c2_self_rec_rawIn_isSpecial, _c2_self_rec_rawIn_out_isNaN_T) connect c2_self_rec_rawIn.isNaN, _c2_self_rec_rawIn_out_isNaN_T_1 node _c2_self_rec_rawIn_out_isInf_T = and(c2_self_rec_rawIn_isSpecial, c2_self_rec_rawIn_isZeroFractIn) connect c2_self_rec_rawIn.isInf, _c2_self_rec_rawIn_out_isInf_T connect c2_self_rec_rawIn.isZero, c2_self_rec_rawIn_isZero connect c2_self_rec_rawIn.sign, c2_self_rec_rawIn_sign node _c2_self_rec_rawIn_out_sExp_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 0) node _c2_self_rec_rawIn_out_sExp_T_1 = cvt(_c2_self_rec_rawIn_out_sExp_T) connect c2_self_rec_rawIn.sExp, _c2_self_rec_rawIn_out_sExp_T_1 node _c2_self_rec_rawIn_out_sig_T = eq(c2_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_self_rec_rawIn_out_sig_T) node _c2_self_rec_rawIn_out_sig_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_subnormFract, c2_self_rec_rawIn_fractIn) node _c2_self_rec_rawIn_out_sig_T_3 = cat(_c2_self_rec_rawIn_out_sig_T_1, _c2_self_rec_rawIn_out_sig_T_2) connect c2_self_rec_rawIn.sig, _c2_self_rec_rawIn_out_sig_T_3 node _c2_self_rec_T = bits(c2_self_rec_rawIn.sExp, 8, 6) node _c2_self_rec_T_1 = mux(c2_self_rec_rawIn.isZero, UInt<3>(0h0), _c2_self_rec_T) node _c2_self_rec_T_2 = mux(c2_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c2_self_rec_T_3 = or(_c2_self_rec_T_1, _c2_self_rec_T_2) node _c2_self_rec_T_4 = cat(c2_self_rec_rawIn.sign, _c2_self_rec_T_3) node _c2_self_rec_T_5 = bits(c2_self_rec_rawIn.sExp, 5, 0) node _c2_self_rec_T_6 = cat(_c2_self_rec_T_4, _c2_self_rec_T_5) node _c2_self_rec_T_7 = bits(c2_self_rec_rawIn.sig, 22, 0) node c2_self_rec = cat(_c2_self_rec_T_6, _c2_self_rec_T_7) inst c2_resizer of RecFNToRecFN_191 connect c2_resizer.io.in, c2_self_rec connect c2_resizer.io.roundingMode, UInt<3>(0h0) connect c2_resizer.io.detectTininess, UInt<1>(0h1) wire c2_result : { bits : UInt<32>} node c2_result_bits_rawIn_exp = bits(c2_resizer.io.out, 31, 23) node _c2_result_bits_rawIn_isZero_T = bits(c2_result_bits_rawIn_exp, 8, 6) node c2_result_bits_rawIn_isZero = eq(_c2_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_isSpecial_T = bits(c2_result_bits_rawIn_exp, 8, 7) node c2_result_bits_rawIn_isSpecial = eq(_c2_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_result_bits_rawIn_out_isNaN_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isNaN_T_1 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isNaN_T) connect c2_result_bits_rawIn.isNaN, _c2_result_bits_rawIn_out_isNaN_T_1 node _c2_result_bits_rawIn_out_isInf_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isInf_T_1 = eq(_c2_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_isInf_T_2 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isInf_T_1) connect c2_result_bits_rawIn.isInf, _c2_result_bits_rawIn_out_isInf_T_2 connect c2_result_bits_rawIn.isZero, c2_result_bits_rawIn_isZero node _c2_result_bits_rawIn_out_sign_T = bits(c2_resizer.io.out, 32, 32) connect c2_result_bits_rawIn.sign, _c2_result_bits_rawIn_out_sign_T node _c2_result_bits_rawIn_out_sExp_T = cvt(c2_result_bits_rawIn_exp) connect c2_result_bits_rawIn.sExp, _c2_result_bits_rawIn_out_sExp_T node _c2_result_bits_rawIn_out_sig_T = eq(c2_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_result_bits_rawIn_out_sig_T) node _c2_result_bits_rawIn_out_sig_T_2 = bits(c2_resizer.io.out, 22, 0) node _c2_result_bits_rawIn_out_sig_T_3 = cat(_c2_result_bits_rawIn_out_sig_T_1, _c2_result_bits_rawIn_out_sig_T_2) connect c2_result_bits_rawIn.sig, _c2_result_bits_rawIn_out_sig_T_3 node c2_result_bits_isSubnormal = lt(c2_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c2_result_bits_denormShiftDist_T = bits(c2_result_bits_rawIn.sExp, 4, 0) node _c2_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c2_result_bits_denormShiftDist_T) node c2_result_bits_denormShiftDist = tail(_c2_result_bits_denormShiftDist_T_1, 1) node _c2_result_bits_denormFract_T = shr(c2_result_bits_rawIn.sig, 1) node _c2_result_bits_denormFract_T_1 = dshr(_c2_result_bits_denormFract_T, c2_result_bits_denormShiftDist) node c2_result_bits_denormFract = bits(_c2_result_bits_denormFract_T_1, 22, 0) node _c2_result_bits_expOut_T = bits(c2_result_bits_rawIn.sExp, 7, 0) node _c2_result_bits_expOut_T_1 = sub(_c2_result_bits_expOut_T, UInt<8>(0h81)) node _c2_result_bits_expOut_T_2 = tail(_c2_result_bits_expOut_T_1, 1) node _c2_result_bits_expOut_T_3 = mux(c2_result_bits_isSubnormal, UInt<1>(0h0), _c2_result_bits_expOut_T_2) node _c2_result_bits_expOut_T_4 = or(c2_result_bits_rawIn.isNaN, c2_result_bits_rawIn.isInf) node _c2_result_bits_expOut_T_5 = mux(_c2_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c2_result_bits_expOut = or(_c2_result_bits_expOut_T_3, _c2_result_bits_expOut_T_5) node _c2_result_bits_fractOut_T = bits(c2_result_bits_rawIn.sig, 22, 0) node _c2_result_bits_fractOut_T_1 = mux(c2_result_bits_rawIn.isInf, UInt<1>(0h0), _c2_result_bits_fractOut_T) node c2_result_bits_fractOut = mux(c2_result_bits_isSubnormal, c2_result_bits_denormFract, _c2_result_bits_fractOut_T_1) node c2_result_bits_hi = cat(c2_result_bits_rawIn.sign, c2_result_bits_expOut) node _c2_result_bits_T = cat(c2_result_bits_hi, c2_result_bits_fractOut) connect c2_result.bits, _c2_result_bits_T connect c2, c2_result else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_4 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_5 : UInt<32> connect _mac_unit_io_in_b_WIRE_5, c2.bits node _mac_unit_io_in_b_T_2 = bits(_mac_unit_io_in_b_WIRE_5, 31, 0) connect _mac_unit_io_in_b_WIRE_4.bits, _mac_unit_io_in_b_T_2 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_4.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_6 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_7 : UInt<32> connect _mac_unit_io_in_b_WIRE_7, c1.bits node _mac_unit_io_in_b_T_3 = bits(_mac_unit_io_in_b_WIRE_7, 31, 0) connect _mac_unit_io_in_b_WIRE_6.bits, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_6.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c.bits invalidate io.out_b.bits wire _mac_unit_io_in_b_WIRE_8 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_9 : UInt<32> connect _mac_unit_io_in_b_WIRE_9, io.in_b.bits node _mac_unit_io_in_b_T_4 = bits(_mac_unit_io_in_b_WIRE_9, 31, 0) connect _mac_unit_io_in_b_WIRE_8.bits, _mac_unit_io_in_b_T_4 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_8.bits connect mac_unit.io.in_c.bits, c2.bits node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b.bits invalidate mac_unit.io.in_c.bits

module PE_23( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [31:0] io_in_a_bits, // @[PE.scala:35:14] input [31:0] io_in_b_bits, // @[PE.scala:35:14] input [31:0] io_in_d_bits, // @[PE.scala:35:14] output [31:0] io_out_a_bits, // @[PE.scala:35:14] output [31:0] io_out_b_bits, // @[PE.scala:35:14] output [31:0] io_out_c_bits, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [3:0] io_in_id, // @[PE.scala:35:14] output [3:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30] wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30] wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7] wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15] wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7] wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37] wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37] wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7] wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7] reg [31:0] c1_bits; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38] reg [31:0] c2_bits; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] | _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29] wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34] wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34] wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] | _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T = |io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15] wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}] wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26] wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN | io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 | _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] | _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26] wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN | io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 | _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37] assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37] wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] | _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26] wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN | c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 | _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] | _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29] wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] | _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T_4 = |io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15] wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_76 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_89 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_76( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_89 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module EntropyCompressorMemwriter_2 : input clock : Clock input reset : Reset output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, l2io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip decompress_dest_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>}}, bufs_completed : UInt<64>, no_writes_inflight : UInt<1>} inst incoming_writes_Q of Queue4_WriterBundle_8 connect incoming_writes_Q.clock, clock connect incoming_writes_Q.reset, reset connect incoming_writes_Q.io.enq, io.memwrites_in inst decompress_dest_info_Q of Queue4_DstInfo_9 connect decompress_dest_info_Q.clock, clock connect decompress_dest_info_Q.reset, reset connect decompress_dest_info_Q.io.enq, io.decompress_dest_info node _decompress_dest_last_fire_T = and(decompress_dest_info_Q.io.deq.ready, decompress_dest_info_Q.io.deq.valid) reg decompress_dest_last_fire : UInt<1>, clock connect decompress_dest_last_fire, _decompress_dest_last_fire_T reg decompress_dest_last_valid : UInt<1>, clock connect decompress_dest_last_valid, decompress_dest_info_Q.io.deq.valid node _decompress_dest_printhelp_T = eq(decompress_dest_last_valid, UInt<1>(0h0)) node _decompress_dest_printhelp_T_1 = or(decompress_dest_last_fire, _decompress_dest_printhelp_T) node decompress_dest_printhelp = and(decompress_dest_info_Q.io.deq.valid, _decompress_dest_printhelp_T_1) when decompress_dest_printhelp : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] got dest info op: 0x%x, cmpflag 0x%x\n", decompress_dest_info_Q.io.deq.bits.op, decompress_dest_info_Q.io.deq.bits.cmpflag) : printf_1 inst buf_lens_Q of Queue10_UInt64_13 connect buf_lens_Q.clock, clock connect buf_lens_Q.reset, reset node _T_4 = and(buf_lens_Q.io.enq.ready, buf_lens_Q.io.enq.valid) when _T_4 : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits) : printf_3 regreset buf_len_tracker : UInt<64>, clock, reset, UInt<64>(0h0) node _T_9 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_9 : when incoming_writes_Q.io.deq.bits.end_of_message : connect buf_len_tracker, UInt<1>(0h0) else : node _buf_len_tracker_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_len_tracker, _buf_len_tracker_T node _T_10 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_10 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_5 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue16_UInt8 of Queue16_UInt8_96 connect Queue16_UInt8.clock, clock connect Queue16_UInt8.reset, reset inst Queue16_UInt8_1 of Queue16_UInt8_97 connect Queue16_UInt8_1.clock, clock connect Queue16_UInt8_1.reset, reset inst Queue16_UInt8_2 of Queue16_UInt8_98 connect Queue16_UInt8_2.clock, clock connect Queue16_UInt8_2.reset, reset inst Queue16_UInt8_3 of Queue16_UInt8_99 connect Queue16_UInt8_3.clock, clock connect Queue16_UInt8_3.reset, reset inst Queue16_UInt8_4 of Queue16_UInt8_100 connect Queue16_UInt8_4.clock, clock connect Queue16_UInt8_4.reset, reset inst Queue16_UInt8_5 of Queue16_UInt8_101 connect Queue16_UInt8_5.clock, clock connect Queue16_UInt8_5.reset, reset inst Queue16_UInt8_6 of Queue16_UInt8_102 connect Queue16_UInt8_6.clock, clock connect Queue16_UInt8_6.reset, reset inst Queue16_UInt8_7 of Queue16_UInt8_103 connect Queue16_UInt8_7.clock, clock connect Queue16_UInt8_7.reset, reset inst Queue16_UInt8_8 of Queue16_UInt8_104 connect Queue16_UInt8_8.clock, clock connect Queue16_UInt8_8.reset, reset inst Queue16_UInt8_9 of Queue16_UInt8_105 connect Queue16_UInt8_9.clock, clock connect Queue16_UInt8_9.reset, reset inst Queue16_UInt8_10 of Queue16_UInt8_106 connect Queue16_UInt8_10.clock, clock connect Queue16_UInt8_10.reset, reset inst Queue16_UInt8_11 of Queue16_UInt8_107 connect Queue16_UInt8_11.clock, clock connect Queue16_UInt8_11.reset, reset inst Queue16_UInt8_12 of Queue16_UInt8_108 connect Queue16_UInt8_12.clock, clock connect Queue16_UInt8_12.reset, reset inst Queue16_UInt8_13 of Queue16_UInt8_109 connect Queue16_UInt8_13.clock, clock connect Queue16_UInt8_13.reset, reset inst Queue16_UInt8_14 of Queue16_UInt8_110 connect Queue16_UInt8_14.clock, clock connect Queue16_UInt8_14.reset, reset inst Queue16_UInt8_15 of Queue16_UInt8_111 connect Queue16_UInt8_15.clock, clock connect Queue16_UInt8_15.reset, reset inst Queue16_UInt8_16 of Queue16_UInt8_112 connect Queue16_UInt8_16.clock, clock connect Queue16_UInt8_16.reset, reset inst Queue16_UInt8_17 of Queue16_UInt8_113 connect Queue16_UInt8_17.clock, clock connect Queue16_UInt8_17.reset, reset inst Queue16_UInt8_18 of Queue16_UInt8_114 connect Queue16_UInt8_18.clock, clock connect Queue16_UInt8_18.reset, reset inst Queue16_UInt8_19 of Queue16_UInt8_115 connect Queue16_UInt8_19.clock, clock connect Queue16_UInt8_19.reset, reset inst Queue16_UInt8_20 of Queue16_UInt8_116 connect Queue16_UInt8_20.clock, clock connect Queue16_UInt8_20.reset, reset inst Queue16_UInt8_21 of Queue16_UInt8_117 connect Queue16_UInt8_21.clock, clock connect Queue16_UInt8_21.reset, reset inst Queue16_UInt8_22 of Queue16_UInt8_118 connect Queue16_UInt8_22.clock, clock connect Queue16_UInt8_22.reset, reset inst Queue16_UInt8_23 of Queue16_UInt8_119 connect Queue16_UInt8_23.clock, clock connect Queue16_UInt8_23.reset, reset inst Queue16_UInt8_24 of Queue16_UInt8_120 connect Queue16_UInt8_24.clock, clock connect Queue16_UInt8_24.reset, reset inst Queue16_UInt8_25 of Queue16_UInt8_121 connect Queue16_UInt8_25.clock, clock connect Queue16_UInt8_25.reset, reset inst Queue16_UInt8_26 of Queue16_UInt8_122 connect Queue16_UInt8_26.clock, clock connect Queue16_UInt8_26.reset, reset inst Queue16_UInt8_27 of Queue16_UInt8_123 connect Queue16_UInt8_27.clock, clock connect Queue16_UInt8_27.reset, reset inst Queue16_UInt8_28 of Queue16_UInt8_124 connect Queue16_UInt8_28.clock, clock connect Queue16_UInt8_28.reset, reset inst Queue16_UInt8_29 of Queue16_UInt8_125 connect Queue16_UInt8_29.clock, clock connect Queue16_UInt8_29.reset, reset inst Queue16_UInt8_30 of Queue16_UInt8_126 connect Queue16_UInt8_30.clock, clock connect Queue16_UInt8_30.reset, reset inst Queue16_UInt8_31 of Queue16_UInt8_127 connect Queue16_UInt8_31.clock, clock connect Queue16_UInt8_31.reset, reset connect Queue16_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue16_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_15 = eq(UInt<1>(0h0), idx) when _T_15 : node _T_16 = shl(UInt<1>(0h0), 3) node _T_17 = dshr(incoming_writes_Q.io.deq.bits.data, _T_16) node _T_18 = bits(_T_17, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_18 node _T_19 = eq(UInt<1>(0h1), idx) when _T_19 : node _T_20 = shl(UInt<1>(0h0), 3) node _T_21 = dshr(incoming_writes_Q.io.deq.bits.data, _T_20) node _T_22 = bits(_T_21, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_22 node _T_23 = eq(UInt<2>(0h2), idx) when _T_23 : node _T_24 = shl(UInt<1>(0h0), 3) node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24) node _T_26 = bits(_T_25, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_26 node _T_27 = eq(UInt<2>(0h3), idx) when _T_27 : node _T_28 = shl(UInt<1>(0h0), 3) node _T_29 = dshr(incoming_writes_Q.io.deq.bits.data, _T_28) node _T_30 = bits(_T_29, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_30 node _T_31 = eq(UInt<3>(0h4), idx) when _T_31 : node _T_32 = shl(UInt<1>(0h0), 3) node _T_33 = dshr(incoming_writes_Q.io.deq.bits.data, _T_32) node _T_34 = bits(_T_33, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_34 node _T_35 = eq(UInt<3>(0h5), idx) when _T_35 : node _T_36 = shl(UInt<1>(0h0), 3) node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36) node _T_38 = bits(_T_37, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_38 node _T_39 = eq(UInt<3>(0h6), idx) when _T_39 : node _T_40 = shl(UInt<1>(0h0), 3) node _T_41 = dshr(incoming_writes_Q.io.deq.bits.data, _T_40) node _T_42 = bits(_T_41, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_42 node _T_43 = eq(UInt<3>(0h7), idx) when _T_43 : node _T_44 = shl(UInt<1>(0h0), 3) node _T_45 = dshr(incoming_writes_Q.io.deq.bits.data, _T_44) node _T_46 = bits(_T_45, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_46 node _T_47 = eq(UInt<4>(0h8), idx) when _T_47 : node _T_48 = shl(UInt<1>(0h0), 3) node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48) node _T_50 = bits(_T_49, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_50 node _T_51 = eq(UInt<4>(0h9), idx) when _T_51 : node _T_52 = shl(UInt<1>(0h0), 3) node _T_53 = dshr(incoming_writes_Q.io.deq.bits.data, _T_52) node _T_54 = bits(_T_53, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_54 node _T_55 = eq(UInt<4>(0ha), idx) when _T_55 : node _T_56 = shl(UInt<1>(0h0), 3) node _T_57 = dshr(incoming_writes_Q.io.deq.bits.data, _T_56) node _T_58 = bits(_T_57, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_58 node _T_59 = eq(UInt<4>(0hb), idx) when _T_59 : node _T_60 = shl(UInt<1>(0h0), 3) node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60) node _T_62 = bits(_T_61, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_62 node _T_63 = eq(UInt<4>(0hc), idx) when _T_63 : node _T_64 = shl(UInt<1>(0h0), 3) node _T_65 = dshr(incoming_writes_Q.io.deq.bits.data, _T_64) node _T_66 = bits(_T_65, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_66 node _T_67 = eq(UInt<4>(0hd), idx) when _T_67 : node _T_68 = shl(UInt<1>(0h0), 3) node _T_69 = dshr(incoming_writes_Q.io.deq.bits.data, _T_68) node _T_70 = bits(_T_69, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_70 node _T_71 = eq(UInt<4>(0he), idx) when _T_71 : node _T_72 = shl(UInt<1>(0h0), 3) node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72) node _T_74 = bits(_T_73, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_74 node _T_75 = eq(UInt<4>(0hf), idx) when _T_75 : node _T_76 = shl(UInt<1>(0h0), 3) node _T_77 = dshr(incoming_writes_Q.io.deq.bits.data, _T_76) node _T_78 = bits(_T_77, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_78 node _T_79 = eq(UInt<5>(0h10), idx) when _T_79 : node _T_80 = shl(UInt<1>(0h0), 3) node _T_81 = dshr(incoming_writes_Q.io.deq.bits.data, _T_80) node _T_82 = bits(_T_81, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_82 node _T_83 = eq(UInt<5>(0h11), idx) when _T_83 : node _T_84 = shl(UInt<1>(0h0), 3) node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84) node _T_86 = bits(_T_85, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_86 node _T_87 = eq(UInt<5>(0h12), idx) when _T_87 : node _T_88 = shl(UInt<1>(0h0), 3) node _T_89 = dshr(incoming_writes_Q.io.deq.bits.data, _T_88) node _T_90 = bits(_T_89, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_90 node _T_91 = eq(UInt<5>(0h13), idx) when _T_91 : node _T_92 = shl(UInt<1>(0h0), 3) node _T_93 = dshr(incoming_writes_Q.io.deq.bits.data, _T_92) node _T_94 = bits(_T_93, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_94 node _T_95 = eq(UInt<5>(0h14), idx) when _T_95 : node _T_96 = shl(UInt<1>(0h0), 3) node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96) node _T_98 = bits(_T_97, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_98 node _T_99 = eq(UInt<5>(0h15), idx) when _T_99 : node _T_100 = shl(UInt<1>(0h0), 3) node _T_101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_100) node _T_102 = bits(_T_101, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_102 node _T_103 = eq(UInt<5>(0h16), idx) when _T_103 : node _T_104 = shl(UInt<1>(0h0), 3) node _T_105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_104) node _T_106 = bits(_T_105, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_106 node _T_107 = eq(UInt<5>(0h17), idx) when _T_107 : node _T_108 = shl(UInt<1>(0h0), 3) node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108) node _T_110 = bits(_T_109, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_110 node _T_111 = eq(UInt<5>(0h18), idx) when _T_111 : node _T_112 = shl(UInt<1>(0h0), 3) node _T_113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_112) node _T_114 = bits(_T_113, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_114 node _T_115 = eq(UInt<5>(0h19), idx) when _T_115 : node _T_116 = shl(UInt<1>(0h0), 3) node _T_117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_116) node _T_118 = bits(_T_117, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_118 node _T_119 = eq(UInt<5>(0h1a), idx) when _T_119 : node _T_120 = shl(UInt<1>(0h0), 3) node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120) node _T_122 = bits(_T_121, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_122 node _T_123 = eq(UInt<5>(0h1b), idx) when _T_123 : node _T_124 = shl(UInt<1>(0h0), 3) node _T_125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_124) node _T_126 = bits(_T_125, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_126 node _T_127 = eq(UInt<5>(0h1c), idx) when _T_127 : node _T_128 = shl(UInt<1>(0h0), 3) node _T_129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_128) node _T_130 = bits(_T_129, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_130 node _T_131 = eq(UInt<5>(0h1d), idx) when _T_131 : node _T_132 = shl(UInt<1>(0h0), 3) node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132) node _T_134 = bits(_T_133, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_134 node _T_135 = eq(UInt<5>(0h1e), idx) when _T_135 : node _T_136 = shl(UInt<1>(0h0), 3) node _T_137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_136) node _T_138 = bits(_T_137, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_138 node _T_139 = eq(UInt<5>(0h1f), idx) when _T_139 : node _T_140 = shl(UInt<1>(0h0), 3) node _T_141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_140) node _T_142 = bits(_T_141, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_142 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_143 = eq(UInt<1>(0h0), idx_1) when _T_143 : node _T_144 = shl(UInt<1>(0h1), 3) node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144) node _T_146 = bits(_T_145, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_146 node _T_147 = eq(UInt<1>(0h1), idx_1) when _T_147 : node _T_148 = shl(UInt<1>(0h1), 3) node _T_149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_148) node _T_150 = bits(_T_149, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_150 node _T_151 = eq(UInt<2>(0h2), idx_1) when _T_151 : node _T_152 = shl(UInt<1>(0h1), 3) node _T_153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_152) node _T_154 = bits(_T_153, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_154 node _T_155 = eq(UInt<2>(0h3), idx_1) when _T_155 : node _T_156 = shl(UInt<1>(0h1), 3) node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156) node _T_158 = bits(_T_157, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_158 node _T_159 = eq(UInt<3>(0h4), idx_1) when _T_159 : node _T_160 = shl(UInt<1>(0h1), 3) node _T_161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_160) node _T_162 = bits(_T_161, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_162 node _T_163 = eq(UInt<3>(0h5), idx_1) when _T_163 : node _T_164 = shl(UInt<1>(0h1), 3) node _T_165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_164) node _T_166 = bits(_T_165, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_166 node _T_167 = eq(UInt<3>(0h6), idx_1) when _T_167 : node _T_168 = shl(UInt<1>(0h1), 3) node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168) node _T_170 = bits(_T_169, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_170 node _T_171 = eq(UInt<3>(0h7), idx_1) when _T_171 : node _T_172 = shl(UInt<1>(0h1), 3) node _T_173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_172) node _T_174 = bits(_T_173, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_174 node _T_175 = eq(UInt<4>(0h8), idx_1) when _T_175 : node _T_176 = shl(UInt<1>(0h1), 3) node _T_177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_176) node _T_178 = bits(_T_177, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_178 node _T_179 = eq(UInt<4>(0h9), idx_1) when _T_179 : node _T_180 = shl(UInt<1>(0h1), 3) node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180) node _T_182 = bits(_T_181, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_182 node _T_183 = eq(UInt<4>(0ha), idx_1) when _T_183 : node _T_184 = shl(UInt<1>(0h1), 3) node _T_185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_184) node _T_186 = bits(_T_185, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_186 node _T_187 = eq(UInt<4>(0hb), idx_1) when _T_187 : node _T_188 = shl(UInt<1>(0h1), 3) node _T_189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_188) node _T_190 = bits(_T_189, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_190 node _T_191 = eq(UInt<4>(0hc), idx_1) when _T_191 : node _T_192 = shl(UInt<1>(0h1), 3) node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192) node _T_194 = bits(_T_193, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_194 node _T_195 = eq(UInt<4>(0hd), idx_1) when _T_195 : node _T_196 = shl(UInt<1>(0h1), 3) node _T_197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_196) node _T_198 = bits(_T_197, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_198 node _T_199 = eq(UInt<4>(0he), idx_1) when _T_199 : node _T_200 = shl(UInt<1>(0h1), 3) node _T_201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_200) node _T_202 = bits(_T_201, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_202 node _T_203 = eq(UInt<4>(0hf), idx_1) when _T_203 : node _T_204 = shl(UInt<1>(0h1), 3) node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204) node _T_206 = bits(_T_205, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_206 node _T_207 = eq(UInt<5>(0h10), idx_1) when _T_207 : node _T_208 = shl(UInt<1>(0h1), 3) node _T_209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_208) node _T_210 = bits(_T_209, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_210 node _T_211 = eq(UInt<5>(0h11), idx_1) when _T_211 : node _T_212 = shl(UInt<1>(0h1), 3) node _T_213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_212) node _T_214 = bits(_T_213, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_214 node _T_215 = eq(UInt<5>(0h12), idx_1) when _T_215 : node _T_216 = shl(UInt<1>(0h1), 3) node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216) node _T_218 = bits(_T_217, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_218 node _T_219 = eq(UInt<5>(0h13), idx_1) when _T_219 : node _T_220 = shl(UInt<1>(0h1), 3) node _T_221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_220) node _T_222 = bits(_T_221, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_222 node _T_223 = eq(UInt<5>(0h14), idx_1) when _T_223 : node _T_224 = shl(UInt<1>(0h1), 3) node _T_225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_224) node _T_226 = bits(_T_225, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_226 node _T_227 = eq(UInt<5>(0h15), idx_1) when _T_227 : node _T_228 = shl(UInt<1>(0h1), 3) node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228) node _T_230 = bits(_T_229, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_230 node _T_231 = eq(UInt<5>(0h16), idx_1) when _T_231 : node _T_232 = shl(UInt<1>(0h1), 3) node _T_233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_232) node _T_234 = bits(_T_233, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_234 node _T_235 = eq(UInt<5>(0h17), idx_1) when _T_235 : node _T_236 = shl(UInt<1>(0h1), 3) node _T_237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_236) node _T_238 = bits(_T_237, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_238 node _T_239 = eq(UInt<5>(0h18), idx_1) when _T_239 : node _T_240 = shl(UInt<1>(0h1), 3) node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240) node _T_242 = bits(_T_241, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_242 node _T_243 = eq(UInt<5>(0h19), idx_1) when _T_243 : node _T_244 = shl(UInt<1>(0h1), 3) node _T_245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_244) node _T_246 = bits(_T_245, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_246 node _T_247 = eq(UInt<5>(0h1a), idx_1) when _T_247 : node _T_248 = shl(UInt<1>(0h1), 3) node _T_249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_248) node _T_250 = bits(_T_249, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_250 node _T_251 = eq(UInt<5>(0h1b), idx_1) when _T_251 : node _T_252 = shl(UInt<1>(0h1), 3) node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252) node _T_254 = bits(_T_253, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_254 node _T_255 = eq(UInt<5>(0h1c), idx_1) when _T_255 : node _T_256 = shl(UInt<1>(0h1), 3) node _T_257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_256) node _T_258 = bits(_T_257, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_258 node _T_259 = eq(UInt<5>(0h1d), idx_1) when _T_259 : node _T_260 = shl(UInt<1>(0h1), 3) node _T_261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_260) node _T_262 = bits(_T_261, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_262 node _T_263 = eq(UInt<5>(0h1e), idx_1) when _T_263 : node _T_264 = shl(UInt<1>(0h1), 3) node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264) node _T_266 = bits(_T_265, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_266 node _T_267 = eq(UInt<5>(0h1f), idx_1) when _T_267 : node _T_268 = shl(UInt<1>(0h1), 3) node _T_269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_268) node _T_270 = bits(_T_269, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_270 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_271 = eq(UInt<1>(0h0), idx_2) when _T_271 : node _T_272 = shl(UInt<2>(0h2), 3) node _T_273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_272) node _T_274 = bits(_T_273, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_274 node _T_275 = eq(UInt<1>(0h1), idx_2) when _T_275 : node _T_276 = shl(UInt<2>(0h2), 3) node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276) node _T_278 = bits(_T_277, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_278 node _T_279 = eq(UInt<2>(0h2), idx_2) when _T_279 : node _T_280 = shl(UInt<2>(0h2), 3) node _T_281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_280) node _T_282 = bits(_T_281, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_282 node _T_283 = eq(UInt<2>(0h3), idx_2) when _T_283 : node _T_284 = shl(UInt<2>(0h2), 3) node _T_285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_284) node _T_286 = bits(_T_285, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_286 node _T_287 = eq(UInt<3>(0h4), idx_2) when _T_287 : node _T_288 = shl(UInt<2>(0h2), 3) node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288) node _T_290 = bits(_T_289, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_290 node _T_291 = eq(UInt<3>(0h5), idx_2) when _T_291 : node _T_292 = shl(UInt<2>(0h2), 3) node _T_293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_292) node _T_294 = bits(_T_293, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_294 node _T_295 = eq(UInt<3>(0h6), idx_2) when _T_295 : node _T_296 = shl(UInt<2>(0h2), 3) node _T_297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_296) node _T_298 = bits(_T_297, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_298 node _T_299 = eq(UInt<3>(0h7), idx_2) when _T_299 : node _T_300 = shl(UInt<2>(0h2), 3) node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300) node _T_302 = bits(_T_301, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_302 node _T_303 = eq(UInt<4>(0h8), idx_2) when _T_303 : node _T_304 = shl(UInt<2>(0h2), 3) node _T_305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_304) node _T_306 = bits(_T_305, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_306 node _T_307 = eq(UInt<4>(0h9), idx_2) when _T_307 : node _T_308 = shl(UInt<2>(0h2), 3) node _T_309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_308) node _T_310 = bits(_T_309, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_310 node _T_311 = eq(UInt<4>(0ha), idx_2) when _T_311 : node _T_312 = shl(UInt<2>(0h2), 3) node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312) node _T_314 = bits(_T_313, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_314 node _T_315 = eq(UInt<4>(0hb), idx_2) when _T_315 : node _T_316 = shl(UInt<2>(0h2), 3) node _T_317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_316) node _T_318 = bits(_T_317, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_318 node _T_319 = eq(UInt<4>(0hc), idx_2) when _T_319 : node _T_320 = shl(UInt<2>(0h2), 3) node _T_321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_320) node _T_322 = bits(_T_321, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_322 node _T_323 = eq(UInt<4>(0hd), idx_2) when _T_323 : node _T_324 = shl(UInt<2>(0h2), 3) node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324) node _T_326 = bits(_T_325, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_326 node _T_327 = eq(UInt<4>(0he), idx_2) when _T_327 : node _T_328 = shl(UInt<2>(0h2), 3) node _T_329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_328) node _T_330 = bits(_T_329, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_330 node _T_331 = eq(UInt<4>(0hf), idx_2) when _T_331 : node _T_332 = shl(UInt<2>(0h2), 3) node _T_333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_332) node _T_334 = bits(_T_333, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_334 node _T_335 = eq(UInt<5>(0h10), idx_2) when _T_335 : node _T_336 = shl(UInt<2>(0h2), 3) node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336) node _T_338 = bits(_T_337, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_338 node _T_339 = eq(UInt<5>(0h11), idx_2) when _T_339 : node _T_340 = shl(UInt<2>(0h2), 3) node _T_341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_340) node _T_342 = bits(_T_341, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_342 node _T_343 = eq(UInt<5>(0h12), idx_2) when _T_343 : node _T_344 = shl(UInt<2>(0h2), 3) node _T_345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_344) node _T_346 = bits(_T_345, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_346 node _T_347 = eq(UInt<5>(0h13), idx_2) when _T_347 : node _T_348 = shl(UInt<2>(0h2), 3) node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348) node _T_350 = bits(_T_349, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_350 node _T_351 = eq(UInt<5>(0h14), idx_2) when _T_351 : node _T_352 = shl(UInt<2>(0h2), 3) node _T_353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_352) node _T_354 = bits(_T_353, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_354 node _T_355 = eq(UInt<5>(0h15), idx_2) when _T_355 : node _T_356 = shl(UInt<2>(0h2), 3) node _T_357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_356) node _T_358 = bits(_T_357, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_358 node _T_359 = eq(UInt<5>(0h16), idx_2) when _T_359 : node _T_360 = shl(UInt<2>(0h2), 3) node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360) node _T_362 = bits(_T_361, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_362 node _T_363 = eq(UInt<5>(0h17), idx_2) when _T_363 : node _T_364 = shl(UInt<2>(0h2), 3) node _T_365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_364) node _T_366 = bits(_T_365, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_366 node _T_367 = eq(UInt<5>(0h18), idx_2) when _T_367 : node _T_368 = shl(UInt<2>(0h2), 3) node _T_369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_368) node _T_370 = bits(_T_369, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_370 node _T_371 = eq(UInt<5>(0h19), idx_2) when _T_371 : node _T_372 = shl(UInt<2>(0h2), 3) node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372) node _T_374 = bits(_T_373, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_374 node _T_375 = eq(UInt<5>(0h1a), idx_2) when _T_375 : node _T_376 = shl(UInt<2>(0h2), 3) node _T_377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_376) node _T_378 = bits(_T_377, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_378 node _T_379 = eq(UInt<5>(0h1b), idx_2) when _T_379 : node _T_380 = shl(UInt<2>(0h2), 3) node _T_381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_380) node _T_382 = bits(_T_381, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_382 node _T_383 = eq(UInt<5>(0h1c), idx_2) when _T_383 : node _T_384 = shl(UInt<2>(0h2), 3) node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384) node _T_386 = bits(_T_385, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_386 node _T_387 = eq(UInt<5>(0h1d), idx_2) when _T_387 : node _T_388 = shl(UInt<2>(0h2), 3) node _T_389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_388) node _T_390 = bits(_T_389, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_390 node _T_391 = eq(UInt<5>(0h1e), idx_2) when _T_391 : node _T_392 = shl(UInt<2>(0h2), 3) node _T_393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_392) node _T_394 = bits(_T_393, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_394 node _T_395 = eq(UInt<5>(0h1f), idx_2) when _T_395 : node _T_396 = shl(UInt<2>(0h2), 3) node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396) node _T_398 = bits(_T_397, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_398 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_399 = eq(UInt<1>(0h0), idx_3) when _T_399 : node _T_400 = shl(UInt<2>(0h3), 3) node _T_401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_400) node _T_402 = bits(_T_401, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_402 node _T_403 = eq(UInt<1>(0h1), idx_3) when _T_403 : node _T_404 = shl(UInt<2>(0h3), 3) node _T_405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_404) node _T_406 = bits(_T_405, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_406 node _T_407 = eq(UInt<2>(0h2), idx_3) when _T_407 : node _T_408 = shl(UInt<2>(0h3), 3) node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408) node _T_410 = bits(_T_409, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_410 node _T_411 = eq(UInt<2>(0h3), idx_3) when _T_411 : node _T_412 = shl(UInt<2>(0h3), 3) node _T_413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_412) node _T_414 = bits(_T_413, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_414 node _T_415 = eq(UInt<3>(0h4), idx_3) when _T_415 : node _T_416 = shl(UInt<2>(0h3), 3) node _T_417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_416) node _T_418 = bits(_T_417, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_418 node _T_419 = eq(UInt<3>(0h5), idx_3) when _T_419 : node _T_420 = shl(UInt<2>(0h3), 3) node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420) node _T_422 = bits(_T_421, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_422 node _T_423 = eq(UInt<3>(0h6), idx_3) when _T_423 : node _T_424 = shl(UInt<2>(0h3), 3) node _T_425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_424) node _T_426 = bits(_T_425, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_426 node _T_427 = eq(UInt<3>(0h7), idx_3) when _T_427 : node _T_428 = shl(UInt<2>(0h3), 3) node _T_429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_428) node _T_430 = bits(_T_429, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_430 node _T_431 = eq(UInt<4>(0h8), idx_3) when _T_431 : node _T_432 = shl(UInt<2>(0h3), 3) node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432) node _T_434 = bits(_T_433, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_434 node _T_435 = eq(UInt<4>(0h9), idx_3) when _T_435 : node _T_436 = shl(UInt<2>(0h3), 3) node _T_437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_436) node _T_438 = bits(_T_437, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_438 node _T_439 = eq(UInt<4>(0ha), idx_3) when _T_439 : node _T_440 = shl(UInt<2>(0h3), 3) node _T_441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_440) node _T_442 = bits(_T_441, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_442 node _T_443 = eq(UInt<4>(0hb), idx_3) when _T_443 : node _T_444 = shl(UInt<2>(0h3), 3) node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444) node _T_446 = bits(_T_445, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_446 node _T_447 = eq(UInt<4>(0hc), idx_3) when _T_447 : node _T_448 = shl(UInt<2>(0h3), 3) node _T_449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_448) node _T_450 = bits(_T_449, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_450 node _T_451 = eq(UInt<4>(0hd), idx_3) when _T_451 : node _T_452 = shl(UInt<2>(0h3), 3) node _T_453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_452) node _T_454 = bits(_T_453, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_454 node _T_455 = eq(UInt<4>(0he), idx_3) when _T_455 : node _T_456 = shl(UInt<2>(0h3), 3) node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456) node _T_458 = bits(_T_457, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_458 node _T_459 = eq(UInt<4>(0hf), idx_3) when _T_459 : node _T_460 = shl(UInt<2>(0h3), 3) node _T_461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_460) node _T_462 = bits(_T_461, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_462 node _T_463 = eq(UInt<5>(0h10), idx_3) when _T_463 : node _T_464 = shl(UInt<2>(0h3), 3) node _T_465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_464) node _T_466 = bits(_T_465, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_466 node _T_467 = eq(UInt<5>(0h11), idx_3) when _T_467 : node _T_468 = shl(UInt<2>(0h3), 3) node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468) node _T_470 = bits(_T_469, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_470 node _T_471 = eq(UInt<5>(0h12), idx_3) when _T_471 : node _T_472 = shl(UInt<2>(0h3), 3) node _T_473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_472) node _T_474 = bits(_T_473, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_474 node _T_475 = eq(UInt<5>(0h13), idx_3) when _T_475 : node _T_476 = shl(UInt<2>(0h3), 3) node _T_477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_476) node _T_478 = bits(_T_477, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_478 node _T_479 = eq(UInt<5>(0h14), idx_3) when _T_479 : node _T_480 = shl(UInt<2>(0h3), 3) node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480) node _T_482 = bits(_T_481, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_482 node _T_483 = eq(UInt<5>(0h15), idx_3) when _T_483 : node _T_484 = shl(UInt<2>(0h3), 3) node _T_485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_484) node _T_486 = bits(_T_485, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_486 node _T_487 = eq(UInt<5>(0h16), idx_3) when _T_487 : node _T_488 = shl(UInt<2>(0h3), 3) node _T_489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_488) node _T_490 = bits(_T_489, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_490 node _T_491 = eq(UInt<5>(0h17), idx_3) when _T_491 : node _T_492 = shl(UInt<2>(0h3), 3) node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492) node _T_494 = bits(_T_493, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_494 node _T_495 = eq(UInt<5>(0h18), idx_3) when _T_495 : node _T_496 = shl(UInt<2>(0h3), 3) node _T_497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_496) node _T_498 = bits(_T_497, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_498 node _T_499 = eq(UInt<5>(0h19), idx_3) when _T_499 : node _T_500 = shl(UInt<2>(0h3), 3) node _T_501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_500) node _T_502 = bits(_T_501, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_502 node _T_503 = eq(UInt<5>(0h1a), idx_3) when _T_503 : node _T_504 = shl(UInt<2>(0h3), 3) node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504) node _T_506 = bits(_T_505, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_506 node _T_507 = eq(UInt<5>(0h1b), idx_3) when _T_507 : node _T_508 = shl(UInt<2>(0h3), 3) node _T_509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_508) node _T_510 = bits(_T_509, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_510 node _T_511 = eq(UInt<5>(0h1c), idx_3) when _T_511 : node _T_512 = shl(UInt<2>(0h3), 3) node _T_513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_512) node _T_514 = bits(_T_513, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_514 node _T_515 = eq(UInt<5>(0h1d), idx_3) when _T_515 : node _T_516 = shl(UInt<2>(0h3), 3) node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516) node _T_518 = bits(_T_517, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_518 node _T_519 = eq(UInt<5>(0h1e), idx_3) when _T_519 : node _T_520 = shl(UInt<2>(0h3), 3) node _T_521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_520) node _T_522 = bits(_T_521, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_522 node _T_523 = eq(UInt<5>(0h1f), idx_3) when _T_523 : node _T_524 = shl(UInt<2>(0h3), 3) node _T_525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_524) node _T_526 = bits(_T_525, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_526 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_527 = eq(UInt<1>(0h0), idx_4) when _T_527 : node _T_528 = shl(UInt<3>(0h4), 3) node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528) node _T_530 = bits(_T_529, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_530 node _T_531 = eq(UInt<1>(0h1), idx_4) when _T_531 : node _T_532 = shl(UInt<3>(0h4), 3) node _T_533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_532) node _T_534 = bits(_T_533, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_534 node _T_535 = eq(UInt<2>(0h2), idx_4) when _T_535 : node _T_536 = shl(UInt<3>(0h4), 3) node _T_537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_536) node _T_538 = bits(_T_537, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_538 node _T_539 = eq(UInt<2>(0h3), idx_4) when _T_539 : node _T_540 = shl(UInt<3>(0h4), 3) node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540) node _T_542 = bits(_T_541, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_542 node _T_543 = eq(UInt<3>(0h4), idx_4) when _T_543 : node _T_544 = shl(UInt<3>(0h4), 3) node _T_545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_544) node _T_546 = bits(_T_545, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_546 node _T_547 = eq(UInt<3>(0h5), idx_4) when _T_547 : node _T_548 = shl(UInt<3>(0h4), 3) node _T_549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_548) node _T_550 = bits(_T_549, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_550 node _T_551 = eq(UInt<3>(0h6), idx_4) when _T_551 : node _T_552 = shl(UInt<3>(0h4), 3) node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552) node _T_554 = bits(_T_553, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_554 node _T_555 = eq(UInt<3>(0h7), idx_4) when _T_555 : node _T_556 = shl(UInt<3>(0h4), 3) node _T_557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_556) node _T_558 = bits(_T_557, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_558 node _T_559 = eq(UInt<4>(0h8), idx_4) when _T_559 : node _T_560 = shl(UInt<3>(0h4), 3) node _T_561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_560) node _T_562 = bits(_T_561, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_562 node _T_563 = eq(UInt<4>(0h9), idx_4) when _T_563 : node _T_564 = shl(UInt<3>(0h4), 3) node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564) node _T_566 = bits(_T_565, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_566 node _T_567 = eq(UInt<4>(0ha), idx_4) when _T_567 : node _T_568 = shl(UInt<3>(0h4), 3) node _T_569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_568) node _T_570 = bits(_T_569, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_570 node _T_571 = eq(UInt<4>(0hb), idx_4) when _T_571 : node _T_572 = shl(UInt<3>(0h4), 3) node _T_573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_572) node _T_574 = bits(_T_573, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_574 node _T_575 = eq(UInt<4>(0hc), idx_4) when _T_575 : node _T_576 = shl(UInt<3>(0h4), 3) node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576) node _T_578 = bits(_T_577, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_578 node _T_579 = eq(UInt<4>(0hd), idx_4) when _T_579 : node _T_580 = shl(UInt<3>(0h4), 3) node _T_581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_580) node _T_582 = bits(_T_581, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_582 node _T_583 = eq(UInt<4>(0he), idx_4) when _T_583 : node _T_584 = shl(UInt<3>(0h4), 3) node _T_585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_584) node _T_586 = bits(_T_585, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_586 node _T_587 = eq(UInt<4>(0hf), idx_4) when _T_587 : node _T_588 = shl(UInt<3>(0h4), 3) node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588) node _T_590 = bits(_T_589, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_590 node _T_591 = eq(UInt<5>(0h10), idx_4) when _T_591 : node _T_592 = shl(UInt<3>(0h4), 3) node _T_593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_592) node _T_594 = bits(_T_593, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_594 node _T_595 = eq(UInt<5>(0h11), idx_4) when _T_595 : node _T_596 = shl(UInt<3>(0h4), 3) node _T_597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_596) node _T_598 = bits(_T_597, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_598 node _T_599 = eq(UInt<5>(0h12), idx_4) when _T_599 : node _T_600 = shl(UInt<3>(0h4), 3) node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600) node _T_602 = bits(_T_601, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_602 node _T_603 = eq(UInt<5>(0h13), idx_4) when _T_603 : node _T_604 = shl(UInt<3>(0h4), 3) node _T_605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_604) node _T_606 = bits(_T_605, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_606 node _T_607 = eq(UInt<5>(0h14), idx_4) when _T_607 : node _T_608 = shl(UInt<3>(0h4), 3) node _T_609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_608) node _T_610 = bits(_T_609, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_610 node _T_611 = eq(UInt<5>(0h15), idx_4) when _T_611 : node _T_612 = shl(UInt<3>(0h4), 3) node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612) node _T_614 = bits(_T_613, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_614 node _T_615 = eq(UInt<5>(0h16), idx_4) when _T_615 : node _T_616 = shl(UInt<3>(0h4), 3) node _T_617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_616) node _T_618 = bits(_T_617, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_618 node _T_619 = eq(UInt<5>(0h17), idx_4) when _T_619 : node _T_620 = shl(UInt<3>(0h4), 3) node _T_621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_620) node _T_622 = bits(_T_621, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_622 node _T_623 = eq(UInt<5>(0h18), idx_4) when _T_623 : node _T_624 = shl(UInt<3>(0h4), 3) node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624) node _T_626 = bits(_T_625, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_626 node _T_627 = eq(UInt<5>(0h19), idx_4) when _T_627 : node _T_628 = shl(UInt<3>(0h4), 3) node _T_629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_628) node _T_630 = bits(_T_629, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_630 node _T_631 = eq(UInt<5>(0h1a), idx_4) when _T_631 : node _T_632 = shl(UInt<3>(0h4), 3) node _T_633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_632) node _T_634 = bits(_T_633, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_634 node _T_635 = eq(UInt<5>(0h1b), idx_4) when _T_635 : node _T_636 = shl(UInt<3>(0h4), 3) node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636) node _T_638 = bits(_T_637, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_638 node _T_639 = eq(UInt<5>(0h1c), idx_4) when _T_639 : node _T_640 = shl(UInt<3>(0h4), 3) node _T_641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_640) node _T_642 = bits(_T_641, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_642 node _T_643 = eq(UInt<5>(0h1d), idx_4) when _T_643 : node _T_644 = shl(UInt<3>(0h4), 3) node _T_645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_644) node _T_646 = bits(_T_645, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_646 node _T_647 = eq(UInt<5>(0h1e), idx_4) when _T_647 : node _T_648 = shl(UInt<3>(0h4), 3) node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648) node _T_650 = bits(_T_649, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_650 node _T_651 = eq(UInt<5>(0h1f), idx_4) when _T_651 : node _T_652 = shl(UInt<3>(0h4), 3) node _T_653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_652) node _T_654 = bits(_T_653, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_654 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_655 = eq(UInt<1>(0h0), idx_5) when _T_655 : node _T_656 = shl(UInt<3>(0h5), 3) node _T_657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_656) node _T_658 = bits(_T_657, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_658 node _T_659 = eq(UInt<1>(0h1), idx_5) when _T_659 : node _T_660 = shl(UInt<3>(0h5), 3) node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660) node _T_662 = bits(_T_661, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_662 node _T_663 = eq(UInt<2>(0h2), idx_5) when _T_663 : node _T_664 = shl(UInt<3>(0h5), 3) node _T_665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_664) node _T_666 = bits(_T_665, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_666 node _T_667 = eq(UInt<2>(0h3), idx_5) when _T_667 : node _T_668 = shl(UInt<3>(0h5), 3) node _T_669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_668) node _T_670 = bits(_T_669, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_670 node _T_671 = eq(UInt<3>(0h4), idx_5) when _T_671 : node _T_672 = shl(UInt<3>(0h5), 3) node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672) node _T_674 = bits(_T_673, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_674 node _T_675 = eq(UInt<3>(0h5), idx_5) when _T_675 : node _T_676 = shl(UInt<3>(0h5), 3) node _T_677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_676) node _T_678 = bits(_T_677, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_678 node _T_679 = eq(UInt<3>(0h6), idx_5) when _T_679 : node _T_680 = shl(UInt<3>(0h5), 3) node _T_681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_680) node _T_682 = bits(_T_681, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_682 node _T_683 = eq(UInt<3>(0h7), idx_5) when _T_683 : node _T_684 = shl(UInt<3>(0h5), 3) node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684) node _T_686 = bits(_T_685, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_686 node _T_687 = eq(UInt<4>(0h8), idx_5) when _T_687 : node _T_688 = shl(UInt<3>(0h5), 3) node _T_689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_688) node _T_690 = bits(_T_689, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_690 node _T_691 = eq(UInt<4>(0h9), idx_5) when _T_691 : node _T_692 = shl(UInt<3>(0h5), 3) node _T_693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_692) node _T_694 = bits(_T_693, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_694 node _T_695 = eq(UInt<4>(0ha), idx_5) when _T_695 : node _T_696 = shl(UInt<3>(0h5), 3) node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696) node _T_698 = bits(_T_697, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_698 node _T_699 = eq(UInt<4>(0hb), idx_5) when _T_699 : node _T_700 = shl(UInt<3>(0h5), 3) node _T_701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_700) node _T_702 = bits(_T_701, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_702 node _T_703 = eq(UInt<4>(0hc), idx_5) when _T_703 : node _T_704 = shl(UInt<3>(0h5), 3) node _T_705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_704) node _T_706 = bits(_T_705, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_706 node _T_707 = eq(UInt<4>(0hd), idx_5) when _T_707 : node _T_708 = shl(UInt<3>(0h5), 3) node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708) node _T_710 = bits(_T_709, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_710 node _T_711 = eq(UInt<4>(0he), idx_5) when _T_711 : node _T_712 = shl(UInt<3>(0h5), 3) node _T_713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_712) node _T_714 = bits(_T_713, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_714 node _T_715 = eq(UInt<4>(0hf), idx_5) when _T_715 : node _T_716 = shl(UInt<3>(0h5), 3) node _T_717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_716) node _T_718 = bits(_T_717, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_718 node _T_719 = eq(UInt<5>(0h10), idx_5) when _T_719 : node _T_720 = shl(UInt<3>(0h5), 3) node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720) node _T_722 = bits(_T_721, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_722 node _T_723 = eq(UInt<5>(0h11), idx_5) when _T_723 : node _T_724 = shl(UInt<3>(0h5), 3) node _T_725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_724) node _T_726 = bits(_T_725, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_726 node _T_727 = eq(UInt<5>(0h12), idx_5) when _T_727 : node _T_728 = shl(UInt<3>(0h5), 3) node _T_729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_728) node _T_730 = bits(_T_729, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_730 node _T_731 = eq(UInt<5>(0h13), idx_5) when _T_731 : node _T_732 = shl(UInt<3>(0h5), 3) node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732) node _T_734 = bits(_T_733, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_734 node _T_735 = eq(UInt<5>(0h14), idx_5) when _T_735 : node _T_736 = shl(UInt<3>(0h5), 3) node _T_737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_736) node _T_738 = bits(_T_737, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_738 node _T_739 = eq(UInt<5>(0h15), idx_5) when _T_739 : node _T_740 = shl(UInt<3>(0h5), 3) node _T_741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_740) node _T_742 = bits(_T_741, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_742 node _T_743 = eq(UInt<5>(0h16), idx_5) when _T_743 : node _T_744 = shl(UInt<3>(0h5), 3) node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744) node _T_746 = bits(_T_745, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_746 node _T_747 = eq(UInt<5>(0h17), idx_5) when _T_747 : node _T_748 = shl(UInt<3>(0h5), 3) node _T_749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_748) node _T_750 = bits(_T_749, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_750 node _T_751 = eq(UInt<5>(0h18), idx_5) when _T_751 : node _T_752 = shl(UInt<3>(0h5), 3) node _T_753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_752) node _T_754 = bits(_T_753, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_754 node _T_755 = eq(UInt<5>(0h19), idx_5) when _T_755 : node _T_756 = shl(UInt<3>(0h5), 3) node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756) node _T_758 = bits(_T_757, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_758 node _T_759 = eq(UInt<5>(0h1a), idx_5) when _T_759 : node _T_760 = shl(UInt<3>(0h5), 3) node _T_761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_760) node _T_762 = bits(_T_761, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_762 node _T_763 = eq(UInt<5>(0h1b), idx_5) when _T_763 : node _T_764 = shl(UInt<3>(0h5), 3) node _T_765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_764) node _T_766 = bits(_T_765, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_766 node _T_767 = eq(UInt<5>(0h1c), idx_5) when _T_767 : node _T_768 = shl(UInt<3>(0h5), 3) node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768) node _T_770 = bits(_T_769, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_770 node _T_771 = eq(UInt<5>(0h1d), idx_5) when _T_771 : node _T_772 = shl(UInt<3>(0h5), 3) node _T_773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_772) node _T_774 = bits(_T_773, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_774 node _T_775 = eq(UInt<5>(0h1e), idx_5) when _T_775 : node _T_776 = shl(UInt<3>(0h5), 3) node _T_777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_776) node _T_778 = bits(_T_777, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_778 node _T_779 = eq(UInt<5>(0h1f), idx_5) when _T_779 : node _T_780 = shl(UInt<3>(0h5), 3) node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780) node _T_782 = bits(_T_781, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_782 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_783 = eq(UInt<1>(0h0), idx_6) when _T_783 : node _T_784 = shl(UInt<3>(0h6), 3) node _T_785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_784) node _T_786 = bits(_T_785, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_786 node _T_787 = eq(UInt<1>(0h1), idx_6) when _T_787 : node _T_788 = shl(UInt<3>(0h6), 3) node _T_789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_788) node _T_790 = bits(_T_789, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_790 node _T_791 = eq(UInt<2>(0h2), idx_6) when _T_791 : node _T_792 = shl(UInt<3>(0h6), 3) node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792) node _T_794 = bits(_T_793, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_794 node _T_795 = eq(UInt<2>(0h3), idx_6) when _T_795 : node _T_796 = shl(UInt<3>(0h6), 3) node _T_797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_796) node _T_798 = bits(_T_797, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_798 node _T_799 = eq(UInt<3>(0h4), idx_6) when _T_799 : node _T_800 = shl(UInt<3>(0h6), 3) node _T_801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_800) node _T_802 = bits(_T_801, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_802 node _T_803 = eq(UInt<3>(0h5), idx_6) when _T_803 : node _T_804 = shl(UInt<3>(0h6), 3) node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804) node _T_806 = bits(_T_805, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_806 node _T_807 = eq(UInt<3>(0h6), idx_6) when _T_807 : node _T_808 = shl(UInt<3>(0h6), 3) node _T_809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_808) node _T_810 = bits(_T_809, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_810 node _T_811 = eq(UInt<3>(0h7), idx_6) when _T_811 : node _T_812 = shl(UInt<3>(0h6), 3) node _T_813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_812) node _T_814 = bits(_T_813, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_814 node _T_815 = eq(UInt<4>(0h8), idx_6) when _T_815 : node _T_816 = shl(UInt<3>(0h6), 3) node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816) node _T_818 = bits(_T_817, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_818 node _T_819 = eq(UInt<4>(0h9), idx_6) when _T_819 : node _T_820 = shl(UInt<3>(0h6), 3) node _T_821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_820) node _T_822 = bits(_T_821, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_822 node _T_823 = eq(UInt<4>(0ha), idx_6) when _T_823 : node _T_824 = shl(UInt<3>(0h6), 3) node _T_825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_824) node _T_826 = bits(_T_825, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_826 node _T_827 = eq(UInt<4>(0hb), idx_6) when _T_827 : node _T_828 = shl(UInt<3>(0h6), 3) node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828) node _T_830 = bits(_T_829, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_830 node _T_831 = eq(UInt<4>(0hc), idx_6) when _T_831 : node _T_832 = shl(UInt<3>(0h6), 3) node _T_833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_832) node _T_834 = bits(_T_833, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_834 node _T_835 = eq(UInt<4>(0hd), idx_6) when _T_835 : node _T_836 = shl(UInt<3>(0h6), 3) node _T_837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_836) node _T_838 = bits(_T_837, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_838 node _T_839 = eq(UInt<4>(0he), idx_6) when _T_839 : node _T_840 = shl(UInt<3>(0h6), 3) node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840) node _T_842 = bits(_T_841, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_842 node _T_843 = eq(UInt<4>(0hf), idx_6) when _T_843 : node _T_844 = shl(UInt<3>(0h6), 3) node _T_845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_844) node _T_846 = bits(_T_845, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_846 node _T_847 = eq(UInt<5>(0h10), idx_6) when _T_847 : node _T_848 = shl(UInt<3>(0h6), 3) node _T_849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_848) node _T_850 = bits(_T_849, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_850 node _T_851 = eq(UInt<5>(0h11), idx_6) when _T_851 : node _T_852 = shl(UInt<3>(0h6), 3) node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852) node _T_854 = bits(_T_853, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_854 node _T_855 = eq(UInt<5>(0h12), idx_6) when _T_855 : node _T_856 = shl(UInt<3>(0h6), 3) node _T_857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_856) node _T_858 = bits(_T_857, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_858 node _T_859 = eq(UInt<5>(0h13), idx_6) when _T_859 : node _T_860 = shl(UInt<3>(0h6), 3) node _T_861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_860) node _T_862 = bits(_T_861, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_862 node _T_863 = eq(UInt<5>(0h14), idx_6) when _T_863 : node _T_864 = shl(UInt<3>(0h6), 3) node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864) node _T_866 = bits(_T_865, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_866 node _T_867 = eq(UInt<5>(0h15), idx_6) when _T_867 : node _T_868 = shl(UInt<3>(0h6), 3) node _T_869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_868) node _T_870 = bits(_T_869, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_870 node _T_871 = eq(UInt<5>(0h16), idx_6) when _T_871 : node _T_872 = shl(UInt<3>(0h6), 3) node _T_873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_872) node _T_874 = bits(_T_873, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_874 node _T_875 = eq(UInt<5>(0h17), idx_6) when _T_875 : node _T_876 = shl(UInt<3>(0h6), 3) node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876) node _T_878 = bits(_T_877, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_878 node _T_879 = eq(UInt<5>(0h18), idx_6) when _T_879 : node _T_880 = shl(UInt<3>(0h6), 3) node _T_881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_880) node _T_882 = bits(_T_881, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_882 node _T_883 = eq(UInt<5>(0h19), idx_6) when _T_883 : node _T_884 = shl(UInt<3>(0h6), 3) node _T_885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_884) node _T_886 = bits(_T_885, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_886 node _T_887 = eq(UInt<5>(0h1a), idx_6) when _T_887 : node _T_888 = shl(UInt<3>(0h6), 3) node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888) node _T_890 = bits(_T_889, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_890 node _T_891 = eq(UInt<5>(0h1b), idx_6) when _T_891 : node _T_892 = shl(UInt<3>(0h6), 3) node _T_893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_892) node _T_894 = bits(_T_893, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_894 node _T_895 = eq(UInt<5>(0h1c), idx_6) when _T_895 : node _T_896 = shl(UInt<3>(0h6), 3) node _T_897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_896) node _T_898 = bits(_T_897, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_898 node _T_899 = eq(UInt<5>(0h1d), idx_6) when _T_899 : node _T_900 = shl(UInt<3>(0h6), 3) node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900) node _T_902 = bits(_T_901, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_902 node _T_903 = eq(UInt<5>(0h1e), idx_6) when _T_903 : node _T_904 = shl(UInt<3>(0h6), 3) node _T_905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_904) node _T_906 = bits(_T_905, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_906 node _T_907 = eq(UInt<5>(0h1f), idx_6) when _T_907 : node _T_908 = shl(UInt<3>(0h6), 3) node _T_909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_908) node _T_910 = bits(_T_909, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_910 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_911 = eq(UInt<1>(0h0), idx_7) when _T_911 : node _T_912 = shl(UInt<3>(0h7), 3) node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912) node _T_914 = bits(_T_913, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_914 node _T_915 = eq(UInt<1>(0h1), idx_7) when _T_915 : node _T_916 = shl(UInt<3>(0h7), 3) node _T_917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_916) node _T_918 = bits(_T_917, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_918 node _T_919 = eq(UInt<2>(0h2), idx_7) when _T_919 : node _T_920 = shl(UInt<3>(0h7), 3) node _T_921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_920) node _T_922 = bits(_T_921, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_922 node _T_923 = eq(UInt<2>(0h3), idx_7) when _T_923 : node _T_924 = shl(UInt<3>(0h7), 3) node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924) node _T_926 = bits(_T_925, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_926 node _T_927 = eq(UInt<3>(0h4), idx_7) when _T_927 : node _T_928 = shl(UInt<3>(0h7), 3) node _T_929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_928) node _T_930 = bits(_T_929, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_930 node _T_931 = eq(UInt<3>(0h5), idx_7) when _T_931 : node _T_932 = shl(UInt<3>(0h7), 3) node _T_933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_932) node _T_934 = bits(_T_933, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_934 node _T_935 = eq(UInt<3>(0h6), idx_7) when _T_935 : node _T_936 = shl(UInt<3>(0h7), 3) node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936) node _T_938 = bits(_T_937, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_938 node _T_939 = eq(UInt<3>(0h7), idx_7) when _T_939 : node _T_940 = shl(UInt<3>(0h7), 3) node _T_941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_940) node _T_942 = bits(_T_941, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_942 node _T_943 = eq(UInt<4>(0h8), idx_7) when _T_943 : node _T_944 = shl(UInt<3>(0h7), 3) node _T_945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_944) node _T_946 = bits(_T_945, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_946 node _T_947 = eq(UInt<4>(0h9), idx_7) when _T_947 : node _T_948 = shl(UInt<3>(0h7), 3) node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948) node _T_950 = bits(_T_949, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_950 node _T_951 = eq(UInt<4>(0ha), idx_7) when _T_951 : node _T_952 = shl(UInt<3>(0h7), 3) node _T_953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_952) node _T_954 = bits(_T_953, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_954 node _T_955 = eq(UInt<4>(0hb), idx_7) when _T_955 : node _T_956 = shl(UInt<3>(0h7), 3) node _T_957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_956) node _T_958 = bits(_T_957, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_958 node _T_959 = eq(UInt<4>(0hc), idx_7) when _T_959 : node _T_960 = shl(UInt<3>(0h7), 3) node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960) node _T_962 = bits(_T_961, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_962 node _T_963 = eq(UInt<4>(0hd), idx_7) when _T_963 : node _T_964 = shl(UInt<3>(0h7), 3) node _T_965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_964) node _T_966 = bits(_T_965, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_966 node _T_967 = eq(UInt<4>(0he), idx_7) when _T_967 : node _T_968 = shl(UInt<3>(0h7), 3) node _T_969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_968) node _T_970 = bits(_T_969, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_970 node _T_971 = eq(UInt<4>(0hf), idx_7) when _T_971 : node _T_972 = shl(UInt<3>(0h7), 3) node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972) node _T_974 = bits(_T_973, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_974 node _T_975 = eq(UInt<5>(0h10), idx_7) when _T_975 : node _T_976 = shl(UInt<3>(0h7), 3) node _T_977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_976) node _T_978 = bits(_T_977, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_978 node _T_979 = eq(UInt<5>(0h11), idx_7) when _T_979 : node _T_980 = shl(UInt<3>(0h7), 3) node _T_981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_980) node _T_982 = bits(_T_981, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_982 node _T_983 = eq(UInt<5>(0h12), idx_7) when _T_983 : node _T_984 = shl(UInt<3>(0h7), 3) node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984) node _T_986 = bits(_T_985, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_986 node _T_987 = eq(UInt<5>(0h13), idx_7) when _T_987 : node _T_988 = shl(UInt<3>(0h7), 3) node _T_989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_988) node _T_990 = bits(_T_989, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_990 node _T_991 = eq(UInt<5>(0h14), idx_7) when _T_991 : node _T_992 = shl(UInt<3>(0h7), 3) node _T_993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_992) node _T_994 = bits(_T_993, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_994 node _T_995 = eq(UInt<5>(0h15), idx_7) when _T_995 : node _T_996 = shl(UInt<3>(0h7), 3) node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996) node _T_998 = bits(_T_997, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_998 node _T_999 = eq(UInt<5>(0h16), idx_7) when _T_999 : node _T_1000 = shl(UInt<3>(0h7), 3) node _T_1001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1000) node _T_1002 = bits(_T_1001, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1002 node _T_1003 = eq(UInt<5>(0h17), idx_7) when _T_1003 : node _T_1004 = shl(UInt<3>(0h7), 3) node _T_1005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1004) node _T_1006 = bits(_T_1005, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1006 node _T_1007 = eq(UInt<5>(0h18), idx_7) when _T_1007 : node _T_1008 = shl(UInt<3>(0h7), 3) node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008) node _T_1010 = bits(_T_1009, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1010 node _T_1011 = eq(UInt<5>(0h19), idx_7) when _T_1011 : node _T_1012 = shl(UInt<3>(0h7), 3) node _T_1013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1012) node _T_1014 = bits(_T_1013, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1014 node _T_1015 = eq(UInt<5>(0h1a), idx_7) when _T_1015 : node _T_1016 = shl(UInt<3>(0h7), 3) node _T_1017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1016) node _T_1018 = bits(_T_1017, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1018 node _T_1019 = eq(UInt<5>(0h1b), idx_7) when _T_1019 : node _T_1020 = shl(UInt<3>(0h7), 3) node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020) node _T_1022 = bits(_T_1021, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1022 node _T_1023 = eq(UInt<5>(0h1c), idx_7) when _T_1023 : node _T_1024 = shl(UInt<3>(0h7), 3) node _T_1025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1024) node _T_1026 = bits(_T_1025, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1026 node _T_1027 = eq(UInt<5>(0h1d), idx_7) when _T_1027 : node _T_1028 = shl(UInt<3>(0h7), 3) node _T_1029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1028) node _T_1030 = bits(_T_1029, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1030 node _T_1031 = eq(UInt<5>(0h1e), idx_7) when _T_1031 : node _T_1032 = shl(UInt<3>(0h7), 3) node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032) node _T_1034 = bits(_T_1033, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1034 node _T_1035 = eq(UInt<5>(0h1f), idx_7) when _T_1035 : node _T_1036 = shl(UInt<3>(0h7), 3) node _T_1037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1036) node _T_1038 = bits(_T_1037, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1038 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_1039 = eq(UInt<1>(0h0), idx_8) when _T_1039 : node _T_1040 = shl(UInt<4>(0h8), 3) node _T_1041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1040) node _T_1042 = bits(_T_1041, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1042 node _T_1043 = eq(UInt<1>(0h1), idx_8) when _T_1043 : node _T_1044 = shl(UInt<4>(0h8), 3) node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044) node _T_1046 = bits(_T_1045, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1046 node _T_1047 = eq(UInt<2>(0h2), idx_8) when _T_1047 : node _T_1048 = shl(UInt<4>(0h8), 3) node _T_1049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1048) node _T_1050 = bits(_T_1049, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1050 node _T_1051 = eq(UInt<2>(0h3), idx_8) when _T_1051 : node _T_1052 = shl(UInt<4>(0h8), 3) node _T_1053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1052) node _T_1054 = bits(_T_1053, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1054 node _T_1055 = eq(UInt<3>(0h4), idx_8) when _T_1055 : node _T_1056 = shl(UInt<4>(0h8), 3) node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056) node _T_1058 = bits(_T_1057, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1058 node _T_1059 = eq(UInt<3>(0h5), idx_8) when _T_1059 : node _T_1060 = shl(UInt<4>(0h8), 3) node _T_1061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1060) node _T_1062 = bits(_T_1061, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1062 node _T_1063 = eq(UInt<3>(0h6), idx_8) when _T_1063 : node _T_1064 = shl(UInt<4>(0h8), 3) node _T_1065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1064) node _T_1066 = bits(_T_1065, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1066 node _T_1067 = eq(UInt<3>(0h7), idx_8) when _T_1067 : node _T_1068 = shl(UInt<4>(0h8), 3) node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068) node _T_1070 = bits(_T_1069, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1070 node _T_1071 = eq(UInt<4>(0h8), idx_8) when _T_1071 : node _T_1072 = shl(UInt<4>(0h8), 3) node _T_1073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1072) node _T_1074 = bits(_T_1073, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1074 node _T_1075 = eq(UInt<4>(0h9), idx_8) when _T_1075 : node _T_1076 = shl(UInt<4>(0h8), 3) node _T_1077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1076) node _T_1078 = bits(_T_1077, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1078 node _T_1079 = eq(UInt<4>(0ha), idx_8) when _T_1079 : node _T_1080 = shl(UInt<4>(0h8), 3) node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080) node _T_1082 = bits(_T_1081, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1082 node _T_1083 = eq(UInt<4>(0hb), idx_8) when _T_1083 : node _T_1084 = shl(UInt<4>(0h8), 3) node _T_1085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1084) node _T_1086 = bits(_T_1085, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1086 node _T_1087 = eq(UInt<4>(0hc), idx_8) when _T_1087 : node _T_1088 = shl(UInt<4>(0h8), 3) node _T_1089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1088) node _T_1090 = bits(_T_1089, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1090 node _T_1091 = eq(UInt<4>(0hd), idx_8) when _T_1091 : node _T_1092 = shl(UInt<4>(0h8), 3) node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092) node _T_1094 = bits(_T_1093, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1094 node _T_1095 = eq(UInt<4>(0he), idx_8) when _T_1095 : node _T_1096 = shl(UInt<4>(0h8), 3) node _T_1097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1096) node _T_1098 = bits(_T_1097, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1098 node _T_1099 = eq(UInt<4>(0hf), idx_8) when _T_1099 : node _T_1100 = shl(UInt<4>(0h8), 3) node _T_1101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1100) node _T_1102 = bits(_T_1101, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1102 node _T_1103 = eq(UInt<5>(0h10), idx_8) when _T_1103 : node _T_1104 = shl(UInt<4>(0h8), 3) node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104) node _T_1106 = bits(_T_1105, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1106 node _T_1107 = eq(UInt<5>(0h11), idx_8) when _T_1107 : node _T_1108 = shl(UInt<4>(0h8), 3) node _T_1109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1108) node _T_1110 = bits(_T_1109, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1110 node _T_1111 = eq(UInt<5>(0h12), idx_8) when _T_1111 : node _T_1112 = shl(UInt<4>(0h8), 3) node _T_1113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1112) node _T_1114 = bits(_T_1113, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1114 node _T_1115 = eq(UInt<5>(0h13), idx_8) when _T_1115 : node _T_1116 = shl(UInt<4>(0h8), 3) node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116) node _T_1118 = bits(_T_1117, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1118 node _T_1119 = eq(UInt<5>(0h14), idx_8) when _T_1119 : node _T_1120 = shl(UInt<4>(0h8), 3) node _T_1121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1120) node _T_1122 = bits(_T_1121, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1122 node _T_1123 = eq(UInt<5>(0h15), idx_8) when _T_1123 : node _T_1124 = shl(UInt<4>(0h8), 3) node _T_1125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1124) node _T_1126 = bits(_T_1125, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1126 node _T_1127 = eq(UInt<5>(0h16), idx_8) when _T_1127 : node _T_1128 = shl(UInt<4>(0h8), 3) node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128) node _T_1130 = bits(_T_1129, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1130 node _T_1131 = eq(UInt<5>(0h17), idx_8) when _T_1131 : node _T_1132 = shl(UInt<4>(0h8), 3) node _T_1133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1132) node _T_1134 = bits(_T_1133, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1134 node _T_1135 = eq(UInt<5>(0h18), idx_8) when _T_1135 : node _T_1136 = shl(UInt<4>(0h8), 3) node _T_1137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1136) node _T_1138 = bits(_T_1137, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1138 node _T_1139 = eq(UInt<5>(0h19), idx_8) when _T_1139 : node _T_1140 = shl(UInt<4>(0h8), 3) node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140) node _T_1142 = bits(_T_1141, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1142 node _T_1143 = eq(UInt<5>(0h1a), idx_8) when _T_1143 : node _T_1144 = shl(UInt<4>(0h8), 3) node _T_1145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1144) node _T_1146 = bits(_T_1145, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1146 node _T_1147 = eq(UInt<5>(0h1b), idx_8) when _T_1147 : node _T_1148 = shl(UInt<4>(0h8), 3) node _T_1149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1148) node _T_1150 = bits(_T_1149, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1150 node _T_1151 = eq(UInt<5>(0h1c), idx_8) when _T_1151 : node _T_1152 = shl(UInt<4>(0h8), 3) node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152) node _T_1154 = bits(_T_1153, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1154 node _T_1155 = eq(UInt<5>(0h1d), idx_8) when _T_1155 : node _T_1156 = shl(UInt<4>(0h8), 3) node _T_1157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1156) node _T_1158 = bits(_T_1157, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1158 node _T_1159 = eq(UInt<5>(0h1e), idx_8) when _T_1159 : node _T_1160 = shl(UInt<4>(0h8), 3) node _T_1161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1160) node _T_1162 = bits(_T_1161, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1162 node _T_1163 = eq(UInt<5>(0h1f), idx_8) when _T_1163 : node _T_1164 = shl(UInt<4>(0h8), 3) node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164) node _T_1166 = bits(_T_1165, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1166 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_1167 = eq(UInt<1>(0h0), idx_9) when _T_1167 : node _T_1168 = shl(UInt<4>(0h9), 3) node _T_1169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1168) node _T_1170 = bits(_T_1169, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1170 node _T_1171 = eq(UInt<1>(0h1), idx_9) when _T_1171 : node _T_1172 = shl(UInt<4>(0h9), 3) node _T_1173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1172) node _T_1174 = bits(_T_1173, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1174 node _T_1175 = eq(UInt<2>(0h2), idx_9) when _T_1175 : node _T_1176 = shl(UInt<4>(0h9), 3) node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176) node _T_1178 = bits(_T_1177, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1178 node _T_1179 = eq(UInt<2>(0h3), idx_9) when _T_1179 : node _T_1180 = shl(UInt<4>(0h9), 3) node _T_1181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1180) node _T_1182 = bits(_T_1181, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1182 node _T_1183 = eq(UInt<3>(0h4), idx_9) when _T_1183 : node _T_1184 = shl(UInt<4>(0h9), 3) node _T_1185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1184) node _T_1186 = bits(_T_1185, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1186 node _T_1187 = eq(UInt<3>(0h5), idx_9) when _T_1187 : node _T_1188 = shl(UInt<4>(0h9), 3) node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188) node _T_1190 = bits(_T_1189, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1190 node _T_1191 = eq(UInt<3>(0h6), idx_9) when _T_1191 : node _T_1192 = shl(UInt<4>(0h9), 3) node _T_1193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1192) node _T_1194 = bits(_T_1193, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1194 node _T_1195 = eq(UInt<3>(0h7), idx_9) when _T_1195 : node _T_1196 = shl(UInt<4>(0h9), 3) node _T_1197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1196) node _T_1198 = bits(_T_1197, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1198 node _T_1199 = eq(UInt<4>(0h8), idx_9) when _T_1199 : node _T_1200 = shl(UInt<4>(0h9), 3) node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200) node _T_1202 = bits(_T_1201, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1202 node _T_1203 = eq(UInt<4>(0h9), idx_9) when _T_1203 : node _T_1204 = shl(UInt<4>(0h9), 3) node _T_1205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1204) node _T_1206 = bits(_T_1205, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1206 node _T_1207 = eq(UInt<4>(0ha), idx_9) when _T_1207 : node _T_1208 = shl(UInt<4>(0h9), 3) node _T_1209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1208) node _T_1210 = bits(_T_1209, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1210 node _T_1211 = eq(UInt<4>(0hb), idx_9) when _T_1211 : node _T_1212 = shl(UInt<4>(0h9), 3) node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212) node _T_1214 = bits(_T_1213, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1214 node _T_1215 = eq(UInt<4>(0hc), idx_9) when _T_1215 : node _T_1216 = shl(UInt<4>(0h9), 3) node _T_1217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1216) node _T_1218 = bits(_T_1217, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1218 node _T_1219 = eq(UInt<4>(0hd), idx_9) when _T_1219 : node _T_1220 = shl(UInt<4>(0h9), 3) node _T_1221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1220) node _T_1222 = bits(_T_1221, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1222 node _T_1223 = eq(UInt<4>(0he), idx_9) when _T_1223 : node _T_1224 = shl(UInt<4>(0h9), 3) node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224) node _T_1226 = bits(_T_1225, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1226 node _T_1227 = eq(UInt<4>(0hf), idx_9) when _T_1227 : node _T_1228 = shl(UInt<4>(0h9), 3) node _T_1229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1228) node _T_1230 = bits(_T_1229, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1230 node _T_1231 = eq(UInt<5>(0h10), idx_9) when _T_1231 : node _T_1232 = shl(UInt<4>(0h9), 3) node _T_1233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1232) node _T_1234 = bits(_T_1233, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1234 node _T_1235 = eq(UInt<5>(0h11), idx_9) when _T_1235 : node _T_1236 = shl(UInt<4>(0h9), 3) node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236) node _T_1238 = bits(_T_1237, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1238 node _T_1239 = eq(UInt<5>(0h12), idx_9) when _T_1239 : node _T_1240 = shl(UInt<4>(0h9), 3) node _T_1241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1240) node _T_1242 = bits(_T_1241, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1242 node _T_1243 = eq(UInt<5>(0h13), idx_9) when _T_1243 : node _T_1244 = shl(UInt<4>(0h9), 3) node _T_1245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1244) node _T_1246 = bits(_T_1245, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1246 node _T_1247 = eq(UInt<5>(0h14), idx_9) when _T_1247 : node _T_1248 = shl(UInt<4>(0h9), 3) node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248) node _T_1250 = bits(_T_1249, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1250 node _T_1251 = eq(UInt<5>(0h15), idx_9) when _T_1251 : node _T_1252 = shl(UInt<4>(0h9), 3) node _T_1253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1252) node _T_1254 = bits(_T_1253, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1254 node _T_1255 = eq(UInt<5>(0h16), idx_9) when _T_1255 : node _T_1256 = shl(UInt<4>(0h9), 3) node _T_1257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1256) node _T_1258 = bits(_T_1257, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1258 node _T_1259 = eq(UInt<5>(0h17), idx_9) when _T_1259 : node _T_1260 = shl(UInt<4>(0h9), 3) node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260) node _T_1262 = bits(_T_1261, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1262 node _T_1263 = eq(UInt<5>(0h18), idx_9) when _T_1263 : node _T_1264 = shl(UInt<4>(0h9), 3) node _T_1265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1264) node _T_1266 = bits(_T_1265, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1266 node _T_1267 = eq(UInt<5>(0h19), idx_9) when _T_1267 : node _T_1268 = shl(UInt<4>(0h9), 3) node _T_1269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1268) node _T_1270 = bits(_T_1269, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1270 node _T_1271 = eq(UInt<5>(0h1a), idx_9) when _T_1271 : node _T_1272 = shl(UInt<4>(0h9), 3) node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272) node _T_1274 = bits(_T_1273, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1274 node _T_1275 = eq(UInt<5>(0h1b), idx_9) when _T_1275 : node _T_1276 = shl(UInt<4>(0h9), 3) node _T_1277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1276) node _T_1278 = bits(_T_1277, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1278 node _T_1279 = eq(UInt<5>(0h1c), idx_9) when _T_1279 : node _T_1280 = shl(UInt<4>(0h9), 3) node _T_1281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1280) node _T_1282 = bits(_T_1281, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1282 node _T_1283 = eq(UInt<5>(0h1d), idx_9) when _T_1283 : node _T_1284 = shl(UInt<4>(0h9), 3) node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284) node _T_1286 = bits(_T_1285, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1286 node _T_1287 = eq(UInt<5>(0h1e), idx_9) when _T_1287 : node _T_1288 = shl(UInt<4>(0h9), 3) node _T_1289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1288) node _T_1290 = bits(_T_1289, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1290 node _T_1291 = eq(UInt<5>(0h1f), idx_9) when _T_1291 : node _T_1292 = shl(UInt<4>(0h9), 3) node _T_1293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1292) node _T_1294 = bits(_T_1293, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1294 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_1295 = eq(UInt<1>(0h0), idx_10) when _T_1295 : node _T_1296 = shl(UInt<4>(0ha), 3) node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296) node _T_1298 = bits(_T_1297, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1298 node _T_1299 = eq(UInt<1>(0h1), idx_10) when _T_1299 : node _T_1300 = shl(UInt<4>(0ha), 3) node _T_1301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1300) node _T_1302 = bits(_T_1301, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1302 node _T_1303 = eq(UInt<2>(0h2), idx_10) when _T_1303 : node _T_1304 = shl(UInt<4>(0ha), 3) node _T_1305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1304) node _T_1306 = bits(_T_1305, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1306 node _T_1307 = eq(UInt<2>(0h3), idx_10) when _T_1307 : node _T_1308 = shl(UInt<4>(0ha), 3) node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308) node _T_1310 = bits(_T_1309, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1310 node _T_1311 = eq(UInt<3>(0h4), idx_10) when _T_1311 : node _T_1312 = shl(UInt<4>(0ha), 3) node _T_1313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1312) node _T_1314 = bits(_T_1313, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1314 node _T_1315 = eq(UInt<3>(0h5), idx_10) when _T_1315 : node _T_1316 = shl(UInt<4>(0ha), 3) node _T_1317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1316) node _T_1318 = bits(_T_1317, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1318 node _T_1319 = eq(UInt<3>(0h6), idx_10) when _T_1319 : node _T_1320 = shl(UInt<4>(0ha), 3) node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320) node _T_1322 = bits(_T_1321, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1322 node _T_1323 = eq(UInt<3>(0h7), idx_10) when _T_1323 : node _T_1324 = shl(UInt<4>(0ha), 3) node _T_1325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1324) node _T_1326 = bits(_T_1325, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1326 node _T_1327 = eq(UInt<4>(0h8), idx_10) when _T_1327 : node _T_1328 = shl(UInt<4>(0ha), 3) node _T_1329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1328) node _T_1330 = bits(_T_1329, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1330 node _T_1331 = eq(UInt<4>(0h9), idx_10) when _T_1331 : node _T_1332 = shl(UInt<4>(0ha), 3) node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332) node _T_1334 = bits(_T_1333, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1334 node _T_1335 = eq(UInt<4>(0ha), idx_10) when _T_1335 : node _T_1336 = shl(UInt<4>(0ha), 3) node _T_1337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1336) node _T_1338 = bits(_T_1337, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1338 node _T_1339 = eq(UInt<4>(0hb), idx_10) when _T_1339 : node _T_1340 = shl(UInt<4>(0ha), 3) node _T_1341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1340) node _T_1342 = bits(_T_1341, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1342 node _T_1343 = eq(UInt<4>(0hc), idx_10) when _T_1343 : node _T_1344 = shl(UInt<4>(0ha), 3) node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344) node _T_1346 = bits(_T_1345, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1346 node _T_1347 = eq(UInt<4>(0hd), idx_10) when _T_1347 : node _T_1348 = shl(UInt<4>(0ha), 3) node _T_1349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1348) node _T_1350 = bits(_T_1349, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1350 node _T_1351 = eq(UInt<4>(0he), idx_10) when _T_1351 : node _T_1352 = shl(UInt<4>(0ha), 3) node _T_1353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1352) node _T_1354 = bits(_T_1353, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1354 node _T_1355 = eq(UInt<4>(0hf), idx_10) when _T_1355 : node _T_1356 = shl(UInt<4>(0ha), 3) node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356) node _T_1358 = bits(_T_1357, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1358 node _T_1359 = eq(UInt<5>(0h10), idx_10) when _T_1359 : node _T_1360 = shl(UInt<4>(0ha), 3) node _T_1361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1360) node _T_1362 = bits(_T_1361, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1362 node _T_1363 = eq(UInt<5>(0h11), idx_10) when _T_1363 : node _T_1364 = shl(UInt<4>(0ha), 3) node _T_1365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1364) node _T_1366 = bits(_T_1365, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1366 node _T_1367 = eq(UInt<5>(0h12), idx_10) when _T_1367 : node _T_1368 = shl(UInt<4>(0ha), 3) node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368) node _T_1370 = bits(_T_1369, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1370 node _T_1371 = eq(UInt<5>(0h13), idx_10) when _T_1371 : node _T_1372 = shl(UInt<4>(0ha), 3) node _T_1373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1372) node _T_1374 = bits(_T_1373, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1374 node _T_1375 = eq(UInt<5>(0h14), idx_10) when _T_1375 : node _T_1376 = shl(UInt<4>(0ha), 3) node _T_1377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1376) node _T_1378 = bits(_T_1377, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1378 node _T_1379 = eq(UInt<5>(0h15), idx_10) when _T_1379 : node _T_1380 = shl(UInt<4>(0ha), 3) node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380) node _T_1382 = bits(_T_1381, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1382 node _T_1383 = eq(UInt<5>(0h16), idx_10) when _T_1383 : node _T_1384 = shl(UInt<4>(0ha), 3) node _T_1385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1384) node _T_1386 = bits(_T_1385, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1386 node _T_1387 = eq(UInt<5>(0h17), idx_10) when _T_1387 : node _T_1388 = shl(UInt<4>(0ha), 3) node _T_1389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1388) node _T_1390 = bits(_T_1389, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1390 node _T_1391 = eq(UInt<5>(0h18), idx_10) when _T_1391 : node _T_1392 = shl(UInt<4>(0ha), 3) node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392) node _T_1394 = bits(_T_1393, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1394 node _T_1395 = eq(UInt<5>(0h19), idx_10) when _T_1395 : node _T_1396 = shl(UInt<4>(0ha), 3) node _T_1397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1396) node _T_1398 = bits(_T_1397, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1398 node _T_1399 = eq(UInt<5>(0h1a), idx_10) when _T_1399 : node _T_1400 = shl(UInt<4>(0ha), 3) node _T_1401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1400) node _T_1402 = bits(_T_1401, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1402 node _T_1403 = eq(UInt<5>(0h1b), idx_10) when _T_1403 : node _T_1404 = shl(UInt<4>(0ha), 3) node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404) node _T_1406 = bits(_T_1405, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1406 node _T_1407 = eq(UInt<5>(0h1c), idx_10) when _T_1407 : node _T_1408 = shl(UInt<4>(0ha), 3) node _T_1409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1408) node _T_1410 = bits(_T_1409, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1410 node _T_1411 = eq(UInt<5>(0h1d), idx_10) when _T_1411 : node _T_1412 = shl(UInt<4>(0ha), 3) node _T_1413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1412) node _T_1414 = bits(_T_1413, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1414 node _T_1415 = eq(UInt<5>(0h1e), idx_10) when _T_1415 : node _T_1416 = shl(UInt<4>(0ha), 3) node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416) node _T_1418 = bits(_T_1417, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1418 node _T_1419 = eq(UInt<5>(0h1f), idx_10) when _T_1419 : node _T_1420 = shl(UInt<4>(0ha), 3) node _T_1421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1420) node _T_1422 = bits(_T_1421, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1422 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_1423 = eq(UInt<1>(0h0), idx_11) when _T_1423 : node _T_1424 = shl(UInt<4>(0hb), 3) node _T_1425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1424) node _T_1426 = bits(_T_1425, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1426 node _T_1427 = eq(UInt<1>(0h1), idx_11) when _T_1427 : node _T_1428 = shl(UInt<4>(0hb), 3) node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428) node _T_1430 = bits(_T_1429, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1430 node _T_1431 = eq(UInt<2>(0h2), idx_11) when _T_1431 : node _T_1432 = shl(UInt<4>(0hb), 3) node _T_1433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1432) node _T_1434 = bits(_T_1433, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1434 node _T_1435 = eq(UInt<2>(0h3), idx_11) when _T_1435 : node _T_1436 = shl(UInt<4>(0hb), 3) node _T_1437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1436) node _T_1438 = bits(_T_1437, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1438 node _T_1439 = eq(UInt<3>(0h4), idx_11) when _T_1439 : node _T_1440 = shl(UInt<4>(0hb), 3) node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440) node _T_1442 = bits(_T_1441, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1442 node _T_1443 = eq(UInt<3>(0h5), idx_11) when _T_1443 : node _T_1444 = shl(UInt<4>(0hb), 3) node _T_1445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1444) node _T_1446 = bits(_T_1445, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1446 node _T_1447 = eq(UInt<3>(0h6), idx_11) when _T_1447 : node _T_1448 = shl(UInt<4>(0hb), 3) node _T_1449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1448) node _T_1450 = bits(_T_1449, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1450 node _T_1451 = eq(UInt<3>(0h7), idx_11) when _T_1451 : node _T_1452 = shl(UInt<4>(0hb), 3) node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452) node _T_1454 = bits(_T_1453, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1454 node _T_1455 = eq(UInt<4>(0h8), idx_11) when _T_1455 : node _T_1456 = shl(UInt<4>(0hb), 3) node _T_1457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1456) node _T_1458 = bits(_T_1457, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1458 node _T_1459 = eq(UInt<4>(0h9), idx_11) when _T_1459 : node _T_1460 = shl(UInt<4>(0hb), 3) node _T_1461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1460) node _T_1462 = bits(_T_1461, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1462 node _T_1463 = eq(UInt<4>(0ha), idx_11) when _T_1463 : node _T_1464 = shl(UInt<4>(0hb), 3) node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464) node _T_1466 = bits(_T_1465, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1466 node _T_1467 = eq(UInt<4>(0hb), idx_11) when _T_1467 : node _T_1468 = shl(UInt<4>(0hb), 3) node _T_1469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1468) node _T_1470 = bits(_T_1469, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1470 node _T_1471 = eq(UInt<4>(0hc), idx_11) when _T_1471 : node _T_1472 = shl(UInt<4>(0hb), 3) node _T_1473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1472) node _T_1474 = bits(_T_1473, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1474 node _T_1475 = eq(UInt<4>(0hd), idx_11) when _T_1475 : node _T_1476 = shl(UInt<4>(0hb), 3) node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476) node _T_1478 = bits(_T_1477, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1478 node _T_1479 = eq(UInt<4>(0he), idx_11) when _T_1479 : node _T_1480 = shl(UInt<4>(0hb), 3) node _T_1481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1480) node _T_1482 = bits(_T_1481, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1482 node _T_1483 = eq(UInt<4>(0hf), idx_11) when _T_1483 : node _T_1484 = shl(UInt<4>(0hb), 3) node _T_1485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1484) node _T_1486 = bits(_T_1485, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1486 node _T_1487 = eq(UInt<5>(0h10), idx_11) when _T_1487 : node _T_1488 = shl(UInt<4>(0hb), 3) node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488) node _T_1490 = bits(_T_1489, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1490 node _T_1491 = eq(UInt<5>(0h11), idx_11) when _T_1491 : node _T_1492 = shl(UInt<4>(0hb), 3) node _T_1493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1492) node _T_1494 = bits(_T_1493, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1494 node _T_1495 = eq(UInt<5>(0h12), idx_11) when _T_1495 : node _T_1496 = shl(UInt<4>(0hb), 3) node _T_1497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1496) node _T_1498 = bits(_T_1497, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1498 node _T_1499 = eq(UInt<5>(0h13), idx_11) when _T_1499 : node _T_1500 = shl(UInt<4>(0hb), 3) node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500) node _T_1502 = bits(_T_1501, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1502 node _T_1503 = eq(UInt<5>(0h14), idx_11) when _T_1503 : node _T_1504 = shl(UInt<4>(0hb), 3) node _T_1505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1504) node _T_1506 = bits(_T_1505, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1506 node _T_1507 = eq(UInt<5>(0h15), idx_11) when _T_1507 : node _T_1508 = shl(UInt<4>(0hb), 3) node _T_1509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1508) node _T_1510 = bits(_T_1509, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1510 node _T_1511 = eq(UInt<5>(0h16), idx_11) when _T_1511 : node _T_1512 = shl(UInt<4>(0hb), 3) node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512) node _T_1514 = bits(_T_1513, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1514 node _T_1515 = eq(UInt<5>(0h17), idx_11) when _T_1515 : node _T_1516 = shl(UInt<4>(0hb), 3) node _T_1517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1516) node _T_1518 = bits(_T_1517, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1518 node _T_1519 = eq(UInt<5>(0h18), idx_11) when _T_1519 : node _T_1520 = shl(UInt<4>(0hb), 3) node _T_1521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1520) node _T_1522 = bits(_T_1521, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1522 node _T_1523 = eq(UInt<5>(0h19), idx_11) when _T_1523 : node _T_1524 = shl(UInt<4>(0hb), 3) node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524) node _T_1526 = bits(_T_1525, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1526 node _T_1527 = eq(UInt<5>(0h1a), idx_11) when _T_1527 : node _T_1528 = shl(UInt<4>(0hb), 3) node _T_1529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1528) node _T_1530 = bits(_T_1529, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1530 node _T_1531 = eq(UInt<5>(0h1b), idx_11) when _T_1531 : node _T_1532 = shl(UInt<4>(0hb), 3) node _T_1533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1532) node _T_1534 = bits(_T_1533, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1534 node _T_1535 = eq(UInt<5>(0h1c), idx_11) when _T_1535 : node _T_1536 = shl(UInt<4>(0hb), 3) node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536) node _T_1538 = bits(_T_1537, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1538 node _T_1539 = eq(UInt<5>(0h1d), idx_11) when _T_1539 : node _T_1540 = shl(UInt<4>(0hb), 3) node _T_1541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1540) node _T_1542 = bits(_T_1541, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1542 node _T_1543 = eq(UInt<5>(0h1e), idx_11) when _T_1543 : node _T_1544 = shl(UInt<4>(0hb), 3) node _T_1545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1544) node _T_1546 = bits(_T_1545, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1546 node _T_1547 = eq(UInt<5>(0h1f), idx_11) when _T_1547 : node _T_1548 = shl(UInt<4>(0hb), 3) node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548) node _T_1550 = bits(_T_1549, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1550 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_1551 = eq(UInt<1>(0h0), idx_12) when _T_1551 : node _T_1552 = shl(UInt<4>(0hc), 3) node _T_1553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1552) node _T_1554 = bits(_T_1553, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1554 node _T_1555 = eq(UInt<1>(0h1), idx_12) when _T_1555 : node _T_1556 = shl(UInt<4>(0hc), 3) node _T_1557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1556) node _T_1558 = bits(_T_1557, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1558 node _T_1559 = eq(UInt<2>(0h2), idx_12) when _T_1559 : node _T_1560 = shl(UInt<4>(0hc), 3) node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560) node _T_1562 = bits(_T_1561, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1562 node _T_1563 = eq(UInt<2>(0h3), idx_12) when _T_1563 : node _T_1564 = shl(UInt<4>(0hc), 3) node _T_1565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1564) node _T_1566 = bits(_T_1565, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1566 node _T_1567 = eq(UInt<3>(0h4), idx_12) when _T_1567 : node _T_1568 = shl(UInt<4>(0hc), 3) node _T_1569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1568) node _T_1570 = bits(_T_1569, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1570 node _T_1571 = eq(UInt<3>(0h5), idx_12) when _T_1571 : node _T_1572 = shl(UInt<4>(0hc), 3) node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572) node _T_1574 = bits(_T_1573, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1574 node _T_1575 = eq(UInt<3>(0h6), idx_12) when _T_1575 : node _T_1576 = shl(UInt<4>(0hc), 3) node _T_1577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1576) node _T_1578 = bits(_T_1577, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1578 node _T_1579 = eq(UInt<3>(0h7), idx_12) when _T_1579 : node _T_1580 = shl(UInt<4>(0hc), 3) node _T_1581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1580) node _T_1582 = bits(_T_1581, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1582 node _T_1583 = eq(UInt<4>(0h8), idx_12) when _T_1583 : node _T_1584 = shl(UInt<4>(0hc), 3) node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584) node _T_1586 = bits(_T_1585, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1586 node _T_1587 = eq(UInt<4>(0h9), idx_12) when _T_1587 : node _T_1588 = shl(UInt<4>(0hc), 3) node _T_1589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1588) node _T_1590 = bits(_T_1589, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1590 node _T_1591 = eq(UInt<4>(0ha), idx_12) when _T_1591 : node _T_1592 = shl(UInt<4>(0hc), 3) node _T_1593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1592) node _T_1594 = bits(_T_1593, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1594 node _T_1595 = eq(UInt<4>(0hb), idx_12) when _T_1595 : node _T_1596 = shl(UInt<4>(0hc), 3) node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596) node _T_1598 = bits(_T_1597, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1598 node _T_1599 = eq(UInt<4>(0hc), idx_12) when _T_1599 : node _T_1600 = shl(UInt<4>(0hc), 3) node _T_1601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1600) node _T_1602 = bits(_T_1601, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1602 node _T_1603 = eq(UInt<4>(0hd), idx_12) when _T_1603 : node _T_1604 = shl(UInt<4>(0hc), 3) node _T_1605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1604) node _T_1606 = bits(_T_1605, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1606 node _T_1607 = eq(UInt<4>(0he), idx_12) when _T_1607 : node _T_1608 = shl(UInt<4>(0hc), 3) node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608) node _T_1610 = bits(_T_1609, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1610 node _T_1611 = eq(UInt<4>(0hf), idx_12) when _T_1611 : node _T_1612 = shl(UInt<4>(0hc), 3) node _T_1613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1612) node _T_1614 = bits(_T_1613, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1614 node _T_1615 = eq(UInt<5>(0h10), idx_12) when _T_1615 : node _T_1616 = shl(UInt<4>(0hc), 3) node _T_1617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1616) node _T_1618 = bits(_T_1617, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1618 node _T_1619 = eq(UInt<5>(0h11), idx_12) when _T_1619 : node _T_1620 = shl(UInt<4>(0hc), 3) node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620) node _T_1622 = bits(_T_1621, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1622 node _T_1623 = eq(UInt<5>(0h12), idx_12) when _T_1623 : node _T_1624 = shl(UInt<4>(0hc), 3) node _T_1625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1624) node _T_1626 = bits(_T_1625, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1626 node _T_1627 = eq(UInt<5>(0h13), idx_12) when _T_1627 : node _T_1628 = shl(UInt<4>(0hc), 3) node _T_1629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1628) node _T_1630 = bits(_T_1629, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1630 node _T_1631 = eq(UInt<5>(0h14), idx_12) when _T_1631 : node _T_1632 = shl(UInt<4>(0hc), 3) node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632) node _T_1634 = bits(_T_1633, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1634 node _T_1635 = eq(UInt<5>(0h15), idx_12) when _T_1635 : node _T_1636 = shl(UInt<4>(0hc), 3) node _T_1637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1636) node _T_1638 = bits(_T_1637, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1638 node _T_1639 = eq(UInt<5>(0h16), idx_12) when _T_1639 : node _T_1640 = shl(UInt<4>(0hc), 3) node _T_1641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1640) node _T_1642 = bits(_T_1641, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1642 node _T_1643 = eq(UInt<5>(0h17), idx_12) when _T_1643 : node _T_1644 = shl(UInt<4>(0hc), 3) node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644) node _T_1646 = bits(_T_1645, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1646 node _T_1647 = eq(UInt<5>(0h18), idx_12) when _T_1647 : node _T_1648 = shl(UInt<4>(0hc), 3) node _T_1649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1648) node _T_1650 = bits(_T_1649, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1650 node _T_1651 = eq(UInt<5>(0h19), idx_12) when _T_1651 : node _T_1652 = shl(UInt<4>(0hc), 3) node _T_1653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1652) node _T_1654 = bits(_T_1653, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1654 node _T_1655 = eq(UInt<5>(0h1a), idx_12) when _T_1655 : node _T_1656 = shl(UInt<4>(0hc), 3) node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656) node _T_1658 = bits(_T_1657, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1658 node _T_1659 = eq(UInt<5>(0h1b), idx_12) when _T_1659 : node _T_1660 = shl(UInt<4>(0hc), 3) node _T_1661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1660) node _T_1662 = bits(_T_1661, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1662 node _T_1663 = eq(UInt<5>(0h1c), idx_12) when _T_1663 : node _T_1664 = shl(UInt<4>(0hc), 3) node _T_1665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1664) node _T_1666 = bits(_T_1665, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1666 node _T_1667 = eq(UInt<5>(0h1d), idx_12) when _T_1667 : node _T_1668 = shl(UInt<4>(0hc), 3) node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668) node _T_1670 = bits(_T_1669, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1670 node _T_1671 = eq(UInt<5>(0h1e), idx_12) when _T_1671 : node _T_1672 = shl(UInt<4>(0hc), 3) node _T_1673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1672) node _T_1674 = bits(_T_1673, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1674 node _T_1675 = eq(UInt<5>(0h1f), idx_12) when _T_1675 : node _T_1676 = shl(UInt<4>(0hc), 3) node _T_1677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1676) node _T_1678 = bits(_T_1677, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1678 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_1679 = eq(UInt<1>(0h0), idx_13) when _T_1679 : node _T_1680 = shl(UInt<4>(0hd), 3) node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680) node _T_1682 = bits(_T_1681, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1682 node _T_1683 = eq(UInt<1>(0h1), idx_13) when _T_1683 : node _T_1684 = shl(UInt<4>(0hd), 3) node _T_1685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1684) node _T_1686 = bits(_T_1685, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1686 node _T_1687 = eq(UInt<2>(0h2), idx_13) when _T_1687 : node _T_1688 = shl(UInt<4>(0hd), 3) node _T_1689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1688) node _T_1690 = bits(_T_1689, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1690 node _T_1691 = eq(UInt<2>(0h3), idx_13) when _T_1691 : node _T_1692 = shl(UInt<4>(0hd), 3) node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692) node _T_1694 = bits(_T_1693, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1694 node _T_1695 = eq(UInt<3>(0h4), idx_13) when _T_1695 : node _T_1696 = shl(UInt<4>(0hd), 3) node _T_1697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1696) node _T_1698 = bits(_T_1697, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1698 node _T_1699 = eq(UInt<3>(0h5), idx_13) when _T_1699 : node _T_1700 = shl(UInt<4>(0hd), 3) node _T_1701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1700) node _T_1702 = bits(_T_1701, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1702 node _T_1703 = eq(UInt<3>(0h6), idx_13) when _T_1703 : node _T_1704 = shl(UInt<4>(0hd), 3) node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704) node _T_1706 = bits(_T_1705, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1706 node _T_1707 = eq(UInt<3>(0h7), idx_13) when _T_1707 : node _T_1708 = shl(UInt<4>(0hd), 3) node _T_1709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1708) node _T_1710 = bits(_T_1709, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1710 node _T_1711 = eq(UInt<4>(0h8), idx_13) when _T_1711 : node _T_1712 = shl(UInt<4>(0hd), 3) node _T_1713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1712) node _T_1714 = bits(_T_1713, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1714 node _T_1715 = eq(UInt<4>(0h9), idx_13) when _T_1715 : node _T_1716 = shl(UInt<4>(0hd), 3) node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716) node _T_1718 = bits(_T_1717, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1718 node _T_1719 = eq(UInt<4>(0ha), idx_13) when _T_1719 : node _T_1720 = shl(UInt<4>(0hd), 3) node _T_1721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1720) node _T_1722 = bits(_T_1721, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1722 node _T_1723 = eq(UInt<4>(0hb), idx_13) when _T_1723 : node _T_1724 = shl(UInt<4>(0hd), 3) node _T_1725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1724) node _T_1726 = bits(_T_1725, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1726 node _T_1727 = eq(UInt<4>(0hc), idx_13) when _T_1727 : node _T_1728 = shl(UInt<4>(0hd), 3) node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728) node _T_1730 = bits(_T_1729, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1730 node _T_1731 = eq(UInt<4>(0hd), idx_13) when _T_1731 : node _T_1732 = shl(UInt<4>(0hd), 3) node _T_1733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1732) node _T_1734 = bits(_T_1733, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1734 node _T_1735 = eq(UInt<4>(0he), idx_13) when _T_1735 : node _T_1736 = shl(UInt<4>(0hd), 3) node _T_1737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1736) node _T_1738 = bits(_T_1737, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1738 node _T_1739 = eq(UInt<4>(0hf), idx_13) when _T_1739 : node _T_1740 = shl(UInt<4>(0hd), 3) node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740) node _T_1742 = bits(_T_1741, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1742 node _T_1743 = eq(UInt<5>(0h10), idx_13) when _T_1743 : node _T_1744 = shl(UInt<4>(0hd), 3) node _T_1745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1744) node _T_1746 = bits(_T_1745, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1746 node _T_1747 = eq(UInt<5>(0h11), idx_13) when _T_1747 : node _T_1748 = shl(UInt<4>(0hd), 3) node _T_1749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1748) node _T_1750 = bits(_T_1749, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1750 node _T_1751 = eq(UInt<5>(0h12), idx_13) when _T_1751 : node _T_1752 = shl(UInt<4>(0hd), 3) node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752) node _T_1754 = bits(_T_1753, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1754 node _T_1755 = eq(UInt<5>(0h13), idx_13) when _T_1755 : node _T_1756 = shl(UInt<4>(0hd), 3) node _T_1757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1756) node _T_1758 = bits(_T_1757, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1758 node _T_1759 = eq(UInt<5>(0h14), idx_13) when _T_1759 : node _T_1760 = shl(UInt<4>(0hd), 3) node _T_1761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1760) node _T_1762 = bits(_T_1761, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1762 node _T_1763 = eq(UInt<5>(0h15), idx_13) when _T_1763 : node _T_1764 = shl(UInt<4>(0hd), 3) node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764) node _T_1766 = bits(_T_1765, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1766 node _T_1767 = eq(UInt<5>(0h16), idx_13) when _T_1767 : node _T_1768 = shl(UInt<4>(0hd), 3) node _T_1769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1768) node _T_1770 = bits(_T_1769, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1770 node _T_1771 = eq(UInt<5>(0h17), idx_13) when _T_1771 : node _T_1772 = shl(UInt<4>(0hd), 3) node _T_1773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1772) node _T_1774 = bits(_T_1773, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1774 node _T_1775 = eq(UInt<5>(0h18), idx_13) when _T_1775 : node _T_1776 = shl(UInt<4>(0hd), 3) node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776) node _T_1778 = bits(_T_1777, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1778 node _T_1779 = eq(UInt<5>(0h19), idx_13) when _T_1779 : node _T_1780 = shl(UInt<4>(0hd), 3) node _T_1781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1780) node _T_1782 = bits(_T_1781, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1782 node _T_1783 = eq(UInt<5>(0h1a), idx_13) when _T_1783 : node _T_1784 = shl(UInt<4>(0hd), 3) node _T_1785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1784) node _T_1786 = bits(_T_1785, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1786 node _T_1787 = eq(UInt<5>(0h1b), idx_13) when _T_1787 : node _T_1788 = shl(UInt<4>(0hd), 3) node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788) node _T_1790 = bits(_T_1789, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1790 node _T_1791 = eq(UInt<5>(0h1c), idx_13) when _T_1791 : node _T_1792 = shl(UInt<4>(0hd), 3) node _T_1793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1792) node _T_1794 = bits(_T_1793, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1794 node _T_1795 = eq(UInt<5>(0h1d), idx_13) when _T_1795 : node _T_1796 = shl(UInt<4>(0hd), 3) node _T_1797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1796) node _T_1798 = bits(_T_1797, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1798 node _T_1799 = eq(UInt<5>(0h1e), idx_13) when _T_1799 : node _T_1800 = shl(UInt<4>(0hd), 3) node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800) node _T_1802 = bits(_T_1801, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1802 node _T_1803 = eq(UInt<5>(0h1f), idx_13) when _T_1803 : node _T_1804 = shl(UInt<4>(0hd), 3) node _T_1805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1804) node _T_1806 = bits(_T_1805, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1806 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_1807 = eq(UInt<1>(0h0), idx_14) when _T_1807 : node _T_1808 = shl(UInt<4>(0he), 3) node _T_1809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1808) node _T_1810 = bits(_T_1809, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1810 node _T_1811 = eq(UInt<1>(0h1), idx_14) when _T_1811 : node _T_1812 = shl(UInt<4>(0he), 3) node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812) node _T_1814 = bits(_T_1813, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1814 node _T_1815 = eq(UInt<2>(0h2), idx_14) when _T_1815 : node _T_1816 = shl(UInt<4>(0he), 3) node _T_1817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1816) node _T_1818 = bits(_T_1817, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1818 node _T_1819 = eq(UInt<2>(0h3), idx_14) when _T_1819 : node _T_1820 = shl(UInt<4>(0he), 3) node _T_1821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1820) node _T_1822 = bits(_T_1821, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1822 node _T_1823 = eq(UInt<3>(0h4), idx_14) when _T_1823 : node _T_1824 = shl(UInt<4>(0he), 3) node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824) node _T_1826 = bits(_T_1825, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1826 node _T_1827 = eq(UInt<3>(0h5), idx_14) when _T_1827 : node _T_1828 = shl(UInt<4>(0he), 3) node _T_1829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1828) node _T_1830 = bits(_T_1829, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1830 node _T_1831 = eq(UInt<3>(0h6), idx_14) when _T_1831 : node _T_1832 = shl(UInt<4>(0he), 3) node _T_1833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1832) node _T_1834 = bits(_T_1833, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1834 node _T_1835 = eq(UInt<3>(0h7), idx_14) when _T_1835 : node _T_1836 = shl(UInt<4>(0he), 3) node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836) node _T_1838 = bits(_T_1837, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1838 node _T_1839 = eq(UInt<4>(0h8), idx_14) when _T_1839 : node _T_1840 = shl(UInt<4>(0he), 3) node _T_1841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1840) node _T_1842 = bits(_T_1841, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1842 node _T_1843 = eq(UInt<4>(0h9), idx_14) when _T_1843 : node _T_1844 = shl(UInt<4>(0he), 3) node _T_1845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1844) node _T_1846 = bits(_T_1845, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1846 node _T_1847 = eq(UInt<4>(0ha), idx_14) when _T_1847 : node _T_1848 = shl(UInt<4>(0he), 3) node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848) node _T_1850 = bits(_T_1849, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1850 node _T_1851 = eq(UInt<4>(0hb), idx_14) when _T_1851 : node _T_1852 = shl(UInt<4>(0he), 3) node _T_1853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1852) node _T_1854 = bits(_T_1853, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1854 node _T_1855 = eq(UInt<4>(0hc), idx_14) when _T_1855 : node _T_1856 = shl(UInt<4>(0he), 3) node _T_1857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1856) node _T_1858 = bits(_T_1857, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1858 node _T_1859 = eq(UInt<4>(0hd), idx_14) when _T_1859 : node _T_1860 = shl(UInt<4>(0he), 3) node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860) node _T_1862 = bits(_T_1861, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1862 node _T_1863 = eq(UInt<4>(0he), idx_14) when _T_1863 : node _T_1864 = shl(UInt<4>(0he), 3) node _T_1865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1864) node _T_1866 = bits(_T_1865, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1866 node _T_1867 = eq(UInt<4>(0hf), idx_14) when _T_1867 : node _T_1868 = shl(UInt<4>(0he), 3) node _T_1869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1868) node _T_1870 = bits(_T_1869, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1870 node _T_1871 = eq(UInt<5>(0h10), idx_14) when _T_1871 : node _T_1872 = shl(UInt<4>(0he), 3) node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872) node _T_1874 = bits(_T_1873, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_1874 node _T_1875 = eq(UInt<5>(0h11), idx_14) when _T_1875 : node _T_1876 = shl(UInt<4>(0he), 3) node _T_1877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1876) node _T_1878 = bits(_T_1877, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_1878 node _T_1879 = eq(UInt<5>(0h12), idx_14) when _T_1879 : node _T_1880 = shl(UInt<4>(0he), 3) node _T_1881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1880) node _T_1882 = bits(_T_1881, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_1882 node _T_1883 = eq(UInt<5>(0h13), idx_14) when _T_1883 : node _T_1884 = shl(UInt<4>(0he), 3) node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884) node _T_1886 = bits(_T_1885, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_1886 node _T_1887 = eq(UInt<5>(0h14), idx_14) when _T_1887 : node _T_1888 = shl(UInt<4>(0he), 3) node _T_1889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1888) node _T_1890 = bits(_T_1889, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_1890 node _T_1891 = eq(UInt<5>(0h15), idx_14) when _T_1891 : node _T_1892 = shl(UInt<4>(0he), 3) node _T_1893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1892) node _T_1894 = bits(_T_1893, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_1894 node _T_1895 = eq(UInt<5>(0h16), idx_14) when _T_1895 : node _T_1896 = shl(UInt<4>(0he), 3) node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896) node _T_1898 = bits(_T_1897, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_1898 node _T_1899 = eq(UInt<5>(0h17), idx_14) when _T_1899 : node _T_1900 = shl(UInt<4>(0he), 3) node _T_1901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1900) node _T_1902 = bits(_T_1901, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_1902 node _T_1903 = eq(UInt<5>(0h18), idx_14) when _T_1903 : node _T_1904 = shl(UInt<4>(0he), 3) node _T_1905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1904) node _T_1906 = bits(_T_1905, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_1906 node _T_1907 = eq(UInt<5>(0h19), idx_14) when _T_1907 : node _T_1908 = shl(UInt<4>(0he), 3) node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908) node _T_1910 = bits(_T_1909, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_1910 node _T_1911 = eq(UInt<5>(0h1a), idx_14) when _T_1911 : node _T_1912 = shl(UInt<4>(0he), 3) node _T_1913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1912) node _T_1914 = bits(_T_1913, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_1914 node _T_1915 = eq(UInt<5>(0h1b), idx_14) when _T_1915 : node _T_1916 = shl(UInt<4>(0he), 3) node _T_1917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1916) node _T_1918 = bits(_T_1917, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_1918 node _T_1919 = eq(UInt<5>(0h1c), idx_14) when _T_1919 : node _T_1920 = shl(UInt<4>(0he), 3) node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920) node _T_1922 = bits(_T_1921, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_1922 node _T_1923 = eq(UInt<5>(0h1d), idx_14) when _T_1923 : node _T_1924 = shl(UInt<4>(0he), 3) node _T_1925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1924) node _T_1926 = bits(_T_1925, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_1926 node _T_1927 = eq(UInt<5>(0h1e), idx_14) when _T_1927 : node _T_1928 = shl(UInt<4>(0he), 3) node _T_1929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1928) node _T_1930 = bits(_T_1929, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_1930 node _T_1931 = eq(UInt<5>(0h1f), idx_14) when _T_1931 : node _T_1932 = shl(UInt<4>(0he), 3) node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932) node _T_1934 = bits(_T_1933, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_1934 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1935 = eq(UInt<1>(0h0), idx_15) when _T_1935 : node _T_1936 = shl(UInt<4>(0hf), 3) node _T_1937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1936) node _T_1938 = bits(_T_1937, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_1938 node _T_1939 = eq(UInt<1>(0h1), idx_15) when _T_1939 : node _T_1940 = shl(UInt<4>(0hf), 3) node _T_1941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1940) node _T_1942 = bits(_T_1941, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_1942 node _T_1943 = eq(UInt<2>(0h2), idx_15) when _T_1943 : node _T_1944 = shl(UInt<4>(0hf), 3) node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944) node _T_1946 = bits(_T_1945, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_1946 node _T_1947 = eq(UInt<2>(0h3), idx_15) when _T_1947 : node _T_1948 = shl(UInt<4>(0hf), 3) node _T_1949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1948) node _T_1950 = bits(_T_1949, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_1950 node _T_1951 = eq(UInt<3>(0h4), idx_15) when _T_1951 : node _T_1952 = shl(UInt<4>(0hf), 3) node _T_1953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1952) node _T_1954 = bits(_T_1953, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_1954 node _T_1955 = eq(UInt<3>(0h5), idx_15) when _T_1955 : node _T_1956 = shl(UInt<4>(0hf), 3) node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956) node _T_1958 = bits(_T_1957, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_1958 node _T_1959 = eq(UInt<3>(0h6), idx_15) when _T_1959 : node _T_1960 = shl(UInt<4>(0hf), 3) node _T_1961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1960) node _T_1962 = bits(_T_1961, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_1962 node _T_1963 = eq(UInt<3>(0h7), idx_15) when _T_1963 : node _T_1964 = shl(UInt<4>(0hf), 3) node _T_1965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1964) node _T_1966 = bits(_T_1965, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_1966 node _T_1967 = eq(UInt<4>(0h8), idx_15) when _T_1967 : node _T_1968 = shl(UInt<4>(0hf), 3) node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968) node _T_1970 = bits(_T_1969, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_1970 node _T_1971 = eq(UInt<4>(0h9), idx_15) when _T_1971 : node _T_1972 = shl(UInt<4>(0hf), 3) node _T_1973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1972) node _T_1974 = bits(_T_1973, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_1974 node _T_1975 = eq(UInt<4>(0ha), idx_15) when _T_1975 : node _T_1976 = shl(UInt<4>(0hf), 3) node _T_1977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1976) node _T_1978 = bits(_T_1977, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_1978 node _T_1979 = eq(UInt<4>(0hb), idx_15) when _T_1979 : node _T_1980 = shl(UInt<4>(0hf), 3) node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980) node _T_1982 = bits(_T_1981, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_1982 node _T_1983 = eq(UInt<4>(0hc), idx_15) when _T_1983 : node _T_1984 = shl(UInt<4>(0hf), 3) node _T_1985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1984) node _T_1986 = bits(_T_1985, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_1986 node _T_1987 = eq(UInt<4>(0hd), idx_15) when _T_1987 : node _T_1988 = shl(UInt<4>(0hf), 3) node _T_1989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1988) node _T_1990 = bits(_T_1989, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_1990 node _T_1991 = eq(UInt<4>(0he), idx_15) when _T_1991 : node _T_1992 = shl(UInt<4>(0hf), 3) node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992) node _T_1994 = bits(_T_1993, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_1994 node _T_1995 = eq(UInt<4>(0hf), idx_15) when _T_1995 : node _T_1996 = shl(UInt<4>(0hf), 3) node _T_1997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1996) node _T_1998 = bits(_T_1997, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_1998 node _T_1999 = eq(UInt<5>(0h10), idx_15) when _T_1999 : node _T_2000 = shl(UInt<4>(0hf), 3) node _T_2001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2000) node _T_2002 = bits(_T_2001, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2002 node _T_2003 = eq(UInt<5>(0h11), idx_15) when _T_2003 : node _T_2004 = shl(UInt<4>(0hf), 3) node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004) node _T_2006 = bits(_T_2005, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2006 node _T_2007 = eq(UInt<5>(0h12), idx_15) when _T_2007 : node _T_2008 = shl(UInt<4>(0hf), 3) node _T_2009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2008) node _T_2010 = bits(_T_2009, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2010 node _T_2011 = eq(UInt<5>(0h13), idx_15) when _T_2011 : node _T_2012 = shl(UInt<4>(0hf), 3) node _T_2013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2012) node _T_2014 = bits(_T_2013, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2014 node _T_2015 = eq(UInt<5>(0h14), idx_15) when _T_2015 : node _T_2016 = shl(UInt<4>(0hf), 3) node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016) node _T_2018 = bits(_T_2017, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2018 node _T_2019 = eq(UInt<5>(0h15), idx_15) when _T_2019 : node _T_2020 = shl(UInt<4>(0hf), 3) node _T_2021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2020) node _T_2022 = bits(_T_2021, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2022 node _T_2023 = eq(UInt<5>(0h16), idx_15) when _T_2023 : node _T_2024 = shl(UInt<4>(0hf), 3) node _T_2025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2024) node _T_2026 = bits(_T_2025, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2026 node _T_2027 = eq(UInt<5>(0h17), idx_15) when _T_2027 : node _T_2028 = shl(UInt<4>(0hf), 3) node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028) node _T_2030 = bits(_T_2029, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2030 node _T_2031 = eq(UInt<5>(0h18), idx_15) when _T_2031 : node _T_2032 = shl(UInt<4>(0hf), 3) node _T_2033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2032) node _T_2034 = bits(_T_2033, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2034 node _T_2035 = eq(UInt<5>(0h19), idx_15) when _T_2035 : node _T_2036 = shl(UInt<4>(0hf), 3) node _T_2037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2036) node _T_2038 = bits(_T_2037, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2038 node _T_2039 = eq(UInt<5>(0h1a), idx_15) when _T_2039 : node _T_2040 = shl(UInt<4>(0hf), 3) node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040) node _T_2042 = bits(_T_2041, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2042 node _T_2043 = eq(UInt<5>(0h1b), idx_15) when _T_2043 : node _T_2044 = shl(UInt<4>(0hf), 3) node _T_2045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2044) node _T_2046 = bits(_T_2045, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2046 node _T_2047 = eq(UInt<5>(0h1c), idx_15) when _T_2047 : node _T_2048 = shl(UInt<4>(0hf), 3) node _T_2049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2048) node _T_2050 = bits(_T_2049, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2050 node _T_2051 = eq(UInt<5>(0h1d), idx_15) when _T_2051 : node _T_2052 = shl(UInt<4>(0hf), 3) node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052) node _T_2054 = bits(_T_2053, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2054 node _T_2055 = eq(UInt<5>(0h1e), idx_15) when _T_2055 : node _T_2056 = shl(UInt<4>(0hf), 3) node _T_2057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2056) node _T_2058 = bits(_T_2057, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2058 node _T_2059 = eq(UInt<5>(0h1f), idx_15) when _T_2059 : node _T_2060 = shl(UInt<4>(0hf), 3) node _T_2061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2060) node _T_2062 = bits(_T_2061, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2062 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_2063 = eq(UInt<1>(0h0), idx_16) when _T_2063 : node _T_2064 = shl(UInt<5>(0h10), 3) node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064) node _T_2066 = bits(_T_2065, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2066 node _T_2067 = eq(UInt<1>(0h1), idx_16) when _T_2067 : node _T_2068 = shl(UInt<5>(0h10), 3) node _T_2069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2068) node _T_2070 = bits(_T_2069, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2070 node _T_2071 = eq(UInt<2>(0h2), idx_16) when _T_2071 : node _T_2072 = shl(UInt<5>(0h10), 3) node _T_2073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2072) node _T_2074 = bits(_T_2073, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2074 node _T_2075 = eq(UInt<2>(0h3), idx_16) when _T_2075 : node _T_2076 = shl(UInt<5>(0h10), 3) node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076) node _T_2078 = bits(_T_2077, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2078 node _T_2079 = eq(UInt<3>(0h4), idx_16) when _T_2079 : node _T_2080 = shl(UInt<5>(0h10), 3) node _T_2081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2080) node _T_2082 = bits(_T_2081, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2082 node _T_2083 = eq(UInt<3>(0h5), idx_16) when _T_2083 : node _T_2084 = shl(UInt<5>(0h10), 3) node _T_2085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2084) node _T_2086 = bits(_T_2085, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2086 node _T_2087 = eq(UInt<3>(0h6), idx_16) when _T_2087 : node _T_2088 = shl(UInt<5>(0h10), 3) node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088) node _T_2090 = bits(_T_2089, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2090 node _T_2091 = eq(UInt<3>(0h7), idx_16) when _T_2091 : node _T_2092 = shl(UInt<5>(0h10), 3) node _T_2093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2092) node _T_2094 = bits(_T_2093, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2094 node _T_2095 = eq(UInt<4>(0h8), idx_16) when _T_2095 : node _T_2096 = shl(UInt<5>(0h10), 3) node _T_2097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2096) node _T_2098 = bits(_T_2097, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2098 node _T_2099 = eq(UInt<4>(0h9), idx_16) when _T_2099 : node _T_2100 = shl(UInt<5>(0h10), 3) node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100) node _T_2102 = bits(_T_2101, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2102 node _T_2103 = eq(UInt<4>(0ha), idx_16) when _T_2103 : node _T_2104 = shl(UInt<5>(0h10), 3) node _T_2105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2104) node _T_2106 = bits(_T_2105, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2106 node _T_2107 = eq(UInt<4>(0hb), idx_16) when _T_2107 : node _T_2108 = shl(UInt<5>(0h10), 3) node _T_2109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2108) node _T_2110 = bits(_T_2109, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2110 node _T_2111 = eq(UInt<4>(0hc), idx_16) when _T_2111 : node _T_2112 = shl(UInt<5>(0h10), 3) node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112) node _T_2114 = bits(_T_2113, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2114 node _T_2115 = eq(UInt<4>(0hd), idx_16) when _T_2115 : node _T_2116 = shl(UInt<5>(0h10), 3) node _T_2117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2116) node _T_2118 = bits(_T_2117, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2118 node _T_2119 = eq(UInt<4>(0he), idx_16) when _T_2119 : node _T_2120 = shl(UInt<5>(0h10), 3) node _T_2121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2120) node _T_2122 = bits(_T_2121, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2122 node _T_2123 = eq(UInt<4>(0hf), idx_16) when _T_2123 : node _T_2124 = shl(UInt<5>(0h10), 3) node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124) node _T_2126 = bits(_T_2125, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2126 node _T_2127 = eq(UInt<5>(0h10), idx_16) when _T_2127 : node _T_2128 = shl(UInt<5>(0h10), 3) node _T_2129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2128) node _T_2130 = bits(_T_2129, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2130 node _T_2131 = eq(UInt<5>(0h11), idx_16) when _T_2131 : node _T_2132 = shl(UInt<5>(0h10), 3) node _T_2133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2132) node _T_2134 = bits(_T_2133, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2134 node _T_2135 = eq(UInt<5>(0h12), idx_16) when _T_2135 : node _T_2136 = shl(UInt<5>(0h10), 3) node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136) node _T_2138 = bits(_T_2137, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2138 node _T_2139 = eq(UInt<5>(0h13), idx_16) when _T_2139 : node _T_2140 = shl(UInt<5>(0h10), 3) node _T_2141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2140) node _T_2142 = bits(_T_2141, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2142 node _T_2143 = eq(UInt<5>(0h14), idx_16) when _T_2143 : node _T_2144 = shl(UInt<5>(0h10), 3) node _T_2145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2144) node _T_2146 = bits(_T_2145, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2146 node _T_2147 = eq(UInt<5>(0h15), idx_16) when _T_2147 : node _T_2148 = shl(UInt<5>(0h10), 3) node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148) node _T_2150 = bits(_T_2149, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2150 node _T_2151 = eq(UInt<5>(0h16), idx_16) when _T_2151 : node _T_2152 = shl(UInt<5>(0h10), 3) node _T_2153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2152) node _T_2154 = bits(_T_2153, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2154 node _T_2155 = eq(UInt<5>(0h17), idx_16) when _T_2155 : node _T_2156 = shl(UInt<5>(0h10), 3) node _T_2157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2156) node _T_2158 = bits(_T_2157, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2158 node _T_2159 = eq(UInt<5>(0h18), idx_16) when _T_2159 : node _T_2160 = shl(UInt<5>(0h10), 3) node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160) node _T_2162 = bits(_T_2161, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2162 node _T_2163 = eq(UInt<5>(0h19), idx_16) when _T_2163 : node _T_2164 = shl(UInt<5>(0h10), 3) node _T_2165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2164) node _T_2166 = bits(_T_2165, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2166 node _T_2167 = eq(UInt<5>(0h1a), idx_16) when _T_2167 : node _T_2168 = shl(UInt<5>(0h10), 3) node _T_2169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2168) node _T_2170 = bits(_T_2169, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2170 node _T_2171 = eq(UInt<5>(0h1b), idx_16) when _T_2171 : node _T_2172 = shl(UInt<5>(0h10), 3) node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172) node _T_2174 = bits(_T_2173, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2174 node _T_2175 = eq(UInt<5>(0h1c), idx_16) when _T_2175 : node _T_2176 = shl(UInt<5>(0h10), 3) node _T_2177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2176) node _T_2178 = bits(_T_2177, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2178 node _T_2179 = eq(UInt<5>(0h1d), idx_16) when _T_2179 : node _T_2180 = shl(UInt<5>(0h10), 3) node _T_2181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2180) node _T_2182 = bits(_T_2181, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2182 node _T_2183 = eq(UInt<5>(0h1e), idx_16) when _T_2183 : node _T_2184 = shl(UInt<5>(0h10), 3) node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184) node _T_2186 = bits(_T_2185, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2186 node _T_2187 = eq(UInt<5>(0h1f), idx_16) when _T_2187 : node _T_2188 = shl(UInt<5>(0h10), 3) node _T_2189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2188) node _T_2190 = bits(_T_2189, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2190 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_2191 = eq(UInt<1>(0h0), idx_17) when _T_2191 : node _T_2192 = shl(UInt<5>(0h11), 3) node _T_2193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2192) node _T_2194 = bits(_T_2193, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2194 node _T_2195 = eq(UInt<1>(0h1), idx_17) when _T_2195 : node _T_2196 = shl(UInt<5>(0h11), 3) node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196) node _T_2198 = bits(_T_2197, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2198 node _T_2199 = eq(UInt<2>(0h2), idx_17) when _T_2199 : node _T_2200 = shl(UInt<5>(0h11), 3) node _T_2201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2200) node _T_2202 = bits(_T_2201, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2202 node _T_2203 = eq(UInt<2>(0h3), idx_17) when _T_2203 : node _T_2204 = shl(UInt<5>(0h11), 3) node _T_2205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2204) node _T_2206 = bits(_T_2205, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2206 node _T_2207 = eq(UInt<3>(0h4), idx_17) when _T_2207 : node _T_2208 = shl(UInt<5>(0h11), 3) node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208) node _T_2210 = bits(_T_2209, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2210 node _T_2211 = eq(UInt<3>(0h5), idx_17) when _T_2211 : node _T_2212 = shl(UInt<5>(0h11), 3) node _T_2213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2212) node _T_2214 = bits(_T_2213, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2214 node _T_2215 = eq(UInt<3>(0h6), idx_17) when _T_2215 : node _T_2216 = shl(UInt<5>(0h11), 3) node _T_2217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2216) node _T_2218 = bits(_T_2217, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2218 node _T_2219 = eq(UInt<3>(0h7), idx_17) when _T_2219 : node _T_2220 = shl(UInt<5>(0h11), 3) node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220) node _T_2222 = bits(_T_2221, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2222 node _T_2223 = eq(UInt<4>(0h8), idx_17) when _T_2223 : node _T_2224 = shl(UInt<5>(0h11), 3) node _T_2225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2224) node _T_2226 = bits(_T_2225, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2226 node _T_2227 = eq(UInt<4>(0h9), idx_17) when _T_2227 : node _T_2228 = shl(UInt<5>(0h11), 3) node _T_2229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2228) node _T_2230 = bits(_T_2229, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2230 node _T_2231 = eq(UInt<4>(0ha), idx_17) when _T_2231 : node _T_2232 = shl(UInt<5>(0h11), 3) node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232) node _T_2234 = bits(_T_2233, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2234 node _T_2235 = eq(UInt<4>(0hb), idx_17) when _T_2235 : node _T_2236 = shl(UInt<5>(0h11), 3) node _T_2237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2236) node _T_2238 = bits(_T_2237, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2238 node _T_2239 = eq(UInt<4>(0hc), idx_17) when _T_2239 : node _T_2240 = shl(UInt<5>(0h11), 3) node _T_2241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2240) node _T_2242 = bits(_T_2241, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2242 node _T_2243 = eq(UInt<4>(0hd), idx_17) when _T_2243 : node _T_2244 = shl(UInt<5>(0h11), 3) node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244) node _T_2246 = bits(_T_2245, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2246 node _T_2247 = eq(UInt<4>(0he), idx_17) when _T_2247 : node _T_2248 = shl(UInt<5>(0h11), 3) node _T_2249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2248) node _T_2250 = bits(_T_2249, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2250 node _T_2251 = eq(UInt<4>(0hf), idx_17) when _T_2251 : node _T_2252 = shl(UInt<5>(0h11), 3) node _T_2253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2252) node _T_2254 = bits(_T_2253, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2254 node _T_2255 = eq(UInt<5>(0h10), idx_17) when _T_2255 : node _T_2256 = shl(UInt<5>(0h11), 3) node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256) node _T_2258 = bits(_T_2257, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2258 node _T_2259 = eq(UInt<5>(0h11), idx_17) when _T_2259 : node _T_2260 = shl(UInt<5>(0h11), 3) node _T_2261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2260) node _T_2262 = bits(_T_2261, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2262 node _T_2263 = eq(UInt<5>(0h12), idx_17) when _T_2263 : node _T_2264 = shl(UInt<5>(0h11), 3) node _T_2265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2264) node _T_2266 = bits(_T_2265, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2266 node _T_2267 = eq(UInt<5>(0h13), idx_17) when _T_2267 : node _T_2268 = shl(UInt<5>(0h11), 3) node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268) node _T_2270 = bits(_T_2269, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2270 node _T_2271 = eq(UInt<5>(0h14), idx_17) when _T_2271 : node _T_2272 = shl(UInt<5>(0h11), 3) node _T_2273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2272) node _T_2274 = bits(_T_2273, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2274 node _T_2275 = eq(UInt<5>(0h15), idx_17) when _T_2275 : node _T_2276 = shl(UInt<5>(0h11), 3) node _T_2277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2276) node _T_2278 = bits(_T_2277, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2278 node _T_2279 = eq(UInt<5>(0h16), idx_17) when _T_2279 : node _T_2280 = shl(UInt<5>(0h11), 3) node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280) node _T_2282 = bits(_T_2281, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2282 node _T_2283 = eq(UInt<5>(0h17), idx_17) when _T_2283 : node _T_2284 = shl(UInt<5>(0h11), 3) node _T_2285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2284) node _T_2286 = bits(_T_2285, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2286 node _T_2287 = eq(UInt<5>(0h18), idx_17) when _T_2287 : node _T_2288 = shl(UInt<5>(0h11), 3) node _T_2289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2288) node _T_2290 = bits(_T_2289, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2290 node _T_2291 = eq(UInt<5>(0h19), idx_17) when _T_2291 : node _T_2292 = shl(UInt<5>(0h11), 3) node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292) node _T_2294 = bits(_T_2293, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2294 node _T_2295 = eq(UInt<5>(0h1a), idx_17) when _T_2295 : node _T_2296 = shl(UInt<5>(0h11), 3) node _T_2297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2296) node _T_2298 = bits(_T_2297, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2298 node _T_2299 = eq(UInt<5>(0h1b), idx_17) when _T_2299 : node _T_2300 = shl(UInt<5>(0h11), 3) node _T_2301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2300) node _T_2302 = bits(_T_2301, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2302 node _T_2303 = eq(UInt<5>(0h1c), idx_17) when _T_2303 : node _T_2304 = shl(UInt<5>(0h11), 3) node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304) node _T_2306 = bits(_T_2305, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2306 node _T_2307 = eq(UInt<5>(0h1d), idx_17) when _T_2307 : node _T_2308 = shl(UInt<5>(0h11), 3) node _T_2309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2308) node _T_2310 = bits(_T_2309, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2310 node _T_2311 = eq(UInt<5>(0h1e), idx_17) when _T_2311 : node _T_2312 = shl(UInt<5>(0h11), 3) node _T_2313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2312) node _T_2314 = bits(_T_2313, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2314 node _T_2315 = eq(UInt<5>(0h1f), idx_17) when _T_2315 : node _T_2316 = shl(UInt<5>(0h11), 3) node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316) node _T_2318 = bits(_T_2317, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2318 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_2319 = eq(UInt<1>(0h0), idx_18) when _T_2319 : node _T_2320 = shl(UInt<5>(0h12), 3) node _T_2321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2320) node _T_2322 = bits(_T_2321, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2322 node _T_2323 = eq(UInt<1>(0h1), idx_18) when _T_2323 : node _T_2324 = shl(UInt<5>(0h12), 3) node _T_2325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2324) node _T_2326 = bits(_T_2325, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2326 node _T_2327 = eq(UInt<2>(0h2), idx_18) when _T_2327 : node _T_2328 = shl(UInt<5>(0h12), 3) node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328) node _T_2330 = bits(_T_2329, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2330 node _T_2331 = eq(UInt<2>(0h3), idx_18) when _T_2331 : node _T_2332 = shl(UInt<5>(0h12), 3) node _T_2333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2332) node _T_2334 = bits(_T_2333, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2334 node _T_2335 = eq(UInt<3>(0h4), idx_18) when _T_2335 : node _T_2336 = shl(UInt<5>(0h12), 3) node _T_2337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2336) node _T_2338 = bits(_T_2337, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2338 node _T_2339 = eq(UInt<3>(0h5), idx_18) when _T_2339 : node _T_2340 = shl(UInt<5>(0h12), 3) node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340) node _T_2342 = bits(_T_2341, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2342 node _T_2343 = eq(UInt<3>(0h6), idx_18) when _T_2343 : node _T_2344 = shl(UInt<5>(0h12), 3) node _T_2345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2344) node _T_2346 = bits(_T_2345, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2346 node _T_2347 = eq(UInt<3>(0h7), idx_18) when _T_2347 : node _T_2348 = shl(UInt<5>(0h12), 3) node _T_2349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2348) node _T_2350 = bits(_T_2349, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2350 node _T_2351 = eq(UInt<4>(0h8), idx_18) when _T_2351 : node _T_2352 = shl(UInt<5>(0h12), 3) node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352) node _T_2354 = bits(_T_2353, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2354 node _T_2355 = eq(UInt<4>(0h9), idx_18) when _T_2355 : node _T_2356 = shl(UInt<5>(0h12), 3) node _T_2357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2356) node _T_2358 = bits(_T_2357, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2358 node _T_2359 = eq(UInt<4>(0ha), idx_18) when _T_2359 : node _T_2360 = shl(UInt<5>(0h12), 3) node _T_2361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2360) node _T_2362 = bits(_T_2361, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2362 node _T_2363 = eq(UInt<4>(0hb), idx_18) when _T_2363 : node _T_2364 = shl(UInt<5>(0h12), 3) node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364) node _T_2366 = bits(_T_2365, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2366 node _T_2367 = eq(UInt<4>(0hc), idx_18) when _T_2367 : node _T_2368 = shl(UInt<5>(0h12), 3) node _T_2369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2368) node _T_2370 = bits(_T_2369, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2370 node _T_2371 = eq(UInt<4>(0hd), idx_18) when _T_2371 : node _T_2372 = shl(UInt<5>(0h12), 3) node _T_2373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2372) node _T_2374 = bits(_T_2373, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2374 node _T_2375 = eq(UInt<4>(0he), idx_18) when _T_2375 : node _T_2376 = shl(UInt<5>(0h12), 3) node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376) node _T_2378 = bits(_T_2377, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2378 node _T_2379 = eq(UInt<4>(0hf), idx_18) when _T_2379 : node _T_2380 = shl(UInt<5>(0h12), 3) node _T_2381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2380) node _T_2382 = bits(_T_2381, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2382 node _T_2383 = eq(UInt<5>(0h10), idx_18) when _T_2383 : node _T_2384 = shl(UInt<5>(0h12), 3) node _T_2385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2384) node _T_2386 = bits(_T_2385, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2386 node _T_2387 = eq(UInt<5>(0h11), idx_18) when _T_2387 : node _T_2388 = shl(UInt<5>(0h12), 3) node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388) node _T_2390 = bits(_T_2389, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2390 node _T_2391 = eq(UInt<5>(0h12), idx_18) when _T_2391 : node _T_2392 = shl(UInt<5>(0h12), 3) node _T_2393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2392) node _T_2394 = bits(_T_2393, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2394 node _T_2395 = eq(UInt<5>(0h13), idx_18) when _T_2395 : node _T_2396 = shl(UInt<5>(0h12), 3) node _T_2397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2396) node _T_2398 = bits(_T_2397, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2398 node _T_2399 = eq(UInt<5>(0h14), idx_18) when _T_2399 : node _T_2400 = shl(UInt<5>(0h12), 3) node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400) node _T_2402 = bits(_T_2401, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2402 node _T_2403 = eq(UInt<5>(0h15), idx_18) when _T_2403 : node _T_2404 = shl(UInt<5>(0h12), 3) node _T_2405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2404) node _T_2406 = bits(_T_2405, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2406 node _T_2407 = eq(UInt<5>(0h16), idx_18) when _T_2407 : node _T_2408 = shl(UInt<5>(0h12), 3) node _T_2409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2408) node _T_2410 = bits(_T_2409, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2410 node _T_2411 = eq(UInt<5>(0h17), idx_18) when _T_2411 : node _T_2412 = shl(UInt<5>(0h12), 3) node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412) node _T_2414 = bits(_T_2413, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2414 node _T_2415 = eq(UInt<5>(0h18), idx_18) when _T_2415 : node _T_2416 = shl(UInt<5>(0h12), 3) node _T_2417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2416) node _T_2418 = bits(_T_2417, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2418 node _T_2419 = eq(UInt<5>(0h19), idx_18) when _T_2419 : node _T_2420 = shl(UInt<5>(0h12), 3) node _T_2421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2420) node _T_2422 = bits(_T_2421, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2422 node _T_2423 = eq(UInt<5>(0h1a), idx_18) when _T_2423 : node _T_2424 = shl(UInt<5>(0h12), 3) node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424) node _T_2426 = bits(_T_2425, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2426 node _T_2427 = eq(UInt<5>(0h1b), idx_18) when _T_2427 : node _T_2428 = shl(UInt<5>(0h12), 3) node _T_2429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2428) node _T_2430 = bits(_T_2429, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2430 node _T_2431 = eq(UInt<5>(0h1c), idx_18) when _T_2431 : node _T_2432 = shl(UInt<5>(0h12), 3) node _T_2433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2432) node _T_2434 = bits(_T_2433, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2434 node _T_2435 = eq(UInt<5>(0h1d), idx_18) when _T_2435 : node _T_2436 = shl(UInt<5>(0h12), 3) node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436) node _T_2438 = bits(_T_2437, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2438 node _T_2439 = eq(UInt<5>(0h1e), idx_18) when _T_2439 : node _T_2440 = shl(UInt<5>(0h12), 3) node _T_2441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2440) node _T_2442 = bits(_T_2441, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2442 node _T_2443 = eq(UInt<5>(0h1f), idx_18) when _T_2443 : node _T_2444 = shl(UInt<5>(0h12), 3) node _T_2445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2444) node _T_2446 = bits(_T_2445, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2446 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_2447 = eq(UInt<1>(0h0), idx_19) when _T_2447 : node _T_2448 = shl(UInt<5>(0h13), 3) node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448) node _T_2450 = bits(_T_2449, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2450 node _T_2451 = eq(UInt<1>(0h1), idx_19) when _T_2451 : node _T_2452 = shl(UInt<5>(0h13), 3) node _T_2453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2452) node _T_2454 = bits(_T_2453, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2454 node _T_2455 = eq(UInt<2>(0h2), idx_19) when _T_2455 : node _T_2456 = shl(UInt<5>(0h13), 3) node _T_2457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2456) node _T_2458 = bits(_T_2457, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2458 node _T_2459 = eq(UInt<2>(0h3), idx_19) when _T_2459 : node _T_2460 = shl(UInt<5>(0h13), 3) node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460) node _T_2462 = bits(_T_2461, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2462 node _T_2463 = eq(UInt<3>(0h4), idx_19) when _T_2463 : node _T_2464 = shl(UInt<5>(0h13), 3) node _T_2465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2464) node _T_2466 = bits(_T_2465, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2466 node _T_2467 = eq(UInt<3>(0h5), idx_19) when _T_2467 : node _T_2468 = shl(UInt<5>(0h13), 3) node _T_2469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2468) node _T_2470 = bits(_T_2469, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2470 node _T_2471 = eq(UInt<3>(0h6), idx_19) when _T_2471 : node _T_2472 = shl(UInt<5>(0h13), 3) node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472) node _T_2474 = bits(_T_2473, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2474 node _T_2475 = eq(UInt<3>(0h7), idx_19) when _T_2475 : node _T_2476 = shl(UInt<5>(0h13), 3) node _T_2477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2476) node _T_2478 = bits(_T_2477, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2478 node _T_2479 = eq(UInt<4>(0h8), idx_19) when _T_2479 : node _T_2480 = shl(UInt<5>(0h13), 3) node _T_2481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2480) node _T_2482 = bits(_T_2481, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2482 node _T_2483 = eq(UInt<4>(0h9), idx_19) when _T_2483 : node _T_2484 = shl(UInt<5>(0h13), 3) node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484) node _T_2486 = bits(_T_2485, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2486 node _T_2487 = eq(UInt<4>(0ha), idx_19) when _T_2487 : node _T_2488 = shl(UInt<5>(0h13), 3) node _T_2489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2488) node _T_2490 = bits(_T_2489, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2490 node _T_2491 = eq(UInt<4>(0hb), idx_19) when _T_2491 : node _T_2492 = shl(UInt<5>(0h13), 3) node _T_2493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2492) node _T_2494 = bits(_T_2493, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2494 node _T_2495 = eq(UInt<4>(0hc), idx_19) when _T_2495 : node _T_2496 = shl(UInt<5>(0h13), 3) node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496) node _T_2498 = bits(_T_2497, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2498 node _T_2499 = eq(UInt<4>(0hd), idx_19) when _T_2499 : node _T_2500 = shl(UInt<5>(0h13), 3) node _T_2501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2500) node _T_2502 = bits(_T_2501, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2502 node _T_2503 = eq(UInt<4>(0he), idx_19) when _T_2503 : node _T_2504 = shl(UInt<5>(0h13), 3) node _T_2505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2504) node _T_2506 = bits(_T_2505, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2506 node _T_2507 = eq(UInt<4>(0hf), idx_19) when _T_2507 : node _T_2508 = shl(UInt<5>(0h13), 3) node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508) node _T_2510 = bits(_T_2509, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2510 node _T_2511 = eq(UInt<5>(0h10), idx_19) when _T_2511 : node _T_2512 = shl(UInt<5>(0h13), 3) node _T_2513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2512) node _T_2514 = bits(_T_2513, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2514 node _T_2515 = eq(UInt<5>(0h11), idx_19) when _T_2515 : node _T_2516 = shl(UInt<5>(0h13), 3) node _T_2517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2516) node _T_2518 = bits(_T_2517, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2518 node _T_2519 = eq(UInt<5>(0h12), idx_19) when _T_2519 : node _T_2520 = shl(UInt<5>(0h13), 3) node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520) node _T_2522 = bits(_T_2521, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2522 node _T_2523 = eq(UInt<5>(0h13), idx_19) when _T_2523 : node _T_2524 = shl(UInt<5>(0h13), 3) node _T_2525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2524) node _T_2526 = bits(_T_2525, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2526 node _T_2527 = eq(UInt<5>(0h14), idx_19) when _T_2527 : node _T_2528 = shl(UInt<5>(0h13), 3) node _T_2529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2528) node _T_2530 = bits(_T_2529, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2530 node _T_2531 = eq(UInt<5>(0h15), idx_19) when _T_2531 : node _T_2532 = shl(UInt<5>(0h13), 3) node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532) node _T_2534 = bits(_T_2533, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2534 node _T_2535 = eq(UInt<5>(0h16), idx_19) when _T_2535 : node _T_2536 = shl(UInt<5>(0h13), 3) node _T_2537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2536) node _T_2538 = bits(_T_2537, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2538 node _T_2539 = eq(UInt<5>(0h17), idx_19) when _T_2539 : node _T_2540 = shl(UInt<5>(0h13), 3) node _T_2541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2540) node _T_2542 = bits(_T_2541, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2542 node _T_2543 = eq(UInt<5>(0h18), idx_19) when _T_2543 : node _T_2544 = shl(UInt<5>(0h13), 3) node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544) node _T_2546 = bits(_T_2545, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2546 node _T_2547 = eq(UInt<5>(0h19), idx_19) when _T_2547 : node _T_2548 = shl(UInt<5>(0h13), 3) node _T_2549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2548) node _T_2550 = bits(_T_2549, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2550 node _T_2551 = eq(UInt<5>(0h1a), idx_19) when _T_2551 : node _T_2552 = shl(UInt<5>(0h13), 3) node _T_2553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2552) node _T_2554 = bits(_T_2553, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2554 node _T_2555 = eq(UInt<5>(0h1b), idx_19) when _T_2555 : node _T_2556 = shl(UInt<5>(0h13), 3) node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556) node _T_2558 = bits(_T_2557, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2558 node _T_2559 = eq(UInt<5>(0h1c), idx_19) when _T_2559 : node _T_2560 = shl(UInt<5>(0h13), 3) node _T_2561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2560) node _T_2562 = bits(_T_2561, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2562 node _T_2563 = eq(UInt<5>(0h1d), idx_19) when _T_2563 : node _T_2564 = shl(UInt<5>(0h13), 3) node _T_2565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2564) node _T_2566 = bits(_T_2565, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2566 node _T_2567 = eq(UInt<5>(0h1e), idx_19) when _T_2567 : node _T_2568 = shl(UInt<5>(0h13), 3) node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568) node _T_2570 = bits(_T_2569, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2570 node _T_2571 = eq(UInt<5>(0h1f), idx_19) when _T_2571 : node _T_2572 = shl(UInt<5>(0h13), 3) node _T_2573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2572) node _T_2574 = bits(_T_2573, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2574 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_2575 = eq(UInt<1>(0h0), idx_20) when _T_2575 : node _T_2576 = shl(UInt<5>(0h14), 3) node _T_2577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2576) node _T_2578 = bits(_T_2577, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2578 node _T_2579 = eq(UInt<1>(0h1), idx_20) when _T_2579 : node _T_2580 = shl(UInt<5>(0h14), 3) node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580) node _T_2582 = bits(_T_2581, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2582 node _T_2583 = eq(UInt<2>(0h2), idx_20) when _T_2583 : node _T_2584 = shl(UInt<5>(0h14), 3) node _T_2585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2584) node _T_2586 = bits(_T_2585, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2586 node _T_2587 = eq(UInt<2>(0h3), idx_20) when _T_2587 : node _T_2588 = shl(UInt<5>(0h14), 3) node _T_2589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2588) node _T_2590 = bits(_T_2589, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2590 node _T_2591 = eq(UInt<3>(0h4), idx_20) when _T_2591 : node _T_2592 = shl(UInt<5>(0h14), 3) node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592) node _T_2594 = bits(_T_2593, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2594 node _T_2595 = eq(UInt<3>(0h5), idx_20) when _T_2595 : node _T_2596 = shl(UInt<5>(0h14), 3) node _T_2597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2596) node _T_2598 = bits(_T_2597, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2598 node _T_2599 = eq(UInt<3>(0h6), idx_20) when _T_2599 : node _T_2600 = shl(UInt<5>(0h14), 3) node _T_2601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2600) node _T_2602 = bits(_T_2601, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2602 node _T_2603 = eq(UInt<3>(0h7), idx_20) when _T_2603 : node _T_2604 = shl(UInt<5>(0h14), 3) node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604) node _T_2606 = bits(_T_2605, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2606 node _T_2607 = eq(UInt<4>(0h8), idx_20) when _T_2607 : node _T_2608 = shl(UInt<5>(0h14), 3) node _T_2609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2608) node _T_2610 = bits(_T_2609, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2610 node _T_2611 = eq(UInt<4>(0h9), idx_20) when _T_2611 : node _T_2612 = shl(UInt<5>(0h14), 3) node _T_2613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2612) node _T_2614 = bits(_T_2613, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2614 node _T_2615 = eq(UInt<4>(0ha), idx_20) when _T_2615 : node _T_2616 = shl(UInt<5>(0h14), 3) node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616) node _T_2618 = bits(_T_2617, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2618 node _T_2619 = eq(UInt<4>(0hb), idx_20) when _T_2619 : node _T_2620 = shl(UInt<5>(0h14), 3) node _T_2621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2620) node _T_2622 = bits(_T_2621, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2622 node _T_2623 = eq(UInt<4>(0hc), idx_20) when _T_2623 : node _T_2624 = shl(UInt<5>(0h14), 3) node _T_2625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2624) node _T_2626 = bits(_T_2625, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2626 node _T_2627 = eq(UInt<4>(0hd), idx_20) when _T_2627 : node _T_2628 = shl(UInt<5>(0h14), 3) node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628) node _T_2630 = bits(_T_2629, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2630 node _T_2631 = eq(UInt<4>(0he), idx_20) when _T_2631 : node _T_2632 = shl(UInt<5>(0h14), 3) node _T_2633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2632) node _T_2634 = bits(_T_2633, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2634 node _T_2635 = eq(UInt<4>(0hf), idx_20) when _T_2635 : node _T_2636 = shl(UInt<5>(0h14), 3) node _T_2637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2636) node _T_2638 = bits(_T_2637, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2638 node _T_2639 = eq(UInt<5>(0h10), idx_20) when _T_2639 : node _T_2640 = shl(UInt<5>(0h14), 3) node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640) node _T_2642 = bits(_T_2641, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2642 node _T_2643 = eq(UInt<5>(0h11), idx_20) when _T_2643 : node _T_2644 = shl(UInt<5>(0h14), 3) node _T_2645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2644) node _T_2646 = bits(_T_2645, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2646 node _T_2647 = eq(UInt<5>(0h12), idx_20) when _T_2647 : node _T_2648 = shl(UInt<5>(0h14), 3) node _T_2649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2648) node _T_2650 = bits(_T_2649, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2650 node _T_2651 = eq(UInt<5>(0h13), idx_20) when _T_2651 : node _T_2652 = shl(UInt<5>(0h14), 3) node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652) node _T_2654 = bits(_T_2653, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2654 node _T_2655 = eq(UInt<5>(0h14), idx_20) when _T_2655 : node _T_2656 = shl(UInt<5>(0h14), 3) node _T_2657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2656) node _T_2658 = bits(_T_2657, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2658 node _T_2659 = eq(UInt<5>(0h15), idx_20) when _T_2659 : node _T_2660 = shl(UInt<5>(0h14), 3) node _T_2661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2660) node _T_2662 = bits(_T_2661, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2662 node _T_2663 = eq(UInt<5>(0h16), idx_20) when _T_2663 : node _T_2664 = shl(UInt<5>(0h14), 3) node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664) node _T_2666 = bits(_T_2665, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2666 node _T_2667 = eq(UInt<5>(0h17), idx_20) when _T_2667 : node _T_2668 = shl(UInt<5>(0h14), 3) node _T_2669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2668) node _T_2670 = bits(_T_2669, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2670 node _T_2671 = eq(UInt<5>(0h18), idx_20) when _T_2671 : node _T_2672 = shl(UInt<5>(0h14), 3) node _T_2673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2672) node _T_2674 = bits(_T_2673, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2674 node _T_2675 = eq(UInt<5>(0h19), idx_20) when _T_2675 : node _T_2676 = shl(UInt<5>(0h14), 3) node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676) node _T_2678 = bits(_T_2677, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2678 node _T_2679 = eq(UInt<5>(0h1a), idx_20) when _T_2679 : node _T_2680 = shl(UInt<5>(0h14), 3) node _T_2681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2680) node _T_2682 = bits(_T_2681, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2682 node _T_2683 = eq(UInt<5>(0h1b), idx_20) when _T_2683 : node _T_2684 = shl(UInt<5>(0h14), 3) node _T_2685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2684) node _T_2686 = bits(_T_2685, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2686 node _T_2687 = eq(UInt<5>(0h1c), idx_20) when _T_2687 : node _T_2688 = shl(UInt<5>(0h14), 3) node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688) node _T_2690 = bits(_T_2689, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2690 node _T_2691 = eq(UInt<5>(0h1d), idx_20) when _T_2691 : node _T_2692 = shl(UInt<5>(0h14), 3) node _T_2693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2692) node _T_2694 = bits(_T_2693, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2694 node _T_2695 = eq(UInt<5>(0h1e), idx_20) when _T_2695 : node _T_2696 = shl(UInt<5>(0h14), 3) node _T_2697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2696) node _T_2698 = bits(_T_2697, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2698 node _T_2699 = eq(UInt<5>(0h1f), idx_20) when _T_2699 : node _T_2700 = shl(UInt<5>(0h14), 3) node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700) node _T_2702 = bits(_T_2701, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2702 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_2703 = eq(UInt<1>(0h0), idx_21) when _T_2703 : node _T_2704 = shl(UInt<5>(0h15), 3) node _T_2705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2704) node _T_2706 = bits(_T_2705, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2706 node _T_2707 = eq(UInt<1>(0h1), idx_21) when _T_2707 : node _T_2708 = shl(UInt<5>(0h15), 3) node _T_2709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2708) node _T_2710 = bits(_T_2709, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2710 node _T_2711 = eq(UInt<2>(0h2), idx_21) when _T_2711 : node _T_2712 = shl(UInt<5>(0h15), 3) node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712) node _T_2714 = bits(_T_2713, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2714 node _T_2715 = eq(UInt<2>(0h3), idx_21) when _T_2715 : node _T_2716 = shl(UInt<5>(0h15), 3) node _T_2717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2716) node _T_2718 = bits(_T_2717, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2718 node _T_2719 = eq(UInt<3>(0h4), idx_21) when _T_2719 : node _T_2720 = shl(UInt<5>(0h15), 3) node _T_2721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2720) node _T_2722 = bits(_T_2721, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2722 node _T_2723 = eq(UInt<3>(0h5), idx_21) when _T_2723 : node _T_2724 = shl(UInt<5>(0h15), 3) node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724) node _T_2726 = bits(_T_2725, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2726 node _T_2727 = eq(UInt<3>(0h6), idx_21) when _T_2727 : node _T_2728 = shl(UInt<5>(0h15), 3) node _T_2729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2728) node _T_2730 = bits(_T_2729, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2730 node _T_2731 = eq(UInt<3>(0h7), idx_21) when _T_2731 : node _T_2732 = shl(UInt<5>(0h15), 3) node _T_2733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2732) node _T_2734 = bits(_T_2733, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2734 node _T_2735 = eq(UInt<4>(0h8), idx_21) when _T_2735 : node _T_2736 = shl(UInt<5>(0h15), 3) node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736) node _T_2738 = bits(_T_2737, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2738 node _T_2739 = eq(UInt<4>(0h9), idx_21) when _T_2739 : node _T_2740 = shl(UInt<5>(0h15), 3) node _T_2741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2740) node _T_2742 = bits(_T_2741, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2742 node _T_2743 = eq(UInt<4>(0ha), idx_21) when _T_2743 : node _T_2744 = shl(UInt<5>(0h15), 3) node _T_2745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2744) node _T_2746 = bits(_T_2745, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2746 node _T_2747 = eq(UInt<4>(0hb), idx_21) when _T_2747 : node _T_2748 = shl(UInt<5>(0h15), 3) node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748) node _T_2750 = bits(_T_2749, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2750 node _T_2751 = eq(UInt<4>(0hc), idx_21) when _T_2751 : node _T_2752 = shl(UInt<5>(0h15), 3) node _T_2753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2752) node _T_2754 = bits(_T_2753, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2754 node _T_2755 = eq(UInt<4>(0hd), idx_21) when _T_2755 : node _T_2756 = shl(UInt<5>(0h15), 3) node _T_2757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2756) node _T_2758 = bits(_T_2757, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2758 node _T_2759 = eq(UInt<4>(0he), idx_21) when _T_2759 : node _T_2760 = shl(UInt<5>(0h15), 3) node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760) node _T_2762 = bits(_T_2761, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2762 node _T_2763 = eq(UInt<4>(0hf), idx_21) when _T_2763 : node _T_2764 = shl(UInt<5>(0h15), 3) node _T_2765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2764) node _T_2766 = bits(_T_2765, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2766 node _T_2767 = eq(UInt<5>(0h10), idx_21) when _T_2767 : node _T_2768 = shl(UInt<5>(0h15), 3) node _T_2769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2768) node _T_2770 = bits(_T_2769, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2770 node _T_2771 = eq(UInt<5>(0h11), idx_21) when _T_2771 : node _T_2772 = shl(UInt<5>(0h15), 3) node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772) node _T_2774 = bits(_T_2773, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2774 node _T_2775 = eq(UInt<5>(0h12), idx_21) when _T_2775 : node _T_2776 = shl(UInt<5>(0h15), 3) node _T_2777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2776) node _T_2778 = bits(_T_2777, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2778 node _T_2779 = eq(UInt<5>(0h13), idx_21) when _T_2779 : node _T_2780 = shl(UInt<5>(0h15), 3) node _T_2781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2780) node _T_2782 = bits(_T_2781, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2782 node _T_2783 = eq(UInt<5>(0h14), idx_21) when _T_2783 : node _T_2784 = shl(UInt<5>(0h15), 3) node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784) node _T_2786 = bits(_T_2785, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2786 node _T_2787 = eq(UInt<5>(0h15), idx_21) when _T_2787 : node _T_2788 = shl(UInt<5>(0h15), 3) node _T_2789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2788) node _T_2790 = bits(_T_2789, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2790 node _T_2791 = eq(UInt<5>(0h16), idx_21) when _T_2791 : node _T_2792 = shl(UInt<5>(0h15), 3) node _T_2793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2792) node _T_2794 = bits(_T_2793, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2794 node _T_2795 = eq(UInt<5>(0h17), idx_21) when _T_2795 : node _T_2796 = shl(UInt<5>(0h15), 3) node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796) node _T_2798 = bits(_T_2797, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2798 node _T_2799 = eq(UInt<5>(0h18), idx_21) when _T_2799 : node _T_2800 = shl(UInt<5>(0h15), 3) node _T_2801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2800) node _T_2802 = bits(_T_2801, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2802 node _T_2803 = eq(UInt<5>(0h19), idx_21) when _T_2803 : node _T_2804 = shl(UInt<5>(0h15), 3) node _T_2805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2804) node _T_2806 = bits(_T_2805, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2806 node _T_2807 = eq(UInt<5>(0h1a), idx_21) when _T_2807 : node _T_2808 = shl(UInt<5>(0h15), 3) node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808) node _T_2810 = bits(_T_2809, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2810 node _T_2811 = eq(UInt<5>(0h1b), idx_21) when _T_2811 : node _T_2812 = shl(UInt<5>(0h15), 3) node _T_2813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2812) node _T_2814 = bits(_T_2813, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2814 node _T_2815 = eq(UInt<5>(0h1c), idx_21) when _T_2815 : node _T_2816 = shl(UInt<5>(0h15), 3) node _T_2817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2816) node _T_2818 = bits(_T_2817, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2818 node _T_2819 = eq(UInt<5>(0h1d), idx_21) when _T_2819 : node _T_2820 = shl(UInt<5>(0h15), 3) node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820) node _T_2822 = bits(_T_2821, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2822 node _T_2823 = eq(UInt<5>(0h1e), idx_21) when _T_2823 : node _T_2824 = shl(UInt<5>(0h15), 3) node _T_2825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2824) node _T_2826 = bits(_T_2825, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2826 node _T_2827 = eq(UInt<5>(0h1f), idx_21) when _T_2827 : node _T_2828 = shl(UInt<5>(0h15), 3) node _T_2829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2828) node _T_2830 = bits(_T_2829, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2830 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_2831 = eq(UInt<1>(0h0), idx_22) when _T_2831 : node _T_2832 = shl(UInt<5>(0h16), 3) node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832) node _T_2834 = bits(_T_2833, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2834 node _T_2835 = eq(UInt<1>(0h1), idx_22) when _T_2835 : node _T_2836 = shl(UInt<5>(0h16), 3) node _T_2837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2836) node _T_2838 = bits(_T_2837, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2838 node _T_2839 = eq(UInt<2>(0h2), idx_22) when _T_2839 : node _T_2840 = shl(UInt<5>(0h16), 3) node _T_2841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2840) node _T_2842 = bits(_T_2841, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2842 node _T_2843 = eq(UInt<2>(0h3), idx_22) when _T_2843 : node _T_2844 = shl(UInt<5>(0h16), 3) node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844) node _T_2846 = bits(_T_2845, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2846 node _T_2847 = eq(UInt<3>(0h4), idx_22) when _T_2847 : node _T_2848 = shl(UInt<5>(0h16), 3) node _T_2849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2848) node _T_2850 = bits(_T_2849, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2850 node _T_2851 = eq(UInt<3>(0h5), idx_22) when _T_2851 : node _T_2852 = shl(UInt<5>(0h16), 3) node _T_2853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2852) node _T_2854 = bits(_T_2853, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2854 node _T_2855 = eq(UInt<3>(0h6), idx_22) when _T_2855 : node _T_2856 = shl(UInt<5>(0h16), 3) node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856) node _T_2858 = bits(_T_2857, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2858 node _T_2859 = eq(UInt<3>(0h7), idx_22) when _T_2859 : node _T_2860 = shl(UInt<5>(0h16), 3) node _T_2861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2860) node _T_2862 = bits(_T_2861, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2862 node _T_2863 = eq(UInt<4>(0h8), idx_22) when _T_2863 : node _T_2864 = shl(UInt<5>(0h16), 3) node _T_2865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2864) node _T_2866 = bits(_T_2865, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2866 node _T_2867 = eq(UInt<4>(0h9), idx_22) when _T_2867 : node _T_2868 = shl(UInt<5>(0h16), 3) node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868) node _T_2870 = bits(_T_2869, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2870 node _T_2871 = eq(UInt<4>(0ha), idx_22) when _T_2871 : node _T_2872 = shl(UInt<5>(0h16), 3) node _T_2873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2872) node _T_2874 = bits(_T_2873, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_2874 node _T_2875 = eq(UInt<4>(0hb), idx_22) when _T_2875 : node _T_2876 = shl(UInt<5>(0h16), 3) node _T_2877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2876) node _T_2878 = bits(_T_2877, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_2878 node _T_2879 = eq(UInt<4>(0hc), idx_22) when _T_2879 : node _T_2880 = shl(UInt<5>(0h16), 3) node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880) node _T_2882 = bits(_T_2881, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_2882 node _T_2883 = eq(UInt<4>(0hd), idx_22) when _T_2883 : node _T_2884 = shl(UInt<5>(0h16), 3) node _T_2885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2884) node _T_2886 = bits(_T_2885, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_2886 node _T_2887 = eq(UInt<4>(0he), idx_22) when _T_2887 : node _T_2888 = shl(UInt<5>(0h16), 3) node _T_2889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2888) node _T_2890 = bits(_T_2889, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_2890 node _T_2891 = eq(UInt<4>(0hf), idx_22) when _T_2891 : node _T_2892 = shl(UInt<5>(0h16), 3) node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892) node _T_2894 = bits(_T_2893, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_2894 node _T_2895 = eq(UInt<5>(0h10), idx_22) when _T_2895 : node _T_2896 = shl(UInt<5>(0h16), 3) node _T_2897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2896) node _T_2898 = bits(_T_2897, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_2898 node _T_2899 = eq(UInt<5>(0h11), idx_22) when _T_2899 : node _T_2900 = shl(UInt<5>(0h16), 3) node _T_2901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2900) node _T_2902 = bits(_T_2901, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_2902 node _T_2903 = eq(UInt<5>(0h12), idx_22) when _T_2903 : node _T_2904 = shl(UInt<5>(0h16), 3) node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904) node _T_2906 = bits(_T_2905, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_2906 node _T_2907 = eq(UInt<5>(0h13), idx_22) when _T_2907 : node _T_2908 = shl(UInt<5>(0h16), 3) node _T_2909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2908) node _T_2910 = bits(_T_2909, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_2910 node _T_2911 = eq(UInt<5>(0h14), idx_22) when _T_2911 : node _T_2912 = shl(UInt<5>(0h16), 3) node _T_2913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2912) node _T_2914 = bits(_T_2913, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_2914 node _T_2915 = eq(UInt<5>(0h15), idx_22) when _T_2915 : node _T_2916 = shl(UInt<5>(0h16), 3) node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916) node _T_2918 = bits(_T_2917, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_2918 node _T_2919 = eq(UInt<5>(0h16), idx_22) when _T_2919 : node _T_2920 = shl(UInt<5>(0h16), 3) node _T_2921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2920) node _T_2922 = bits(_T_2921, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_2922 node _T_2923 = eq(UInt<5>(0h17), idx_22) when _T_2923 : node _T_2924 = shl(UInt<5>(0h16), 3) node _T_2925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2924) node _T_2926 = bits(_T_2925, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_2926 node _T_2927 = eq(UInt<5>(0h18), idx_22) when _T_2927 : node _T_2928 = shl(UInt<5>(0h16), 3) node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928) node _T_2930 = bits(_T_2929, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_2930 node _T_2931 = eq(UInt<5>(0h19), idx_22) when _T_2931 : node _T_2932 = shl(UInt<5>(0h16), 3) node _T_2933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2932) node _T_2934 = bits(_T_2933, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_2934 node _T_2935 = eq(UInt<5>(0h1a), idx_22) when _T_2935 : node _T_2936 = shl(UInt<5>(0h16), 3) node _T_2937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2936) node _T_2938 = bits(_T_2937, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_2938 node _T_2939 = eq(UInt<5>(0h1b), idx_22) when _T_2939 : node _T_2940 = shl(UInt<5>(0h16), 3) node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940) node _T_2942 = bits(_T_2941, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_2942 node _T_2943 = eq(UInt<5>(0h1c), idx_22) when _T_2943 : node _T_2944 = shl(UInt<5>(0h16), 3) node _T_2945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2944) node _T_2946 = bits(_T_2945, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_2946 node _T_2947 = eq(UInt<5>(0h1d), idx_22) when _T_2947 : node _T_2948 = shl(UInt<5>(0h16), 3) node _T_2949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2948) node _T_2950 = bits(_T_2949, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_2950 node _T_2951 = eq(UInt<5>(0h1e), idx_22) when _T_2951 : node _T_2952 = shl(UInt<5>(0h16), 3) node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952) node _T_2954 = bits(_T_2953, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_2954 node _T_2955 = eq(UInt<5>(0h1f), idx_22) when _T_2955 : node _T_2956 = shl(UInt<5>(0h16), 3) node _T_2957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2956) node _T_2958 = bits(_T_2957, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_2958 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_2959 = eq(UInt<1>(0h0), idx_23) when _T_2959 : node _T_2960 = shl(UInt<5>(0h17), 3) node _T_2961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2960) node _T_2962 = bits(_T_2961, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_2962 node _T_2963 = eq(UInt<1>(0h1), idx_23) when _T_2963 : node _T_2964 = shl(UInt<5>(0h17), 3) node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964) node _T_2966 = bits(_T_2965, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_2966 node _T_2967 = eq(UInt<2>(0h2), idx_23) when _T_2967 : node _T_2968 = shl(UInt<5>(0h17), 3) node _T_2969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2968) node _T_2970 = bits(_T_2969, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_2970 node _T_2971 = eq(UInt<2>(0h3), idx_23) when _T_2971 : node _T_2972 = shl(UInt<5>(0h17), 3) node _T_2973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2972) node _T_2974 = bits(_T_2973, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_2974 node _T_2975 = eq(UInt<3>(0h4), idx_23) when _T_2975 : node _T_2976 = shl(UInt<5>(0h17), 3) node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976) node _T_2978 = bits(_T_2977, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_2978 node _T_2979 = eq(UInt<3>(0h5), idx_23) when _T_2979 : node _T_2980 = shl(UInt<5>(0h17), 3) node _T_2981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2980) node _T_2982 = bits(_T_2981, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_2982 node _T_2983 = eq(UInt<3>(0h6), idx_23) when _T_2983 : node _T_2984 = shl(UInt<5>(0h17), 3) node _T_2985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2984) node _T_2986 = bits(_T_2985, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_2986 node _T_2987 = eq(UInt<3>(0h7), idx_23) when _T_2987 : node _T_2988 = shl(UInt<5>(0h17), 3) node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988) node _T_2990 = bits(_T_2989, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_2990 node _T_2991 = eq(UInt<4>(0h8), idx_23) when _T_2991 : node _T_2992 = shl(UInt<5>(0h17), 3) node _T_2993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2992) node _T_2994 = bits(_T_2993, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_2994 node _T_2995 = eq(UInt<4>(0h9), idx_23) when _T_2995 : node _T_2996 = shl(UInt<5>(0h17), 3) node _T_2997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2996) node _T_2998 = bits(_T_2997, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_2998 node _T_2999 = eq(UInt<4>(0ha), idx_23) when _T_2999 : node _T_3000 = shl(UInt<5>(0h17), 3) node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000) node _T_3002 = bits(_T_3001, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3002 node _T_3003 = eq(UInt<4>(0hb), idx_23) when _T_3003 : node _T_3004 = shl(UInt<5>(0h17), 3) node _T_3005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3004) node _T_3006 = bits(_T_3005, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3006 node _T_3007 = eq(UInt<4>(0hc), idx_23) when _T_3007 : node _T_3008 = shl(UInt<5>(0h17), 3) node _T_3009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3008) node _T_3010 = bits(_T_3009, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3010 node _T_3011 = eq(UInt<4>(0hd), idx_23) when _T_3011 : node _T_3012 = shl(UInt<5>(0h17), 3) node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012) node _T_3014 = bits(_T_3013, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3014 node _T_3015 = eq(UInt<4>(0he), idx_23) when _T_3015 : node _T_3016 = shl(UInt<5>(0h17), 3) node _T_3017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3016) node _T_3018 = bits(_T_3017, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3018 node _T_3019 = eq(UInt<4>(0hf), idx_23) when _T_3019 : node _T_3020 = shl(UInt<5>(0h17), 3) node _T_3021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3020) node _T_3022 = bits(_T_3021, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3022 node _T_3023 = eq(UInt<5>(0h10), idx_23) when _T_3023 : node _T_3024 = shl(UInt<5>(0h17), 3) node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024) node _T_3026 = bits(_T_3025, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3026 node _T_3027 = eq(UInt<5>(0h11), idx_23) when _T_3027 : node _T_3028 = shl(UInt<5>(0h17), 3) node _T_3029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3028) node _T_3030 = bits(_T_3029, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3030 node _T_3031 = eq(UInt<5>(0h12), idx_23) when _T_3031 : node _T_3032 = shl(UInt<5>(0h17), 3) node _T_3033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3032) node _T_3034 = bits(_T_3033, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3034 node _T_3035 = eq(UInt<5>(0h13), idx_23) when _T_3035 : node _T_3036 = shl(UInt<5>(0h17), 3) node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036) node _T_3038 = bits(_T_3037, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3038 node _T_3039 = eq(UInt<5>(0h14), idx_23) when _T_3039 : node _T_3040 = shl(UInt<5>(0h17), 3) node _T_3041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3040) node _T_3042 = bits(_T_3041, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3042 node _T_3043 = eq(UInt<5>(0h15), idx_23) when _T_3043 : node _T_3044 = shl(UInt<5>(0h17), 3) node _T_3045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3044) node _T_3046 = bits(_T_3045, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3046 node _T_3047 = eq(UInt<5>(0h16), idx_23) when _T_3047 : node _T_3048 = shl(UInt<5>(0h17), 3) node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048) node _T_3050 = bits(_T_3049, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3050 node _T_3051 = eq(UInt<5>(0h17), idx_23) when _T_3051 : node _T_3052 = shl(UInt<5>(0h17), 3) node _T_3053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3052) node _T_3054 = bits(_T_3053, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3054 node _T_3055 = eq(UInt<5>(0h18), idx_23) when _T_3055 : node _T_3056 = shl(UInt<5>(0h17), 3) node _T_3057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3056) node _T_3058 = bits(_T_3057, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3058 node _T_3059 = eq(UInt<5>(0h19), idx_23) when _T_3059 : node _T_3060 = shl(UInt<5>(0h17), 3) node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060) node _T_3062 = bits(_T_3061, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3062 node _T_3063 = eq(UInt<5>(0h1a), idx_23) when _T_3063 : node _T_3064 = shl(UInt<5>(0h17), 3) node _T_3065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3064) node _T_3066 = bits(_T_3065, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3066 node _T_3067 = eq(UInt<5>(0h1b), idx_23) when _T_3067 : node _T_3068 = shl(UInt<5>(0h17), 3) node _T_3069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3068) node _T_3070 = bits(_T_3069, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3070 node _T_3071 = eq(UInt<5>(0h1c), idx_23) when _T_3071 : node _T_3072 = shl(UInt<5>(0h17), 3) node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072) node _T_3074 = bits(_T_3073, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3074 node _T_3075 = eq(UInt<5>(0h1d), idx_23) when _T_3075 : node _T_3076 = shl(UInt<5>(0h17), 3) node _T_3077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3076) node _T_3078 = bits(_T_3077, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3078 node _T_3079 = eq(UInt<5>(0h1e), idx_23) when _T_3079 : node _T_3080 = shl(UInt<5>(0h17), 3) node _T_3081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3080) node _T_3082 = bits(_T_3081, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3082 node _T_3083 = eq(UInt<5>(0h1f), idx_23) when _T_3083 : node _T_3084 = shl(UInt<5>(0h17), 3) node _T_3085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3084) node _T_3086 = bits(_T_3085, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3086 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_3087 = eq(UInt<1>(0h0), idx_24) when _T_3087 : node _T_3088 = shl(UInt<5>(0h18), 3) node _T_3089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3088) node _T_3090 = bits(_T_3089, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3090 node _T_3091 = eq(UInt<1>(0h1), idx_24) when _T_3091 : node _T_3092 = shl(UInt<5>(0h18), 3) node _T_3093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3092) node _T_3094 = bits(_T_3093, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3094 node _T_3095 = eq(UInt<2>(0h2), idx_24) when _T_3095 : node _T_3096 = shl(UInt<5>(0h18), 3) node _T_3097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3096) node _T_3098 = bits(_T_3097, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3098 node _T_3099 = eq(UInt<2>(0h3), idx_24) when _T_3099 : node _T_3100 = shl(UInt<5>(0h18), 3) node _T_3101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3100) node _T_3102 = bits(_T_3101, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3102 node _T_3103 = eq(UInt<3>(0h4), idx_24) when _T_3103 : node _T_3104 = shl(UInt<5>(0h18), 3) node _T_3105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3104) node _T_3106 = bits(_T_3105, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3106 node _T_3107 = eq(UInt<3>(0h5), idx_24) when _T_3107 : node _T_3108 = shl(UInt<5>(0h18), 3) node _T_3109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3108) node _T_3110 = bits(_T_3109, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3110 node _T_3111 = eq(UInt<3>(0h6), idx_24) when _T_3111 : node _T_3112 = shl(UInt<5>(0h18), 3) node _T_3113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3112) node _T_3114 = bits(_T_3113, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3114 node _T_3115 = eq(UInt<3>(0h7), idx_24) when _T_3115 : node _T_3116 = shl(UInt<5>(0h18), 3) node _T_3117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3116) node _T_3118 = bits(_T_3117, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3118 node _T_3119 = eq(UInt<4>(0h8), idx_24) when _T_3119 : node _T_3120 = shl(UInt<5>(0h18), 3) node _T_3121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3120) node _T_3122 = bits(_T_3121, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3122 node _T_3123 = eq(UInt<4>(0h9), idx_24) when _T_3123 : node _T_3124 = shl(UInt<5>(0h18), 3) node _T_3125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3124) node _T_3126 = bits(_T_3125, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3126 node _T_3127 = eq(UInt<4>(0ha), idx_24) when _T_3127 : node _T_3128 = shl(UInt<5>(0h18), 3) node _T_3129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3128) node _T_3130 = bits(_T_3129, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3130 node _T_3131 = eq(UInt<4>(0hb), idx_24) when _T_3131 : node _T_3132 = shl(UInt<5>(0h18), 3) node _T_3133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3132) node _T_3134 = bits(_T_3133, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3134 node _T_3135 = eq(UInt<4>(0hc), idx_24) when _T_3135 : node _T_3136 = shl(UInt<5>(0h18), 3) node _T_3137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3136) node _T_3138 = bits(_T_3137, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3138 node _T_3139 = eq(UInt<4>(0hd), idx_24) when _T_3139 : node _T_3140 = shl(UInt<5>(0h18), 3) node _T_3141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3140) node _T_3142 = bits(_T_3141, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3142 node _T_3143 = eq(UInt<4>(0he), idx_24) when _T_3143 : node _T_3144 = shl(UInt<5>(0h18), 3) node _T_3145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3144) node _T_3146 = bits(_T_3145, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3146 node _T_3147 = eq(UInt<4>(0hf), idx_24) when _T_3147 : node _T_3148 = shl(UInt<5>(0h18), 3) node _T_3149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3148) node _T_3150 = bits(_T_3149, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3150 node _T_3151 = eq(UInt<5>(0h10), idx_24) when _T_3151 : node _T_3152 = shl(UInt<5>(0h18), 3) node _T_3153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3152) node _T_3154 = bits(_T_3153, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3154 node _T_3155 = eq(UInt<5>(0h11), idx_24) when _T_3155 : node _T_3156 = shl(UInt<5>(0h18), 3) node _T_3157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3156) node _T_3158 = bits(_T_3157, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3158 node _T_3159 = eq(UInt<5>(0h12), idx_24) when _T_3159 : node _T_3160 = shl(UInt<5>(0h18), 3) node _T_3161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3160) node _T_3162 = bits(_T_3161, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3162 node _T_3163 = eq(UInt<5>(0h13), idx_24) when _T_3163 : node _T_3164 = shl(UInt<5>(0h18), 3) node _T_3165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3164) node _T_3166 = bits(_T_3165, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3166 node _T_3167 = eq(UInt<5>(0h14), idx_24) when _T_3167 : node _T_3168 = shl(UInt<5>(0h18), 3) node _T_3169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3168) node _T_3170 = bits(_T_3169, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3170 node _T_3171 = eq(UInt<5>(0h15), idx_24) when _T_3171 : node _T_3172 = shl(UInt<5>(0h18), 3) node _T_3173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3172) node _T_3174 = bits(_T_3173, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3174 node _T_3175 = eq(UInt<5>(0h16), idx_24) when _T_3175 : node _T_3176 = shl(UInt<5>(0h18), 3) node _T_3177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3176) node _T_3178 = bits(_T_3177, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3178 node _T_3179 = eq(UInt<5>(0h17), idx_24) when _T_3179 : node _T_3180 = shl(UInt<5>(0h18), 3) node _T_3181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3180) node _T_3182 = bits(_T_3181, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3182 node _T_3183 = eq(UInt<5>(0h18), idx_24) when _T_3183 : node _T_3184 = shl(UInt<5>(0h18), 3) node _T_3185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3184) node _T_3186 = bits(_T_3185, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3186 node _T_3187 = eq(UInt<5>(0h19), idx_24) when _T_3187 : node _T_3188 = shl(UInt<5>(0h18), 3) node _T_3189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3188) node _T_3190 = bits(_T_3189, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3190 node _T_3191 = eq(UInt<5>(0h1a), idx_24) when _T_3191 : node _T_3192 = shl(UInt<5>(0h18), 3) node _T_3193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3192) node _T_3194 = bits(_T_3193, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3194 node _T_3195 = eq(UInt<5>(0h1b), idx_24) when _T_3195 : node _T_3196 = shl(UInt<5>(0h18), 3) node _T_3197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3196) node _T_3198 = bits(_T_3197, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3198 node _T_3199 = eq(UInt<5>(0h1c), idx_24) when _T_3199 : node _T_3200 = shl(UInt<5>(0h18), 3) node _T_3201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3200) node _T_3202 = bits(_T_3201, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3202 node _T_3203 = eq(UInt<5>(0h1d), idx_24) when _T_3203 : node _T_3204 = shl(UInt<5>(0h18), 3) node _T_3205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3204) node _T_3206 = bits(_T_3205, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3206 node _T_3207 = eq(UInt<5>(0h1e), idx_24) when _T_3207 : node _T_3208 = shl(UInt<5>(0h18), 3) node _T_3209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3208) node _T_3210 = bits(_T_3209, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3210 node _T_3211 = eq(UInt<5>(0h1f), idx_24) when _T_3211 : node _T_3212 = shl(UInt<5>(0h18), 3) node _T_3213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3212) node _T_3214 = bits(_T_3213, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3214 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_3215 = eq(UInt<1>(0h0), idx_25) when _T_3215 : node _T_3216 = shl(UInt<5>(0h19), 3) node _T_3217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3216) node _T_3218 = bits(_T_3217, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3218 node _T_3219 = eq(UInt<1>(0h1), idx_25) when _T_3219 : node _T_3220 = shl(UInt<5>(0h19), 3) node _T_3221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3220) node _T_3222 = bits(_T_3221, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3222 node _T_3223 = eq(UInt<2>(0h2), idx_25) when _T_3223 : node _T_3224 = shl(UInt<5>(0h19), 3) node _T_3225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3224) node _T_3226 = bits(_T_3225, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3226 node _T_3227 = eq(UInt<2>(0h3), idx_25) when _T_3227 : node _T_3228 = shl(UInt<5>(0h19), 3) node _T_3229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3228) node _T_3230 = bits(_T_3229, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3230 node _T_3231 = eq(UInt<3>(0h4), idx_25) when _T_3231 : node _T_3232 = shl(UInt<5>(0h19), 3) node _T_3233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3232) node _T_3234 = bits(_T_3233, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3234 node _T_3235 = eq(UInt<3>(0h5), idx_25) when _T_3235 : node _T_3236 = shl(UInt<5>(0h19), 3) node _T_3237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3236) node _T_3238 = bits(_T_3237, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3238 node _T_3239 = eq(UInt<3>(0h6), idx_25) when _T_3239 : node _T_3240 = shl(UInt<5>(0h19), 3) node _T_3241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3240) node _T_3242 = bits(_T_3241, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3242 node _T_3243 = eq(UInt<3>(0h7), idx_25) when _T_3243 : node _T_3244 = shl(UInt<5>(0h19), 3) node _T_3245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3244) node _T_3246 = bits(_T_3245, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3246 node _T_3247 = eq(UInt<4>(0h8), idx_25) when _T_3247 : node _T_3248 = shl(UInt<5>(0h19), 3) node _T_3249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3248) node _T_3250 = bits(_T_3249, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3250 node _T_3251 = eq(UInt<4>(0h9), idx_25) when _T_3251 : node _T_3252 = shl(UInt<5>(0h19), 3) node _T_3253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3252) node _T_3254 = bits(_T_3253, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3254 node _T_3255 = eq(UInt<4>(0ha), idx_25) when _T_3255 : node _T_3256 = shl(UInt<5>(0h19), 3) node _T_3257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3256) node _T_3258 = bits(_T_3257, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3258 node _T_3259 = eq(UInt<4>(0hb), idx_25) when _T_3259 : node _T_3260 = shl(UInt<5>(0h19), 3) node _T_3261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3260) node _T_3262 = bits(_T_3261, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3262 node _T_3263 = eq(UInt<4>(0hc), idx_25) when _T_3263 : node _T_3264 = shl(UInt<5>(0h19), 3) node _T_3265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3264) node _T_3266 = bits(_T_3265, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3266 node _T_3267 = eq(UInt<4>(0hd), idx_25) when _T_3267 : node _T_3268 = shl(UInt<5>(0h19), 3) node _T_3269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3268) node _T_3270 = bits(_T_3269, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3270 node _T_3271 = eq(UInt<4>(0he), idx_25) when _T_3271 : node _T_3272 = shl(UInt<5>(0h19), 3) node _T_3273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3272) node _T_3274 = bits(_T_3273, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3274 node _T_3275 = eq(UInt<4>(0hf), idx_25) when _T_3275 : node _T_3276 = shl(UInt<5>(0h19), 3) node _T_3277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3276) node _T_3278 = bits(_T_3277, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3278 node _T_3279 = eq(UInt<5>(0h10), idx_25) when _T_3279 : node _T_3280 = shl(UInt<5>(0h19), 3) node _T_3281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3280) node _T_3282 = bits(_T_3281, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3282 node _T_3283 = eq(UInt<5>(0h11), idx_25) when _T_3283 : node _T_3284 = shl(UInt<5>(0h19), 3) node _T_3285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3284) node _T_3286 = bits(_T_3285, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3286 node _T_3287 = eq(UInt<5>(0h12), idx_25) when _T_3287 : node _T_3288 = shl(UInt<5>(0h19), 3) node _T_3289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3288) node _T_3290 = bits(_T_3289, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3290 node _T_3291 = eq(UInt<5>(0h13), idx_25) when _T_3291 : node _T_3292 = shl(UInt<5>(0h19), 3) node _T_3293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3292) node _T_3294 = bits(_T_3293, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3294 node _T_3295 = eq(UInt<5>(0h14), idx_25) when _T_3295 : node _T_3296 = shl(UInt<5>(0h19), 3) node _T_3297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3296) node _T_3298 = bits(_T_3297, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3298 node _T_3299 = eq(UInt<5>(0h15), idx_25) when _T_3299 : node _T_3300 = shl(UInt<5>(0h19), 3) node _T_3301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3300) node _T_3302 = bits(_T_3301, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3302 node _T_3303 = eq(UInt<5>(0h16), idx_25) when _T_3303 : node _T_3304 = shl(UInt<5>(0h19), 3) node _T_3305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3304) node _T_3306 = bits(_T_3305, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3306 node _T_3307 = eq(UInt<5>(0h17), idx_25) when _T_3307 : node _T_3308 = shl(UInt<5>(0h19), 3) node _T_3309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3308) node _T_3310 = bits(_T_3309, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3310 node _T_3311 = eq(UInt<5>(0h18), idx_25) when _T_3311 : node _T_3312 = shl(UInt<5>(0h19), 3) node _T_3313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3312) node _T_3314 = bits(_T_3313, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3314 node _T_3315 = eq(UInt<5>(0h19), idx_25) when _T_3315 : node _T_3316 = shl(UInt<5>(0h19), 3) node _T_3317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3316) node _T_3318 = bits(_T_3317, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3318 node _T_3319 = eq(UInt<5>(0h1a), idx_25) when _T_3319 : node _T_3320 = shl(UInt<5>(0h19), 3) node _T_3321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3320) node _T_3322 = bits(_T_3321, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3322 node _T_3323 = eq(UInt<5>(0h1b), idx_25) when _T_3323 : node _T_3324 = shl(UInt<5>(0h19), 3) node _T_3325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3324) node _T_3326 = bits(_T_3325, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3326 node _T_3327 = eq(UInt<5>(0h1c), idx_25) when _T_3327 : node _T_3328 = shl(UInt<5>(0h19), 3) node _T_3329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3328) node _T_3330 = bits(_T_3329, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3330 node _T_3331 = eq(UInt<5>(0h1d), idx_25) when _T_3331 : node _T_3332 = shl(UInt<5>(0h19), 3) node _T_3333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3332) node _T_3334 = bits(_T_3333, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3334 node _T_3335 = eq(UInt<5>(0h1e), idx_25) when _T_3335 : node _T_3336 = shl(UInt<5>(0h19), 3) node _T_3337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3336) node _T_3338 = bits(_T_3337, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3338 node _T_3339 = eq(UInt<5>(0h1f), idx_25) when _T_3339 : node _T_3340 = shl(UInt<5>(0h19), 3) node _T_3341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3340) node _T_3342 = bits(_T_3341, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3342 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_3343 = eq(UInt<1>(0h0), idx_26) when _T_3343 : node _T_3344 = shl(UInt<5>(0h1a), 3) node _T_3345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3344) node _T_3346 = bits(_T_3345, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3346 node _T_3347 = eq(UInt<1>(0h1), idx_26) when _T_3347 : node _T_3348 = shl(UInt<5>(0h1a), 3) node _T_3349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3348) node _T_3350 = bits(_T_3349, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3350 node _T_3351 = eq(UInt<2>(0h2), idx_26) when _T_3351 : node _T_3352 = shl(UInt<5>(0h1a), 3) node _T_3353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3352) node _T_3354 = bits(_T_3353, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3354 node _T_3355 = eq(UInt<2>(0h3), idx_26) when _T_3355 : node _T_3356 = shl(UInt<5>(0h1a), 3) node _T_3357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3356) node _T_3358 = bits(_T_3357, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3358 node _T_3359 = eq(UInt<3>(0h4), idx_26) when _T_3359 : node _T_3360 = shl(UInt<5>(0h1a), 3) node _T_3361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3360) node _T_3362 = bits(_T_3361, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3362 node _T_3363 = eq(UInt<3>(0h5), idx_26) when _T_3363 : node _T_3364 = shl(UInt<5>(0h1a), 3) node _T_3365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3364) node _T_3366 = bits(_T_3365, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3366 node _T_3367 = eq(UInt<3>(0h6), idx_26) when _T_3367 : node _T_3368 = shl(UInt<5>(0h1a), 3) node _T_3369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3368) node _T_3370 = bits(_T_3369, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3370 node _T_3371 = eq(UInt<3>(0h7), idx_26) when _T_3371 : node _T_3372 = shl(UInt<5>(0h1a), 3) node _T_3373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3372) node _T_3374 = bits(_T_3373, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3374 node _T_3375 = eq(UInt<4>(0h8), idx_26) when _T_3375 : node _T_3376 = shl(UInt<5>(0h1a), 3) node _T_3377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3376) node _T_3378 = bits(_T_3377, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3378 node _T_3379 = eq(UInt<4>(0h9), idx_26) when _T_3379 : node _T_3380 = shl(UInt<5>(0h1a), 3) node _T_3381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3380) node _T_3382 = bits(_T_3381, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3382 node _T_3383 = eq(UInt<4>(0ha), idx_26) when _T_3383 : node _T_3384 = shl(UInt<5>(0h1a), 3) node _T_3385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3384) node _T_3386 = bits(_T_3385, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3386 node _T_3387 = eq(UInt<4>(0hb), idx_26) when _T_3387 : node _T_3388 = shl(UInt<5>(0h1a), 3) node _T_3389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3388) node _T_3390 = bits(_T_3389, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3390 node _T_3391 = eq(UInt<4>(0hc), idx_26) when _T_3391 : node _T_3392 = shl(UInt<5>(0h1a), 3) node _T_3393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3392) node _T_3394 = bits(_T_3393, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3394 node _T_3395 = eq(UInt<4>(0hd), idx_26) when _T_3395 : node _T_3396 = shl(UInt<5>(0h1a), 3) node _T_3397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3396) node _T_3398 = bits(_T_3397, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3398 node _T_3399 = eq(UInt<4>(0he), idx_26) when _T_3399 : node _T_3400 = shl(UInt<5>(0h1a), 3) node _T_3401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3400) node _T_3402 = bits(_T_3401, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3402 node _T_3403 = eq(UInt<4>(0hf), idx_26) when _T_3403 : node _T_3404 = shl(UInt<5>(0h1a), 3) node _T_3405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3404) node _T_3406 = bits(_T_3405, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3406 node _T_3407 = eq(UInt<5>(0h10), idx_26) when _T_3407 : node _T_3408 = shl(UInt<5>(0h1a), 3) node _T_3409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3408) node _T_3410 = bits(_T_3409, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3410 node _T_3411 = eq(UInt<5>(0h11), idx_26) when _T_3411 : node _T_3412 = shl(UInt<5>(0h1a), 3) node _T_3413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3412) node _T_3414 = bits(_T_3413, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3414 node _T_3415 = eq(UInt<5>(0h12), idx_26) when _T_3415 : node _T_3416 = shl(UInt<5>(0h1a), 3) node _T_3417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3416) node _T_3418 = bits(_T_3417, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3418 node _T_3419 = eq(UInt<5>(0h13), idx_26) when _T_3419 : node _T_3420 = shl(UInt<5>(0h1a), 3) node _T_3421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3420) node _T_3422 = bits(_T_3421, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3422 node _T_3423 = eq(UInt<5>(0h14), idx_26) when _T_3423 : node _T_3424 = shl(UInt<5>(0h1a), 3) node _T_3425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3424) node _T_3426 = bits(_T_3425, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3426 node _T_3427 = eq(UInt<5>(0h15), idx_26) when _T_3427 : node _T_3428 = shl(UInt<5>(0h1a), 3) node _T_3429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3428) node _T_3430 = bits(_T_3429, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3430 node _T_3431 = eq(UInt<5>(0h16), idx_26) when _T_3431 : node _T_3432 = shl(UInt<5>(0h1a), 3) node _T_3433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3432) node _T_3434 = bits(_T_3433, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3434 node _T_3435 = eq(UInt<5>(0h17), idx_26) when _T_3435 : node _T_3436 = shl(UInt<5>(0h1a), 3) node _T_3437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3436) node _T_3438 = bits(_T_3437, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3438 node _T_3439 = eq(UInt<5>(0h18), idx_26) when _T_3439 : node _T_3440 = shl(UInt<5>(0h1a), 3) node _T_3441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3440) node _T_3442 = bits(_T_3441, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3442 node _T_3443 = eq(UInt<5>(0h19), idx_26) when _T_3443 : node _T_3444 = shl(UInt<5>(0h1a), 3) node _T_3445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3444) node _T_3446 = bits(_T_3445, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3446 node _T_3447 = eq(UInt<5>(0h1a), idx_26) when _T_3447 : node _T_3448 = shl(UInt<5>(0h1a), 3) node _T_3449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3448) node _T_3450 = bits(_T_3449, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3450 node _T_3451 = eq(UInt<5>(0h1b), idx_26) when _T_3451 : node _T_3452 = shl(UInt<5>(0h1a), 3) node _T_3453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3452) node _T_3454 = bits(_T_3453, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3454 node _T_3455 = eq(UInt<5>(0h1c), idx_26) when _T_3455 : node _T_3456 = shl(UInt<5>(0h1a), 3) node _T_3457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3456) node _T_3458 = bits(_T_3457, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3458 node _T_3459 = eq(UInt<5>(0h1d), idx_26) when _T_3459 : node _T_3460 = shl(UInt<5>(0h1a), 3) node _T_3461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3460) node _T_3462 = bits(_T_3461, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3462 node _T_3463 = eq(UInt<5>(0h1e), idx_26) when _T_3463 : node _T_3464 = shl(UInt<5>(0h1a), 3) node _T_3465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3464) node _T_3466 = bits(_T_3465, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3466 node _T_3467 = eq(UInt<5>(0h1f), idx_26) when _T_3467 : node _T_3468 = shl(UInt<5>(0h1a), 3) node _T_3469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3468) node _T_3470 = bits(_T_3469, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3470 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_3471 = eq(UInt<1>(0h0), idx_27) when _T_3471 : node _T_3472 = shl(UInt<5>(0h1b), 3) node _T_3473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3472) node _T_3474 = bits(_T_3473, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3474 node _T_3475 = eq(UInt<1>(0h1), idx_27) when _T_3475 : node _T_3476 = shl(UInt<5>(0h1b), 3) node _T_3477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3476) node _T_3478 = bits(_T_3477, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3478 node _T_3479 = eq(UInt<2>(0h2), idx_27) when _T_3479 : node _T_3480 = shl(UInt<5>(0h1b), 3) node _T_3481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3480) node _T_3482 = bits(_T_3481, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3482 node _T_3483 = eq(UInt<2>(0h3), idx_27) when _T_3483 : node _T_3484 = shl(UInt<5>(0h1b), 3) node _T_3485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3484) node _T_3486 = bits(_T_3485, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3486 node _T_3487 = eq(UInt<3>(0h4), idx_27) when _T_3487 : node _T_3488 = shl(UInt<5>(0h1b), 3) node _T_3489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3488) node _T_3490 = bits(_T_3489, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3490 node _T_3491 = eq(UInt<3>(0h5), idx_27) when _T_3491 : node _T_3492 = shl(UInt<5>(0h1b), 3) node _T_3493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3492) node _T_3494 = bits(_T_3493, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3494 node _T_3495 = eq(UInt<3>(0h6), idx_27) when _T_3495 : node _T_3496 = shl(UInt<5>(0h1b), 3) node _T_3497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3496) node _T_3498 = bits(_T_3497, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3498 node _T_3499 = eq(UInt<3>(0h7), idx_27) when _T_3499 : node _T_3500 = shl(UInt<5>(0h1b), 3) node _T_3501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3500) node _T_3502 = bits(_T_3501, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3502 node _T_3503 = eq(UInt<4>(0h8), idx_27) when _T_3503 : node _T_3504 = shl(UInt<5>(0h1b), 3) node _T_3505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3504) node _T_3506 = bits(_T_3505, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3506 node _T_3507 = eq(UInt<4>(0h9), idx_27) when _T_3507 : node _T_3508 = shl(UInt<5>(0h1b), 3) node _T_3509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3508) node _T_3510 = bits(_T_3509, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3510 node _T_3511 = eq(UInt<4>(0ha), idx_27) when _T_3511 : node _T_3512 = shl(UInt<5>(0h1b), 3) node _T_3513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3512) node _T_3514 = bits(_T_3513, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3514 node _T_3515 = eq(UInt<4>(0hb), idx_27) when _T_3515 : node _T_3516 = shl(UInt<5>(0h1b), 3) node _T_3517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3516) node _T_3518 = bits(_T_3517, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3518 node _T_3519 = eq(UInt<4>(0hc), idx_27) when _T_3519 : node _T_3520 = shl(UInt<5>(0h1b), 3) node _T_3521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3520) node _T_3522 = bits(_T_3521, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3522 node _T_3523 = eq(UInt<4>(0hd), idx_27) when _T_3523 : node _T_3524 = shl(UInt<5>(0h1b), 3) node _T_3525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3524) node _T_3526 = bits(_T_3525, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3526 node _T_3527 = eq(UInt<4>(0he), idx_27) when _T_3527 : node _T_3528 = shl(UInt<5>(0h1b), 3) node _T_3529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3528) node _T_3530 = bits(_T_3529, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3530 node _T_3531 = eq(UInt<4>(0hf), idx_27) when _T_3531 : node _T_3532 = shl(UInt<5>(0h1b), 3) node _T_3533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3532) node _T_3534 = bits(_T_3533, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3534 node _T_3535 = eq(UInt<5>(0h10), idx_27) when _T_3535 : node _T_3536 = shl(UInt<5>(0h1b), 3) node _T_3537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3536) node _T_3538 = bits(_T_3537, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3538 node _T_3539 = eq(UInt<5>(0h11), idx_27) when _T_3539 : node _T_3540 = shl(UInt<5>(0h1b), 3) node _T_3541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3540) node _T_3542 = bits(_T_3541, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3542 node _T_3543 = eq(UInt<5>(0h12), idx_27) when _T_3543 : node _T_3544 = shl(UInt<5>(0h1b), 3) node _T_3545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3544) node _T_3546 = bits(_T_3545, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3546 node _T_3547 = eq(UInt<5>(0h13), idx_27) when _T_3547 : node _T_3548 = shl(UInt<5>(0h1b), 3) node _T_3549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3548) node _T_3550 = bits(_T_3549, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3550 node _T_3551 = eq(UInt<5>(0h14), idx_27) when _T_3551 : node _T_3552 = shl(UInt<5>(0h1b), 3) node _T_3553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3552) node _T_3554 = bits(_T_3553, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3554 node _T_3555 = eq(UInt<5>(0h15), idx_27) when _T_3555 : node _T_3556 = shl(UInt<5>(0h1b), 3) node _T_3557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3556) node _T_3558 = bits(_T_3557, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3558 node _T_3559 = eq(UInt<5>(0h16), idx_27) when _T_3559 : node _T_3560 = shl(UInt<5>(0h1b), 3) node _T_3561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3560) node _T_3562 = bits(_T_3561, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3562 node _T_3563 = eq(UInt<5>(0h17), idx_27) when _T_3563 : node _T_3564 = shl(UInt<5>(0h1b), 3) node _T_3565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3564) node _T_3566 = bits(_T_3565, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3566 node _T_3567 = eq(UInt<5>(0h18), idx_27) when _T_3567 : node _T_3568 = shl(UInt<5>(0h1b), 3) node _T_3569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3568) node _T_3570 = bits(_T_3569, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3570 node _T_3571 = eq(UInt<5>(0h19), idx_27) when _T_3571 : node _T_3572 = shl(UInt<5>(0h1b), 3) node _T_3573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3572) node _T_3574 = bits(_T_3573, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3574 node _T_3575 = eq(UInt<5>(0h1a), idx_27) when _T_3575 : node _T_3576 = shl(UInt<5>(0h1b), 3) node _T_3577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3576) node _T_3578 = bits(_T_3577, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3578 node _T_3579 = eq(UInt<5>(0h1b), idx_27) when _T_3579 : node _T_3580 = shl(UInt<5>(0h1b), 3) node _T_3581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3580) node _T_3582 = bits(_T_3581, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3582 node _T_3583 = eq(UInt<5>(0h1c), idx_27) when _T_3583 : node _T_3584 = shl(UInt<5>(0h1b), 3) node _T_3585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3584) node _T_3586 = bits(_T_3585, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3586 node _T_3587 = eq(UInt<5>(0h1d), idx_27) when _T_3587 : node _T_3588 = shl(UInt<5>(0h1b), 3) node _T_3589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3588) node _T_3590 = bits(_T_3589, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3590 node _T_3591 = eq(UInt<5>(0h1e), idx_27) when _T_3591 : node _T_3592 = shl(UInt<5>(0h1b), 3) node _T_3593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3592) node _T_3594 = bits(_T_3593, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3594 node _T_3595 = eq(UInt<5>(0h1f), idx_27) when _T_3595 : node _T_3596 = shl(UInt<5>(0h1b), 3) node _T_3597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3596) node _T_3598 = bits(_T_3597, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3598 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_3599 = eq(UInt<1>(0h0), idx_28) when _T_3599 : node _T_3600 = shl(UInt<5>(0h1c), 3) node _T_3601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3600) node _T_3602 = bits(_T_3601, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3602 node _T_3603 = eq(UInt<1>(0h1), idx_28) when _T_3603 : node _T_3604 = shl(UInt<5>(0h1c), 3) node _T_3605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3604) node _T_3606 = bits(_T_3605, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3606 node _T_3607 = eq(UInt<2>(0h2), idx_28) when _T_3607 : node _T_3608 = shl(UInt<5>(0h1c), 3) node _T_3609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3608) node _T_3610 = bits(_T_3609, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3610 node _T_3611 = eq(UInt<2>(0h3), idx_28) when _T_3611 : node _T_3612 = shl(UInt<5>(0h1c), 3) node _T_3613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3612) node _T_3614 = bits(_T_3613, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3614 node _T_3615 = eq(UInt<3>(0h4), idx_28) when _T_3615 : node _T_3616 = shl(UInt<5>(0h1c), 3) node _T_3617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3616) node _T_3618 = bits(_T_3617, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3618 node _T_3619 = eq(UInt<3>(0h5), idx_28) when _T_3619 : node _T_3620 = shl(UInt<5>(0h1c), 3) node _T_3621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3620) node _T_3622 = bits(_T_3621, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3622 node _T_3623 = eq(UInt<3>(0h6), idx_28) when _T_3623 : node _T_3624 = shl(UInt<5>(0h1c), 3) node _T_3625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3624) node _T_3626 = bits(_T_3625, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3626 node _T_3627 = eq(UInt<3>(0h7), idx_28) when _T_3627 : node _T_3628 = shl(UInt<5>(0h1c), 3) node _T_3629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3628) node _T_3630 = bits(_T_3629, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3630 node _T_3631 = eq(UInt<4>(0h8), idx_28) when _T_3631 : node _T_3632 = shl(UInt<5>(0h1c), 3) node _T_3633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3632) node _T_3634 = bits(_T_3633, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3634 node _T_3635 = eq(UInt<4>(0h9), idx_28) when _T_3635 : node _T_3636 = shl(UInt<5>(0h1c), 3) node _T_3637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3636) node _T_3638 = bits(_T_3637, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3638 node _T_3639 = eq(UInt<4>(0ha), idx_28) when _T_3639 : node _T_3640 = shl(UInt<5>(0h1c), 3) node _T_3641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3640) node _T_3642 = bits(_T_3641, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3642 node _T_3643 = eq(UInt<4>(0hb), idx_28) when _T_3643 : node _T_3644 = shl(UInt<5>(0h1c), 3) node _T_3645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3644) node _T_3646 = bits(_T_3645, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3646 node _T_3647 = eq(UInt<4>(0hc), idx_28) when _T_3647 : node _T_3648 = shl(UInt<5>(0h1c), 3) node _T_3649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3648) node _T_3650 = bits(_T_3649, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3650 node _T_3651 = eq(UInt<4>(0hd), idx_28) when _T_3651 : node _T_3652 = shl(UInt<5>(0h1c), 3) node _T_3653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3652) node _T_3654 = bits(_T_3653, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3654 node _T_3655 = eq(UInt<4>(0he), idx_28) when _T_3655 : node _T_3656 = shl(UInt<5>(0h1c), 3) node _T_3657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3656) node _T_3658 = bits(_T_3657, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3658 node _T_3659 = eq(UInt<4>(0hf), idx_28) when _T_3659 : node _T_3660 = shl(UInt<5>(0h1c), 3) node _T_3661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3660) node _T_3662 = bits(_T_3661, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3662 node _T_3663 = eq(UInt<5>(0h10), idx_28) when _T_3663 : node _T_3664 = shl(UInt<5>(0h1c), 3) node _T_3665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3664) node _T_3666 = bits(_T_3665, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3666 node _T_3667 = eq(UInt<5>(0h11), idx_28) when _T_3667 : node _T_3668 = shl(UInt<5>(0h1c), 3) node _T_3669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3668) node _T_3670 = bits(_T_3669, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3670 node _T_3671 = eq(UInt<5>(0h12), idx_28) when _T_3671 : node _T_3672 = shl(UInt<5>(0h1c), 3) node _T_3673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3672) node _T_3674 = bits(_T_3673, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3674 node _T_3675 = eq(UInt<5>(0h13), idx_28) when _T_3675 : node _T_3676 = shl(UInt<5>(0h1c), 3) node _T_3677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3676) node _T_3678 = bits(_T_3677, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3678 node _T_3679 = eq(UInt<5>(0h14), idx_28) when _T_3679 : node _T_3680 = shl(UInt<5>(0h1c), 3) node _T_3681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3680) node _T_3682 = bits(_T_3681, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3682 node _T_3683 = eq(UInt<5>(0h15), idx_28) when _T_3683 : node _T_3684 = shl(UInt<5>(0h1c), 3) node _T_3685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3684) node _T_3686 = bits(_T_3685, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3686 node _T_3687 = eq(UInt<5>(0h16), idx_28) when _T_3687 : node _T_3688 = shl(UInt<5>(0h1c), 3) node _T_3689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3688) node _T_3690 = bits(_T_3689, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3690 node _T_3691 = eq(UInt<5>(0h17), idx_28) when _T_3691 : node _T_3692 = shl(UInt<5>(0h1c), 3) node _T_3693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3692) node _T_3694 = bits(_T_3693, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3694 node _T_3695 = eq(UInt<5>(0h18), idx_28) when _T_3695 : node _T_3696 = shl(UInt<5>(0h1c), 3) node _T_3697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3696) node _T_3698 = bits(_T_3697, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3698 node _T_3699 = eq(UInt<5>(0h19), idx_28) when _T_3699 : node _T_3700 = shl(UInt<5>(0h1c), 3) node _T_3701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3700) node _T_3702 = bits(_T_3701, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3702 node _T_3703 = eq(UInt<5>(0h1a), idx_28) when _T_3703 : node _T_3704 = shl(UInt<5>(0h1c), 3) node _T_3705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3704) node _T_3706 = bits(_T_3705, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3706 node _T_3707 = eq(UInt<5>(0h1b), idx_28) when _T_3707 : node _T_3708 = shl(UInt<5>(0h1c), 3) node _T_3709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3708) node _T_3710 = bits(_T_3709, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3710 node _T_3711 = eq(UInt<5>(0h1c), idx_28) when _T_3711 : node _T_3712 = shl(UInt<5>(0h1c), 3) node _T_3713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3712) node _T_3714 = bits(_T_3713, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3714 node _T_3715 = eq(UInt<5>(0h1d), idx_28) when _T_3715 : node _T_3716 = shl(UInt<5>(0h1c), 3) node _T_3717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3716) node _T_3718 = bits(_T_3717, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3718 node _T_3719 = eq(UInt<5>(0h1e), idx_28) when _T_3719 : node _T_3720 = shl(UInt<5>(0h1c), 3) node _T_3721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3720) node _T_3722 = bits(_T_3721, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3722 node _T_3723 = eq(UInt<5>(0h1f), idx_28) when _T_3723 : node _T_3724 = shl(UInt<5>(0h1c), 3) node _T_3725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3724) node _T_3726 = bits(_T_3725, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3726 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_3727 = eq(UInt<1>(0h0), idx_29) when _T_3727 : node _T_3728 = shl(UInt<5>(0h1d), 3) node _T_3729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3728) node _T_3730 = bits(_T_3729, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3730 node _T_3731 = eq(UInt<1>(0h1), idx_29) when _T_3731 : node _T_3732 = shl(UInt<5>(0h1d), 3) node _T_3733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3732) node _T_3734 = bits(_T_3733, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3734 node _T_3735 = eq(UInt<2>(0h2), idx_29) when _T_3735 : node _T_3736 = shl(UInt<5>(0h1d), 3) node _T_3737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3736) node _T_3738 = bits(_T_3737, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3738 node _T_3739 = eq(UInt<2>(0h3), idx_29) when _T_3739 : node _T_3740 = shl(UInt<5>(0h1d), 3) node _T_3741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3740) node _T_3742 = bits(_T_3741, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3742 node _T_3743 = eq(UInt<3>(0h4), idx_29) when _T_3743 : node _T_3744 = shl(UInt<5>(0h1d), 3) node _T_3745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3744) node _T_3746 = bits(_T_3745, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3746 node _T_3747 = eq(UInt<3>(0h5), idx_29) when _T_3747 : node _T_3748 = shl(UInt<5>(0h1d), 3) node _T_3749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3748) node _T_3750 = bits(_T_3749, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3750 node _T_3751 = eq(UInt<3>(0h6), idx_29) when _T_3751 : node _T_3752 = shl(UInt<5>(0h1d), 3) node _T_3753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3752) node _T_3754 = bits(_T_3753, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3754 node _T_3755 = eq(UInt<3>(0h7), idx_29) when _T_3755 : node _T_3756 = shl(UInt<5>(0h1d), 3) node _T_3757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3756) node _T_3758 = bits(_T_3757, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3758 node _T_3759 = eq(UInt<4>(0h8), idx_29) when _T_3759 : node _T_3760 = shl(UInt<5>(0h1d), 3) node _T_3761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3760) node _T_3762 = bits(_T_3761, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3762 node _T_3763 = eq(UInt<4>(0h9), idx_29) when _T_3763 : node _T_3764 = shl(UInt<5>(0h1d), 3) node _T_3765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3764) node _T_3766 = bits(_T_3765, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3766 node _T_3767 = eq(UInt<4>(0ha), idx_29) when _T_3767 : node _T_3768 = shl(UInt<5>(0h1d), 3) node _T_3769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3768) node _T_3770 = bits(_T_3769, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3770 node _T_3771 = eq(UInt<4>(0hb), idx_29) when _T_3771 : node _T_3772 = shl(UInt<5>(0h1d), 3) node _T_3773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3772) node _T_3774 = bits(_T_3773, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3774 node _T_3775 = eq(UInt<4>(0hc), idx_29) when _T_3775 : node _T_3776 = shl(UInt<5>(0h1d), 3) node _T_3777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3776) node _T_3778 = bits(_T_3777, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3778 node _T_3779 = eq(UInt<4>(0hd), idx_29) when _T_3779 : node _T_3780 = shl(UInt<5>(0h1d), 3) node _T_3781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3780) node _T_3782 = bits(_T_3781, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3782 node _T_3783 = eq(UInt<4>(0he), idx_29) when _T_3783 : node _T_3784 = shl(UInt<5>(0h1d), 3) node _T_3785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3784) node _T_3786 = bits(_T_3785, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3786 node _T_3787 = eq(UInt<4>(0hf), idx_29) when _T_3787 : node _T_3788 = shl(UInt<5>(0h1d), 3) node _T_3789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3788) node _T_3790 = bits(_T_3789, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3790 node _T_3791 = eq(UInt<5>(0h10), idx_29) when _T_3791 : node _T_3792 = shl(UInt<5>(0h1d), 3) node _T_3793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3792) node _T_3794 = bits(_T_3793, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3794 node _T_3795 = eq(UInt<5>(0h11), idx_29) when _T_3795 : node _T_3796 = shl(UInt<5>(0h1d), 3) node _T_3797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3796) node _T_3798 = bits(_T_3797, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3798 node _T_3799 = eq(UInt<5>(0h12), idx_29) when _T_3799 : node _T_3800 = shl(UInt<5>(0h1d), 3) node _T_3801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3800) node _T_3802 = bits(_T_3801, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3802 node _T_3803 = eq(UInt<5>(0h13), idx_29) when _T_3803 : node _T_3804 = shl(UInt<5>(0h1d), 3) node _T_3805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3804) node _T_3806 = bits(_T_3805, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3806 node _T_3807 = eq(UInt<5>(0h14), idx_29) when _T_3807 : node _T_3808 = shl(UInt<5>(0h1d), 3) node _T_3809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3808) node _T_3810 = bits(_T_3809, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3810 node _T_3811 = eq(UInt<5>(0h15), idx_29) when _T_3811 : node _T_3812 = shl(UInt<5>(0h1d), 3) node _T_3813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3812) node _T_3814 = bits(_T_3813, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3814 node _T_3815 = eq(UInt<5>(0h16), idx_29) when _T_3815 : node _T_3816 = shl(UInt<5>(0h1d), 3) node _T_3817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3816) node _T_3818 = bits(_T_3817, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3818 node _T_3819 = eq(UInt<5>(0h17), idx_29) when _T_3819 : node _T_3820 = shl(UInt<5>(0h1d), 3) node _T_3821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3820) node _T_3822 = bits(_T_3821, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3822 node _T_3823 = eq(UInt<5>(0h18), idx_29) when _T_3823 : node _T_3824 = shl(UInt<5>(0h1d), 3) node _T_3825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3824) node _T_3826 = bits(_T_3825, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3826 node _T_3827 = eq(UInt<5>(0h19), idx_29) when _T_3827 : node _T_3828 = shl(UInt<5>(0h1d), 3) node _T_3829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3828) node _T_3830 = bits(_T_3829, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3830 node _T_3831 = eq(UInt<5>(0h1a), idx_29) when _T_3831 : node _T_3832 = shl(UInt<5>(0h1d), 3) node _T_3833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3832) node _T_3834 = bits(_T_3833, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3834 node _T_3835 = eq(UInt<5>(0h1b), idx_29) when _T_3835 : node _T_3836 = shl(UInt<5>(0h1d), 3) node _T_3837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3836) node _T_3838 = bits(_T_3837, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3838 node _T_3839 = eq(UInt<5>(0h1c), idx_29) when _T_3839 : node _T_3840 = shl(UInt<5>(0h1d), 3) node _T_3841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3840) node _T_3842 = bits(_T_3841, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3842 node _T_3843 = eq(UInt<5>(0h1d), idx_29) when _T_3843 : node _T_3844 = shl(UInt<5>(0h1d), 3) node _T_3845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3844) node _T_3846 = bits(_T_3845, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3846 node _T_3847 = eq(UInt<5>(0h1e), idx_29) when _T_3847 : node _T_3848 = shl(UInt<5>(0h1d), 3) node _T_3849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3848) node _T_3850 = bits(_T_3849, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3850 node _T_3851 = eq(UInt<5>(0h1f), idx_29) when _T_3851 : node _T_3852 = shl(UInt<5>(0h1d), 3) node _T_3853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3852) node _T_3854 = bits(_T_3853, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3854 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_3855 = eq(UInt<1>(0h0), idx_30) when _T_3855 : node _T_3856 = shl(UInt<5>(0h1e), 3) node _T_3857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3856) node _T_3858 = bits(_T_3857, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3858 node _T_3859 = eq(UInt<1>(0h1), idx_30) when _T_3859 : node _T_3860 = shl(UInt<5>(0h1e), 3) node _T_3861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3860) node _T_3862 = bits(_T_3861, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3862 node _T_3863 = eq(UInt<2>(0h2), idx_30) when _T_3863 : node _T_3864 = shl(UInt<5>(0h1e), 3) node _T_3865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3864) node _T_3866 = bits(_T_3865, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3866 node _T_3867 = eq(UInt<2>(0h3), idx_30) when _T_3867 : node _T_3868 = shl(UInt<5>(0h1e), 3) node _T_3869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3868) node _T_3870 = bits(_T_3869, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3870 node _T_3871 = eq(UInt<3>(0h4), idx_30) when _T_3871 : node _T_3872 = shl(UInt<5>(0h1e), 3) node _T_3873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3872) node _T_3874 = bits(_T_3873, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_3874 node _T_3875 = eq(UInt<3>(0h5), idx_30) when _T_3875 : node _T_3876 = shl(UInt<5>(0h1e), 3) node _T_3877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3876) node _T_3878 = bits(_T_3877, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_3878 node _T_3879 = eq(UInt<3>(0h6), idx_30) when _T_3879 : node _T_3880 = shl(UInt<5>(0h1e), 3) node _T_3881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3880) node _T_3882 = bits(_T_3881, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_3882 node _T_3883 = eq(UInt<3>(0h7), idx_30) when _T_3883 : node _T_3884 = shl(UInt<5>(0h1e), 3) node _T_3885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3884) node _T_3886 = bits(_T_3885, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_3886 node _T_3887 = eq(UInt<4>(0h8), idx_30) when _T_3887 : node _T_3888 = shl(UInt<5>(0h1e), 3) node _T_3889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3888) node _T_3890 = bits(_T_3889, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_3890 node _T_3891 = eq(UInt<4>(0h9), idx_30) when _T_3891 : node _T_3892 = shl(UInt<5>(0h1e), 3) node _T_3893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3892) node _T_3894 = bits(_T_3893, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_3894 node _T_3895 = eq(UInt<4>(0ha), idx_30) when _T_3895 : node _T_3896 = shl(UInt<5>(0h1e), 3) node _T_3897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3896) node _T_3898 = bits(_T_3897, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_3898 node _T_3899 = eq(UInt<4>(0hb), idx_30) when _T_3899 : node _T_3900 = shl(UInt<5>(0h1e), 3) node _T_3901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3900) node _T_3902 = bits(_T_3901, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_3902 node _T_3903 = eq(UInt<4>(0hc), idx_30) when _T_3903 : node _T_3904 = shl(UInt<5>(0h1e), 3) node _T_3905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3904) node _T_3906 = bits(_T_3905, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_3906 node _T_3907 = eq(UInt<4>(0hd), idx_30) when _T_3907 : node _T_3908 = shl(UInt<5>(0h1e), 3) node _T_3909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3908) node _T_3910 = bits(_T_3909, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_3910 node _T_3911 = eq(UInt<4>(0he), idx_30) when _T_3911 : node _T_3912 = shl(UInt<5>(0h1e), 3) node _T_3913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3912) node _T_3914 = bits(_T_3913, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_3914 node _T_3915 = eq(UInt<4>(0hf), idx_30) when _T_3915 : node _T_3916 = shl(UInt<5>(0h1e), 3) node _T_3917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3916) node _T_3918 = bits(_T_3917, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_3918 node _T_3919 = eq(UInt<5>(0h10), idx_30) when _T_3919 : node _T_3920 = shl(UInt<5>(0h1e), 3) node _T_3921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3920) node _T_3922 = bits(_T_3921, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_3922 node _T_3923 = eq(UInt<5>(0h11), idx_30) when _T_3923 : node _T_3924 = shl(UInt<5>(0h1e), 3) node _T_3925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3924) node _T_3926 = bits(_T_3925, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_3926 node _T_3927 = eq(UInt<5>(0h12), idx_30) when _T_3927 : node _T_3928 = shl(UInt<5>(0h1e), 3) node _T_3929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3928) node _T_3930 = bits(_T_3929, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_3930 node _T_3931 = eq(UInt<5>(0h13), idx_30) when _T_3931 : node _T_3932 = shl(UInt<5>(0h1e), 3) node _T_3933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3932) node _T_3934 = bits(_T_3933, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_3934 node _T_3935 = eq(UInt<5>(0h14), idx_30) when _T_3935 : node _T_3936 = shl(UInt<5>(0h1e), 3) node _T_3937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3936) node _T_3938 = bits(_T_3937, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_3938 node _T_3939 = eq(UInt<5>(0h15), idx_30) when _T_3939 : node _T_3940 = shl(UInt<5>(0h1e), 3) node _T_3941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3940) node _T_3942 = bits(_T_3941, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_3942 node _T_3943 = eq(UInt<5>(0h16), idx_30) when _T_3943 : node _T_3944 = shl(UInt<5>(0h1e), 3) node _T_3945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3944) node _T_3946 = bits(_T_3945, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_3946 node _T_3947 = eq(UInt<5>(0h17), idx_30) when _T_3947 : node _T_3948 = shl(UInt<5>(0h1e), 3) node _T_3949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3948) node _T_3950 = bits(_T_3949, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_3950 node _T_3951 = eq(UInt<5>(0h18), idx_30) when _T_3951 : node _T_3952 = shl(UInt<5>(0h1e), 3) node _T_3953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3952) node _T_3954 = bits(_T_3953, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_3954 node _T_3955 = eq(UInt<5>(0h19), idx_30) when _T_3955 : node _T_3956 = shl(UInt<5>(0h1e), 3) node _T_3957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3956) node _T_3958 = bits(_T_3957, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_3958 node _T_3959 = eq(UInt<5>(0h1a), idx_30) when _T_3959 : node _T_3960 = shl(UInt<5>(0h1e), 3) node _T_3961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3960) node _T_3962 = bits(_T_3961, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_3962 node _T_3963 = eq(UInt<5>(0h1b), idx_30) when _T_3963 : node _T_3964 = shl(UInt<5>(0h1e), 3) node _T_3965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3964) node _T_3966 = bits(_T_3965, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_3966 node _T_3967 = eq(UInt<5>(0h1c), idx_30) when _T_3967 : node _T_3968 = shl(UInt<5>(0h1e), 3) node _T_3969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3968) node _T_3970 = bits(_T_3969, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_3970 node _T_3971 = eq(UInt<5>(0h1d), idx_30) when _T_3971 : node _T_3972 = shl(UInt<5>(0h1e), 3) node _T_3973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3972) node _T_3974 = bits(_T_3973, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_3974 node _T_3975 = eq(UInt<5>(0h1e), idx_30) when _T_3975 : node _T_3976 = shl(UInt<5>(0h1e), 3) node _T_3977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3976) node _T_3978 = bits(_T_3977, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_3978 node _T_3979 = eq(UInt<5>(0h1f), idx_30) when _T_3979 : node _T_3980 = shl(UInt<5>(0h1e), 3) node _T_3981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3980) node _T_3982 = bits(_T_3981, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_3982 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_3983 = eq(UInt<1>(0h0), idx_31) when _T_3983 : node _T_3984 = shl(UInt<5>(0h1f), 3) node _T_3985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3984) node _T_3986 = bits(_T_3985, 7, 0) connect Queue16_UInt8.io.enq.bits, _T_3986 node _T_3987 = eq(UInt<1>(0h1), idx_31) when _T_3987 : node _T_3988 = shl(UInt<5>(0h1f), 3) node _T_3989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3988) node _T_3990 = bits(_T_3989, 7, 0) connect Queue16_UInt8_1.io.enq.bits, _T_3990 node _T_3991 = eq(UInt<2>(0h2), idx_31) when _T_3991 : node _T_3992 = shl(UInt<5>(0h1f), 3) node _T_3993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3992) node _T_3994 = bits(_T_3993, 7, 0) connect Queue16_UInt8_2.io.enq.bits, _T_3994 node _T_3995 = eq(UInt<2>(0h3), idx_31) when _T_3995 : node _T_3996 = shl(UInt<5>(0h1f), 3) node _T_3997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3996) node _T_3998 = bits(_T_3997, 7, 0) connect Queue16_UInt8_3.io.enq.bits, _T_3998 node _T_3999 = eq(UInt<3>(0h4), idx_31) when _T_3999 : node _T_4000 = shl(UInt<5>(0h1f), 3) node _T_4001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4000) node _T_4002 = bits(_T_4001, 7, 0) connect Queue16_UInt8_4.io.enq.bits, _T_4002 node _T_4003 = eq(UInt<3>(0h5), idx_31) when _T_4003 : node _T_4004 = shl(UInt<5>(0h1f), 3) node _T_4005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4004) node _T_4006 = bits(_T_4005, 7, 0) connect Queue16_UInt8_5.io.enq.bits, _T_4006 node _T_4007 = eq(UInt<3>(0h6), idx_31) when _T_4007 : node _T_4008 = shl(UInt<5>(0h1f), 3) node _T_4009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4008) node _T_4010 = bits(_T_4009, 7, 0) connect Queue16_UInt8_6.io.enq.bits, _T_4010 node _T_4011 = eq(UInt<3>(0h7), idx_31) when _T_4011 : node _T_4012 = shl(UInt<5>(0h1f), 3) node _T_4013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4012) node _T_4014 = bits(_T_4013, 7, 0) connect Queue16_UInt8_7.io.enq.bits, _T_4014 node _T_4015 = eq(UInt<4>(0h8), idx_31) when _T_4015 : node _T_4016 = shl(UInt<5>(0h1f), 3) node _T_4017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4016) node _T_4018 = bits(_T_4017, 7, 0) connect Queue16_UInt8_8.io.enq.bits, _T_4018 node _T_4019 = eq(UInt<4>(0h9), idx_31) when _T_4019 : node _T_4020 = shl(UInt<5>(0h1f), 3) node _T_4021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4020) node _T_4022 = bits(_T_4021, 7, 0) connect Queue16_UInt8_9.io.enq.bits, _T_4022 node _T_4023 = eq(UInt<4>(0ha), idx_31) when _T_4023 : node _T_4024 = shl(UInt<5>(0h1f), 3) node _T_4025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4024) node _T_4026 = bits(_T_4025, 7, 0) connect Queue16_UInt8_10.io.enq.bits, _T_4026 node _T_4027 = eq(UInt<4>(0hb), idx_31) when _T_4027 : node _T_4028 = shl(UInt<5>(0h1f), 3) node _T_4029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4028) node _T_4030 = bits(_T_4029, 7, 0) connect Queue16_UInt8_11.io.enq.bits, _T_4030 node _T_4031 = eq(UInt<4>(0hc), idx_31) when _T_4031 : node _T_4032 = shl(UInt<5>(0h1f), 3) node _T_4033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4032) node _T_4034 = bits(_T_4033, 7, 0) connect Queue16_UInt8_12.io.enq.bits, _T_4034 node _T_4035 = eq(UInt<4>(0hd), idx_31) when _T_4035 : node _T_4036 = shl(UInt<5>(0h1f), 3) node _T_4037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4036) node _T_4038 = bits(_T_4037, 7, 0) connect Queue16_UInt8_13.io.enq.bits, _T_4038 node _T_4039 = eq(UInt<4>(0he), idx_31) when _T_4039 : node _T_4040 = shl(UInt<5>(0h1f), 3) node _T_4041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4040) node _T_4042 = bits(_T_4041, 7, 0) connect Queue16_UInt8_14.io.enq.bits, _T_4042 node _T_4043 = eq(UInt<4>(0hf), idx_31) when _T_4043 : node _T_4044 = shl(UInt<5>(0h1f), 3) node _T_4045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4044) node _T_4046 = bits(_T_4045, 7, 0) connect Queue16_UInt8_15.io.enq.bits, _T_4046 node _T_4047 = eq(UInt<5>(0h10), idx_31) when _T_4047 : node _T_4048 = shl(UInt<5>(0h1f), 3) node _T_4049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4048) node _T_4050 = bits(_T_4049, 7, 0) connect Queue16_UInt8_16.io.enq.bits, _T_4050 node _T_4051 = eq(UInt<5>(0h11), idx_31) when _T_4051 : node _T_4052 = shl(UInt<5>(0h1f), 3) node _T_4053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4052) node _T_4054 = bits(_T_4053, 7, 0) connect Queue16_UInt8_17.io.enq.bits, _T_4054 node _T_4055 = eq(UInt<5>(0h12), idx_31) when _T_4055 : node _T_4056 = shl(UInt<5>(0h1f), 3) node _T_4057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4056) node _T_4058 = bits(_T_4057, 7, 0) connect Queue16_UInt8_18.io.enq.bits, _T_4058 node _T_4059 = eq(UInt<5>(0h13), idx_31) when _T_4059 : node _T_4060 = shl(UInt<5>(0h1f), 3) node _T_4061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4060) node _T_4062 = bits(_T_4061, 7, 0) connect Queue16_UInt8_19.io.enq.bits, _T_4062 node _T_4063 = eq(UInt<5>(0h14), idx_31) when _T_4063 : node _T_4064 = shl(UInt<5>(0h1f), 3) node _T_4065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4064) node _T_4066 = bits(_T_4065, 7, 0) connect Queue16_UInt8_20.io.enq.bits, _T_4066 node _T_4067 = eq(UInt<5>(0h15), idx_31) when _T_4067 : node _T_4068 = shl(UInt<5>(0h1f), 3) node _T_4069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4068) node _T_4070 = bits(_T_4069, 7, 0) connect Queue16_UInt8_21.io.enq.bits, _T_4070 node _T_4071 = eq(UInt<5>(0h16), idx_31) when _T_4071 : node _T_4072 = shl(UInt<5>(0h1f), 3) node _T_4073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4072) node _T_4074 = bits(_T_4073, 7, 0) connect Queue16_UInt8_22.io.enq.bits, _T_4074 node _T_4075 = eq(UInt<5>(0h17), idx_31) when _T_4075 : node _T_4076 = shl(UInt<5>(0h1f), 3) node _T_4077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4076) node _T_4078 = bits(_T_4077, 7, 0) connect Queue16_UInt8_23.io.enq.bits, _T_4078 node _T_4079 = eq(UInt<5>(0h18), idx_31) when _T_4079 : node _T_4080 = shl(UInt<5>(0h1f), 3) node _T_4081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4080) node _T_4082 = bits(_T_4081, 7, 0) connect Queue16_UInt8_24.io.enq.bits, _T_4082 node _T_4083 = eq(UInt<5>(0h19), idx_31) when _T_4083 : node _T_4084 = shl(UInt<5>(0h1f), 3) node _T_4085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4084) node _T_4086 = bits(_T_4085, 7, 0) connect Queue16_UInt8_25.io.enq.bits, _T_4086 node _T_4087 = eq(UInt<5>(0h1a), idx_31) when _T_4087 : node _T_4088 = shl(UInt<5>(0h1f), 3) node _T_4089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4088) node _T_4090 = bits(_T_4089, 7, 0) connect Queue16_UInt8_26.io.enq.bits, _T_4090 node _T_4091 = eq(UInt<5>(0h1b), idx_31) when _T_4091 : node _T_4092 = shl(UInt<5>(0h1f), 3) node _T_4093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4092) node _T_4094 = bits(_T_4093, 7, 0) connect Queue16_UInt8_27.io.enq.bits, _T_4094 node _T_4095 = eq(UInt<5>(0h1c), idx_31) when _T_4095 : node _T_4096 = shl(UInt<5>(0h1f), 3) node _T_4097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4096) node _T_4098 = bits(_T_4097, 7, 0) connect Queue16_UInt8_28.io.enq.bits, _T_4098 node _T_4099 = eq(UInt<5>(0h1d), idx_31) when _T_4099 : node _T_4100 = shl(UInt<5>(0h1f), 3) node _T_4101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4100) node _T_4102 = bits(_T_4101, 7, 0) connect Queue16_UInt8_29.io.enq.bits, _T_4102 node _T_4103 = eq(UInt<5>(0h1e), idx_31) when _T_4103 : node _T_4104 = shl(UInt<5>(0h1f), 3) node _T_4105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4104) node _T_4106 = bits(_T_4105, 7, 0) connect Queue16_UInt8_30.io.enq.bits, _T_4106 node _T_4107 = eq(UInt<5>(0h1f), idx_31) when _T_4107 : node _T_4108 = shl(UInt<5>(0h1f), 3) node _T_4109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4108) node _T_4110 = bits(_T_4109, 7, 0) connect Queue16_UInt8_31.io.enq.bits, _T_4110 node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) node _all_queues_ready_T = and(Queue16_UInt8.io.enq.ready, Queue16_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue16_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue16_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue16_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue16_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue16_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue16_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue16_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue16_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue16_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue16_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue16_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue16_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue16_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue16_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue16_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue16_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue16_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue16_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue16_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue16_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue16_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue16_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue16_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue16_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue16_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue16_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue16_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue16_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue16_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue16_UInt8_31.io.enq.ready) node _account_for_buf_lens_Q_T = eq(incoming_writes_Q.io.deq.bits.end_of_message, UInt<1>(0h0)) node _account_for_buf_lens_Q_T_1 = and(incoming_writes_Q.io.deq.bits.end_of_message, buf_lens_Q.io.enq.ready) node account_for_buf_lens_Q = or(_account_for_buf_lens_Q_T, _account_for_buf_lens_Q_T_1) node _buf_lens_Q_io_enq_valid_T = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _buf_lens_Q_io_enq_valid_T_1 = and(_buf_lens_Q_io_enq_valid_T, incoming_writes_Q.io.deq.bits.end_of_message) connect buf_lens_Q.io.enq.valid, _buf_lens_Q_io_enq_valid_T_1 node _buf_lens_Q_io_enq_bits_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_lens_Q.io.enq.bits, _buf_lens_Q_io_enq_bits_T node _incoming_writes_Q_io_deq_ready_T = and(all_queues_ready, account_for_buf_lens_Q) connect incoming_writes_Q.io.deq.ready, _incoming_writes_Q_io_deq_ready_T node _T_4111 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4112 = and(_T_4111, account_for_buf_lens_Q) when _T_4112 : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_4113 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4114 = and(_T_4113, account_for_buf_lens_Q) node _T_4115 = and(_T_4114, use_this_queue) connect Queue16_UInt8.io.enq.valid, _T_4115 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_4116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4117 = and(_T_4116, account_for_buf_lens_Q) node _T_4118 = and(_T_4117, use_this_queue_1) connect Queue16_UInt8_1.io.enq.valid, _T_4118 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_4119 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4120 = and(_T_4119, account_for_buf_lens_Q) node _T_4121 = and(_T_4120, use_this_queue_2) connect Queue16_UInt8_2.io.enq.valid, _T_4121 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_4122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4123 = and(_T_4122, account_for_buf_lens_Q) node _T_4124 = and(_T_4123, use_this_queue_3) connect Queue16_UInt8_3.io.enq.valid, _T_4124 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_4125 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4126 = and(_T_4125, account_for_buf_lens_Q) node _T_4127 = and(_T_4126, use_this_queue_4) connect Queue16_UInt8_4.io.enq.valid, _T_4127 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_4128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4129 = and(_T_4128, account_for_buf_lens_Q) node _T_4130 = and(_T_4129, use_this_queue_5) connect Queue16_UInt8_5.io.enq.valid, _T_4130 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_4131 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4132 = and(_T_4131, account_for_buf_lens_Q) node _T_4133 = and(_T_4132, use_this_queue_6) connect Queue16_UInt8_6.io.enq.valid, _T_4133 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_4134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4135 = and(_T_4134, account_for_buf_lens_Q) node _T_4136 = and(_T_4135, use_this_queue_7) connect Queue16_UInt8_7.io.enq.valid, _T_4136 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_4137 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4138 = and(_T_4137, account_for_buf_lens_Q) node _T_4139 = and(_T_4138, use_this_queue_8) connect Queue16_UInt8_8.io.enq.valid, _T_4139 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_4140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4141 = and(_T_4140, account_for_buf_lens_Q) node _T_4142 = and(_T_4141, use_this_queue_9) connect Queue16_UInt8_9.io.enq.valid, _T_4142 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_4143 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4144 = and(_T_4143, account_for_buf_lens_Q) node _T_4145 = and(_T_4144, use_this_queue_10) connect Queue16_UInt8_10.io.enq.valid, _T_4145 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_4146 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4147 = and(_T_4146, account_for_buf_lens_Q) node _T_4148 = and(_T_4147, use_this_queue_11) connect Queue16_UInt8_11.io.enq.valid, _T_4148 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_4149 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4150 = and(_T_4149, account_for_buf_lens_Q) node _T_4151 = and(_T_4150, use_this_queue_12) connect Queue16_UInt8_12.io.enq.valid, _T_4151 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_4152 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4153 = and(_T_4152, account_for_buf_lens_Q) node _T_4154 = and(_T_4153, use_this_queue_13) connect Queue16_UInt8_13.io.enq.valid, _T_4154 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_4155 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4156 = and(_T_4155, account_for_buf_lens_Q) node _T_4157 = and(_T_4156, use_this_queue_14) connect Queue16_UInt8_14.io.enq.valid, _T_4157 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_4158 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4159 = and(_T_4158, account_for_buf_lens_Q) node _T_4160 = and(_T_4159, use_this_queue_15) connect Queue16_UInt8_15.io.enq.valid, _T_4160 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_4161 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4162 = and(_T_4161, account_for_buf_lens_Q) node _T_4163 = and(_T_4162, use_this_queue_16) connect Queue16_UInt8_16.io.enq.valid, _T_4163 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_4164 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4165 = and(_T_4164, account_for_buf_lens_Q) node _T_4166 = and(_T_4165, use_this_queue_17) connect Queue16_UInt8_17.io.enq.valid, _T_4166 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_4167 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4168 = and(_T_4167, account_for_buf_lens_Q) node _T_4169 = and(_T_4168, use_this_queue_18) connect Queue16_UInt8_18.io.enq.valid, _T_4169 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_4170 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4171 = and(_T_4170, account_for_buf_lens_Q) node _T_4172 = and(_T_4171, use_this_queue_19) connect Queue16_UInt8_19.io.enq.valid, _T_4172 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_4173 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4174 = and(_T_4173, account_for_buf_lens_Q) node _T_4175 = and(_T_4174, use_this_queue_20) connect Queue16_UInt8_20.io.enq.valid, _T_4175 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_4176 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4177 = and(_T_4176, account_for_buf_lens_Q) node _T_4178 = and(_T_4177, use_this_queue_21) connect Queue16_UInt8_21.io.enq.valid, _T_4178 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_4179 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4180 = and(_T_4179, account_for_buf_lens_Q) node _T_4181 = and(_T_4180, use_this_queue_22) connect Queue16_UInt8_22.io.enq.valid, _T_4181 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_4182 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4183 = and(_T_4182, account_for_buf_lens_Q) node _T_4184 = and(_T_4183, use_this_queue_23) connect Queue16_UInt8_23.io.enq.valid, _T_4184 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_4185 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4186 = and(_T_4185, account_for_buf_lens_Q) node _T_4187 = and(_T_4186, use_this_queue_24) connect Queue16_UInt8_24.io.enq.valid, _T_4187 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_4188 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4189 = and(_T_4188, account_for_buf_lens_Q) node _T_4190 = and(_T_4189, use_this_queue_25) connect Queue16_UInt8_25.io.enq.valid, _T_4190 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_4191 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4192 = and(_T_4191, account_for_buf_lens_Q) node _T_4193 = and(_T_4192, use_this_queue_26) connect Queue16_UInt8_26.io.enq.valid, _T_4193 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_4194 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4195 = and(_T_4194, account_for_buf_lens_Q) node _T_4196 = and(_T_4195, use_this_queue_27) connect Queue16_UInt8_27.io.enq.valid, _T_4196 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_4197 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4198 = and(_T_4197, account_for_buf_lens_Q) node _T_4199 = and(_T_4198, use_this_queue_28) connect Queue16_UInt8_28.io.enq.valid, _T_4199 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_4200 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4201 = and(_T_4200, account_for_buf_lens_Q) node _T_4202 = and(_T_4201, use_this_queue_29) connect Queue16_UInt8_29.io.enq.valid, _T_4202 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_4203 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4204 = and(_T_4203, account_for_buf_lens_Q) node _T_4205 = and(_T_4204, use_this_queue_30) connect Queue16_UInt8_30.io.enq.valid, _T_4205 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_4206 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4207 = and(_T_4206, account_for_buf_lens_Q) node _T_4208 = and(_T_4207, use_this_queue_31) connect Queue16_UInt8_31.io.enq.valid, _T_4208 when Queue16_UInt8.io.deq.valid : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_4209 = asUInt(reset) node _T_4210 = eq(_T_4209, UInt<1>(0h0)) when _T_4210 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_4211 = asUInt(reset) node _T_4212 = eq(_T_4211, UInt<1>(0h0)) when _T_4212 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h0), Queue16_UInt8.io.deq.bits) : printf_7 when Queue16_UInt8_1.io.deq.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_4213 = asUInt(reset) node _T_4214 = eq(_T_4213, UInt<1>(0h0)) when _T_4214 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_4215 = asUInt(reset) node _T_4216 = eq(_T_4215, UInt<1>(0h0)) when _T_4216 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h1), Queue16_UInt8_1.io.deq.bits) : printf_9 when Queue16_UInt8_2.io.deq.valid : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_4217 = asUInt(reset) node _T_4218 = eq(_T_4217, UInt<1>(0h0)) when _T_4218 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_4219 = asUInt(reset) node _T_4220 = eq(_T_4219, UInt<1>(0h0)) when _T_4220 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h2), Queue16_UInt8_2.io.deq.bits) : printf_11 when Queue16_UInt8_3.io.deq.valid : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_4221 = asUInt(reset) node _T_4222 = eq(_T_4221, UInt<1>(0h0)) when _T_4222 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_4223 = asUInt(reset) node _T_4224 = eq(_T_4223, UInt<1>(0h0)) when _T_4224 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h3), Queue16_UInt8_3.io.deq.bits) : printf_13 when Queue16_UInt8_4.io.deq.valid : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_4225 = asUInt(reset) node _T_4226 = eq(_T_4225, UInt<1>(0h0)) when _T_4226 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_4227 = asUInt(reset) node _T_4228 = eq(_T_4227, UInt<1>(0h0)) when _T_4228 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h4), Queue16_UInt8_4.io.deq.bits) : printf_15 when Queue16_UInt8_5.io.deq.valid : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_4229 = asUInt(reset) node _T_4230 = eq(_T_4229, UInt<1>(0h0)) when _T_4230 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_4231 = asUInt(reset) node _T_4232 = eq(_T_4231, UInt<1>(0h0)) when _T_4232 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h5), Queue16_UInt8_5.io.deq.bits) : printf_17 when Queue16_UInt8_6.io.deq.valid : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_4233 = asUInt(reset) node _T_4234 = eq(_T_4233, UInt<1>(0h0)) when _T_4234 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_4235 = asUInt(reset) node _T_4236 = eq(_T_4235, UInt<1>(0h0)) when _T_4236 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h6), Queue16_UInt8_6.io.deq.bits) : printf_19 when Queue16_UInt8_7.io.deq.valid : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_4237 = asUInt(reset) node _T_4238 = eq(_T_4237, UInt<1>(0h0)) when _T_4238 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_4239 = asUInt(reset) node _T_4240 = eq(_T_4239, UInt<1>(0h0)) when _T_4240 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h7), Queue16_UInt8_7.io.deq.bits) : printf_21 when Queue16_UInt8_8.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_4241 = asUInt(reset) node _T_4242 = eq(_T_4241, UInt<1>(0h0)) when _T_4242 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_4243 = asUInt(reset) node _T_4244 = eq(_T_4243, UInt<1>(0h0)) when _T_4244 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h8), Queue16_UInt8_8.io.deq.bits) : printf_23 when Queue16_UInt8_9.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_4245 = asUInt(reset) node _T_4246 = eq(_T_4245, UInt<1>(0h0)) when _T_4246 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_4247 = asUInt(reset) node _T_4248 = eq(_T_4247, UInt<1>(0h0)) when _T_4248 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h9), Queue16_UInt8_9.io.deq.bits) : printf_25 when Queue16_UInt8_10.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_4249 = asUInt(reset) node _T_4250 = eq(_T_4249, UInt<1>(0h0)) when _T_4250 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_4251 = asUInt(reset) node _T_4252 = eq(_T_4251, UInt<1>(0h0)) when _T_4252 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0ha), Queue16_UInt8_10.io.deq.bits) : printf_27 when Queue16_UInt8_11.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_4253 = asUInt(reset) node _T_4254 = eq(_T_4253, UInt<1>(0h0)) when _T_4254 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_4255 = asUInt(reset) node _T_4256 = eq(_T_4255, UInt<1>(0h0)) when _T_4256 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hb), Queue16_UInt8_11.io.deq.bits) : printf_29 when Queue16_UInt8_12.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_4257 = asUInt(reset) node _T_4258 = eq(_T_4257, UInt<1>(0h0)) when _T_4258 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_4259 = asUInt(reset) node _T_4260 = eq(_T_4259, UInt<1>(0h0)) when _T_4260 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hc), Queue16_UInt8_12.io.deq.bits) : printf_31 when Queue16_UInt8_13.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_4261 = asUInt(reset) node _T_4262 = eq(_T_4261, UInt<1>(0h0)) when _T_4262 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_4263 = asUInt(reset) node _T_4264 = eq(_T_4263, UInt<1>(0h0)) when _T_4264 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hd), Queue16_UInt8_13.io.deq.bits) : printf_33 when Queue16_UInt8_14.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_4265 = asUInt(reset) node _T_4266 = eq(_T_4265, UInt<1>(0h0)) when _T_4266 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_4267 = asUInt(reset) node _T_4268 = eq(_T_4267, UInt<1>(0h0)) when _T_4268 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0he), Queue16_UInt8_14.io.deq.bits) : printf_35 when Queue16_UInt8_15.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_4269 = asUInt(reset) node _T_4270 = eq(_T_4269, UInt<1>(0h0)) when _T_4270 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_4271 = asUInt(reset) node _T_4272 = eq(_T_4271, UInt<1>(0h0)) when _T_4272 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hf), Queue16_UInt8_15.io.deq.bits) : printf_37 when Queue16_UInt8_16.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_4273 = asUInt(reset) node _T_4274 = eq(_T_4273, UInt<1>(0h0)) when _T_4274 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_4275 = asUInt(reset) node _T_4276 = eq(_T_4275, UInt<1>(0h0)) when _T_4276 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h10), Queue16_UInt8_16.io.deq.bits) : printf_39 when Queue16_UInt8_17.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_4277 = asUInt(reset) node _T_4278 = eq(_T_4277, UInt<1>(0h0)) when _T_4278 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_4279 = asUInt(reset) node _T_4280 = eq(_T_4279, UInt<1>(0h0)) when _T_4280 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h11), Queue16_UInt8_17.io.deq.bits) : printf_41 when Queue16_UInt8_18.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_4281 = asUInt(reset) node _T_4282 = eq(_T_4281, UInt<1>(0h0)) when _T_4282 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_4283 = asUInt(reset) node _T_4284 = eq(_T_4283, UInt<1>(0h0)) when _T_4284 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h12), Queue16_UInt8_18.io.deq.bits) : printf_43 when Queue16_UInt8_19.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_4285 = asUInt(reset) node _T_4286 = eq(_T_4285, UInt<1>(0h0)) when _T_4286 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_4287 = asUInt(reset) node _T_4288 = eq(_T_4287, UInt<1>(0h0)) when _T_4288 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h13), Queue16_UInt8_19.io.deq.bits) : printf_45 when Queue16_UInt8_20.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_4289 = asUInt(reset) node _T_4290 = eq(_T_4289, UInt<1>(0h0)) when _T_4290 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_4291 = asUInt(reset) node _T_4292 = eq(_T_4291, UInt<1>(0h0)) when _T_4292 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h14), Queue16_UInt8_20.io.deq.bits) : printf_47 when Queue16_UInt8_21.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_4293 = asUInt(reset) node _T_4294 = eq(_T_4293, UInt<1>(0h0)) when _T_4294 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h15), Queue16_UInt8_21.io.deq.bits) : printf_49 when Queue16_UInt8_22.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_4297 = asUInt(reset) node _T_4298 = eq(_T_4297, UInt<1>(0h0)) when _T_4298 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_4299 = asUInt(reset) node _T_4300 = eq(_T_4299, UInt<1>(0h0)) when _T_4300 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h16), Queue16_UInt8_22.io.deq.bits) : printf_51 when Queue16_UInt8_23.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_4301 = asUInt(reset) node _T_4302 = eq(_T_4301, UInt<1>(0h0)) when _T_4302 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_4303 = asUInt(reset) node _T_4304 = eq(_T_4303, UInt<1>(0h0)) when _T_4304 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h17), Queue16_UInt8_23.io.deq.bits) : printf_53 when Queue16_UInt8_24.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_4305 = asUInt(reset) node _T_4306 = eq(_T_4305, UInt<1>(0h0)) when _T_4306 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_4307 = asUInt(reset) node _T_4308 = eq(_T_4307, UInt<1>(0h0)) when _T_4308 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h18), Queue16_UInt8_24.io.deq.bits) : printf_55 when Queue16_UInt8_25.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_4309 = asUInt(reset) node _T_4310 = eq(_T_4309, UInt<1>(0h0)) when _T_4310 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_4311 = asUInt(reset) node _T_4312 = eq(_T_4311, UInt<1>(0h0)) when _T_4312 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h19), Queue16_UInt8_25.io.deq.bits) : printf_57 when Queue16_UInt8_26.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_4313 = asUInt(reset) node _T_4314 = eq(_T_4313, UInt<1>(0h0)) when _T_4314 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_4315 = asUInt(reset) node _T_4316 = eq(_T_4315, UInt<1>(0h0)) when _T_4316 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1a), Queue16_UInt8_26.io.deq.bits) : printf_59 when Queue16_UInt8_27.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_4317 = asUInt(reset) node _T_4318 = eq(_T_4317, UInt<1>(0h0)) when _T_4318 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_4319 = asUInt(reset) node _T_4320 = eq(_T_4319, UInt<1>(0h0)) when _T_4320 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1b), Queue16_UInt8_27.io.deq.bits) : printf_61 when Queue16_UInt8_28.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_4321 = asUInt(reset) node _T_4322 = eq(_T_4321, UInt<1>(0h0)) when _T_4322 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_4323 = asUInt(reset) node _T_4324 = eq(_T_4323, UInt<1>(0h0)) when _T_4324 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1c), Queue16_UInt8_28.io.deq.bits) : printf_63 when Queue16_UInt8_29.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_4325 = asUInt(reset) node _T_4326 = eq(_T_4325, UInt<1>(0h0)) when _T_4326 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_4327 = asUInt(reset) node _T_4328 = eq(_T_4327, UInt<1>(0h0)) when _T_4328 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1d), Queue16_UInt8_29.io.deq.bits) : printf_65 when Queue16_UInt8_30.io.deq.valid : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_4329 = asUInt(reset) node _T_4330 = eq(_T_4329, UInt<1>(0h0)) when _T_4330 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_4331 = asUInt(reset) node _T_4332 = eq(_T_4331, UInt<1>(0h0)) when _T_4332 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1e), Queue16_UInt8_30.io.deq.bits) : printf_67 when Queue16_UInt8_31.io.deq.valid : regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_4333 = asUInt(reset) node _T_4334 = eq(_T_4333, UInt<1>(0h0)) when _T_4334 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_4335 = asUInt(reset) node _T_4336 = eq(_T_4335, UInt<1>(0h0)) when _T_4336 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1f), Queue16_UInt8_31.io.deq.bits) : printf_69 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue16_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue16_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue16_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue16_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue16_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue16_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue16_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue16_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue16_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue16_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue16_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue16_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue16_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue16_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue16_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue16_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue16_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue16_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue16_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue16_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue16_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue16_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue16_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue16_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue16_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue16_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue16_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue16_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue16_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue16_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue16_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue16_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_4337 = eq(UInt<1>(0h0), remapindex) when _T_4337 : connect remapVecData[0], Queue16_UInt8.io.deq.bits connect remapVecValids[0], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[0] node _T_4338 = eq(UInt<1>(0h1), remapindex) when _T_4338 : connect remapVecData[0], Queue16_UInt8_1.io.deq.bits connect remapVecValids[0], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_4339 = eq(UInt<2>(0h2), remapindex) when _T_4339 : connect remapVecData[0], Queue16_UInt8_2.io.deq.bits connect remapVecValids[0], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_4340 = eq(UInt<2>(0h3), remapindex) when _T_4340 : connect remapVecData[0], Queue16_UInt8_3.io.deq.bits connect remapVecValids[0], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_4341 = eq(UInt<3>(0h4), remapindex) when _T_4341 : connect remapVecData[0], Queue16_UInt8_4.io.deq.bits connect remapVecValids[0], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_4342 = eq(UInt<3>(0h5), remapindex) when _T_4342 : connect remapVecData[0], Queue16_UInt8_5.io.deq.bits connect remapVecValids[0], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_4343 = eq(UInt<3>(0h6), remapindex) when _T_4343 : connect remapVecData[0], Queue16_UInt8_6.io.deq.bits connect remapVecValids[0], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_4344 = eq(UInt<3>(0h7), remapindex) when _T_4344 : connect remapVecData[0], Queue16_UInt8_7.io.deq.bits connect remapVecValids[0], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_4345 = eq(UInt<4>(0h8), remapindex) when _T_4345 : connect remapVecData[0], Queue16_UInt8_8.io.deq.bits connect remapVecValids[0], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_4346 = eq(UInt<4>(0h9), remapindex) when _T_4346 : connect remapVecData[0], Queue16_UInt8_9.io.deq.bits connect remapVecValids[0], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_4347 = eq(UInt<4>(0ha), remapindex) when _T_4347 : connect remapVecData[0], Queue16_UInt8_10.io.deq.bits connect remapVecValids[0], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_4348 = eq(UInt<4>(0hb), remapindex) when _T_4348 : connect remapVecData[0], Queue16_UInt8_11.io.deq.bits connect remapVecValids[0], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_4349 = eq(UInt<4>(0hc), remapindex) when _T_4349 : connect remapVecData[0], Queue16_UInt8_12.io.deq.bits connect remapVecValids[0], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_4350 = eq(UInt<4>(0hd), remapindex) when _T_4350 : connect remapVecData[0], Queue16_UInt8_13.io.deq.bits connect remapVecValids[0], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_4351 = eq(UInt<4>(0he), remapindex) when _T_4351 : connect remapVecData[0], Queue16_UInt8_14.io.deq.bits connect remapVecValids[0], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_4352 = eq(UInt<4>(0hf), remapindex) when _T_4352 : connect remapVecData[0], Queue16_UInt8_15.io.deq.bits connect remapVecValids[0], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_4353 = eq(UInt<5>(0h10), remapindex) when _T_4353 : connect remapVecData[0], Queue16_UInt8_16.io.deq.bits connect remapVecValids[0], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_4354 = eq(UInt<5>(0h11), remapindex) when _T_4354 : connect remapVecData[0], Queue16_UInt8_17.io.deq.bits connect remapVecValids[0], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_4355 = eq(UInt<5>(0h12), remapindex) when _T_4355 : connect remapVecData[0], Queue16_UInt8_18.io.deq.bits connect remapVecValids[0], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_4356 = eq(UInt<5>(0h13), remapindex) when _T_4356 : connect remapVecData[0], Queue16_UInt8_19.io.deq.bits connect remapVecValids[0], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_4357 = eq(UInt<5>(0h14), remapindex) when _T_4357 : connect remapVecData[0], Queue16_UInt8_20.io.deq.bits connect remapVecValids[0], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_4358 = eq(UInt<5>(0h15), remapindex) when _T_4358 : connect remapVecData[0], Queue16_UInt8_21.io.deq.bits connect remapVecValids[0], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_4359 = eq(UInt<5>(0h16), remapindex) when _T_4359 : connect remapVecData[0], Queue16_UInt8_22.io.deq.bits connect remapVecValids[0], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_4360 = eq(UInt<5>(0h17), remapindex) when _T_4360 : connect remapVecData[0], Queue16_UInt8_23.io.deq.bits connect remapVecValids[0], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_4361 = eq(UInt<5>(0h18), remapindex) when _T_4361 : connect remapVecData[0], Queue16_UInt8_24.io.deq.bits connect remapVecValids[0], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_4362 = eq(UInt<5>(0h19), remapindex) when _T_4362 : connect remapVecData[0], Queue16_UInt8_25.io.deq.bits connect remapVecValids[0], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_4363 = eq(UInt<5>(0h1a), remapindex) when _T_4363 : connect remapVecData[0], Queue16_UInt8_26.io.deq.bits connect remapVecValids[0], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_4364 = eq(UInt<5>(0h1b), remapindex) when _T_4364 : connect remapVecData[0], Queue16_UInt8_27.io.deq.bits connect remapVecValids[0], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_4365 = eq(UInt<5>(0h1c), remapindex) when _T_4365 : connect remapVecData[0], Queue16_UInt8_28.io.deq.bits connect remapVecValids[0], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_4366 = eq(UInt<5>(0h1d), remapindex) when _T_4366 : connect remapVecData[0], Queue16_UInt8_29.io.deq.bits connect remapVecValids[0], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_4367 = eq(UInt<5>(0h1e), remapindex) when _T_4367 : connect remapVecData[0], Queue16_UInt8_30.io.deq.bits connect remapVecValids[0], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_4368 = eq(UInt<5>(0h1f), remapindex) when _T_4368 : connect remapVecData[0], Queue16_UInt8_31.io.deq.bits connect remapVecValids[0], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_4369 = eq(UInt<1>(0h0), remapindex_1) when _T_4369 : connect remapVecData[1], Queue16_UInt8.io.deq.bits connect remapVecValids[1], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[1] node _T_4370 = eq(UInt<1>(0h1), remapindex_1) when _T_4370 : connect remapVecData[1], Queue16_UInt8_1.io.deq.bits connect remapVecValids[1], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_4371 = eq(UInt<2>(0h2), remapindex_1) when _T_4371 : connect remapVecData[1], Queue16_UInt8_2.io.deq.bits connect remapVecValids[1], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_4372 = eq(UInt<2>(0h3), remapindex_1) when _T_4372 : connect remapVecData[1], Queue16_UInt8_3.io.deq.bits connect remapVecValids[1], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_4373 = eq(UInt<3>(0h4), remapindex_1) when _T_4373 : connect remapVecData[1], Queue16_UInt8_4.io.deq.bits connect remapVecValids[1], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_4374 = eq(UInt<3>(0h5), remapindex_1) when _T_4374 : connect remapVecData[1], Queue16_UInt8_5.io.deq.bits connect remapVecValids[1], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_4375 = eq(UInt<3>(0h6), remapindex_1) when _T_4375 : connect remapVecData[1], Queue16_UInt8_6.io.deq.bits connect remapVecValids[1], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_4376 = eq(UInt<3>(0h7), remapindex_1) when _T_4376 : connect remapVecData[1], Queue16_UInt8_7.io.deq.bits connect remapVecValids[1], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_4377 = eq(UInt<4>(0h8), remapindex_1) when _T_4377 : connect remapVecData[1], Queue16_UInt8_8.io.deq.bits connect remapVecValids[1], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_4378 = eq(UInt<4>(0h9), remapindex_1) when _T_4378 : connect remapVecData[1], Queue16_UInt8_9.io.deq.bits connect remapVecValids[1], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_4379 = eq(UInt<4>(0ha), remapindex_1) when _T_4379 : connect remapVecData[1], Queue16_UInt8_10.io.deq.bits connect remapVecValids[1], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_4380 = eq(UInt<4>(0hb), remapindex_1) when _T_4380 : connect remapVecData[1], Queue16_UInt8_11.io.deq.bits connect remapVecValids[1], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_4381 = eq(UInt<4>(0hc), remapindex_1) when _T_4381 : connect remapVecData[1], Queue16_UInt8_12.io.deq.bits connect remapVecValids[1], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_4382 = eq(UInt<4>(0hd), remapindex_1) when _T_4382 : connect remapVecData[1], Queue16_UInt8_13.io.deq.bits connect remapVecValids[1], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_4383 = eq(UInt<4>(0he), remapindex_1) when _T_4383 : connect remapVecData[1], Queue16_UInt8_14.io.deq.bits connect remapVecValids[1], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_4384 = eq(UInt<4>(0hf), remapindex_1) when _T_4384 : connect remapVecData[1], Queue16_UInt8_15.io.deq.bits connect remapVecValids[1], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_4385 = eq(UInt<5>(0h10), remapindex_1) when _T_4385 : connect remapVecData[1], Queue16_UInt8_16.io.deq.bits connect remapVecValids[1], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_4386 = eq(UInt<5>(0h11), remapindex_1) when _T_4386 : connect remapVecData[1], Queue16_UInt8_17.io.deq.bits connect remapVecValids[1], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_4387 = eq(UInt<5>(0h12), remapindex_1) when _T_4387 : connect remapVecData[1], Queue16_UInt8_18.io.deq.bits connect remapVecValids[1], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_4388 = eq(UInt<5>(0h13), remapindex_1) when _T_4388 : connect remapVecData[1], Queue16_UInt8_19.io.deq.bits connect remapVecValids[1], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_4389 = eq(UInt<5>(0h14), remapindex_1) when _T_4389 : connect remapVecData[1], Queue16_UInt8_20.io.deq.bits connect remapVecValids[1], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_4390 = eq(UInt<5>(0h15), remapindex_1) when _T_4390 : connect remapVecData[1], Queue16_UInt8_21.io.deq.bits connect remapVecValids[1], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_4391 = eq(UInt<5>(0h16), remapindex_1) when _T_4391 : connect remapVecData[1], Queue16_UInt8_22.io.deq.bits connect remapVecValids[1], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_4392 = eq(UInt<5>(0h17), remapindex_1) when _T_4392 : connect remapVecData[1], Queue16_UInt8_23.io.deq.bits connect remapVecValids[1], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_4393 = eq(UInt<5>(0h18), remapindex_1) when _T_4393 : connect remapVecData[1], Queue16_UInt8_24.io.deq.bits connect remapVecValids[1], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_4394 = eq(UInt<5>(0h19), remapindex_1) when _T_4394 : connect remapVecData[1], Queue16_UInt8_25.io.deq.bits connect remapVecValids[1], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_4395 = eq(UInt<5>(0h1a), remapindex_1) when _T_4395 : connect remapVecData[1], Queue16_UInt8_26.io.deq.bits connect remapVecValids[1], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_4396 = eq(UInt<5>(0h1b), remapindex_1) when _T_4396 : connect remapVecData[1], Queue16_UInt8_27.io.deq.bits connect remapVecValids[1], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_4397 = eq(UInt<5>(0h1c), remapindex_1) when _T_4397 : connect remapVecData[1], Queue16_UInt8_28.io.deq.bits connect remapVecValids[1], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_4398 = eq(UInt<5>(0h1d), remapindex_1) when _T_4398 : connect remapVecData[1], Queue16_UInt8_29.io.deq.bits connect remapVecValids[1], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_4399 = eq(UInt<5>(0h1e), remapindex_1) when _T_4399 : connect remapVecData[1], Queue16_UInt8_30.io.deq.bits connect remapVecValids[1], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_4400 = eq(UInt<5>(0h1f), remapindex_1) when _T_4400 : connect remapVecData[1], Queue16_UInt8_31.io.deq.bits connect remapVecValids[1], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_4401 = eq(UInt<1>(0h0), remapindex_2) when _T_4401 : connect remapVecData[2], Queue16_UInt8.io.deq.bits connect remapVecValids[2], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[2] node _T_4402 = eq(UInt<1>(0h1), remapindex_2) when _T_4402 : connect remapVecData[2], Queue16_UInt8_1.io.deq.bits connect remapVecValids[2], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_4403 = eq(UInt<2>(0h2), remapindex_2) when _T_4403 : connect remapVecData[2], Queue16_UInt8_2.io.deq.bits connect remapVecValids[2], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_4404 = eq(UInt<2>(0h3), remapindex_2) when _T_4404 : connect remapVecData[2], Queue16_UInt8_3.io.deq.bits connect remapVecValids[2], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_4405 = eq(UInt<3>(0h4), remapindex_2) when _T_4405 : connect remapVecData[2], Queue16_UInt8_4.io.deq.bits connect remapVecValids[2], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_4406 = eq(UInt<3>(0h5), remapindex_2) when _T_4406 : connect remapVecData[2], Queue16_UInt8_5.io.deq.bits connect remapVecValids[2], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_4407 = eq(UInt<3>(0h6), remapindex_2) when _T_4407 : connect remapVecData[2], Queue16_UInt8_6.io.deq.bits connect remapVecValids[2], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_4408 = eq(UInt<3>(0h7), remapindex_2) when _T_4408 : connect remapVecData[2], Queue16_UInt8_7.io.deq.bits connect remapVecValids[2], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_4409 = eq(UInt<4>(0h8), remapindex_2) when _T_4409 : connect remapVecData[2], Queue16_UInt8_8.io.deq.bits connect remapVecValids[2], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_4410 = eq(UInt<4>(0h9), remapindex_2) when _T_4410 : connect remapVecData[2], Queue16_UInt8_9.io.deq.bits connect remapVecValids[2], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_4411 = eq(UInt<4>(0ha), remapindex_2) when _T_4411 : connect remapVecData[2], Queue16_UInt8_10.io.deq.bits connect remapVecValids[2], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_4412 = eq(UInt<4>(0hb), remapindex_2) when _T_4412 : connect remapVecData[2], Queue16_UInt8_11.io.deq.bits connect remapVecValids[2], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_4413 = eq(UInt<4>(0hc), remapindex_2) when _T_4413 : connect remapVecData[2], Queue16_UInt8_12.io.deq.bits connect remapVecValids[2], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_4414 = eq(UInt<4>(0hd), remapindex_2) when _T_4414 : connect remapVecData[2], Queue16_UInt8_13.io.deq.bits connect remapVecValids[2], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_4415 = eq(UInt<4>(0he), remapindex_2) when _T_4415 : connect remapVecData[2], Queue16_UInt8_14.io.deq.bits connect remapVecValids[2], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_4416 = eq(UInt<4>(0hf), remapindex_2) when _T_4416 : connect remapVecData[2], Queue16_UInt8_15.io.deq.bits connect remapVecValids[2], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_4417 = eq(UInt<5>(0h10), remapindex_2) when _T_4417 : connect remapVecData[2], Queue16_UInt8_16.io.deq.bits connect remapVecValids[2], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_4418 = eq(UInt<5>(0h11), remapindex_2) when _T_4418 : connect remapVecData[2], Queue16_UInt8_17.io.deq.bits connect remapVecValids[2], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_4419 = eq(UInt<5>(0h12), remapindex_2) when _T_4419 : connect remapVecData[2], Queue16_UInt8_18.io.deq.bits connect remapVecValids[2], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_4420 = eq(UInt<5>(0h13), remapindex_2) when _T_4420 : connect remapVecData[2], Queue16_UInt8_19.io.deq.bits connect remapVecValids[2], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_4421 = eq(UInt<5>(0h14), remapindex_2) when _T_4421 : connect remapVecData[2], Queue16_UInt8_20.io.deq.bits connect remapVecValids[2], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_4422 = eq(UInt<5>(0h15), remapindex_2) when _T_4422 : connect remapVecData[2], Queue16_UInt8_21.io.deq.bits connect remapVecValids[2], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_4423 = eq(UInt<5>(0h16), remapindex_2) when _T_4423 : connect remapVecData[2], Queue16_UInt8_22.io.deq.bits connect remapVecValids[2], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_4424 = eq(UInt<5>(0h17), remapindex_2) when _T_4424 : connect remapVecData[2], Queue16_UInt8_23.io.deq.bits connect remapVecValids[2], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_4425 = eq(UInt<5>(0h18), remapindex_2) when _T_4425 : connect remapVecData[2], Queue16_UInt8_24.io.deq.bits connect remapVecValids[2], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_4426 = eq(UInt<5>(0h19), remapindex_2) when _T_4426 : connect remapVecData[2], Queue16_UInt8_25.io.deq.bits connect remapVecValids[2], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_4427 = eq(UInt<5>(0h1a), remapindex_2) when _T_4427 : connect remapVecData[2], Queue16_UInt8_26.io.deq.bits connect remapVecValids[2], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_4428 = eq(UInt<5>(0h1b), remapindex_2) when _T_4428 : connect remapVecData[2], Queue16_UInt8_27.io.deq.bits connect remapVecValids[2], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_4429 = eq(UInt<5>(0h1c), remapindex_2) when _T_4429 : connect remapVecData[2], Queue16_UInt8_28.io.deq.bits connect remapVecValids[2], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_4430 = eq(UInt<5>(0h1d), remapindex_2) when _T_4430 : connect remapVecData[2], Queue16_UInt8_29.io.deq.bits connect remapVecValids[2], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_4431 = eq(UInt<5>(0h1e), remapindex_2) when _T_4431 : connect remapVecData[2], Queue16_UInt8_30.io.deq.bits connect remapVecValids[2], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_4432 = eq(UInt<5>(0h1f), remapindex_2) when _T_4432 : connect remapVecData[2], Queue16_UInt8_31.io.deq.bits connect remapVecValids[2], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_4433 = eq(UInt<1>(0h0), remapindex_3) when _T_4433 : connect remapVecData[3], Queue16_UInt8.io.deq.bits connect remapVecValids[3], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[3] node _T_4434 = eq(UInt<1>(0h1), remapindex_3) when _T_4434 : connect remapVecData[3], Queue16_UInt8_1.io.deq.bits connect remapVecValids[3], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_4435 = eq(UInt<2>(0h2), remapindex_3) when _T_4435 : connect remapVecData[3], Queue16_UInt8_2.io.deq.bits connect remapVecValids[3], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_4436 = eq(UInt<2>(0h3), remapindex_3) when _T_4436 : connect remapVecData[3], Queue16_UInt8_3.io.deq.bits connect remapVecValids[3], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_4437 = eq(UInt<3>(0h4), remapindex_3) when _T_4437 : connect remapVecData[3], Queue16_UInt8_4.io.deq.bits connect remapVecValids[3], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_4438 = eq(UInt<3>(0h5), remapindex_3) when _T_4438 : connect remapVecData[3], Queue16_UInt8_5.io.deq.bits connect remapVecValids[3], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_4439 = eq(UInt<3>(0h6), remapindex_3) when _T_4439 : connect remapVecData[3], Queue16_UInt8_6.io.deq.bits connect remapVecValids[3], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_4440 = eq(UInt<3>(0h7), remapindex_3) when _T_4440 : connect remapVecData[3], Queue16_UInt8_7.io.deq.bits connect remapVecValids[3], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_4441 = eq(UInt<4>(0h8), remapindex_3) when _T_4441 : connect remapVecData[3], Queue16_UInt8_8.io.deq.bits connect remapVecValids[3], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_4442 = eq(UInt<4>(0h9), remapindex_3) when _T_4442 : connect remapVecData[3], Queue16_UInt8_9.io.deq.bits connect remapVecValids[3], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_4443 = eq(UInt<4>(0ha), remapindex_3) when _T_4443 : connect remapVecData[3], Queue16_UInt8_10.io.deq.bits connect remapVecValids[3], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_4444 = eq(UInt<4>(0hb), remapindex_3) when _T_4444 : connect remapVecData[3], Queue16_UInt8_11.io.deq.bits connect remapVecValids[3], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_4445 = eq(UInt<4>(0hc), remapindex_3) when _T_4445 : connect remapVecData[3], Queue16_UInt8_12.io.deq.bits connect remapVecValids[3], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_4446 = eq(UInt<4>(0hd), remapindex_3) when _T_4446 : connect remapVecData[3], Queue16_UInt8_13.io.deq.bits connect remapVecValids[3], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_4447 = eq(UInt<4>(0he), remapindex_3) when _T_4447 : connect remapVecData[3], Queue16_UInt8_14.io.deq.bits connect remapVecValids[3], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_4448 = eq(UInt<4>(0hf), remapindex_3) when _T_4448 : connect remapVecData[3], Queue16_UInt8_15.io.deq.bits connect remapVecValids[3], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_4449 = eq(UInt<5>(0h10), remapindex_3) when _T_4449 : connect remapVecData[3], Queue16_UInt8_16.io.deq.bits connect remapVecValids[3], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_4450 = eq(UInt<5>(0h11), remapindex_3) when _T_4450 : connect remapVecData[3], Queue16_UInt8_17.io.deq.bits connect remapVecValids[3], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_4451 = eq(UInt<5>(0h12), remapindex_3) when _T_4451 : connect remapVecData[3], Queue16_UInt8_18.io.deq.bits connect remapVecValids[3], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_4452 = eq(UInt<5>(0h13), remapindex_3) when _T_4452 : connect remapVecData[3], Queue16_UInt8_19.io.deq.bits connect remapVecValids[3], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_4453 = eq(UInt<5>(0h14), remapindex_3) when _T_4453 : connect remapVecData[3], Queue16_UInt8_20.io.deq.bits connect remapVecValids[3], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_4454 = eq(UInt<5>(0h15), remapindex_3) when _T_4454 : connect remapVecData[3], Queue16_UInt8_21.io.deq.bits connect remapVecValids[3], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_4455 = eq(UInt<5>(0h16), remapindex_3) when _T_4455 : connect remapVecData[3], Queue16_UInt8_22.io.deq.bits connect remapVecValids[3], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_4456 = eq(UInt<5>(0h17), remapindex_3) when _T_4456 : connect remapVecData[3], Queue16_UInt8_23.io.deq.bits connect remapVecValids[3], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_4457 = eq(UInt<5>(0h18), remapindex_3) when _T_4457 : connect remapVecData[3], Queue16_UInt8_24.io.deq.bits connect remapVecValids[3], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_4458 = eq(UInt<5>(0h19), remapindex_3) when _T_4458 : connect remapVecData[3], Queue16_UInt8_25.io.deq.bits connect remapVecValids[3], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_4459 = eq(UInt<5>(0h1a), remapindex_3) when _T_4459 : connect remapVecData[3], Queue16_UInt8_26.io.deq.bits connect remapVecValids[3], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_4460 = eq(UInt<5>(0h1b), remapindex_3) when _T_4460 : connect remapVecData[3], Queue16_UInt8_27.io.deq.bits connect remapVecValids[3], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_4461 = eq(UInt<5>(0h1c), remapindex_3) when _T_4461 : connect remapVecData[3], Queue16_UInt8_28.io.deq.bits connect remapVecValids[3], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_4462 = eq(UInt<5>(0h1d), remapindex_3) when _T_4462 : connect remapVecData[3], Queue16_UInt8_29.io.deq.bits connect remapVecValids[3], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_4463 = eq(UInt<5>(0h1e), remapindex_3) when _T_4463 : connect remapVecData[3], Queue16_UInt8_30.io.deq.bits connect remapVecValids[3], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_4464 = eq(UInt<5>(0h1f), remapindex_3) when _T_4464 : connect remapVecData[3], Queue16_UInt8_31.io.deq.bits connect remapVecValids[3], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_4465 = eq(UInt<1>(0h0), remapindex_4) when _T_4465 : connect remapVecData[4], Queue16_UInt8.io.deq.bits connect remapVecValids[4], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[4] node _T_4466 = eq(UInt<1>(0h1), remapindex_4) when _T_4466 : connect remapVecData[4], Queue16_UInt8_1.io.deq.bits connect remapVecValids[4], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_4467 = eq(UInt<2>(0h2), remapindex_4) when _T_4467 : connect remapVecData[4], Queue16_UInt8_2.io.deq.bits connect remapVecValids[4], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_4468 = eq(UInt<2>(0h3), remapindex_4) when _T_4468 : connect remapVecData[4], Queue16_UInt8_3.io.deq.bits connect remapVecValids[4], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_4469 = eq(UInt<3>(0h4), remapindex_4) when _T_4469 : connect remapVecData[4], Queue16_UInt8_4.io.deq.bits connect remapVecValids[4], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_4470 = eq(UInt<3>(0h5), remapindex_4) when _T_4470 : connect remapVecData[4], Queue16_UInt8_5.io.deq.bits connect remapVecValids[4], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_4471 = eq(UInt<3>(0h6), remapindex_4) when _T_4471 : connect remapVecData[4], Queue16_UInt8_6.io.deq.bits connect remapVecValids[4], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_4472 = eq(UInt<3>(0h7), remapindex_4) when _T_4472 : connect remapVecData[4], Queue16_UInt8_7.io.deq.bits connect remapVecValids[4], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_4473 = eq(UInt<4>(0h8), remapindex_4) when _T_4473 : connect remapVecData[4], Queue16_UInt8_8.io.deq.bits connect remapVecValids[4], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_4474 = eq(UInt<4>(0h9), remapindex_4) when _T_4474 : connect remapVecData[4], Queue16_UInt8_9.io.deq.bits connect remapVecValids[4], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_4475 = eq(UInt<4>(0ha), remapindex_4) when _T_4475 : connect remapVecData[4], Queue16_UInt8_10.io.deq.bits connect remapVecValids[4], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_4476 = eq(UInt<4>(0hb), remapindex_4) when _T_4476 : connect remapVecData[4], Queue16_UInt8_11.io.deq.bits connect remapVecValids[4], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_4477 = eq(UInt<4>(0hc), remapindex_4) when _T_4477 : connect remapVecData[4], Queue16_UInt8_12.io.deq.bits connect remapVecValids[4], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_4478 = eq(UInt<4>(0hd), remapindex_4) when _T_4478 : connect remapVecData[4], Queue16_UInt8_13.io.deq.bits connect remapVecValids[4], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_4479 = eq(UInt<4>(0he), remapindex_4) when _T_4479 : connect remapVecData[4], Queue16_UInt8_14.io.deq.bits connect remapVecValids[4], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_4480 = eq(UInt<4>(0hf), remapindex_4) when _T_4480 : connect remapVecData[4], Queue16_UInt8_15.io.deq.bits connect remapVecValids[4], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_4481 = eq(UInt<5>(0h10), remapindex_4) when _T_4481 : connect remapVecData[4], Queue16_UInt8_16.io.deq.bits connect remapVecValids[4], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_4482 = eq(UInt<5>(0h11), remapindex_4) when _T_4482 : connect remapVecData[4], Queue16_UInt8_17.io.deq.bits connect remapVecValids[4], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_4483 = eq(UInt<5>(0h12), remapindex_4) when _T_4483 : connect remapVecData[4], Queue16_UInt8_18.io.deq.bits connect remapVecValids[4], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_4484 = eq(UInt<5>(0h13), remapindex_4) when _T_4484 : connect remapVecData[4], Queue16_UInt8_19.io.deq.bits connect remapVecValids[4], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_4485 = eq(UInt<5>(0h14), remapindex_4) when _T_4485 : connect remapVecData[4], Queue16_UInt8_20.io.deq.bits connect remapVecValids[4], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_4486 = eq(UInt<5>(0h15), remapindex_4) when _T_4486 : connect remapVecData[4], Queue16_UInt8_21.io.deq.bits connect remapVecValids[4], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_4487 = eq(UInt<5>(0h16), remapindex_4) when _T_4487 : connect remapVecData[4], Queue16_UInt8_22.io.deq.bits connect remapVecValids[4], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_4488 = eq(UInt<5>(0h17), remapindex_4) when _T_4488 : connect remapVecData[4], Queue16_UInt8_23.io.deq.bits connect remapVecValids[4], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_4489 = eq(UInt<5>(0h18), remapindex_4) when _T_4489 : connect remapVecData[4], Queue16_UInt8_24.io.deq.bits connect remapVecValids[4], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_4490 = eq(UInt<5>(0h19), remapindex_4) when _T_4490 : connect remapVecData[4], Queue16_UInt8_25.io.deq.bits connect remapVecValids[4], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_4491 = eq(UInt<5>(0h1a), remapindex_4) when _T_4491 : connect remapVecData[4], Queue16_UInt8_26.io.deq.bits connect remapVecValids[4], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_4492 = eq(UInt<5>(0h1b), remapindex_4) when _T_4492 : connect remapVecData[4], Queue16_UInt8_27.io.deq.bits connect remapVecValids[4], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_4493 = eq(UInt<5>(0h1c), remapindex_4) when _T_4493 : connect remapVecData[4], Queue16_UInt8_28.io.deq.bits connect remapVecValids[4], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_4494 = eq(UInt<5>(0h1d), remapindex_4) when _T_4494 : connect remapVecData[4], Queue16_UInt8_29.io.deq.bits connect remapVecValids[4], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_4495 = eq(UInt<5>(0h1e), remapindex_4) when _T_4495 : connect remapVecData[4], Queue16_UInt8_30.io.deq.bits connect remapVecValids[4], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_4496 = eq(UInt<5>(0h1f), remapindex_4) when _T_4496 : connect remapVecData[4], Queue16_UInt8_31.io.deq.bits connect remapVecValids[4], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_4497 = eq(UInt<1>(0h0), remapindex_5) when _T_4497 : connect remapVecData[5], Queue16_UInt8.io.deq.bits connect remapVecValids[5], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[5] node _T_4498 = eq(UInt<1>(0h1), remapindex_5) when _T_4498 : connect remapVecData[5], Queue16_UInt8_1.io.deq.bits connect remapVecValids[5], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_4499 = eq(UInt<2>(0h2), remapindex_5) when _T_4499 : connect remapVecData[5], Queue16_UInt8_2.io.deq.bits connect remapVecValids[5], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_4500 = eq(UInt<2>(0h3), remapindex_5) when _T_4500 : connect remapVecData[5], Queue16_UInt8_3.io.deq.bits connect remapVecValids[5], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_4501 = eq(UInt<3>(0h4), remapindex_5) when _T_4501 : connect remapVecData[5], Queue16_UInt8_4.io.deq.bits connect remapVecValids[5], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_4502 = eq(UInt<3>(0h5), remapindex_5) when _T_4502 : connect remapVecData[5], Queue16_UInt8_5.io.deq.bits connect remapVecValids[5], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_4503 = eq(UInt<3>(0h6), remapindex_5) when _T_4503 : connect remapVecData[5], Queue16_UInt8_6.io.deq.bits connect remapVecValids[5], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_4504 = eq(UInt<3>(0h7), remapindex_5) when _T_4504 : connect remapVecData[5], Queue16_UInt8_7.io.deq.bits connect remapVecValids[5], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_4505 = eq(UInt<4>(0h8), remapindex_5) when _T_4505 : connect remapVecData[5], Queue16_UInt8_8.io.deq.bits connect remapVecValids[5], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_4506 = eq(UInt<4>(0h9), remapindex_5) when _T_4506 : connect remapVecData[5], Queue16_UInt8_9.io.deq.bits connect remapVecValids[5], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_4507 = eq(UInt<4>(0ha), remapindex_5) when _T_4507 : connect remapVecData[5], Queue16_UInt8_10.io.deq.bits connect remapVecValids[5], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_4508 = eq(UInt<4>(0hb), remapindex_5) when _T_4508 : connect remapVecData[5], Queue16_UInt8_11.io.deq.bits connect remapVecValids[5], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_4509 = eq(UInt<4>(0hc), remapindex_5) when _T_4509 : connect remapVecData[5], Queue16_UInt8_12.io.deq.bits connect remapVecValids[5], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_4510 = eq(UInt<4>(0hd), remapindex_5) when _T_4510 : connect remapVecData[5], Queue16_UInt8_13.io.deq.bits connect remapVecValids[5], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_4511 = eq(UInt<4>(0he), remapindex_5) when _T_4511 : connect remapVecData[5], Queue16_UInt8_14.io.deq.bits connect remapVecValids[5], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_4512 = eq(UInt<4>(0hf), remapindex_5) when _T_4512 : connect remapVecData[5], Queue16_UInt8_15.io.deq.bits connect remapVecValids[5], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_4513 = eq(UInt<5>(0h10), remapindex_5) when _T_4513 : connect remapVecData[5], Queue16_UInt8_16.io.deq.bits connect remapVecValids[5], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_4514 = eq(UInt<5>(0h11), remapindex_5) when _T_4514 : connect remapVecData[5], Queue16_UInt8_17.io.deq.bits connect remapVecValids[5], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_4515 = eq(UInt<5>(0h12), remapindex_5) when _T_4515 : connect remapVecData[5], Queue16_UInt8_18.io.deq.bits connect remapVecValids[5], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_4516 = eq(UInt<5>(0h13), remapindex_5) when _T_4516 : connect remapVecData[5], Queue16_UInt8_19.io.deq.bits connect remapVecValids[5], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_4517 = eq(UInt<5>(0h14), remapindex_5) when _T_4517 : connect remapVecData[5], Queue16_UInt8_20.io.deq.bits connect remapVecValids[5], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_4518 = eq(UInt<5>(0h15), remapindex_5) when _T_4518 : connect remapVecData[5], Queue16_UInt8_21.io.deq.bits connect remapVecValids[5], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_4519 = eq(UInt<5>(0h16), remapindex_5) when _T_4519 : connect remapVecData[5], Queue16_UInt8_22.io.deq.bits connect remapVecValids[5], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_4520 = eq(UInt<5>(0h17), remapindex_5) when _T_4520 : connect remapVecData[5], Queue16_UInt8_23.io.deq.bits connect remapVecValids[5], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_4521 = eq(UInt<5>(0h18), remapindex_5) when _T_4521 : connect remapVecData[5], Queue16_UInt8_24.io.deq.bits connect remapVecValids[5], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_4522 = eq(UInt<5>(0h19), remapindex_5) when _T_4522 : connect remapVecData[5], Queue16_UInt8_25.io.deq.bits connect remapVecValids[5], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_4523 = eq(UInt<5>(0h1a), remapindex_5) when _T_4523 : connect remapVecData[5], Queue16_UInt8_26.io.deq.bits connect remapVecValids[5], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_4524 = eq(UInt<5>(0h1b), remapindex_5) when _T_4524 : connect remapVecData[5], Queue16_UInt8_27.io.deq.bits connect remapVecValids[5], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_4525 = eq(UInt<5>(0h1c), remapindex_5) when _T_4525 : connect remapVecData[5], Queue16_UInt8_28.io.deq.bits connect remapVecValids[5], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_4526 = eq(UInt<5>(0h1d), remapindex_5) when _T_4526 : connect remapVecData[5], Queue16_UInt8_29.io.deq.bits connect remapVecValids[5], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_4527 = eq(UInt<5>(0h1e), remapindex_5) when _T_4527 : connect remapVecData[5], Queue16_UInt8_30.io.deq.bits connect remapVecValids[5], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_4528 = eq(UInt<5>(0h1f), remapindex_5) when _T_4528 : connect remapVecData[5], Queue16_UInt8_31.io.deq.bits connect remapVecValids[5], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_4529 = eq(UInt<1>(0h0), remapindex_6) when _T_4529 : connect remapVecData[6], Queue16_UInt8.io.deq.bits connect remapVecValids[6], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[6] node _T_4530 = eq(UInt<1>(0h1), remapindex_6) when _T_4530 : connect remapVecData[6], Queue16_UInt8_1.io.deq.bits connect remapVecValids[6], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_4531 = eq(UInt<2>(0h2), remapindex_6) when _T_4531 : connect remapVecData[6], Queue16_UInt8_2.io.deq.bits connect remapVecValids[6], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_4532 = eq(UInt<2>(0h3), remapindex_6) when _T_4532 : connect remapVecData[6], Queue16_UInt8_3.io.deq.bits connect remapVecValids[6], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_4533 = eq(UInt<3>(0h4), remapindex_6) when _T_4533 : connect remapVecData[6], Queue16_UInt8_4.io.deq.bits connect remapVecValids[6], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_4534 = eq(UInt<3>(0h5), remapindex_6) when _T_4534 : connect remapVecData[6], Queue16_UInt8_5.io.deq.bits connect remapVecValids[6], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_4535 = eq(UInt<3>(0h6), remapindex_6) when _T_4535 : connect remapVecData[6], Queue16_UInt8_6.io.deq.bits connect remapVecValids[6], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_4536 = eq(UInt<3>(0h7), remapindex_6) when _T_4536 : connect remapVecData[6], Queue16_UInt8_7.io.deq.bits connect remapVecValids[6], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_4537 = eq(UInt<4>(0h8), remapindex_6) when _T_4537 : connect remapVecData[6], Queue16_UInt8_8.io.deq.bits connect remapVecValids[6], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_4538 = eq(UInt<4>(0h9), remapindex_6) when _T_4538 : connect remapVecData[6], Queue16_UInt8_9.io.deq.bits connect remapVecValids[6], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_4539 = eq(UInt<4>(0ha), remapindex_6) when _T_4539 : connect remapVecData[6], Queue16_UInt8_10.io.deq.bits connect remapVecValids[6], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_4540 = eq(UInt<4>(0hb), remapindex_6) when _T_4540 : connect remapVecData[6], Queue16_UInt8_11.io.deq.bits connect remapVecValids[6], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_4541 = eq(UInt<4>(0hc), remapindex_6) when _T_4541 : connect remapVecData[6], Queue16_UInt8_12.io.deq.bits connect remapVecValids[6], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_4542 = eq(UInt<4>(0hd), remapindex_6) when _T_4542 : connect remapVecData[6], Queue16_UInt8_13.io.deq.bits connect remapVecValids[6], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_4543 = eq(UInt<4>(0he), remapindex_6) when _T_4543 : connect remapVecData[6], Queue16_UInt8_14.io.deq.bits connect remapVecValids[6], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_4544 = eq(UInt<4>(0hf), remapindex_6) when _T_4544 : connect remapVecData[6], Queue16_UInt8_15.io.deq.bits connect remapVecValids[6], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_4545 = eq(UInt<5>(0h10), remapindex_6) when _T_4545 : connect remapVecData[6], Queue16_UInt8_16.io.deq.bits connect remapVecValids[6], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_4546 = eq(UInt<5>(0h11), remapindex_6) when _T_4546 : connect remapVecData[6], Queue16_UInt8_17.io.deq.bits connect remapVecValids[6], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_4547 = eq(UInt<5>(0h12), remapindex_6) when _T_4547 : connect remapVecData[6], Queue16_UInt8_18.io.deq.bits connect remapVecValids[6], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_4548 = eq(UInt<5>(0h13), remapindex_6) when _T_4548 : connect remapVecData[6], Queue16_UInt8_19.io.deq.bits connect remapVecValids[6], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_4549 = eq(UInt<5>(0h14), remapindex_6) when _T_4549 : connect remapVecData[6], Queue16_UInt8_20.io.deq.bits connect remapVecValids[6], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_4550 = eq(UInt<5>(0h15), remapindex_6) when _T_4550 : connect remapVecData[6], Queue16_UInt8_21.io.deq.bits connect remapVecValids[6], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_4551 = eq(UInt<5>(0h16), remapindex_6) when _T_4551 : connect remapVecData[6], Queue16_UInt8_22.io.deq.bits connect remapVecValids[6], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_4552 = eq(UInt<5>(0h17), remapindex_6) when _T_4552 : connect remapVecData[6], Queue16_UInt8_23.io.deq.bits connect remapVecValids[6], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_4553 = eq(UInt<5>(0h18), remapindex_6) when _T_4553 : connect remapVecData[6], Queue16_UInt8_24.io.deq.bits connect remapVecValids[6], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_4554 = eq(UInt<5>(0h19), remapindex_6) when _T_4554 : connect remapVecData[6], Queue16_UInt8_25.io.deq.bits connect remapVecValids[6], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_4555 = eq(UInt<5>(0h1a), remapindex_6) when _T_4555 : connect remapVecData[6], Queue16_UInt8_26.io.deq.bits connect remapVecValids[6], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_4556 = eq(UInt<5>(0h1b), remapindex_6) when _T_4556 : connect remapVecData[6], Queue16_UInt8_27.io.deq.bits connect remapVecValids[6], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_4557 = eq(UInt<5>(0h1c), remapindex_6) when _T_4557 : connect remapVecData[6], Queue16_UInt8_28.io.deq.bits connect remapVecValids[6], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_4558 = eq(UInt<5>(0h1d), remapindex_6) when _T_4558 : connect remapVecData[6], Queue16_UInt8_29.io.deq.bits connect remapVecValids[6], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_4559 = eq(UInt<5>(0h1e), remapindex_6) when _T_4559 : connect remapVecData[6], Queue16_UInt8_30.io.deq.bits connect remapVecValids[6], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_4560 = eq(UInt<5>(0h1f), remapindex_6) when _T_4560 : connect remapVecData[6], Queue16_UInt8_31.io.deq.bits connect remapVecValids[6], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_4561 = eq(UInt<1>(0h0), remapindex_7) when _T_4561 : connect remapVecData[7], Queue16_UInt8.io.deq.bits connect remapVecValids[7], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[7] node _T_4562 = eq(UInt<1>(0h1), remapindex_7) when _T_4562 : connect remapVecData[7], Queue16_UInt8_1.io.deq.bits connect remapVecValids[7], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_4563 = eq(UInt<2>(0h2), remapindex_7) when _T_4563 : connect remapVecData[7], Queue16_UInt8_2.io.deq.bits connect remapVecValids[7], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_4564 = eq(UInt<2>(0h3), remapindex_7) when _T_4564 : connect remapVecData[7], Queue16_UInt8_3.io.deq.bits connect remapVecValids[7], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_4565 = eq(UInt<3>(0h4), remapindex_7) when _T_4565 : connect remapVecData[7], Queue16_UInt8_4.io.deq.bits connect remapVecValids[7], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_4566 = eq(UInt<3>(0h5), remapindex_7) when _T_4566 : connect remapVecData[7], Queue16_UInt8_5.io.deq.bits connect remapVecValids[7], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_4567 = eq(UInt<3>(0h6), remapindex_7) when _T_4567 : connect remapVecData[7], Queue16_UInt8_6.io.deq.bits connect remapVecValids[7], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_4568 = eq(UInt<3>(0h7), remapindex_7) when _T_4568 : connect remapVecData[7], Queue16_UInt8_7.io.deq.bits connect remapVecValids[7], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_4569 = eq(UInt<4>(0h8), remapindex_7) when _T_4569 : connect remapVecData[7], Queue16_UInt8_8.io.deq.bits connect remapVecValids[7], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_4570 = eq(UInt<4>(0h9), remapindex_7) when _T_4570 : connect remapVecData[7], Queue16_UInt8_9.io.deq.bits connect remapVecValids[7], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_4571 = eq(UInt<4>(0ha), remapindex_7) when _T_4571 : connect remapVecData[7], Queue16_UInt8_10.io.deq.bits connect remapVecValids[7], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_4572 = eq(UInt<4>(0hb), remapindex_7) when _T_4572 : connect remapVecData[7], Queue16_UInt8_11.io.deq.bits connect remapVecValids[7], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_4573 = eq(UInt<4>(0hc), remapindex_7) when _T_4573 : connect remapVecData[7], Queue16_UInt8_12.io.deq.bits connect remapVecValids[7], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_4574 = eq(UInt<4>(0hd), remapindex_7) when _T_4574 : connect remapVecData[7], Queue16_UInt8_13.io.deq.bits connect remapVecValids[7], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_4575 = eq(UInt<4>(0he), remapindex_7) when _T_4575 : connect remapVecData[7], Queue16_UInt8_14.io.deq.bits connect remapVecValids[7], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_4576 = eq(UInt<4>(0hf), remapindex_7) when _T_4576 : connect remapVecData[7], Queue16_UInt8_15.io.deq.bits connect remapVecValids[7], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_4577 = eq(UInt<5>(0h10), remapindex_7) when _T_4577 : connect remapVecData[7], Queue16_UInt8_16.io.deq.bits connect remapVecValids[7], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_4578 = eq(UInt<5>(0h11), remapindex_7) when _T_4578 : connect remapVecData[7], Queue16_UInt8_17.io.deq.bits connect remapVecValids[7], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_4579 = eq(UInt<5>(0h12), remapindex_7) when _T_4579 : connect remapVecData[7], Queue16_UInt8_18.io.deq.bits connect remapVecValids[7], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_4580 = eq(UInt<5>(0h13), remapindex_7) when _T_4580 : connect remapVecData[7], Queue16_UInt8_19.io.deq.bits connect remapVecValids[7], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_4581 = eq(UInt<5>(0h14), remapindex_7) when _T_4581 : connect remapVecData[7], Queue16_UInt8_20.io.deq.bits connect remapVecValids[7], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_4582 = eq(UInt<5>(0h15), remapindex_7) when _T_4582 : connect remapVecData[7], Queue16_UInt8_21.io.deq.bits connect remapVecValids[7], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_4583 = eq(UInt<5>(0h16), remapindex_7) when _T_4583 : connect remapVecData[7], Queue16_UInt8_22.io.deq.bits connect remapVecValids[7], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_4584 = eq(UInt<5>(0h17), remapindex_7) when _T_4584 : connect remapVecData[7], Queue16_UInt8_23.io.deq.bits connect remapVecValids[7], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_4585 = eq(UInt<5>(0h18), remapindex_7) when _T_4585 : connect remapVecData[7], Queue16_UInt8_24.io.deq.bits connect remapVecValids[7], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_4586 = eq(UInt<5>(0h19), remapindex_7) when _T_4586 : connect remapVecData[7], Queue16_UInt8_25.io.deq.bits connect remapVecValids[7], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_4587 = eq(UInt<5>(0h1a), remapindex_7) when _T_4587 : connect remapVecData[7], Queue16_UInt8_26.io.deq.bits connect remapVecValids[7], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_4588 = eq(UInt<5>(0h1b), remapindex_7) when _T_4588 : connect remapVecData[7], Queue16_UInt8_27.io.deq.bits connect remapVecValids[7], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_4589 = eq(UInt<5>(0h1c), remapindex_7) when _T_4589 : connect remapVecData[7], Queue16_UInt8_28.io.deq.bits connect remapVecValids[7], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_4590 = eq(UInt<5>(0h1d), remapindex_7) when _T_4590 : connect remapVecData[7], Queue16_UInt8_29.io.deq.bits connect remapVecValids[7], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_4591 = eq(UInt<5>(0h1e), remapindex_7) when _T_4591 : connect remapVecData[7], Queue16_UInt8_30.io.deq.bits connect remapVecValids[7], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_4592 = eq(UInt<5>(0h1f), remapindex_7) when _T_4592 : connect remapVecData[7], Queue16_UInt8_31.io.deq.bits connect remapVecValids[7], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_4593 = eq(UInt<1>(0h0), remapindex_8) when _T_4593 : connect remapVecData[8], Queue16_UInt8.io.deq.bits connect remapVecValids[8], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[8] node _T_4594 = eq(UInt<1>(0h1), remapindex_8) when _T_4594 : connect remapVecData[8], Queue16_UInt8_1.io.deq.bits connect remapVecValids[8], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_4595 = eq(UInt<2>(0h2), remapindex_8) when _T_4595 : connect remapVecData[8], Queue16_UInt8_2.io.deq.bits connect remapVecValids[8], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_4596 = eq(UInt<2>(0h3), remapindex_8) when _T_4596 : connect remapVecData[8], Queue16_UInt8_3.io.deq.bits connect remapVecValids[8], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_4597 = eq(UInt<3>(0h4), remapindex_8) when _T_4597 : connect remapVecData[8], Queue16_UInt8_4.io.deq.bits connect remapVecValids[8], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_4598 = eq(UInt<3>(0h5), remapindex_8) when _T_4598 : connect remapVecData[8], Queue16_UInt8_5.io.deq.bits connect remapVecValids[8], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_4599 = eq(UInt<3>(0h6), remapindex_8) when _T_4599 : connect remapVecData[8], Queue16_UInt8_6.io.deq.bits connect remapVecValids[8], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_4600 = eq(UInt<3>(0h7), remapindex_8) when _T_4600 : connect remapVecData[8], Queue16_UInt8_7.io.deq.bits connect remapVecValids[8], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_4601 = eq(UInt<4>(0h8), remapindex_8) when _T_4601 : connect remapVecData[8], Queue16_UInt8_8.io.deq.bits connect remapVecValids[8], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_4602 = eq(UInt<4>(0h9), remapindex_8) when _T_4602 : connect remapVecData[8], Queue16_UInt8_9.io.deq.bits connect remapVecValids[8], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_4603 = eq(UInt<4>(0ha), remapindex_8) when _T_4603 : connect remapVecData[8], Queue16_UInt8_10.io.deq.bits connect remapVecValids[8], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_4604 = eq(UInt<4>(0hb), remapindex_8) when _T_4604 : connect remapVecData[8], Queue16_UInt8_11.io.deq.bits connect remapVecValids[8], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_4605 = eq(UInt<4>(0hc), remapindex_8) when _T_4605 : connect remapVecData[8], Queue16_UInt8_12.io.deq.bits connect remapVecValids[8], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_4606 = eq(UInt<4>(0hd), remapindex_8) when _T_4606 : connect remapVecData[8], Queue16_UInt8_13.io.deq.bits connect remapVecValids[8], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_4607 = eq(UInt<4>(0he), remapindex_8) when _T_4607 : connect remapVecData[8], Queue16_UInt8_14.io.deq.bits connect remapVecValids[8], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_4608 = eq(UInt<4>(0hf), remapindex_8) when _T_4608 : connect remapVecData[8], Queue16_UInt8_15.io.deq.bits connect remapVecValids[8], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_4609 = eq(UInt<5>(0h10), remapindex_8) when _T_4609 : connect remapVecData[8], Queue16_UInt8_16.io.deq.bits connect remapVecValids[8], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_4610 = eq(UInt<5>(0h11), remapindex_8) when _T_4610 : connect remapVecData[8], Queue16_UInt8_17.io.deq.bits connect remapVecValids[8], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_4611 = eq(UInt<5>(0h12), remapindex_8) when _T_4611 : connect remapVecData[8], Queue16_UInt8_18.io.deq.bits connect remapVecValids[8], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_4612 = eq(UInt<5>(0h13), remapindex_8) when _T_4612 : connect remapVecData[8], Queue16_UInt8_19.io.deq.bits connect remapVecValids[8], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_4613 = eq(UInt<5>(0h14), remapindex_8) when _T_4613 : connect remapVecData[8], Queue16_UInt8_20.io.deq.bits connect remapVecValids[8], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_4614 = eq(UInt<5>(0h15), remapindex_8) when _T_4614 : connect remapVecData[8], Queue16_UInt8_21.io.deq.bits connect remapVecValids[8], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_4615 = eq(UInt<5>(0h16), remapindex_8) when _T_4615 : connect remapVecData[8], Queue16_UInt8_22.io.deq.bits connect remapVecValids[8], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_4616 = eq(UInt<5>(0h17), remapindex_8) when _T_4616 : connect remapVecData[8], Queue16_UInt8_23.io.deq.bits connect remapVecValids[8], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_4617 = eq(UInt<5>(0h18), remapindex_8) when _T_4617 : connect remapVecData[8], Queue16_UInt8_24.io.deq.bits connect remapVecValids[8], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_4618 = eq(UInt<5>(0h19), remapindex_8) when _T_4618 : connect remapVecData[8], Queue16_UInt8_25.io.deq.bits connect remapVecValids[8], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_4619 = eq(UInt<5>(0h1a), remapindex_8) when _T_4619 : connect remapVecData[8], Queue16_UInt8_26.io.deq.bits connect remapVecValids[8], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_4620 = eq(UInt<5>(0h1b), remapindex_8) when _T_4620 : connect remapVecData[8], Queue16_UInt8_27.io.deq.bits connect remapVecValids[8], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_4621 = eq(UInt<5>(0h1c), remapindex_8) when _T_4621 : connect remapVecData[8], Queue16_UInt8_28.io.deq.bits connect remapVecValids[8], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_4622 = eq(UInt<5>(0h1d), remapindex_8) when _T_4622 : connect remapVecData[8], Queue16_UInt8_29.io.deq.bits connect remapVecValids[8], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_4623 = eq(UInt<5>(0h1e), remapindex_8) when _T_4623 : connect remapVecData[8], Queue16_UInt8_30.io.deq.bits connect remapVecValids[8], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_4624 = eq(UInt<5>(0h1f), remapindex_8) when _T_4624 : connect remapVecData[8], Queue16_UInt8_31.io.deq.bits connect remapVecValids[8], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_4625 = eq(UInt<1>(0h0), remapindex_9) when _T_4625 : connect remapVecData[9], Queue16_UInt8.io.deq.bits connect remapVecValids[9], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[9] node _T_4626 = eq(UInt<1>(0h1), remapindex_9) when _T_4626 : connect remapVecData[9], Queue16_UInt8_1.io.deq.bits connect remapVecValids[9], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_4627 = eq(UInt<2>(0h2), remapindex_9) when _T_4627 : connect remapVecData[9], Queue16_UInt8_2.io.deq.bits connect remapVecValids[9], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_4628 = eq(UInt<2>(0h3), remapindex_9) when _T_4628 : connect remapVecData[9], Queue16_UInt8_3.io.deq.bits connect remapVecValids[9], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_4629 = eq(UInt<3>(0h4), remapindex_9) when _T_4629 : connect remapVecData[9], Queue16_UInt8_4.io.deq.bits connect remapVecValids[9], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_4630 = eq(UInt<3>(0h5), remapindex_9) when _T_4630 : connect remapVecData[9], Queue16_UInt8_5.io.deq.bits connect remapVecValids[9], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_4631 = eq(UInt<3>(0h6), remapindex_9) when _T_4631 : connect remapVecData[9], Queue16_UInt8_6.io.deq.bits connect remapVecValids[9], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_4632 = eq(UInt<3>(0h7), remapindex_9) when _T_4632 : connect remapVecData[9], Queue16_UInt8_7.io.deq.bits connect remapVecValids[9], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_4633 = eq(UInt<4>(0h8), remapindex_9) when _T_4633 : connect remapVecData[9], Queue16_UInt8_8.io.deq.bits connect remapVecValids[9], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_4634 = eq(UInt<4>(0h9), remapindex_9) when _T_4634 : connect remapVecData[9], Queue16_UInt8_9.io.deq.bits connect remapVecValids[9], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_4635 = eq(UInt<4>(0ha), remapindex_9) when _T_4635 : connect remapVecData[9], Queue16_UInt8_10.io.deq.bits connect remapVecValids[9], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_4636 = eq(UInt<4>(0hb), remapindex_9) when _T_4636 : connect remapVecData[9], Queue16_UInt8_11.io.deq.bits connect remapVecValids[9], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_4637 = eq(UInt<4>(0hc), remapindex_9) when _T_4637 : connect remapVecData[9], Queue16_UInt8_12.io.deq.bits connect remapVecValids[9], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_4638 = eq(UInt<4>(0hd), remapindex_9) when _T_4638 : connect remapVecData[9], Queue16_UInt8_13.io.deq.bits connect remapVecValids[9], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_4639 = eq(UInt<4>(0he), remapindex_9) when _T_4639 : connect remapVecData[9], Queue16_UInt8_14.io.deq.bits connect remapVecValids[9], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_4640 = eq(UInt<4>(0hf), remapindex_9) when _T_4640 : connect remapVecData[9], Queue16_UInt8_15.io.deq.bits connect remapVecValids[9], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_4641 = eq(UInt<5>(0h10), remapindex_9) when _T_4641 : connect remapVecData[9], Queue16_UInt8_16.io.deq.bits connect remapVecValids[9], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_4642 = eq(UInt<5>(0h11), remapindex_9) when _T_4642 : connect remapVecData[9], Queue16_UInt8_17.io.deq.bits connect remapVecValids[9], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_4643 = eq(UInt<5>(0h12), remapindex_9) when _T_4643 : connect remapVecData[9], Queue16_UInt8_18.io.deq.bits connect remapVecValids[9], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_4644 = eq(UInt<5>(0h13), remapindex_9) when _T_4644 : connect remapVecData[9], Queue16_UInt8_19.io.deq.bits connect remapVecValids[9], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_4645 = eq(UInt<5>(0h14), remapindex_9) when _T_4645 : connect remapVecData[9], Queue16_UInt8_20.io.deq.bits connect remapVecValids[9], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_4646 = eq(UInt<5>(0h15), remapindex_9) when _T_4646 : connect remapVecData[9], Queue16_UInt8_21.io.deq.bits connect remapVecValids[9], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_4647 = eq(UInt<5>(0h16), remapindex_9) when _T_4647 : connect remapVecData[9], Queue16_UInt8_22.io.deq.bits connect remapVecValids[9], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_4648 = eq(UInt<5>(0h17), remapindex_9) when _T_4648 : connect remapVecData[9], Queue16_UInt8_23.io.deq.bits connect remapVecValids[9], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_4649 = eq(UInt<5>(0h18), remapindex_9) when _T_4649 : connect remapVecData[9], Queue16_UInt8_24.io.deq.bits connect remapVecValids[9], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_4650 = eq(UInt<5>(0h19), remapindex_9) when _T_4650 : connect remapVecData[9], Queue16_UInt8_25.io.deq.bits connect remapVecValids[9], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_4651 = eq(UInt<5>(0h1a), remapindex_9) when _T_4651 : connect remapVecData[9], Queue16_UInt8_26.io.deq.bits connect remapVecValids[9], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_4652 = eq(UInt<5>(0h1b), remapindex_9) when _T_4652 : connect remapVecData[9], Queue16_UInt8_27.io.deq.bits connect remapVecValids[9], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_4653 = eq(UInt<5>(0h1c), remapindex_9) when _T_4653 : connect remapVecData[9], Queue16_UInt8_28.io.deq.bits connect remapVecValids[9], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_4654 = eq(UInt<5>(0h1d), remapindex_9) when _T_4654 : connect remapVecData[9], Queue16_UInt8_29.io.deq.bits connect remapVecValids[9], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_4655 = eq(UInt<5>(0h1e), remapindex_9) when _T_4655 : connect remapVecData[9], Queue16_UInt8_30.io.deq.bits connect remapVecValids[9], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_4656 = eq(UInt<5>(0h1f), remapindex_9) when _T_4656 : connect remapVecData[9], Queue16_UInt8_31.io.deq.bits connect remapVecValids[9], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_4657 = eq(UInt<1>(0h0), remapindex_10) when _T_4657 : connect remapVecData[10], Queue16_UInt8.io.deq.bits connect remapVecValids[10], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[10] node _T_4658 = eq(UInt<1>(0h1), remapindex_10) when _T_4658 : connect remapVecData[10], Queue16_UInt8_1.io.deq.bits connect remapVecValids[10], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_4659 = eq(UInt<2>(0h2), remapindex_10) when _T_4659 : connect remapVecData[10], Queue16_UInt8_2.io.deq.bits connect remapVecValids[10], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_4660 = eq(UInt<2>(0h3), remapindex_10) when _T_4660 : connect remapVecData[10], Queue16_UInt8_3.io.deq.bits connect remapVecValids[10], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_4661 = eq(UInt<3>(0h4), remapindex_10) when _T_4661 : connect remapVecData[10], Queue16_UInt8_4.io.deq.bits connect remapVecValids[10], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_4662 = eq(UInt<3>(0h5), remapindex_10) when _T_4662 : connect remapVecData[10], Queue16_UInt8_5.io.deq.bits connect remapVecValids[10], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_4663 = eq(UInt<3>(0h6), remapindex_10) when _T_4663 : connect remapVecData[10], Queue16_UInt8_6.io.deq.bits connect remapVecValids[10], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_4664 = eq(UInt<3>(0h7), remapindex_10) when _T_4664 : connect remapVecData[10], Queue16_UInt8_7.io.deq.bits connect remapVecValids[10], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_4665 = eq(UInt<4>(0h8), remapindex_10) when _T_4665 : connect remapVecData[10], Queue16_UInt8_8.io.deq.bits connect remapVecValids[10], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_4666 = eq(UInt<4>(0h9), remapindex_10) when _T_4666 : connect remapVecData[10], Queue16_UInt8_9.io.deq.bits connect remapVecValids[10], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_4667 = eq(UInt<4>(0ha), remapindex_10) when _T_4667 : connect remapVecData[10], Queue16_UInt8_10.io.deq.bits connect remapVecValids[10], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_4668 = eq(UInt<4>(0hb), remapindex_10) when _T_4668 : connect remapVecData[10], Queue16_UInt8_11.io.deq.bits connect remapVecValids[10], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_4669 = eq(UInt<4>(0hc), remapindex_10) when _T_4669 : connect remapVecData[10], Queue16_UInt8_12.io.deq.bits connect remapVecValids[10], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_4670 = eq(UInt<4>(0hd), remapindex_10) when _T_4670 : connect remapVecData[10], Queue16_UInt8_13.io.deq.bits connect remapVecValids[10], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_4671 = eq(UInt<4>(0he), remapindex_10) when _T_4671 : connect remapVecData[10], Queue16_UInt8_14.io.deq.bits connect remapVecValids[10], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_4672 = eq(UInt<4>(0hf), remapindex_10) when _T_4672 : connect remapVecData[10], Queue16_UInt8_15.io.deq.bits connect remapVecValids[10], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_4673 = eq(UInt<5>(0h10), remapindex_10) when _T_4673 : connect remapVecData[10], Queue16_UInt8_16.io.deq.bits connect remapVecValids[10], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_4674 = eq(UInt<5>(0h11), remapindex_10) when _T_4674 : connect remapVecData[10], Queue16_UInt8_17.io.deq.bits connect remapVecValids[10], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_4675 = eq(UInt<5>(0h12), remapindex_10) when _T_4675 : connect remapVecData[10], Queue16_UInt8_18.io.deq.bits connect remapVecValids[10], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_4676 = eq(UInt<5>(0h13), remapindex_10) when _T_4676 : connect remapVecData[10], Queue16_UInt8_19.io.deq.bits connect remapVecValids[10], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_4677 = eq(UInt<5>(0h14), remapindex_10) when _T_4677 : connect remapVecData[10], Queue16_UInt8_20.io.deq.bits connect remapVecValids[10], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_4678 = eq(UInt<5>(0h15), remapindex_10) when _T_4678 : connect remapVecData[10], Queue16_UInt8_21.io.deq.bits connect remapVecValids[10], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_4679 = eq(UInt<5>(0h16), remapindex_10) when _T_4679 : connect remapVecData[10], Queue16_UInt8_22.io.deq.bits connect remapVecValids[10], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_4680 = eq(UInt<5>(0h17), remapindex_10) when _T_4680 : connect remapVecData[10], Queue16_UInt8_23.io.deq.bits connect remapVecValids[10], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_4681 = eq(UInt<5>(0h18), remapindex_10) when _T_4681 : connect remapVecData[10], Queue16_UInt8_24.io.deq.bits connect remapVecValids[10], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_4682 = eq(UInt<5>(0h19), remapindex_10) when _T_4682 : connect remapVecData[10], Queue16_UInt8_25.io.deq.bits connect remapVecValids[10], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_4683 = eq(UInt<5>(0h1a), remapindex_10) when _T_4683 : connect remapVecData[10], Queue16_UInt8_26.io.deq.bits connect remapVecValids[10], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_4684 = eq(UInt<5>(0h1b), remapindex_10) when _T_4684 : connect remapVecData[10], Queue16_UInt8_27.io.deq.bits connect remapVecValids[10], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_4685 = eq(UInt<5>(0h1c), remapindex_10) when _T_4685 : connect remapVecData[10], Queue16_UInt8_28.io.deq.bits connect remapVecValids[10], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_4686 = eq(UInt<5>(0h1d), remapindex_10) when _T_4686 : connect remapVecData[10], Queue16_UInt8_29.io.deq.bits connect remapVecValids[10], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_4687 = eq(UInt<5>(0h1e), remapindex_10) when _T_4687 : connect remapVecData[10], Queue16_UInt8_30.io.deq.bits connect remapVecValids[10], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_4688 = eq(UInt<5>(0h1f), remapindex_10) when _T_4688 : connect remapVecData[10], Queue16_UInt8_31.io.deq.bits connect remapVecValids[10], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_4689 = eq(UInt<1>(0h0), remapindex_11) when _T_4689 : connect remapVecData[11], Queue16_UInt8.io.deq.bits connect remapVecValids[11], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[11] node _T_4690 = eq(UInt<1>(0h1), remapindex_11) when _T_4690 : connect remapVecData[11], Queue16_UInt8_1.io.deq.bits connect remapVecValids[11], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_4691 = eq(UInt<2>(0h2), remapindex_11) when _T_4691 : connect remapVecData[11], Queue16_UInt8_2.io.deq.bits connect remapVecValids[11], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_4692 = eq(UInt<2>(0h3), remapindex_11) when _T_4692 : connect remapVecData[11], Queue16_UInt8_3.io.deq.bits connect remapVecValids[11], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_4693 = eq(UInt<3>(0h4), remapindex_11) when _T_4693 : connect remapVecData[11], Queue16_UInt8_4.io.deq.bits connect remapVecValids[11], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_4694 = eq(UInt<3>(0h5), remapindex_11) when _T_4694 : connect remapVecData[11], Queue16_UInt8_5.io.deq.bits connect remapVecValids[11], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_4695 = eq(UInt<3>(0h6), remapindex_11) when _T_4695 : connect remapVecData[11], Queue16_UInt8_6.io.deq.bits connect remapVecValids[11], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_4696 = eq(UInt<3>(0h7), remapindex_11) when _T_4696 : connect remapVecData[11], Queue16_UInt8_7.io.deq.bits connect remapVecValids[11], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_4697 = eq(UInt<4>(0h8), remapindex_11) when _T_4697 : connect remapVecData[11], Queue16_UInt8_8.io.deq.bits connect remapVecValids[11], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_4698 = eq(UInt<4>(0h9), remapindex_11) when _T_4698 : connect remapVecData[11], Queue16_UInt8_9.io.deq.bits connect remapVecValids[11], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_4699 = eq(UInt<4>(0ha), remapindex_11) when _T_4699 : connect remapVecData[11], Queue16_UInt8_10.io.deq.bits connect remapVecValids[11], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_4700 = eq(UInt<4>(0hb), remapindex_11) when _T_4700 : connect remapVecData[11], Queue16_UInt8_11.io.deq.bits connect remapVecValids[11], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_4701 = eq(UInt<4>(0hc), remapindex_11) when _T_4701 : connect remapVecData[11], Queue16_UInt8_12.io.deq.bits connect remapVecValids[11], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_4702 = eq(UInt<4>(0hd), remapindex_11) when _T_4702 : connect remapVecData[11], Queue16_UInt8_13.io.deq.bits connect remapVecValids[11], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_4703 = eq(UInt<4>(0he), remapindex_11) when _T_4703 : connect remapVecData[11], Queue16_UInt8_14.io.deq.bits connect remapVecValids[11], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_4704 = eq(UInt<4>(0hf), remapindex_11) when _T_4704 : connect remapVecData[11], Queue16_UInt8_15.io.deq.bits connect remapVecValids[11], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_4705 = eq(UInt<5>(0h10), remapindex_11) when _T_4705 : connect remapVecData[11], Queue16_UInt8_16.io.deq.bits connect remapVecValids[11], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_4706 = eq(UInt<5>(0h11), remapindex_11) when _T_4706 : connect remapVecData[11], Queue16_UInt8_17.io.deq.bits connect remapVecValids[11], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_4707 = eq(UInt<5>(0h12), remapindex_11) when _T_4707 : connect remapVecData[11], Queue16_UInt8_18.io.deq.bits connect remapVecValids[11], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_4708 = eq(UInt<5>(0h13), remapindex_11) when _T_4708 : connect remapVecData[11], Queue16_UInt8_19.io.deq.bits connect remapVecValids[11], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_4709 = eq(UInt<5>(0h14), remapindex_11) when _T_4709 : connect remapVecData[11], Queue16_UInt8_20.io.deq.bits connect remapVecValids[11], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_4710 = eq(UInt<5>(0h15), remapindex_11) when _T_4710 : connect remapVecData[11], Queue16_UInt8_21.io.deq.bits connect remapVecValids[11], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_4711 = eq(UInt<5>(0h16), remapindex_11) when _T_4711 : connect remapVecData[11], Queue16_UInt8_22.io.deq.bits connect remapVecValids[11], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_4712 = eq(UInt<5>(0h17), remapindex_11) when _T_4712 : connect remapVecData[11], Queue16_UInt8_23.io.deq.bits connect remapVecValids[11], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_4713 = eq(UInt<5>(0h18), remapindex_11) when _T_4713 : connect remapVecData[11], Queue16_UInt8_24.io.deq.bits connect remapVecValids[11], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_4714 = eq(UInt<5>(0h19), remapindex_11) when _T_4714 : connect remapVecData[11], Queue16_UInt8_25.io.deq.bits connect remapVecValids[11], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_4715 = eq(UInt<5>(0h1a), remapindex_11) when _T_4715 : connect remapVecData[11], Queue16_UInt8_26.io.deq.bits connect remapVecValids[11], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_4716 = eq(UInt<5>(0h1b), remapindex_11) when _T_4716 : connect remapVecData[11], Queue16_UInt8_27.io.deq.bits connect remapVecValids[11], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_4717 = eq(UInt<5>(0h1c), remapindex_11) when _T_4717 : connect remapVecData[11], Queue16_UInt8_28.io.deq.bits connect remapVecValids[11], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_4718 = eq(UInt<5>(0h1d), remapindex_11) when _T_4718 : connect remapVecData[11], Queue16_UInt8_29.io.deq.bits connect remapVecValids[11], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_4719 = eq(UInt<5>(0h1e), remapindex_11) when _T_4719 : connect remapVecData[11], Queue16_UInt8_30.io.deq.bits connect remapVecValids[11], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_4720 = eq(UInt<5>(0h1f), remapindex_11) when _T_4720 : connect remapVecData[11], Queue16_UInt8_31.io.deq.bits connect remapVecValids[11], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_4721 = eq(UInt<1>(0h0), remapindex_12) when _T_4721 : connect remapVecData[12], Queue16_UInt8.io.deq.bits connect remapVecValids[12], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[12] node _T_4722 = eq(UInt<1>(0h1), remapindex_12) when _T_4722 : connect remapVecData[12], Queue16_UInt8_1.io.deq.bits connect remapVecValids[12], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_4723 = eq(UInt<2>(0h2), remapindex_12) when _T_4723 : connect remapVecData[12], Queue16_UInt8_2.io.deq.bits connect remapVecValids[12], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_4724 = eq(UInt<2>(0h3), remapindex_12) when _T_4724 : connect remapVecData[12], Queue16_UInt8_3.io.deq.bits connect remapVecValids[12], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_4725 = eq(UInt<3>(0h4), remapindex_12) when _T_4725 : connect remapVecData[12], Queue16_UInt8_4.io.deq.bits connect remapVecValids[12], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_4726 = eq(UInt<3>(0h5), remapindex_12) when _T_4726 : connect remapVecData[12], Queue16_UInt8_5.io.deq.bits connect remapVecValids[12], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_4727 = eq(UInt<3>(0h6), remapindex_12) when _T_4727 : connect remapVecData[12], Queue16_UInt8_6.io.deq.bits connect remapVecValids[12], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_4728 = eq(UInt<3>(0h7), remapindex_12) when _T_4728 : connect remapVecData[12], Queue16_UInt8_7.io.deq.bits connect remapVecValids[12], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_4729 = eq(UInt<4>(0h8), remapindex_12) when _T_4729 : connect remapVecData[12], Queue16_UInt8_8.io.deq.bits connect remapVecValids[12], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_4730 = eq(UInt<4>(0h9), remapindex_12) when _T_4730 : connect remapVecData[12], Queue16_UInt8_9.io.deq.bits connect remapVecValids[12], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_4731 = eq(UInt<4>(0ha), remapindex_12) when _T_4731 : connect remapVecData[12], Queue16_UInt8_10.io.deq.bits connect remapVecValids[12], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_4732 = eq(UInt<4>(0hb), remapindex_12) when _T_4732 : connect remapVecData[12], Queue16_UInt8_11.io.deq.bits connect remapVecValids[12], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_4733 = eq(UInt<4>(0hc), remapindex_12) when _T_4733 : connect remapVecData[12], Queue16_UInt8_12.io.deq.bits connect remapVecValids[12], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_4734 = eq(UInt<4>(0hd), remapindex_12) when _T_4734 : connect remapVecData[12], Queue16_UInt8_13.io.deq.bits connect remapVecValids[12], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_4735 = eq(UInt<4>(0he), remapindex_12) when _T_4735 : connect remapVecData[12], Queue16_UInt8_14.io.deq.bits connect remapVecValids[12], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_4736 = eq(UInt<4>(0hf), remapindex_12) when _T_4736 : connect remapVecData[12], Queue16_UInt8_15.io.deq.bits connect remapVecValids[12], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_4737 = eq(UInt<5>(0h10), remapindex_12) when _T_4737 : connect remapVecData[12], Queue16_UInt8_16.io.deq.bits connect remapVecValids[12], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_4738 = eq(UInt<5>(0h11), remapindex_12) when _T_4738 : connect remapVecData[12], Queue16_UInt8_17.io.deq.bits connect remapVecValids[12], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_4739 = eq(UInt<5>(0h12), remapindex_12) when _T_4739 : connect remapVecData[12], Queue16_UInt8_18.io.deq.bits connect remapVecValids[12], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_4740 = eq(UInt<5>(0h13), remapindex_12) when _T_4740 : connect remapVecData[12], Queue16_UInt8_19.io.deq.bits connect remapVecValids[12], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_4741 = eq(UInt<5>(0h14), remapindex_12) when _T_4741 : connect remapVecData[12], Queue16_UInt8_20.io.deq.bits connect remapVecValids[12], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_4742 = eq(UInt<5>(0h15), remapindex_12) when _T_4742 : connect remapVecData[12], Queue16_UInt8_21.io.deq.bits connect remapVecValids[12], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_4743 = eq(UInt<5>(0h16), remapindex_12) when _T_4743 : connect remapVecData[12], Queue16_UInt8_22.io.deq.bits connect remapVecValids[12], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_4744 = eq(UInt<5>(0h17), remapindex_12) when _T_4744 : connect remapVecData[12], Queue16_UInt8_23.io.deq.bits connect remapVecValids[12], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_4745 = eq(UInt<5>(0h18), remapindex_12) when _T_4745 : connect remapVecData[12], Queue16_UInt8_24.io.deq.bits connect remapVecValids[12], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_4746 = eq(UInt<5>(0h19), remapindex_12) when _T_4746 : connect remapVecData[12], Queue16_UInt8_25.io.deq.bits connect remapVecValids[12], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_4747 = eq(UInt<5>(0h1a), remapindex_12) when _T_4747 : connect remapVecData[12], Queue16_UInt8_26.io.deq.bits connect remapVecValids[12], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_4748 = eq(UInt<5>(0h1b), remapindex_12) when _T_4748 : connect remapVecData[12], Queue16_UInt8_27.io.deq.bits connect remapVecValids[12], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_4749 = eq(UInt<5>(0h1c), remapindex_12) when _T_4749 : connect remapVecData[12], Queue16_UInt8_28.io.deq.bits connect remapVecValids[12], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_4750 = eq(UInt<5>(0h1d), remapindex_12) when _T_4750 : connect remapVecData[12], Queue16_UInt8_29.io.deq.bits connect remapVecValids[12], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_4751 = eq(UInt<5>(0h1e), remapindex_12) when _T_4751 : connect remapVecData[12], Queue16_UInt8_30.io.deq.bits connect remapVecValids[12], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_4752 = eq(UInt<5>(0h1f), remapindex_12) when _T_4752 : connect remapVecData[12], Queue16_UInt8_31.io.deq.bits connect remapVecValids[12], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_4753 = eq(UInt<1>(0h0), remapindex_13) when _T_4753 : connect remapVecData[13], Queue16_UInt8.io.deq.bits connect remapVecValids[13], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[13] node _T_4754 = eq(UInt<1>(0h1), remapindex_13) when _T_4754 : connect remapVecData[13], Queue16_UInt8_1.io.deq.bits connect remapVecValids[13], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_4755 = eq(UInt<2>(0h2), remapindex_13) when _T_4755 : connect remapVecData[13], Queue16_UInt8_2.io.deq.bits connect remapVecValids[13], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_4756 = eq(UInt<2>(0h3), remapindex_13) when _T_4756 : connect remapVecData[13], Queue16_UInt8_3.io.deq.bits connect remapVecValids[13], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_4757 = eq(UInt<3>(0h4), remapindex_13) when _T_4757 : connect remapVecData[13], Queue16_UInt8_4.io.deq.bits connect remapVecValids[13], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_4758 = eq(UInt<3>(0h5), remapindex_13) when _T_4758 : connect remapVecData[13], Queue16_UInt8_5.io.deq.bits connect remapVecValids[13], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_4759 = eq(UInt<3>(0h6), remapindex_13) when _T_4759 : connect remapVecData[13], Queue16_UInt8_6.io.deq.bits connect remapVecValids[13], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_4760 = eq(UInt<3>(0h7), remapindex_13) when _T_4760 : connect remapVecData[13], Queue16_UInt8_7.io.deq.bits connect remapVecValids[13], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_4761 = eq(UInt<4>(0h8), remapindex_13) when _T_4761 : connect remapVecData[13], Queue16_UInt8_8.io.deq.bits connect remapVecValids[13], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_4762 = eq(UInt<4>(0h9), remapindex_13) when _T_4762 : connect remapVecData[13], Queue16_UInt8_9.io.deq.bits connect remapVecValids[13], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_4763 = eq(UInt<4>(0ha), remapindex_13) when _T_4763 : connect remapVecData[13], Queue16_UInt8_10.io.deq.bits connect remapVecValids[13], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_4764 = eq(UInt<4>(0hb), remapindex_13) when _T_4764 : connect remapVecData[13], Queue16_UInt8_11.io.deq.bits connect remapVecValids[13], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_4765 = eq(UInt<4>(0hc), remapindex_13) when _T_4765 : connect remapVecData[13], Queue16_UInt8_12.io.deq.bits connect remapVecValids[13], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_4766 = eq(UInt<4>(0hd), remapindex_13) when _T_4766 : connect remapVecData[13], Queue16_UInt8_13.io.deq.bits connect remapVecValids[13], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_4767 = eq(UInt<4>(0he), remapindex_13) when _T_4767 : connect remapVecData[13], Queue16_UInt8_14.io.deq.bits connect remapVecValids[13], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_4768 = eq(UInt<4>(0hf), remapindex_13) when _T_4768 : connect remapVecData[13], Queue16_UInt8_15.io.deq.bits connect remapVecValids[13], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_4769 = eq(UInt<5>(0h10), remapindex_13) when _T_4769 : connect remapVecData[13], Queue16_UInt8_16.io.deq.bits connect remapVecValids[13], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_4770 = eq(UInt<5>(0h11), remapindex_13) when _T_4770 : connect remapVecData[13], Queue16_UInt8_17.io.deq.bits connect remapVecValids[13], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_4771 = eq(UInt<5>(0h12), remapindex_13) when _T_4771 : connect remapVecData[13], Queue16_UInt8_18.io.deq.bits connect remapVecValids[13], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_4772 = eq(UInt<5>(0h13), remapindex_13) when _T_4772 : connect remapVecData[13], Queue16_UInt8_19.io.deq.bits connect remapVecValids[13], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_4773 = eq(UInt<5>(0h14), remapindex_13) when _T_4773 : connect remapVecData[13], Queue16_UInt8_20.io.deq.bits connect remapVecValids[13], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_4774 = eq(UInt<5>(0h15), remapindex_13) when _T_4774 : connect remapVecData[13], Queue16_UInt8_21.io.deq.bits connect remapVecValids[13], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_4775 = eq(UInt<5>(0h16), remapindex_13) when _T_4775 : connect remapVecData[13], Queue16_UInt8_22.io.deq.bits connect remapVecValids[13], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_4776 = eq(UInt<5>(0h17), remapindex_13) when _T_4776 : connect remapVecData[13], Queue16_UInt8_23.io.deq.bits connect remapVecValids[13], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_4777 = eq(UInt<5>(0h18), remapindex_13) when _T_4777 : connect remapVecData[13], Queue16_UInt8_24.io.deq.bits connect remapVecValids[13], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_4778 = eq(UInt<5>(0h19), remapindex_13) when _T_4778 : connect remapVecData[13], Queue16_UInt8_25.io.deq.bits connect remapVecValids[13], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_4779 = eq(UInt<5>(0h1a), remapindex_13) when _T_4779 : connect remapVecData[13], Queue16_UInt8_26.io.deq.bits connect remapVecValids[13], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_4780 = eq(UInt<5>(0h1b), remapindex_13) when _T_4780 : connect remapVecData[13], Queue16_UInt8_27.io.deq.bits connect remapVecValids[13], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_4781 = eq(UInt<5>(0h1c), remapindex_13) when _T_4781 : connect remapVecData[13], Queue16_UInt8_28.io.deq.bits connect remapVecValids[13], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_4782 = eq(UInt<5>(0h1d), remapindex_13) when _T_4782 : connect remapVecData[13], Queue16_UInt8_29.io.deq.bits connect remapVecValids[13], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_4783 = eq(UInt<5>(0h1e), remapindex_13) when _T_4783 : connect remapVecData[13], Queue16_UInt8_30.io.deq.bits connect remapVecValids[13], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_4784 = eq(UInt<5>(0h1f), remapindex_13) when _T_4784 : connect remapVecData[13], Queue16_UInt8_31.io.deq.bits connect remapVecValids[13], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_4785 = eq(UInt<1>(0h0), remapindex_14) when _T_4785 : connect remapVecData[14], Queue16_UInt8.io.deq.bits connect remapVecValids[14], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[14] node _T_4786 = eq(UInt<1>(0h1), remapindex_14) when _T_4786 : connect remapVecData[14], Queue16_UInt8_1.io.deq.bits connect remapVecValids[14], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_4787 = eq(UInt<2>(0h2), remapindex_14) when _T_4787 : connect remapVecData[14], Queue16_UInt8_2.io.deq.bits connect remapVecValids[14], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_4788 = eq(UInt<2>(0h3), remapindex_14) when _T_4788 : connect remapVecData[14], Queue16_UInt8_3.io.deq.bits connect remapVecValids[14], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_4789 = eq(UInt<3>(0h4), remapindex_14) when _T_4789 : connect remapVecData[14], Queue16_UInt8_4.io.deq.bits connect remapVecValids[14], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_4790 = eq(UInt<3>(0h5), remapindex_14) when _T_4790 : connect remapVecData[14], Queue16_UInt8_5.io.deq.bits connect remapVecValids[14], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_4791 = eq(UInt<3>(0h6), remapindex_14) when _T_4791 : connect remapVecData[14], Queue16_UInt8_6.io.deq.bits connect remapVecValids[14], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_4792 = eq(UInt<3>(0h7), remapindex_14) when _T_4792 : connect remapVecData[14], Queue16_UInt8_7.io.deq.bits connect remapVecValids[14], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_4793 = eq(UInt<4>(0h8), remapindex_14) when _T_4793 : connect remapVecData[14], Queue16_UInt8_8.io.deq.bits connect remapVecValids[14], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_4794 = eq(UInt<4>(0h9), remapindex_14) when _T_4794 : connect remapVecData[14], Queue16_UInt8_9.io.deq.bits connect remapVecValids[14], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_4795 = eq(UInt<4>(0ha), remapindex_14) when _T_4795 : connect remapVecData[14], Queue16_UInt8_10.io.deq.bits connect remapVecValids[14], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_4796 = eq(UInt<4>(0hb), remapindex_14) when _T_4796 : connect remapVecData[14], Queue16_UInt8_11.io.deq.bits connect remapVecValids[14], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_4797 = eq(UInt<4>(0hc), remapindex_14) when _T_4797 : connect remapVecData[14], Queue16_UInt8_12.io.deq.bits connect remapVecValids[14], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_4798 = eq(UInt<4>(0hd), remapindex_14) when _T_4798 : connect remapVecData[14], Queue16_UInt8_13.io.deq.bits connect remapVecValids[14], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_4799 = eq(UInt<4>(0he), remapindex_14) when _T_4799 : connect remapVecData[14], Queue16_UInt8_14.io.deq.bits connect remapVecValids[14], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_4800 = eq(UInt<4>(0hf), remapindex_14) when _T_4800 : connect remapVecData[14], Queue16_UInt8_15.io.deq.bits connect remapVecValids[14], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_4801 = eq(UInt<5>(0h10), remapindex_14) when _T_4801 : connect remapVecData[14], Queue16_UInt8_16.io.deq.bits connect remapVecValids[14], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_4802 = eq(UInt<5>(0h11), remapindex_14) when _T_4802 : connect remapVecData[14], Queue16_UInt8_17.io.deq.bits connect remapVecValids[14], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_4803 = eq(UInt<5>(0h12), remapindex_14) when _T_4803 : connect remapVecData[14], Queue16_UInt8_18.io.deq.bits connect remapVecValids[14], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_4804 = eq(UInt<5>(0h13), remapindex_14) when _T_4804 : connect remapVecData[14], Queue16_UInt8_19.io.deq.bits connect remapVecValids[14], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_4805 = eq(UInt<5>(0h14), remapindex_14) when _T_4805 : connect remapVecData[14], Queue16_UInt8_20.io.deq.bits connect remapVecValids[14], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_4806 = eq(UInt<5>(0h15), remapindex_14) when _T_4806 : connect remapVecData[14], Queue16_UInt8_21.io.deq.bits connect remapVecValids[14], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_4807 = eq(UInt<5>(0h16), remapindex_14) when _T_4807 : connect remapVecData[14], Queue16_UInt8_22.io.deq.bits connect remapVecValids[14], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_4808 = eq(UInt<5>(0h17), remapindex_14) when _T_4808 : connect remapVecData[14], Queue16_UInt8_23.io.deq.bits connect remapVecValids[14], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_4809 = eq(UInt<5>(0h18), remapindex_14) when _T_4809 : connect remapVecData[14], Queue16_UInt8_24.io.deq.bits connect remapVecValids[14], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_4810 = eq(UInt<5>(0h19), remapindex_14) when _T_4810 : connect remapVecData[14], Queue16_UInt8_25.io.deq.bits connect remapVecValids[14], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_4811 = eq(UInt<5>(0h1a), remapindex_14) when _T_4811 : connect remapVecData[14], Queue16_UInt8_26.io.deq.bits connect remapVecValids[14], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_4812 = eq(UInt<5>(0h1b), remapindex_14) when _T_4812 : connect remapVecData[14], Queue16_UInt8_27.io.deq.bits connect remapVecValids[14], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_4813 = eq(UInt<5>(0h1c), remapindex_14) when _T_4813 : connect remapVecData[14], Queue16_UInt8_28.io.deq.bits connect remapVecValids[14], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_4814 = eq(UInt<5>(0h1d), remapindex_14) when _T_4814 : connect remapVecData[14], Queue16_UInt8_29.io.deq.bits connect remapVecValids[14], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_4815 = eq(UInt<5>(0h1e), remapindex_14) when _T_4815 : connect remapVecData[14], Queue16_UInt8_30.io.deq.bits connect remapVecValids[14], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_4816 = eq(UInt<5>(0h1f), remapindex_14) when _T_4816 : connect remapVecData[14], Queue16_UInt8_31.io.deq.bits connect remapVecValids[14], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_4817 = eq(UInt<1>(0h0), remapindex_15) when _T_4817 : connect remapVecData[15], Queue16_UInt8.io.deq.bits connect remapVecValids[15], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[15] node _T_4818 = eq(UInt<1>(0h1), remapindex_15) when _T_4818 : connect remapVecData[15], Queue16_UInt8_1.io.deq.bits connect remapVecValids[15], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_4819 = eq(UInt<2>(0h2), remapindex_15) when _T_4819 : connect remapVecData[15], Queue16_UInt8_2.io.deq.bits connect remapVecValids[15], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_4820 = eq(UInt<2>(0h3), remapindex_15) when _T_4820 : connect remapVecData[15], Queue16_UInt8_3.io.deq.bits connect remapVecValids[15], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_4821 = eq(UInt<3>(0h4), remapindex_15) when _T_4821 : connect remapVecData[15], Queue16_UInt8_4.io.deq.bits connect remapVecValids[15], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_4822 = eq(UInt<3>(0h5), remapindex_15) when _T_4822 : connect remapVecData[15], Queue16_UInt8_5.io.deq.bits connect remapVecValids[15], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_4823 = eq(UInt<3>(0h6), remapindex_15) when _T_4823 : connect remapVecData[15], Queue16_UInt8_6.io.deq.bits connect remapVecValids[15], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_4824 = eq(UInt<3>(0h7), remapindex_15) when _T_4824 : connect remapVecData[15], Queue16_UInt8_7.io.deq.bits connect remapVecValids[15], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_4825 = eq(UInt<4>(0h8), remapindex_15) when _T_4825 : connect remapVecData[15], Queue16_UInt8_8.io.deq.bits connect remapVecValids[15], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_4826 = eq(UInt<4>(0h9), remapindex_15) when _T_4826 : connect remapVecData[15], Queue16_UInt8_9.io.deq.bits connect remapVecValids[15], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_4827 = eq(UInt<4>(0ha), remapindex_15) when _T_4827 : connect remapVecData[15], Queue16_UInt8_10.io.deq.bits connect remapVecValids[15], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_4828 = eq(UInt<4>(0hb), remapindex_15) when _T_4828 : connect remapVecData[15], Queue16_UInt8_11.io.deq.bits connect remapVecValids[15], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_4829 = eq(UInt<4>(0hc), remapindex_15) when _T_4829 : connect remapVecData[15], Queue16_UInt8_12.io.deq.bits connect remapVecValids[15], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_4830 = eq(UInt<4>(0hd), remapindex_15) when _T_4830 : connect remapVecData[15], Queue16_UInt8_13.io.deq.bits connect remapVecValids[15], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_4831 = eq(UInt<4>(0he), remapindex_15) when _T_4831 : connect remapVecData[15], Queue16_UInt8_14.io.deq.bits connect remapVecValids[15], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_4832 = eq(UInt<4>(0hf), remapindex_15) when _T_4832 : connect remapVecData[15], Queue16_UInt8_15.io.deq.bits connect remapVecValids[15], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_4833 = eq(UInt<5>(0h10), remapindex_15) when _T_4833 : connect remapVecData[15], Queue16_UInt8_16.io.deq.bits connect remapVecValids[15], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_4834 = eq(UInt<5>(0h11), remapindex_15) when _T_4834 : connect remapVecData[15], Queue16_UInt8_17.io.deq.bits connect remapVecValids[15], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_4835 = eq(UInt<5>(0h12), remapindex_15) when _T_4835 : connect remapVecData[15], Queue16_UInt8_18.io.deq.bits connect remapVecValids[15], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_4836 = eq(UInt<5>(0h13), remapindex_15) when _T_4836 : connect remapVecData[15], Queue16_UInt8_19.io.deq.bits connect remapVecValids[15], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_4837 = eq(UInt<5>(0h14), remapindex_15) when _T_4837 : connect remapVecData[15], Queue16_UInt8_20.io.deq.bits connect remapVecValids[15], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_4838 = eq(UInt<5>(0h15), remapindex_15) when _T_4838 : connect remapVecData[15], Queue16_UInt8_21.io.deq.bits connect remapVecValids[15], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_4839 = eq(UInt<5>(0h16), remapindex_15) when _T_4839 : connect remapVecData[15], Queue16_UInt8_22.io.deq.bits connect remapVecValids[15], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_4840 = eq(UInt<5>(0h17), remapindex_15) when _T_4840 : connect remapVecData[15], Queue16_UInt8_23.io.deq.bits connect remapVecValids[15], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_4841 = eq(UInt<5>(0h18), remapindex_15) when _T_4841 : connect remapVecData[15], Queue16_UInt8_24.io.deq.bits connect remapVecValids[15], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_4842 = eq(UInt<5>(0h19), remapindex_15) when _T_4842 : connect remapVecData[15], Queue16_UInt8_25.io.deq.bits connect remapVecValids[15], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_4843 = eq(UInt<5>(0h1a), remapindex_15) when _T_4843 : connect remapVecData[15], Queue16_UInt8_26.io.deq.bits connect remapVecValids[15], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_4844 = eq(UInt<5>(0h1b), remapindex_15) when _T_4844 : connect remapVecData[15], Queue16_UInt8_27.io.deq.bits connect remapVecValids[15], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_4845 = eq(UInt<5>(0h1c), remapindex_15) when _T_4845 : connect remapVecData[15], Queue16_UInt8_28.io.deq.bits connect remapVecValids[15], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_4846 = eq(UInt<5>(0h1d), remapindex_15) when _T_4846 : connect remapVecData[15], Queue16_UInt8_29.io.deq.bits connect remapVecValids[15], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_4847 = eq(UInt<5>(0h1e), remapindex_15) when _T_4847 : connect remapVecData[15], Queue16_UInt8_30.io.deq.bits connect remapVecValids[15], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_4848 = eq(UInt<5>(0h1f), remapindex_15) when _T_4848 : connect remapVecData[15], Queue16_UInt8_31.io.deq.bits connect remapVecValids[15], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_4849 = eq(UInt<1>(0h0), remapindex_16) when _T_4849 : connect remapVecData[16], Queue16_UInt8.io.deq.bits connect remapVecValids[16], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[16] node _T_4850 = eq(UInt<1>(0h1), remapindex_16) when _T_4850 : connect remapVecData[16], Queue16_UInt8_1.io.deq.bits connect remapVecValids[16], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_4851 = eq(UInt<2>(0h2), remapindex_16) when _T_4851 : connect remapVecData[16], Queue16_UInt8_2.io.deq.bits connect remapVecValids[16], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_4852 = eq(UInt<2>(0h3), remapindex_16) when _T_4852 : connect remapVecData[16], Queue16_UInt8_3.io.deq.bits connect remapVecValids[16], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_4853 = eq(UInt<3>(0h4), remapindex_16) when _T_4853 : connect remapVecData[16], Queue16_UInt8_4.io.deq.bits connect remapVecValids[16], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_4854 = eq(UInt<3>(0h5), remapindex_16) when _T_4854 : connect remapVecData[16], Queue16_UInt8_5.io.deq.bits connect remapVecValids[16], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_4855 = eq(UInt<3>(0h6), remapindex_16) when _T_4855 : connect remapVecData[16], Queue16_UInt8_6.io.deq.bits connect remapVecValids[16], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_4856 = eq(UInt<3>(0h7), remapindex_16) when _T_4856 : connect remapVecData[16], Queue16_UInt8_7.io.deq.bits connect remapVecValids[16], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_4857 = eq(UInt<4>(0h8), remapindex_16) when _T_4857 : connect remapVecData[16], Queue16_UInt8_8.io.deq.bits connect remapVecValids[16], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_4858 = eq(UInt<4>(0h9), remapindex_16) when _T_4858 : connect remapVecData[16], Queue16_UInt8_9.io.deq.bits connect remapVecValids[16], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_4859 = eq(UInt<4>(0ha), remapindex_16) when _T_4859 : connect remapVecData[16], Queue16_UInt8_10.io.deq.bits connect remapVecValids[16], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_4860 = eq(UInt<4>(0hb), remapindex_16) when _T_4860 : connect remapVecData[16], Queue16_UInt8_11.io.deq.bits connect remapVecValids[16], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_4861 = eq(UInt<4>(0hc), remapindex_16) when _T_4861 : connect remapVecData[16], Queue16_UInt8_12.io.deq.bits connect remapVecValids[16], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_4862 = eq(UInt<4>(0hd), remapindex_16) when _T_4862 : connect remapVecData[16], Queue16_UInt8_13.io.deq.bits connect remapVecValids[16], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_4863 = eq(UInt<4>(0he), remapindex_16) when _T_4863 : connect remapVecData[16], Queue16_UInt8_14.io.deq.bits connect remapVecValids[16], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_4864 = eq(UInt<4>(0hf), remapindex_16) when _T_4864 : connect remapVecData[16], Queue16_UInt8_15.io.deq.bits connect remapVecValids[16], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_4865 = eq(UInt<5>(0h10), remapindex_16) when _T_4865 : connect remapVecData[16], Queue16_UInt8_16.io.deq.bits connect remapVecValids[16], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_4866 = eq(UInt<5>(0h11), remapindex_16) when _T_4866 : connect remapVecData[16], Queue16_UInt8_17.io.deq.bits connect remapVecValids[16], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_4867 = eq(UInt<5>(0h12), remapindex_16) when _T_4867 : connect remapVecData[16], Queue16_UInt8_18.io.deq.bits connect remapVecValids[16], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_4868 = eq(UInt<5>(0h13), remapindex_16) when _T_4868 : connect remapVecData[16], Queue16_UInt8_19.io.deq.bits connect remapVecValids[16], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_4869 = eq(UInt<5>(0h14), remapindex_16) when _T_4869 : connect remapVecData[16], Queue16_UInt8_20.io.deq.bits connect remapVecValids[16], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_4870 = eq(UInt<5>(0h15), remapindex_16) when _T_4870 : connect remapVecData[16], Queue16_UInt8_21.io.deq.bits connect remapVecValids[16], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_4871 = eq(UInt<5>(0h16), remapindex_16) when _T_4871 : connect remapVecData[16], Queue16_UInt8_22.io.deq.bits connect remapVecValids[16], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_4872 = eq(UInt<5>(0h17), remapindex_16) when _T_4872 : connect remapVecData[16], Queue16_UInt8_23.io.deq.bits connect remapVecValids[16], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_4873 = eq(UInt<5>(0h18), remapindex_16) when _T_4873 : connect remapVecData[16], Queue16_UInt8_24.io.deq.bits connect remapVecValids[16], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_4874 = eq(UInt<5>(0h19), remapindex_16) when _T_4874 : connect remapVecData[16], Queue16_UInt8_25.io.deq.bits connect remapVecValids[16], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_4875 = eq(UInt<5>(0h1a), remapindex_16) when _T_4875 : connect remapVecData[16], Queue16_UInt8_26.io.deq.bits connect remapVecValids[16], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_4876 = eq(UInt<5>(0h1b), remapindex_16) when _T_4876 : connect remapVecData[16], Queue16_UInt8_27.io.deq.bits connect remapVecValids[16], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_4877 = eq(UInt<5>(0h1c), remapindex_16) when _T_4877 : connect remapVecData[16], Queue16_UInt8_28.io.deq.bits connect remapVecValids[16], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_4878 = eq(UInt<5>(0h1d), remapindex_16) when _T_4878 : connect remapVecData[16], Queue16_UInt8_29.io.deq.bits connect remapVecValids[16], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_4879 = eq(UInt<5>(0h1e), remapindex_16) when _T_4879 : connect remapVecData[16], Queue16_UInt8_30.io.deq.bits connect remapVecValids[16], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_4880 = eq(UInt<5>(0h1f), remapindex_16) when _T_4880 : connect remapVecData[16], Queue16_UInt8_31.io.deq.bits connect remapVecValids[16], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_4881 = eq(UInt<1>(0h0), remapindex_17) when _T_4881 : connect remapVecData[17], Queue16_UInt8.io.deq.bits connect remapVecValids[17], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[17] node _T_4882 = eq(UInt<1>(0h1), remapindex_17) when _T_4882 : connect remapVecData[17], Queue16_UInt8_1.io.deq.bits connect remapVecValids[17], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_4883 = eq(UInt<2>(0h2), remapindex_17) when _T_4883 : connect remapVecData[17], Queue16_UInt8_2.io.deq.bits connect remapVecValids[17], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_4884 = eq(UInt<2>(0h3), remapindex_17) when _T_4884 : connect remapVecData[17], Queue16_UInt8_3.io.deq.bits connect remapVecValids[17], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_4885 = eq(UInt<3>(0h4), remapindex_17) when _T_4885 : connect remapVecData[17], Queue16_UInt8_4.io.deq.bits connect remapVecValids[17], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_4886 = eq(UInt<3>(0h5), remapindex_17) when _T_4886 : connect remapVecData[17], Queue16_UInt8_5.io.deq.bits connect remapVecValids[17], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_4887 = eq(UInt<3>(0h6), remapindex_17) when _T_4887 : connect remapVecData[17], Queue16_UInt8_6.io.deq.bits connect remapVecValids[17], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_4888 = eq(UInt<3>(0h7), remapindex_17) when _T_4888 : connect remapVecData[17], Queue16_UInt8_7.io.deq.bits connect remapVecValids[17], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_4889 = eq(UInt<4>(0h8), remapindex_17) when _T_4889 : connect remapVecData[17], Queue16_UInt8_8.io.deq.bits connect remapVecValids[17], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_4890 = eq(UInt<4>(0h9), remapindex_17) when _T_4890 : connect remapVecData[17], Queue16_UInt8_9.io.deq.bits connect remapVecValids[17], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_4891 = eq(UInt<4>(0ha), remapindex_17) when _T_4891 : connect remapVecData[17], Queue16_UInt8_10.io.deq.bits connect remapVecValids[17], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_4892 = eq(UInt<4>(0hb), remapindex_17) when _T_4892 : connect remapVecData[17], Queue16_UInt8_11.io.deq.bits connect remapVecValids[17], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_4893 = eq(UInt<4>(0hc), remapindex_17) when _T_4893 : connect remapVecData[17], Queue16_UInt8_12.io.deq.bits connect remapVecValids[17], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_4894 = eq(UInt<4>(0hd), remapindex_17) when _T_4894 : connect remapVecData[17], Queue16_UInt8_13.io.deq.bits connect remapVecValids[17], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_4895 = eq(UInt<4>(0he), remapindex_17) when _T_4895 : connect remapVecData[17], Queue16_UInt8_14.io.deq.bits connect remapVecValids[17], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_4896 = eq(UInt<4>(0hf), remapindex_17) when _T_4896 : connect remapVecData[17], Queue16_UInt8_15.io.deq.bits connect remapVecValids[17], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_4897 = eq(UInt<5>(0h10), remapindex_17) when _T_4897 : connect remapVecData[17], Queue16_UInt8_16.io.deq.bits connect remapVecValids[17], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_4898 = eq(UInt<5>(0h11), remapindex_17) when _T_4898 : connect remapVecData[17], Queue16_UInt8_17.io.deq.bits connect remapVecValids[17], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_4899 = eq(UInt<5>(0h12), remapindex_17) when _T_4899 : connect remapVecData[17], Queue16_UInt8_18.io.deq.bits connect remapVecValids[17], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_4900 = eq(UInt<5>(0h13), remapindex_17) when _T_4900 : connect remapVecData[17], Queue16_UInt8_19.io.deq.bits connect remapVecValids[17], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_4901 = eq(UInt<5>(0h14), remapindex_17) when _T_4901 : connect remapVecData[17], Queue16_UInt8_20.io.deq.bits connect remapVecValids[17], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_4902 = eq(UInt<5>(0h15), remapindex_17) when _T_4902 : connect remapVecData[17], Queue16_UInt8_21.io.deq.bits connect remapVecValids[17], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_4903 = eq(UInt<5>(0h16), remapindex_17) when _T_4903 : connect remapVecData[17], Queue16_UInt8_22.io.deq.bits connect remapVecValids[17], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_4904 = eq(UInt<5>(0h17), remapindex_17) when _T_4904 : connect remapVecData[17], Queue16_UInt8_23.io.deq.bits connect remapVecValids[17], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_4905 = eq(UInt<5>(0h18), remapindex_17) when _T_4905 : connect remapVecData[17], Queue16_UInt8_24.io.deq.bits connect remapVecValids[17], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_4906 = eq(UInt<5>(0h19), remapindex_17) when _T_4906 : connect remapVecData[17], Queue16_UInt8_25.io.deq.bits connect remapVecValids[17], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_4907 = eq(UInt<5>(0h1a), remapindex_17) when _T_4907 : connect remapVecData[17], Queue16_UInt8_26.io.deq.bits connect remapVecValids[17], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_4908 = eq(UInt<5>(0h1b), remapindex_17) when _T_4908 : connect remapVecData[17], Queue16_UInt8_27.io.deq.bits connect remapVecValids[17], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_4909 = eq(UInt<5>(0h1c), remapindex_17) when _T_4909 : connect remapVecData[17], Queue16_UInt8_28.io.deq.bits connect remapVecValids[17], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_4910 = eq(UInt<5>(0h1d), remapindex_17) when _T_4910 : connect remapVecData[17], Queue16_UInt8_29.io.deq.bits connect remapVecValids[17], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_4911 = eq(UInt<5>(0h1e), remapindex_17) when _T_4911 : connect remapVecData[17], Queue16_UInt8_30.io.deq.bits connect remapVecValids[17], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_4912 = eq(UInt<5>(0h1f), remapindex_17) when _T_4912 : connect remapVecData[17], Queue16_UInt8_31.io.deq.bits connect remapVecValids[17], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_4913 = eq(UInt<1>(0h0), remapindex_18) when _T_4913 : connect remapVecData[18], Queue16_UInt8.io.deq.bits connect remapVecValids[18], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[18] node _T_4914 = eq(UInt<1>(0h1), remapindex_18) when _T_4914 : connect remapVecData[18], Queue16_UInt8_1.io.deq.bits connect remapVecValids[18], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_4915 = eq(UInt<2>(0h2), remapindex_18) when _T_4915 : connect remapVecData[18], Queue16_UInt8_2.io.deq.bits connect remapVecValids[18], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_4916 = eq(UInt<2>(0h3), remapindex_18) when _T_4916 : connect remapVecData[18], Queue16_UInt8_3.io.deq.bits connect remapVecValids[18], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_4917 = eq(UInt<3>(0h4), remapindex_18) when _T_4917 : connect remapVecData[18], Queue16_UInt8_4.io.deq.bits connect remapVecValids[18], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_4918 = eq(UInt<3>(0h5), remapindex_18) when _T_4918 : connect remapVecData[18], Queue16_UInt8_5.io.deq.bits connect remapVecValids[18], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_4919 = eq(UInt<3>(0h6), remapindex_18) when _T_4919 : connect remapVecData[18], Queue16_UInt8_6.io.deq.bits connect remapVecValids[18], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_4920 = eq(UInt<3>(0h7), remapindex_18) when _T_4920 : connect remapVecData[18], Queue16_UInt8_7.io.deq.bits connect remapVecValids[18], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_4921 = eq(UInt<4>(0h8), remapindex_18) when _T_4921 : connect remapVecData[18], Queue16_UInt8_8.io.deq.bits connect remapVecValids[18], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_4922 = eq(UInt<4>(0h9), remapindex_18) when _T_4922 : connect remapVecData[18], Queue16_UInt8_9.io.deq.bits connect remapVecValids[18], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_4923 = eq(UInt<4>(0ha), remapindex_18) when _T_4923 : connect remapVecData[18], Queue16_UInt8_10.io.deq.bits connect remapVecValids[18], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_4924 = eq(UInt<4>(0hb), remapindex_18) when _T_4924 : connect remapVecData[18], Queue16_UInt8_11.io.deq.bits connect remapVecValids[18], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_4925 = eq(UInt<4>(0hc), remapindex_18) when _T_4925 : connect remapVecData[18], Queue16_UInt8_12.io.deq.bits connect remapVecValids[18], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_4926 = eq(UInt<4>(0hd), remapindex_18) when _T_4926 : connect remapVecData[18], Queue16_UInt8_13.io.deq.bits connect remapVecValids[18], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_4927 = eq(UInt<4>(0he), remapindex_18) when _T_4927 : connect remapVecData[18], Queue16_UInt8_14.io.deq.bits connect remapVecValids[18], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_4928 = eq(UInt<4>(0hf), remapindex_18) when _T_4928 : connect remapVecData[18], Queue16_UInt8_15.io.deq.bits connect remapVecValids[18], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_4929 = eq(UInt<5>(0h10), remapindex_18) when _T_4929 : connect remapVecData[18], Queue16_UInt8_16.io.deq.bits connect remapVecValids[18], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_4930 = eq(UInt<5>(0h11), remapindex_18) when _T_4930 : connect remapVecData[18], Queue16_UInt8_17.io.deq.bits connect remapVecValids[18], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_4931 = eq(UInt<5>(0h12), remapindex_18) when _T_4931 : connect remapVecData[18], Queue16_UInt8_18.io.deq.bits connect remapVecValids[18], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_4932 = eq(UInt<5>(0h13), remapindex_18) when _T_4932 : connect remapVecData[18], Queue16_UInt8_19.io.deq.bits connect remapVecValids[18], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_4933 = eq(UInt<5>(0h14), remapindex_18) when _T_4933 : connect remapVecData[18], Queue16_UInt8_20.io.deq.bits connect remapVecValids[18], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_4934 = eq(UInt<5>(0h15), remapindex_18) when _T_4934 : connect remapVecData[18], Queue16_UInt8_21.io.deq.bits connect remapVecValids[18], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_4935 = eq(UInt<5>(0h16), remapindex_18) when _T_4935 : connect remapVecData[18], Queue16_UInt8_22.io.deq.bits connect remapVecValids[18], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_4936 = eq(UInt<5>(0h17), remapindex_18) when _T_4936 : connect remapVecData[18], Queue16_UInt8_23.io.deq.bits connect remapVecValids[18], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_4937 = eq(UInt<5>(0h18), remapindex_18) when _T_4937 : connect remapVecData[18], Queue16_UInt8_24.io.deq.bits connect remapVecValids[18], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_4938 = eq(UInt<5>(0h19), remapindex_18) when _T_4938 : connect remapVecData[18], Queue16_UInt8_25.io.deq.bits connect remapVecValids[18], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_4939 = eq(UInt<5>(0h1a), remapindex_18) when _T_4939 : connect remapVecData[18], Queue16_UInt8_26.io.deq.bits connect remapVecValids[18], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_4940 = eq(UInt<5>(0h1b), remapindex_18) when _T_4940 : connect remapVecData[18], Queue16_UInt8_27.io.deq.bits connect remapVecValids[18], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_4941 = eq(UInt<5>(0h1c), remapindex_18) when _T_4941 : connect remapVecData[18], Queue16_UInt8_28.io.deq.bits connect remapVecValids[18], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_4942 = eq(UInt<5>(0h1d), remapindex_18) when _T_4942 : connect remapVecData[18], Queue16_UInt8_29.io.deq.bits connect remapVecValids[18], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_4943 = eq(UInt<5>(0h1e), remapindex_18) when _T_4943 : connect remapVecData[18], Queue16_UInt8_30.io.deq.bits connect remapVecValids[18], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_4944 = eq(UInt<5>(0h1f), remapindex_18) when _T_4944 : connect remapVecData[18], Queue16_UInt8_31.io.deq.bits connect remapVecValids[18], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_4945 = eq(UInt<1>(0h0), remapindex_19) when _T_4945 : connect remapVecData[19], Queue16_UInt8.io.deq.bits connect remapVecValids[19], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[19] node _T_4946 = eq(UInt<1>(0h1), remapindex_19) when _T_4946 : connect remapVecData[19], Queue16_UInt8_1.io.deq.bits connect remapVecValids[19], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_4947 = eq(UInt<2>(0h2), remapindex_19) when _T_4947 : connect remapVecData[19], Queue16_UInt8_2.io.deq.bits connect remapVecValids[19], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_4948 = eq(UInt<2>(0h3), remapindex_19) when _T_4948 : connect remapVecData[19], Queue16_UInt8_3.io.deq.bits connect remapVecValids[19], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_4949 = eq(UInt<3>(0h4), remapindex_19) when _T_4949 : connect remapVecData[19], Queue16_UInt8_4.io.deq.bits connect remapVecValids[19], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_4950 = eq(UInt<3>(0h5), remapindex_19) when _T_4950 : connect remapVecData[19], Queue16_UInt8_5.io.deq.bits connect remapVecValids[19], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_4951 = eq(UInt<3>(0h6), remapindex_19) when _T_4951 : connect remapVecData[19], Queue16_UInt8_6.io.deq.bits connect remapVecValids[19], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_4952 = eq(UInt<3>(0h7), remapindex_19) when _T_4952 : connect remapVecData[19], Queue16_UInt8_7.io.deq.bits connect remapVecValids[19], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_4953 = eq(UInt<4>(0h8), remapindex_19) when _T_4953 : connect remapVecData[19], Queue16_UInt8_8.io.deq.bits connect remapVecValids[19], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_4954 = eq(UInt<4>(0h9), remapindex_19) when _T_4954 : connect remapVecData[19], Queue16_UInt8_9.io.deq.bits connect remapVecValids[19], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_4955 = eq(UInt<4>(0ha), remapindex_19) when _T_4955 : connect remapVecData[19], Queue16_UInt8_10.io.deq.bits connect remapVecValids[19], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_4956 = eq(UInt<4>(0hb), remapindex_19) when _T_4956 : connect remapVecData[19], Queue16_UInt8_11.io.deq.bits connect remapVecValids[19], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_4957 = eq(UInt<4>(0hc), remapindex_19) when _T_4957 : connect remapVecData[19], Queue16_UInt8_12.io.deq.bits connect remapVecValids[19], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_4958 = eq(UInt<4>(0hd), remapindex_19) when _T_4958 : connect remapVecData[19], Queue16_UInt8_13.io.deq.bits connect remapVecValids[19], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_4959 = eq(UInt<4>(0he), remapindex_19) when _T_4959 : connect remapVecData[19], Queue16_UInt8_14.io.deq.bits connect remapVecValids[19], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_4960 = eq(UInt<4>(0hf), remapindex_19) when _T_4960 : connect remapVecData[19], Queue16_UInt8_15.io.deq.bits connect remapVecValids[19], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_4961 = eq(UInt<5>(0h10), remapindex_19) when _T_4961 : connect remapVecData[19], Queue16_UInt8_16.io.deq.bits connect remapVecValids[19], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_4962 = eq(UInt<5>(0h11), remapindex_19) when _T_4962 : connect remapVecData[19], Queue16_UInt8_17.io.deq.bits connect remapVecValids[19], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_4963 = eq(UInt<5>(0h12), remapindex_19) when _T_4963 : connect remapVecData[19], Queue16_UInt8_18.io.deq.bits connect remapVecValids[19], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_4964 = eq(UInt<5>(0h13), remapindex_19) when _T_4964 : connect remapVecData[19], Queue16_UInt8_19.io.deq.bits connect remapVecValids[19], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_4965 = eq(UInt<5>(0h14), remapindex_19) when _T_4965 : connect remapVecData[19], Queue16_UInt8_20.io.deq.bits connect remapVecValids[19], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_4966 = eq(UInt<5>(0h15), remapindex_19) when _T_4966 : connect remapVecData[19], Queue16_UInt8_21.io.deq.bits connect remapVecValids[19], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_4967 = eq(UInt<5>(0h16), remapindex_19) when _T_4967 : connect remapVecData[19], Queue16_UInt8_22.io.deq.bits connect remapVecValids[19], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_4968 = eq(UInt<5>(0h17), remapindex_19) when _T_4968 : connect remapVecData[19], Queue16_UInt8_23.io.deq.bits connect remapVecValids[19], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_4969 = eq(UInt<5>(0h18), remapindex_19) when _T_4969 : connect remapVecData[19], Queue16_UInt8_24.io.deq.bits connect remapVecValids[19], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_4970 = eq(UInt<5>(0h19), remapindex_19) when _T_4970 : connect remapVecData[19], Queue16_UInt8_25.io.deq.bits connect remapVecValids[19], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_4971 = eq(UInt<5>(0h1a), remapindex_19) when _T_4971 : connect remapVecData[19], Queue16_UInt8_26.io.deq.bits connect remapVecValids[19], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_4972 = eq(UInt<5>(0h1b), remapindex_19) when _T_4972 : connect remapVecData[19], Queue16_UInt8_27.io.deq.bits connect remapVecValids[19], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_4973 = eq(UInt<5>(0h1c), remapindex_19) when _T_4973 : connect remapVecData[19], Queue16_UInt8_28.io.deq.bits connect remapVecValids[19], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_4974 = eq(UInt<5>(0h1d), remapindex_19) when _T_4974 : connect remapVecData[19], Queue16_UInt8_29.io.deq.bits connect remapVecValids[19], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_4975 = eq(UInt<5>(0h1e), remapindex_19) when _T_4975 : connect remapVecData[19], Queue16_UInt8_30.io.deq.bits connect remapVecValids[19], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_4976 = eq(UInt<5>(0h1f), remapindex_19) when _T_4976 : connect remapVecData[19], Queue16_UInt8_31.io.deq.bits connect remapVecValids[19], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_4977 = eq(UInt<1>(0h0), remapindex_20) when _T_4977 : connect remapVecData[20], Queue16_UInt8.io.deq.bits connect remapVecValids[20], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[20] node _T_4978 = eq(UInt<1>(0h1), remapindex_20) when _T_4978 : connect remapVecData[20], Queue16_UInt8_1.io.deq.bits connect remapVecValids[20], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_4979 = eq(UInt<2>(0h2), remapindex_20) when _T_4979 : connect remapVecData[20], Queue16_UInt8_2.io.deq.bits connect remapVecValids[20], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_4980 = eq(UInt<2>(0h3), remapindex_20) when _T_4980 : connect remapVecData[20], Queue16_UInt8_3.io.deq.bits connect remapVecValids[20], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_4981 = eq(UInt<3>(0h4), remapindex_20) when _T_4981 : connect remapVecData[20], Queue16_UInt8_4.io.deq.bits connect remapVecValids[20], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_4982 = eq(UInt<3>(0h5), remapindex_20) when _T_4982 : connect remapVecData[20], Queue16_UInt8_5.io.deq.bits connect remapVecValids[20], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_4983 = eq(UInt<3>(0h6), remapindex_20) when _T_4983 : connect remapVecData[20], Queue16_UInt8_6.io.deq.bits connect remapVecValids[20], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_4984 = eq(UInt<3>(0h7), remapindex_20) when _T_4984 : connect remapVecData[20], Queue16_UInt8_7.io.deq.bits connect remapVecValids[20], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_4985 = eq(UInt<4>(0h8), remapindex_20) when _T_4985 : connect remapVecData[20], Queue16_UInt8_8.io.deq.bits connect remapVecValids[20], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_4986 = eq(UInt<4>(0h9), remapindex_20) when _T_4986 : connect remapVecData[20], Queue16_UInt8_9.io.deq.bits connect remapVecValids[20], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_4987 = eq(UInt<4>(0ha), remapindex_20) when _T_4987 : connect remapVecData[20], Queue16_UInt8_10.io.deq.bits connect remapVecValids[20], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_4988 = eq(UInt<4>(0hb), remapindex_20) when _T_4988 : connect remapVecData[20], Queue16_UInt8_11.io.deq.bits connect remapVecValids[20], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_4989 = eq(UInt<4>(0hc), remapindex_20) when _T_4989 : connect remapVecData[20], Queue16_UInt8_12.io.deq.bits connect remapVecValids[20], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_4990 = eq(UInt<4>(0hd), remapindex_20) when _T_4990 : connect remapVecData[20], Queue16_UInt8_13.io.deq.bits connect remapVecValids[20], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_4991 = eq(UInt<4>(0he), remapindex_20) when _T_4991 : connect remapVecData[20], Queue16_UInt8_14.io.deq.bits connect remapVecValids[20], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_4992 = eq(UInt<4>(0hf), remapindex_20) when _T_4992 : connect remapVecData[20], Queue16_UInt8_15.io.deq.bits connect remapVecValids[20], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_4993 = eq(UInt<5>(0h10), remapindex_20) when _T_4993 : connect remapVecData[20], Queue16_UInt8_16.io.deq.bits connect remapVecValids[20], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_4994 = eq(UInt<5>(0h11), remapindex_20) when _T_4994 : connect remapVecData[20], Queue16_UInt8_17.io.deq.bits connect remapVecValids[20], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_4995 = eq(UInt<5>(0h12), remapindex_20) when _T_4995 : connect remapVecData[20], Queue16_UInt8_18.io.deq.bits connect remapVecValids[20], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_4996 = eq(UInt<5>(0h13), remapindex_20) when _T_4996 : connect remapVecData[20], Queue16_UInt8_19.io.deq.bits connect remapVecValids[20], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_4997 = eq(UInt<5>(0h14), remapindex_20) when _T_4997 : connect remapVecData[20], Queue16_UInt8_20.io.deq.bits connect remapVecValids[20], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_4998 = eq(UInt<5>(0h15), remapindex_20) when _T_4998 : connect remapVecData[20], Queue16_UInt8_21.io.deq.bits connect remapVecValids[20], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_4999 = eq(UInt<5>(0h16), remapindex_20) when _T_4999 : connect remapVecData[20], Queue16_UInt8_22.io.deq.bits connect remapVecValids[20], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_5000 = eq(UInt<5>(0h17), remapindex_20) when _T_5000 : connect remapVecData[20], Queue16_UInt8_23.io.deq.bits connect remapVecValids[20], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_5001 = eq(UInt<5>(0h18), remapindex_20) when _T_5001 : connect remapVecData[20], Queue16_UInt8_24.io.deq.bits connect remapVecValids[20], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_5002 = eq(UInt<5>(0h19), remapindex_20) when _T_5002 : connect remapVecData[20], Queue16_UInt8_25.io.deq.bits connect remapVecValids[20], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_5003 = eq(UInt<5>(0h1a), remapindex_20) when _T_5003 : connect remapVecData[20], Queue16_UInt8_26.io.deq.bits connect remapVecValids[20], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_5004 = eq(UInt<5>(0h1b), remapindex_20) when _T_5004 : connect remapVecData[20], Queue16_UInt8_27.io.deq.bits connect remapVecValids[20], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_5005 = eq(UInt<5>(0h1c), remapindex_20) when _T_5005 : connect remapVecData[20], Queue16_UInt8_28.io.deq.bits connect remapVecValids[20], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_5006 = eq(UInt<5>(0h1d), remapindex_20) when _T_5006 : connect remapVecData[20], Queue16_UInt8_29.io.deq.bits connect remapVecValids[20], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_5007 = eq(UInt<5>(0h1e), remapindex_20) when _T_5007 : connect remapVecData[20], Queue16_UInt8_30.io.deq.bits connect remapVecValids[20], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_5008 = eq(UInt<5>(0h1f), remapindex_20) when _T_5008 : connect remapVecData[20], Queue16_UInt8_31.io.deq.bits connect remapVecValids[20], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_5009 = eq(UInt<1>(0h0), remapindex_21) when _T_5009 : connect remapVecData[21], Queue16_UInt8.io.deq.bits connect remapVecValids[21], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[21] node _T_5010 = eq(UInt<1>(0h1), remapindex_21) when _T_5010 : connect remapVecData[21], Queue16_UInt8_1.io.deq.bits connect remapVecValids[21], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_5011 = eq(UInt<2>(0h2), remapindex_21) when _T_5011 : connect remapVecData[21], Queue16_UInt8_2.io.deq.bits connect remapVecValids[21], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_5012 = eq(UInt<2>(0h3), remapindex_21) when _T_5012 : connect remapVecData[21], Queue16_UInt8_3.io.deq.bits connect remapVecValids[21], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_5013 = eq(UInt<3>(0h4), remapindex_21) when _T_5013 : connect remapVecData[21], Queue16_UInt8_4.io.deq.bits connect remapVecValids[21], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_5014 = eq(UInt<3>(0h5), remapindex_21) when _T_5014 : connect remapVecData[21], Queue16_UInt8_5.io.deq.bits connect remapVecValids[21], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_5015 = eq(UInt<3>(0h6), remapindex_21) when _T_5015 : connect remapVecData[21], Queue16_UInt8_6.io.deq.bits connect remapVecValids[21], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_5016 = eq(UInt<3>(0h7), remapindex_21) when _T_5016 : connect remapVecData[21], Queue16_UInt8_7.io.deq.bits connect remapVecValids[21], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_5017 = eq(UInt<4>(0h8), remapindex_21) when _T_5017 : connect remapVecData[21], Queue16_UInt8_8.io.deq.bits connect remapVecValids[21], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_5018 = eq(UInt<4>(0h9), remapindex_21) when _T_5018 : connect remapVecData[21], Queue16_UInt8_9.io.deq.bits connect remapVecValids[21], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_5019 = eq(UInt<4>(0ha), remapindex_21) when _T_5019 : connect remapVecData[21], Queue16_UInt8_10.io.deq.bits connect remapVecValids[21], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_5020 = eq(UInt<4>(0hb), remapindex_21) when _T_5020 : connect remapVecData[21], Queue16_UInt8_11.io.deq.bits connect remapVecValids[21], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_5021 = eq(UInt<4>(0hc), remapindex_21) when _T_5021 : connect remapVecData[21], Queue16_UInt8_12.io.deq.bits connect remapVecValids[21], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_5022 = eq(UInt<4>(0hd), remapindex_21) when _T_5022 : connect remapVecData[21], Queue16_UInt8_13.io.deq.bits connect remapVecValids[21], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_5023 = eq(UInt<4>(0he), remapindex_21) when _T_5023 : connect remapVecData[21], Queue16_UInt8_14.io.deq.bits connect remapVecValids[21], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_5024 = eq(UInt<4>(0hf), remapindex_21) when _T_5024 : connect remapVecData[21], Queue16_UInt8_15.io.deq.bits connect remapVecValids[21], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_5025 = eq(UInt<5>(0h10), remapindex_21) when _T_5025 : connect remapVecData[21], Queue16_UInt8_16.io.deq.bits connect remapVecValids[21], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_5026 = eq(UInt<5>(0h11), remapindex_21) when _T_5026 : connect remapVecData[21], Queue16_UInt8_17.io.deq.bits connect remapVecValids[21], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_5027 = eq(UInt<5>(0h12), remapindex_21) when _T_5027 : connect remapVecData[21], Queue16_UInt8_18.io.deq.bits connect remapVecValids[21], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_5028 = eq(UInt<5>(0h13), remapindex_21) when _T_5028 : connect remapVecData[21], Queue16_UInt8_19.io.deq.bits connect remapVecValids[21], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_5029 = eq(UInt<5>(0h14), remapindex_21) when _T_5029 : connect remapVecData[21], Queue16_UInt8_20.io.deq.bits connect remapVecValids[21], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_5030 = eq(UInt<5>(0h15), remapindex_21) when _T_5030 : connect remapVecData[21], Queue16_UInt8_21.io.deq.bits connect remapVecValids[21], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_5031 = eq(UInt<5>(0h16), remapindex_21) when _T_5031 : connect remapVecData[21], Queue16_UInt8_22.io.deq.bits connect remapVecValids[21], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_5032 = eq(UInt<5>(0h17), remapindex_21) when _T_5032 : connect remapVecData[21], Queue16_UInt8_23.io.deq.bits connect remapVecValids[21], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_5033 = eq(UInt<5>(0h18), remapindex_21) when _T_5033 : connect remapVecData[21], Queue16_UInt8_24.io.deq.bits connect remapVecValids[21], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_5034 = eq(UInt<5>(0h19), remapindex_21) when _T_5034 : connect remapVecData[21], Queue16_UInt8_25.io.deq.bits connect remapVecValids[21], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_5035 = eq(UInt<5>(0h1a), remapindex_21) when _T_5035 : connect remapVecData[21], Queue16_UInt8_26.io.deq.bits connect remapVecValids[21], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_5036 = eq(UInt<5>(0h1b), remapindex_21) when _T_5036 : connect remapVecData[21], Queue16_UInt8_27.io.deq.bits connect remapVecValids[21], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_5037 = eq(UInt<5>(0h1c), remapindex_21) when _T_5037 : connect remapVecData[21], Queue16_UInt8_28.io.deq.bits connect remapVecValids[21], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_5038 = eq(UInt<5>(0h1d), remapindex_21) when _T_5038 : connect remapVecData[21], Queue16_UInt8_29.io.deq.bits connect remapVecValids[21], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_5039 = eq(UInt<5>(0h1e), remapindex_21) when _T_5039 : connect remapVecData[21], Queue16_UInt8_30.io.deq.bits connect remapVecValids[21], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_5040 = eq(UInt<5>(0h1f), remapindex_21) when _T_5040 : connect remapVecData[21], Queue16_UInt8_31.io.deq.bits connect remapVecValids[21], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_5041 = eq(UInt<1>(0h0), remapindex_22) when _T_5041 : connect remapVecData[22], Queue16_UInt8.io.deq.bits connect remapVecValids[22], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[22] node _T_5042 = eq(UInt<1>(0h1), remapindex_22) when _T_5042 : connect remapVecData[22], Queue16_UInt8_1.io.deq.bits connect remapVecValids[22], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_5043 = eq(UInt<2>(0h2), remapindex_22) when _T_5043 : connect remapVecData[22], Queue16_UInt8_2.io.deq.bits connect remapVecValids[22], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_5044 = eq(UInt<2>(0h3), remapindex_22) when _T_5044 : connect remapVecData[22], Queue16_UInt8_3.io.deq.bits connect remapVecValids[22], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_5045 = eq(UInt<3>(0h4), remapindex_22) when _T_5045 : connect remapVecData[22], Queue16_UInt8_4.io.deq.bits connect remapVecValids[22], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_5046 = eq(UInt<3>(0h5), remapindex_22) when _T_5046 : connect remapVecData[22], Queue16_UInt8_5.io.deq.bits connect remapVecValids[22], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_5047 = eq(UInt<3>(0h6), remapindex_22) when _T_5047 : connect remapVecData[22], Queue16_UInt8_6.io.deq.bits connect remapVecValids[22], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_5048 = eq(UInt<3>(0h7), remapindex_22) when _T_5048 : connect remapVecData[22], Queue16_UInt8_7.io.deq.bits connect remapVecValids[22], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_5049 = eq(UInt<4>(0h8), remapindex_22) when _T_5049 : connect remapVecData[22], Queue16_UInt8_8.io.deq.bits connect remapVecValids[22], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_5050 = eq(UInt<4>(0h9), remapindex_22) when _T_5050 : connect remapVecData[22], Queue16_UInt8_9.io.deq.bits connect remapVecValids[22], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_5051 = eq(UInt<4>(0ha), remapindex_22) when _T_5051 : connect remapVecData[22], Queue16_UInt8_10.io.deq.bits connect remapVecValids[22], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_5052 = eq(UInt<4>(0hb), remapindex_22) when _T_5052 : connect remapVecData[22], Queue16_UInt8_11.io.deq.bits connect remapVecValids[22], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_5053 = eq(UInt<4>(0hc), remapindex_22) when _T_5053 : connect remapVecData[22], Queue16_UInt8_12.io.deq.bits connect remapVecValids[22], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_5054 = eq(UInt<4>(0hd), remapindex_22) when _T_5054 : connect remapVecData[22], Queue16_UInt8_13.io.deq.bits connect remapVecValids[22], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_5055 = eq(UInt<4>(0he), remapindex_22) when _T_5055 : connect remapVecData[22], Queue16_UInt8_14.io.deq.bits connect remapVecValids[22], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_5056 = eq(UInt<4>(0hf), remapindex_22) when _T_5056 : connect remapVecData[22], Queue16_UInt8_15.io.deq.bits connect remapVecValids[22], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_5057 = eq(UInt<5>(0h10), remapindex_22) when _T_5057 : connect remapVecData[22], Queue16_UInt8_16.io.deq.bits connect remapVecValids[22], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_5058 = eq(UInt<5>(0h11), remapindex_22) when _T_5058 : connect remapVecData[22], Queue16_UInt8_17.io.deq.bits connect remapVecValids[22], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_5059 = eq(UInt<5>(0h12), remapindex_22) when _T_5059 : connect remapVecData[22], Queue16_UInt8_18.io.deq.bits connect remapVecValids[22], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_5060 = eq(UInt<5>(0h13), remapindex_22) when _T_5060 : connect remapVecData[22], Queue16_UInt8_19.io.deq.bits connect remapVecValids[22], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_5061 = eq(UInt<5>(0h14), remapindex_22) when _T_5061 : connect remapVecData[22], Queue16_UInt8_20.io.deq.bits connect remapVecValids[22], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_5062 = eq(UInt<5>(0h15), remapindex_22) when _T_5062 : connect remapVecData[22], Queue16_UInt8_21.io.deq.bits connect remapVecValids[22], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_5063 = eq(UInt<5>(0h16), remapindex_22) when _T_5063 : connect remapVecData[22], Queue16_UInt8_22.io.deq.bits connect remapVecValids[22], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_5064 = eq(UInt<5>(0h17), remapindex_22) when _T_5064 : connect remapVecData[22], Queue16_UInt8_23.io.deq.bits connect remapVecValids[22], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_5065 = eq(UInt<5>(0h18), remapindex_22) when _T_5065 : connect remapVecData[22], Queue16_UInt8_24.io.deq.bits connect remapVecValids[22], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_5066 = eq(UInt<5>(0h19), remapindex_22) when _T_5066 : connect remapVecData[22], Queue16_UInt8_25.io.deq.bits connect remapVecValids[22], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_5067 = eq(UInt<5>(0h1a), remapindex_22) when _T_5067 : connect remapVecData[22], Queue16_UInt8_26.io.deq.bits connect remapVecValids[22], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_5068 = eq(UInt<5>(0h1b), remapindex_22) when _T_5068 : connect remapVecData[22], Queue16_UInt8_27.io.deq.bits connect remapVecValids[22], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_5069 = eq(UInt<5>(0h1c), remapindex_22) when _T_5069 : connect remapVecData[22], Queue16_UInt8_28.io.deq.bits connect remapVecValids[22], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_5070 = eq(UInt<5>(0h1d), remapindex_22) when _T_5070 : connect remapVecData[22], Queue16_UInt8_29.io.deq.bits connect remapVecValids[22], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_5071 = eq(UInt<5>(0h1e), remapindex_22) when _T_5071 : connect remapVecData[22], Queue16_UInt8_30.io.deq.bits connect remapVecValids[22], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_5072 = eq(UInt<5>(0h1f), remapindex_22) when _T_5072 : connect remapVecData[22], Queue16_UInt8_31.io.deq.bits connect remapVecValids[22], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_5073 = eq(UInt<1>(0h0), remapindex_23) when _T_5073 : connect remapVecData[23], Queue16_UInt8.io.deq.bits connect remapVecValids[23], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[23] node _T_5074 = eq(UInt<1>(0h1), remapindex_23) when _T_5074 : connect remapVecData[23], Queue16_UInt8_1.io.deq.bits connect remapVecValids[23], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_5075 = eq(UInt<2>(0h2), remapindex_23) when _T_5075 : connect remapVecData[23], Queue16_UInt8_2.io.deq.bits connect remapVecValids[23], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_5076 = eq(UInt<2>(0h3), remapindex_23) when _T_5076 : connect remapVecData[23], Queue16_UInt8_3.io.deq.bits connect remapVecValids[23], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_5077 = eq(UInt<3>(0h4), remapindex_23) when _T_5077 : connect remapVecData[23], Queue16_UInt8_4.io.deq.bits connect remapVecValids[23], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_5078 = eq(UInt<3>(0h5), remapindex_23) when _T_5078 : connect remapVecData[23], Queue16_UInt8_5.io.deq.bits connect remapVecValids[23], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_5079 = eq(UInt<3>(0h6), remapindex_23) when _T_5079 : connect remapVecData[23], Queue16_UInt8_6.io.deq.bits connect remapVecValids[23], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_5080 = eq(UInt<3>(0h7), remapindex_23) when _T_5080 : connect remapVecData[23], Queue16_UInt8_7.io.deq.bits connect remapVecValids[23], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_5081 = eq(UInt<4>(0h8), remapindex_23) when _T_5081 : connect remapVecData[23], Queue16_UInt8_8.io.deq.bits connect remapVecValids[23], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_5082 = eq(UInt<4>(0h9), remapindex_23) when _T_5082 : connect remapVecData[23], Queue16_UInt8_9.io.deq.bits connect remapVecValids[23], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_5083 = eq(UInt<4>(0ha), remapindex_23) when _T_5083 : connect remapVecData[23], Queue16_UInt8_10.io.deq.bits connect remapVecValids[23], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_5084 = eq(UInt<4>(0hb), remapindex_23) when _T_5084 : connect remapVecData[23], Queue16_UInt8_11.io.deq.bits connect remapVecValids[23], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_5085 = eq(UInt<4>(0hc), remapindex_23) when _T_5085 : connect remapVecData[23], Queue16_UInt8_12.io.deq.bits connect remapVecValids[23], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_5086 = eq(UInt<4>(0hd), remapindex_23) when _T_5086 : connect remapVecData[23], Queue16_UInt8_13.io.deq.bits connect remapVecValids[23], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_5087 = eq(UInt<4>(0he), remapindex_23) when _T_5087 : connect remapVecData[23], Queue16_UInt8_14.io.deq.bits connect remapVecValids[23], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_5088 = eq(UInt<4>(0hf), remapindex_23) when _T_5088 : connect remapVecData[23], Queue16_UInt8_15.io.deq.bits connect remapVecValids[23], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_5089 = eq(UInt<5>(0h10), remapindex_23) when _T_5089 : connect remapVecData[23], Queue16_UInt8_16.io.deq.bits connect remapVecValids[23], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_5090 = eq(UInt<5>(0h11), remapindex_23) when _T_5090 : connect remapVecData[23], Queue16_UInt8_17.io.deq.bits connect remapVecValids[23], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_5091 = eq(UInt<5>(0h12), remapindex_23) when _T_5091 : connect remapVecData[23], Queue16_UInt8_18.io.deq.bits connect remapVecValids[23], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_5092 = eq(UInt<5>(0h13), remapindex_23) when _T_5092 : connect remapVecData[23], Queue16_UInt8_19.io.deq.bits connect remapVecValids[23], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_5093 = eq(UInt<5>(0h14), remapindex_23) when _T_5093 : connect remapVecData[23], Queue16_UInt8_20.io.deq.bits connect remapVecValids[23], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_5094 = eq(UInt<5>(0h15), remapindex_23) when _T_5094 : connect remapVecData[23], Queue16_UInt8_21.io.deq.bits connect remapVecValids[23], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_5095 = eq(UInt<5>(0h16), remapindex_23) when _T_5095 : connect remapVecData[23], Queue16_UInt8_22.io.deq.bits connect remapVecValids[23], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_5096 = eq(UInt<5>(0h17), remapindex_23) when _T_5096 : connect remapVecData[23], Queue16_UInt8_23.io.deq.bits connect remapVecValids[23], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_5097 = eq(UInt<5>(0h18), remapindex_23) when _T_5097 : connect remapVecData[23], Queue16_UInt8_24.io.deq.bits connect remapVecValids[23], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_5098 = eq(UInt<5>(0h19), remapindex_23) when _T_5098 : connect remapVecData[23], Queue16_UInt8_25.io.deq.bits connect remapVecValids[23], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_5099 = eq(UInt<5>(0h1a), remapindex_23) when _T_5099 : connect remapVecData[23], Queue16_UInt8_26.io.deq.bits connect remapVecValids[23], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_5100 = eq(UInt<5>(0h1b), remapindex_23) when _T_5100 : connect remapVecData[23], Queue16_UInt8_27.io.deq.bits connect remapVecValids[23], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_5101 = eq(UInt<5>(0h1c), remapindex_23) when _T_5101 : connect remapVecData[23], Queue16_UInt8_28.io.deq.bits connect remapVecValids[23], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_5102 = eq(UInt<5>(0h1d), remapindex_23) when _T_5102 : connect remapVecData[23], Queue16_UInt8_29.io.deq.bits connect remapVecValids[23], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_5103 = eq(UInt<5>(0h1e), remapindex_23) when _T_5103 : connect remapVecData[23], Queue16_UInt8_30.io.deq.bits connect remapVecValids[23], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_5104 = eq(UInt<5>(0h1f), remapindex_23) when _T_5104 : connect remapVecData[23], Queue16_UInt8_31.io.deq.bits connect remapVecValids[23], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_5105 = eq(UInt<1>(0h0), remapindex_24) when _T_5105 : connect remapVecData[24], Queue16_UInt8.io.deq.bits connect remapVecValids[24], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[24] node _T_5106 = eq(UInt<1>(0h1), remapindex_24) when _T_5106 : connect remapVecData[24], Queue16_UInt8_1.io.deq.bits connect remapVecValids[24], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_5107 = eq(UInt<2>(0h2), remapindex_24) when _T_5107 : connect remapVecData[24], Queue16_UInt8_2.io.deq.bits connect remapVecValids[24], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_5108 = eq(UInt<2>(0h3), remapindex_24) when _T_5108 : connect remapVecData[24], Queue16_UInt8_3.io.deq.bits connect remapVecValids[24], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_5109 = eq(UInt<3>(0h4), remapindex_24) when _T_5109 : connect remapVecData[24], Queue16_UInt8_4.io.deq.bits connect remapVecValids[24], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_5110 = eq(UInt<3>(0h5), remapindex_24) when _T_5110 : connect remapVecData[24], Queue16_UInt8_5.io.deq.bits connect remapVecValids[24], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_5111 = eq(UInt<3>(0h6), remapindex_24) when _T_5111 : connect remapVecData[24], Queue16_UInt8_6.io.deq.bits connect remapVecValids[24], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_5112 = eq(UInt<3>(0h7), remapindex_24) when _T_5112 : connect remapVecData[24], Queue16_UInt8_7.io.deq.bits connect remapVecValids[24], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_5113 = eq(UInt<4>(0h8), remapindex_24) when _T_5113 : connect remapVecData[24], Queue16_UInt8_8.io.deq.bits connect remapVecValids[24], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_5114 = eq(UInt<4>(0h9), remapindex_24) when _T_5114 : connect remapVecData[24], Queue16_UInt8_9.io.deq.bits connect remapVecValids[24], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_5115 = eq(UInt<4>(0ha), remapindex_24) when _T_5115 : connect remapVecData[24], Queue16_UInt8_10.io.deq.bits connect remapVecValids[24], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_5116 = eq(UInt<4>(0hb), remapindex_24) when _T_5116 : connect remapVecData[24], Queue16_UInt8_11.io.deq.bits connect remapVecValids[24], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_5117 = eq(UInt<4>(0hc), remapindex_24) when _T_5117 : connect remapVecData[24], Queue16_UInt8_12.io.deq.bits connect remapVecValids[24], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_5118 = eq(UInt<4>(0hd), remapindex_24) when _T_5118 : connect remapVecData[24], Queue16_UInt8_13.io.deq.bits connect remapVecValids[24], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_5119 = eq(UInt<4>(0he), remapindex_24) when _T_5119 : connect remapVecData[24], Queue16_UInt8_14.io.deq.bits connect remapVecValids[24], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_5120 = eq(UInt<4>(0hf), remapindex_24) when _T_5120 : connect remapVecData[24], Queue16_UInt8_15.io.deq.bits connect remapVecValids[24], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_5121 = eq(UInt<5>(0h10), remapindex_24) when _T_5121 : connect remapVecData[24], Queue16_UInt8_16.io.deq.bits connect remapVecValids[24], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_5122 = eq(UInt<5>(0h11), remapindex_24) when _T_5122 : connect remapVecData[24], Queue16_UInt8_17.io.deq.bits connect remapVecValids[24], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_5123 = eq(UInt<5>(0h12), remapindex_24) when _T_5123 : connect remapVecData[24], Queue16_UInt8_18.io.deq.bits connect remapVecValids[24], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_5124 = eq(UInt<5>(0h13), remapindex_24) when _T_5124 : connect remapVecData[24], Queue16_UInt8_19.io.deq.bits connect remapVecValids[24], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_5125 = eq(UInt<5>(0h14), remapindex_24) when _T_5125 : connect remapVecData[24], Queue16_UInt8_20.io.deq.bits connect remapVecValids[24], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_5126 = eq(UInt<5>(0h15), remapindex_24) when _T_5126 : connect remapVecData[24], Queue16_UInt8_21.io.deq.bits connect remapVecValids[24], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_5127 = eq(UInt<5>(0h16), remapindex_24) when _T_5127 : connect remapVecData[24], Queue16_UInt8_22.io.deq.bits connect remapVecValids[24], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_5128 = eq(UInt<5>(0h17), remapindex_24) when _T_5128 : connect remapVecData[24], Queue16_UInt8_23.io.deq.bits connect remapVecValids[24], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_5129 = eq(UInt<5>(0h18), remapindex_24) when _T_5129 : connect remapVecData[24], Queue16_UInt8_24.io.deq.bits connect remapVecValids[24], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_5130 = eq(UInt<5>(0h19), remapindex_24) when _T_5130 : connect remapVecData[24], Queue16_UInt8_25.io.deq.bits connect remapVecValids[24], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_5131 = eq(UInt<5>(0h1a), remapindex_24) when _T_5131 : connect remapVecData[24], Queue16_UInt8_26.io.deq.bits connect remapVecValids[24], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_5132 = eq(UInt<5>(0h1b), remapindex_24) when _T_5132 : connect remapVecData[24], Queue16_UInt8_27.io.deq.bits connect remapVecValids[24], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_5133 = eq(UInt<5>(0h1c), remapindex_24) when _T_5133 : connect remapVecData[24], Queue16_UInt8_28.io.deq.bits connect remapVecValids[24], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_5134 = eq(UInt<5>(0h1d), remapindex_24) when _T_5134 : connect remapVecData[24], Queue16_UInt8_29.io.deq.bits connect remapVecValids[24], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_5135 = eq(UInt<5>(0h1e), remapindex_24) when _T_5135 : connect remapVecData[24], Queue16_UInt8_30.io.deq.bits connect remapVecValids[24], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_5136 = eq(UInt<5>(0h1f), remapindex_24) when _T_5136 : connect remapVecData[24], Queue16_UInt8_31.io.deq.bits connect remapVecValids[24], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_5137 = eq(UInt<1>(0h0), remapindex_25) when _T_5137 : connect remapVecData[25], Queue16_UInt8.io.deq.bits connect remapVecValids[25], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[25] node _T_5138 = eq(UInt<1>(0h1), remapindex_25) when _T_5138 : connect remapVecData[25], Queue16_UInt8_1.io.deq.bits connect remapVecValids[25], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_5139 = eq(UInt<2>(0h2), remapindex_25) when _T_5139 : connect remapVecData[25], Queue16_UInt8_2.io.deq.bits connect remapVecValids[25], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_5140 = eq(UInt<2>(0h3), remapindex_25) when _T_5140 : connect remapVecData[25], Queue16_UInt8_3.io.deq.bits connect remapVecValids[25], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_5141 = eq(UInt<3>(0h4), remapindex_25) when _T_5141 : connect remapVecData[25], Queue16_UInt8_4.io.deq.bits connect remapVecValids[25], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_5142 = eq(UInt<3>(0h5), remapindex_25) when _T_5142 : connect remapVecData[25], Queue16_UInt8_5.io.deq.bits connect remapVecValids[25], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_5143 = eq(UInt<3>(0h6), remapindex_25) when _T_5143 : connect remapVecData[25], Queue16_UInt8_6.io.deq.bits connect remapVecValids[25], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_5144 = eq(UInt<3>(0h7), remapindex_25) when _T_5144 : connect remapVecData[25], Queue16_UInt8_7.io.deq.bits connect remapVecValids[25], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_5145 = eq(UInt<4>(0h8), remapindex_25) when _T_5145 : connect remapVecData[25], Queue16_UInt8_8.io.deq.bits connect remapVecValids[25], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_5146 = eq(UInt<4>(0h9), remapindex_25) when _T_5146 : connect remapVecData[25], Queue16_UInt8_9.io.deq.bits connect remapVecValids[25], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_5147 = eq(UInt<4>(0ha), remapindex_25) when _T_5147 : connect remapVecData[25], Queue16_UInt8_10.io.deq.bits connect remapVecValids[25], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_5148 = eq(UInt<4>(0hb), remapindex_25) when _T_5148 : connect remapVecData[25], Queue16_UInt8_11.io.deq.bits connect remapVecValids[25], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_5149 = eq(UInt<4>(0hc), remapindex_25) when _T_5149 : connect remapVecData[25], Queue16_UInt8_12.io.deq.bits connect remapVecValids[25], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_5150 = eq(UInt<4>(0hd), remapindex_25) when _T_5150 : connect remapVecData[25], Queue16_UInt8_13.io.deq.bits connect remapVecValids[25], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_5151 = eq(UInt<4>(0he), remapindex_25) when _T_5151 : connect remapVecData[25], Queue16_UInt8_14.io.deq.bits connect remapVecValids[25], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_5152 = eq(UInt<4>(0hf), remapindex_25) when _T_5152 : connect remapVecData[25], Queue16_UInt8_15.io.deq.bits connect remapVecValids[25], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_5153 = eq(UInt<5>(0h10), remapindex_25) when _T_5153 : connect remapVecData[25], Queue16_UInt8_16.io.deq.bits connect remapVecValids[25], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_5154 = eq(UInt<5>(0h11), remapindex_25) when _T_5154 : connect remapVecData[25], Queue16_UInt8_17.io.deq.bits connect remapVecValids[25], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_5155 = eq(UInt<5>(0h12), remapindex_25) when _T_5155 : connect remapVecData[25], Queue16_UInt8_18.io.deq.bits connect remapVecValids[25], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_5156 = eq(UInt<5>(0h13), remapindex_25) when _T_5156 : connect remapVecData[25], Queue16_UInt8_19.io.deq.bits connect remapVecValids[25], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_5157 = eq(UInt<5>(0h14), remapindex_25) when _T_5157 : connect remapVecData[25], Queue16_UInt8_20.io.deq.bits connect remapVecValids[25], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_5158 = eq(UInt<5>(0h15), remapindex_25) when _T_5158 : connect remapVecData[25], Queue16_UInt8_21.io.deq.bits connect remapVecValids[25], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_5159 = eq(UInt<5>(0h16), remapindex_25) when _T_5159 : connect remapVecData[25], Queue16_UInt8_22.io.deq.bits connect remapVecValids[25], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_5160 = eq(UInt<5>(0h17), remapindex_25) when _T_5160 : connect remapVecData[25], Queue16_UInt8_23.io.deq.bits connect remapVecValids[25], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_5161 = eq(UInt<5>(0h18), remapindex_25) when _T_5161 : connect remapVecData[25], Queue16_UInt8_24.io.deq.bits connect remapVecValids[25], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_5162 = eq(UInt<5>(0h19), remapindex_25) when _T_5162 : connect remapVecData[25], Queue16_UInt8_25.io.deq.bits connect remapVecValids[25], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_5163 = eq(UInt<5>(0h1a), remapindex_25) when _T_5163 : connect remapVecData[25], Queue16_UInt8_26.io.deq.bits connect remapVecValids[25], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_5164 = eq(UInt<5>(0h1b), remapindex_25) when _T_5164 : connect remapVecData[25], Queue16_UInt8_27.io.deq.bits connect remapVecValids[25], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_5165 = eq(UInt<5>(0h1c), remapindex_25) when _T_5165 : connect remapVecData[25], Queue16_UInt8_28.io.deq.bits connect remapVecValids[25], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_5166 = eq(UInt<5>(0h1d), remapindex_25) when _T_5166 : connect remapVecData[25], Queue16_UInt8_29.io.deq.bits connect remapVecValids[25], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_5167 = eq(UInt<5>(0h1e), remapindex_25) when _T_5167 : connect remapVecData[25], Queue16_UInt8_30.io.deq.bits connect remapVecValids[25], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_5168 = eq(UInt<5>(0h1f), remapindex_25) when _T_5168 : connect remapVecData[25], Queue16_UInt8_31.io.deq.bits connect remapVecValids[25], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_5169 = eq(UInt<1>(0h0), remapindex_26) when _T_5169 : connect remapVecData[26], Queue16_UInt8.io.deq.bits connect remapVecValids[26], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[26] node _T_5170 = eq(UInt<1>(0h1), remapindex_26) when _T_5170 : connect remapVecData[26], Queue16_UInt8_1.io.deq.bits connect remapVecValids[26], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_5171 = eq(UInt<2>(0h2), remapindex_26) when _T_5171 : connect remapVecData[26], Queue16_UInt8_2.io.deq.bits connect remapVecValids[26], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_5172 = eq(UInt<2>(0h3), remapindex_26) when _T_5172 : connect remapVecData[26], Queue16_UInt8_3.io.deq.bits connect remapVecValids[26], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_5173 = eq(UInt<3>(0h4), remapindex_26) when _T_5173 : connect remapVecData[26], Queue16_UInt8_4.io.deq.bits connect remapVecValids[26], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_5174 = eq(UInt<3>(0h5), remapindex_26) when _T_5174 : connect remapVecData[26], Queue16_UInt8_5.io.deq.bits connect remapVecValids[26], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_5175 = eq(UInt<3>(0h6), remapindex_26) when _T_5175 : connect remapVecData[26], Queue16_UInt8_6.io.deq.bits connect remapVecValids[26], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_5176 = eq(UInt<3>(0h7), remapindex_26) when _T_5176 : connect remapVecData[26], Queue16_UInt8_7.io.deq.bits connect remapVecValids[26], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_5177 = eq(UInt<4>(0h8), remapindex_26) when _T_5177 : connect remapVecData[26], Queue16_UInt8_8.io.deq.bits connect remapVecValids[26], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_5178 = eq(UInt<4>(0h9), remapindex_26) when _T_5178 : connect remapVecData[26], Queue16_UInt8_9.io.deq.bits connect remapVecValids[26], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_5179 = eq(UInt<4>(0ha), remapindex_26) when _T_5179 : connect remapVecData[26], Queue16_UInt8_10.io.deq.bits connect remapVecValids[26], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_5180 = eq(UInt<4>(0hb), remapindex_26) when _T_5180 : connect remapVecData[26], Queue16_UInt8_11.io.deq.bits connect remapVecValids[26], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_5181 = eq(UInt<4>(0hc), remapindex_26) when _T_5181 : connect remapVecData[26], Queue16_UInt8_12.io.deq.bits connect remapVecValids[26], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_5182 = eq(UInt<4>(0hd), remapindex_26) when _T_5182 : connect remapVecData[26], Queue16_UInt8_13.io.deq.bits connect remapVecValids[26], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_5183 = eq(UInt<4>(0he), remapindex_26) when _T_5183 : connect remapVecData[26], Queue16_UInt8_14.io.deq.bits connect remapVecValids[26], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_5184 = eq(UInt<4>(0hf), remapindex_26) when _T_5184 : connect remapVecData[26], Queue16_UInt8_15.io.deq.bits connect remapVecValids[26], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_5185 = eq(UInt<5>(0h10), remapindex_26) when _T_5185 : connect remapVecData[26], Queue16_UInt8_16.io.deq.bits connect remapVecValids[26], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_5186 = eq(UInt<5>(0h11), remapindex_26) when _T_5186 : connect remapVecData[26], Queue16_UInt8_17.io.deq.bits connect remapVecValids[26], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_5187 = eq(UInt<5>(0h12), remapindex_26) when _T_5187 : connect remapVecData[26], Queue16_UInt8_18.io.deq.bits connect remapVecValids[26], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_5188 = eq(UInt<5>(0h13), remapindex_26) when _T_5188 : connect remapVecData[26], Queue16_UInt8_19.io.deq.bits connect remapVecValids[26], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_5189 = eq(UInt<5>(0h14), remapindex_26) when _T_5189 : connect remapVecData[26], Queue16_UInt8_20.io.deq.bits connect remapVecValids[26], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_5190 = eq(UInt<5>(0h15), remapindex_26) when _T_5190 : connect remapVecData[26], Queue16_UInt8_21.io.deq.bits connect remapVecValids[26], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_5191 = eq(UInt<5>(0h16), remapindex_26) when _T_5191 : connect remapVecData[26], Queue16_UInt8_22.io.deq.bits connect remapVecValids[26], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_5192 = eq(UInt<5>(0h17), remapindex_26) when _T_5192 : connect remapVecData[26], Queue16_UInt8_23.io.deq.bits connect remapVecValids[26], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_5193 = eq(UInt<5>(0h18), remapindex_26) when _T_5193 : connect remapVecData[26], Queue16_UInt8_24.io.deq.bits connect remapVecValids[26], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_5194 = eq(UInt<5>(0h19), remapindex_26) when _T_5194 : connect remapVecData[26], Queue16_UInt8_25.io.deq.bits connect remapVecValids[26], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_5195 = eq(UInt<5>(0h1a), remapindex_26) when _T_5195 : connect remapVecData[26], Queue16_UInt8_26.io.deq.bits connect remapVecValids[26], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_5196 = eq(UInt<5>(0h1b), remapindex_26) when _T_5196 : connect remapVecData[26], Queue16_UInt8_27.io.deq.bits connect remapVecValids[26], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_5197 = eq(UInt<5>(0h1c), remapindex_26) when _T_5197 : connect remapVecData[26], Queue16_UInt8_28.io.deq.bits connect remapVecValids[26], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_5198 = eq(UInt<5>(0h1d), remapindex_26) when _T_5198 : connect remapVecData[26], Queue16_UInt8_29.io.deq.bits connect remapVecValids[26], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_5199 = eq(UInt<5>(0h1e), remapindex_26) when _T_5199 : connect remapVecData[26], Queue16_UInt8_30.io.deq.bits connect remapVecValids[26], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_5200 = eq(UInt<5>(0h1f), remapindex_26) when _T_5200 : connect remapVecData[26], Queue16_UInt8_31.io.deq.bits connect remapVecValids[26], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_5201 = eq(UInt<1>(0h0), remapindex_27) when _T_5201 : connect remapVecData[27], Queue16_UInt8.io.deq.bits connect remapVecValids[27], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[27] node _T_5202 = eq(UInt<1>(0h1), remapindex_27) when _T_5202 : connect remapVecData[27], Queue16_UInt8_1.io.deq.bits connect remapVecValids[27], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_5203 = eq(UInt<2>(0h2), remapindex_27) when _T_5203 : connect remapVecData[27], Queue16_UInt8_2.io.deq.bits connect remapVecValids[27], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_5204 = eq(UInt<2>(0h3), remapindex_27) when _T_5204 : connect remapVecData[27], Queue16_UInt8_3.io.deq.bits connect remapVecValids[27], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_5205 = eq(UInt<3>(0h4), remapindex_27) when _T_5205 : connect remapVecData[27], Queue16_UInt8_4.io.deq.bits connect remapVecValids[27], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_5206 = eq(UInt<3>(0h5), remapindex_27) when _T_5206 : connect remapVecData[27], Queue16_UInt8_5.io.deq.bits connect remapVecValids[27], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_5207 = eq(UInt<3>(0h6), remapindex_27) when _T_5207 : connect remapVecData[27], Queue16_UInt8_6.io.deq.bits connect remapVecValids[27], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_5208 = eq(UInt<3>(0h7), remapindex_27) when _T_5208 : connect remapVecData[27], Queue16_UInt8_7.io.deq.bits connect remapVecValids[27], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_5209 = eq(UInt<4>(0h8), remapindex_27) when _T_5209 : connect remapVecData[27], Queue16_UInt8_8.io.deq.bits connect remapVecValids[27], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_5210 = eq(UInt<4>(0h9), remapindex_27) when _T_5210 : connect remapVecData[27], Queue16_UInt8_9.io.deq.bits connect remapVecValids[27], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_5211 = eq(UInt<4>(0ha), remapindex_27) when _T_5211 : connect remapVecData[27], Queue16_UInt8_10.io.deq.bits connect remapVecValids[27], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_5212 = eq(UInt<4>(0hb), remapindex_27) when _T_5212 : connect remapVecData[27], Queue16_UInt8_11.io.deq.bits connect remapVecValids[27], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_5213 = eq(UInt<4>(0hc), remapindex_27) when _T_5213 : connect remapVecData[27], Queue16_UInt8_12.io.deq.bits connect remapVecValids[27], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_5214 = eq(UInt<4>(0hd), remapindex_27) when _T_5214 : connect remapVecData[27], Queue16_UInt8_13.io.deq.bits connect remapVecValids[27], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_5215 = eq(UInt<4>(0he), remapindex_27) when _T_5215 : connect remapVecData[27], Queue16_UInt8_14.io.deq.bits connect remapVecValids[27], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_5216 = eq(UInt<4>(0hf), remapindex_27) when _T_5216 : connect remapVecData[27], Queue16_UInt8_15.io.deq.bits connect remapVecValids[27], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_5217 = eq(UInt<5>(0h10), remapindex_27) when _T_5217 : connect remapVecData[27], Queue16_UInt8_16.io.deq.bits connect remapVecValids[27], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_5218 = eq(UInt<5>(0h11), remapindex_27) when _T_5218 : connect remapVecData[27], Queue16_UInt8_17.io.deq.bits connect remapVecValids[27], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_5219 = eq(UInt<5>(0h12), remapindex_27) when _T_5219 : connect remapVecData[27], Queue16_UInt8_18.io.deq.bits connect remapVecValids[27], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_5220 = eq(UInt<5>(0h13), remapindex_27) when _T_5220 : connect remapVecData[27], Queue16_UInt8_19.io.deq.bits connect remapVecValids[27], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_5221 = eq(UInt<5>(0h14), remapindex_27) when _T_5221 : connect remapVecData[27], Queue16_UInt8_20.io.deq.bits connect remapVecValids[27], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_5222 = eq(UInt<5>(0h15), remapindex_27) when _T_5222 : connect remapVecData[27], Queue16_UInt8_21.io.deq.bits connect remapVecValids[27], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_5223 = eq(UInt<5>(0h16), remapindex_27) when _T_5223 : connect remapVecData[27], Queue16_UInt8_22.io.deq.bits connect remapVecValids[27], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_5224 = eq(UInt<5>(0h17), remapindex_27) when _T_5224 : connect remapVecData[27], Queue16_UInt8_23.io.deq.bits connect remapVecValids[27], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_5225 = eq(UInt<5>(0h18), remapindex_27) when _T_5225 : connect remapVecData[27], Queue16_UInt8_24.io.deq.bits connect remapVecValids[27], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_5226 = eq(UInt<5>(0h19), remapindex_27) when _T_5226 : connect remapVecData[27], Queue16_UInt8_25.io.deq.bits connect remapVecValids[27], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_5227 = eq(UInt<5>(0h1a), remapindex_27) when _T_5227 : connect remapVecData[27], Queue16_UInt8_26.io.deq.bits connect remapVecValids[27], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_5228 = eq(UInt<5>(0h1b), remapindex_27) when _T_5228 : connect remapVecData[27], Queue16_UInt8_27.io.deq.bits connect remapVecValids[27], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_5229 = eq(UInt<5>(0h1c), remapindex_27) when _T_5229 : connect remapVecData[27], Queue16_UInt8_28.io.deq.bits connect remapVecValids[27], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_5230 = eq(UInt<5>(0h1d), remapindex_27) when _T_5230 : connect remapVecData[27], Queue16_UInt8_29.io.deq.bits connect remapVecValids[27], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_5231 = eq(UInt<5>(0h1e), remapindex_27) when _T_5231 : connect remapVecData[27], Queue16_UInt8_30.io.deq.bits connect remapVecValids[27], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_5232 = eq(UInt<5>(0h1f), remapindex_27) when _T_5232 : connect remapVecData[27], Queue16_UInt8_31.io.deq.bits connect remapVecValids[27], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_5233 = eq(UInt<1>(0h0), remapindex_28) when _T_5233 : connect remapVecData[28], Queue16_UInt8.io.deq.bits connect remapVecValids[28], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[28] node _T_5234 = eq(UInt<1>(0h1), remapindex_28) when _T_5234 : connect remapVecData[28], Queue16_UInt8_1.io.deq.bits connect remapVecValids[28], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_5235 = eq(UInt<2>(0h2), remapindex_28) when _T_5235 : connect remapVecData[28], Queue16_UInt8_2.io.deq.bits connect remapVecValids[28], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_5236 = eq(UInt<2>(0h3), remapindex_28) when _T_5236 : connect remapVecData[28], Queue16_UInt8_3.io.deq.bits connect remapVecValids[28], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_5237 = eq(UInt<3>(0h4), remapindex_28) when _T_5237 : connect remapVecData[28], Queue16_UInt8_4.io.deq.bits connect remapVecValids[28], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_5238 = eq(UInt<3>(0h5), remapindex_28) when _T_5238 : connect remapVecData[28], Queue16_UInt8_5.io.deq.bits connect remapVecValids[28], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_5239 = eq(UInt<3>(0h6), remapindex_28) when _T_5239 : connect remapVecData[28], Queue16_UInt8_6.io.deq.bits connect remapVecValids[28], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_5240 = eq(UInt<3>(0h7), remapindex_28) when _T_5240 : connect remapVecData[28], Queue16_UInt8_7.io.deq.bits connect remapVecValids[28], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_5241 = eq(UInt<4>(0h8), remapindex_28) when _T_5241 : connect remapVecData[28], Queue16_UInt8_8.io.deq.bits connect remapVecValids[28], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_5242 = eq(UInt<4>(0h9), remapindex_28) when _T_5242 : connect remapVecData[28], Queue16_UInt8_9.io.deq.bits connect remapVecValids[28], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_5243 = eq(UInt<4>(0ha), remapindex_28) when _T_5243 : connect remapVecData[28], Queue16_UInt8_10.io.deq.bits connect remapVecValids[28], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_5244 = eq(UInt<4>(0hb), remapindex_28) when _T_5244 : connect remapVecData[28], Queue16_UInt8_11.io.deq.bits connect remapVecValids[28], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_5245 = eq(UInt<4>(0hc), remapindex_28) when _T_5245 : connect remapVecData[28], Queue16_UInt8_12.io.deq.bits connect remapVecValids[28], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_5246 = eq(UInt<4>(0hd), remapindex_28) when _T_5246 : connect remapVecData[28], Queue16_UInt8_13.io.deq.bits connect remapVecValids[28], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_5247 = eq(UInt<4>(0he), remapindex_28) when _T_5247 : connect remapVecData[28], Queue16_UInt8_14.io.deq.bits connect remapVecValids[28], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_5248 = eq(UInt<4>(0hf), remapindex_28) when _T_5248 : connect remapVecData[28], Queue16_UInt8_15.io.deq.bits connect remapVecValids[28], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_5249 = eq(UInt<5>(0h10), remapindex_28) when _T_5249 : connect remapVecData[28], Queue16_UInt8_16.io.deq.bits connect remapVecValids[28], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_5250 = eq(UInt<5>(0h11), remapindex_28) when _T_5250 : connect remapVecData[28], Queue16_UInt8_17.io.deq.bits connect remapVecValids[28], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_5251 = eq(UInt<5>(0h12), remapindex_28) when _T_5251 : connect remapVecData[28], Queue16_UInt8_18.io.deq.bits connect remapVecValids[28], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_5252 = eq(UInt<5>(0h13), remapindex_28) when _T_5252 : connect remapVecData[28], Queue16_UInt8_19.io.deq.bits connect remapVecValids[28], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_5253 = eq(UInt<5>(0h14), remapindex_28) when _T_5253 : connect remapVecData[28], Queue16_UInt8_20.io.deq.bits connect remapVecValids[28], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_5254 = eq(UInt<5>(0h15), remapindex_28) when _T_5254 : connect remapVecData[28], Queue16_UInt8_21.io.deq.bits connect remapVecValids[28], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_5255 = eq(UInt<5>(0h16), remapindex_28) when _T_5255 : connect remapVecData[28], Queue16_UInt8_22.io.deq.bits connect remapVecValids[28], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_5256 = eq(UInt<5>(0h17), remapindex_28) when _T_5256 : connect remapVecData[28], Queue16_UInt8_23.io.deq.bits connect remapVecValids[28], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_5257 = eq(UInt<5>(0h18), remapindex_28) when _T_5257 : connect remapVecData[28], Queue16_UInt8_24.io.deq.bits connect remapVecValids[28], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_5258 = eq(UInt<5>(0h19), remapindex_28) when _T_5258 : connect remapVecData[28], Queue16_UInt8_25.io.deq.bits connect remapVecValids[28], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_5259 = eq(UInt<5>(0h1a), remapindex_28) when _T_5259 : connect remapVecData[28], Queue16_UInt8_26.io.deq.bits connect remapVecValids[28], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_5260 = eq(UInt<5>(0h1b), remapindex_28) when _T_5260 : connect remapVecData[28], Queue16_UInt8_27.io.deq.bits connect remapVecValids[28], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_5261 = eq(UInt<5>(0h1c), remapindex_28) when _T_5261 : connect remapVecData[28], Queue16_UInt8_28.io.deq.bits connect remapVecValids[28], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_5262 = eq(UInt<5>(0h1d), remapindex_28) when _T_5262 : connect remapVecData[28], Queue16_UInt8_29.io.deq.bits connect remapVecValids[28], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_5263 = eq(UInt<5>(0h1e), remapindex_28) when _T_5263 : connect remapVecData[28], Queue16_UInt8_30.io.deq.bits connect remapVecValids[28], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_5264 = eq(UInt<5>(0h1f), remapindex_28) when _T_5264 : connect remapVecData[28], Queue16_UInt8_31.io.deq.bits connect remapVecValids[28], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_5265 = eq(UInt<1>(0h0), remapindex_29) when _T_5265 : connect remapVecData[29], Queue16_UInt8.io.deq.bits connect remapVecValids[29], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[29] node _T_5266 = eq(UInt<1>(0h1), remapindex_29) when _T_5266 : connect remapVecData[29], Queue16_UInt8_1.io.deq.bits connect remapVecValids[29], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_5267 = eq(UInt<2>(0h2), remapindex_29) when _T_5267 : connect remapVecData[29], Queue16_UInt8_2.io.deq.bits connect remapVecValids[29], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_5268 = eq(UInt<2>(0h3), remapindex_29) when _T_5268 : connect remapVecData[29], Queue16_UInt8_3.io.deq.bits connect remapVecValids[29], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_5269 = eq(UInt<3>(0h4), remapindex_29) when _T_5269 : connect remapVecData[29], Queue16_UInt8_4.io.deq.bits connect remapVecValids[29], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_5270 = eq(UInt<3>(0h5), remapindex_29) when _T_5270 : connect remapVecData[29], Queue16_UInt8_5.io.deq.bits connect remapVecValids[29], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_5271 = eq(UInt<3>(0h6), remapindex_29) when _T_5271 : connect remapVecData[29], Queue16_UInt8_6.io.deq.bits connect remapVecValids[29], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_5272 = eq(UInt<3>(0h7), remapindex_29) when _T_5272 : connect remapVecData[29], Queue16_UInt8_7.io.deq.bits connect remapVecValids[29], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_5273 = eq(UInt<4>(0h8), remapindex_29) when _T_5273 : connect remapVecData[29], Queue16_UInt8_8.io.deq.bits connect remapVecValids[29], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_5274 = eq(UInt<4>(0h9), remapindex_29) when _T_5274 : connect remapVecData[29], Queue16_UInt8_9.io.deq.bits connect remapVecValids[29], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_5275 = eq(UInt<4>(0ha), remapindex_29) when _T_5275 : connect remapVecData[29], Queue16_UInt8_10.io.deq.bits connect remapVecValids[29], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_5276 = eq(UInt<4>(0hb), remapindex_29) when _T_5276 : connect remapVecData[29], Queue16_UInt8_11.io.deq.bits connect remapVecValids[29], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_5277 = eq(UInt<4>(0hc), remapindex_29) when _T_5277 : connect remapVecData[29], Queue16_UInt8_12.io.deq.bits connect remapVecValids[29], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_5278 = eq(UInt<4>(0hd), remapindex_29) when _T_5278 : connect remapVecData[29], Queue16_UInt8_13.io.deq.bits connect remapVecValids[29], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_5279 = eq(UInt<4>(0he), remapindex_29) when _T_5279 : connect remapVecData[29], Queue16_UInt8_14.io.deq.bits connect remapVecValids[29], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_5280 = eq(UInt<4>(0hf), remapindex_29) when _T_5280 : connect remapVecData[29], Queue16_UInt8_15.io.deq.bits connect remapVecValids[29], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_5281 = eq(UInt<5>(0h10), remapindex_29) when _T_5281 : connect remapVecData[29], Queue16_UInt8_16.io.deq.bits connect remapVecValids[29], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_5282 = eq(UInt<5>(0h11), remapindex_29) when _T_5282 : connect remapVecData[29], Queue16_UInt8_17.io.deq.bits connect remapVecValids[29], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_5283 = eq(UInt<5>(0h12), remapindex_29) when _T_5283 : connect remapVecData[29], Queue16_UInt8_18.io.deq.bits connect remapVecValids[29], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_5284 = eq(UInt<5>(0h13), remapindex_29) when _T_5284 : connect remapVecData[29], Queue16_UInt8_19.io.deq.bits connect remapVecValids[29], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_5285 = eq(UInt<5>(0h14), remapindex_29) when _T_5285 : connect remapVecData[29], Queue16_UInt8_20.io.deq.bits connect remapVecValids[29], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_5286 = eq(UInt<5>(0h15), remapindex_29) when _T_5286 : connect remapVecData[29], Queue16_UInt8_21.io.deq.bits connect remapVecValids[29], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_5287 = eq(UInt<5>(0h16), remapindex_29) when _T_5287 : connect remapVecData[29], Queue16_UInt8_22.io.deq.bits connect remapVecValids[29], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_5288 = eq(UInt<5>(0h17), remapindex_29) when _T_5288 : connect remapVecData[29], Queue16_UInt8_23.io.deq.bits connect remapVecValids[29], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_5289 = eq(UInt<5>(0h18), remapindex_29) when _T_5289 : connect remapVecData[29], Queue16_UInt8_24.io.deq.bits connect remapVecValids[29], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_5290 = eq(UInt<5>(0h19), remapindex_29) when _T_5290 : connect remapVecData[29], Queue16_UInt8_25.io.deq.bits connect remapVecValids[29], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_5291 = eq(UInt<5>(0h1a), remapindex_29) when _T_5291 : connect remapVecData[29], Queue16_UInt8_26.io.deq.bits connect remapVecValids[29], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_5292 = eq(UInt<5>(0h1b), remapindex_29) when _T_5292 : connect remapVecData[29], Queue16_UInt8_27.io.deq.bits connect remapVecValids[29], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_5293 = eq(UInt<5>(0h1c), remapindex_29) when _T_5293 : connect remapVecData[29], Queue16_UInt8_28.io.deq.bits connect remapVecValids[29], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_5294 = eq(UInt<5>(0h1d), remapindex_29) when _T_5294 : connect remapVecData[29], Queue16_UInt8_29.io.deq.bits connect remapVecValids[29], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_5295 = eq(UInt<5>(0h1e), remapindex_29) when _T_5295 : connect remapVecData[29], Queue16_UInt8_30.io.deq.bits connect remapVecValids[29], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_5296 = eq(UInt<5>(0h1f), remapindex_29) when _T_5296 : connect remapVecData[29], Queue16_UInt8_31.io.deq.bits connect remapVecValids[29], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_5297 = eq(UInt<1>(0h0), remapindex_30) when _T_5297 : connect remapVecData[30], Queue16_UInt8.io.deq.bits connect remapVecValids[30], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[30] node _T_5298 = eq(UInt<1>(0h1), remapindex_30) when _T_5298 : connect remapVecData[30], Queue16_UInt8_1.io.deq.bits connect remapVecValids[30], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_5299 = eq(UInt<2>(0h2), remapindex_30) when _T_5299 : connect remapVecData[30], Queue16_UInt8_2.io.deq.bits connect remapVecValids[30], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_5300 = eq(UInt<2>(0h3), remapindex_30) when _T_5300 : connect remapVecData[30], Queue16_UInt8_3.io.deq.bits connect remapVecValids[30], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_5301 = eq(UInt<3>(0h4), remapindex_30) when _T_5301 : connect remapVecData[30], Queue16_UInt8_4.io.deq.bits connect remapVecValids[30], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_5302 = eq(UInt<3>(0h5), remapindex_30) when _T_5302 : connect remapVecData[30], Queue16_UInt8_5.io.deq.bits connect remapVecValids[30], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_5303 = eq(UInt<3>(0h6), remapindex_30) when _T_5303 : connect remapVecData[30], Queue16_UInt8_6.io.deq.bits connect remapVecValids[30], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_5304 = eq(UInt<3>(0h7), remapindex_30) when _T_5304 : connect remapVecData[30], Queue16_UInt8_7.io.deq.bits connect remapVecValids[30], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_5305 = eq(UInt<4>(0h8), remapindex_30) when _T_5305 : connect remapVecData[30], Queue16_UInt8_8.io.deq.bits connect remapVecValids[30], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_5306 = eq(UInt<4>(0h9), remapindex_30) when _T_5306 : connect remapVecData[30], Queue16_UInt8_9.io.deq.bits connect remapVecValids[30], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_5307 = eq(UInt<4>(0ha), remapindex_30) when _T_5307 : connect remapVecData[30], Queue16_UInt8_10.io.deq.bits connect remapVecValids[30], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_5308 = eq(UInt<4>(0hb), remapindex_30) when _T_5308 : connect remapVecData[30], Queue16_UInt8_11.io.deq.bits connect remapVecValids[30], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_5309 = eq(UInt<4>(0hc), remapindex_30) when _T_5309 : connect remapVecData[30], Queue16_UInt8_12.io.deq.bits connect remapVecValids[30], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_5310 = eq(UInt<4>(0hd), remapindex_30) when _T_5310 : connect remapVecData[30], Queue16_UInt8_13.io.deq.bits connect remapVecValids[30], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_5311 = eq(UInt<4>(0he), remapindex_30) when _T_5311 : connect remapVecData[30], Queue16_UInt8_14.io.deq.bits connect remapVecValids[30], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_5312 = eq(UInt<4>(0hf), remapindex_30) when _T_5312 : connect remapVecData[30], Queue16_UInt8_15.io.deq.bits connect remapVecValids[30], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_5313 = eq(UInt<5>(0h10), remapindex_30) when _T_5313 : connect remapVecData[30], Queue16_UInt8_16.io.deq.bits connect remapVecValids[30], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_5314 = eq(UInt<5>(0h11), remapindex_30) when _T_5314 : connect remapVecData[30], Queue16_UInt8_17.io.deq.bits connect remapVecValids[30], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_5315 = eq(UInt<5>(0h12), remapindex_30) when _T_5315 : connect remapVecData[30], Queue16_UInt8_18.io.deq.bits connect remapVecValids[30], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_5316 = eq(UInt<5>(0h13), remapindex_30) when _T_5316 : connect remapVecData[30], Queue16_UInt8_19.io.deq.bits connect remapVecValids[30], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_5317 = eq(UInt<5>(0h14), remapindex_30) when _T_5317 : connect remapVecData[30], Queue16_UInt8_20.io.deq.bits connect remapVecValids[30], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_5318 = eq(UInt<5>(0h15), remapindex_30) when _T_5318 : connect remapVecData[30], Queue16_UInt8_21.io.deq.bits connect remapVecValids[30], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_5319 = eq(UInt<5>(0h16), remapindex_30) when _T_5319 : connect remapVecData[30], Queue16_UInt8_22.io.deq.bits connect remapVecValids[30], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_5320 = eq(UInt<5>(0h17), remapindex_30) when _T_5320 : connect remapVecData[30], Queue16_UInt8_23.io.deq.bits connect remapVecValids[30], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_5321 = eq(UInt<5>(0h18), remapindex_30) when _T_5321 : connect remapVecData[30], Queue16_UInt8_24.io.deq.bits connect remapVecValids[30], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_5322 = eq(UInt<5>(0h19), remapindex_30) when _T_5322 : connect remapVecData[30], Queue16_UInt8_25.io.deq.bits connect remapVecValids[30], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_5323 = eq(UInt<5>(0h1a), remapindex_30) when _T_5323 : connect remapVecData[30], Queue16_UInt8_26.io.deq.bits connect remapVecValids[30], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_5324 = eq(UInt<5>(0h1b), remapindex_30) when _T_5324 : connect remapVecData[30], Queue16_UInt8_27.io.deq.bits connect remapVecValids[30], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_5325 = eq(UInt<5>(0h1c), remapindex_30) when _T_5325 : connect remapVecData[30], Queue16_UInt8_28.io.deq.bits connect remapVecValids[30], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_5326 = eq(UInt<5>(0h1d), remapindex_30) when _T_5326 : connect remapVecData[30], Queue16_UInt8_29.io.deq.bits connect remapVecValids[30], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_5327 = eq(UInt<5>(0h1e), remapindex_30) when _T_5327 : connect remapVecData[30], Queue16_UInt8_30.io.deq.bits connect remapVecValids[30], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_5328 = eq(UInt<5>(0h1f), remapindex_30) when _T_5328 : connect remapVecData[30], Queue16_UInt8_31.io.deq.bits connect remapVecValids[30], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_5329 = eq(UInt<1>(0h0), remapindex_31) when _T_5329 : connect remapVecData[31], Queue16_UInt8.io.deq.bits connect remapVecValids[31], Queue16_UInt8.io.deq.valid connect Queue16_UInt8.io.deq.ready, remapVecReadys[31] node _T_5330 = eq(UInt<1>(0h1), remapindex_31) when _T_5330 : connect remapVecData[31], Queue16_UInt8_1.io.deq.bits connect remapVecValids[31], Queue16_UInt8_1.io.deq.valid connect Queue16_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_5331 = eq(UInt<2>(0h2), remapindex_31) when _T_5331 : connect remapVecData[31], Queue16_UInt8_2.io.deq.bits connect remapVecValids[31], Queue16_UInt8_2.io.deq.valid connect Queue16_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_5332 = eq(UInt<2>(0h3), remapindex_31) when _T_5332 : connect remapVecData[31], Queue16_UInt8_3.io.deq.bits connect remapVecValids[31], Queue16_UInt8_3.io.deq.valid connect Queue16_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_5333 = eq(UInt<3>(0h4), remapindex_31) when _T_5333 : connect remapVecData[31], Queue16_UInt8_4.io.deq.bits connect remapVecValids[31], Queue16_UInt8_4.io.deq.valid connect Queue16_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_5334 = eq(UInt<3>(0h5), remapindex_31) when _T_5334 : connect remapVecData[31], Queue16_UInt8_5.io.deq.bits connect remapVecValids[31], Queue16_UInt8_5.io.deq.valid connect Queue16_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_5335 = eq(UInt<3>(0h6), remapindex_31) when _T_5335 : connect remapVecData[31], Queue16_UInt8_6.io.deq.bits connect remapVecValids[31], Queue16_UInt8_6.io.deq.valid connect Queue16_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_5336 = eq(UInt<3>(0h7), remapindex_31) when _T_5336 : connect remapVecData[31], Queue16_UInt8_7.io.deq.bits connect remapVecValids[31], Queue16_UInt8_7.io.deq.valid connect Queue16_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_5337 = eq(UInt<4>(0h8), remapindex_31) when _T_5337 : connect remapVecData[31], Queue16_UInt8_8.io.deq.bits connect remapVecValids[31], Queue16_UInt8_8.io.deq.valid connect Queue16_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_5338 = eq(UInt<4>(0h9), remapindex_31) when _T_5338 : connect remapVecData[31], Queue16_UInt8_9.io.deq.bits connect remapVecValids[31], Queue16_UInt8_9.io.deq.valid connect Queue16_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_5339 = eq(UInt<4>(0ha), remapindex_31) when _T_5339 : connect remapVecData[31], Queue16_UInt8_10.io.deq.bits connect remapVecValids[31], Queue16_UInt8_10.io.deq.valid connect Queue16_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_5340 = eq(UInt<4>(0hb), remapindex_31) when _T_5340 : connect remapVecData[31], Queue16_UInt8_11.io.deq.bits connect remapVecValids[31], Queue16_UInt8_11.io.deq.valid connect Queue16_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_5341 = eq(UInt<4>(0hc), remapindex_31) when _T_5341 : connect remapVecData[31], Queue16_UInt8_12.io.deq.bits connect remapVecValids[31], Queue16_UInt8_12.io.deq.valid connect Queue16_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_5342 = eq(UInt<4>(0hd), remapindex_31) when _T_5342 : connect remapVecData[31], Queue16_UInt8_13.io.deq.bits connect remapVecValids[31], Queue16_UInt8_13.io.deq.valid connect Queue16_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_5343 = eq(UInt<4>(0he), remapindex_31) when _T_5343 : connect remapVecData[31], Queue16_UInt8_14.io.deq.bits connect remapVecValids[31], Queue16_UInt8_14.io.deq.valid connect Queue16_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_5344 = eq(UInt<4>(0hf), remapindex_31) when _T_5344 : connect remapVecData[31], Queue16_UInt8_15.io.deq.bits connect remapVecValids[31], Queue16_UInt8_15.io.deq.valid connect Queue16_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_5345 = eq(UInt<5>(0h10), remapindex_31) when _T_5345 : connect remapVecData[31], Queue16_UInt8_16.io.deq.bits connect remapVecValids[31], Queue16_UInt8_16.io.deq.valid connect Queue16_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_5346 = eq(UInt<5>(0h11), remapindex_31) when _T_5346 : connect remapVecData[31], Queue16_UInt8_17.io.deq.bits connect remapVecValids[31], Queue16_UInt8_17.io.deq.valid connect Queue16_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_5347 = eq(UInt<5>(0h12), remapindex_31) when _T_5347 : connect remapVecData[31], Queue16_UInt8_18.io.deq.bits connect remapVecValids[31], Queue16_UInt8_18.io.deq.valid connect Queue16_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_5348 = eq(UInt<5>(0h13), remapindex_31) when _T_5348 : connect remapVecData[31], Queue16_UInt8_19.io.deq.bits connect remapVecValids[31], Queue16_UInt8_19.io.deq.valid connect Queue16_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_5349 = eq(UInt<5>(0h14), remapindex_31) when _T_5349 : connect remapVecData[31], Queue16_UInt8_20.io.deq.bits connect remapVecValids[31], Queue16_UInt8_20.io.deq.valid connect Queue16_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_5350 = eq(UInt<5>(0h15), remapindex_31) when _T_5350 : connect remapVecData[31], Queue16_UInt8_21.io.deq.bits connect remapVecValids[31], Queue16_UInt8_21.io.deq.valid connect Queue16_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_5351 = eq(UInt<5>(0h16), remapindex_31) when _T_5351 : connect remapVecData[31], Queue16_UInt8_22.io.deq.bits connect remapVecValids[31], Queue16_UInt8_22.io.deq.valid connect Queue16_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_5352 = eq(UInt<5>(0h17), remapindex_31) when _T_5352 : connect remapVecData[31], Queue16_UInt8_23.io.deq.bits connect remapVecValids[31], Queue16_UInt8_23.io.deq.valid connect Queue16_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_5353 = eq(UInt<5>(0h18), remapindex_31) when _T_5353 : connect remapVecData[31], Queue16_UInt8_24.io.deq.bits connect remapVecValids[31], Queue16_UInt8_24.io.deq.valid connect Queue16_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_5354 = eq(UInt<5>(0h19), remapindex_31) when _T_5354 : connect remapVecData[31], Queue16_UInt8_25.io.deq.bits connect remapVecValids[31], Queue16_UInt8_25.io.deq.valid connect Queue16_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_5355 = eq(UInt<5>(0h1a), remapindex_31) when _T_5355 : connect remapVecData[31], Queue16_UInt8_26.io.deq.bits connect remapVecValids[31], Queue16_UInt8_26.io.deq.valid connect Queue16_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_5356 = eq(UInt<5>(0h1b), remapindex_31) when _T_5356 : connect remapVecData[31], Queue16_UInt8_27.io.deq.bits connect remapVecValids[31], Queue16_UInt8_27.io.deq.valid connect Queue16_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_5357 = eq(UInt<5>(0h1c), remapindex_31) when _T_5357 : connect remapVecData[31], Queue16_UInt8_28.io.deq.bits connect remapVecValids[31], Queue16_UInt8_28.io.deq.valid connect Queue16_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_5358 = eq(UInt<5>(0h1d), remapindex_31) when _T_5358 : connect remapVecData[31], Queue16_UInt8_29.io.deq.bits connect remapVecValids[31], Queue16_UInt8_29.io.deq.valid connect Queue16_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_5359 = eq(UInt<5>(0h1e), remapindex_31) when _T_5359 : connect remapVecData[31], Queue16_UInt8_30.io.deq.bits connect remapVecValids[31], Queue16_UInt8_30.io.deq.valid connect Queue16_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_5360 = eq(UInt<5>(0h1f), remapindex_31) when _T_5360 : connect remapVecData[31], Queue16_UInt8_31.io.deq.bits connect remapVecValids[31], Queue16_UInt8_31.io.deq.valid connect Queue16_UInt8_31.io.deq.ready, remapVecReadys[31] node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) regreset backend_bytes_written : UInt<64>, clock, reset, UInt<64>(0h0) node _backend_next_write_addr_T = add(decompress_dest_info_Q.io.deq.bits.op, backend_bytes_written) node backend_next_write_addr = tail(_backend_next_write_addr_T, 1) node _throttle_end_T = sub(buf_lens_Q.io.deq.bits, backend_bytes_written) node _throttle_end_T_1 = tail(_throttle_end_T, 1) node throttle_end = mux(buf_lens_Q.io.deq.valid, _throttle_end_T_1, UInt<6>(0h20)) node _throttle_end_writeable_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_T_6 = mux(_throttle_end_writeable_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _throttle_end_writeable_T_7 = mux(_throttle_end_writeable_T_4, UInt<2>(0h2), _throttle_end_writeable_T_6) node _throttle_end_writeable_T_8 = mux(_throttle_end_writeable_T_3, UInt<3>(0h4), _throttle_end_writeable_T_7) node _throttle_end_writeable_T_9 = mux(_throttle_end_writeable_T_2, UInt<4>(0h8), _throttle_end_writeable_T_8) node _throttle_end_writeable_T_10 = mux(_throttle_end_writeable_T_1, UInt<5>(0h10), _throttle_end_writeable_T_9) node throttle_end_writeable = mux(_throttle_end_writeable_T, UInt<6>(0h20), _throttle_end_writeable_T_10) node _throttle_end_writeable_log2_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_log2_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_log2_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_log2_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_log2_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_log2_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_log2_T_6 = mux(_throttle_end_writeable_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _throttle_end_writeable_log2_T_7 = mux(_throttle_end_writeable_log2_T_4, UInt<1>(0h1), _throttle_end_writeable_log2_T_6) node _throttle_end_writeable_log2_T_8 = mux(_throttle_end_writeable_log2_T_3, UInt<2>(0h2), _throttle_end_writeable_log2_T_7) node _throttle_end_writeable_log2_T_9 = mux(_throttle_end_writeable_log2_T_2, UInt<2>(0h3), _throttle_end_writeable_log2_T_8) node _throttle_end_writeable_log2_T_10 = mux(_throttle_end_writeable_log2_T_1, UInt<3>(0h4), _throttle_end_writeable_log2_T_9) node throttle_end_writeable_log2 = mux(_throttle_end_writeable_log2_T, UInt<3>(0h5), _throttle_end_writeable_log2_T_10) node _ptr_align_max_bytes_writeable_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_T_5 = mux(_ptr_align_max_bytes_writeable_T_4, UInt<5>(0h10), UInt<6>(0h20)) node _ptr_align_max_bytes_writeable_T_6 = mux(_ptr_align_max_bytes_writeable_T_3, UInt<4>(0h8), _ptr_align_max_bytes_writeable_T_5) node _ptr_align_max_bytes_writeable_T_7 = mux(_ptr_align_max_bytes_writeable_T_2, UInt<3>(0h4), _ptr_align_max_bytes_writeable_T_6) node _ptr_align_max_bytes_writeable_T_8 = mux(_ptr_align_max_bytes_writeable_T_1, UInt<2>(0h2), _ptr_align_max_bytes_writeable_T_7) node ptr_align_max_bytes_writeable = mux(_ptr_align_max_bytes_writeable_T, UInt<1>(0h1), _ptr_align_max_bytes_writeable_T_8) node _ptr_align_max_bytes_writeable_log2_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_log2_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_log2_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_log2_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_log2_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_log2_T_5 = mux(_ptr_align_max_bytes_writeable_log2_T_4, UInt<3>(0h4), UInt<3>(0h5)) node _ptr_align_max_bytes_writeable_log2_T_6 = mux(_ptr_align_max_bytes_writeable_log2_T_3, UInt<2>(0h3), _ptr_align_max_bytes_writeable_log2_T_5) node _ptr_align_max_bytes_writeable_log2_T_7 = mux(_ptr_align_max_bytes_writeable_log2_T_2, UInt<2>(0h2), _ptr_align_max_bytes_writeable_log2_T_6) node _ptr_align_max_bytes_writeable_log2_T_8 = mux(_ptr_align_max_bytes_writeable_log2_T_1, UInt<1>(0h1), _ptr_align_max_bytes_writeable_log2_T_7) node ptr_align_max_bytes_writeable_log2 = mux(_ptr_align_max_bytes_writeable_log2_T, UInt<1>(0h0), _ptr_align_max_bytes_writeable_log2_T_8) node _count_valids_largest_aligned_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_T_6 = mux(_count_valids_largest_aligned_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _count_valids_largest_aligned_T_7 = mux(_count_valids_largest_aligned_T_4, UInt<2>(0h2), _count_valids_largest_aligned_T_6) node _count_valids_largest_aligned_T_8 = mux(_count_valids_largest_aligned_T_3, UInt<3>(0h4), _count_valids_largest_aligned_T_7) node _count_valids_largest_aligned_T_9 = mux(_count_valids_largest_aligned_T_2, UInt<4>(0h8), _count_valids_largest_aligned_T_8) node _count_valids_largest_aligned_T_10 = mux(_count_valids_largest_aligned_T_1, UInt<5>(0h10), _count_valids_largest_aligned_T_9) node count_valids_largest_aligned = mux(_count_valids_largest_aligned_T, UInt<6>(0h20), _count_valids_largest_aligned_T_10) node _count_valids_largest_aligned_log2_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_log2_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_log2_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_log2_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_log2_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_log2_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_log2_T_6 = mux(_count_valids_largest_aligned_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _count_valids_largest_aligned_log2_T_7 = mux(_count_valids_largest_aligned_log2_T_4, UInt<1>(0h1), _count_valids_largest_aligned_log2_T_6) node _count_valids_largest_aligned_log2_T_8 = mux(_count_valids_largest_aligned_log2_T_3, UInt<2>(0h2), _count_valids_largest_aligned_log2_T_7) node _count_valids_largest_aligned_log2_T_9 = mux(_count_valids_largest_aligned_log2_T_2, UInt<2>(0h3), _count_valids_largest_aligned_log2_T_8) node _count_valids_largest_aligned_log2_T_10 = mux(_count_valids_largest_aligned_log2_T_1, UInt<3>(0h4), _count_valids_largest_aligned_log2_T_9) node count_valids_largest_aligned_log2 = mux(_count_valids_largest_aligned_log2_T, UInt<3>(0h5), _count_valids_largest_aligned_log2_T_10) node _bytes_to_write_T = lt(ptr_align_max_bytes_writeable, count_valids_largest_aligned) node _bytes_to_write_T_1 = lt(ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_2 = mux(_bytes_to_write_T_1, ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_3 = lt(count_valids_largest_aligned, throttle_end_writeable) node _bytes_to_write_T_4 = mux(_bytes_to_write_T_3, count_valids_largest_aligned, throttle_end_writeable) node bytes_to_write = mux(_bytes_to_write_T, _bytes_to_write_T_2, _bytes_to_write_T_4) node remapped_write_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node remapped_write_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node remapped_write_data_lo_lo_lo = cat(remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo) node remapped_write_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node remapped_write_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node remapped_write_data_lo_lo_hi = cat(remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo) node remapped_write_data_lo_lo = cat(remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo) node remapped_write_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node remapped_write_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node remapped_write_data_lo_hi_lo = cat(remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo) node remapped_write_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node remapped_write_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node remapped_write_data_lo_hi_hi = cat(remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo) node remapped_write_data_lo_hi = cat(remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo) node remapped_write_data_lo = cat(remapped_write_data_lo_hi, remapped_write_data_lo_lo) node remapped_write_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node remapped_write_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node remapped_write_data_hi_lo_lo = cat(remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo) node remapped_write_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node remapped_write_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node remapped_write_data_hi_lo_hi = cat(remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo) node remapped_write_data_hi_lo = cat(remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo) node remapped_write_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node remapped_write_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node remapped_write_data_hi_hi_lo = cat(remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo) node remapped_write_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node remapped_write_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node remapped_write_data_hi_hi_hi = cat(remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo) node remapped_write_data_hi_hi = cat(remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo) node remapped_write_data_hi = cat(remapped_write_data_hi_hi, remapped_write_data_hi_lo) node remapped_write_data = cat(remapped_write_data_hi, remapped_write_data_lo) node enough_data = neq(bytes_to_write, UInt<1>(0h0)) node _bytes_to_write_log2_T = lt(ptr_align_max_bytes_writeable_log2, count_valids_largest_aligned_log2) node _bytes_to_write_log2_T_1 = lt(ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_2 = mux(_bytes_to_write_log2_T_1, ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_3 = lt(count_valids_largest_aligned_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_4 = mux(_bytes_to_write_log2_T_3, count_valids_largest_aligned_log2, throttle_end_writeable_log2) node bytes_to_write_log2 = mux(_bytes_to_write_log2_T, _bytes_to_write_log2_T_2, _bytes_to_write_log2_T_4) node _write_ptr_override_T = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node write_ptr_override = and(buf_lens_Q.io.deq.valid, _write_ptr_override_T) node _T_5361 = eq(write_ptr_override, UInt<1>(0h0)) node _T_5362 = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node _remapVecReadys_0_T = lt(UInt<1>(0h0), bytes_to_write) node _remapVecReadys_0_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, _T_5361) node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_0_T_4 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_3) connect remapVecReadys[0], _remapVecReadys_0_T_4 node _remapVecReadys_1_T = lt(UInt<1>(0h1), bytes_to_write) node _remapVecReadys_1_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, _T_5361) node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_1_T_4 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_3) connect remapVecReadys[1], _remapVecReadys_1_T_4 node _remapVecReadys_2_T = lt(UInt<2>(0h2), bytes_to_write) node _remapVecReadys_2_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, _T_5361) node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_2_T_4 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_3) connect remapVecReadys[2], _remapVecReadys_2_T_4 node _remapVecReadys_3_T = lt(UInt<2>(0h3), bytes_to_write) node _remapVecReadys_3_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, _T_5361) node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_3_T_4 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_3) connect remapVecReadys[3], _remapVecReadys_3_T_4 node _remapVecReadys_4_T = lt(UInt<3>(0h4), bytes_to_write) node _remapVecReadys_4_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, _T_5361) node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_4_T_4 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_3) connect remapVecReadys[4], _remapVecReadys_4_T_4 node _remapVecReadys_5_T = lt(UInt<3>(0h5), bytes_to_write) node _remapVecReadys_5_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, _T_5361) node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_5_T_4 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_3) connect remapVecReadys[5], _remapVecReadys_5_T_4 node _remapVecReadys_6_T = lt(UInt<3>(0h6), bytes_to_write) node _remapVecReadys_6_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, _T_5361) node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_6_T_4 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_3) connect remapVecReadys[6], _remapVecReadys_6_T_4 node _remapVecReadys_7_T = lt(UInt<3>(0h7), bytes_to_write) node _remapVecReadys_7_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, _T_5361) node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_7_T_4 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_3) connect remapVecReadys[7], _remapVecReadys_7_T_4 node _remapVecReadys_8_T = lt(UInt<4>(0h8), bytes_to_write) node _remapVecReadys_8_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, _T_5361) node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_8_T_4 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_3) connect remapVecReadys[8], _remapVecReadys_8_T_4 node _remapVecReadys_9_T = lt(UInt<4>(0h9), bytes_to_write) node _remapVecReadys_9_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, _T_5361) node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_9_T_4 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_3) connect remapVecReadys[9], _remapVecReadys_9_T_4 node _remapVecReadys_10_T = lt(UInt<4>(0ha), bytes_to_write) node _remapVecReadys_10_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, _T_5361) node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_10_T_4 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_3) connect remapVecReadys[10], _remapVecReadys_10_T_4 node _remapVecReadys_11_T = lt(UInt<4>(0hb), bytes_to_write) node _remapVecReadys_11_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, _T_5361) node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_11_T_4 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_3) connect remapVecReadys[11], _remapVecReadys_11_T_4 node _remapVecReadys_12_T = lt(UInt<4>(0hc), bytes_to_write) node _remapVecReadys_12_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, _T_5361) node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_12_T_4 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_3) connect remapVecReadys[12], _remapVecReadys_12_T_4 node _remapVecReadys_13_T = lt(UInt<4>(0hd), bytes_to_write) node _remapVecReadys_13_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, _T_5361) node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_13_T_4 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_3) connect remapVecReadys[13], _remapVecReadys_13_T_4 node _remapVecReadys_14_T = lt(UInt<4>(0he), bytes_to_write) node _remapVecReadys_14_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, _T_5361) node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_14_T_4 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_3) connect remapVecReadys[14], _remapVecReadys_14_T_4 node _remapVecReadys_15_T = lt(UInt<4>(0hf), bytes_to_write) node _remapVecReadys_15_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, _T_5361) node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_15_T_4 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_3) connect remapVecReadys[15], _remapVecReadys_15_T_4 node _remapVecReadys_16_T = lt(UInt<5>(0h10), bytes_to_write) node _remapVecReadys_16_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, _T_5361) node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_16_T_4 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_3) connect remapVecReadys[16], _remapVecReadys_16_T_4 node _remapVecReadys_17_T = lt(UInt<5>(0h11), bytes_to_write) node _remapVecReadys_17_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, _T_5361) node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_17_T_4 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_3) connect remapVecReadys[17], _remapVecReadys_17_T_4 node _remapVecReadys_18_T = lt(UInt<5>(0h12), bytes_to_write) node _remapVecReadys_18_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, _T_5361) node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_18_T_4 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_3) connect remapVecReadys[18], _remapVecReadys_18_T_4 node _remapVecReadys_19_T = lt(UInt<5>(0h13), bytes_to_write) node _remapVecReadys_19_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, _T_5361) node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_19_T_4 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_3) connect remapVecReadys[19], _remapVecReadys_19_T_4 node _remapVecReadys_20_T = lt(UInt<5>(0h14), bytes_to_write) node _remapVecReadys_20_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, _T_5361) node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_20_T_4 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_3) connect remapVecReadys[20], _remapVecReadys_20_T_4 node _remapVecReadys_21_T = lt(UInt<5>(0h15), bytes_to_write) node _remapVecReadys_21_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, _T_5361) node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_21_T_4 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_3) connect remapVecReadys[21], _remapVecReadys_21_T_4 node _remapVecReadys_22_T = lt(UInt<5>(0h16), bytes_to_write) node _remapVecReadys_22_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, _T_5361) node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_22_T_4 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_3) connect remapVecReadys[22], _remapVecReadys_22_T_4 node _remapVecReadys_23_T = lt(UInt<5>(0h17), bytes_to_write) node _remapVecReadys_23_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, _T_5361) node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_23_T_4 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_3) connect remapVecReadys[23], _remapVecReadys_23_T_4 node _remapVecReadys_24_T = lt(UInt<5>(0h18), bytes_to_write) node _remapVecReadys_24_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, _T_5361) node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_24_T_4 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_3) connect remapVecReadys[24], _remapVecReadys_24_T_4 node _remapVecReadys_25_T = lt(UInt<5>(0h19), bytes_to_write) node _remapVecReadys_25_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, _T_5361) node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_25_T_4 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_3) connect remapVecReadys[25], _remapVecReadys_25_T_4 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), bytes_to_write) node _remapVecReadys_26_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, _T_5361) node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_26_T_4 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_3) connect remapVecReadys[26], _remapVecReadys_26_T_4 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), bytes_to_write) node _remapVecReadys_27_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, _T_5361) node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_27_T_4 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_3) connect remapVecReadys[27], _remapVecReadys_27_T_4 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), bytes_to_write) node _remapVecReadys_28_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, _T_5361) node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_28_T_4 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_3) connect remapVecReadys[28], _remapVecReadys_28_T_4 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), bytes_to_write) node _remapVecReadys_29_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, _T_5361) node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_29_T_4 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_3) connect remapVecReadys[29], _remapVecReadys_29_T_4 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), bytes_to_write) node _remapVecReadys_30_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, _T_5361) node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_30_T_4 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_3) connect remapVecReadys[30], _remapVecReadys_30_T_4 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), bytes_to_write) node _remapVecReadys_31_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, _T_5361) node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T_2, decompress_dest_info_Q.io.deq.valid) node _remapVecReadys_31_T_4 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_3) connect remapVecReadys[31], _remapVecReadys_31_T_4 node _T_5363 = and(io.l2io.req.ready, enough_data) node _T_5364 = and(_T_5363, _T_5361) node _T_5365 = and(_T_5364, decompress_dest_info_Q.io.deq.valid) when _T_5365 : node _read_start_index_T = add(read_start_index, bytes_to_write) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1 node _backend_bytes_written_T = add(backend_bytes_written, bytes_to_write) node _backend_bytes_written_T_1 = tail(_backend_bytes_written_T, 1) connect backend_bytes_written, _backend_bytes_written_T_1 regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_5366 = asUInt(reset) node _T_5367 = eq(_T_5366, UInt<1>(0h0)) when _T_5367 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70 node _T_5368 = asUInt(reset) node _T_5369 = eq(_T_5368, UInt<1>(0h0)) when _T_5369 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] writefire: addr: 0x%x, data 0x%x, size %d\n", io.l2io.req.bits.addr, io.l2io.req.bits.data, io.l2io.req.bits.size) : printf_71 node _io_l2io_req_valid_T = and(enough_data, _T_5361) node _io_l2io_req_valid_T_1 = and(_io_l2io_req_valid_T, decompress_dest_info_Q.io.deq.valid) connect io.l2io.req.valid, _io_l2io_req_valid_T_1 node _io_l2io_req_bits_size_T = mux(write_ptr_override, UInt<2>(0h2), bytes_to_write_log2) connect io.l2io.req.bits.size, _io_l2io_req_bits_size_T node _io_l2io_req_bits_addr_T = mux(write_ptr_override, decompress_dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr) connect io.l2io.req.bits.addr, _io_l2io_req_bits_addr_T node _io_l2io_req_bits_data_T = mux(write_ptr_override, buf_lens_Q.io.deq.bits, remapped_write_data) connect io.l2io.req.bits.data, _io_l2io_req_bits_data_T connect io.l2io.req.bits.cmd, UInt<1>(0h1) node _buf_lens_Q_io_deq_ready_T = and(io.l2io.req.ready, _T_5362) node _buf_lens_Q_io_deq_ready_T_1 = and(_buf_lens_Q_io_deq_ready_T, decompress_dest_info_Q.io.deq.valid) connect buf_lens_Q.io.deq.ready, _buf_lens_Q_io_deq_ready_T_1 node _decompress_dest_info_Q_io_deq_ready_T = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _decompress_dest_info_Q_io_deq_ready_T_1 = and(_decompress_dest_info_Q_io_deq_ready_T, _T_5362) connect decompress_dest_info_Q.io.deq.ready, _decompress_dest_info_Q_io_deq_ready_T_1 regreset bufs_completed : UInt<64>, clock, reset, UInt<64>(0h0) connect io.bufs_completed, bufs_completed connect io.l2io.resp.ready, UInt<1>(0h1) connect io.no_writes_inflight, io.l2io.no_memops_inflight node _T_5370 = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _T_5371 = and(_T_5370, _T_5362) node _T_5372 = and(_T_5371, decompress_dest_info_Q.io.deq.valid) when _T_5372 : node _bufs_completed_T = add(bufs_completed, UInt<1>(0h1)) node _bufs_completed_T_1 = tail(_bufs_completed_T, 1) connect bufs_completed, _bufs_completed_T_1 connect backend_bytes_written, UInt<1>(0h0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_5373 = asUInt(reset) node _T_5374 = eq(_T_5373, UInt<1>(0h0)) when _T_5374 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72 node _T_5375 = asUInt(reset) node _T_5376 = eq(_T_5375, UInt<1>(0h0)) when _T_5376 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] write cmpflag addr: 0x%x, final_bytes_written: %d\n", decompress_dest_info_Q.io.deq.bits.cmpflag, buf_lens_Q.io.deq.bits) : printf_73 node _T_5377 = neq(count_valids, UInt<1>(0h0)) when _T_5377 : node _T_5378 = eq(write_ptr_override, UInt<1>(0h0)) regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_5379 = asUInt(reset) node _T_5380 = eq(_T_5379, UInt<1>(0h0)) when _T_5380 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74 node _T_5381 = asUInt(reset) node _T_5382 = eq(_T_5381, UInt<1>(0h0)) when _T_5382 : printf(clock, UInt<1>(0h1), "[lit-comp-memwr] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d, l2io.req.ready: %d, enough_data: %d, write_ptr_override: %d, decompress_dest_info_Q.io.deq.valid: %d\n", read_start_index, backend_bytes_written, count_valids, ptr_align_max_bytes_writeable, bytes_to_write, bytes_to_write_log2, io.l2io.req.ready, enough_data, _T_5378, decompress_dest_info_Q.io.deq.valid) : printf_75

module EntropyCompressorMemwriter_2( // @[EntropyCompressorMemWriter.scala:21:7] input clock, // @[EntropyCompressorMemWriter.scala:21:7] input reset, // @[EntropyCompressorMemWriter.scala:21:7] output io_memwrites_in_ready, // @[EntropyCompressorMemWriter.scala:24:14] input io_memwrites_in_valid, // @[EntropyCompressorMemWriter.scala:24:14] input [255:0] io_memwrites_in_bits_data, // @[EntropyCompressorMemWriter.scala:24:14] input [5:0] io_memwrites_in_bits_validbytes, // @[EntropyCompressorMemWriter.scala:24:14] input io_memwrites_in_bits_end_of_message, // @[EntropyCompressorMemWriter.scala:24:14] input io_l2io_req_ready, // @[EntropyCompressorMemWriter.scala:24:14] output io_l2io_req_valid, // @[EntropyCompressorMemWriter.scala:24:14] output [63:0] io_l2io_req_bits_addr, // @[EntropyCompressorMemWriter.scala:24:14] output [2:0] io_l2io_req_bits_size, // @[EntropyCompressorMemWriter.scala:24:14] output [255:0] io_l2io_req_bits_data, // @[EntropyCompressorMemWriter.scala:24:14] input io_l2io_resp_valid, // @[EntropyCompressorMemWriter.scala:24:14] input [255:0] io_l2io_resp_bits_data, // @[EntropyCompressorMemWriter.scala:24:14] input io_l2io_no_memops_inflight, // @[EntropyCompressorMemWriter.scala:24:14] output io_decompress_dest_info_ready, // @[EntropyCompressorMemWriter.scala:24:14] input io_decompress_dest_info_valid, // @[EntropyCompressorMemWriter.scala:24:14] input [63:0] io_decompress_dest_info_bits_op, // @[EntropyCompressorMemWriter.scala:24:14] input [63:0] io_decompress_dest_info_bits_cmpflag // @[EntropyCompressorMemWriter.scala:24:14] ); wire _Queue16_UInt8_31_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_31_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_31_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_30_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_30_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_30_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_29_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_29_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_29_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_28_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_28_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_28_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_27_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_27_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_27_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_26_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_26_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_26_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_25_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_25_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_25_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_24_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_24_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_24_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_23_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_23_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_23_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_22_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_22_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_22_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_21_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_21_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_21_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_20_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_20_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_20_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_19_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_19_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_19_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_18_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_18_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_18_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_17_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_17_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_17_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_16_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_16_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_16_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_15_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_15_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_15_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_14_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_14_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_14_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_13_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_13_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_13_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_12_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_12_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_12_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_11_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_11_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_11_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_10_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_10_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_10_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_9_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_9_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_9_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_8_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_8_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_7_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_7_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_7_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_6_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_6_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_6_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_5_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_5_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_5_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_4_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_4_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_4_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_3_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_3_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_3_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_2_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_2_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_2_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_1_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_1_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_1_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52] wire _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52] wire [7:0] _Queue16_UInt8_io_deq_bits; // @[EntropyCompressorMemWriter.scala:75:52] wire _buf_lens_Q_io_enq_ready; // @[EntropyCompressorMemWriter.scala:50:26] wire _buf_lens_Q_io_deq_valid; // @[EntropyCompressorMemWriter.scala:50:26] wire [63:0] _buf_lens_Q_io_deq_bits; // @[EntropyCompressorMemWriter.scala:50:26] wire _decompress_dest_info_Q_io_deq_valid; // @[EntropyCompressorMemWriter.scala:37:38] wire [63:0] _decompress_dest_info_Q_io_deq_bits_op; // @[EntropyCompressorMemWriter.scala:37:38] wire [63:0] _decompress_dest_info_Q_io_deq_bits_cmpflag; // @[EntropyCompressorMemWriter.scala:37:38] wire _incoming_writes_Q_io_deq_valid; // @[EntropyCompressorMemWriter.scala:33:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[EntropyCompressorMemWriter.scala:33:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[EntropyCompressorMemWriter.scala:33:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[EntropyCompressorMemWriter.scala:33:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[EntropyCompressorMemWriter.scala:21:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[EntropyCompressorMemWriter.scala:21:7] wire [5:0] io_memwrites_in_bits_validbytes_0 = io_memwrites_in_bits_validbytes; // @[EntropyCompressorMemWriter.scala:21:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[EntropyCompressorMemWriter.scala:21:7] wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[EntropyCompressorMemWriter.scala:21:7] wire io_decompress_dest_info_valid_0 = io_decompress_dest_info_valid; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_decompress_dest_info_bits_op_0 = io_decompress_dest_info_bits_op; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_decompress_dest_info_bits_cmpflag_0 = io_decompress_dest_info_bits_cmpflag; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_req_bits_cmd = 1'h1; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_resp_ready = 1'h1; // @[EntropyCompressorMemWriter.scala:21:7] wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[EntropyCompressorMemWriter.scala:182:50] wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[EntropyCompressorMemWriter.scala:213:56] wire _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] wire [63:0] _io_l2io_req_bits_addr_T; // @[EntropyCompressorMemWriter.scala:280:31] wire [2:0] _io_l2io_req_bits_size_T; // @[EntropyCompressorMemWriter.scala:279:31] wire [255:0] _io_l2io_req_bits_data_T; // @[EntropyCompressorMemWriter.scala:281:31] wire io_no_writes_inflight = io_l2io_no_memops_inflight_0; // @[EntropyCompressorMemWriter.scala:21:7] wire io_memwrites_in_ready_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_l2io_req_bits_addr_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [2:0] io_l2io_req_bits_size_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [255:0] io_l2io_req_bits_data_0; // @[EntropyCompressorMemWriter.scala:21:7] wire io_l2io_req_valid_0; // @[EntropyCompressorMemWriter.scala:21:7] wire io_decompress_dest_info_ready_0; // @[EntropyCompressorMemWriter.scala:21:7] wire [63:0] io_bufs_completed; // @[EntropyCompressorMemWriter.scala:21:7] wire _decompress_dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53] wire _decompress_dest_last_fire_T = _decompress_dest_info_Q_io_deq_ready_T_1 & _decompress_dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35] reg decompress_dest_last_fire; // @[EntropyCompressorMemWriter.scala:40:42] reg decompress_dest_last_valid; // @[EntropyCompressorMemWriter.scala:41:43] wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[EntropyCompressorMemWriter.scala:41:43, :42:105] wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire | _decompress_dest_printhelp_T; // @[EntropyCompressorMemWriter.scala:40:42, :42:{101,105}] wire decompress_dest_printhelp = _decompress_dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[EntropyCompressorMemWriter.scala:37:38, :42:{71,101}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] buf_len_tracker; // @[EntropyCompressorMemWriter.scala:55:32] wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53] wire _T_10 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35] wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[EntropyCompressorMemWriter.scala:33:33, :55:32, :60:42] wire [64:0] _buf_len_tracker_T; // @[EntropyCompressorMemWriter.scala:60:42] assign _buf_len_tracker_T = _GEN; // @[EntropyCompressorMemWriter.scala:60:42] wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[EntropyCompressorMemWriter.scala:110:45] assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[EntropyCompressorMemWriter.scala:60:42, :110:45] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[EntropyCompressorMemWriter.scala:74:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[EntropyCompressorMemWriter.scala:74:34, :84:34] wire [6:0] _GEN_0 = _idx_T % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx = _GEN_0[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_1 = _idx_T_1 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_1 = _GEN_1[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_2 = _idx_T_2 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_2 = _GEN_2[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_3 = _idx_T_3 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_3 = _GEN_3[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_4 = _idx_T_4 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_4 = _GEN_4[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_5 = _idx_T_5 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_5 = _GEN_5[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_6 = _idx_T_6 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_6 = _GEN_6[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_7 = _idx_T_7 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_7 = _GEN_7[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_8 = _idx_T_8 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_8 = _GEN_8[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_9 = _idx_T_9 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_9 = _GEN_9[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_10 = _idx_T_10 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_10 = _GEN_10[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_11 = _idx_T_11 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_11 = _GEN_11[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_12 = _idx_T_12 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_12 = _GEN_12[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_13 = _idx_T_13 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_13 = _GEN_13[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_14 = _idx_T_14 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_14 = _GEN_14[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_15 = _idx_T_15 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_15 = _GEN_15[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_16 = _idx_T_16 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_16 = _GEN_16[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_17 = _idx_T_17 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_17 = _GEN_17[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_18 = _idx_T_18 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_18 = _GEN_18[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_19 = _idx_T_19 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_19 = _GEN_19[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_20 = _idx_T_20 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_20 = _GEN_20[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_21 = _idx_T_21 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_21 = _GEN_21[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_22 = _idx_T_22 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_22 = _GEN_22[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_23 = _idx_T_23 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_23 = _GEN_23[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_24 = _idx_T_24 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_24 = _GEN_24[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_25 = _idx_T_25 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_25 = _GEN_25[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_26 = _idx_T_26 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_26 = _GEN_26[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_27 = _idx_T_27 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_27 = _GEN_27[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_28 = _idx_T_28 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_28 = _GEN_28[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_29 = _idx_T_29 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_29 = _GEN_29[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_30 = _idx_T_30 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_30 = _GEN_30[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[EntropyCompressorMemWriter.scala:84:34] wire [6:0] _GEN_31 = _idx_T_31 % 7'h20; // @[EntropyCompressorMemWriter.scala:84:{34,48}] wire [5:0] idx_31 = _GEN_31[5:0]; // @[EntropyCompressorMemWriter.scala:84:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[EntropyCompressorMemWriter.scala:33:33, :84:34, :93:47] wire [6:0] _GEN_32 = wrap_len_index_wide % 7'h20; // @[EntropyCompressorMemWriter.scala:93:47, :94:48] wire [5:0] wrap_len_index_end = _GEN_32[5:0]; // @[EntropyCompressorMemWriter.scala:94:48] wire wrapped = |(wrap_len_index_wide[6:5]); // @[EntropyCompressorMemWriter.scala:93:47, :95:37] wire _all_queues_ready_T = _Queue16_UInt8_io_enq_ready & _Queue16_UInt8_1_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue16_UInt8_2_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue16_UInt8_3_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue16_UInt8_4_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue16_UInt8_5_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue16_UInt8_6_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue16_UInt8_7_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue16_UInt8_8_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue16_UInt8_9_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue16_UInt8_10_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue16_UInt8_11_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue16_UInt8_12_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue16_UInt8_13_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue16_UInt8_14_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue16_UInt8_15_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue16_UInt8_16_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue16_UInt8_17_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue16_UInt8_18_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue16_UInt8_19_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue16_UInt8_20_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue16_UInt8_21_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue16_UInt8_22_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue16_UInt8_23_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue16_UInt8_24_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue16_UInt8_25_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue16_UInt8_26_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue16_UInt8_27_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue16_UInt8_28_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue16_UInt8_29_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue16_UInt8_30_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue16_UInt8_31_io_enq_ready; // @[EntropyCompressorMemWriter.scala:75:52, :97:68] wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[EntropyCompressorMemWriter.scala:33:33, :101:33] wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[EntropyCompressorMemWriter.scala:33:33, :50:26, :101:61] wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T | _account_for_buf_lens_Q_T_1; // @[EntropyCompressorMemWriter.scala:101:{33,46,61}] wire _buf_lens_Q_io_enq_valid_T = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53] assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53] wire _GEN_33 = write_start_index == 6'h0; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T = _GEN_33; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_3; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_3 = _GEN_33; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_1 = |wrap_len_index_end; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_4 = |wrap_len_index_end; // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_34 = write_start_index < 6'h2; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_6; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_6 = _GEN_34; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_9; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_9 = _GEN_34; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_35 = write_start_index < 6'h3; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_12; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_12 = _GEN_35; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_15; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_15 = _GEN_35; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_36 = wrap_len_index_end > 6'h2; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_13; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_13 = _GEN_36; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_16; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_16 = _GEN_36; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_37 = write_start_index < 6'h4; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_18; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_18 = _GEN_37; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_21; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_21 = _GEN_37; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_38 = write_start_index < 6'h5; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_24; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_24 = _GEN_38; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_27; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_27 = _GEN_38; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_39 = wrap_len_index_end > 6'h4; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_25; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_25 = _GEN_39; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_28; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_28 = _GEN_39; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_40 = write_start_index < 6'h6; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_30; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_30 = _GEN_40; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_33; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_33 = _GEN_40; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_41 = wrap_len_index_end > 6'h5; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_31; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_31 = _GEN_41; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_34; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_34 = _GEN_41; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_42 = write_start_index < 6'h7; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_36; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_36 = _GEN_42; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_39; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_39 = _GEN_42; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_43 = wrap_len_index_end > 6'h6; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_37; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_37 = _GEN_43; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_40; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_40 = _GEN_43; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_44 = write_start_index < 6'h8; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_42; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_42 = _GEN_44; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_45; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_45 = _GEN_44; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_45 = write_start_index < 6'h9; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_48; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_48 = _GEN_45; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_51; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_51 = _GEN_45; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_46 = wrap_len_index_end > 6'h8; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_49; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_49 = _GEN_46; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_52; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_52 = _GEN_46; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_47 = write_start_index < 6'hA; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_54; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_54 = _GEN_47; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_57; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_57 = _GEN_47; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_48 = wrap_len_index_end > 6'h9; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_55; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_55 = _GEN_48; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_58; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_58 = _GEN_48; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_49 = write_start_index < 6'hB; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_60; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_60 = _GEN_49; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_63; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_63 = _GEN_49; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_50 = wrap_len_index_end > 6'hA; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_61; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_61 = _GEN_50; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_64; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_64 = _GEN_50; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_51 = write_start_index < 6'hC; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_66; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_66 = _GEN_51; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_69; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_69 = _GEN_51; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_52 = wrap_len_index_end > 6'hB; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_67; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_67 = _GEN_52; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_70; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_70 = _GEN_52; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_53 = write_start_index < 6'hD; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_72; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_72 = _GEN_53; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_75; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_75 = _GEN_53; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_54 = wrap_len_index_end > 6'hC; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_73; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_73 = _GEN_54; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_76; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_76 = _GEN_54; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_55 = write_start_index < 6'hE; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_78; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_78 = _GEN_55; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_81; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_81 = _GEN_55; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_56 = wrap_len_index_end > 6'hD; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_79; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_79 = _GEN_56; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_82; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_82 = _GEN_56; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_57 = write_start_index < 6'hF; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_84; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_84 = _GEN_57; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_87; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_87 = _GEN_57; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_58 = wrap_len_index_end > 6'hE; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_85; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_85 = _GEN_58; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_88; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_88 = _GEN_58; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_59 = write_start_index < 6'h10; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_90; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_90 = _GEN_59; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_93; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_93 = _GEN_59; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_60 = write_start_index < 6'h11; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_96; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_96 = _GEN_60; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_99; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_99 = _GEN_60; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_61 = wrap_len_index_end > 6'h10; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_97; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_97 = _GEN_61; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_100; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_100 = _GEN_61; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_62 = write_start_index < 6'h12; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_102; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_102 = _GEN_62; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_105; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_105 = _GEN_62; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_63 = wrap_len_index_end > 6'h11; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_103; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_103 = _GEN_63; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_106; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_106 = _GEN_63; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_64 = write_start_index < 6'h13; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_108; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_108 = _GEN_64; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_111; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_111 = _GEN_64; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_65 = wrap_len_index_end > 6'h12; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_109; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_109 = _GEN_65; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_112; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_112 = _GEN_65; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_66 = write_start_index < 6'h14; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_114; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_114 = _GEN_66; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_117; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_117 = _GEN_66; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_67 = wrap_len_index_end > 6'h13; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_115; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_115 = _GEN_67; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_118; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_118 = _GEN_67; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_68 = write_start_index < 6'h15; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_120; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_120 = _GEN_68; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_123; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_123 = _GEN_68; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_69 = wrap_len_index_end > 6'h14; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_121; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_121 = _GEN_69; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_124; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_124 = _GEN_69; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_70 = write_start_index < 6'h16; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_126; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_126 = _GEN_70; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_129; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_129 = _GEN_70; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_71 = wrap_len_index_end > 6'h15; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_127; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_127 = _GEN_71; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_130; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_130 = _GEN_71; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_72 = write_start_index < 6'h17; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_132; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_132 = _GEN_72; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_135; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_135 = _GEN_72; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_73 = wrap_len_index_end > 6'h16; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_133; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_133 = _GEN_73; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_136; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_136 = _GEN_73; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_74 = write_start_index < 6'h18; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_138; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_138 = _GEN_74; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_141; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_141 = _GEN_74; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_75 = wrap_len_index_end > 6'h17; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_139; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_139 = _GEN_75; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_142; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_142 = _GEN_75; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_76 = write_start_index < 6'h19; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_144; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_144 = _GEN_76; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_147; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_147 = _GEN_76; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_77 = wrap_len_index_end > 6'h18; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_145; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_145 = _GEN_77; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_148; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_148 = _GEN_77; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_78 = write_start_index < 6'h1A; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_150; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_150 = _GEN_78; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_153; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_153 = _GEN_78; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_79 = wrap_len_index_end > 6'h19; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_151; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_151 = _GEN_79; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_154; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_154 = _GEN_79; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_80 = write_start_index < 6'h1B; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_156; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_156 = _GEN_80; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_159; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_159 = _GEN_80; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_81 = wrap_len_index_end > 6'h1A; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_157; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_157 = _GEN_81; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_160; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_160 = _GEN_81; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_82 = write_start_index < 6'h1C; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_162; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_162 = _GEN_82; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_165; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_165 = _GEN_82; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_83 = wrap_len_index_end > 6'h1B; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_163; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_163 = _GEN_83; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_166; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_166 = _GEN_83; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_84 = write_start_index < 6'h1D; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_168; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_168 = _GEN_84; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_171; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_171 = _GEN_84; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_85 = wrap_len_index_end > 6'h1C; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_169; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_169 = _GEN_85; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_172; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_172 = _GEN_85; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_86 = write_start_index < 6'h1E; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_174; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_174 = _GEN_86; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_177; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_177 = _GEN_86; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_87 = wrap_len_index_end > 6'h1D; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_175; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_175 = _GEN_87; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_178; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_178 = _GEN_87; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _GEN_88 = write_start_index < 6'h1F; // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_180; // @[EntropyCompressorMemWriter.scala:121:41] assign _use_this_queue_T_180 = _GEN_88; // @[EntropyCompressorMemWriter.scala:121:41] wire _use_this_queue_T_183; // @[EntropyCompressorMemWriter.scala:122:41] assign _use_this_queue_T_183 = _GEN_88; // @[EntropyCompressorMemWriter.scala:121:41, :122:41] wire _GEN_89 = wrap_len_index_end > 6'h1E; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_181; // @[EntropyCompressorMemWriter.scala:121:77] assign _use_this_queue_T_181 = _GEN_89; // @[EntropyCompressorMemWriter.scala:121:77] wire _use_this_queue_T_184; // @[EntropyCompressorMemWriter.scala:122:77] assign _use_this_queue_T_184 = _GEN_89; // @[EntropyCompressorMemWriter.scala:121:77, :122:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[EntropyCompressorMemWriter.scala:74:34, :121:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[EntropyCompressorMemWriter.scala:94:48, :121:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[EntropyCompressorMemWriter.scala:94:48, :121:77, :122:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[EntropyCompressorMemWriter.scala:121:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[EntropyCompressorMemWriter.scala:74:34, :121:41, :122:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[EntropyCompressorMemWriter.scala:122:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[EntropyCompressorMemWriter.scala:95:37, :120:29, :121:63, :122:63] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[EntropyCompressorMemWriter.scala:134:33] wire [7:0] remapVecData_0; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_1; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_2; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_3; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_4; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_5; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_6; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_7; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_8; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_9; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_10; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_11; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_12; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_13; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_14; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_15; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_16; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_17; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_18; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_19; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_20; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_21; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_22; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_23; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_24; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_25; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_26; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_27; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_28; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_29; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_30; // @[EntropyCompressorMemWriter.scala:136:26] wire [7:0] remapVecData_31; // @[EntropyCompressorMemWriter.scala:136:26] wire remapVecValids_0; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_1; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_2; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_3; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_4; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_5; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_6; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_7; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_8; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_9; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_10; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_11; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_12; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_13; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_14; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_15; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_16; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_17; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_18; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_19; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_20; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_21; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_22; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_23; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_24; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_25; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_26; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_27; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_28; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_29; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_30; // @[EntropyCompressorMemWriter.scala:137:28] wire remapVecValids_31; // @[EntropyCompressorMemWriter.scala:137:28] wire _remapVecReadys_0_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_1_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_2_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_3_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_4_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_5_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_6_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_7_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_8_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_9_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_10_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_11_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_12_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_13_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_14_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_15_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_16_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_17_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_18_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_19_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_20_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_21_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_22_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_23_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_24_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_25_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_26_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_27_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_28_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_29_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_30_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire _remapVecReadys_31_T_4; // @[EntropyCompressorMemWriter.scala:259:61] wire remapVecReadys_0; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_1; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_2; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_3; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_4; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_5; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_6; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_7; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_8; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_9; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_10; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_11; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_12; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_13; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_14; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_15; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_16; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_17; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_18; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_19; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_20; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_21; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_22; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_23; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_24; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_25; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_26; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_27; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_28; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_29; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_30; // @[EntropyCompressorMemWriter.scala:138:28] wire remapVecReadys_31; // @[EntropyCompressorMemWriter.scala:138:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[EntropyCompressorMemWriter.scala:134:33, :148:33] wire [6:0] _GEN_90 = _remapindex_T % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex = _GEN_90[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4337 = remapindex == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4338 = remapindex == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4339 = remapindex == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4340 = remapindex == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4341 = remapindex == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4342 = remapindex == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4343 = remapindex == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4344 = remapindex == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4345 = remapindex == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4346 = remapindex == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4347 = remapindex == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4348 = remapindex == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4349 = remapindex == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4350 = remapindex == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4351 = remapindex == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4352 = remapindex == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4353 = remapindex == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4354 = remapindex == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4355 = remapindex == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4356 = remapindex == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4357 = remapindex == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4358 = remapindex == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4359 = remapindex == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4360 = remapindex == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4361 = remapindex == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4362 = remapindex == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4363 = remapindex == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4364 = remapindex == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4365 = remapindex == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4366 = remapindex == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4367 = remapindex == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4368 = remapindex == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_bits : _T_4367 ? _Queue16_UInt8_30_io_deq_bits : _T_4366 ? _Queue16_UInt8_29_io_deq_bits : _T_4365 ? _Queue16_UInt8_28_io_deq_bits : _T_4364 ? _Queue16_UInt8_27_io_deq_bits : _T_4363 ? _Queue16_UInt8_26_io_deq_bits : _T_4362 ? _Queue16_UInt8_25_io_deq_bits : _T_4361 ? _Queue16_UInt8_24_io_deq_bits : _T_4360 ? _Queue16_UInt8_23_io_deq_bits : _T_4359 ? _Queue16_UInt8_22_io_deq_bits : _T_4358 ? _Queue16_UInt8_21_io_deq_bits : _T_4357 ? _Queue16_UInt8_20_io_deq_bits : _T_4356 ? _Queue16_UInt8_19_io_deq_bits : _T_4355 ? _Queue16_UInt8_18_io_deq_bits : _T_4354 ? _Queue16_UInt8_17_io_deq_bits : _T_4353 ? _Queue16_UInt8_16_io_deq_bits : _T_4352 ? _Queue16_UInt8_15_io_deq_bits : _T_4351 ? _Queue16_UInt8_14_io_deq_bits : _T_4350 ? _Queue16_UInt8_13_io_deq_bits : _T_4349 ? _Queue16_UInt8_12_io_deq_bits : _T_4348 ? _Queue16_UInt8_11_io_deq_bits : _T_4347 ? _Queue16_UInt8_10_io_deq_bits : _T_4346 ? _Queue16_UInt8_9_io_deq_bits : _T_4345 ? _Queue16_UInt8_8_io_deq_bits : _T_4344 ? _Queue16_UInt8_7_io_deq_bits : _T_4343 ? _Queue16_UInt8_6_io_deq_bits : _T_4342 ? _Queue16_UInt8_5_io_deq_bits : _T_4341 ? _Queue16_UInt8_4_io_deq_bits : _T_4340 ? _Queue16_UInt8_3_io_deq_bits : _T_4339 ? _Queue16_UInt8_2_io_deq_bits : _T_4338 ? _Queue16_UInt8_1_io_deq_bits : _T_4337 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_valid : _T_4367 ? _Queue16_UInt8_30_io_deq_valid : _T_4366 ? _Queue16_UInt8_29_io_deq_valid : _T_4365 ? _Queue16_UInt8_28_io_deq_valid : _T_4364 ? _Queue16_UInt8_27_io_deq_valid : _T_4363 ? _Queue16_UInt8_26_io_deq_valid : _T_4362 ? _Queue16_UInt8_25_io_deq_valid : _T_4361 ? _Queue16_UInt8_24_io_deq_valid : _T_4360 ? _Queue16_UInt8_23_io_deq_valid : _T_4359 ? _Queue16_UInt8_22_io_deq_valid : _T_4358 ? _Queue16_UInt8_21_io_deq_valid : _T_4357 ? _Queue16_UInt8_20_io_deq_valid : _T_4356 ? _Queue16_UInt8_19_io_deq_valid : _T_4355 ? _Queue16_UInt8_18_io_deq_valid : _T_4354 ? _Queue16_UInt8_17_io_deq_valid : _T_4353 ? _Queue16_UInt8_16_io_deq_valid : _T_4352 ? _Queue16_UInt8_15_io_deq_valid : _T_4351 ? _Queue16_UInt8_14_io_deq_valid : _T_4350 ? _Queue16_UInt8_13_io_deq_valid : _T_4349 ? _Queue16_UInt8_12_io_deq_valid : _T_4348 ? _Queue16_UInt8_11_io_deq_valid : _T_4347 ? _Queue16_UInt8_10_io_deq_valid : _T_4346 ? _Queue16_UInt8_9_io_deq_valid : _T_4345 ? _Queue16_UInt8_8_io_deq_valid : _T_4344 ? _Queue16_UInt8_7_io_deq_valid : _T_4343 ? _Queue16_UInt8_6_io_deq_valid : _T_4342 ? _Queue16_UInt8_5_io_deq_valid : _T_4341 ? _Queue16_UInt8_4_io_deq_valid : _T_4340 ? _Queue16_UInt8_3_io_deq_valid : _T_4339 ? _Queue16_UInt8_2_io_deq_valid : _T_4338 ? _Queue16_UInt8_1_io_deq_valid : _T_4337 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_91 = _remapindex_T_1 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_1 = _GEN_91[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4369 = remapindex_1 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4370 = remapindex_1 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4371 = remapindex_1 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4372 = remapindex_1 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4373 = remapindex_1 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4374 = remapindex_1 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4375 = remapindex_1 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4376 = remapindex_1 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4377 = remapindex_1 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4378 = remapindex_1 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4379 = remapindex_1 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4380 = remapindex_1 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4381 = remapindex_1 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4382 = remapindex_1 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4383 = remapindex_1 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4384 = remapindex_1 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4385 = remapindex_1 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4386 = remapindex_1 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4387 = remapindex_1 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4388 = remapindex_1 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4389 = remapindex_1 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4390 = remapindex_1 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4391 = remapindex_1 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4392 = remapindex_1 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4393 = remapindex_1 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4394 = remapindex_1 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4395 = remapindex_1 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4396 = remapindex_1 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4397 = remapindex_1 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4398 = remapindex_1 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4399 = remapindex_1 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4400 = remapindex_1 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_bits : _T_4399 ? _Queue16_UInt8_30_io_deq_bits : _T_4398 ? _Queue16_UInt8_29_io_deq_bits : _T_4397 ? _Queue16_UInt8_28_io_deq_bits : _T_4396 ? _Queue16_UInt8_27_io_deq_bits : _T_4395 ? _Queue16_UInt8_26_io_deq_bits : _T_4394 ? _Queue16_UInt8_25_io_deq_bits : _T_4393 ? _Queue16_UInt8_24_io_deq_bits : _T_4392 ? _Queue16_UInt8_23_io_deq_bits : _T_4391 ? _Queue16_UInt8_22_io_deq_bits : _T_4390 ? _Queue16_UInt8_21_io_deq_bits : _T_4389 ? _Queue16_UInt8_20_io_deq_bits : _T_4388 ? _Queue16_UInt8_19_io_deq_bits : _T_4387 ? _Queue16_UInt8_18_io_deq_bits : _T_4386 ? _Queue16_UInt8_17_io_deq_bits : _T_4385 ? _Queue16_UInt8_16_io_deq_bits : _T_4384 ? _Queue16_UInt8_15_io_deq_bits : _T_4383 ? _Queue16_UInt8_14_io_deq_bits : _T_4382 ? _Queue16_UInt8_13_io_deq_bits : _T_4381 ? _Queue16_UInt8_12_io_deq_bits : _T_4380 ? _Queue16_UInt8_11_io_deq_bits : _T_4379 ? _Queue16_UInt8_10_io_deq_bits : _T_4378 ? _Queue16_UInt8_9_io_deq_bits : _T_4377 ? _Queue16_UInt8_8_io_deq_bits : _T_4376 ? _Queue16_UInt8_7_io_deq_bits : _T_4375 ? _Queue16_UInt8_6_io_deq_bits : _T_4374 ? _Queue16_UInt8_5_io_deq_bits : _T_4373 ? _Queue16_UInt8_4_io_deq_bits : _T_4372 ? _Queue16_UInt8_3_io_deq_bits : _T_4371 ? _Queue16_UInt8_2_io_deq_bits : _T_4370 ? _Queue16_UInt8_1_io_deq_bits : _T_4369 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_valid : _T_4399 ? _Queue16_UInt8_30_io_deq_valid : _T_4398 ? _Queue16_UInt8_29_io_deq_valid : _T_4397 ? _Queue16_UInt8_28_io_deq_valid : _T_4396 ? _Queue16_UInt8_27_io_deq_valid : _T_4395 ? _Queue16_UInt8_26_io_deq_valid : _T_4394 ? _Queue16_UInt8_25_io_deq_valid : _T_4393 ? _Queue16_UInt8_24_io_deq_valid : _T_4392 ? _Queue16_UInt8_23_io_deq_valid : _T_4391 ? _Queue16_UInt8_22_io_deq_valid : _T_4390 ? _Queue16_UInt8_21_io_deq_valid : _T_4389 ? _Queue16_UInt8_20_io_deq_valid : _T_4388 ? _Queue16_UInt8_19_io_deq_valid : _T_4387 ? _Queue16_UInt8_18_io_deq_valid : _T_4386 ? _Queue16_UInt8_17_io_deq_valid : _T_4385 ? _Queue16_UInt8_16_io_deq_valid : _T_4384 ? _Queue16_UInt8_15_io_deq_valid : _T_4383 ? _Queue16_UInt8_14_io_deq_valid : _T_4382 ? _Queue16_UInt8_13_io_deq_valid : _T_4381 ? _Queue16_UInt8_12_io_deq_valid : _T_4380 ? _Queue16_UInt8_11_io_deq_valid : _T_4379 ? _Queue16_UInt8_10_io_deq_valid : _T_4378 ? _Queue16_UInt8_9_io_deq_valid : _T_4377 ? _Queue16_UInt8_8_io_deq_valid : _T_4376 ? _Queue16_UInt8_7_io_deq_valid : _T_4375 ? _Queue16_UInt8_6_io_deq_valid : _T_4374 ? _Queue16_UInt8_5_io_deq_valid : _T_4373 ? _Queue16_UInt8_4_io_deq_valid : _T_4372 ? _Queue16_UInt8_3_io_deq_valid : _T_4371 ? _Queue16_UInt8_2_io_deq_valid : _T_4370 ? _Queue16_UInt8_1_io_deq_valid : _T_4369 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_92 = _remapindex_T_2 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_2 = _GEN_92[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4401 = remapindex_2 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4402 = remapindex_2 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4403 = remapindex_2 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4404 = remapindex_2 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4405 = remapindex_2 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4406 = remapindex_2 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4407 = remapindex_2 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4408 = remapindex_2 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4409 = remapindex_2 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4410 = remapindex_2 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4411 = remapindex_2 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4412 = remapindex_2 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4413 = remapindex_2 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4414 = remapindex_2 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4415 = remapindex_2 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4416 = remapindex_2 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4417 = remapindex_2 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4418 = remapindex_2 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4419 = remapindex_2 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4420 = remapindex_2 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4421 = remapindex_2 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4422 = remapindex_2 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4423 = remapindex_2 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4424 = remapindex_2 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4425 = remapindex_2 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4426 = remapindex_2 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4427 = remapindex_2 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4428 = remapindex_2 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4429 = remapindex_2 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4430 = remapindex_2 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4431 = remapindex_2 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4432 = remapindex_2 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_bits : _T_4431 ? _Queue16_UInt8_30_io_deq_bits : _T_4430 ? _Queue16_UInt8_29_io_deq_bits : _T_4429 ? _Queue16_UInt8_28_io_deq_bits : _T_4428 ? _Queue16_UInt8_27_io_deq_bits : _T_4427 ? _Queue16_UInt8_26_io_deq_bits : _T_4426 ? _Queue16_UInt8_25_io_deq_bits : _T_4425 ? _Queue16_UInt8_24_io_deq_bits : _T_4424 ? _Queue16_UInt8_23_io_deq_bits : _T_4423 ? _Queue16_UInt8_22_io_deq_bits : _T_4422 ? _Queue16_UInt8_21_io_deq_bits : _T_4421 ? _Queue16_UInt8_20_io_deq_bits : _T_4420 ? _Queue16_UInt8_19_io_deq_bits : _T_4419 ? _Queue16_UInt8_18_io_deq_bits : _T_4418 ? _Queue16_UInt8_17_io_deq_bits : _T_4417 ? _Queue16_UInt8_16_io_deq_bits : _T_4416 ? _Queue16_UInt8_15_io_deq_bits : _T_4415 ? _Queue16_UInt8_14_io_deq_bits : _T_4414 ? _Queue16_UInt8_13_io_deq_bits : _T_4413 ? _Queue16_UInt8_12_io_deq_bits : _T_4412 ? _Queue16_UInt8_11_io_deq_bits : _T_4411 ? _Queue16_UInt8_10_io_deq_bits : _T_4410 ? _Queue16_UInt8_9_io_deq_bits : _T_4409 ? _Queue16_UInt8_8_io_deq_bits : _T_4408 ? _Queue16_UInt8_7_io_deq_bits : _T_4407 ? _Queue16_UInt8_6_io_deq_bits : _T_4406 ? _Queue16_UInt8_5_io_deq_bits : _T_4405 ? _Queue16_UInt8_4_io_deq_bits : _T_4404 ? _Queue16_UInt8_3_io_deq_bits : _T_4403 ? _Queue16_UInt8_2_io_deq_bits : _T_4402 ? _Queue16_UInt8_1_io_deq_bits : _T_4401 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_valid : _T_4431 ? _Queue16_UInt8_30_io_deq_valid : _T_4430 ? _Queue16_UInt8_29_io_deq_valid : _T_4429 ? _Queue16_UInt8_28_io_deq_valid : _T_4428 ? _Queue16_UInt8_27_io_deq_valid : _T_4427 ? _Queue16_UInt8_26_io_deq_valid : _T_4426 ? _Queue16_UInt8_25_io_deq_valid : _T_4425 ? _Queue16_UInt8_24_io_deq_valid : _T_4424 ? _Queue16_UInt8_23_io_deq_valid : _T_4423 ? _Queue16_UInt8_22_io_deq_valid : _T_4422 ? _Queue16_UInt8_21_io_deq_valid : _T_4421 ? _Queue16_UInt8_20_io_deq_valid : _T_4420 ? _Queue16_UInt8_19_io_deq_valid : _T_4419 ? _Queue16_UInt8_18_io_deq_valid : _T_4418 ? _Queue16_UInt8_17_io_deq_valid : _T_4417 ? _Queue16_UInt8_16_io_deq_valid : _T_4416 ? _Queue16_UInt8_15_io_deq_valid : _T_4415 ? _Queue16_UInt8_14_io_deq_valid : _T_4414 ? _Queue16_UInt8_13_io_deq_valid : _T_4413 ? _Queue16_UInt8_12_io_deq_valid : _T_4412 ? _Queue16_UInt8_11_io_deq_valid : _T_4411 ? _Queue16_UInt8_10_io_deq_valid : _T_4410 ? _Queue16_UInt8_9_io_deq_valid : _T_4409 ? _Queue16_UInt8_8_io_deq_valid : _T_4408 ? _Queue16_UInt8_7_io_deq_valid : _T_4407 ? _Queue16_UInt8_6_io_deq_valid : _T_4406 ? _Queue16_UInt8_5_io_deq_valid : _T_4405 ? _Queue16_UInt8_4_io_deq_valid : _T_4404 ? _Queue16_UInt8_3_io_deq_valid : _T_4403 ? _Queue16_UInt8_2_io_deq_valid : _T_4402 ? _Queue16_UInt8_1_io_deq_valid : _T_4401 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_93 = _remapindex_T_3 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_3 = _GEN_93[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4433 = remapindex_3 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4434 = remapindex_3 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4435 = remapindex_3 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4436 = remapindex_3 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4437 = remapindex_3 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4438 = remapindex_3 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4439 = remapindex_3 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4440 = remapindex_3 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4441 = remapindex_3 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4442 = remapindex_3 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4443 = remapindex_3 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4444 = remapindex_3 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4445 = remapindex_3 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4446 = remapindex_3 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4447 = remapindex_3 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4448 = remapindex_3 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4449 = remapindex_3 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4450 = remapindex_3 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4451 = remapindex_3 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4452 = remapindex_3 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4453 = remapindex_3 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4454 = remapindex_3 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4455 = remapindex_3 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4456 = remapindex_3 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4457 = remapindex_3 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4458 = remapindex_3 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4459 = remapindex_3 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4460 = remapindex_3 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4461 = remapindex_3 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4462 = remapindex_3 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4463 = remapindex_3 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4464 = remapindex_3 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_bits : _T_4463 ? _Queue16_UInt8_30_io_deq_bits : _T_4462 ? _Queue16_UInt8_29_io_deq_bits : _T_4461 ? _Queue16_UInt8_28_io_deq_bits : _T_4460 ? _Queue16_UInt8_27_io_deq_bits : _T_4459 ? _Queue16_UInt8_26_io_deq_bits : _T_4458 ? _Queue16_UInt8_25_io_deq_bits : _T_4457 ? _Queue16_UInt8_24_io_deq_bits : _T_4456 ? _Queue16_UInt8_23_io_deq_bits : _T_4455 ? _Queue16_UInt8_22_io_deq_bits : _T_4454 ? _Queue16_UInt8_21_io_deq_bits : _T_4453 ? _Queue16_UInt8_20_io_deq_bits : _T_4452 ? _Queue16_UInt8_19_io_deq_bits : _T_4451 ? _Queue16_UInt8_18_io_deq_bits : _T_4450 ? _Queue16_UInt8_17_io_deq_bits : _T_4449 ? _Queue16_UInt8_16_io_deq_bits : _T_4448 ? _Queue16_UInt8_15_io_deq_bits : _T_4447 ? _Queue16_UInt8_14_io_deq_bits : _T_4446 ? _Queue16_UInt8_13_io_deq_bits : _T_4445 ? _Queue16_UInt8_12_io_deq_bits : _T_4444 ? _Queue16_UInt8_11_io_deq_bits : _T_4443 ? _Queue16_UInt8_10_io_deq_bits : _T_4442 ? _Queue16_UInt8_9_io_deq_bits : _T_4441 ? _Queue16_UInt8_8_io_deq_bits : _T_4440 ? _Queue16_UInt8_7_io_deq_bits : _T_4439 ? _Queue16_UInt8_6_io_deq_bits : _T_4438 ? _Queue16_UInt8_5_io_deq_bits : _T_4437 ? _Queue16_UInt8_4_io_deq_bits : _T_4436 ? _Queue16_UInt8_3_io_deq_bits : _T_4435 ? _Queue16_UInt8_2_io_deq_bits : _T_4434 ? _Queue16_UInt8_1_io_deq_bits : _T_4433 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_valid : _T_4463 ? _Queue16_UInt8_30_io_deq_valid : _T_4462 ? _Queue16_UInt8_29_io_deq_valid : _T_4461 ? _Queue16_UInt8_28_io_deq_valid : _T_4460 ? _Queue16_UInt8_27_io_deq_valid : _T_4459 ? _Queue16_UInt8_26_io_deq_valid : _T_4458 ? _Queue16_UInt8_25_io_deq_valid : _T_4457 ? _Queue16_UInt8_24_io_deq_valid : _T_4456 ? _Queue16_UInt8_23_io_deq_valid : _T_4455 ? _Queue16_UInt8_22_io_deq_valid : _T_4454 ? _Queue16_UInt8_21_io_deq_valid : _T_4453 ? _Queue16_UInt8_20_io_deq_valid : _T_4452 ? _Queue16_UInt8_19_io_deq_valid : _T_4451 ? _Queue16_UInt8_18_io_deq_valid : _T_4450 ? _Queue16_UInt8_17_io_deq_valid : _T_4449 ? _Queue16_UInt8_16_io_deq_valid : _T_4448 ? _Queue16_UInt8_15_io_deq_valid : _T_4447 ? _Queue16_UInt8_14_io_deq_valid : _T_4446 ? _Queue16_UInt8_13_io_deq_valid : _T_4445 ? _Queue16_UInt8_12_io_deq_valid : _T_4444 ? _Queue16_UInt8_11_io_deq_valid : _T_4443 ? _Queue16_UInt8_10_io_deq_valid : _T_4442 ? _Queue16_UInt8_9_io_deq_valid : _T_4441 ? _Queue16_UInt8_8_io_deq_valid : _T_4440 ? _Queue16_UInt8_7_io_deq_valid : _T_4439 ? _Queue16_UInt8_6_io_deq_valid : _T_4438 ? _Queue16_UInt8_5_io_deq_valid : _T_4437 ? _Queue16_UInt8_4_io_deq_valid : _T_4436 ? _Queue16_UInt8_3_io_deq_valid : _T_4435 ? _Queue16_UInt8_2_io_deq_valid : _T_4434 ? _Queue16_UInt8_1_io_deq_valid : _T_4433 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_94 = _remapindex_T_4 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_4 = _GEN_94[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4465 = remapindex_4 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4466 = remapindex_4 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4467 = remapindex_4 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4468 = remapindex_4 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4469 = remapindex_4 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4470 = remapindex_4 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4471 = remapindex_4 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4472 = remapindex_4 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4473 = remapindex_4 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4474 = remapindex_4 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4475 = remapindex_4 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4476 = remapindex_4 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4477 = remapindex_4 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4478 = remapindex_4 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4479 = remapindex_4 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4480 = remapindex_4 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4481 = remapindex_4 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4482 = remapindex_4 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4483 = remapindex_4 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4484 = remapindex_4 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4485 = remapindex_4 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4486 = remapindex_4 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4487 = remapindex_4 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4488 = remapindex_4 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4489 = remapindex_4 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4490 = remapindex_4 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4491 = remapindex_4 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4492 = remapindex_4 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4493 = remapindex_4 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4494 = remapindex_4 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4495 = remapindex_4 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4496 = remapindex_4 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_bits : _T_4495 ? _Queue16_UInt8_30_io_deq_bits : _T_4494 ? _Queue16_UInt8_29_io_deq_bits : _T_4493 ? _Queue16_UInt8_28_io_deq_bits : _T_4492 ? _Queue16_UInt8_27_io_deq_bits : _T_4491 ? _Queue16_UInt8_26_io_deq_bits : _T_4490 ? _Queue16_UInt8_25_io_deq_bits : _T_4489 ? _Queue16_UInt8_24_io_deq_bits : _T_4488 ? _Queue16_UInt8_23_io_deq_bits : _T_4487 ? _Queue16_UInt8_22_io_deq_bits : _T_4486 ? _Queue16_UInt8_21_io_deq_bits : _T_4485 ? _Queue16_UInt8_20_io_deq_bits : _T_4484 ? _Queue16_UInt8_19_io_deq_bits : _T_4483 ? _Queue16_UInt8_18_io_deq_bits : _T_4482 ? _Queue16_UInt8_17_io_deq_bits : _T_4481 ? _Queue16_UInt8_16_io_deq_bits : _T_4480 ? _Queue16_UInt8_15_io_deq_bits : _T_4479 ? _Queue16_UInt8_14_io_deq_bits : _T_4478 ? _Queue16_UInt8_13_io_deq_bits : _T_4477 ? _Queue16_UInt8_12_io_deq_bits : _T_4476 ? _Queue16_UInt8_11_io_deq_bits : _T_4475 ? _Queue16_UInt8_10_io_deq_bits : _T_4474 ? _Queue16_UInt8_9_io_deq_bits : _T_4473 ? _Queue16_UInt8_8_io_deq_bits : _T_4472 ? _Queue16_UInt8_7_io_deq_bits : _T_4471 ? _Queue16_UInt8_6_io_deq_bits : _T_4470 ? _Queue16_UInt8_5_io_deq_bits : _T_4469 ? _Queue16_UInt8_4_io_deq_bits : _T_4468 ? _Queue16_UInt8_3_io_deq_bits : _T_4467 ? _Queue16_UInt8_2_io_deq_bits : _T_4466 ? _Queue16_UInt8_1_io_deq_bits : _T_4465 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_valid : _T_4495 ? _Queue16_UInt8_30_io_deq_valid : _T_4494 ? _Queue16_UInt8_29_io_deq_valid : _T_4493 ? _Queue16_UInt8_28_io_deq_valid : _T_4492 ? _Queue16_UInt8_27_io_deq_valid : _T_4491 ? _Queue16_UInt8_26_io_deq_valid : _T_4490 ? _Queue16_UInt8_25_io_deq_valid : _T_4489 ? _Queue16_UInt8_24_io_deq_valid : _T_4488 ? _Queue16_UInt8_23_io_deq_valid : _T_4487 ? _Queue16_UInt8_22_io_deq_valid : _T_4486 ? _Queue16_UInt8_21_io_deq_valid : _T_4485 ? _Queue16_UInt8_20_io_deq_valid : _T_4484 ? _Queue16_UInt8_19_io_deq_valid : _T_4483 ? _Queue16_UInt8_18_io_deq_valid : _T_4482 ? _Queue16_UInt8_17_io_deq_valid : _T_4481 ? _Queue16_UInt8_16_io_deq_valid : _T_4480 ? _Queue16_UInt8_15_io_deq_valid : _T_4479 ? _Queue16_UInt8_14_io_deq_valid : _T_4478 ? _Queue16_UInt8_13_io_deq_valid : _T_4477 ? _Queue16_UInt8_12_io_deq_valid : _T_4476 ? _Queue16_UInt8_11_io_deq_valid : _T_4475 ? _Queue16_UInt8_10_io_deq_valid : _T_4474 ? _Queue16_UInt8_9_io_deq_valid : _T_4473 ? _Queue16_UInt8_8_io_deq_valid : _T_4472 ? _Queue16_UInt8_7_io_deq_valid : _T_4471 ? _Queue16_UInt8_6_io_deq_valid : _T_4470 ? _Queue16_UInt8_5_io_deq_valid : _T_4469 ? _Queue16_UInt8_4_io_deq_valid : _T_4468 ? _Queue16_UInt8_3_io_deq_valid : _T_4467 ? _Queue16_UInt8_2_io_deq_valid : _T_4466 ? _Queue16_UInt8_1_io_deq_valid : _T_4465 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_95 = _remapindex_T_5 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_5 = _GEN_95[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4497 = remapindex_5 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4498 = remapindex_5 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4499 = remapindex_5 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4500 = remapindex_5 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4501 = remapindex_5 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4502 = remapindex_5 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4503 = remapindex_5 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4504 = remapindex_5 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4505 = remapindex_5 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4506 = remapindex_5 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4507 = remapindex_5 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4508 = remapindex_5 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4509 = remapindex_5 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4510 = remapindex_5 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4511 = remapindex_5 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4512 = remapindex_5 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4513 = remapindex_5 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4514 = remapindex_5 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4515 = remapindex_5 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4516 = remapindex_5 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4517 = remapindex_5 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4518 = remapindex_5 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4519 = remapindex_5 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4520 = remapindex_5 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4521 = remapindex_5 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4522 = remapindex_5 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4523 = remapindex_5 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4524 = remapindex_5 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4525 = remapindex_5 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4526 = remapindex_5 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4527 = remapindex_5 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4528 = remapindex_5 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_bits : _T_4527 ? _Queue16_UInt8_30_io_deq_bits : _T_4526 ? _Queue16_UInt8_29_io_deq_bits : _T_4525 ? _Queue16_UInt8_28_io_deq_bits : _T_4524 ? _Queue16_UInt8_27_io_deq_bits : _T_4523 ? _Queue16_UInt8_26_io_deq_bits : _T_4522 ? _Queue16_UInt8_25_io_deq_bits : _T_4521 ? _Queue16_UInt8_24_io_deq_bits : _T_4520 ? _Queue16_UInt8_23_io_deq_bits : _T_4519 ? _Queue16_UInt8_22_io_deq_bits : _T_4518 ? _Queue16_UInt8_21_io_deq_bits : _T_4517 ? _Queue16_UInt8_20_io_deq_bits : _T_4516 ? _Queue16_UInt8_19_io_deq_bits : _T_4515 ? _Queue16_UInt8_18_io_deq_bits : _T_4514 ? _Queue16_UInt8_17_io_deq_bits : _T_4513 ? _Queue16_UInt8_16_io_deq_bits : _T_4512 ? _Queue16_UInt8_15_io_deq_bits : _T_4511 ? _Queue16_UInt8_14_io_deq_bits : _T_4510 ? _Queue16_UInt8_13_io_deq_bits : _T_4509 ? _Queue16_UInt8_12_io_deq_bits : _T_4508 ? _Queue16_UInt8_11_io_deq_bits : _T_4507 ? _Queue16_UInt8_10_io_deq_bits : _T_4506 ? _Queue16_UInt8_9_io_deq_bits : _T_4505 ? _Queue16_UInt8_8_io_deq_bits : _T_4504 ? _Queue16_UInt8_7_io_deq_bits : _T_4503 ? _Queue16_UInt8_6_io_deq_bits : _T_4502 ? _Queue16_UInt8_5_io_deq_bits : _T_4501 ? _Queue16_UInt8_4_io_deq_bits : _T_4500 ? _Queue16_UInt8_3_io_deq_bits : _T_4499 ? _Queue16_UInt8_2_io_deq_bits : _T_4498 ? _Queue16_UInt8_1_io_deq_bits : _T_4497 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_valid : _T_4527 ? _Queue16_UInt8_30_io_deq_valid : _T_4526 ? _Queue16_UInt8_29_io_deq_valid : _T_4525 ? _Queue16_UInt8_28_io_deq_valid : _T_4524 ? _Queue16_UInt8_27_io_deq_valid : _T_4523 ? _Queue16_UInt8_26_io_deq_valid : _T_4522 ? _Queue16_UInt8_25_io_deq_valid : _T_4521 ? _Queue16_UInt8_24_io_deq_valid : _T_4520 ? _Queue16_UInt8_23_io_deq_valid : _T_4519 ? _Queue16_UInt8_22_io_deq_valid : _T_4518 ? _Queue16_UInt8_21_io_deq_valid : _T_4517 ? _Queue16_UInt8_20_io_deq_valid : _T_4516 ? _Queue16_UInt8_19_io_deq_valid : _T_4515 ? _Queue16_UInt8_18_io_deq_valid : _T_4514 ? _Queue16_UInt8_17_io_deq_valid : _T_4513 ? _Queue16_UInt8_16_io_deq_valid : _T_4512 ? _Queue16_UInt8_15_io_deq_valid : _T_4511 ? _Queue16_UInt8_14_io_deq_valid : _T_4510 ? _Queue16_UInt8_13_io_deq_valid : _T_4509 ? _Queue16_UInt8_12_io_deq_valid : _T_4508 ? _Queue16_UInt8_11_io_deq_valid : _T_4507 ? _Queue16_UInt8_10_io_deq_valid : _T_4506 ? _Queue16_UInt8_9_io_deq_valid : _T_4505 ? _Queue16_UInt8_8_io_deq_valid : _T_4504 ? _Queue16_UInt8_7_io_deq_valid : _T_4503 ? _Queue16_UInt8_6_io_deq_valid : _T_4502 ? _Queue16_UInt8_5_io_deq_valid : _T_4501 ? _Queue16_UInt8_4_io_deq_valid : _T_4500 ? _Queue16_UInt8_3_io_deq_valid : _T_4499 ? _Queue16_UInt8_2_io_deq_valid : _T_4498 ? _Queue16_UInt8_1_io_deq_valid : _T_4497 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_96 = _remapindex_T_6 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_6 = _GEN_96[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4529 = remapindex_6 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4530 = remapindex_6 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4531 = remapindex_6 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4532 = remapindex_6 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4533 = remapindex_6 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4534 = remapindex_6 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4535 = remapindex_6 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4536 = remapindex_6 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4537 = remapindex_6 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4538 = remapindex_6 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4539 = remapindex_6 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4540 = remapindex_6 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4541 = remapindex_6 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4542 = remapindex_6 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4543 = remapindex_6 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4544 = remapindex_6 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4545 = remapindex_6 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4546 = remapindex_6 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4547 = remapindex_6 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4548 = remapindex_6 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4549 = remapindex_6 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4550 = remapindex_6 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4551 = remapindex_6 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4552 = remapindex_6 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4553 = remapindex_6 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4554 = remapindex_6 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4555 = remapindex_6 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4556 = remapindex_6 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4557 = remapindex_6 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4558 = remapindex_6 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4559 = remapindex_6 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4560 = remapindex_6 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_bits : _T_4559 ? _Queue16_UInt8_30_io_deq_bits : _T_4558 ? _Queue16_UInt8_29_io_deq_bits : _T_4557 ? _Queue16_UInt8_28_io_deq_bits : _T_4556 ? _Queue16_UInt8_27_io_deq_bits : _T_4555 ? _Queue16_UInt8_26_io_deq_bits : _T_4554 ? _Queue16_UInt8_25_io_deq_bits : _T_4553 ? _Queue16_UInt8_24_io_deq_bits : _T_4552 ? _Queue16_UInt8_23_io_deq_bits : _T_4551 ? _Queue16_UInt8_22_io_deq_bits : _T_4550 ? _Queue16_UInt8_21_io_deq_bits : _T_4549 ? _Queue16_UInt8_20_io_deq_bits : _T_4548 ? _Queue16_UInt8_19_io_deq_bits : _T_4547 ? _Queue16_UInt8_18_io_deq_bits : _T_4546 ? _Queue16_UInt8_17_io_deq_bits : _T_4545 ? _Queue16_UInt8_16_io_deq_bits : _T_4544 ? _Queue16_UInt8_15_io_deq_bits : _T_4543 ? _Queue16_UInt8_14_io_deq_bits : _T_4542 ? _Queue16_UInt8_13_io_deq_bits : _T_4541 ? _Queue16_UInt8_12_io_deq_bits : _T_4540 ? _Queue16_UInt8_11_io_deq_bits : _T_4539 ? _Queue16_UInt8_10_io_deq_bits : _T_4538 ? _Queue16_UInt8_9_io_deq_bits : _T_4537 ? _Queue16_UInt8_8_io_deq_bits : _T_4536 ? _Queue16_UInt8_7_io_deq_bits : _T_4535 ? _Queue16_UInt8_6_io_deq_bits : _T_4534 ? _Queue16_UInt8_5_io_deq_bits : _T_4533 ? _Queue16_UInt8_4_io_deq_bits : _T_4532 ? _Queue16_UInt8_3_io_deq_bits : _T_4531 ? _Queue16_UInt8_2_io_deq_bits : _T_4530 ? _Queue16_UInt8_1_io_deq_bits : _T_4529 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_valid : _T_4559 ? _Queue16_UInt8_30_io_deq_valid : _T_4558 ? _Queue16_UInt8_29_io_deq_valid : _T_4557 ? _Queue16_UInt8_28_io_deq_valid : _T_4556 ? _Queue16_UInt8_27_io_deq_valid : _T_4555 ? _Queue16_UInt8_26_io_deq_valid : _T_4554 ? _Queue16_UInt8_25_io_deq_valid : _T_4553 ? _Queue16_UInt8_24_io_deq_valid : _T_4552 ? _Queue16_UInt8_23_io_deq_valid : _T_4551 ? _Queue16_UInt8_22_io_deq_valid : _T_4550 ? _Queue16_UInt8_21_io_deq_valid : _T_4549 ? _Queue16_UInt8_20_io_deq_valid : _T_4548 ? _Queue16_UInt8_19_io_deq_valid : _T_4547 ? _Queue16_UInt8_18_io_deq_valid : _T_4546 ? _Queue16_UInt8_17_io_deq_valid : _T_4545 ? _Queue16_UInt8_16_io_deq_valid : _T_4544 ? _Queue16_UInt8_15_io_deq_valid : _T_4543 ? _Queue16_UInt8_14_io_deq_valid : _T_4542 ? _Queue16_UInt8_13_io_deq_valid : _T_4541 ? _Queue16_UInt8_12_io_deq_valid : _T_4540 ? _Queue16_UInt8_11_io_deq_valid : _T_4539 ? _Queue16_UInt8_10_io_deq_valid : _T_4538 ? _Queue16_UInt8_9_io_deq_valid : _T_4537 ? _Queue16_UInt8_8_io_deq_valid : _T_4536 ? _Queue16_UInt8_7_io_deq_valid : _T_4535 ? _Queue16_UInt8_6_io_deq_valid : _T_4534 ? _Queue16_UInt8_5_io_deq_valid : _T_4533 ? _Queue16_UInt8_4_io_deq_valid : _T_4532 ? _Queue16_UInt8_3_io_deq_valid : _T_4531 ? _Queue16_UInt8_2_io_deq_valid : _T_4530 ? _Queue16_UInt8_1_io_deq_valid : _T_4529 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_97 = _remapindex_T_7 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_7 = _GEN_97[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4561 = remapindex_7 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4562 = remapindex_7 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4563 = remapindex_7 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4564 = remapindex_7 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4565 = remapindex_7 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4566 = remapindex_7 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4567 = remapindex_7 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4568 = remapindex_7 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4569 = remapindex_7 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4570 = remapindex_7 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4571 = remapindex_7 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4572 = remapindex_7 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4573 = remapindex_7 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4574 = remapindex_7 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4575 = remapindex_7 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4576 = remapindex_7 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4577 = remapindex_7 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4578 = remapindex_7 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4579 = remapindex_7 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4580 = remapindex_7 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4581 = remapindex_7 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4582 = remapindex_7 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4583 = remapindex_7 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4584 = remapindex_7 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4585 = remapindex_7 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4586 = remapindex_7 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4587 = remapindex_7 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4588 = remapindex_7 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4589 = remapindex_7 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4590 = remapindex_7 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4591 = remapindex_7 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4592 = remapindex_7 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_bits : _T_4591 ? _Queue16_UInt8_30_io_deq_bits : _T_4590 ? _Queue16_UInt8_29_io_deq_bits : _T_4589 ? _Queue16_UInt8_28_io_deq_bits : _T_4588 ? _Queue16_UInt8_27_io_deq_bits : _T_4587 ? _Queue16_UInt8_26_io_deq_bits : _T_4586 ? _Queue16_UInt8_25_io_deq_bits : _T_4585 ? _Queue16_UInt8_24_io_deq_bits : _T_4584 ? _Queue16_UInt8_23_io_deq_bits : _T_4583 ? _Queue16_UInt8_22_io_deq_bits : _T_4582 ? _Queue16_UInt8_21_io_deq_bits : _T_4581 ? _Queue16_UInt8_20_io_deq_bits : _T_4580 ? _Queue16_UInt8_19_io_deq_bits : _T_4579 ? _Queue16_UInt8_18_io_deq_bits : _T_4578 ? _Queue16_UInt8_17_io_deq_bits : _T_4577 ? _Queue16_UInt8_16_io_deq_bits : _T_4576 ? _Queue16_UInt8_15_io_deq_bits : _T_4575 ? _Queue16_UInt8_14_io_deq_bits : _T_4574 ? _Queue16_UInt8_13_io_deq_bits : _T_4573 ? _Queue16_UInt8_12_io_deq_bits : _T_4572 ? _Queue16_UInt8_11_io_deq_bits : _T_4571 ? _Queue16_UInt8_10_io_deq_bits : _T_4570 ? _Queue16_UInt8_9_io_deq_bits : _T_4569 ? _Queue16_UInt8_8_io_deq_bits : _T_4568 ? _Queue16_UInt8_7_io_deq_bits : _T_4567 ? _Queue16_UInt8_6_io_deq_bits : _T_4566 ? _Queue16_UInt8_5_io_deq_bits : _T_4565 ? _Queue16_UInt8_4_io_deq_bits : _T_4564 ? _Queue16_UInt8_3_io_deq_bits : _T_4563 ? _Queue16_UInt8_2_io_deq_bits : _T_4562 ? _Queue16_UInt8_1_io_deq_bits : _T_4561 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_valid : _T_4591 ? _Queue16_UInt8_30_io_deq_valid : _T_4590 ? _Queue16_UInt8_29_io_deq_valid : _T_4589 ? _Queue16_UInt8_28_io_deq_valid : _T_4588 ? _Queue16_UInt8_27_io_deq_valid : _T_4587 ? _Queue16_UInt8_26_io_deq_valid : _T_4586 ? _Queue16_UInt8_25_io_deq_valid : _T_4585 ? _Queue16_UInt8_24_io_deq_valid : _T_4584 ? _Queue16_UInt8_23_io_deq_valid : _T_4583 ? _Queue16_UInt8_22_io_deq_valid : _T_4582 ? _Queue16_UInt8_21_io_deq_valid : _T_4581 ? _Queue16_UInt8_20_io_deq_valid : _T_4580 ? _Queue16_UInt8_19_io_deq_valid : _T_4579 ? _Queue16_UInt8_18_io_deq_valid : _T_4578 ? _Queue16_UInt8_17_io_deq_valid : _T_4577 ? _Queue16_UInt8_16_io_deq_valid : _T_4576 ? _Queue16_UInt8_15_io_deq_valid : _T_4575 ? _Queue16_UInt8_14_io_deq_valid : _T_4574 ? _Queue16_UInt8_13_io_deq_valid : _T_4573 ? _Queue16_UInt8_12_io_deq_valid : _T_4572 ? _Queue16_UInt8_11_io_deq_valid : _T_4571 ? _Queue16_UInt8_10_io_deq_valid : _T_4570 ? _Queue16_UInt8_9_io_deq_valid : _T_4569 ? _Queue16_UInt8_8_io_deq_valid : _T_4568 ? _Queue16_UInt8_7_io_deq_valid : _T_4567 ? _Queue16_UInt8_6_io_deq_valid : _T_4566 ? _Queue16_UInt8_5_io_deq_valid : _T_4565 ? _Queue16_UInt8_4_io_deq_valid : _T_4564 ? _Queue16_UInt8_3_io_deq_valid : _T_4563 ? _Queue16_UInt8_2_io_deq_valid : _T_4562 ? _Queue16_UInt8_1_io_deq_valid : _T_4561 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_98 = _remapindex_T_8 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_8 = _GEN_98[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4593 = remapindex_8 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4594 = remapindex_8 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4595 = remapindex_8 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4596 = remapindex_8 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4597 = remapindex_8 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4598 = remapindex_8 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4599 = remapindex_8 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4600 = remapindex_8 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4601 = remapindex_8 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4602 = remapindex_8 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4603 = remapindex_8 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4604 = remapindex_8 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4605 = remapindex_8 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4606 = remapindex_8 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4607 = remapindex_8 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4608 = remapindex_8 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4609 = remapindex_8 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4610 = remapindex_8 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4611 = remapindex_8 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4612 = remapindex_8 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4613 = remapindex_8 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4614 = remapindex_8 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4615 = remapindex_8 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4616 = remapindex_8 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4617 = remapindex_8 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4618 = remapindex_8 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4619 = remapindex_8 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4620 = remapindex_8 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4621 = remapindex_8 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4622 = remapindex_8 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4623 = remapindex_8 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4624 = remapindex_8 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_bits : _T_4623 ? _Queue16_UInt8_30_io_deq_bits : _T_4622 ? _Queue16_UInt8_29_io_deq_bits : _T_4621 ? _Queue16_UInt8_28_io_deq_bits : _T_4620 ? _Queue16_UInt8_27_io_deq_bits : _T_4619 ? _Queue16_UInt8_26_io_deq_bits : _T_4618 ? _Queue16_UInt8_25_io_deq_bits : _T_4617 ? _Queue16_UInt8_24_io_deq_bits : _T_4616 ? _Queue16_UInt8_23_io_deq_bits : _T_4615 ? _Queue16_UInt8_22_io_deq_bits : _T_4614 ? _Queue16_UInt8_21_io_deq_bits : _T_4613 ? _Queue16_UInt8_20_io_deq_bits : _T_4612 ? _Queue16_UInt8_19_io_deq_bits : _T_4611 ? _Queue16_UInt8_18_io_deq_bits : _T_4610 ? _Queue16_UInt8_17_io_deq_bits : _T_4609 ? _Queue16_UInt8_16_io_deq_bits : _T_4608 ? _Queue16_UInt8_15_io_deq_bits : _T_4607 ? _Queue16_UInt8_14_io_deq_bits : _T_4606 ? _Queue16_UInt8_13_io_deq_bits : _T_4605 ? _Queue16_UInt8_12_io_deq_bits : _T_4604 ? _Queue16_UInt8_11_io_deq_bits : _T_4603 ? _Queue16_UInt8_10_io_deq_bits : _T_4602 ? _Queue16_UInt8_9_io_deq_bits : _T_4601 ? _Queue16_UInt8_8_io_deq_bits : _T_4600 ? _Queue16_UInt8_7_io_deq_bits : _T_4599 ? _Queue16_UInt8_6_io_deq_bits : _T_4598 ? _Queue16_UInt8_5_io_deq_bits : _T_4597 ? _Queue16_UInt8_4_io_deq_bits : _T_4596 ? _Queue16_UInt8_3_io_deq_bits : _T_4595 ? _Queue16_UInt8_2_io_deq_bits : _T_4594 ? _Queue16_UInt8_1_io_deq_bits : _T_4593 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_valid : _T_4623 ? _Queue16_UInt8_30_io_deq_valid : _T_4622 ? _Queue16_UInt8_29_io_deq_valid : _T_4621 ? _Queue16_UInt8_28_io_deq_valid : _T_4620 ? _Queue16_UInt8_27_io_deq_valid : _T_4619 ? _Queue16_UInt8_26_io_deq_valid : _T_4618 ? _Queue16_UInt8_25_io_deq_valid : _T_4617 ? _Queue16_UInt8_24_io_deq_valid : _T_4616 ? _Queue16_UInt8_23_io_deq_valid : _T_4615 ? _Queue16_UInt8_22_io_deq_valid : _T_4614 ? _Queue16_UInt8_21_io_deq_valid : _T_4613 ? _Queue16_UInt8_20_io_deq_valid : _T_4612 ? _Queue16_UInt8_19_io_deq_valid : _T_4611 ? _Queue16_UInt8_18_io_deq_valid : _T_4610 ? _Queue16_UInt8_17_io_deq_valid : _T_4609 ? _Queue16_UInt8_16_io_deq_valid : _T_4608 ? _Queue16_UInt8_15_io_deq_valid : _T_4607 ? _Queue16_UInt8_14_io_deq_valid : _T_4606 ? _Queue16_UInt8_13_io_deq_valid : _T_4605 ? _Queue16_UInt8_12_io_deq_valid : _T_4604 ? _Queue16_UInt8_11_io_deq_valid : _T_4603 ? _Queue16_UInt8_10_io_deq_valid : _T_4602 ? _Queue16_UInt8_9_io_deq_valid : _T_4601 ? _Queue16_UInt8_8_io_deq_valid : _T_4600 ? _Queue16_UInt8_7_io_deq_valid : _T_4599 ? _Queue16_UInt8_6_io_deq_valid : _T_4598 ? _Queue16_UInt8_5_io_deq_valid : _T_4597 ? _Queue16_UInt8_4_io_deq_valid : _T_4596 ? _Queue16_UInt8_3_io_deq_valid : _T_4595 ? _Queue16_UInt8_2_io_deq_valid : _T_4594 ? _Queue16_UInt8_1_io_deq_valid : _T_4593 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_99 = _remapindex_T_9 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_9 = _GEN_99[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4625 = remapindex_9 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4626 = remapindex_9 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4627 = remapindex_9 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4628 = remapindex_9 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4629 = remapindex_9 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4630 = remapindex_9 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4631 = remapindex_9 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4632 = remapindex_9 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4633 = remapindex_9 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4634 = remapindex_9 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4635 = remapindex_9 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4636 = remapindex_9 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4637 = remapindex_9 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4638 = remapindex_9 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4639 = remapindex_9 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4640 = remapindex_9 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4641 = remapindex_9 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4642 = remapindex_9 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4643 = remapindex_9 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4644 = remapindex_9 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4645 = remapindex_9 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4646 = remapindex_9 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4647 = remapindex_9 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4648 = remapindex_9 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4649 = remapindex_9 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4650 = remapindex_9 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4651 = remapindex_9 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4652 = remapindex_9 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4653 = remapindex_9 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4654 = remapindex_9 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4655 = remapindex_9 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4656 = remapindex_9 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_bits : _T_4655 ? _Queue16_UInt8_30_io_deq_bits : _T_4654 ? _Queue16_UInt8_29_io_deq_bits : _T_4653 ? _Queue16_UInt8_28_io_deq_bits : _T_4652 ? _Queue16_UInt8_27_io_deq_bits : _T_4651 ? _Queue16_UInt8_26_io_deq_bits : _T_4650 ? _Queue16_UInt8_25_io_deq_bits : _T_4649 ? _Queue16_UInt8_24_io_deq_bits : _T_4648 ? _Queue16_UInt8_23_io_deq_bits : _T_4647 ? _Queue16_UInt8_22_io_deq_bits : _T_4646 ? _Queue16_UInt8_21_io_deq_bits : _T_4645 ? _Queue16_UInt8_20_io_deq_bits : _T_4644 ? _Queue16_UInt8_19_io_deq_bits : _T_4643 ? _Queue16_UInt8_18_io_deq_bits : _T_4642 ? _Queue16_UInt8_17_io_deq_bits : _T_4641 ? _Queue16_UInt8_16_io_deq_bits : _T_4640 ? _Queue16_UInt8_15_io_deq_bits : _T_4639 ? _Queue16_UInt8_14_io_deq_bits : _T_4638 ? _Queue16_UInt8_13_io_deq_bits : _T_4637 ? _Queue16_UInt8_12_io_deq_bits : _T_4636 ? _Queue16_UInt8_11_io_deq_bits : _T_4635 ? _Queue16_UInt8_10_io_deq_bits : _T_4634 ? _Queue16_UInt8_9_io_deq_bits : _T_4633 ? _Queue16_UInt8_8_io_deq_bits : _T_4632 ? _Queue16_UInt8_7_io_deq_bits : _T_4631 ? _Queue16_UInt8_6_io_deq_bits : _T_4630 ? _Queue16_UInt8_5_io_deq_bits : _T_4629 ? _Queue16_UInt8_4_io_deq_bits : _T_4628 ? _Queue16_UInt8_3_io_deq_bits : _T_4627 ? _Queue16_UInt8_2_io_deq_bits : _T_4626 ? _Queue16_UInt8_1_io_deq_bits : _T_4625 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_valid : _T_4655 ? _Queue16_UInt8_30_io_deq_valid : _T_4654 ? _Queue16_UInt8_29_io_deq_valid : _T_4653 ? _Queue16_UInt8_28_io_deq_valid : _T_4652 ? _Queue16_UInt8_27_io_deq_valid : _T_4651 ? _Queue16_UInt8_26_io_deq_valid : _T_4650 ? _Queue16_UInt8_25_io_deq_valid : _T_4649 ? _Queue16_UInt8_24_io_deq_valid : _T_4648 ? _Queue16_UInt8_23_io_deq_valid : _T_4647 ? _Queue16_UInt8_22_io_deq_valid : _T_4646 ? _Queue16_UInt8_21_io_deq_valid : _T_4645 ? _Queue16_UInt8_20_io_deq_valid : _T_4644 ? _Queue16_UInt8_19_io_deq_valid : _T_4643 ? _Queue16_UInt8_18_io_deq_valid : _T_4642 ? _Queue16_UInt8_17_io_deq_valid : _T_4641 ? _Queue16_UInt8_16_io_deq_valid : _T_4640 ? _Queue16_UInt8_15_io_deq_valid : _T_4639 ? _Queue16_UInt8_14_io_deq_valid : _T_4638 ? _Queue16_UInt8_13_io_deq_valid : _T_4637 ? _Queue16_UInt8_12_io_deq_valid : _T_4636 ? _Queue16_UInt8_11_io_deq_valid : _T_4635 ? _Queue16_UInt8_10_io_deq_valid : _T_4634 ? _Queue16_UInt8_9_io_deq_valid : _T_4633 ? _Queue16_UInt8_8_io_deq_valid : _T_4632 ? _Queue16_UInt8_7_io_deq_valid : _T_4631 ? _Queue16_UInt8_6_io_deq_valid : _T_4630 ? _Queue16_UInt8_5_io_deq_valid : _T_4629 ? _Queue16_UInt8_4_io_deq_valid : _T_4628 ? _Queue16_UInt8_3_io_deq_valid : _T_4627 ? _Queue16_UInt8_2_io_deq_valid : _T_4626 ? _Queue16_UInt8_1_io_deq_valid : _T_4625 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_100 = _remapindex_T_10 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_10 = _GEN_100[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4657 = remapindex_10 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4658 = remapindex_10 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4659 = remapindex_10 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4660 = remapindex_10 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4661 = remapindex_10 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4662 = remapindex_10 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4663 = remapindex_10 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4664 = remapindex_10 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4665 = remapindex_10 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4666 = remapindex_10 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4667 = remapindex_10 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4668 = remapindex_10 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4669 = remapindex_10 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4670 = remapindex_10 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4671 = remapindex_10 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4672 = remapindex_10 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4673 = remapindex_10 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4674 = remapindex_10 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4675 = remapindex_10 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4676 = remapindex_10 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4677 = remapindex_10 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4678 = remapindex_10 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4679 = remapindex_10 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4680 = remapindex_10 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4681 = remapindex_10 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4682 = remapindex_10 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4683 = remapindex_10 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4684 = remapindex_10 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4685 = remapindex_10 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4686 = remapindex_10 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4687 = remapindex_10 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4688 = remapindex_10 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_bits : _T_4687 ? _Queue16_UInt8_30_io_deq_bits : _T_4686 ? _Queue16_UInt8_29_io_deq_bits : _T_4685 ? _Queue16_UInt8_28_io_deq_bits : _T_4684 ? _Queue16_UInt8_27_io_deq_bits : _T_4683 ? _Queue16_UInt8_26_io_deq_bits : _T_4682 ? _Queue16_UInt8_25_io_deq_bits : _T_4681 ? _Queue16_UInt8_24_io_deq_bits : _T_4680 ? _Queue16_UInt8_23_io_deq_bits : _T_4679 ? _Queue16_UInt8_22_io_deq_bits : _T_4678 ? _Queue16_UInt8_21_io_deq_bits : _T_4677 ? _Queue16_UInt8_20_io_deq_bits : _T_4676 ? _Queue16_UInt8_19_io_deq_bits : _T_4675 ? _Queue16_UInt8_18_io_deq_bits : _T_4674 ? _Queue16_UInt8_17_io_deq_bits : _T_4673 ? _Queue16_UInt8_16_io_deq_bits : _T_4672 ? _Queue16_UInt8_15_io_deq_bits : _T_4671 ? _Queue16_UInt8_14_io_deq_bits : _T_4670 ? _Queue16_UInt8_13_io_deq_bits : _T_4669 ? _Queue16_UInt8_12_io_deq_bits : _T_4668 ? _Queue16_UInt8_11_io_deq_bits : _T_4667 ? _Queue16_UInt8_10_io_deq_bits : _T_4666 ? _Queue16_UInt8_9_io_deq_bits : _T_4665 ? _Queue16_UInt8_8_io_deq_bits : _T_4664 ? _Queue16_UInt8_7_io_deq_bits : _T_4663 ? _Queue16_UInt8_6_io_deq_bits : _T_4662 ? _Queue16_UInt8_5_io_deq_bits : _T_4661 ? _Queue16_UInt8_4_io_deq_bits : _T_4660 ? _Queue16_UInt8_3_io_deq_bits : _T_4659 ? _Queue16_UInt8_2_io_deq_bits : _T_4658 ? _Queue16_UInt8_1_io_deq_bits : _T_4657 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_valid : _T_4687 ? _Queue16_UInt8_30_io_deq_valid : _T_4686 ? _Queue16_UInt8_29_io_deq_valid : _T_4685 ? _Queue16_UInt8_28_io_deq_valid : _T_4684 ? _Queue16_UInt8_27_io_deq_valid : _T_4683 ? _Queue16_UInt8_26_io_deq_valid : _T_4682 ? _Queue16_UInt8_25_io_deq_valid : _T_4681 ? _Queue16_UInt8_24_io_deq_valid : _T_4680 ? _Queue16_UInt8_23_io_deq_valid : _T_4679 ? _Queue16_UInt8_22_io_deq_valid : _T_4678 ? _Queue16_UInt8_21_io_deq_valid : _T_4677 ? _Queue16_UInt8_20_io_deq_valid : _T_4676 ? _Queue16_UInt8_19_io_deq_valid : _T_4675 ? _Queue16_UInt8_18_io_deq_valid : _T_4674 ? _Queue16_UInt8_17_io_deq_valid : _T_4673 ? _Queue16_UInt8_16_io_deq_valid : _T_4672 ? _Queue16_UInt8_15_io_deq_valid : _T_4671 ? _Queue16_UInt8_14_io_deq_valid : _T_4670 ? _Queue16_UInt8_13_io_deq_valid : _T_4669 ? _Queue16_UInt8_12_io_deq_valid : _T_4668 ? _Queue16_UInt8_11_io_deq_valid : _T_4667 ? _Queue16_UInt8_10_io_deq_valid : _T_4666 ? _Queue16_UInt8_9_io_deq_valid : _T_4665 ? _Queue16_UInt8_8_io_deq_valid : _T_4664 ? _Queue16_UInt8_7_io_deq_valid : _T_4663 ? _Queue16_UInt8_6_io_deq_valid : _T_4662 ? _Queue16_UInt8_5_io_deq_valid : _T_4661 ? _Queue16_UInt8_4_io_deq_valid : _T_4660 ? _Queue16_UInt8_3_io_deq_valid : _T_4659 ? _Queue16_UInt8_2_io_deq_valid : _T_4658 ? _Queue16_UInt8_1_io_deq_valid : _T_4657 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_101 = _remapindex_T_11 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_11 = _GEN_101[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4689 = remapindex_11 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4690 = remapindex_11 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4691 = remapindex_11 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4692 = remapindex_11 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4693 = remapindex_11 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4694 = remapindex_11 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4695 = remapindex_11 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4696 = remapindex_11 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4697 = remapindex_11 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4698 = remapindex_11 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4699 = remapindex_11 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4700 = remapindex_11 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4701 = remapindex_11 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4702 = remapindex_11 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4703 = remapindex_11 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4704 = remapindex_11 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4705 = remapindex_11 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4706 = remapindex_11 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4707 = remapindex_11 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4708 = remapindex_11 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4709 = remapindex_11 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4710 = remapindex_11 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4711 = remapindex_11 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4712 = remapindex_11 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4713 = remapindex_11 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4714 = remapindex_11 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4715 = remapindex_11 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4716 = remapindex_11 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4717 = remapindex_11 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4718 = remapindex_11 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4719 = remapindex_11 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4720 = remapindex_11 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_bits : _T_4719 ? _Queue16_UInt8_30_io_deq_bits : _T_4718 ? _Queue16_UInt8_29_io_deq_bits : _T_4717 ? _Queue16_UInt8_28_io_deq_bits : _T_4716 ? _Queue16_UInt8_27_io_deq_bits : _T_4715 ? _Queue16_UInt8_26_io_deq_bits : _T_4714 ? _Queue16_UInt8_25_io_deq_bits : _T_4713 ? _Queue16_UInt8_24_io_deq_bits : _T_4712 ? _Queue16_UInt8_23_io_deq_bits : _T_4711 ? _Queue16_UInt8_22_io_deq_bits : _T_4710 ? _Queue16_UInt8_21_io_deq_bits : _T_4709 ? _Queue16_UInt8_20_io_deq_bits : _T_4708 ? _Queue16_UInt8_19_io_deq_bits : _T_4707 ? _Queue16_UInt8_18_io_deq_bits : _T_4706 ? _Queue16_UInt8_17_io_deq_bits : _T_4705 ? _Queue16_UInt8_16_io_deq_bits : _T_4704 ? _Queue16_UInt8_15_io_deq_bits : _T_4703 ? _Queue16_UInt8_14_io_deq_bits : _T_4702 ? _Queue16_UInt8_13_io_deq_bits : _T_4701 ? _Queue16_UInt8_12_io_deq_bits : _T_4700 ? _Queue16_UInt8_11_io_deq_bits : _T_4699 ? _Queue16_UInt8_10_io_deq_bits : _T_4698 ? _Queue16_UInt8_9_io_deq_bits : _T_4697 ? _Queue16_UInt8_8_io_deq_bits : _T_4696 ? _Queue16_UInt8_7_io_deq_bits : _T_4695 ? _Queue16_UInt8_6_io_deq_bits : _T_4694 ? _Queue16_UInt8_5_io_deq_bits : _T_4693 ? _Queue16_UInt8_4_io_deq_bits : _T_4692 ? _Queue16_UInt8_3_io_deq_bits : _T_4691 ? _Queue16_UInt8_2_io_deq_bits : _T_4690 ? _Queue16_UInt8_1_io_deq_bits : _T_4689 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_valid : _T_4719 ? _Queue16_UInt8_30_io_deq_valid : _T_4718 ? _Queue16_UInt8_29_io_deq_valid : _T_4717 ? _Queue16_UInt8_28_io_deq_valid : _T_4716 ? _Queue16_UInt8_27_io_deq_valid : _T_4715 ? _Queue16_UInt8_26_io_deq_valid : _T_4714 ? _Queue16_UInt8_25_io_deq_valid : _T_4713 ? _Queue16_UInt8_24_io_deq_valid : _T_4712 ? _Queue16_UInt8_23_io_deq_valid : _T_4711 ? _Queue16_UInt8_22_io_deq_valid : _T_4710 ? _Queue16_UInt8_21_io_deq_valid : _T_4709 ? _Queue16_UInt8_20_io_deq_valid : _T_4708 ? _Queue16_UInt8_19_io_deq_valid : _T_4707 ? _Queue16_UInt8_18_io_deq_valid : _T_4706 ? _Queue16_UInt8_17_io_deq_valid : _T_4705 ? _Queue16_UInt8_16_io_deq_valid : _T_4704 ? _Queue16_UInt8_15_io_deq_valid : _T_4703 ? _Queue16_UInt8_14_io_deq_valid : _T_4702 ? _Queue16_UInt8_13_io_deq_valid : _T_4701 ? _Queue16_UInt8_12_io_deq_valid : _T_4700 ? _Queue16_UInt8_11_io_deq_valid : _T_4699 ? _Queue16_UInt8_10_io_deq_valid : _T_4698 ? _Queue16_UInt8_9_io_deq_valid : _T_4697 ? _Queue16_UInt8_8_io_deq_valid : _T_4696 ? _Queue16_UInt8_7_io_deq_valid : _T_4695 ? _Queue16_UInt8_6_io_deq_valid : _T_4694 ? _Queue16_UInt8_5_io_deq_valid : _T_4693 ? _Queue16_UInt8_4_io_deq_valid : _T_4692 ? _Queue16_UInt8_3_io_deq_valid : _T_4691 ? _Queue16_UInt8_2_io_deq_valid : _T_4690 ? _Queue16_UInt8_1_io_deq_valid : _T_4689 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_102 = _remapindex_T_12 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_12 = _GEN_102[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4721 = remapindex_12 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4722 = remapindex_12 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4723 = remapindex_12 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4724 = remapindex_12 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4725 = remapindex_12 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4726 = remapindex_12 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4727 = remapindex_12 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4728 = remapindex_12 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4729 = remapindex_12 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4730 = remapindex_12 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4731 = remapindex_12 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4732 = remapindex_12 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4733 = remapindex_12 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4734 = remapindex_12 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4735 = remapindex_12 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4736 = remapindex_12 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4737 = remapindex_12 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4738 = remapindex_12 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4739 = remapindex_12 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4740 = remapindex_12 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4741 = remapindex_12 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4742 = remapindex_12 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4743 = remapindex_12 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4744 = remapindex_12 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4745 = remapindex_12 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4746 = remapindex_12 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4747 = remapindex_12 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4748 = remapindex_12 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4749 = remapindex_12 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4750 = remapindex_12 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4751 = remapindex_12 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4752 = remapindex_12 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_bits : _T_4751 ? _Queue16_UInt8_30_io_deq_bits : _T_4750 ? _Queue16_UInt8_29_io_deq_bits : _T_4749 ? _Queue16_UInt8_28_io_deq_bits : _T_4748 ? _Queue16_UInt8_27_io_deq_bits : _T_4747 ? _Queue16_UInt8_26_io_deq_bits : _T_4746 ? _Queue16_UInt8_25_io_deq_bits : _T_4745 ? _Queue16_UInt8_24_io_deq_bits : _T_4744 ? _Queue16_UInt8_23_io_deq_bits : _T_4743 ? _Queue16_UInt8_22_io_deq_bits : _T_4742 ? _Queue16_UInt8_21_io_deq_bits : _T_4741 ? _Queue16_UInt8_20_io_deq_bits : _T_4740 ? _Queue16_UInt8_19_io_deq_bits : _T_4739 ? _Queue16_UInt8_18_io_deq_bits : _T_4738 ? _Queue16_UInt8_17_io_deq_bits : _T_4737 ? _Queue16_UInt8_16_io_deq_bits : _T_4736 ? _Queue16_UInt8_15_io_deq_bits : _T_4735 ? _Queue16_UInt8_14_io_deq_bits : _T_4734 ? _Queue16_UInt8_13_io_deq_bits : _T_4733 ? _Queue16_UInt8_12_io_deq_bits : _T_4732 ? _Queue16_UInt8_11_io_deq_bits : _T_4731 ? _Queue16_UInt8_10_io_deq_bits : _T_4730 ? _Queue16_UInt8_9_io_deq_bits : _T_4729 ? _Queue16_UInt8_8_io_deq_bits : _T_4728 ? _Queue16_UInt8_7_io_deq_bits : _T_4727 ? _Queue16_UInt8_6_io_deq_bits : _T_4726 ? _Queue16_UInt8_5_io_deq_bits : _T_4725 ? _Queue16_UInt8_4_io_deq_bits : _T_4724 ? _Queue16_UInt8_3_io_deq_bits : _T_4723 ? _Queue16_UInt8_2_io_deq_bits : _T_4722 ? _Queue16_UInt8_1_io_deq_bits : _T_4721 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_valid : _T_4751 ? _Queue16_UInt8_30_io_deq_valid : _T_4750 ? _Queue16_UInt8_29_io_deq_valid : _T_4749 ? _Queue16_UInt8_28_io_deq_valid : _T_4748 ? _Queue16_UInt8_27_io_deq_valid : _T_4747 ? _Queue16_UInt8_26_io_deq_valid : _T_4746 ? _Queue16_UInt8_25_io_deq_valid : _T_4745 ? _Queue16_UInt8_24_io_deq_valid : _T_4744 ? _Queue16_UInt8_23_io_deq_valid : _T_4743 ? _Queue16_UInt8_22_io_deq_valid : _T_4742 ? _Queue16_UInt8_21_io_deq_valid : _T_4741 ? _Queue16_UInt8_20_io_deq_valid : _T_4740 ? _Queue16_UInt8_19_io_deq_valid : _T_4739 ? _Queue16_UInt8_18_io_deq_valid : _T_4738 ? _Queue16_UInt8_17_io_deq_valid : _T_4737 ? _Queue16_UInt8_16_io_deq_valid : _T_4736 ? _Queue16_UInt8_15_io_deq_valid : _T_4735 ? _Queue16_UInt8_14_io_deq_valid : _T_4734 ? _Queue16_UInt8_13_io_deq_valid : _T_4733 ? _Queue16_UInt8_12_io_deq_valid : _T_4732 ? _Queue16_UInt8_11_io_deq_valid : _T_4731 ? _Queue16_UInt8_10_io_deq_valid : _T_4730 ? _Queue16_UInt8_9_io_deq_valid : _T_4729 ? _Queue16_UInt8_8_io_deq_valid : _T_4728 ? _Queue16_UInt8_7_io_deq_valid : _T_4727 ? _Queue16_UInt8_6_io_deq_valid : _T_4726 ? _Queue16_UInt8_5_io_deq_valid : _T_4725 ? _Queue16_UInt8_4_io_deq_valid : _T_4724 ? _Queue16_UInt8_3_io_deq_valid : _T_4723 ? _Queue16_UInt8_2_io_deq_valid : _T_4722 ? _Queue16_UInt8_1_io_deq_valid : _T_4721 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_103 = _remapindex_T_13 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_13 = _GEN_103[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4753 = remapindex_13 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4754 = remapindex_13 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4755 = remapindex_13 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4756 = remapindex_13 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4757 = remapindex_13 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4758 = remapindex_13 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4759 = remapindex_13 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4760 = remapindex_13 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4761 = remapindex_13 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4762 = remapindex_13 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4763 = remapindex_13 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4764 = remapindex_13 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4765 = remapindex_13 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4766 = remapindex_13 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4767 = remapindex_13 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4768 = remapindex_13 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4769 = remapindex_13 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4770 = remapindex_13 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4771 = remapindex_13 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4772 = remapindex_13 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4773 = remapindex_13 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4774 = remapindex_13 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4775 = remapindex_13 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4776 = remapindex_13 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4777 = remapindex_13 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4778 = remapindex_13 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4779 = remapindex_13 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4780 = remapindex_13 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4781 = remapindex_13 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4782 = remapindex_13 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4783 = remapindex_13 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4784 = remapindex_13 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_bits : _T_4783 ? _Queue16_UInt8_30_io_deq_bits : _T_4782 ? _Queue16_UInt8_29_io_deq_bits : _T_4781 ? _Queue16_UInt8_28_io_deq_bits : _T_4780 ? _Queue16_UInt8_27_io_deq_bits : _T_4779 ? _Queue16_UInt8_26_io_deq_bits : _T_4778 ? _Queue16_UInt8_25_io_deq_bits : _T_4777 ? _Queue16_UInt8_24_io_deq_bits : _T_4776 ? _Queue16_UInt8_23_io_deq_bits : _T_4775 ? _Queue16_UInt8_22_io_deq_bits : _T_4774 ? _Queue16_UInt8_21_io_deq_bits : _T_4773 ? _Queue16_UInt8_20_io_deq_bits : _T_4772 ? _Queue16_UInt8_19_io_deq_bits : _T_4771 ? _Queue16_UInt8_18_io_deq_bits : _T_4770 ? _Queue16_UInt8_17_io_deq_bits : _T_4769 ? _Queue16_UInt8_16_io_deq_bits : _T_4768 ? _Queue16_UInt8_15_io_deq_bits : _T_4767 ? _Queue16_UInt8_14_io_deq_bits : _T_4766 ? _Queue16_UInt8_13_io_deq_bits : _T_4765 ? _Queue16_UInt8_12_io_deq_bits : _T_4764 ? _Queue16_UInt8_11_io_deq_bits : _T_4763 ? _Queue16_UInt8_10_io_deq_bits : _T_4762 ? _Queue16_UInt8_9_io_deq_bits : _T_4761 ? _Queue16_UInt8_8_io_deq_bits : _T_4760 ? _Queue16_UInt8_7_io_deq_bits : _T_4759 ? _Queue16_UInt8_6_io_deq_bits : _T_4758 ? _Queue16_UInt8_5_io_deq_bits : _T_4757 ? _Queue16_UInt8_4_io_deq_bits : _T_4756 ? _Queue16_UInt8_3_io_deq_bits : _T_4755 ? _Queue16_UInt8_2_io_deq_bits : _T_4754 ? _Queue16_UInt8_1_io_deq_bits : _T_4753 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_valid : _T_4783 ? _Queue16_UInt8_30_io_deq_valid : _T_4782 ? _Queue16_UInt8_29_io_deq_valid : _T_4781 ? _Queue16_UInt8_28_io_deq_valid : _T_4780 ? _Queue16_UInt8_27_io_deq_valid : _T_4779 ? _Queue16_UInt8_26_io_deq_valid : _T_4778 ? _Queue16_UInt8_25_io_deq_valid : _T_4777 ? _Queue16_UInt8_24_io_deq_valid : _T_4776 ? _Queue16_UInt8_23_io_deq_valid : _T_4775 ? _Queue16_UInt8_22_io_deq_valid : _T_4774 ? _Queue16_UInt8_21_io_deq_valid : _T_4773 ? _Queue16_UInt8_20_io_deq_valid : _T_4772 ? _Queue16_UInt8_19_io_deq_valid : _T_4771 ? _Queue16_UInt8_18_io_deq_valid : _T_4770 ? _Queue16_UInt8_17_io_deq_valid : _T_4769 ? _Queue16_UInt8_16_io_deq_valid : _T_4768 ? _Queue16_UInt8_15_io_deq_valid : _T_4767 ? _Queue16_UInt8_14_io_deq_valid : _T_4766 ? _Queue16_UInt8_13_io_deq_valid : _T_4765 ? _Queue16_UInt8_12_io_deq_valid : _T_4764 ? _Queue16_UInt8_11_io_deq_valid : _T_4763 ? _Queue16_UInt8_10_io_deq_valid : _T_4762 ? _Queue16_UInt8_9_io_deq_valid : _T_4761 ? _Queue16_UInt8_8_io_deq_valid : _T_4760 ? _Queue16_UInt8_7_io_deq_valid : _T_4759 ? _Queue16_UInt8_6_io_deq_valid : _T_4758 ? _Queue16_UInt8_5_io_deq_valid : _T_4757 ? _Queue16_UInt8_4_io_deq_valid : _T_4756 ? _Queue16_UInt8_3_io_deq_valid : _T_4755 ? _Queue16_UInt8_2_io_deq_valid : _T_4754 ? _Queue16_UInt8_1_io_deq_valid : _T_4753 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_104 = _remapindex_T_14 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_14 = _GEN_104[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4785 = remapindex_14 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4786 = remapindex_14 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4787 = remapindex_14 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4788 = remapindex_14 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4789 = remapindex_14 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4790 = remapindex_14 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4791 = remapindex_14 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4792 = remapindex_14 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4793 = remapindex_14 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4794 = remapindex_14 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4795 = remapindex_14 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4796 = remapindex_14 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4797 = remapindex_14 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4798 = remapindex_14 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4799 = remapindex_14 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4800 = remapindex_14 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4801 = remapindex_14 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4802 = remapindex_14 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4803 = remapindex_14 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4804 = remapindex_14 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4805 = remapindex_14 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4806 = remapindex_14 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4807 = remapindex_14 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4808 = remapindex_14 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4809 = remapindex_14 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4810 = remapindex_14 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4811 = remapindex_14 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4812 = remapindex_14 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4813 = remapindex_14 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4814 = remapindex_14 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4815 = remapindex_14 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4816 = remapindex_14 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_bits : _T_4815 ? _Queue16_UInt8_30_io_deq_bits : _T_4814 ? _Queue16_UInt8_29_io_deq_bits : _T_4813 ? _Queue16_UInt8_28_io_deq_bits : _T_4812 ? _Queue16_UInt8_27_io_deq_bits : _T_4811 ? _Queue16_UInt8_26_io_deq_bits : _T_4810 ? _Queue16_UInt8_25_io_deq_bits : _T_4809 ? _Queue16_UInt8_24_io_deq_bits : _T_4808 ? _Queue16_UInt8_23_io_deq_bits : _T_4807 ? _Queue16_UInt8_22_io_deq_bits : _T_4806 ? _Queue16_UInt8_21_io_deq_bits : _T_4805 ? _Queue16_UInt8_20_io_deq_bits : _T_4804 ? _Queue16_UInt8_19_io_deq_bits : _T_4803 ? _Queue16_UInt8_18_io_deq_bits : _T_4802 ? _Queue16_UInt8_17_io_deq_bits : _T_4801 ? _Queue16_UInt8_16_io_deq_bits : _T_4800 ? _Queue16_UInt8_15_io_deq_bits : _T_4799 ? _Queue16_UInt8_14_io_deq_bits : _T_4798 ? _Queue16_UInt8_13_io_deq_bits : _T_4797 ? _Queue16_UInt8_12_io_deq_bits : _T_4796 ? _Queue16_UInt8_11_io_deq_bits : _T_4795 ? _Queue16_UInt8_10_io_deq_bits : _T_4794 ? _Queue16_UInt8_9_io_deq_bits : _T_4793 ? _Queue16_UInt8_8_io_deq_bits : _T_4792 ? _Queue16_UInt8_7_io_deq_bits : _T_4791 ? _Queue16_UInt8_6_io_deq_bits : _T_4790 ? _Queue16_UInt8_5_io_deq_bits : _T_4789 ? _Queue16_UInt8_4_io_deq_bits : _T_4788 ? _Queue16_UInt8_3_io_deq_bits : _T_4787 ? _Queue16_UInt8_2_io_deq_bits : _T_4786 ? _Queue16_UInt8_1_io_deq_bits : _T_4785 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_valid : _T_4815 ? _Queue16_UInt8_30_io_deq_valid : _T_4814 ? _Queue16_UInt8_29_io_deq_valid : _T_4813 ? _Queue16_UInt8_28_io_deq_valid : _T_4812 ? _Queue16_UInt8_27_io_deq_valid : _T_4811 ? _Queue16_UInt8_26_io_deq_valid : _T_4810 ? _Queue16_UInt8_25_io_deq_valid : _T_4809 ? _Queue16_UInt8_24_io_deq_valid : _T_4808 ? _Queue16_UInt8_23_io_deq_valid : _T_4807 ? _Queue16_UInt8_22_io_deq_valid : _T_4806 ? _Queue16_UInt8_21_io_deq_valid : _T_4805 ? _Queue16_UInt8_20_io_deq_valid : _T_4804 ? _Queue16_UInt8_19_io_deq_valid : _T_4803 ? _Queue16_UInt8_18_io_deq_valid : _T_4802 ? _Queue16_UInt8_17_io_deq_valid : _T_4801 ? _Queue16_UInt8_16_io_deq_valid : _T_4800 ? _Queue16_UInt8_15_io_deq_valid : _T_4799 ? _Queue16_UInt8_14_io_deq_valid : _T_4798 ? _Queue16_UInt8_13_io_deq_valid : _T_4797 ? _Queue16_UInt8_12_io_deq_valid : _T_4796 ? _Queue16_UInt8_11_io_deq_valid : _T_4795 ? _Queue16_UInt8_10_io_deq_valid : _T_4794 ? _Queue16_UInt8_9_io_deq_valid : _T_4793 ? _Queue16_UInt8_8_io_deq_valid : _T_4792 ? _Queue16_UInt8_7_io_deq_valid : _T_4791 ? _Queue16_UInt8_6_io_deq_valid : _T_4790 ? _Queue16_UInt8_5_io_deq_valid : _T_4789 ? _Queue16_UInt8_4_io_deq_valid : _T_4788 ? _Queue16_UInt8_3_io_deq_valid : _T_4787 ? _Queue16_UInt8_2_io_deq_valid : _T_4786 ? _Queue16_UInt8_1_io_deq_valid : _T_4785 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_105 = _remapindex_T_15 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_15 = _GEN_105[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4817 = remapindex_15 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4818 = remapindex_15 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4819 = remapindex_15 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4820 = remapindex_15 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4821 = remapindex_15 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4822 = remapindex_15 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4823 = remapindex_15 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4824 = remapindex_15 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4825 = remapindex_15 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4826 = remapindex_15 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4827 = remapindex_15 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4828 = remapindex_15 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4829 = remapindex_15 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4830 = remapindex_15 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4831 = remapindex_15 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4832 = remapindex_15 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4833 = remapindex_15 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4834 = remapindex_15 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4835 = remapindex_15 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4836 = remapindex_15 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4837 = remapindex_15 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4838 = remapindex_15 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4839 = remapindex_15 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4840 = remapindex_15 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4841 = remapindex_15 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4842 = remapindex_15 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4843 = remapindex_15 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4844 = remapindex_15 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4845 = remapindex_15 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4846 = remapindex_15 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4847 = remapindex_15 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4848 = remapindex_15 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_bits : _T_4847 ? _Queue16_UInt8_30_io_deq_bits : _T_4846 ? _Queue16_UInt8_29_io_deq_bits : _T_4845 ? _Queue16_UInt8_28_io_deq_bits : _T_4844 ? _Queue16_UInt8_27_io_deq_bits : _T_4843 ? _Queue16_UInt8_26_io_deq_bits : _T_4842 ? _Queue16_UInt8_25_io_deq_bits : _T_4841 ? _Queue16_UInt8_24_io_deq_bits : _T_4840 ? _Queue16_UInt8_23_io_deq_bits : _T_4839 ? _Queue16_UInt8_22_io_deq_bits : _T_4838 ? _Queue16_UInt8_21_io_deq_bits : _T_4837 ? _Queue16_UInt8_20_io_deq_bits : _T_4836 ? _Queue16_UInt8_19_io_deq_bits : _T_4835 ? _Queue16_UInt8_18_io_deq_bits : _T_4834 ? _Queue16_UInt8_17_io_deq_bits : _T_4833 ? _Queue16_UInt8_16_io_deq_bits : _T_4832 ? _Queue16_UInt8_15_io_deq_bits : _T_4831 ? _Queue16_UInt8_14_io_deq_bits : _T_4830 ? _Queue16_UInt8_13_io_deq_bits : _T_4829 ? _Queue16_UInt8_12_io_deq_bits : _T_4828 ? _Queue16_UInt8_11_io_deq_bits : _T_4827 ? _Queue16_UInt8_10_io_deq_bits : _T_4826 ? _Queue16_UInt8_9_io_deq_bits : _T_4825 ? _Queue16_UInt8_8_io_deq_bits : _T_4824 ? _Queue16_UInt8_7_io_deq_bits : _T_4823 ? _Queue16_UInt8_6_io_deq_bits : _T_4822 ? _Queue16_UInt8_5_io_deq_bits : _T_4821 ? _Queue16_UInt8_4_io_deq_bits : _T_4820 ? _Queue16_UInt8_3_io_deq_bits : _T_4819 ? _Queue16_UInt8_2_io_deq_bits : _T_4818 ? _Queue16_UInt8_1_io_deq_bits : _T_4817 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_valid : _T_4847 ? _Queue16_UInt8_30_io_deq_valid : _T_4846 ? _Queue16_UInt8_29_io_deq_valid : _T_4845 ? _Queue16_UInt8_28_io_deq_valid : _T_4844 ? _Queue16_UInt8_27_io_deq_valid : _T_4843 ? _Queue16_UInt8_26_io_deq_valid : _T_4842 ? _Queue16_UInt8_25_io_deq_valid : _T_4841 ? _Queue16_UInt8_24_io_deq_valid : _T_4840 ? _Queue16_UInt8_23_io_deq_valid : _T_4839 ? _Queue16_UInt8_22_io_deq_valid : _T_4838 ? _Queue16_UInt8_21_io_deq_valid : _T_4837 ? _Queue16_UInt8_20_io_deq_valid : _T_4836 ? _Queue16_UInt8_19_io_deq_valid : _T_4835 ? _Queue16_UInt8_18_io_deq_valid : _T_4834 ? _Queue16_UInt8_17_io_deq_valid : _T_4833 ? _Queue16_UInt8_16_io_deq_valid : _T_4832 ? _Queue16_UInt8_15_io_deq_valid : _T_4831 ? _Queue16_UInt8_14_io_deq_valid : _T_4830 ? _Queue16_UInt8_13_io_deq_valid : _T_4829 ? _Queue16_UInt8_12_io_deq_valid : _T_4828 ? _Queue16_UInt8_11_io_deq_valid : _T_4827 ? _Queue16_UInt8_10_io_deq_valid : _T_4826 ? _Queue16_UInt8_9_io_deq_valid : _T_4825 ? _Queue16_UInt8_8_io_deq_valid : _T_4824 ? _Queue16_UInt8_7_io_deq_valid : _T_4823 ? _Queue16_UInt8_6_io_deq_valid : _T_4822 ? _Queue16_UInt8_5_io_deq_valid : _T_4821 ? _Queue16_UInt8_4_io_deq_valid : _T_4820 ? _Queue16_UInt8_3_io_deq_valid : _T_4819 ? _Queue16_UInt8_2_io_deq_valid : _T_4818 ? _Queue16_UInt8_1_io_deq_valid : _T_4817 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_106 = _remapindex_T_16 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_16 = _GEN_106[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4849 = remapindex_16 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4850 = remapindex_16 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4851 = remapindex_16 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4852 = remapindex_16 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4853 = remapindex_16 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4854 = remapindex_16 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4855 = remapindex_16 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4856 = remapindex_16 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4857 = remapindex_16 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4858 = remapindex_16 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4859 = remapindex_16 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4860 = remapindex_16 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4861 = remapindex_16 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4862 = remapindex_16 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4863 = remapindex_16 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4864 = remapindex_16 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4865 = remapindex_16 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4866 = remapindex_16 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4867 = remapindex_16 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4868 = remapindex_16 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4869 = remapindex_16 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4870 = remapindex_16 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4871 = remapindex_16 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4872 = remapindex_16 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4873 = remapindex_16 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4874 = remapindex_16 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4875 = remapindex_16 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4876 = remapindex_16 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4877 = remapindex_16 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4878 = remapindex_16 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4879 = remapindex_16 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4880 = remapindex_16 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_bits : _T_4879 ? _Queue16_UInt8_30_io_deq_bits : _T_4878 ? _Queue16_UInt8_29_io_deq_bits : _T_4877 ? _Queue16_UInt8_28_io_deq_bits : _T_4876 ? _Queue16_UInt8_27_io_deq_bits : _T_4875 ? _Queue16_UInt8_26_io_deq_bits : _T_4874 ? _Queue16_UInt8_25_io_deq_bits : _T_4873 ? _Queue16_UInt8_24_io_deq_bits : _T_4872 ? _Queue16_UInt8_23_io_deq_bits : _T_4871 ? _Queue16_UInt8_22_io_deq_bits : _T_4870 ? _Queue16_UInt8_21_io_deq_bits : _T_4869 ? _Queue16_UInt8_20_io_deq_bits : _T_4868 ? _Queue16_UInt8_19_io_deq_bits : _T_4867 ? _Queue16_UInt8_18_io_deq_bits : _T_4866 ? _Queue16_UInt8_17_io_deq_bits : _T_4865 ? _Queue16_UInt8_16_io_deq_bits : _T_4864 ? _Queue16_UInt8_15_io_deq_bits : _T_4863 ? _Queue16_UInt8_14_io_deq_bits : _T_4862 ? _Queue16_UInt8_13_io_deq_bits : _T_4861 ? _Queue16_UInt8_12_io_deq_bits : _T_4860 ? _Queue16_UInt8_11_io_deq_bits : _T_4859 ? _Queue16_UInt8_10_io_deq_bits : _T_4858 ? _Queue16_UInt8_9_io_deq_bits : _T_4857 ? _Queue16_UInt8_8_io_deq_bits : _T_4856 ? _Queue16_UInt8_7_io_deq_bits : _T_4855 ? _Queue16_UInt8_6_io_deq_bits : _T_4854 ? _Queue16_UInt8_5_io_deq_bits : _T_4853 ? _Queue16_UInt8_4_io_deq_bits : _T_4852 ? _Queue16_UInt8_3_io_deq_bits : _T_4851 ? _Queue16_UInt8_2_io_deq_bits : _T_4850 ? _Queue16_UInt8_1_io_deq_bits : _T_4849 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_valid : _T_4879 ? _Queue16_UInt8_30_io_deq_valid : _T_4878 ? _Queue16_UInt8_29_io_deq_valid : _T_4877 ? _Queue16_UInt8_28_io_deq_valid : _T_4876 ? _Queue16_UInt8_27_io_deq_valid : _T_4875 ? _Queue16_UInt8_26_io_deq_valid : _T_4874 ? _Queue16_UInt8_25_io_deq_valid : _T_4873 ? _Queue16_UInt8_24_io_deq_valid : _T_4872 ? _Queue16_UInt8_23_io_deq_valid : _T_4871 ? _Queue16_UInt8_22_io_deq_valid : _T_4870 ? _Queue16_UInt8_21_io_deq_valid : _T_4869 ? _Queue16_UInt8_20_io_deq_valid : _T_4868 ? _Queue16_UInt8_19_io_deq_valid : _T_4867 ? _Queue16_UInt8_18_io_deq_valid : _T_4866 ? _Queue16_UInt8_17_io_deq_valid : _T_4865 ? _Queue16_UInt8_16_io_deq_valid : _T_4864 ? _Queue16_UInt8_15_io_deq_valid : _T_4863 ? _Queue16_UInt8_14_io_deq_valid : _T_4862 ? _Queue16_UInt8_13_io_deq_valid : _T_4861 ? _Queue16_UInt8_12_io_deq_valid : _T_4860 ? _Queue16_UInt8_11_io_deq_valid : _T_4859 ? _Queue16_UInt8_10_io_deq_valid : _T_4858 ? _Queue16_UInt8_9_io_deq_valid : _T_4857 ? _Queue16_UInt8_8_io_deq_valid : _T_4856 ? _Queue16_UInt8_7_io_deq_valid : _T_4855 ? _Queue16_UInt8_6_io_deq_valid : _T_4854 ? _Queue16_UInt8_5_io_deq_valid : _T_4853 ? _Queue16_UInt8_4_io_deq_valid : _T_4852 ? _Queue16_UInt8_3_io_deq_valid : _T_4851 ? _Queue16_UInt8_2_io_deq_valid : _T_4850 ? _Queue16_UInt8_1_io_deq_valid : _T_4849 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_107 = _remapindex_T_17 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_17 = _GEN_107[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4881 = remapindex_17 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4882 = remapindex_17 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4883 = remapindex_17 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4884 = remapindex_17 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4885 = remapindex_17 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4886 = remapindex_17 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4887 = remapindex_17 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4888 = remapindex_17 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4889 = remapindex_17 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4890 = remapindex_17 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4891 = remapindex_17 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4892 = remapindex_17 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4893 = remapindex_17 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4894 = remapindex_17 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4895 = remapindex_17 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4896 = remapindex_17 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4897 = remapindex_17 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4898 = remapindex_17 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4899 = remapindex_17 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4900 = remapindex_17 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4901 = remapindex_17 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4902 = remapindex_17 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4903 = remapindex_17 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4904 = remapindex_17 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4905 = remapindex_17 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4906 = remapindex_17 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4907 = remapindex_17 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4908 = remapindex_17 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4909 = remapindex_17 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4910 = remapindex_17 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4911 = remapindex_17 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4912 = remapindex_17 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_bits : _T_4911 ? _Queue16_UInt8_30_io_deq_bits : _T_4910 ? _Queue16_UInt8_29_io_deq_bits : _T_4909 ? _Queue16_UInt8_28_io_deq_bits : _T_4908 ? _Queue16_UInt8_27_io_deq_bits : _T_4907 ? _Queue16_UInt8_26_io_deq_bits : _T_4906 ? _Queue16_UInt8_25_io_deq_bits : _T_4905 ? _Queue16_UInt8_24_io_deq_bits : _T_4904 ? _Queue16_UInt8_23_io_deq_bits : _T_4903 ? _Queue16_UInt8_22_io_deq_bits : _T_4902 ? _Queue16_UInt8_21_io_deq_bits : _T_4901 ? _Queue16_UInt8_20_io_deq_bits : _T_4900 ? _Queue16_UInt8_19_io_deq_bits : _T_4899 ? _Queue16_UInt8_18_io_deq_bits : _T_4898 ? _Queue16_UInt8_17_io_deq_bits : _T_4897 ? _Queue16_UInt8_16_io_deq_bits : _T_4896 ? _Queue16_UInt8_15_io_deq_bits : _T_4895 ? _Queue16_UInt8_14_io_deq_bits : _T_4894 ? _Queue16_UInt8_13_io_deq_bits : _T_4893 ? _Queue16_UInt8_12_io_deq_bits : _T_4892 ? _Queue16_UInt8_11_io_deq_bits : _T_4891 ? _Queue16_UInt8_10_io_deq_bits : _T_4890 ? _Queue16_UInt8_9_io_deq_bits : _T_4889 ? _Queue16_UInt8_8_io_deq_bits : _T_4888 ? _Queue16_UInt8_7_io_deq_bits : _T_4887 ? _Queue16_UInt8_6_io_deq_bits : _T_4886 ? _Queue16_UInt8_5_io_deq_bits : _T_4885 ? _Queue16_UInt8_4_io_deq_bits : _T_4884 ? _Queue16_UInt8_3_io_deq_bits : _T_4883 ? _Queue16_UInt8_2_io_deq_bits : _T_4882 ? _Queue16_UInt8_1_io_deq_bits : _T_4881 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_valid : _T_4911 ? _Queue16_UInt8_30_io_deq_valid : _T_4910 ? _Queue16_UInt8_29_io_deq_valid : _T_4909 ? _Queue16_UInt8_28_io_deq_valid : _T_4908 ? _Queue16_UInt8_27_io_deq_valid : _T_4907 ? _Queue16_UInt8_26_io_deq_valid : _T_4906 ? _Queue16_UInt8_25_io_deq_valid : _T_4905 ? _Queue16_UInt8_24_io_deq_valid : _T_4904 ? _Queue16_UInt8_23_io_deq_valid : _T_4903 ? _Queue16_UInt8_22_io_deq_valid : _T_4902 ? _Queue16_UInt8_21_io_deq_valid : _T_4901 ? _Queue16_UInt8_20_io_deq_valid : _T_4900 ? _Queue16_UInt8_19_io_deq_valid : _T_4899 ? _Queue16_UInt8_18_io_deq_valid : _T_4898 ? _Queue16_UInt8_17_io_deq_valid : _T_4897 ? _Queue16_UInt8_16_io_deq_valid : _T_4896 ? _Queue16_UInt8_15_io_deq_valid : _T_4895 ? _Queue16_UInt8_14_io_deq_valid : _T_4894 ? _Queue16_UInt8_13_io_deq_valid : _T_4893 ? _Queue16_UInt8_12_io_deq_valid : _T_4892 ? _Queue16_UInt8_11_io_deq_valid : _T_4891 ? _Queue16_UInt8_10_io_deq_valid : _T_4890 ? _Queue16_UInt8_9_io_deq_valid : _T_4889 ? _Queue16_UInt8_8_io_deq_valid : _T_4888 ? _Queue16_UInt8_7_io_deq_valid : _T_4887 ? _Queue16_UInt8_6_io_deq_valid : _T_4886 ? _Queue16_UInt8_5_io_deq_valid : _T_4885 ? _Queue16_UInt8_4_io_deq_valid : _T_4884 ? _Queue16_UInt8_3_io_deq_valid : _T_4883 ? _Queue16_UInt8_2_io_deq_valid : _T_4882 ? _Queue16_UInt8_1_io_deq_valid : _T_4881 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_108 = _remapindex_T_18 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_18 = _GEN_108[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4913 = remapindex_18 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4914 = remapindex_18 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4915 = remapindex_18 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4916 = remapindex_18 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4917 = remapindex_18 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4918 = remapindex_18 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4919 = remapindex_18 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4920 = remapindex_18 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4921 = remapindex_18 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4922 = remapindex_18 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4923 = remapindex_18 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4924 = remapindex_18 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4925 = remapindex_18 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4926 = remapindex_18 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4927 = remapindex_18 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4928 = remapindex_18 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4929 = remapindex_18 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4930 = remapindex_18 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4931 = remapindex_18 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4932 = remapindex_18 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4933 = remapindex_18 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4934 = remapindex_18 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4935 = remapindex_18 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4936 = remapindex_18 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4937 = remapindex_18 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4938 = remapindex_18 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4939 = remapindex_18 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4940 = remapindex_18 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4941 = remapindex_18 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4942 = remapindex_18 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4943 = remapindex_18 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4944 = remapindex_18 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_bits : _T_4943 ? _Queue16_UInt8_30_io_deq_bits : _T_4942 ? _Queue16_UInt8_29_io_deq_bits : _T_4941 ? _Queue16_UInt8_28_io_deq_bits : _T_4940 ? _Queue16_UInt8_27_io_deq_bits : _T_4939 ? _Queue16_UInt8_26_io_deq_bits : _T_4938 ? _Queue16_UInt8_25_io_deq_bits : _T_4937 ? _Queue16_UInt8_24_io_deq_bits : _T_4936 ? _Queue16_UInt8_23_io_deq_bits : _T_4935 ? _Queue16_UInt8_22_io_deq_bits : _T_4934 ? _Queue16_UInt8_21_io_deq_bits : _T_4933 ? _Queue16_UInt8_20_io_deq_bits : _T_4932 ? _Queue16_UInt8_19_io_deq_bits : _T_4931 ? _Queue16_UInt8_18_io_deq_bits : _T_4930 ? _Queue16_UInt8_17_io_deq_bits : _T_4929 ? _Queue16_UInt8_16_io_deq_bits : _T_4928 ? _Queue16_UInt8_15_io_deq_bits : _T_4927 ? _Queue16_UInt8_14_io_deq_bits : _T_4926 ? _Queue16_UInt8_13_io_deq_bits : _T_4925 ? _Queue16_UInt8_12_io_deq_bits : _T_4924 ? _Queue16_UInt8_11_io_deq_bits : _T_4923 ? _Queue16_UInt8_10_io_deq_bits : _T_4922 ? _Queue16_UInt8_9_io_deq_bits : _T_4921 ? _Queue16_UInt8_8_io_deq_bits : _T_4920 ? _Queue16_UInt8_7_io_deq_bits : _T_4919 ? _Queue16_UInt8_6_io_deq_bits : _T_4918 ? _Queue16_UInt8_5_io_deq_bits : _T_4917 ? _Queue16_UInt8_4_io_deq_bits : _T_4916 ? _Queue16_UInt8_3_io_deq_bits : _T_4915 ? _Queue16_UInt8_2_io_deq_bits : _T_4914 ? _Queue16_UInt8_1_io_deq_bits : _T_4913 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_valid : _T_4943 ? _Queue16_UInt8_30_io_deq_valid : _T_4942 ? _Queue16_UInt8_29_io_deq_valid : _T_4941 ? _Queue16_UInt8_28_io_deq_valid : _T_4940 ? _Queue16_UInt8_27_io_deq_valid : _T_4939 ? _Queue16_UInt8_26_io_deq_valid : _T_4938 ? _Queue16_UInt8_25_io_deq_valid : _T_4937 ? _Queue16_UInt8_24_io_deq_valid : _T_4936 ? _Queue16_UInt8_23_io_deq_valid : _T_4935 ? _Queue16_UInt8_22_io_deq_valid : _T_4934 ? _Queue16_UInt8_21_io_deq_valid : _T_4933 ? _Queue16_UInt8_20_io_deq_valid : _T_4932 ? _Queue16_UInt8_19_io_deq_valid : _T_4931 ? _Queue16_UInt8_18_io_deq_valid : _T_4930 ? _Queue16_UInt8_17_io_deq_valid : _T_4929 ? _Queue16_UInt8_16_io_deq_valid : _T_4928 ? _Queue16_UInt8_15_io_deq_valid : _T_4927 ? _Queue16_UInt8_14_io_deq_valid : _T_4926 ? _Queue16_UInt8_13_io_deq_valid : _T_4925 ? _Queue16_UInt8_12_io_deq_valid : _T_4924 ? _Queue16_UInt8_11_io_deq_valid : _T_4923 ? _Queue16_UInt8_10_io_deq_valid : _T_4922 ? _Queue16_UInt8_9_io_deq_valid : _T_4921 ? _Queue16_UInt8_8_io_deq_valid : _T_4920 ? _Queue16_UInt8_7_io_deq_valid : _T_4919 ? _Queue16_UInt8_6_io_deq_valid : _T_4918 ? _Queue16_UInt8_5_io_deq_valid : _T_4917 ? _Queue16_UInt8_4_io_deq_valid : _T_4916 ? _Queue16_UInt8_3_io_deq_valid : _T_4915 ? _Queue16_UInt8_2_io_deq_valid : _T_4914 ? _Queue16_UInt8_1_io_deq_valid : _T_4913 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_109 = _remapindex_T_19 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_19 = _GEN_109[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4945 = remapindex_19 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4946 = remapindex_19 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4947 = remapindex_19 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4948 = remapindex_19 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4949 = remapindex_19 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4950 = remapindex_19 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4951 = remapindex_19 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4952 = remapindex_19 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4953 = remapindex_19 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4954 = remapindex_19 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4955 = remapindex_19 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4956 = remapindex_19 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4957 = remapindex_19 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4958 = remapindex_19 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4959 = remapindex_19 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4960 = remapindex_19 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4961 = remapindex_19 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4962 = remapindex_19 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4963 = remapindex_19 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4964 = remapindex_19 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4965 = remapindex_19 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4966 = remapindex_19 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4967 = remapindex_19 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4968 = remapindex_19 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4969 = remapindex_19 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4970 = remapindex_19 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4971 = remapindex_19 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4972 = remapindex_19 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4973 = remapindex_19 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4974 = remapindex_19 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4975 = remapindex_19 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4976 = remapindex_19 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_bits : _T_4975 ? _Queue16_UInt8_30_io_deq_bits : _T_4974 ? _Queue16_UInt8_29_io_deq_bits : _T_4973 ? _Queue16_UInt8_28_io_deq_bits : _T_4972 ? _Queue16_UInt8_27_io_deq_bits : _T_4971 ? _Queue16_UInt8_26_io_deq_bits : _T_4970 ? _Queue16_UInt8_25_io_deq_bits : _T_4969 ? _Queue16_UInt8_24_io_deq_bits : _T_4968 ? _Queue16_UInt8_23_io_deq_bits : _T_4967 ? _Queue16_UInt8_22_io_deq_bits : _T_4966 ? _Queue16_UInt8_21_io_deq_bits : _T_4965 ? _Queue16_UInt8_20_io_deq_bits : _T_4964 ? _Queue16_UInt8_19_io_deq_bits : _T_4963 ? _Queue16_UInt8_18_io_deq_bits : _T_4962 ? _Queue16_UInt8_17_io_deq_bits : _T_4961 ? _Queue16_UInt8_16_io_deq_bits : _T_4960 ? _Queue16_UInt8_15_io_deq_bits : _T_4959 ? _Queue16_UInt8_14_io_deq_bits : _T_4958 ? _Queue16_UInt8_13_io_deq_bits : _T_4957 ? _Queue16_UInt8_12_io_deq_bits : _T_4956 ? _Queue16_UInt8_11_io_deq_bits : _T_4955 ? _Queue16_UInt8_10_io_deq_bits : _T_4954 ? _Queue16_UInt8_9_io_deq_bits : _T_4953 ? _Queue16_UInt8_8_io_deq_bits : _T_4952 ? _Queue16_UInt8_7_io_deq_bits : _T_4951 ? _Queue16_UInt8_6_io_deq_bits : _T_4950 ? _Queue16_UInt8_5_io_deq_bits : _T_4949 ? _Queue16_UInt8_4_io_deq_bits : _T_4948 ? _Queue16_UInt8_3_io_deq_bits : _T_4947 ? _Queue16_UInt8_2_io_deq_bits : _T_4946 ? _Queue16_UInt8_1_io_deq_bits : _T_4945 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_valid : _T_4975 ? _Queue16_UInt8_30_io_deq_valid : _T_4974 ? _Queue16_UInt8_29_io_deq_valid : _T_4973 ? _Queue16_UInt8_28_io_deq_valid : _T_4972 ? _Queue16_UInt8_27_io_deq_valid : _T_4971 ? _Queue16_UInt8_26_io_deq_valid : _T_4970 ? _Queue16_UInt8_25_io_deq_valid : _T_4969 ? _Queue16_UInt8_24_io_deq_valid : _T_4968 ? _Queue16_UInt8_23_io_deq_valid : _T_4967 ? _Queue16_UInt8_22_io_deq_valid : _T_4966 ? _Queue16_UInt8_21_io_deq_valid : _T_4965 ? _Queue16_UInt8_20_io_deq_valid : _T_4964 ? _Queue16_UInt8_19_io_deq_valid : _T_4963 ? _Queue16_UInt8_18_io_deq_valid : _T_4962 ? _Queue16_UInt8_17_io_deq_valid : _T_4961 ? _Queue16_UInt8_16_io_deq_valid : _T_4960 ? _Queue16_UInt8_15_io_deq_valid : _T_4959 ? _Queue16_UInt8_14_io_deq_valid : _T_4958 ? _Queue16_UInt8_13_io_deq_valid : _T_4957 ? _Queue16_UInt8_12_io_deq_valid : _T_4956 ? _Queue16_UInt8_11_io_deq_valid : _T_4955 ? _Queue16_UInt8_10_io_deq_valid : _T_4954 ? _Queue16_UInt8_9_io_deq_valid : _T_4953 ? _Queue16_UInt8_8_io_deq_valid : _T_4952 ? _Queue16_UInt8_7_io_deq_valid : _T_4951 ? _Queue16_UInt8_6_io_deq_valid : _T_4950 ? _Queue16_UInt8_5_io_deq_valid : _T_4949 ? _Queue16_UInt8_4_io_deq_valid : _T_4948 ? _Queue16_UInt8_3_io_deq_valid : _T_4947 ? _Queue16_UInt8_2_io_deq_valid : _T_4946 ? _Queue16_UInt8_1_io_deq_valid : _T_4945 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_110 = _remapindex_T_20 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_20 = _GEN_110[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_4977 = remapindex_20 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4978 = remapindex_20 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4979 = remapindex_20 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4980 = remapindex_20 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4981 = remapindex_20 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4982 = remapindex_20 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4983 = remapindex_20 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4984 = remapindex_20 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4985 = remapindex_20 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4986 = remapindex_20 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4987 = remapindex_20 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4988 = remapindex_20 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4989 = remapindex_20 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4990 = remapindex_20 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4991 = remapindex_20 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4992 = remapindex_20 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4993 = remapindex_20 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4994 = remapindex_20 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4995 = remapindex_20 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4996 = remapindex_20 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4997 = remapindex_20 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4998 = remapindex_20 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_4999 = remapindex_20 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5000 = remapindex_20 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5001 = remapindex_20 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5002 = remapindex_20 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5003 = remapindex_20 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5004 = remapindex_20 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5005 = remapindex_20 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5006 = remapindex_20 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5007 = remapindex_20 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5008 = remapindex_20 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_bits : _T_5007 ? _Queue16_UInt8_30_io_deq_bits : _T_5006 ? _Queue16_UInt8_29_io_deq_bits : _T_5005 ? _Queue16_UInt8_28_io_deq_bits : _T_5004 ? _Queue16_UInt8_27_io_deq_bits : _T_5003 ? _Queue16_UInt8_26_io_deq_bits : _T_5002 ? _Queue16_UInt8_25_io_deq_bits : _T_5001 ? _Queue16_UInt8_24_io_deq_bits : _T_5000 ? _Queue16_UInt8_23_io_deq_bits : _T_4999 ? _Queue16_UInt8_22_io_deq_bits : _T_4998 ? _Queue16_UInt8_21_io_deq_bits : _T_4997 ? _Queue16_UInt8_20_io_deq_bits : _T_4996 ? _Queue16_UInt8_19_io_deq_bits : _T_4995 ? _Queue16_UInt8_18_io_deq_bits : _T_4994 ? _Queue16_UInt8_17_io_deq_bits : _T_4993 ? _Queue16_UInt8_16_io_deq_bits : _T_4992 ? _Queue16_UInt8_15_io_deq_bits : _T_4991 ? _Queue16_UInt8_14_io_deq_bits : _T_4990 ? _Queue16_UInt8_13_io_deq_bits : _T_4989 ? _Queue16_UInt8_12_io_deq_bits : _T_4988 ? _Queue16_UInt8_11_io_deq_bits : _T_4987 ? _Queue16_UInt8_10_io_deq_bits : _T_4986 ? _Queue16_UInt8_9_io_deq_bits : _T_4985 ? _Queue16_UInt8_8_io_deq_bits : _T_4984 ? _Queue16_UInt8_7_io_deq_bits : _T_4983 ? _Queue16_UInt8_6_io_deq_bits : _T_4982 ? _Queue16_UInt8_5_io_deq_bits : _T_4981 ? _Queue16_UInt8_4_io_deq_bits : _T_4980 ? _Queue16_UInt8_3_io_deq_bits : _T_4979 ? _Queue16_UInt8_2_io_deq_bits : _T_4978 ? _Queue16_UInt8_1_io_deq_bits : _T_4977 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_valid : _T_5007 ? _Queue16_UInt8_30_io_deq_valid : _T_5006 ? _Queue16_UInt8_29_io_deq_valid : _T_5005 ? _Queue16_UInt8_28_io_deq_valid : _T_5004 ? _Queue16_UInt8_27_io_deq_valid : _T_5003 ? _Queue16_UInt8_26_io_deq_valid : _T_5002 ? _Queue16_UInt8_25_io_deq_valid : _T_5001 ? _Queue16_UInt8_24_io_deq_valid : _T_5000 ? _Queue16_UInt8_23_io_deq_valid : _T_4999 ? _Queue16_UInt8_22_io_deq_valid : _T_4998 ? _Queue16_UInt8_21_io_deq_valid : _T_4997 ? _Queue16_UInt8_20_io_deq_valid : _T_4996 ? _Queue16_UInt8_19_io_deq_valid : _T_4995 ? _Queue16_UInt8_18_io_deq_valid : _T_4994 ? _Queue16_UInt8_17_io_deq_valid : _T_4993 ? _Queue16_UInt8_16_io_deq_valid : _T_4992 ? _Queue16_UInt8_15_io_deq_valid : _T_4991 ? _Queue16_UInt8_14_io_deq_valid : _T_4990 ? _Queue16_UInt8_13_io_deq_valid : _T_4989 ? _Queue16_UInt8_12_io_deq_valid : _T_4988 ? _Queue16_UInt8_11_io_deq_valid : _T_4987 ? _Queue16_UInt8_10_io_deq_valid : _T_4986 ? _Queue16_UInt8_9_io_deq_valid : _T_4985 ? _Queue16_UInt8_8_io_deq_valid : _T_4984 ? _Queue16_UInt8_7_io_deq_valid : _T_4983 ? _Queue16_UInt8_6_io_deq_valid : _T_4982 ? _Queue16_UInt8_5_io_deq_valid : _T_4981 ? _Queue16_UInt8_4_io_deq_valid : _T_4980 ? _Queue16_UInt8_3_io_deq_valid : _T_4979 ? _Queue16_UInt8_2_io_deq_valid : _T_4978 ? _Queue16_UInt8_1_io_deq_valid : _T_4977 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_111 = _remapindex_T_21 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_21 = _GEN_111[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5009 = remapindex_21 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5010 = remapindex_21 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5011 = remapindex_21 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5012 = remapindex_21 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5013 = remapindex_21 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5014 = remapindex_21 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5015 = remapindex_21 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5016 = remapindex_21 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5017 = remapindex_21 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5018 = remapindex_21 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5019 = remapindex_21 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5020 = remapindex_21 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5021 = remapindex_21 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5022 = remapindex_21 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5023 = remapindex_21 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5024 = remapindex_21 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5025 = remapindex_21 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5026 = remapindex_21 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5027 = remapindex_21 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5028 = remapindex_21 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5029 = remapindex_21 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5030 = remapindex_21 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5031 = remapindex_21 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5032 = remapindex_21 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5033 = remapindex_21 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5034 = remapindex_21 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5035 = remapindex_21 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5036 = remapindex_21 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5037 = remapindex_21 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5038 = remapindex_21 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5039 = remapindex_21 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5040 = remapindex_21 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_bits : _T_5039 ? _Queue16_UInt8_30_io_deq_bits : _T_5038 ? _Queue16_UInt8_29_io_deq_bits : _T_5037 ? _Queue16_UInt8_28_io_deq_bits : _T_5036 ? _Queue16_UInt8_27_io_deq_bits : _T_5035 ? _Queue16_UInt8_26_io_deq_bits : _T_5034 ? _Queue16_UInt8_25_io_deq_bits : _T_5033 ? _Queue16_UInt8_24_io_deq_bits : _T_5032 ? _Queue16_UInt8_23_io_deq_bits : _T_5031 ? _Queue16_UInt8_22_io_deq_bits : _T_5030 ? _Queue16_UInt8_21_io_deq_bits : _T_5029 ? _Queue16_UInt8_20_io_deq_bits : _T_5028 ? _Queue16_UInt8_19_io_deq_bits : _T_5027 ? _Queue16_UInt8_18_io_deq_bits : _T_5026 ? _Queue16_UInt8_17_io_deq_bits : _T_5025 ? _Queue16_UInt8_16_io_deq_bits : _T_5024 ? _Queue16_UInt8_15_io_deq_bits : _T_5023 ? _Queue16_UInt8_14_io_deq_bits : _T_5022 ? _Queue16_UInt8_13_io_deq_bits : _T_5021 ? _Queue16_UInt8_12_io_deq_bits : _T_5020 ? _Queue16_UInt8_11_io_deq_bits : _T_5019 ? _Queue16_UInt8_10_io_deq_bits : _T_5018 ? _Queue16_UInt8_9_io_deq_bits : _T_5017 ? _Queue16_UInt8_8_io_deq_bits : _T_5016 ? _Queue16_UInt8_7_io_deq_bits : _T_5015 ? _Queue16_UInt8_6_io_deq_bits : _T_5014 ? _Queue16_UInt8_5_io_deq_bits : _T_5013 ? _Queue16_UInt8_4_io_deq_bits : _T_5012 ? _Queue16_UInt8_3_io_deq_bits : _T_5011 ? _Queue16_UInt8_2_io_deq_bits : _T_5010 ? _Queue16_UInt8_1_io_deq_bits : _T_5009 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_valid : _T_5039 ? _Queue16_UInt8_30_io_deq_valid : _T_5038 ? _Queue16_UInt8_29_io_deq_valid : _T_5037 ? _Queue16_UInt8_28_io_deq_valid : _T_5036 ? _Queue16_UInt8_27_io_deq_valid : _T_5035 ? _Queue16_UInt8_26_io_deq_valid : _T_5034 ? _Queue16_UInt8_25_io_deq_valid : _T_5033 ? _Queue16_UInt8_24_io_deq_valid : _T_5032 ? _Queue16_UInt8_23_io_deq_valid : _T_5031 ? _Queue16_UInt8_22_io_deq_valid : _T_5030 ? _Queue16_UInt8_21_io_deq_valid : _T_5029 ? _Queue16_UInt8_20_io_deq_valid : _T_5028 ? _Queue16_UInt8_19_io_deq_valid : _T_5027 ? _Queue16_UInt8_18_io_deq_valid : _T_5026 ? _Queue16_UInt8_17_io_deq_valid : _T_5025 ? _Queue16_UInt8_16_io_deq_valid : _T_5024 ? _Queue16_UInt8_15_io_deq_valid : _T_5023 ? _Queue16_UInt8_14_io_deq_valid : _T_5022 ? _Queue16_UInt8_13_io_deq_valid : _T_5021 ? _Queue16_UInt8_12_io_deq_valid : _T_5020 ? _Queue16_UInt8_11_io_deq_valid : _T_5019 ? _Queue16_UInt8_10_io_deq_valid : _T_5018 ? _Queue16_UInt8_9_io_deq_valid : _T_5017 ? _Queue16_UInt8_8_io_deq_valid : _T_5016 ? _Queue16_UInt8_7_io_deq_valid : _T_5015 ? _Queue16_UInt8_6_io_deq_valid : _T_5014 ? _Queue16_UInt8_5_io_deq_valid : _T_5013 ? _Queue16_UInt8_4_io_deq_valid : _T_5012 ? _Queue16_UInt8_3_io_deq_valid : _T_5011 ? _Queue16_UInt8_2_io_deq_valid : _T_5010 ? _Queue16_UInt8_1_io_deq_valid : _T_5009 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_112 = _remapindex_T_22 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_22 = _GEN_112[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5041 = remapindex_22 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5042 = remapindex_22 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5043 = remapindex_22 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5044 = remapindex_22 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5045 = remapindex_22 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5046 = remapindex_22 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5047 = remapindex_22 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5048 = remapindex_22 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5049 = remapindex_22 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5050 = remapindex_22 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5051 = remapindex_22 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5052 = remapindex_22 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5053 = remapindex_22 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5054 = remapindex_22 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5055 = remapindex_22 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5056 = remapindex_22 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5057 = remapindex_22 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5058 = remapindex_22 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5059 = remapindex_22 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5060 = remapindex_22 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5061 = remapindex_22 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5062 = remapindex_22 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5063 = remapindex_22 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5064 = remapindex_22 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5065 = remapindex_22 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5066 = remapindex_22 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5067 = remapindex_22 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5068 = remapindex_22 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5069 = remapindex_22 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5070 = remapindex_22 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5071 = remapindex_22 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5072 = remapindex_22 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_bits : _T_5071 ? _Queue16_UInt8_30_io_deq_bits : _T_5070 ? _Queue16_UInt8_29_io_deq_bits : _T_5069 ? _Queue16_UInt8_28_io_deq_bits : _T_5068 ? _Queue16_UInt8_27_io_deq_bits : _T_5067 ? _Queue16_UInt8_26_io_deq_bits : _T_5066 ? _Queue16_UInt8_25_io_deq_bits : _T_5065 ? _Queue16_UInt8_24_io_deq_bits : _T_5064 ? _Queue16_UInt8_23_io_deq_bits : _T_5063 ? _Queue16_UInt8_22_io_deq_bits : _T_5062 ? _Queue16_UInt8_21_io_deq_bits : _T_5061 ? _Queue16_UInt8_20_io_deq_bits : _T_5060 ? _Queue16_UInt8_19_io_deq_bits : _T_5059 ? _Queue16_UInt8_18_io_deq_bits : _T_5058 ? _Queue16_UInt8_17_io_deq_bits : _T_5057 ? _Queue16_UInt8_16_io_deq_bits : _T_5056 ? _Queue16_UInt8_15_io_deq_bits : _T_5055 ? _Queue16_UInt8_14_io_deq_bits : _T_5054 ? _Queue16_UInt8_13_io_deq_bits : _T_5053 ? _Queue16_UInt8_12_io_deq_bits : _T_5052 ? _Queue16_UInt8_11_io_deq_bits : _T_5051 ? _Queue16_UInt8_10_io_deq_bits : _T_5050 ? _Queue16_UInt8_9_io_deq_bits : _T_5049 ? _Queue16_UInt8_8_io_deq_bits : _T_5048 ? _Queue16_UInt8_7_io_deq_bits : _T_5047 ? _Queue16_UInt8_6_io_deq_bits : _T_5046 ? _Queue16_UInt8_5_io_deq_bits : _T_5045 ? _Queue16_UInt8_4_io_deq_bits : _T_5044 ? _Queue16_UInt8_3_io_deq_bits : _T_5043 ? _Queue16_UInt8_2_io_deq_bits : _T_5042 ? _Queue16_UInt8_1_io_deq_bits : _T_5041 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_valid : _T_5071 ? _Queue16_UInt8_30_io_deq_valid : _T_5070 ? _Queue16_UInt8_29_io_deq_valid : _T_5069 ? _Queue16_UInt8_28_io_deq_valid : _T_5068 ? _Queue16_UInt8_27_io_deq_valid : _T_5067 ? _Queue16_UInt8_26_io_deq_valid : _T_5066 ? _Queue16_UInt8_25_io_deq_valid : _T_5065 ? _Queue16_UInt8_24_io_deq_valid : _T_5064 ? _Queue16_UInt8_23_io_deq_valid : _T_5063 ? _Queue16_UInt8_22_io_deq_valid : _T_5062 ? _Queue16_UInt8_21_io_deq_valid : _T_5061 ? _Queue16_UInt8_20_io_deq_valid : _T_5060 ? _Queue16_UInt8_19_io_deq_valid : _T_5059 ? _Queue16_UInt8_18_io_deq_valid : _T_5058 ? _Queue16_UInt8_17_io_deq_valid : _T_5057 ? _Queue16_UInt8_16_io_deq_valid : _T_5056 ? _Queue16_UInt8_15_io_deq_valid : _T_5055 ? _Queue16_UInt8_14_io_deq_valid : _T_5054 ? _Queue16_UInt8_13_io_deq_valid : _T_5053 ? _Queue16_UInt8_12_io_deq_valid : _T_5052 ? _Queue16_UInt8_11_io_deq_valid : _T_5051 ? _Queue16_UInt8_10_io_deq_valid : _T_5050 ? _Queue16_UInt8_9_io_deq_valid : _T_5049 ? _Queue16_UInt8_8_io_deq_valid : _T_5048 ? _Queue16_UInt8_7_io_deq_valid : _T_5047 ? _Queue16_UInt8_6_io_deq_valid : _T_5046 ? _Queue16_UInt8_5_io_deq_valid : _T_5045 ? _Queue16_UInt8_4_io_deq_valid : _T_5044 ? _Queue16_UInt8_3_io_deq_valid : _T_5043 ? _Queue16_UInt8_2_io_deq_valid : _T_5042 ? _Queue16_UInt8_1_io_deq_valid : _T_5041 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_113 = _remapindex_T_23 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_23 = _GEN_113[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5073 = remapindex_23 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5074 = remapindex_23 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5075 = remapindex_23 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5076 = remapindex_23 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5077 = remapindex_23 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5078 = remapindex_23 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5079 = remapindex_23 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5080 = remapindex_23 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5081 = remapindex_23 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5082 = remapindex_23 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5083 = remapindex_23 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5084 = remapindex_23 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5085 = remapindex_23 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5086 = remapindex_23 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5087 = remapindex_23 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5088 = remapindex_23 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5089 = remapindex_23 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5090 = remapindex_23 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5091 = remapindex_23 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5092 = remapindex_23 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5093 = remapindex_23 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5094 = remapindex_23 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5095 = remapindex_23 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5096 = remapindex_23 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5097 = remapindex_23 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5098 = remapindex_23 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5099 = remapindex_23 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5100 = remapindex_23 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5101 = remapindex_23 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5102 = remapindex_23 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5103 = remapindex_23 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5104 = remapindex_23 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_bits : _T_5103 ? _Queue16_UInt8_30_io_deq_bits : _T_5102 ? _Queue16_UInt8_29_io_deq_bits : _T_5101 ? _Queue16_UInt8_28_io_deq_bits : _T_5100 ? _Queue16_UInt8_27_io_deq_bits : _T_5099 ? _Queue16_UInt8_26_io_deq_bits : _T_5098 ? _Queue16_UInt8_25_io_deq_bits : _T_5097 ? _Queue16_UInt8_24_io_deq_bits : _T_5096 ? _Queue16_UInt8_23_io_deq_bits : _T_5095 ? _Queue16_UInt8_22_io_deq_bits : _T_5094 ? _Queue16_UInt8_21_io_deq_bits : _T_5093 ? _Queue16_UInt8_20_io_deq_bits : _T_5092 ? _Queue16_UInt8_19_io_deq_bits : _T_5091 ? _Queue16_UInt8_18_io_deq_bits : _T_5090 ? _Queue16_UInt8_17_io_deq_bits : _T_5089 ? _Queue16_UInt8_16_io_deq_bits : _T_5088 ? _Queue16_UInt8_15_io_deq_bits : _T_5087 ? _Queue16_UInt8_14_io_deq_bits : _T_5086 ? _Queue16_UInt8_13_io_deq_bits : _T_5085 ? _Queue16_UInt8_12_io_deq_bits : _T_5084 ? _Queue16_UInt8_11_io_deq_bits : _T_5083 ? _Queue16_UInt8_10_io_deq_bits : _T_5082 ? _Queue16_UInt8_9_io_deq_bits : _T_5081 ? _Queue16_UInt8_8_io_deq_bits : _T_5080 ? _Queue16_UInt8_7_io_deq_bits : _T_5079 ? _Queue16_UInt8_6_io_deq_bits : _T_5078 ? _Queue16_UInt8_5_io_deq_bits : _T_5077 ? _Queue16_UInt8_4_io_deq_bits : _T_5076 ? _Queue16_UInt8_3_io_deq_bits : _T_5075 ? _Queue16_UInt8_2_io_deq_bits : _T_5074 ? _Queue16_UInt8_1_io_deq_bits : _T_5073 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_valid : _T_5103 ? _Queue16_UInt8_30_io_deq_valid : _T_5102 ? _Queue16_UInt8_29_io_deq_valid : _T_5101 ? _Queue16_UInt8_28_io_deq_valid : _T_5100 ? _Queue16_UInt8_27_io_deq_valid : _T_5099 ? _Queue16_UInt8_26_io_deq_valid : _T_5098 ? _Queue16_UInt8_25_io_deq_valid : _T_5097 ? _Queue16_UInt8_24_io_deq_valid : _T_5096 ? _Queue16_UInt8_23_io_deq_valid : _T_5095 ? _Queue16_UInt8_22_io_deq_valid : _T_5094 ? _Queue16_UInt8_21_io_deq_valid : _T_5093 ? _Queue16_UInt8_20_io_deq_valid : _T_5092 ? _Queue16_UInt8_19_io_deq_valid : _T_5091 ? _Queue16_UInt8_18_io_deq_valid : _T_5090 ? _Queue16_UInt8_17_io_deq_valid : _T_5089 ? _Queue16_UInt8_16_io_deq_valid : _T_5088 ? _Queue16_UInt8_15_io_deq_valid : _T_5087 ? _Queue16_UInt8_14_io_deq_valid : _T_5086 ? _Queue16_UInt8_13_io_deq_valid : _T_5085 ? _Queue16_UInt8_12_io_deq_valid : _T_5084 ? _Queue16_UInt8_11_io_deq_valid : _T_5083 ? _Queue16_UInt8_10_io_deq_valid : _T_5082 ? _Queue16_UInt8_9_io_deq_valid : _T_5081 ? _Queue16_UInt8_8_io_deq_valid : _T_5080 ? _Queue16_UInt8_7_io_deq_valid : _T_5079 ? _Queue16_UInt8_6_io_deq_valid : _T_5078 ? _Queue16_UInt8_5_io_deq_valid : _T_5077 ? _Queue16_UInt8_4_io_deq_valid : _T_5076 ? _Queue16_UInt8_3_io_deq_valid : _T_5075 ? _Queue16_UInt8_2_io_deq_valid : _T_5074 ? _Queue16_UInt8_1_io_deq_valid : _T_5073 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_114 = _remapindex_T_24 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_24 = _GEN_114[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5105 = remapindex_24 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5106 = remapindex_24 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5107 = remapindex_24 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5108 = remapindex_24 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5109 = remapindex_24 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5110 = remapindex_24 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5111 = remapindex_24 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5112 = remapindex_24 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5113 = remapindex_24 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5114 = remapindex_24 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5115 = remapindex_24 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5116 = remapindex_24 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5117 = remapindex_24 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5118 = remapindex_24 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5119 = remapindex_24 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5120 = remapindex_24 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5121 = remapindex_24 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5122 = remapindex_24 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5123 = remapindex_24 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5124 = remapindex_24 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5125 = remapindex_24 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5126 = remapindex_24 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5127 = remapindex_24 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5128 = remapindex_24 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5129 = remapindex_24 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5130 = remapindex_24 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5131 = remapindex_24 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5132 = remapindex_24 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5133 = remapindex_24 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5134 = remapindex_24 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5135 = remapindex_24 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5136 = remapindex_24 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_bits : _T_5135 ? _Queue16_UInt8_30_io_deq_bits : _T_5134 ? _Queue16_UInt8_29_io_deq_bits : _T_5133 ? _Queue16_UInt8_28_io_deq_bits : _T_5132 ? _Queue16_UInt8_27_io_deq_bits : _T_5131 ? _Queue16_UInt8_26_io_deq_bits : _T_5130 ? _Queue16_UInt8_25_io_deq_bits : _T_5129 ? _Queue16_UInt8_24_io_deq_bits : _T_5128 ? _Queue16_UInt8_23_io_deq_bits : _T_5127 ? _Queue16_UInt8_22_io_deq_bits : _T_5126 ? _Queue16_UInt8_21_io_deq_bits : _T_5125 ? _Queue16_UInt8_20_io_deq_bits : _T_5124 ? _Queue16_UInt8_19_io_deq_bits : _T_5123 ? _Queue16_UInt8_18_io_deq_bits : _T_5122 ? _Queue16_UInt8_17_io_deq_bits : _T_5121 ? _Queue16_UInt8_16_io_deq_bits : _T_5120 ? _Queue16_UInt8_15_io_deq_bits : _T_5119 ? _Queue16_UInt8_14_io_deq_bits : _T_5118 ? _Queue16_UInt8_13_io_deq_bits : _T_5117 ? _Queue16_UInt8_12_io_deq_bits : _T_5116 ? _Queue16_UInt8_11_io_deq_bits : _T_5115 ? _Queue16_UInt8_10_io_deq_bits : _T_5114 ? _Queue16_UInt8_9_io_deq_bits : _T_5113 ? _Queue16_UInt8_8_io_deq_bits : _T_5112 ? _Queue16_UInt8_7_io_deq_bits : _T_5111 ? _Queue16_UInt8_6_io_deq_bits : _T_5110 ? _Queue16_UInt8_5_io_deq_bits : _T_5109 ? _Queue16_UInt8_4_io_deq_bits : _T_5108 ? _Queue16_UInt8_3_io_deq_bits : _T_5107 ? _Queue16_UInt8_2_io_deq_bits : _T_5106 ? _Queue16_UInt8_1_io_deq_bits : _T_5105 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_valid : _T_5135 ? _Queue16_UInt8_30_io_deq_valid : _T_5134 ? _Queue16_UInt8_29_io_deq_valid : _T_5133 ? _Queue16_UInt8_28_io_deq_valid : _T_5132 ? _Queue16_UInt8_27_io_deq_valid : _T_5131 ? _Queue16_UInt8_26_io_deq_valid : _T_5130 ? _Queue16_UInt8_25_io_deq_valid : _T_5129 ? _Queue16_UInt8_24_io_deq_valid : _T_5128 ? _Queue16_UInt8_23_io_deq_valid : _T_5127 ? _Queue16_UInt8_22_io_deq_valid : _T_5126 ? _Queue16_UInt8_21_io_deq_valid : _T_5125 ? _Queue16_UInt8_20_io_deq_valid : _T_5124 ? _Queue16_UInt8_19_io_deq_valid : _T_5123 ? _Queue16_UInt8_18_io_deq_valid : _T_5122 ? _Queue16_UInt8_17_io_deq_valid : _T_5121 ? _Queue16_UInt8_16_io_deq_valid : _T_5120 ? _Queue16_UInt8_15_io_deq_valid : _T_5119 ? _Queue16_UInt8_14_io_deq_valid : _T_5118 ? _Queue16_UInt8_13_io_deq_valid : _T_5117 ? _Queue16_UInt8_12_io_deq_valid : _T_5116 ? _Queue16_UInt8_11_io_deq_valid : _T_5115 ? _Queue16_UInt8_10_io_deq_valid : _T_5114 ? _Queue16_UInt8_9_io_deq_valid : _T_5113 ? _Queue16_UInt8_8_io_deq_valid : _T_5112 ? _Queue16_UInt8_7_io_deq_valid : _T_5111 ? _Queue16_UInt8_6_io_deq_valid : _T_5110 ? _Queue16_UInt8_5_io_deq_valid : _T_5109 ? _Queue16_UInt8_4_io_deq_valid : _T_5108 ? _Queue16_UInt8_3_io_deq_valid : _T_5107 ? _Queue16_UInt8_2_io_deq_valid : _T_5106 ? _Queue16_UInt8_1_io_deq_valid : _T_5105 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_115 = _remapindex_T_25 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_25 = _GEN_115[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5137 = remapindex_25 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5138 = remapindex_25 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5139 = remapindex_25 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5140 = remapindex_25 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5141 = remapindex_25 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5142 = remapindex_25 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5143 = remapindex_25 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5144 = remapindex_25 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5145 = remapindex_25 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5146 = remapindex_25 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5147 = remapindex_25 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5148 = remapindex_25 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5149 = remapindex_25 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5150 = remapindex_25 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5151 = remapindex_25 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5152 = remapindex_25 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5153 = remapindex_25 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5154 = remapindex_25 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5155 = remapindex_25 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5156 = remapindex_25 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5157 = remapindex_25 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5158 = remapindex_25 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5159 = remapindex_25 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5160 = remapindex_25 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5161 = remapindex_25 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5162 = remapindex_25 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5163 = remapindex_25 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5164 = remapindex_25 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5165 = remapindex_25 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5166 = remapindex_25 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5167 = remapindex_25 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5168 = remapindex_25 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_bits : _T_5167 ? _Queue16_UInt8_30_io_deq_bits : _T_5166 ? _Queue16_UInt8_29_io_deq_bits : _T_5165 ? _Queue16_UInt8_28_io_deq_bits : _T_5164 ? _Queue16_UInt8_27_io_deq_bits : _T_5163 ? _Queue16_UInt8_26_io_deq_bits : _T_5162 ? _Queue16_UInt8_25_io_deq_bits : _T_5161 ? _Queue16_UInt8_24_io_deq_bits : _T_5160 ? _Queue16_UInt8_23_io_deq_bits : _T_5159 ? _Queue16_UInt8_22_io_deq_bits : _T_5158 ? _Queue16_UInt8_21_io_deq_bits : _T_5157 ? _Queue16_UInt8_20_io_deq_bits : _T_5156 ? _Queue16_UInt8_19_io_deq_bits : _T_5155 ? _Queue16_UInt8_18_io_deq_bits : _T_5154 ? _Queue16_UInt8_17_io_deq_bits : _T_5153 ? _Queue16_UInt8_16_io_deq_bits : _T_5152 ? _Queue16_UInt8_15_io_deq_bits : _T_5151 ? _Queue16_UInt8_14_io_deq_bits : _T_5150 ? _Queue16_UInt8_13_io_deq_bits : _T_5149 ? _Queue16_UInt8_12_io_deq_bits : _T_5148 ? _Queue16_UInt8_11_io_deq_bits : _T_5147 ? _Queue16_UInt8_10_io_deq_bits : _T_5146 ? _Queue16_UInt8_9_io_deq_bits : _T_5145 ? _Queue16_UInt8_8_io_deq_bits : _T_5144 ? _Queue16_UInt8_7_io_deq_bits : _T_5143 ? _Queue16_UInt8_6_io_deq_bits : _T_5142 ? _Queue16_UInt8_5_io_deq_bits : _T_5141 ? _Queue16_UInt8_4_io_deq_bits : _T_5140 ? _Queue16_UInt8_3_io_deq_bits : _T_5139 ? _Queue16_UInt8_2_io_deq_bits : _T_5138 ? _Queue16_UInt8_1_io_deq_bits : _T_5137 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_valid : _T_5167 ? _Queue16_UInt8_30_io_deq_valid : _T_5166 ? _Queue16_UInt8_29_io_deq_valid : _T_5165 ? _Queue16_UInt8_28_io_deq_valid : _T_5164 ? _Queue16_UInt8_27_io_deq_valid : _T_5163 ? _Queue16_UInt8_26_io_deq_valid : _T_5162 ? _Queue16_UInt8_25_io_deq_valid : _T_5161 ? _Queue16_UInt8_24_io_deq_valid : _T_5160 ? _Queue16_UInt8_23_io_deq_valid : _T_5159 ? _Queue16_UInt8_22_io_deq_valid : _T_5158 ? _Queue16_UInt8_21_io_deq_valid : _T_5157 ? _Queue16_UInt8_20_io_deq_valid : _T_5156 ? _Queue16_UInt8_19_io_deq_valid : _T_5155 ? _Queue16_UInt8_18_io_deq_valid : _T_5154 ? _Queue16_UInt8_17_io_deq_valid : _T_5153 ? _Queue16_UInt8_16_io_deq_valid : _T_5152 ? _Queue16_UInt8_15_io_deq_valid : _T_5151 ? _Queue16_UInt8_14_io_deq_valid : _T_5150 ? _Queue16_UInt8_13_io_deq_valid : _T_5149 ? _Queue16_UInt8_12_io_deq_valid : _T_5148 ? _Queue16_UInt8_11_io_deq_valid : _T_5147 ? _Queue16_UInt8_10_io_deq_valid : _T_5146 ? _Queue16_UInt8_9_io_deq_valid : _T_5145 ? _Queue16_UInt8_8_io_deq_valid : _T_5144 ? _Queue16_UInt8_7_io_deq_valid : _T_5143 ? _Queue16_UInt8_6_io_deq_valid : _T_5142 ? _Queue16_UInt8_5_io_deq_valid : _T_5141 ? _Queue16_UInt8_4_io_deq_valid : _T_5140 ? _Queue16_UInt8_3_io_deq_valid : _T_5139 ? _Queue16_UInt8_2_io_deq_valid : _T_5138 ? _Queue16_UInt8_1_io_deq_valid : _T_5137 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_116 = _remapindex_T_26 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_26 = _GEN_116[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5169 = remapindex_26 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5170 = remapindex_26 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5171 = remapindex_26 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5172 = remapindex_26 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5173 = remapindex_26 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5174 = remapindex_26 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5175 = remapindex_26 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5176 = remapindex_26 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5177 = remapindex_26 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5178 = remapindex_26 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5179 = remapindex_26 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5180 = remapindex_26 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5181 = remapindex_26 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5182 = remapindex_26 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5183 = remapindex_26 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5184 = remapindex_26 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5185 = remapindex_26 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5186 = remapindex_26 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5187 = remapindex_26 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5188 = remapindex_26 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5189 = remapindex_26 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5190 = remapindex_26 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5191 = remapindex_26 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5192 = remapindex_26 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5193 = remapindex_26 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5194 = remapindex_26 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5195 = remapindex_26 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5196 = remapindex_26 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5197 = remapindex_26 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5198 = remapindex_26 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5199 = remapindex_26 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5200 = remapindex_26 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_bits : _T_5199 ? _Queue16_UInt8_30_io_deq_bits : _T_5198 ? _Queue16_UInt8_29_io_deq_bits : _T_5197 ? _Queue16_UInt8_28_io_deq_bits : _T_5196 ? _Queue16_UInt8_27_io_deq_bits : _T_5195 ? _Queue16_UInt8_26_io_deq_bits : _T_5194 ? _Queue16_UInt8_25_io_deq_bits : _T_5193 ? _Queue16_UInt8_24_io_deq_bits : _T_5192 ? _Queue16_UInt8_23_io_deq_bits : _T_5191 ? _Queue16_UInt8_22_io_deq_bits : _T_5190 ? _Queue16_UInt8_21_io_deq_bits : _T_5189 ? _Queue16_UInt8_20_io_deq_bits : _T_5188 ? _Queue16_UInt8_19_io_deq_bits : _T_5187 ? _Queue16_UInt8_18_io_deq_bits : _T_5186 ? _Queue16_UInt8_17_io_deq_bits : _T_5185 ? _Queue16_UInt8_16_io_deq_bits : _T_5184 ? _Queue16_UInt8_15_io_deq_bits : _T_5183 ? _Queue16_UInt8_14_io_deq_bits : _T_5182 ? _Queue16_UInt8_13_io_deq_bits : _T_5181 ? _Queue16_UInt8_12_io_deq_bits : _T_5180 ? _Queue16_UInt8_11_io_deq_bits : _T_5179 ? _Queue16_UInt8_10_io_deq_bits : _T_5178 ? _Queue16_UInt8_9_io_deq_bits : _T_5177 ? _Queue16_UInt8_8_io_deq_bits : _T_5176 ? _Queue16_UInt8_7_io_deq_bits : _T_5175 ? _Queue16_UInt8_6_io_deq_bits : _T_5174 ? _Queue16_UInt8_5_io_deq_bits : _T_5173 ? _Queue16_UInt8_4_io_deq_bits : _T_5172 ? _Queue16_UInt8_3_io_deq_bits : _T_5171 ? _Queue16_UInt8_2_io_deq_bits : _T_5170 ? _Queue16_UInt8_1_io_deq_bits : _T_5169 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_valid : _T_5199 ? _Queue16_UInt8_30_io_deq_valid : _T_5198 ? _Queue16_UInt8_29_io_deq_valid : _T_5197 ? _Queue16_UInt8_28_io_deq_valid : _T_5196 ? _Queue16_UInt8_27_io_deq_valid : _T_5195 ? _Queue16_UInt8_26_io_deq_valid : _T_5194 ? _Queue16_UInt8_25_io_deq_valid : _T_5193 ? _Queue16_UInt8_24_io_deq_valid : _T_5192 ? _Queue16_UInt8_23_io_deq_valid : _T_5191 ? _Queue16_UInt8_22_io_deq_valid : _T_5190 ? _Queue16_UInt8_21_io_deq_valid : _T_5189 ? _Queue16_UInt8_20_io_deq_valid : _T_5188 ? _Queue16_UInt8_19_io_deq_valid : _T_5187 ? _Queue16_UInt8_18_io_deq_valid : _T_5186 ? _Queue16_UInt8_17_io_deq_valid : _T_5185 ? _Queue16_UInt8_16_io_deq_valid : _T_5184 ? _Queue16_UInt8_15_io_deq_valid : _T_5183 ? _Queue16_UInt8_14_io_deq_valid : _T_5182 ? _Queue16_UInt8_13_io_deq_valid : _T_5181 ? _Queue16_UInt8_12_io_deq_valid : _T_5180 ? _Queue16_UInt8_11_io_deq_valid : _T_5179 ? _Queue16_UInt8_10_io_deq_valid : _T_5178 ? _Queue16_UInt8_9_io_deq_valid : _T_5177 ? _Queue16_UInt8_8_io_deq_valid : _T_5176 ? _Queue16_UInt8_7_io_deq_valid : _T_5175 ? _Queue16_UInt8_6_io_deq_valid : _T_5174 ? _Queue16_UInt8_5_io_deq_valid : _T_5173 ? _Queue16_UInt8_4_io_deq_valid : _T_5172 ? _Queue16_UInt8_3_io_deq_valid : _T_5171 ? _Queue16_UInt8_2_io_deq_valid : _T_5170 ? _Queue16_UInt8_1_io_deq_valid : _T_5169 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_117 = _remapindex_T_27 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_27 = _GEN_117[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5201 = remapindex_27 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5202 = remapindex_27 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5203 = remapindex_27 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5204 = remapindex_27 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5205 = remapindex_27 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5206 = remapindex_27 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5207 = remapindex_27 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5208 = remapindex_27 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5209 = remapindex_27 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5210 = remapindex_27 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5211 = remapindex_27 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5212 = remapindex_27 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5213 = remapindex_27 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5214 = remapindex_27 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5215 = remapindex_27 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5216 = remapindex_27 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5217 = remapindex_27 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5218 = remapindex_27 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5219 = remapindex_27 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5220 = remapindex_27 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5221 = remapindex_27 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5222 = remapindex_27 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5223 = remapindex_27 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5224 = remapindex_27 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5225 = remapindex_27 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5226 = remapindex_27 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5227 = remapindex_27 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5228 = remapindex_27 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5229 = remapindex_27 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5230 = remapindex_27 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5231 = remapindex_27 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5232 = remapindex_27 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_bits : _T_5231 ? _Queue16_UInt8_30_io_deq_bits : _T_5230 ? _Queue16_UInt8_29_io_deq_bits : _T_5229 ? _Queue16_UInt8_28_io_deq_bits : _T_5228 ? _Queue16_UInt8_27_io_deq_bits : _T_5227 ? _Queue16_UInt8_26_io_deq_bits : _T_5226 ? _Queue16_UInt8_25_io_deq_bits : _T_5225 ? _Queue16_UInt8_24_io_deq_bits : _T_5224 ? _Queue16_UInt8_23_io_deq_bits : _T_5223 ? _Queue16_UInt8_22_io_deq_bits : _T_5222 ? _Queue16_UInt8_21_io_deq_bits : _T_5221 ? _Queue16_UInt8_20_io_deq_bits : _T_5220 ? _Queue16_UInt8_19_io_deq_bits : _T_5219 ? _Queue16_UInt8_18_io_deq_bits : _T_5218 ? _Queue16_UInt8_17_io_deq_bits : _T_5217 ? _Queue16_UInt8_16_io_deq_bits : _T_5216 ? _Queue16_UInt8_15_io_deq_bits : _T_5215 ? _Queue16_UInt8_14_io_deq_bits : _T_5214 ? _Queue16_UInt8_13_io_deq_bits : _T_5213 ? _Queue16_UInt8_12_io_deq_bits : _T_5212 ? _Queue16_UInt8_11_io_deq_bits : _T_5211 ? _Queue16_UInt8_10_io_deq_bits : _T_5210 ? _Queue16_UInt8_9_io_deq_bits : _T_5209 ? _Queue16_UInt8_8_io_deq_bits : _T_5208 ? _Queue16_UInt8_7_io_deq_bits : _T_5207 ? _Queue16_UInt8_6_io_deq_bits : _T_5206 ? _Queue16_UInt8_5_io_deq_bits : _T_5205 ? _Queue16_UInt8_4_io_deq_bits : _T_5204 ? _Queue16_UInt8_3_io_deq_bits : _T_5203 ? _Queue16_UInt8_2_io_deq_bits : _T_5202 ? _Queue16_UInt8_1_io_deq_bits : _T_5201 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_valid : _T_5231 ? _Queue16_UInt8_30_io_deq_valid : _T_5230 ? _Queue16_UInt8_29_io_deq_valid : _T_5229 ? _Queue16_UInt8_28_io_deq_valid : _T_5228 ? _Queue16_UInt8_27_io_deq_valid : _T_5227 ? _Queue16_UInt8_26_io_deq_valid : _T_5226 ? _Queue16_UInt8_25_io_deq_valid : _T_5225 ? _Queue16_UInt8_24_io_deq_valid : _T_5224 ? _Queue16_UInt8_23_io_deq_valid : _T_5223 ? _Queue16_UInt8_22_io_deq_valid : _T_5222 ? _Queue16_UInt8_21_io_deq_valid : _T_5221 ? _Queue16_UInt8_20_io_deq_valid : _T_5220 ? _Queue16_UInt8_19_io_deq_valid : _T_5219 ? _Queue16_UInt8_18_io_deq_valid : _T_5218 ? _Queue16_UInt8_17_io_deq_valid : _T_5217 ? _Queue16_UInt8_16_io_deq_valid : _T_5216 ? _Queue16_UInt8_15_io_deq_valid : _T_5215 ? _Queue16_UInt8_14_io_deq_valid : _T_5214 ? _Queue16_UInt8_13_io_deq_valid : _T_5213 ? _Queue16_UInt8_12_io_deq_valid : _T_5212 ? _Queue16_UInt8_11_io_deq_valid : _T_5211 ? _Queue16_UInt8_10_io_deq_valid : _T_5210 ? _Queue16_UInt8_9_io_deq_valid : _T_5209 ? _Queue16_UInt8_8_io_deq_valid : _T_5208 ? _Queue16_UInt8_7_io_deq_valid : _T_5207 ? _Queue16_UInt8_6_io_deq_valid : _T_5206 ? _Queue16_UInt8_5_io_deq_valid : _T_5205 ? _Queue16_UInt8_4_io_deq_valid : _T_5204 ? _Queue16_UInt8_3_io_deq_valid : _T_5203 ? _Queue16_UInt8_2_io_deq_valid : _T_5202 ? _Queue16_UInt8_1_io_deq_valid : _T_5201 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_118 = _remapindex_T_28 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_28 = _GEN_118[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5233 = remapindex_28 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5234 = remapindex_28 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5235 = remapindex_28 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5236 = remapindex_28 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5237 = remapindex_28 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5238 = remapindex_28 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5239 = remapindex_28 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5240 = remapindex_28 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5241 = remapindex_28 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5242 = remapindex_28 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5243 = remapindex_28 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5244 = remapindex_28 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5245 = remapindex_28 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5246 = remapindex_28 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5247 = remapindex_28 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5248 = remapindex_28 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5249 = remapindex_28 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5250 = remapindex_28 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5251 = remapindex_28 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5252 = remapindex_28 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5253 = remapindex_28 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5254 = remapindex_28 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5255 = remapindex_28 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5256 = remapindex_28 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5257 = remapindex_28 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5258 = remapindex_28 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5259 = remapindex_28 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5260 = remapindex_28 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5261 = remapindex_28 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5262 = remapindex_28 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5263 = remapindex_28 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5264 = remapindex_28 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_bits : _T_5263 ? _Queue16_UInt8_30_io_deq_bits : _T_5262 ? _Queue16_UInt8_29_io_deq_bits : _T_5261 ? _Queue16_UInt8_28_io_deq_bits : _T_5260 ? _Queue16_UInt8_27_io_deq_bits : _T_5259 ? _Queue16_UInt8_26_io_deq_bits : _T_5258 ? _Queue16_UInt8_25_io_deq_bits : _T_5257 ? _Queue16_UInt8_24_io_deq_bits : _T_5256 ? _Queue16_UInt8_23_io_deq_bits : _T_5255 ? _Queue16_UInt8_22_io_deq_bits : _T_5254 ? _Queue16_UInt8_21_io_deq_bits : _T_5253 ? _Queue16_UInt8_20_io_deq_bits : _T_5252 ? _Queue16_UInt8_19_io_deq_bits : _T_5251 ? _Queue16_UInt8_18_io_deq_bits : _T_5250 ? _Queue16_UInt8_17_io_deq_bits : _T_5249 ? _Queue16_UInt8_16_io_deq_bits : _T_5248 ? _Queue16_UInt8_15_io_deq_bits : _T_5247 ? _Queue16_UInt8_14_io_deq_bits : _T_5246 ? _Queue16_UInt8_13_io_deq_bits : _T_5245 ? _Queue16_UInt8_12_io_deq_bits : _T_5244 ? _Queue16_UInt8_11_io_deq_bits : _T_5243 ? _Queue16_UInt8_10_io_deq_bits : _T_5242 ? _Queue16_UInt8_9_io_deq_bits : _T_5241 ? _Queue16_UInt8_8_io_deq_bits : _T_5240 ? _Queue16_UInt8_7_io_deq_bits : _T_5239 ? _Queue16_UInt8_6_io_deq_bits : _T_5238 ? _Queue16_UInt8_5_io_deq_bits : _T_5237 ? _Queue16_UInt8_4_io_deq_bits : _T_5236 ? _Queue16_UInt8_3_io_deq_bits : _T_5235 ? _Queue16_UInt8_2_io_deq_bits : _T_5234 ? _Queue16_UInt8_1_io_deq_bits : _T_5233 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_valid : _T_5263 ? _Queue16_UInt8_30_io_deq_valid : _T_5262 ? _Queue16_UInt8_29_io_deq_valid : _T_5261 ? _Queue16_UInt8_28_io_deq_valid : _T_5260 ? _Queue16_UInt8_27_io_deq_valid : _T_5259 ? _Queue16_UInt8_26_io_deq_valid : _T_5258 ? _Queue16_UInt8_25_io_deq_valid : _T_5257 ? _Queue16_UInt8_24_io_deq_valid : _T_5256 ? _Queue16_UInt8_23_io_deq_valid : _T_5255 ? _Queue16_UInt8_22_io_deq_valid : _T_5254 ? _Queue16_UInt8_21_io_deq_valid : _T_5253 ? _Queue16_UInt8_20_io_deq_valid : _T_5252 ? _Queue16_UInt8_19_io_deq_valid : _T_5251 ? _Queue16_UInt8_18_io_deq_valid : _T_5250 ? _Queue16_UInt8_17_io_deq_valid : _T_5249 ? _Queue16_UInt8_16_io_deq_valid : _T_5248 ? _Queue16_UInt8_15_io_deq_valid : _T_5247 ? _Queue16_UInt8_14_io_deq_valid : _T_5246 ? _Queue16_UInt8_13_io_deq_valid : _T_5245 ? _Queue16_UInt8_12_io_deq_valid : _T_5244 ? _Queue16_UInt8_11_io_deq_valid : _T_5243 ? _Queue16_UInt8_10_io_deq_valid : _T_5242 ? _Queue16_UInt8_9_io_deq_valid : _T_5241 ? _Queue16_UInt8_8_io_deq_valid : _T_5240 ? _Queue16_UInt8_7_io_deq_valid : _T_5239 ? _Queue16_UInt8_6_io_deq_valid : _T_5238 ? _Queue16_UInt8_5_io_deq_valid : _T_5237 ? _Queue16_UInt8_4_io_deq_valid : _T_5236 ? _Queue16_UInt8_3_io_deq_valid : _T_5235 ? _Queue16_UInt8_2_io_deq_valid : _T_5234 ? _Queue16_UInt8_1_io_deq_valid : _T_5233 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_119 = _remapindex_T_29 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_29 = _GEN_119[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5265 = remapindex_29 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5266 = remapindex_29 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5267 = remapindex_29 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5268 = remapindex_29 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5269 = remapindex_29 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5270 = remapindex_29 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5271 = remapindex_29 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5272 = remapindex_29 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5273 = remapindex_29 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5274 = remapindex_29 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5275 = remapindex_29 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5276 = remapindex_29 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5277 = remapindex_29 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5278 = remapindex_29 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5279 = remapindex_29 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5280 = remapindex_29 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5281 = remapindex_29 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5282 = remapindex_29 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5283 = remapindex_29 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5284 = remapindex_29 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5285 = remapindex_29 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5286 = remapindex_29 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5287 = remapindex_29 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5288 = remapindex_29 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5289 = remapindex_29 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5290 = remapindex_29 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5291 = remapindex_29 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5292 = remapindex_29 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5293 = remapindex_29 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5294 = remapindex_29 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5295 = remapindex_29 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5296 = remapindex_29 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_bits : _T_5295 ? _Queue16_UInt8_30_io_deq_bits : _T_5294 ? _Queue16_UInt8_29_io_deq_bits : _T_5293 ? _Queue16_UInt8_28_io_deq_bits : _T_5292 ? _Queue16_UInt8_27_io_deq_bits : _T_5291 ? _Queue16_UInt8_26_io_deq_bits : _T_5290 ? _Queue16_UInt8_25_io_deq_bits : _T_5289 ? _Queue16_UInt8_24_io_deq_bits : _T_5288 ? _Queue16_UInt8_23_io_deq_bits : _T_5287 ? _Queue16_UInt8_22_io_deq_bits : _T_5286 ? _Queue16_UInt8_21_io_deq_bits : _T_5285 ? _Queue16_UInt8_20_io_deq_bits : _T_5284 ? _Queue16_UInt8_19_io_deq_bits : _T_5283 ? _Queue16_UInt8_18_io_deq_bits : _T_5282 ? _Queue16_UInt8_17_io_deq_bits : _T_5281 ? _Queue16_UInt8_16_io_deq_bits : _T_5280 ? _Queue16_UInt8_15_io_deq_bits : _T_5279 ? _Queue16_UInt8_14_io_deq_bits : _T_5278 ? _Queue16_UInt8_13_io_deq_bits : _T_5277 ? _Queue16_UInt8_12_io_deq_bits : _T_5276 ? _Queue16_UInt8_11_io_deq_bits : _T_5275 ? _Queue16_UInt8_10_io_deq_bits : _T_5274 ? _Queue16_UInt8_9_io_deq_bits : _T_5273 ? _Queue16_UInt8_8_io_deq_bits : _T_5272 ? _Queue16_UInt8_7_io_deq_bits : _T_5271 ? _Queue16_UInt8_6_io_deq_bits : _T_5270 ? _Queue16_UInt8_5_io_deq_bits : _T_5269 ? _Queue16_UInt8_4_io_deq_bits : _T_5268 ? _Queue16_UInt8_3_io_deq_bits : _T_5267 ? _Queue16_UInt8_2_io_deq_bits : _T_5266 ? _Queue16_UInt8_1_io_deq_bits : _T_5265 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_valid : _T_5295 ? _Queue16_UInt8_30_io_deq_valid : _T_5294 ? _Queue16_UInt8_29_io_deq_valid : _T_5293 ? _Queue16_UInt8_28_io_deq_valid : _T_5292 ? _Queue16_UInt8_27_io_deq_valid : _T_5291 ? _Queue16_UInt8_26_io_deq_valid : _T_5290 ? _Queue16_UInt8_25_io_deq_valid : _T_5289 ? _Queue16_UInt8_24_io_deq_valid : _T_5288 ? _Queue16_UInt8_23_io_deq_valid : _T_5287 ? _Queue16_UInt8_22_io_deq_valid : _T_5286 ? _Queue16_UInt8_21_io_deq_valid : _T_5285 ? _Queue16_UInt8_20_io_deq_valid : _T_5284 ? _Queue16_UInt8_19_io_deq_valid : _T_5283 ? _Queue16_UInt8_18_io_deq_valid : _T_5282 ? _Queue16_UInt8_17_io_deq_valid : _T_5281 ? _Queue16_UInt8_16_io_deq_valid : _T_5280 ? _Queue16_UInt8_15_io_deq_valid : _T_5279 ? _Queue16_UInt8_14_io_deq_valid : _T_5278 ? _Queue16_UInt8_13_io_deq_valid : _T_5277 ? _Queue16_UInt8_12_io_deq_valid : _T_5276 ? _Queue16_UInt8_11_io_deq_valid : _T_5275 ? _Queue16_UInt8_10_io_deq_valid : _T_5274 ? _Queue16_UInt8_9_io_deq_valid : _T_5273 ? _Queue16_UInt8_8_io_deq_valid : _T_5272 ? _Queue16_UInt8_7_io_deq_valid : _T_5271 ? _Queue16_UInt8_6_io_deq_valid : _T_5270 ? _Queue16_UInt8_5_io_deq_valid : _T_5269 ? _Queue16_UInt8_4_io_deq_valid : _T_5268 ? _Queue16_UInt8_3_io_deq_valid : _T_5267 ? _Queue16_UInt8_2_io_deq_valid : _T_5266 ? _Queue16_UInt8_1_io_deq_valid : _T_5265 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_120 = _remapindex_T_30 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_30 = _GEN_120[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5297 = remapindex_30 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5298 = remapindex_30 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5299 = remapindex_30 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5300 = remapindex_30 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5301 = remapindex_30 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5302 = remapindex_30 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5303 = remapindex_30 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5304 = remapindex_30 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5305 = remapindex_30 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5306 = remapindex_30 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5307 = remapindex_30 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5308 = remapindex_30 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5309 = remapindex_30 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5310 = remapindex_30 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5311 = remapindex_30 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5312 = remapindex_30 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5313 = remapindex_30 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5314 = remapindex_30 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5315 = remapindex_30 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5316 = remapindex_30 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5317 = remapindex_30 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5318 = remapindex_30 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5319 = remapindex_30 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5320 = remapindex_30 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5321 = remapindex_30 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5322 = remapindex_30 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5323 = remapindex_30 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5324 = remapindex_30 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5325 = remapindex_30 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5326 = remapindex_30 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5327 = remapindex_30 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5328 = remapindex_30 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_bits : _T_5327 ? _Queue16_UInt8_30_io_deq_bits : _T_5326 ? _Queue16_UInt8_29_io_deq_bits : _T_5325 ? _Queue16_UInt8_28_io_deq_bits : _T_5324 ? _Queue16_UInt8_27_io_deq_bits : _T_5323 ? _Queue16_UInt8_26_io_deq_bits : _T_5322 ? _Queue16_UInt8_25_io_deq_bits : _T_5321 ? _Queue16_UInt8_24_io_deq_bits : _T_5320 ? _Queue16_UInt8_23_io_deq_bits : _T_5319 ? _Queue16_UInt8_22_io_deq_bits : _T_5318 ? _Queue16_UInt8_21_io_deq_bits : _T_5317 ? _Queue16_UInt8_20_io_deq_bits : _T_5316 ? _Queue16_UInt8_19_io_deq_bits : _T_5315 ? _Queue16_UInt8_18_io_deq_bits : _T_5314 ? _Queue16_UInt8_17_io_deq_bits : _T_5313 ? _Queue16_UInt8_16_io_deq_bits : _T_5312 ? _Queue16_UInt8_15_io_deq_bits : _T_5311 ? _Queue16_UInt8_14_io_deq_bits : _T_5310 ? _Queue16_UInt8_13_io_deq_bits : _T_5309 ? _Queue16_UInt8_12_io_deq_bits : _T_5308 ? _Queue16_UInt8_11_io_deq_bits : _T_5307 ? _Queue16_UInt8_10_io_deq_bits : _T_5306 ? _Queue16_UInt8_9_io_deq_bits : _T_5305 ? _Queue16_UInt8_8_io_deq_bits : _T_5304 ? _Queue16_UInt8_7_io_deq_bits : _T_5303 ? _Queue16_UInt8_6_io_deq_bits : _T_5302 ? _Queue16_UInt8_5_io_deq_bits : _T_5301 ? _Queue16_UInt8_4_io_deq_bits : _T_5300 ? _Queue16_UInt8_3_io_deq_bits : _T_5299 ? _Queue16_UInt8_2_io_deq_bits : _T_5298 ? _Queue16_UInt8_1_io_deq_bits : _T_5297 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_valid : _T_5327 ? _Queue16_UInt8_30_io_deq_valid : _T_5326 ? _Queue16_UInt8_29_io_deq_valid : _T_5325 ? _Queue16_UInt8_28_io_deq_valid : _T_5324 ? _Queue16_UInt8_27_io_deq_valid : _T_5323 ? _Queue16_UInt8_26_io_deq_valid : _T_5322 ? _Queue16_UInt8_25_io_deq_valid : _T_5321 ? _Queue16_UInt8_24_io_deq_valid : _T_5320 ? _Queue16_UInt8_23_io_deq_valid : _T_5319 ? _Queue16_UInt8_22_io_deq_valid : _T_5318 ? _Queue16_UInt8_21_io_deq_valid : _T_5317 ? _Queue16_UInt8_20_io_deq_valid : _T_5316 ? _Queue16_UInt8_19_io_deq_valid : _T_5315 ? _Queue16_UInt8_18_io_deq_valid : _T_5314 ? _Queue16_UInt8_17_io_deq_valid : _T_5313 ? _Queue16_UInt8_16_io_deq_valid : _T_5312 ? _Queue16_UInt8_15_io_deq_valid : _T_5311 ? _Queue16_UInt8_14_io_deq_valid : _T_5310 ? _Queue16_UInt8_13_io_deq_valid : _T_5309 ? _Queue16_UInt8_12_io_deq_valid : _T_5308 ? _Queue16_UInt8_11_io_deq_valid : _T_5307 ? _Queue16_UInt8_10_io_deq_valid : _T_5306 ? _Queue16_UInt8_9_io_deq_valid : _T_5305 ? _Queue16_UInt8_8_io_deq_valid : _T_5304 ? _Queue16_UInt8_7_io_deq_valid : _T_5303 ? _Queue16_UInt8_6_io_deq_valid : _T_5302 ? _Queue16_UInt8_5_io_deq_valid : _T_5301 ? _Queue16_UInt8_4_io_deq_valid : _T_5300 ? _Queue16_UInt8_3_io_deq_valid : _T_5299 ? _Queue16_UInt8_2_io_deq_valid : _T_5298 ? _Queue16_UInt8_1_io_deq_valid : _T_5297 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[EntropyCompressorMemWriter.scala:148:33] wire [6:0] _GEN_121 = _remapindex_T_31 % 7'h20; // @[EntropyCompressorMemWriter.scala:148:{33,54}] wire [5:0] remapindex_31 = _GEN_121[5:0]; // @[EntropyCompressorMemWriter.scala:148:54] wire _T_5329 = remapindex_31 == 6'h0; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5330 = remapindex_31 == 6'h1; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5331 = remapindex_31 == 6'h2; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5332 = remapindex_31 == 6'h3; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5333 = remapindex_31 == 6'h4; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5334 = remapindex_31 == 6'h5; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5335 = remapindex_31 == 6'h6; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5336 = remapindex_31 == 6'h7; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5337 = remapindex_31 == 6'h8; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5338 = remapindex_31 == 6'h9; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5339 = remapindex_31 == 6'hA; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5340 = remapindex_31 == 6'hB; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5341 = remapindex_31 == 6'hC; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5342 = remapindex_31 == 6'hD; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5343 = remapindex_31 == 6'hE; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5344 = remapindex_31 == 6'hF; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5345 = remapindex_31 == 6'h10; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5346 = remapindex_31 == 6'h11; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5347 = remapindex_31 == 6'h12; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5348 = remapindex_31 == 6'h13; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5349 = remapindex_31 == 6'h14; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5350 = remapindex_31 == 6'h15; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5351 = remapindex_31 == 6'h16; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5352 = remapindex_31 == 6'h17; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5353 = remapindex_31 == 6'h18; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5354 = remapindex_31 == 6'h19; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5355 = remapindex_31 == 6'h1A; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5356 = remapindex_31 == 6'h1B; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5357 = remapindex_31 == 6'h1C; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5358 = remapindex_31 == 6'h1D; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5359 = remapindex_31 == 6'h1E; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] wire _T_5360 = remapindex_31 == 6'h1F; // @[EntropyCompressorMemWriter.scala:148:54, :150:17] assign remapVecData_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_bits : _T_5359 ? _Queue16_UInt8_30_io_deq_bits : _T_5358 ? _Queue16_UInt8_29_io_deq_bits : _T_5357 ? _Queue16_UInt8_28_io_deq_bits : _T_5356 ? _Queue16_UInt8_27_io_deq_bits : _T_5355 ? _Queue16_UInt8_26_io_deq_bits : _T_5354 ? _Queue16_UInt8_25_io_deq_bits : _T_5353 ? _Queue16_UInt8_24_io_deq_bits : _T_5352 ? _Queue16_UInt8_23_io_deq_bits : _T_5351 ? _Queue16_UInt8_22_io_deq_bits : _T_5350 ? _Queue16_UInt8_21_io_deq_bits : _T_5349 ? _Queue16_UInt8_20_io_deq_bits : _T_5348 ? _Queue16_UInt8_19_io_deq_bits : _T_5347 ? _Queue16_UInt8_18_io_deq_bits : _T_5346 ? _Queue16_UInt8_17_io_deq_bits : _T_5345 ? _Queue16_UInt8_16_io_deq_bits : _T_5344 ? _Queue16_UInt8_15_io_deq_bits : _T_5343 ? _Queue16_UInt8_14_io_deq_bits : _T_5342 ? _Queue16_UInt8_13_io_deq_bits : _T_5341 ? _Queue16_UInt8_12_io_deq_bits : _T_5340 ? _Queue16_UInt8_11_io_deq_bits : _T_5339 ? _Queue16_UInt8_10_io_deq_bits : _T_5338 ? _Queue16_UInt8_9_io_deq_bits : _T_5337 ? _Queue16_UInt8_8_io_deq_bits : _T_5336 ? _Queue16_UInt8_7_io_deq_bits : _T_5335 ? _Queue16_UInt8_6_io_deq_bits : _T_5334 ? _Queue16_UInt8_5_io_deq_bits : _T_5333 ? _Queue16_UInt8_4_io_deq_bits : _T_5332 ? _Queue16_UInt8_3_io_deq_bits : _T_5331 ? _Queue16_UInt8_2_io_deq_bits : _T_5330 ? _Queue16_UInt8_1_io_deq_bits : _T_5329 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[EntropyCompressorMemWriter.scala:75:52, :136:26, :142:27, :150:{17,33}, :151:31] assign remapVecValids_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_valid : _T_5359 ? _Queue16_UInt8_30_io_deq_valid : _T_5358 ? _Queue16_UInt8_29_io_deq_valid : _T_5357 ? _Queue16_UInt8_28_io_deq_valid : _T_5356 ? _Queue16_UInt8_27_io_deq_valid : _T_5355 ? _Queue16_UInt8_26_io_deq_valid : _T_5354 ? _Queue16_UInt8_25_io_deq_valid : _T_5353 ? _Queue16_UInt8_24_io_deq_valid : _T_5352 ? _Queue16_UInt8_23_io_deq_valid : _T_5351 ? _Queue16_UInt8_22_io_deq_valid : _T_5350 ? _Queue16_UInt8_21_io_deq_valid : _T_5349 ? _Queue16_UInt8_20_io_deq_valid : _T_5348 ? _Queue16_UInt8_19_io_deq_valid : _T_5347 ? _Queue16_UInt8_18_io_deq_valid : _T_5346 ? _Queue16_UInt8_17_io_deq_valid : _T_5345 ? _Queue16_UInt8_16_io_deq_valid : _T_5344 ? _Queue16_UInt8_15_io_deq_valid : _T_5343 ? _Queue16_UInt8_14_io_deq_valid : _T_5342 ? _Queue16_UInt8_13_io_deq_valid : _T_5341 ? _Queue16_UInt8_12_io_deq_valid : _T_5340 ? _Queue16_UInt8_11_io_deq_valid : _T_5339 ? _Queue16_UInt8_10_io_deq_valid : _T_5338 ? _Queue16_UInt8_9_io_deq_valid : _T_5337 ? _Queue16_UInt8_8_io_deq_valid : _T_5336 ? _Queue16_UInt8_7_io_deq_valid : _T_5335 ? _Queue16_UInt8_6_io_deq_valid : _T_5334 ? _Queue16_UInt8_5_io_deq_valid : _T_5333 ? _Queue16_UInt8_4_io_deq_valid : _T_5332 ? _Queue16_UInt8_3_io_deq_valid : _T_5331 ? _Queue16_UInt8_2_io_deq_valid : _T_5330 ? _Queue16_UInt8_1_io_deq_valid : _T_5329 & _Queue16_UInt8_io_deq_valid; // @[EntropyCompressorMemWriter.scala:75:52, :137:28, :143:29, :150:{17,33}, :152:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[EntropyCompressorMemWriter.scala:87:{76,90}, :137:28, :158:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[EntropyCompressorMemWriter.scala:87:{76,90}, :137:28, :158:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[EntropyCompressorMemWriter.scala:137:28, :158:60] reg [63:0] backend_bytes_written; // @[EntropyCompressorMemWriter.scala:162:38] wire [64:0] _GEN_122 = {1'h0, backend_bytes_written}; // @[EntropyCompressorMemWriter.scala:162:38, :163:71] wire [64:0] _backend_next_write_addr_T = {1'h0, _decompress_dest_info_Q_io_deq_bits_op} + _GEN_122; // @[EntropyCompressorMemWriter.scala:37:38, :163:71] wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[EntropyCompressorMemWriter.scala:163:71] wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_122; // @[EntropyCompressorMemWriter.scala:50:26, :163:71, :166:28] wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[EntropyCompressorMemWriter.scala:166:28] wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[EntropyCompressorMemWriter.scala:50:26, :165:25, :166:28] wire _throttle_end_writeable_T = |(throttle_end[63:5]); // @[EntropyCompressorMemWriter.scala:165:25, :169:49] wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[EntropyCompressorMemWriter.scala:165:25, :170:53] wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[EntropyCompressorMemWriter.scala:165:25, :170:53, :178:55] wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[EntropyCompressorMemWriter.scala:165:25, :171:55] wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[EntropyCompressorMemWriter.scala:165:25, :171:55, :179:57] wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[EntropyCompressorMemWriter.scala:165:25, :172:57] wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[EntropyCompressorMemWriter.scala:165:25, :172:57, :180:59] wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[EntropyCompressorMemWriter.scala:165:25, :173:59] wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[EntropyCompressorMemWriter.scala:165:25, :173:59, :181:61] wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[EntropyCompressorMemWriter.scala:165:25, :174:61] wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[EntropyCompressorMemWriter.scala:165:25, :174:61, :182:63] wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[EntropyCompressorMemWriter.scala:174:{48,61}] wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[EntropyCompressorMemWriter.scala:173:{46,59}, :174:48] wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[EntropyCompressorMemWriter.scala:172:{44,57}, :173:46] wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[EntropyCompressorMemWriter.scala:171:{42,55}, :172:44] wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[EntropyCompressorMemWriter.scala:170:{40,53}, :171:42] wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[EntropyCompressorMemWriter.scala:169:{35,49}, :170:40] wire _throttle_end_writeable_log2_T = |(throttle_end[63:5]); // @[EntropyCompressorMemWriter.scala:165:25, :169:49, :177:54] wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[EntropyCompressorMemWriter.scala:181:{48,61}] wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[EntropyCompressorMemWriter.scala:180:{46,59}, :181:48] wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[EntropyCompressorMemWriter.scala:179:{44,57}, :180:46] wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[EntropyCompressorMemWriter.scala:178:{42,55}, :179:44] wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[EntropyCompressorMemWriter.scala:177:{40,54}, :178:42] wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[EntropyCompressorMemWriter.scala:163:71, :186:66] wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[EntropyCompressorMemWriter.scala:163:71, :186:66, :193:71] wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[EntropyCompressorMemWriter.scala:163:71, :187:68] wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[EntropyCompressorMemWriter.scala:163:71, :187:68, :194:72] wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[EntropyCompressorMemWriter.scala:163:71, :188:70] wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[EntropyCompressorMemWriter.scala:163:71, :188:70, :195:74] wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[EntropyCompressorMemWriter.scala:163:71, :189:72] wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[EntropyCompressorMemWriter.scala:163:71, :189:72, :196:76] wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[EntropyCompressorMemWriter.scala:163:71, :190:74] wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[EntropyCompressorMemWriter.scala:163:71, :190:74, :197:78] wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[EntropyCompressorMemWriter.scala:190:{50,74}] wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[EntropyCompressorMemWriter.scala:189:{48,72}, :190:50] wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[EntropyCompressorMemWriter.scala:188:{46,70}, :189:48] wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[EntropyCompressorMemWriter.scala:187:{44,68}, :188:46] wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[EntropyCompressorMemWriter.scala:186:{42,66}, :187:44] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[EntropyCompressorMemWriter.scala:197:{54,78}] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[EntropyCompressorMemWriter.scala:196:{52,76}, :197:54] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[EntropyCompressorMemWriter.scala:195:{50,74}, :196:52] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[EntropyCompressorMemWriter.scala:194:{48,72}, :195:50] wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[EntropyCompressorMemWriter.scala:193:{47,71}, :194:48] wire _count_valids_largest_aligned_T = count_valids[5]; // @[EntropyCompressorMemWriter.scala:158:60, :200:54] wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[EntropyCompressorMemWriter.scala:158:60, :200:54, :208:59] wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[EntropyCompressorMemWriter.scala:158:60, :201:55] wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[EntropyCompressorMemWriter.scala:158:60, :201:55, :209:61] wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[EntropyCompressorMemWriter.scala:158:60, :202:57] wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[EntropyCompressorMemWriter.scala:158:60, :202:57, :210:63] wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[EntropyCompressorMemWriter.scala:158:60, :203:59] wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[EntropyCompressorMemWriter.scala:158:60, :203:59, :211:65] wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[EntropyCompressorMemWriter.scala:158:60, :204:61] wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[EntropyCompressorMemWriter.scala:158:60, :204:61, :212:67] wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[EntropyCompressorMemWriter.scala:158:60, :205:63] wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[EntropyCompressorMemWriter.scala:158:60, :205:63, :213:69] wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[EntropyCompressorMemWriter.scala:205:{50,63}] wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[EntropyCompressorMemWriter.scala:204:{48,61}, :205:50] wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[EntropyCompressorMemWriter.scala:203:{46,59}, :204:48] wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[EntropyCompressorMemWriter.scala:202:{44,57}, :203:46] wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[EntropyCompressorMemWriter.scala:201:{42,55}, :202:44] wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[EntropyCompressorMemWriter.scala:200:{41,54}, :201:42] wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[EntropyCompressorMemWriter.scala:212:{54,67}] wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[EntropyCompressorMemWriter.scala:211:{52,65}, :212:54] wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[EntropyCompressorMemWriter.scala:210:{50,63}, :211:52] wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[EntropyCompressorMemWriter.scala:209:{48,61}, :210:50] wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[EntropyCompressorMemWriter.scala:208:{46,59}, :209:48] wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[EntropyCompressorMemWriter.scala:186:42, :200:41, :220:35] wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :186:42, :221:39] wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :186:42, :221:{8,39}] wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :200:41, :224:38] wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[EntropyCompressorMemWriter.scala:169:35, :200:41, :224:{8,38}] wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[EntropyCompressorMemWriter.scala:219:27, :220:35, :221:8, :224:8] wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[EntropyCompressorMemWriter.scala:136:26, :228:32] wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[EntropyCompressorMemWriter.scala:228:32] wire enough_data = |bytes_to_write; // @[EntropyCompressorMemWriter.scala:219:27, :230:36] wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[EntropyCompressorMemWriter.scala:193:47, :208:46, :233:40] wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :193:47, :234:44] wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :193:47, :234:{8,44}] wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :208:46, :237:43] wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[EntropyCompressorMemWriter.scala:177:40, :208:46, :237:{8,43}] wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[EntropyCompressorMemWriter.scala:232:32, :233:40, :234:8, :237:8] wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[EntropyCompressorMemWriter.scala:50:26, :162:38, :242:79] wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[EntropyCompressorMemWriter.scala:50:26, :242:{52,79}] wire _remapVecReadys_0_T = |bytes_to_write; // @[EntropyCompressorMemWriter.scala:219:27, :230:36, :259:43] wire _T_5363 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_1_T = |(bytes_to_write[5:1]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_3_T = |(bytes_to_write[5:2]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_7_T = |(bytes_to_write[5:3]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_15_T = |(bytes_to_write[5:4]); // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _remapVecReadys_31_T = bytes_to_write[5]; // @[EntropyCompressorMemWriter.scala:219:27, :259:43] wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[EntropyCompressorMemWriter.scala:138:28, :259:61] wire _T_5365 = _T_5363 & ~write_ptr_override & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[EntropyCompressorMemWriter.scala:148:33, :219:27, :263:43] wire [6:0] _GEN_123 = _read_start_index_T % 7'h20; // @[EntropyCompressorMemWriter.scala:263:{43,62}] wire [5:0] _read_start_index_T_1 = _GEN_123[5:0]; // @[EntropyCompressorMemWriter.scala:263:62] wire [64:0] _backend_bytes_written_T = _GEN_122 + {59'h0, bytes_to_write}; // @[EntropyCompressorMemWriter.scala:163:71, :219:27, :264:52] wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[EntropyCompressorMemWriter.scala:264:52] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53] assign _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h2 : bytes_to_write_log2; // @[EntropyCompressorMemWriter.scala:232:32, :242:52, :279:31] assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[EntropyCompressorMemWriter.scala:21:7, :279:31] assign _io_l2io_req_bits_addr_T = write_ptr_override ? _decompress_dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[EntropyCompressorMemWriter.scala:37:38, :163:71, :242:52, :280:31] assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[EntropyCompressorMemWriter.scala:21:7, :280:31] assign _io_l2io_req_bits_data_T = write_ptr_override ? {192'h0, _buf_lens_Q_io_deq_bits} : remapped_write_data; // @[EntropyCompressorMemWriter.scala:50:26, :87:{76,90}, :228:32, :242:52, :281:31] assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[EntropyCompressorMemWriter.scala:21:7, :281:31] wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53] wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _decompress_dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53] assign _decompress_dest_info_Q_io_deq_ready_T_1 = _decompress_dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53] reg [63:0] bufs_completed; // @[EntropyCompressorMemWriter.scala:287:31] assign io_bufs_completed = bufs_completed; // @[EntropyCompressorMemWriter.scala:21:7, :287:31] wire _T_5372 = _decompress_dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18] wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[EntropyCompressorMemWriter.scala:287:31, :295:38] wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[EntropyCompressorMemWriter.scala:295:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_58 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_58( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module VectorScalarMultiplier_1 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { in : { bits : UInt<32>}[4], scale : { bits : UInt<32>}, repeats : UInt<16>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}} reg in : { valid : UInt<1>, bits : { in : { bits : UInt<32>}[4], scale : { bits : UInt<32>}, repeats : UInt<16>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, clock wire in_fire : UInt<1> connect in_fire, UInt<1>(0h0) node _io_req_ready_T = eq(in.valid, UInt<1>(0h0)) node _io_req_ready_T_1 = eq(in.bits.repeats, UInt<1>(0h0)) node _io_req_ready_T_2 = and(_io_req_ready_T_1, in_fire) node _io_req_ready_T_3 = or(_io_req_ready_T, _io_req_ready_T_2) connect io.req.ready, _io_req_ready_T_3 node _T = and(io.req.ready, io.req.valid) when _T : connect in.valid, io.req.valid connect in.bits, io.req.bits else : when in_fire : node _T_1 = eq(in.bits.repeats, UInt<1>(0h0)) when _T_1 : connect in.valid, UInt<1>(0h0) node _in_bits_repeats_T = sub(in.bits.repeats, UInt<1>(0h1)) node _in_bits_repeats_T_1 = tail(_in_bits_repeats_T, 1) connect in.bits.repeats, _in_bits_repeats_T_1 node _T_2 = asUInt(reset) when _T_2 : connect in.valid, UInt<1>(0h0) inst pipe of Pipeline_1 connect pipe.clock, clock connect pipe.reset, reset connect io.resp.bits, pipe.io.out.bits connect io.resp.valid, pipe.io.out.valid connect pipe.io.out.ready, io.resp.ready node _in_fire_T = and(pipe.io.in.ready, pipe.io.in.valid) connect in_fire, _in_fire_T connect pipe.io.in.valid, in.valid connect pipe.io.in.bits.tag.cmd_id, in.bits.tag.cmd_id connect pipe.io.in.bits.tag.bytes_read, in.bits.tag.bytes_read connect pipe.io.in.bits.tag.last, in.bits.tag.last connect pipe.io.in.bits.tag.len, in.bits.tag.len connect pipe.io.in.bits.tag.pixel_repeats, in.bits.tag.pixel_repeats connect pipe.io.in.bits.tag.repeats, in.bits.tag.repeats connect pipe.io.in.bits.tag.scale, in.bits.tag.scale connect pipe.io.in.bits.tag.has_acc_bitwidth, in.bits.tag.has_acc_bitwidth connect pipe.io.in.bits.tag.accumulate, in.bits.tag.accumulate connect pipe.io.in.bits.tag.is_acc, in.bits.tag.is_acc connect pipe.io.in.bits.tag.mask[0], in.bits.tag.mask[0] connect pipe.io.in.bits.tag.mask[1], in.bits.tag.mask[1] connect pipe.io.in.bits.tag.mask[2], in.bits.tag.mask[2] connect pipe.io.in.bits.tag.mask[3], in.bits.tag.mask[3] connect pipe.io.in.bits.tag.mask[4], in.bits.tag.mask[4] connect pipe.io.in.bits.tag.mask[5], in.bits.tag.mask[5] connect pipe.io.in.bits.tag.mask[6], in.bits.tag.mask[6] connect pipe.io.in.bits.tag.mask[7], in.bits.tag.mask[7] connect pipe.io.in.bits.tag.mask[8], in.bits.tag.mask[8] connect pipe.io.in.bits.tag.mask[9], in.bits.tag.mask[9] connect pipe.io.in.bits.tag.mask[10], in.bits.tag.mask[10] connect pipe.io.in.bits.tag.mask[11], in.bits.tag.mask[11] connect pipe.io.in.bits.tag.mask[12], in.bits.tag.mask[12] connect pipe.io.in.bits.tag.mask[13], in.bits.tag.mask[13] connect pipe.io.in.bits.tag.mask[14], in.bits.tag.mask[14] connect pipe.io.in.bits.tag.mask[15], in.bits.tag.mask[15] connect pipe.io.in.bits.tag.addr, in.bits.tag.addr connect pipe.io.in.bits.tag.data, in.bits.tag.data node _pipe_io_in_bits_last_T = eq(in.bits.repeats, UInt<1>(0h0)) node _pipe_io_in_bits_last_T_1 = and(_pipe_io_in_bits_last_T, in.bits.last) connect pipe.io.in.bits.last, _pipe_io_in_bits_last_T_1 connect pipe.io.in.bits.row, in.bits.repeats wire _WIRE : { bits : UInt<32>} wire _WIRE_1 : UInt<32> connect _WIRE_1, in.bits.scale.bits node _T_3 = bits(_WIRE_1, 31, 0) connect _WIRE.bits, _T_3 node t_rec_rawIn_sign = bits(_WIRE.bits, 31, 31) node t_rec_rawIn_expIn = bits(_WIRE.bits, 30, 23) node t_rec_rawIn_fractIn = bits(_WIRE.bits, 22, 0) node t_rec_rawIn_isZeroExpIn = eq(t_rec_rawIn_expIn, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn = eq(t_rec_rawIn_fractIn, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T = bits(t_rec_rawIn_fractIn, 0, 0) node _t_rec_rawIn_normDist_T_1 = bits(t_rec_rawIn_fractIn, 1, 1) node _t_rec_rawIn_normDist_T_2 = bits(t_rec_rawIn_fractIn, 2, 2) node _t_rec_rawIn_normDist_T_3 = bits(t_rec_rawIn_fractIn, 3, 3) node _t_rec_rawIn_normDist_T_4 = bits(t_rec_rawIn_fractIn, 4, 4) node _t_rec_rawIn_normDist_T_5 = bits(t_rec_rawIn_fractIn, 5, 5) node _t_rec_rawIn_normDist_T_6 = bits(t_rec_rawIn_fractIn, 6, 6) node _t_rec_rawIn_normDist_T_7 = bits(t_rec_rawIn_fractIn, 7, 7) node _t_rec_rawIn_normDist_T_8 = bits(t_rec_rawIn_fractIn, 8, 8) node _t_rec_rawIn_normDist_T_9 = bits(t_rec_rawIn_fractIn, 9, 9) node _t_rec_rawIn_normDist_T_10 = bits(t_rec_rawIn_fractIn, 10, 10) node _t_rec_rawIn_normDist_T_11 = bits(t_rec_rawIn_fractIn, 11, 11) node _t_rec_rawIn_normDist_T_12 = bits(t_rec_rawIn_fractIn, 12, 12) node _t_rec_rawIn_normDist_T_13 = bits(t_rec_rawIn_fractIn, 13, 13) node _t_rec_rawIn_normDist_T_14 = bits(t_rec_rawIn_fractIn, 14, 14) node _t_rec_rawIn_normDist_T_15 = bits(t_rec_rawIn_fractIn, 15, 15) node _t_rec_rawIn_normDist_T_16 = bits(t_rec_rawIn_fractIn, 16, 16) node _t_rec_rawIn_normDist_T_17 = bits(t_rec_rawIn_fractIn, 17, 17) node _t_rec_rawIn_normDist_T_18 = bits(t_rec_rawIn_fractIn, 18, 18) node _t_rec_rawIn_normDist_T_19 = bits(t_rec_rawIn_fractIn, 19, 19) node _t_rec_rawIn_normDist_T_20 = bits(t_rec_rawIn_fractIn, 20, 20) node _t_rec_rawIn_normDist_T_21 = bits(t_rec_rawIn_fractIn, 21, 21) node _t_rec_rawIn_normDist_T_22 = bits(t_rec_rawIn_fractIn, 22, 22) node _t_rec_rawIn_normDist_T_23 = mux(_t_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_24 = mux(_t_rec_rawIn_normDist_T_2, UInt<5>(0h14), _t_rec_rawIn_normDist_T_23) node _t_rec_rawIn_normDist_T_25 = mux(_t_rec_rawIn_normDist_T_3, UInt<5>(0h13), _t_rec_rawIn_normDist_T_24) node _t_rec_rawIn_normDist_T_26 = mux(_t_rec_rawIn_normDist_T_4, UInt<5>(0h12), _t_rec_rawIn_normDist_T_25) node _t_rec_rawIn_normDist_T_27 = mux(_t_rec_rawIn_normDist_T_5, UInt<5>(0h11), _t_rec_rawIn_normDist_T_26) node _t_rec_rawIn_normDist_T_28 = mux(_t_rec_rawIn_normDist_T_6, UInt<5>(0h10), _t_rec_rawIn_normDist_T_27) node _t_rec_rawIn_normDist_T_29 = mux(_t_rec_rawIn_normDist_T_7, UInt<4>(0hf), _t_rec_rawIn_normDist_T_28) node _t_rec_rawIn_normDist_T_30 = mux(_t_rec_rawIn_normDist_T_8, UInt<4>(0he), _t_rec_rawIn_normDist_T_29) node _t_rec_rawIn_normDist_T_31 = mux(_t_rec_rawIn_normDist_T_9, UInt<4>(0hd), _t_rec_rawIn_normDist_T_30) node _t_rec_rawIn_normDist_T_32 = mux(_t_rec_rawIn_normDist_T_10, UInt<4>(0hc), _t_rec_rawIn_normDist_T_31) node _t_rec_rawIn_normDist_T_33 = mux(_t_rec_rawIn_normDist_T_11, UInt<4>(0hb), _t_rec_rawIn_normDist_T_32) node _t_rec_rawIn_normDist_T_34 = mux(_t_rec_rawIn_normDist_T_12, UInt<4>(0ha), _t_rec_rawIn_normDist_T_33) node _t_rec_rawIn_normDist_T_35 = mux(_t_rec_rawIn_normDist_T_13, UInt<4>(0h9), _t_rec_rawIn_normDist_T_34) node _t_rec_rawIn_normDist_T_36 = mux(_t_rec_rawIn_normDist_T_14, UInt<4>(0h8), _t_rec_rawIn_normDist_T_35) node _t_rec_rawIn_normDist_T_37 = mux(_t_rec_rawIn_normDist_T_15, UInt<3>(0h7), _t_rec_rawIn_normDist_T_36) node _t_rec_rawIn_normDist_T_38 = mux(_t_rec_rawIn_normDist_T_16, UInt<3>(0h6), _t_rec_rawIn_normDist_T_37) node _t_rec_rawIn_normDist_T_39 = mux(_t_rec_rawIn_normDist_T_17, UInt<3>(0h5), _t_rec_rawIn_normDist_T_38) node _t_rec_rawIn_normDist_T_40 = mux(_t_rec_rawIn_normDist_T_18, UInt<3>(0h4), _t_rec_rawIn_normDist_T_39) node _t_rec_rawIn_normDist_T_41 = mux(_t_rec_rawIn_normDist_T_19, UInt<2>(0h3), _t_rec_rawIn_normDist_T_40) node _t_rec_rawIn_normDist_T_42 = mux(_t_rec_rawIn_normDist_T_20, UInt<2>(0h2), _t_rec_rawIn_normDist_T_41) node _t_rec_rawIn_normDist_T_43 = mux(_t_rec_rawIn_normDist_T_21, UInt<1>(0h1), _t_rec_rawIn_normDist_T_42) node t_rec_rawIn_normDist = mux(_t_rec_rawIn_normDist_T_22, UInt<1>(0h0), _t_rec_rawIn_normDist_T_43) node _t_rec_rawIn_subnormFract_T = dshl(t_rec_rawIn_fractIn, t_rec_rawIn_normDist) node _t_rec_rawIn_subnormFract_T_1 = bits(_t_rec_rawIn_subnormFract_T, 21, 0) node t_rec_rawIn_subnormFract = shl(_t_rec_rawIn_subnormFract_T_1, 1) node _t_rec_rawIn_adjustedExp_T = xor(t_rec_rawIn_normDist, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_1 = mux(t_rec_rawIn_isZeroExpIn, _t_rec_rawIn_adjustedExp_T, t_rec_rawIn_expIn) node _t_rec_rawIn_adjustedExp_T_2 = mux(t_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_2) node _t_rec_rawIn_adjustedExp_T_4 = add(_t_rec_rawIn_adjustedExp_T_1, _t_rec_rawIn_adjustedExp_T_3) node t_rec_rawIn_adjustedExp = tail(_t_rec_rawIn_adjustedExp_T_4, 1) node t_rec_rawIn_isZero = and(t_rec_rawIn_isZeroExpIn, t_rec_rawIn_isZeroFractIn) node _t_rec_rawIn_isSpecial_T = bits(t_rec_rawIn_adjustedExp, 8, 7) node t_rec_rawIn_isSpecial = eq(_t_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire t_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T = eq(t_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_1 = and(t_rec_rawIn_isSpecial, _t_rec_rawIn_out_isNaN_T) connect t_rec_rawIn.isNaN, _t_rec_rawIn_out_isNaN_T_1 node _t_rec_rawIn_out_isInf_T = and(t_rec_rawIn_isSpecial, t_rec_rawIn_isZeroFractIn) connect t_rec_rawIn.isInf, _t_rec_rawIn_out_isInf_T connect t_rec_rawIn.isZero, t_rec_rawIn_isZero connect t_rec_rawIn.sign, t_rec_rawIn_sign node _t_rec_rawIn_out_sExp_T = bits(t_rec_rawIn_adjustedExp, 8, 0) node _t_rec_rawIn_out_sExp_T_1 = cvt(_t_rec_rawIn_out_sExp_T) connect t_rec_rawIn.sExp, _t_rec_rawIn_out_sExp_T_1 node _t_rec_rawIn_out_sig_T = eq(t_rec_rawIn_isZero, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T) node _t_rec_rawIn_out_sig_T_2 = mux(t_rec_rawIn_isZeroExpIn, t_rec_rawIn_subnormFract, t_rec_rawIn_fractIn) node _t_rec_rawIn_out_sig_T_3 = cat(_t_rec_rawIn_out_sig_T_1, _t_rec_rawIn_out_sig_T_2) connect t_rec_rawIn.sig, _t_rec_rawIn_out_sig_T_3 node _t_rec_T = bits(t_rec_rawIn.sExp, 8, 6) node _t_rec_T_1 = mux(t_rec_rawIn.isZero, UInt<3>(0h0), _t_rec_T) node _t_rec_T_2 = mux(t_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_3 = or(_t_rec_T_1, _t_rec_T_2) node _t_rec_T_4 = cat(t_rec_rawIn.sign, _t_rec_T_3) node _t_rec_T_5 = bits(t_rec_rawIn.sExp, 5, 0) node _t_rec_T_6 = cat(_t_rec_T_4, _t_rec_T_5) node _t_rec_T_7 = bits(t_rec_rawIn.sig, 22, 0) node t_rec = cat(_t_rec_T_6, _t_rec_T_7) node self_rec_rawIn_sign = bits(in.bits.in[0].bits, 31, 31) node self_rec_rawIn_expIn = bits(in.bits.in[0].bits, 30, 23) node self_rec_rawIn_fractIn = bits(in.bits.in[0].bits, 22, 0) node self_rec_rawIn_isZeroExpIn = eq(self_rec_rawIn_expIn, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn = eq(self_rec_rawIn_fractIn, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T = bits(self_rec_rawIn_fractIn, 0, 0) node _self_rec_rawIn_normDist_T_1 = bits(self_rec_rawIn_fractIn, 1, 1) node _self_rec_rawIn_normDist_T_2 = bits(self_rec_rawIn_fractIn, 2, 2) node _self_rec_rawIn_normDist_T_3 = bits(self_rec_rawIn_fractIn, 3, 3) node _self_rec_rawIn_normDist_T_4 = bits(self_rec_rawIn_fractIn, 4, 4) node _self_rec_rawIn_normDist_T_5 = bits(self_rec_rawIn_fractIn, 5, 5) node _self_rec_rawIn_normDist_T_6 = bits(self_rec_rawIn_fractIn, 6, 6) node _self_rec_rawIn_normDist_T_7 = bits(self_rec_rawIn_fractIn, 7, 7) node _self_rec_rawIn_normDist_T_8 = bits(self_rec_rawIn_fractIn, 8, 8) node _self_rec_rawIn_normDist_T_9 = bits(self_rec_rawIn_fractIn, 9, 9) node _self_rec_rawIn_normDist_T_10 = bits(self_rec_rawIn_fractIn, 10, 10) node _self_rec_rawIn_normDist_T_11 = bits(self_rec_rawIn_fractIn, 11, 11) node _self_rec_rawIn_normDist_T_12 = bits(self_rec_rawIn_fractIn, 12, 12) node _self_rec_rawIn_normDist_T_13 = bits(self_rec_rawIn_fractIn, 13, 13) node _self_rec_rawIn_normDist_T_14 = bits(self_rec_rawIn_fractIn, 14, 14) node _self_rec_rawIn_normDist_T_15 = bits(self_rec_rawIn_fractIn, 15, 15) node _self_rec_rawIn_normDist_T_16 = bits(self_rec_rawIn_fractIn, 16, 16) node _self_rec_rawIn_normDist_T_17 = bits(self_rec_rawIn_fractIn, 17, 17) node _self_rec_rawIn_normDist_T_18 = bits(self_rec_rawIn_fractIn, 18, 18) node _self_rec_rawIn_normDist_T_19 = bits(self_rec_rawIn_fractIn, 19, 19) node _self_rec_rawIn_normDist_T_20 = bits(self_rec_rawIn_fractIn, 20, 20) node _self_rec_rawIn_normDist_T_21 = bits(self_rec_rawIn_fractIn, 21, 21) node _self_rec_rawIn_normDist_T_22 = bits(self_rec_rawIn_fractIn, 22, 22) node _self_rec_rawIn_normDist_T_23 = mux(_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_24 = mux(_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _self_rec_rawIn_normDist_T_23) node _self_rec_rawIn_normDist_T_25 = mux(_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _self_rec_rawIn_normDist_T_24) node _self_rec_rawIn_normDist_T_26 = mux(_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _self_rec_rawIn_normDist_T_25) node _self_rec_rawIn_normDist_T_27 = mux(_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _self_rec_rawIn_normDist_T_26) node _self_rec_rawIn_normDist_T_28 = mux(_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _self_rec_rawIn_normDist_T_27) node _self_rec_rawIn_normDist_T_29 = mux(_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _self_rec_rawIn_normDist_T_28) node _self_rec_rawIn_normDist_T_30 = mux(_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _self_rec_rawIn_normDist_T_29) node _self_rec_rawIn_normDist_T_31 = mux(_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _self_rec_rawIn_normDist_T_30) node _self_rec_rawIn_normDist_T_32 = mux(_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _self_rec_rawIn_normDist_T_31) node _self_rec_rawIn_normDist_T_33 = mux(_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _self_rec_rawIn_normDist_T_32) node _self_rec_rawIn_normDist_T_34 = mux(_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _self_rec_rawIn_normDist_T_33) node _self_rec_rawIn_normDist_T_35 = mux(_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _self_rec_rawIn_normDist_T_34) node _self_rec_rawIn_normDist_T_36 = mux(_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _self_rec_rawIn_normDist_T_35) node _self_rec_rawIn_normDist_T_37 = mux(_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _self_rec_rawIn_normDist_T_36) node _self_rec_rawIn_normDist_T_38 = mux(_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _self_rec_rawIn_normDist_T_37) node _self_rec_rawIn_normDist_T_39 = mux(_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _self_rec_rawIn_normDist_T_38) node _self_rec_rawIn_normDist_T_40 = mux(_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _self_rec_rawIn_normDist_T_39) node _self_rec_rawIn_normDist_T_41 = mux(_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _self_rec_rawIn_normDist_T_40) node _self_rec_rawIn_normDist_T_42 = mux(_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _self_rec_rawIn_normDist_T_41) node _self_rec_rawIn_normDist_T_43 = mux(_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _self_rec_rawIn_normDist_T_42) node self_rec_rawIn_normDist = mux(_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _self_rec_rawIn_normDist_T_43) node _self_rec_rawIn_subnormFract_T = dshl(self_rec_rawIn_fractIn, self_rec_rawIn_normDist) node _self_rec_rawIn_subnormFract_T_1 = bits(_self_rec_rawIn_subnormFract_T, 21, 0) node self_rec_rawIn_subnormFract = shl(_self_rec_rawIn_subnormFract_T_1, 1) node _self_rec_rawIn_adjustedExp_T = xor(self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_1 = mux(self_rec_rawIn_isZeroExpIn, _self_rec_rawIn_adjustedExp_T, self_rec_rawIn_expIn) node _self_rec_rawIn_adjustedExp_T_2 = mux(self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_2) node _self_rec_rawIn_adjustedExp_T_4 = add(_self_rec_rawIn_adjustedExp_T_1, _self_rec_rawIn_adjustedExp_T_3) node self_rec_rawIn_adjustedExp = tail(_self_rec_rawIn_adjustedExp_T_4, 1) node self_rec_rawIn_isZero = and(self_rec_rawIn_isZeroExpIn, self_rec_rawIn_isZeroFractIn) node _self_rec_rawIn_isSpecial_T = bits(self_rec_rawIn_adjustedExp, 8, 7) node self_rec_rawIn_isSpecial = eq(_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T = eq(self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_1 = and(self_rec_rawIn_isSpecial, _self_rec_rawIn_out_isNaN_T) connect self_rec_rawIn.isNaN, _self_rec_rawIn_out_isNaN_T_1 node _self_rec_rawIn_out_isInf_T = and(self_rec_rawIn_isSpecial, self_rec_rawIn_isZeroFractIn) connect self_rec_rawIn.isInf, _self_rec_rawIn_out_isInf_T connect self_rec_rawIn.isZero, self_rec_rawIn_isZero connect self_rec_rawIn.sign, self_rec_rawIn_sign node _self_rec_rawIn_out_sExp_T = bits(self_rec_rawIn_adjustedExp, 8, 0) node _self_rec_rawIn_out_sExp_T_1 = cvt(_self_rec_rawIn_out_sExp_T) connect self_rec_rawIn.sExp, _self_rec_rawIn_out_sExp_T_1 node _self_rec_rawIn_out_sig_T = eq(self_rec_rawIn_isZero, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T) node _self_rec_rawIn_out_sig_T_2 = mux(self_rec_rawIn_isZeroExpIn, self_rec_rawIn_subnormFract, self_rec_rawIn_fractIn) node _self_rec_rawIn_out_sig_T_3 = cat(_self_rec_rawIn_out_sig_T_1, _self_rec_rawIn_out_sig_T_2) connect self_rec_rawIn.sig, _self_rec_rawIn_out_sig_T_3 node _self_rec_T = bits(self_rec_rawIn.sExp, 8, 6) node _self_rec_T_1 = mux(self_rec_rawIn.isZero, UInt<3>(0h0), _self_rec_T) node _self_rec_T_2 = mux(self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_3 = or(_self_rec_T_1, _self_rec_T_2) node _self_rec_T_4 = cat(self_rec_rawIn.sign, _self_rec_T_3) node _self_rec_T_5 = bits(self_rec_rawIn.sExp, 5, 0) node _self_rec_T_6 = cat(_self_rec_T_4, _self_rec_T_5) node _self_rec_T_7 = bits(self_rec_rawIn.sig, 22, 0) node self_rec = cat(_self_rec_T_6, _self_rec_T_7) inst t_resizer of RecFNToRecFN_8 connect t_resizer.io.in, t_rec connect t_resizer.io.roundingMode, UInt<3>(0h0) connect t_resizer.io.detectTininess, UInt<1>(0h1) inst muladder of MulRecFN_4 connect muladder.io.roundingMode, UInt<3>(0h0) connect muladder.io.detectTininess, UInt<1>(0h1) connect muladder.io.a, self_rec connect muladder.io.b, t_resizer.io.out wire out : { bits : UInt<32>} node out_bits_rawIn_exp = bits(muladder.io.out, 31, 23) node _out_bits_rawIn_isZero_T = bits(out_bits_rawIn_exp, 8, 6) node out_bits_rawIn_isZero = eq(_out_bits_rawIn_isZero_T, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T = bits(out_bits_rawIn_exp, 8, 7) node out_bits_rawIn_isSpecial = eq(_out_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T = bits(out_bits_rawIn_exp, 6, 6) node _out_bits_rawIn_out_isNaN_T_1 = and(out_bits_rawIn_isSpecial, _out_bits_rawIn_out_isNaN_T) connect out_bits_rawIn.isNaN, _out_bits_rawIn_out_isNaN_T_1 node _out_bits_rawIn_out_isInf_T = bits(out_bits_rawIn_exp, 6, 6) node _out_bits_rawIn_out_isInf_T_1 = eq(_out_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_2 = and(out_bits_rawIn_isSpecial, _out_bits_rawIn_out_isInf_T_1) connect out_bits_rawIn.isInf, _out_bits_rawIn_out_isInf_T_2 connect out_bits_rawIn.isZero, out_bits_rawIn_isZero node _out_bits_rawIn_out_sign_T = bits(muladder.io.out, 32, 32) connect out_bits_rawIn.sign, _out_bits_rawIn_out_sign_T node _out_bits_rawIn_out_sExp_T = cvt(out_bits_rawIn_exp) connect out_bits_rawIn.sExp, _out_bits_rawIn_out_sExp_T node _out_bits_rawIn_out_sig_T = eq(out_bits_rawIn_isZero, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T) node _out_bits_rawIn_out_sig_T_2 = bits(muladder.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_3 = cat(_out_bits_rawIn_out_sig_T_1, _out_bits_rawIn_out_sig_T_2) connect out_bits_rawIn.sig, _out_bits_rawIn_out_sig_T_3 node out_bits_isSubnormal = lt(out_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T = bits(out_bits_rawIn.sExp, 4, 0) node _out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T) node out_bits_denormShiftDist = tail(_out_bits_denormShiftDist_T_1, 1) node _out_bits_denormFract_T = shr(out_bits_rawIn.sig, 1) node _out_bits_denormFract_T_1 = dshr(_out_bits_denormFract_T, out_bits_denormShiftDist) node out_bits_denormFract = bits(_out_bits_denormFract_T_1, 22, 0) node _out_bits_expOut_T = bits(out_bits_rawIn.sExp, 7, 0) node _out_bits_expOut_T_1 = sub(_out_bits_expOut_T, UInt<8>(0h81)) node _out_bits_expOut_T_2 = tail(_out_bits_expOut_T_1, 1) node _out_bits_expOut_T_3 = mux(out_bits_isSubnormal, UInt<1>(0h0), _out_bits_expOut_T_2) node _out_bits_expOut_T_4 = or(out_bits_rawIn.isNaN, out_bits_rawIn.isInf) node _out_bits_expOut_T_5 = mux(_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut = or(_out_bits_expOut_T_3, _out_bits_expOut_T_5) node _out_bits_fractOut_T = bits(out_bits_rawIn.sig, 22, 0) node _out_bits_fractOut_T_1 = mux(out_bits_rawIn.isInf, UInt<1>(0h0), _out_bits_fractOut_T) node out_bits_fractOut = mux(out_bits_isSubnormal, out_bits_denormFract, _out_bits_fractOut_T_1) node out_bits_hi = cat(out_bits_rawIn.sign, out_bits_expOut) node _out_bits_T = cat(out_bits_hi, out_bits_fractOut) connect out.bits, _out_bits_T wire _WIRE_2 : { bits : UInt<32>} wire _WIRE_3 : UInt<32> connect _WIRE_3, in.bits.scale.bits node _T_4 = bits(_WIRE_3, 31, 0) connect _WIRE_2.bits, _T_4 node t_rec_rawIn_sign_1 = bits(_WIRE_2.bits, 31, 31) node t_rec_rawIn_expIn_1 = bits(_WIRE_2.bits, 30, 23) node t_rec_rawIn_fractIn_1 = bits(_WIRE_2.bits, 22, 0) node t_rec_rawIn_isZeroExpIn_1 = eq(t_rec_rawIn_expIn_1, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn_1 = eq(t_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T_44 = bits(t_rec_rawIn_fractIn_1, 0, 0) node _t_rec_rawIn_normDist_T_45 = bits(t_rec_rawIn_fractIn_1, 1, 1) node _t_rec_rawIn_normDist_T_46 = bits(t_rec_rawIn_fractIn_1, 2, 2) node _t_rec_rawIn_normDist_T_47 = bits(t_rec_rawIn_fractIn_1, 3, 3) node _t_rec_rawIn_normDist_T_48 = bits(t_rec_rawIn_fractIn_1, 4, 4) node _t_rec_rawIn_normDist_T_49 = bits(t_rec_rawIn_fractIn_1, 5, 5) node _t_rec_rawIn_normDist_T_50 = bits(t_rec_rawIn_fractIn_1, 6, 6) node _t_rec_rawIn_normDist_T_51 = bits(t_rec_rawIn_fractIn_1, 7, 7) node _t_rec_rawIn_normDist_T_52 = bits(t_rec_rawIn_fractIn_1, 8, 8) node _t_rec_rawIn_normDist_T_53 = bits(t_rec_rawIn_fractIn_1, 9, 9) node _t_rec_rawIn_normDist_T_54 = bits(t_rec_rawIn_fractIn_1, 10, 10) node _t_rec_rawIn_normDist_T_55 = bits(t_rec_rawIn_fractIn_1, 11, 11) node _t_rec_rawIn_normDist_T_56 = bits(t_rec_rawIn_fractIn_1, 12, 12) node _t_rec_rawIn_normDist_T_57 = bits(t_rec_rawIn_fractIn_1, 13, 13) node _t_rec_rawIn_normDist_T_58 = bits(t_rec_rawIn_fractIn_1, 14, 14) node _t_rec_rawIn_normDist_T_59 = bits(t_rec_rawIn_fractIn_1, 15, 15) node _t_rec_rawIn_normDist_T_60 = bits(t_rec_rawIn_fractIn_1, 16, 16) node _t_rec_rawIn_normDist_T_61 = bits(t_rec_rawIn_fractIn_1, 17, 17) node _t_rec_rawIn_normDist_T_62 = bits(t_rec_rawIn_fractIn_1, 18, 18) node _t_rec_rawIn_normDist_T_63 = bits(t_rec_rawIn_fractIn_1, 19, 19) node _t_rec_rawIn_normDist_T_64 = bits(t_rec_rawIn_fractIn_1, 20, 20) node _t_rec_rawIn_normDist_T_65 = bits(t_rec_rawIn_fractIn_1, 21, 21) node _t_rec_rawIn_normDist_T_66 = bits(t_rec_rawIn_fractIn_1, 22, 22) node _t_rec_rawIn_normDist_T_67 = mux(_t_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_68 = mux(_t_rec_rawIn_normDist_T_46, UInt<5>(0h14), _t_rec_rawIn_normDist_T_67) node _t_rec_rawIn_normDist_T_69 = mux(_t_rec_rawIn_normDist_T_47, UInt<5>(0h13), _t_rec_rawIn_normDist_T_68) node _t_rec_rawIn_normDist_T_70 = mux(_t_rec_rawIn_normDist_T_48, UInt<5>(0h12), _t_rec_rawIn_normDist_T_69) node _t_rec_rawIn_normDist_T_71 = mux(_t_rec_rawIn_normDist_T_49, UInt<5>(0h11), _t_rec_rawIn_normDist_T_70) node _t_rec_rawIn_normDist_T_72 = mux(_t_rec_rawIn_normDist_T_50, UInt<5>(0h10), _t_rec_rawIn_normDist_T_71) node _t_rec_rawIn_normDist_T_73 = mux(_t_rec_rawIn_normDist_T_51, UInt<4>(0hf), _t_rec_rawIn_normDist_T_72) node _t_rec_rawIn_normDist_T_74 = mux(_t_rec_rawIn_normDist_T_52, UInt<4>(0he), _t_rec_rawIn_normDist_T_73) node _t_rec_rawIn_normDist_T_75 = mux(_t_rec_rawIn_normDist_T_53, UInt<4>(0hd), _t_rec_rawIn_normDist_T_74) node _t_rec_rawIn_normDist_T_76 = mux(_t_rec_rawIn_normDist_T_54, UInt<4>(0hc), _t_rec_rawIn_normDist_T_75) node _t_rec_rawIn_normDist_T_77 = mux(_t_rec_rawIn_normDist_T_55, UInt<4>(0hb), _t_rec_rawIn_normDist_T_76) node _t_rec_rawIn_normDist_T_78 = mux(_t_rec_rawIn_normDist_T_56, UInt<4>(0ha), _t_rec_rawIn_normDist_T_77) node _t_rec_rawIn_normDist_T_79 = mux(_t_rec_rawIn_normDist_T_57, UInt<4>(0h9), _t_rec_rawIn_normDist_T_78) node _t_rec_rawIn_normDist_T_80 = mux(_t_rec_rawIn_normDist_T_58, UInt<4>(0h8), _t_rec_rawIn_normDist_T_79) node _t_rec_rawIn_normDist_T_81 = mux(_t_rec_rawIn_normDist_T_59, UInt<3>(0h7), _t_rec_rawIn_normDist_T_80) node _t_rec_rawIn_normDist_T_82 = mux(_t_rec_rawIn_normDist_T_60, UInt<3>(0h6), _t_rec_rawIn_normDist_T_81) node _t_rec_rawIn_normDist_T_83 = mux(_t_rec_rawIn_normDist_T_61, UInt<3>(0h5), _t_rec_rawIn_normDist_T_82) node _t_rec_rawIn_normDist_T_84 = mux(_t_rec_rawIn_normDist_T_62, UInt<3>(0h4), _t_rec_rawIn_normDist_T_83) node _t_rec_rawIn_normDist_T_85 = mux(_t_rec_rawIn_normDist_T_63, UInt<2>(0h3), _t_rec_rawIn_normDist_T_84) node _t_rec_rawIn_normDist_T_86 = mux(_t_rec_rawIn_normDist_T_64, UInt<2>(0h2), _t_rec_rawIn_normDist_T_85) node _t_rec_rawIn_normDist_T_87 = mux(_t_rec_rawIn_normDist_T_65, UInt<1>(0h1), _t_rec_rawIn_normDist_T_86) node t_rec_rawIn_normDist_1 = mux(_t_rec_rawIn_normDist_T_66, UInt<1>(0h0), _t_rec_rawIn_normDist_T_87) node _t_rec_rawIn_subnormFract_T_2 = dshl(t_rec_rawIn_fractIn_1, t_rec_rawIn_normDist_1) node _t_rec_rawIn_subnormFract_T_3 = bits(_t_rec_rawIn_subnormFract_T_2, 21, 0) node t_rec_rawIn_subnormFract_1 = shl(_t_rec_rawIn_subnormFract_T_3, 1) node _t_rec_rawIn_adjustedExp_T_5 = xor(t_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_6 = mux(t_rec_rawIn_isZeroExpIn_1, _t_rec_rawIn_adjustedExp_T_5, t_rec_rawIn_expIn_1) node _t_rec_rawIn_adjustedExp_T_7 = mux(t_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_7) node _t_rec_rawIn_adjustedExp_T_9 = add(_t_rec_rawIn_adjustedExp_T_6, _t_rec_rawIn_adjustedExp_T_8) node t_rec_rawIn_adjustedExp_1 = tail(_t_rec_rawIn_adjustedExp_T_9, 1) node t_rec_rawIn_isZero_1 = and(t_rec_rawIn_isZeroExpIn_1, t_rec_rawIn_isZeroFractIn_1) node _t_rec_rawIn_isSpecial_T_1 = bits(t_rec_rawIn_adjustedExp_1, 8, 7) node t_rec_rawIn_isSpecial_1 = eq(_t_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire t_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T_2 = eq(t_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_3 = and(t_rec_rawIn_isSpecial_1, _t_rec_rawIn_out_isNaN_T_2) connect t_rec_rawIn_1.isNaN, _t_rec_rawIn_out_isNaN_T_3 node _t_rec_rawIn_out_isInf_T_1 = and(t_rec_rawIn_isSpecial_1, t_rec_rawIn_isZeroFractIn_1) connect t_rec_rawIn_1.isInf, _t_rec_rawIn_out_isInf_T_1 connect t_rec_rawIn_1.isZero, t_rec_rawIn_isZero_1 connect t_rec_rawIn_1.sign, t_rec_rawIn_sign_1 node _t_rec_rawIn_out_sExp_T_2 = bits(t_rec_rawIn_adjustedExp_1, 8, 0) node _t_rec_rawIn_out_sExp_T_3 = cvt(_t_rec_rawIn_out_sExp_T_2) connect t_rec_rawIn_1.sExp, _t_rec_rawIn_out_sExp_T_3 node _t_rec_rawIn_out_sig_T_4 = eq(t_rec_rawIn_isZero_1, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T_4) node _t_rec_rawIn_out_sig_T_6 = mux(t_rec_rawIn_isZeroExpIn_1, t_rec_rawIn_subnormFract_1, t_rec_rawIn_fractIn_1) node _t_rec_rawIn_out_sig_T_7 = cat(_t_rec_rawIn_out_sig_T_5, _t_rec_rawIn_out_sig_T_6) connect t_rec_rawIn_1.sig, _t_rec_rawIn_out_sig_T_7 node _t_rec_T_8 = bits(t_rec_rawIn_1.sExp, 8, 6) node _t_rec_T_9 = mux(t_rec_rawIn_1.isZero, UInt<3>(0h0), _t_rec_T_8) node _t_rec_T_10 = mux(t_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_11 = or(_t_rec_T_9, _t_rec_T_10) node _t_rec_T_12 = cat(t_rec_rawIn_1.sign, _t_rec_T_11) node _t_rec_T_13 = bits(t_rec_rawIn_1.sExp, 5, 0) node _t_rec_T_14 = cat(_t_rec_T_12, _t_rec_T_13) node _t_rec_T_15 = bits(t_rec_rawIn_1.sig, 22, 0) node t_rec_1 = cat(_t_rec_T_14, _t_rec_T_15) node self_rec_rawIn_sign_1 = bits(in.bits.in[1].bits, 31, 31) node self_rec_rawIn_expIn_1 = bits(in.bits.in[1].bits, 30, 23) node self_rec_rawIn_fractIn_1 = bits(in.bits.in[1].bits, 22, 0) node self_rec_rawIn_isZeroExpIn_1 = eq(self_rec_rawIn_expIn_1, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn_1 = eq(self_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T_44 = bits(self_rec_rawIn_fractIn_1, 0, 0) node _self_rec_rawIn_normDist_T_45 = bits(self_rec_rawIn_fractIn_1, 1, 1) node _self_rec_rawIn_normDist_T_46 = bits(self_rec_rawIn_fractIn_1, 2, 2) node _self_rec_rawIn_normDist_T_47 = bits(self_rec_rawIn_fractIn_1, 3, 3) node _self_rec_rawIn_normDist_T_48 = bits(self_rec_rawIn_fractIn_1, 4, 4) node _self_rec_rawIn_normDist_T_49 = bits(self_rec_rawIn_fractIn_1, 5, 5) node _self_rec_rawIn_normDist_T_50 = bits(self_rec_rawIn_fractIn_1, 6, 6) node _self_rec_rawIn_normDist_T_51 = bits(self_rec_rawIn_fractIn_1, 7, 7) node _self_rec_rawIn_normDist_T_52 = bits(self_rec_rawIn_fractIn_1, 8, 8) node _self_rec_rawIn_normDist_T_53 = bits(self_rec_rawIn_fractIn_1, 9, 9) node _self_rec_rawIn_normDist_T_54 = bits(self_rec_rawIn_fractIn_1, 10, 10) node _self_rec_rawIn_normDist_T_55 = bits(self_rec_rawIn_fractIn_1, 11, 11) node _self_rec_rawIn_normDist_T_56 = bits(self_rec_rawIn_fractIn_1, 12, 12) node _self_rec_rawIn_normDist_T_57 = bits(self_rec_rawIn_fractIn_1, 13, 13) node _self_rec_rawIn_normDist_T_58 = bits(self_rec_rawIn_fractIn_1, 14, 14) node _self_rec_rawIn_normDist_T_59 = bits(self_rec_rawIn_fractIn_1, 15, 15) node _self_rec_rawIn_normDist_T_60 = bits(self_rec_rawIn_fractIn_1, 16, 16) node _self_rec_rawIn_normDist_T_61 = bits(self_rec_rawIn_fractIn_1, 17, 17) node _self_rec_rawIn_normDist_T_62 = bits(self_rec_rawIn_fractIn_1, 18, 18) node _self_rec_rawIn_normDist_T_63 = bits(self_rec_rawIn_fractIn_1, 19, 19) node _self_rec_rawIn_normDist_T_64 = bits(self_rec_rawIn_fractIn_1, 20, 20) node _self_rec_rawIn_normDist_T_65 = bits(self_rec_rawIn_fractIn_1, 21, 21) node _self_rec_rawIn_normDist_T_66 = bits(self_rec_rawIn_fractIn_1, 22, 22) node _self_rec_rawIn_normDist_T_67 = mux(_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_68 = mux(_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _self_rec_rawIn_normDist_T_67) node _self_rec_rawIn_normDist_T_69 = mux(_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _self_rec_rawIn_normDist_T_68) node _self_rec_rawIn_normDist_T_70 = mux(_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _self_rec_rawIn_normDist_T_69) node _self_rec_rawIn_normDist_T_71 = mux(_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _self_rec_rawIn_normDist_T_70) node _self_rec_rawIn_normDist_T_72 = mux(_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _self_rec_rawIn_normDist_T_71) node _self_rec_rawIn_normDist_T_73 = mux(_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _self_rec_rawIn_normDist_T_72) node _self_rec_rawIn_normDist_T_74 = mux(_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _self_rec_rawIn_normDist_T_73) node _self_rec_rawIn_normDist_T_75 = mux(_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _self_rec_rawIn_normDist_T_74) node _self_rec_rawIn_normDist_T_76 = mux(_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _self_rec_rawIn_normDist_T_75) node _self_rec_rawIn_normDist_T_77 = mux(_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _self_rec_rawIn_normDist_T_76) node _self_rec_rawIn_normDist_T_78 = mux(_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _self_rec_rawIn_normDist_T_77) node _self_rec_rawIn_normDist_T_79 = mux(_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _self_rec_rawIn_normDist_T_78) node _self_rec_rawIn_normDist_T_80 = mux(_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _self_rec_rawIn_normDist_T_79) node _self_rec_rawIn_normDist_T_81 = mux(_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _self_rec_rawIn_normDist_T_80) node _self_rec_rawIn_normDist_T_82 = mux(_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _self_rec_rawIn_normDist_T_81) node _self_rec_rawIn_normDist_T_83 = mux(_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _self_rec_rawIn_normDist_T_82) node _self_rec_rawIn_normDist_T_84 = mux(_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _self_rec_rawIn_normDist_T_83) node _self_rec_rawIn_normDist_T_85 = mux(_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _self_rec_rawIn_normDist_T_84) node _self_rec_rawIn_normDist_T_86 = mux(_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _self_rec_rawIn_normDist_T_85) node _self_rec_rawIn_normDist_T_87 = mux(_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _self_rec_rawIn_normDist_T_86) node self_rec_rawIn_normDist_1 = mux(_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _self_rec_rawIn_normDist_T_87) node _self_rec_rawIn_subnormFract_T_2 = dshl(self_rec_rawIn_fractIn_1, self_rec_rawIn_normDist_1) node _self_rec_rawIn_subnormFract_T_3 = bits(_self_rec_rawIn_subnormFract_T_2, 21, 0) node self_rec_rawIn_subnormFract_1 = shl(_self_rec_rawIn_subnormFract_T_3, 1) node _self_rec_rawIn_adjustedExp_T_5 = xor(self_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_6 = mux(self_rec_rawIn_isZeroExpIn_1, _self_rec_rawIn_adjustedExp_T_5, self_rec_rawIn_expIn_1) node _self_rec_rawIn_adjustedExp_T_7 = mux(self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_7) node _self_rec_rawIn_adjustedExp_T_9 = add(_self_rec_rawIn_adjustedExp_T_6, _self_rec_rawIn_adjustedExp_T_8) node self_rec_rawIn_adjustedExp_1 = tail(_self_rec_rawIn_adjustedExp_T_9, 1) node self_rec_rawIn_isZero_1 = and(self_rec_rawIn_isZeroExpIn_1, self_rec_rawIn_isZeroFractIn_1) node _self_rec_rawIn_isSpecial_T_1 = bits(self_rec_rawIn_adjustedExp_1, 8, 7) node self_rec_rawIn_isSpecial_1 = eq(_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T_2 = eq(self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_3 = and(self_rec_rawIn_isSpecial_1, _self_rec_rawIn_out_isNaN_T_2) connect self_rec_rawIn_1.isNaN, _self_rec_rawIn_out_isNaN_T_3 node _self_rec_rawIn_out_isInf_T_1 = and(self_rec_rawIn_isSpecial_1, self_rec_rawIn_isZeroFractIn_1) connect self_rec_rawIn_1.isInf, _self_rec_rawIn_out_isInf_T_1 connect self_rec_rawIn_1.isZero, self_rec_rawIn_isZero_1 connect self_rec_rawIn_1.sign, self_rec_rawIn_sign_1 node _self_rec_rawIn_out_sExp_T_2 = bits(self_rec_rawIn_adjustedExp_1, 8, 0) node _self_rec_rawIn_out_sExp_T_3 = cvt(_self_rec_rawIn_out_sExp_T_2) connect self_rec_rawIn_1.sExp, _self_rec_rawIn_out_sExp_T_3 node _self_rec_rawIn_out_sig_T_4 = eq(self_rec_rawIn_isZero_1, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_4) node _self_rec_rawIn_out_sig_T_6 = mux(self_rec_rawIn_isZeroExpIn_1, self_rec_rawIn_subnormFract_1, self_rec_rawIn_fractIn_1) node _self_rec_rawIn_out_sig_T_7 = cat(_self_rec_rawIn_out_sig_T_5, _self_rec_rawIn_out_sig_T_6) connect self_rec_rawIn_1.sig, _self_rec_rawIn_out_sig_T_7 node _self_rec_T_8 = bits(self_rec_rawIn_1.sExp, 8, 6) node _self_rec_T_9 = mux(self_rec_rawIn_1.isZero, UInt<3>(0h0), _self_rec_T_8) node _self_rec_T_10 = mux(self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_11 = or(_self_rec_T_9, _self_rec_T_10) node _self_rec_T_12 = cat(self_rec_rawIn_1.sign, _self_rec_T_11) node _self_rec_T_13 = bits(self_rec_rawIn_1.sExp, 5, 0) node _self_rec_T_14 = cat(_self_rec_T_12, _self_rec_T_13) node _self_rec_T_15 = bits(self_rec_rawIn_1.sig, 22, 0) node self_rec_1 = cat(_self_rec_T_14, _self_rec_T_15) inst t_resizer_1 of RecFNToRecFN_9 connect t_resizer_1.io.in, t_rec_1 connect t_resizer_1.io.roundingMode, UInt<3>(0h0) connect t_resizer_1.io.detectTininess, UInt<1>(0h1) inst muladder_1 of MulRecFN_5 connect muladder_1.io.roundingMode, UInt<3>(0h0) connect muladder_1.io.detectTininess, UInt<1>(0h1) connect muladder_1.io.a, self_rec_1 connect muladder_1.io.b, t_resizer_1.io.out wire out_1 : { bits : UInt<32>} node out_bits_rawIn_exp_1 = bits(muladder_1.io.out, 31, 23) node _out_bits_rawIn_isZero_T_1 = bits(out_bits_rawIn_exp_1, 8, 6) node out_bits_rawIn_isZero_1 = eq(_out_bits_rawIn_isZero_T_1, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T_1 = bits(out_bits_rawIn_exp_1, 8, 7) node out_bits_rawIn_isSpecial_1 = eq(_out_bits_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire out_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T_2 = bits(out_bits_rawIn_exp_1, 6, 6) node _out_bits_rawIn_out_isNaN_T_3 = and(out_bits_rawIn_isSpecial_1, _out_bits_rawIn_out_isNaN_T_2) connect out_bits_rawIn_1.isNaN, _out_bits_rawIn_out_isNaN_T_3 node _out_bits_rawIn_out_isInf_T_3 = bits(out_bits_rawIn_exp_1, 6, 6) node _out_bits_rawIn_out_isInf_T_4 = eq(_out_bits_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_5 = and(out_bits_rawIn_isSpecial_1, _out_bits_rawIn_out_isInf_T_4) connect out_bits_rawIn_1.isInf, _out_bits_rawIn_out_isInf_T_5 connect out_bits_rawIn_1.isZero, out_bits_rawIn_isZero_1 node _out_bits_rawIn_out_sign_T_1 = bits(muladder_1.io.out, 32, 32) connect out_bits_rawIn_1.sign, _out_bits_rawIn_out_sign_T_1 node _out_bits_rawIn_out_sExp_T_1 = cvt(out_bits_rawIn_exp_1) connect out_bits_rawIn_1.sExp, _out_bits_rawIn_out_sExp_T_1 node _out_bits_rawIn_out_sig_T_4 = eq(out_bits_rawIn_isZero_1, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T_4) node _out_bits_rawIn_out_sig_T_6 = bits(muladder_1.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_7 = cat(_out_bits_rawIn_out_sig_T_5, _out_bits_rawIn_out_sig_T_6) connect out_bits_rawIn_1.sig, _out_bits_rawIn_out_sig_T_7 node out_bits_isSubnormal_1 = lt(out_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T_2 = bits(out_bits_rawIn_1.sExp, 4, 0) node _out_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T_2) node out_bits_denormShiftDist_1 = tail(_out_bits_denormShiftDist_T_3, 1) node _out_bits_denormFract_T_2 = shr(out_bits_rawIn_1.sig, 1) node _out_bits_denormFract_T_3 = dshr(_out_bits_denormFract_T_2, out_bits_denormShiftDist_1) node out_bits_denormFract_1 = bits(_out_bits_denormFract_T_3, 22, 0) node _out_bits_expOut_T_6 = bits(out_bits_rawIn_1.sExp, 7, 0) node _out_bits_expOut_T_7 = sub(_out_bits_expOut_T_6, UInt<8>(0h81)) node _out_bits_expOut_T_8 = tail(_out_bits_expOut_T_7, 1) node _out_bits_expOut_T_9 = mux(out_bits_isSubnormal_1, UInt<1>(0h0), _out_bits_expOut_T_8) node _out_bits_expOut_T_10 = or(out_bits_rawIn_1.isNaN, out_bits_rawIn_1.isInf) node _out_bits_expOut_T_11 = mux(_out_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut_1 = or(_out_bits_expOut_T_9, _out_bits_expOut_T_11) node _out_bits_fractOut_T_2 = bits(out_bits_rawIn_1.sig, 22, 0) node _out_bits_fractOut_T_3 = mux(out_bits_rawIn_1.isInf, UInt<1>(0h0), _out_bits_fractOut_T_2) node out_bits_fractOut_1 = mux(out_bits_isSubnormal_1, out_bits_denormFract_1, _out_bits_fractOut_T_3) node out_bits_hi_1 = cat(out_bits_rawIn_1.sign, out_bits_expOut_1) node _out_bits_T_1 = cat(out_bits_hi_1, out_bits_fractOut_1) connect out_1.bits, _out_bits_T_1 wire _WIRE_4 : { bits : UInt<32>} wire _WIRE_5 : UInt<32> connect _WIRE_5, in.bits.scale.bits node _T_5 = bits(_WIRE_5, 31, 0) connect _WIRE_4.bits, _T_5 node t_rec_rawIn_sign_2 = bits(_WIRE_4.bits, 31, 31) node t_rec_rawIn_expIn_2 = bits(_WIRE_4.bits, 30, 23) node t_rec_rawIn_fractIn_2 = bits(_WIRE_4.bits, 22, 0) node t_rec_rawIn_isZeroExpIn_2 = eq(t_rec_rawIn_expIn_2, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn_2 = eq(t_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T_88 = bits(t_rec_rawIn_fractIn_2, 0, 0) node _t_rec_rawIn_normDist_T_89 = bits(t_rec_rawIn_fractIn_2, 1, 1) node _t_rec_rawIn_normDist_T_90 = bits(t_rec_rawIn_fractIn_2, 2, 2) node _t_rec_rawIn_normDist_T_91 = bits(t_rec_rawIn_fractIn_2, 3, 3) node _t_rec_rawIn_normDist_T_92 = bits(t_rec_rawIn_fractIn_2, 4, 4) node _t_rec_rawIn_normDist_T_93 = bits(t_rec_rawIn_fractIn_2, 5, 5) node _t_rec_rawIn_normDist_T_94 = bits(t_rec_rawIn_fractIn_2, 6, 6) node _t_rec_rawIn_normDist_T_95 = bits(t_rec_rawIn_fractIn_2, 7, 7) node _t_rec_rawIn_normDist_T_96 = bits(t_rec_rawIn_fractIn_2, 8, 8) node _t_rec_rawIn_normDist_T_97 = bits(t_rec_rawIn_fractIn_2, 9, 9) node _t_rec_rawIn_normDist_T_98 = bits(t_rec_rawIn_fractIn_2, 10, 10) node _t_rec_rawIn_normDist_T_99 = bits(t_rec_rawIn_fractIn_2, 11, 11) node _t_rec_rawIn_normDist_T_100 = bits(t_rec_rawIn_fractIn_2, 12, 12) node _t_rec_rawIn_normDist_T_101 = bits(t_rec_rawIn_fractIn_2, 13, 13) node _t_rec_rawIn_normDist_T_102 = bits(t_rec_rawIn_fractIn_2, 14, 14) node _t_rec_rawIn_normDist_T_103 = bits(t_rec_rawIn_fractIn_2, 15, 15) node _t_rec_rawIn_normDist_T_104 = bits(t_rec_rawIn_fractIn_2, 16, 16) node _t_rec_rawIn_normDist_T_105 = bits(t_rec_rawIn_fractIn_2, 17, 17) node _t_rec_rawIn_normDist_T_106 = bits(t_rec_rawIn_fractIn_2, 18, 18) node _t_rec_rawIn_normDist_T_107 = bits(t_rec_rawIn_fractIn_2, 19, 19) node _t_rec_rawIn_normDist_T_108 = bits(t_rec_rawIn_fractIn_2, 20, 20) node _t_rec_rawIn_normDist_T_109 = bits(t_rec_rawIn_fractIn_2, 21, 21) node _t_rec_rawIn_normDist_T_110 = bits(t_rec_rawIn_fractIn_2, 22, 22) node _t_rec_rawIn_normDist_T_111 = mux(_t_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_112 = mux(_t_rec_rawIn_normDist_T_90, UInt<5>(0h14), _t_rec_rawIn_normDist_T_111) node _t_rec_rawIn_normDist_T_113 = mux(_t_rec_rawIn_normDist_T_91, UInt<5>(0h13), _t_rec_rawIn_normDist_T_112) node _t_rec_rawIn_normDist_T_114 = mux(_t_rec_rawIn_normDist_T_92, UInt<5>(0h12), _t_rec_rawIn_normDist_T_113) node _t_rec_rawIn_normDist_T_115 = mux(_t_rec_rawIn_normDist_T_93, UInt<5>(0h11), _t_rec_rawIn_normDist_T_114) node _t_rec_rawIn_normDist_T_116 = mux(_t_rec_rawIn_normDist_T_94, UInt<5>(0h10), _t_rec_rawIn_normDist_T_115) node _t_rec_rawIn_normDist_T_117 = mux(_t_rec_rawIn_normDist_T_95, UInt<4>(0hf), _t_rec_rawIn_normDist_T_116) node _t_rec_rawIn_normDist_T_118 = mux(_t_rec_rawIn_normDist_T_96, UInt<4>(0he), _t_rec_rawIn_normDist_T_117) node _t_rec_rawIn_normDist_T_119 = mux(_t_rec_rawIn_normDist_T_97, UInt<4>(0hd), _t_rec_rawIn_normDist_T_118) node _t_rec_rawIn_normDist_T_120 = mux(_t_rec_rawIn_normDist_T_98, UInt<4>(0hc), _t_rec_rawIn_normDist_T_119) node _t_rec_rawIn_normDist_T_121 = mux(_t_rec_rawIn_normDist_T_99, UInt<4>(0hb), _t_rec_rawIn_normDist_T_120) node _t_rec_rawIn_normDist_T_122 = mux(_t_rec_rawIn_normDist_T_100, UInt<4>(0ha), _t_rec_rawIn_normDist_T_121) node _t_rec_rawIn_normDist_T_123 = mux(_t_rec_rawIn_normDist_T_101, UInt<4>(0h9), _t_rec_rawIn_normDist_T_122) node _t_rec_rawIn_normDist_T_124 = mux(_t_rec_rawIn_normDist_T_102, UInt<4>(0h8), _t_rec_rawIn_normDist_T_123) node _t_rec_rawIn_normDist_T_125 = mux(_t_rec_rawIn_normDist_T_103, UInt<3>(0h7), _t_rec_rawIn_normDist_T_124) node _t_rec_rawIn_normDist_T_126 = mux(_t_rec_rawIn_normDist_T_104, UInt<3>(0h6), _t_rec_rawIn_normDist_T_125) node _t_rec_rawIn_normDist_T_127 = mux(_t_rec_rawIn_normDist_T_105, UInt<3>(0h5), _t_rec_rawIn_normDist_T_126) node _t_rec_rawIn_normDist_T_128 = mux(_t_rec_rawIn_normDist_T_106, UInt<3>(0h4), _t_rec_rawIn_normDist_T_127) node _t_rec_rawIn_normDist_T_129 = mux(_t_rec_rawIn_normDist_T_107, UInt<2>(0h3), _t_rec_rawIn_normDist_T_128) node _t_rec_rawIn_normDist_T_130 = mux(_t_rec_rawIn_normDist_T_108, UInt<2>(0h2), _t_rec_rawIn_normDist_T_129) node _t_rec_rawIn_normDist_T_131 = mux(_t_rec_rawIn_normDist_T_109, UInt<1>(0h1), _t_rec_rawIn_normDist_T_130) node t_rec_rawIn_normDist_2 = mux(_t_rec_rawIn_normDist_T_110, UInt<1>(0h0), _t_rec_rawIn_normDist_T_131) node _t_rec_rawIn_subnormFract_T_4 = dshl(t_rec_rawIn_fractIn_2, t_rec_rawIn_normDist_2) node _t_rec_rawIn_subnormFract_T_5 = bits(_t_rec_rawIn_subnormFract_T_4, 21, 0) node t_rec_rawIn_subnormFract_2 = shl(_t_rec_rawIn_subnormFract_T_5, 1) node _t_rec_rawIn_adjustedExp_T_10 = xor(t_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_11 = mux(t_rec_rawIn_isZeroExpIn_2, _t_rec_rawIn_adjustedExp_T_10, t_rec_rawIn_expIn_2) node _t_rec_rawIn_adjustedExp_T_12 = mux(t_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_12) node _t_rec_rawIn_adjustedExp_T_14 = add(_t_rec_rawIn_adjustedExp_T_11, _t_rec_rawIn_adjustedExp_T_13) node t_rec_rawIn_adjustedExp_2 = tail(_t_rec_rawIn_adjustedExp_T_14, 1) node t_rec_rawIn_isZero_2 = and(t_rec_rawIn_isZeroExpIn_2, t_rec_rawIn_isZeroFractIn_2) node _t_rec_rawIn_isSpecial_T_2 = bits(t_rec_rawIn_adjustedExp_2, 8, 7) node t_rec_rawIn_isSpecial_2 = eq(_t_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire t_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T_4 = eq(t_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_5 = and(t_rec_rawIn_isSpecial_2, _t_rec_rawIn_out_isNaN_T_4) connect t_rec_rawIn_2.isNaN, _t_rec_rawIn_out_isNaN_T_5 node _t_rec_rawIn_out_isInf_T_2 = and(t_rec_rawIn_isSpecial_2, t_rec_rawIn_isZeroFractIn_2) connect t_rec_rawIn_2.isInf, _t_rec_rawIn_out_isInf_T_2 connect t_rec_rawIn_2.isZero, t_rec_rawIn_isZero_2 connect t_rec_rawIn_2.sign, t_rec_rawIn_sign_2 node _t_rec_rawIn_out_sExp_T_4 = bits(t_rec_rawIn_adjustedExp_2, 8, 0) node _t_rec_rawIn_out_sExp_T_5 = cvt(_t_rec_rawIn_out_sExp_T_4) connect t_rec_rawIn_2.sExp, _t_rec_rawIn_out_sExp_T_5 node _t_rec_rawIn_out_sig_T_8 = eq(t_rec_rawIn_isZero_2, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T_8) node _t_rec_rawIn_out_sig_T_10 = mux(t_rec_rawIn_isZeroExpIn_2, t_rec_rawIn_subnormFract_2, t_rec_rawIn_fractIn_2) node _t_rec_rawIn_out_sig_T_11 = cat(_t_rec_rawIn_out_sig_T_9, _t_rec_rawIn_out_sig_T_10) connect t_rec_rawIn_2.sig, _t_rec_rawIn_out_sig_T_11 node _t_rec_T_16 = bits(t_rec_rawIn_2.sExp, 8, 6) node _t_rec_T_17 = mux(t_rec_rawIn_2.isZero, UInt<3>(0h0), _t_rec_T_16) node _t_rec_T_18 = mux(t_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_19 = or(_t_rec_T_17, _t_rec_T_18) node _t_rec_T_20 = cat(t_rec_rawIn_2.sign, _t_rec_T_19) node _t_rec_T_21 = bits(t_rec_rawIn_2.sExp, 5, 0) node _t_rec_T_22 = cat(_t_rec_T_20, _t_rec_T_21) node _t_rec_T_23 = bits(t_rec_rawIn_2.sig, 22, 0) node t_rec_2 = cat(_t_rec_T_22, _t_rec_T_23) node self_rec_rawIn_sign_2 = bits(in.bits.in[2].bits, 31, 31) node self_rec_rawIn_expIn_2 = bits(in.bits.in[2].bits, 30, 23) node self_rec_rawIn_fractIn_2 = bits(in.bits.in[2].bits, 22, 0) node self_rec_rawIn_isZeroExpIn_2 = eq(self_rec_rawIn_expIn_2, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn_2 = eq(self_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T_88 = bits(self_rec_rawIn_fractIn_2, 0, 0) node _self_rec_rawIn_normDist_T_89 = bits(self_rec_rawIn_fractIn_2, 1, 1) node _self_rec_rawIn_normDist_T_90 = bits(self_rec_rawIn_fractIn_2, 2, 2) node _self_rec_rawIn_normDist_T_91 = bits(self_rec_rawIn_fractIn_2, 3, 3) node _self_rec_rawIn_normDist_T_92 = bits(self_rec_rawIn_fractIn_2, 4, 4) node _self_rec_rawIn_normDist_T_93 = bits(self_rec_rawIn_fractIn_2, 5, 5) node _self_rec_rawIn_normDist_T_94 = bits(self_rec_rawIn_fractIn_2, 6, 6) node _self_rec_rawIn_normDist_T_95 = bits(self_rec_rawIn_fractIn_2, 7, 7) node _self_rec_rawIn_normDist_T_96 = bits(self_rec_rawIn_fractIn_2, 8, 8) node _self_rec_rawIn_normDist_T_97 = bits(self_rec_rawIn_fractIn_2, 9, 9) node _self_rec_rawIn_normDist_T_98 = bits(self_rec_rawIn_fractIn_2, 10, 10) node _self_rec_rawIn_normDist_T_99 = bits(self_rec_rawIn_fractIn_2, 11, 11) node _self_rec_rawIn_normDist_T_100 = bits(self_rec_rawIn_fractIn_2, 12, 12) node _self_rec_rawIn_normDist_T_101 = bits(self_rec_rawIn_fractIn_2, 13, 13) node _self_rec_rawIn_normDist_T_102 = bits(self_rec_rawIn_fractIn_2, 14, 14) node _self_rec_rawIn_normDist_T_103 = bits(self_rec_rawIn_fractIn_2, 15, 15) node _self_rec_rawIn_normDist_T_104 = bits(self_rec_rawIn_fractIn_2, 16, 16) node _self_rec_rawIn_normDist_T_105 = bits(self_rec_rawIn_fractIn_2, 17, 17) node _self_rec_rawIn_normDist_T_106 = bits(self_rec_rawIn_fractIn_2, 18, 18) node _self_rec_rawIn_normDist_T_107 = bits(self_rec_rawIn_fractIn_2, 19, 19) node _self_rec_rawIn_normDist_T_108 = bits(self_rec_rawIn_fractIn_2, 20, 20) node _self_rec_rawIn_normDist_T_109 = bits(self_rec_rawIn_fractIn_2, 21, 21) node _self_rec_rawIn_normDist_T_110 = bits(self_rec_rawIn_fractIn_2, 22, 22) node _self_rec_rawIn_normDist_T_111 = mux(_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_112 = mux(_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _self_rec_rawIn_normDist_T_111) node _self_rec_rawIn_normDist_T_113 = mux(_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _self_rec_rawIn_normDist_T_112) node _self_rec_rawIn_normDist_T_114 = mux(_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _self_rec_rawIn_normDist_T_113) node _self_rec_rawIn_normDist_T_115 = mux(_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _self_rec_rawIn_normDist_T_114) node _self_rec_rawIn_normDist_T_116 = mux(_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _self_rec_rawIn_normDist_T_115) node _self_rec_rawIn_normDist_T_117 = mux(_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _self_rec_rawIn_normDist_T_116) node _self_rec_rawIn_normDist_T_118 = mux(_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _self_rec_rawIn_normDist_T_117) node _self_rec_rawIn_normDist_T_119 = mux(_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _self_rec_rawIn_normDist_T_118) node _self_rec_rawIn_normDist_T_120 = mux(_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _self_rec_rawIn_normDist_T_119) node _self_rec_rawIn_normDist_T_121 = mux(_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _self_rec_rawIn_normDist_T_120) node _self_rec_rawIn_normDist_T_122 = mux(_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _self_rec_rawIn_normDist_T_121) node _self_rec_rawIn_normDist_T_123 = mux(_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _self_rec_rawIn_normDist_T_122) node _self_rec_rawIn_normDist_T_124 = mux(_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _self_rec_rawIn_normDist_T_123) node _self_rec_rawIn_normDist_T_125 = mux(_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _self_rec_rawIn_normDist_T_124) node _self_rec_rawIn_normDist_T_126 = mux(_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _self_rec_rawIn_normDist_T_125) node _self_rec_rawIn_normDist_T_127 = mux(_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _self_rec_rawIn_normDist_T_126) node _self_rec_rawIn_normDist_T_128 = mux(_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _self_rec_rawIn_normDist_T_127) node _self_rec_rawIn_normDist_T_129 = mux(_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _self_rec_rawIn_normDist_T_128) node _self_rec_rawIn_normDist_T_130 = mux(_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _self_rec_rawIn_normDist_T_129) node _self_rec_rawIn_normDist_T_131 = mux(_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _self_rec_rawIn_normDist_T_130) node self_rec_rawIn_normDist_2 = mux(_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _self_rec_rawIn_normDist_T_131) node _self_rec_rawIn_subnormFract_T_4 = dshl(self_rec_rawIn_fractIn_2, self_rec_rawIn_normDist_2) node _self_rec_rawIn_subnormFract_T_5 = bits(_self_rec_rawIn_subnormFract_T_4, 21, 0) node self_rec_rawIn_subnormFract_2 = shl(_self_rec_rawIn_subnormFract_T_5, 1) node _self_rec_rawIn_adjustedExp_T_10 = xor(self_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_11 = mux(self_rec_rawIn_isZeroExpIn_2, _self_rec_rawIn_adjustedExp_T_10, self_rec_rawIn_expIn_2) node _self_rec_rawIn_adjustedExp_T_12 = mux(self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_12) node _self_rec_rawIn_adjustedExp_T_14 = add(_self_rec_rawIn_adjustedExp_T_11, _self_rec_rawIn_adjustedExp_T_13) node self_rec_rawIn_adjustedExp_2 = tail(_self_rec_rawIn_adjustedExp_T_14, 1) node self_rec_rawIn_isZero_2 = and(self_rec_rawIn_isZeroExpIn_2, self_rec_rawIn_isZeroFractIn_2) node _self_rec_rawIn_isSpecial_T_2 = bits(self_rec_rawIn_adjustedExp_2, 8, 7) node self_rec_rawIn_isSpecial_2 = eq(_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T_4 = eq(self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_5 = and(self_rec_rawIn_isSpecial_2, _self_rec_rawIn_out_isNaN_T_4) connect self_rec_rawIn_2.isNaN, _self_rec_rawIn_out_isNaN_T_5 node _self_rec_rawIn_out_isInf_T_2 = and(self_rec_rawIn_isSpecial_2, self_rec_rawIn_isZeroFractIn_2) connect self_rec_rawIn_2.isInf, _self_rec_rawIn_out_isInf_T_2 connect self_rec_rawIn_2.isZero, self_rec_rawIn_isZero_2 connect self_rec_rawIn_2.sign, self_rec_rawIn_sign_2 node _self_rec_rawIn_out_sExp_T_4 = bits(self_rec_rawIn_adjustedExp_2, 8, 0) node _self_rec_rawIn_out_sExp_T_5 = cvt(_self_rec_rawIn_out_sExp_T_4) connect self_rec_rawIn_2.sExp, _self_rec_rawIn_out_sExp_T_5 node _self_rec_rawIn_out_sig_T_8 = eq(self_rec_rawIn_isZero_2, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_8) node _self_rec_rawIn_out_sig_T_10 = mux(self_rec_rawIn_isZeroExpIn_2, self_rec_rawIn_subnormFract_2, self_rec_rawIn_fractIn_2) node _self_rec_rawIn_out_sig_T_11 = cat(_self_rec_rawIn_out_sig_T_9, _self_rec_rawIn_out_sig_T_10) connect self_rec_rawIn_2.sig, _self_rec_rawIn_out_sig_T_11 node _self_rec_T_16 = bits(self_rec_rawIn_2.sExp, 8, 6) node _self_rec_T_17 = mux(self_rec_rawIn_2.isZero, UInt<3>(0h0), _self_rec_T_16) node _self_rec_T_18 = mux(self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_19 = or(_self_rec_T_17, _self_rec_T_18) node _self_rec_T_20 = cat(self_rec_rawIn_2.sign, _self_rec_T_19) node _self_rec_T_21 = bits(self_rec_rawIn_2.sExp, 5, 0) node _self_rec_T_22 = cat(_self_rec_T_20, _self_rec_T_21) node _self_rec_T_23 = bits(self_rec_rawIn_2.sig, 22, 0) node self_rec_2 = cat(_self_rec_T_22, _self_rec_T_23) inst t_resizer_2 of RecFNToRecFN_10 connect t_resizer_2.io.in, t_rec_2 connect t_resizer_2.io.roundingMode, UInt<3>(0h0) connect t_resizer_2.io.detectTininess, UInt<1>(0h1) inst muladder_2 of MulRecFN_6 connect muladder_2.io.roundingMode, UInt<3>(0h0) connect muladder_2.io.detectTininess, UInt<1>(0h1) connect muladder_2.io.a, self_rec_2 connect muladder_2.io.b, t_resizer_2.io.out wire out_2 : { bits : UInt<32>} node out_bits_rawIn_exp_2 = bits(muladder_2.io.out, 31, 23) node _out_bits_rawIn_isZero_T_2 = bits(out_bits_rawIn_exp_2, 8, 6) node out_bits_rawIn_isZero_2 = eq(_out_bits_rawIn_isZero_T_2, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T_2 = bits(out_bits_rawIn_exp_2, 8, 7) node out_bits_rawIn_isSpecial_2 = eq(_out_bits_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire out_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T_4 = bits(out_bits_rawIn_exp_2, 6, 6) node _out_bits_rawIn_out_isNaN_T_5 = and(out_bits_rawIn_isSpecial_2, _out_bits_rawIn_out_isNaN_T_4) connect out_bits_rawIn_2.isNaN, _out_bits_rawIn_out_isNaN_T_5 node _out_bits_rawIn_out_isInf_T_6 = bits(out_bits_rawIn_exp_2, 6, 6) node _out_bits_rawIn_out_isInf_T_7 = eq(_out_bits_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_8 = and(out_bits_rawIn_isSpecial_2, _out_bits_rawIn_out_isInf_T_7) connect out_bits_rawIn_2.isInf, _out_bits_rawIn_out_isInf_T_8 connect out_bits_rawIn_2.isZero, out_bits_rawIn_isZero_2 node _out_bits_rawIn_out_sign_T_2 = bits(muladder_2.io.out, 32, 32) connect out_bits_rawIn_2.sign, _out_bits_rawIn_out_sign_T_2 node _out_bits_rawIn_out_sExp_T_2 = cvt(out_bits_rawIn_exp_2) connect out_bits_rawIn_2.sExp, _out_bits_rawIn_out_sExp_T_2 node _out_bits_rawIn_out_sig_T_8 = eq(out_bits_rawIn_isZero_2, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T_8) node _out_bits_rawIn_out_sig_T_10 = bits(muladder_2.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_11 = cat(_out_bits_rawIn_out_sig_T_9, _out_bits_rawIn_out_sig_T_10) connect out_bits_rawIn_2.sig, _out_bits_rawIn_out_sig_T_11 node out_bits_isSubnormal_2 = lt(out_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T_4 = bits(out_bits_rawIn_2.sExp, 4, 0) node _out_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T_4) node out_bits_denormShiftDist_2 = tail(_out_bits_denormShiftDist_T_5, 1) node _out_bits_denormFract_T_4 = shr(out_bits_rawIn_2.sig, 1) node _out_bits_denormFract_T_5 = dshr(_out_bits_denormFract_T_4, out_bits_denormShiftDist_2) node out_bits_denormFract_2 = bits(_out_bits_denormFract_T_5, 22, 0) node _out_bits_expOut_T_12 = bits(out_bits_rawIn_2.sExp, 7, 0) node _out_bits_expOut_T_13 = sub(_out_bits_expOut_T_12, UInt<8>(0h81)) node _out_bits_expOut_T_14 = tail(_out_bits_expOut_T_13, 1) node _out_bits_expOut_T_15 = mux(out_bits_isSubnormal_2, UInt<1>(0h0), _out_bits_expOut_T_14) node _out_bits_expOut_T_16 = or(out_bits_rawIn_2.isNaN, out_bits_rawIn_2.isInf) node _out_bits_expOut_T_17 = mux(_out_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut_2 = or(_out_bits_expOut_T_15, _out_bits_expOut_T_17) node _out_bits_fractOut_T_4 = bits(out_bits_rawIn_2.sig, 22, 0) node _out_bits_fractOut_T_5 = mux(out_bits_rawIn_2.isInf, UInt<1>(0h0), _out_bits_fractOut_T_4) node out_bits_fractOut_2 = mux(out_bits_isSubnormal_2, out_bits_denormFract_2, _out_bits_fractOut_T_5) node out_bits_hi_2 = cat(out_bits_rawIn_2.sign, out_bits_expOut_2) node _out_bits_T_2 = cat(out_bits_hi_2, out_bits_fractOut_2) connect out_2.bits, _out_bits_T_2 wire _WIRE_6 : { bits : UInt<32>} wire _WIRE_7 : UInt<32> connect _WIRE_7, in.bits.scale.bits node _T_6 = bits(_WIRE_7, 31, 0) connect _WIRE_6.bits, _T_6 node t_rec_rawIn_sign_3 = bits(_WIRE_6.bits, 31, 31) node t_rec_rawIn_expIn_3 = bits(_WIRE_6.bits, 30, 23) node t_rec_rawIn_fractIn_3 = bits(_WIRE_6.bits, 22, 0) node t_rec_rawIn_isZeroExpIn_3 = eq(t_rec_rawIn_expIn_3, UInt<1>(0h0)) node t_rec_rawIn_isZeroFractIn_3 = eq(t_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _t_rec_rawIn_normDist_T_132 = bits(t_rec_rawIn_fractIn_3, 0, 0) node _t_rec_rawIn_normDist_T_133 = bits(t_rec_rawIn_fractIn_3, 1, 1) node _t_rec_rawIn_normDist_T_134 = bits(t_rec_rawIn_fractIn_3, 2, 2) node _t_rec_rawIn_normDist_T_135 = bits(t_rec_rawIn_fractIn_3, 3, 3) node _t_rec_rawIn_normDist_T_136 = bits(t_rec_rawIn_fractIn_3, 4, 4) node _t_rec_rawIn_normDist_T_137 = bits(t_rec_rawIn_fractIn_3, 5, 5) node _t_rec_rawIn_normDist_T_138 = bits(t_rec_rawIn_fractIn_3, 6, 6) node _t_rec_rawIn_normDist_T_139 = bits(t_rec_rawIn_fractIn_3, 7, 7) node _t_rec_rawIn_normDist_T_140 = bits(t_rec_rawIn_fractIn_3, 8, 8) node _t_rec_rawIn_normDist_T_141 = bits(t_rec_rawIn_fractIn_3, 9, 9) node _t_rec_rawIn_normDist_T_142 = bits(t_rec_rawIn_fractIn_3, 10, 10) node _t_rec_rawIn_normDist_T_143 = bits(t_rec_rawIn_fractIn_3, 11, 11) node _t_rec_rawIn_normDist_T_144 = bits(t_rec_rawIn_fractIn_3, 12, 12) node _t_rec_rawIn_normDist_T_145 = bits(t_rec_rawIn_fractIn_3, 13, 13) node _t_rec_rawIn_normDist_T_146 = bits(t_rec_rawIn_fractIn_3, 14, 14) node _t_rec_rawIn_normDist_T_147 = bits(t_rec_rawIn_fractIn_3, 15, 15) node _t_rec_rawIn_normDist_T_148 = bits(t_rec_rawIn_fractIn_3, 16, 16) node _t_rec_rawIn_normDist_T_149 = bits(t_rec_rawIn_fractIn_3, 17, 17) node _t_rec_rawIn_normDist_T_150 = bits(t_rec_rawIn_fractIn_3, 18, 18) node _t_rec_rawIn_normDist_T_151 = bits(t_rec_rawIn_fractIn_3, 19, 19) node _t_rec_rawIn_normDist_T_152 = bits(t_rec_rawIn_fractIn_3, 20, 20) node _t_rec_rawIn_normDist_T_153 = bits(t_rec_rawIn_fractIn_3, 21, 21) node _t_rec_rawIn_normDist_T_154 = bits(t_rec_rawIn_fractIn_3, 22, 22) node _t_rec_rawIn_normDist_T_155 = mux(_t_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _t_rec_rawIn_normDist_T_156 = mux(_t_rec_rawIn_normDist_T_134, UInt<5>(0h14), _t_rec_rawIn_normDist_T_155) node _t_rec_rawIn_normDist_T_157 = mux(_t_rec_rawIn_normDist_T_135, UInt<5>(0h13), _t_rec_rawIn_normDist_T_156) node _t_rec_rawIn_normDist_T_158 = mux(_t_rec_rawIn_normDist_T_136, UInt<5>(0h12), _t_rec_rawIn_normDist_T_157) node _t_rec_rawIn_normDist_T_159 = mux(_t_rec_rawIn_normDist_T_137, UInt<5>(0h11), _t_rec_rawIn_normDist_T_158) node _t_rec_rawIn_normDist_T_160 = mux(_t_rec_rawIn_normDist_T_138, UInt<5>(0h10), _t_rec_rawIn_normDist_T_159) node _t_rec_rawIn_normDist_T_161 = mux(_t_rec_rawIn_normDist_T_139, UInt<4>(0hf), _t_rec_rawIn_normDist_T_160) node _t_rec_rawIn_normDist_T_162 = mux(_t_rec_rawIn_normDist_T_140, UInt<4>(0he), _t_rec_rawIn_normDist_T_161) node _t_rec_rawIn_normDist_T_163 = mux(_t_rec_rawIn_normDist_T_141, UInt<4>(0hd), _t_rec_rawIn_normDist_T_162) node _t_rec_rawIn_normDist_T_164 = mux(_t_rec_rawIn_normDist_T_142, UInt<4>(0hc), _t_rec_rawIn_normDist_T_163) node _t_rec_rawIn_normDist_T_165 = mux(_t_rec_rawIn_normDist_T_143, UInt<4>(0hb), _t_rec_rawIn_normDist_T_164) node _t_rec_rawIn_normDist_T_166 = mux(_t_rec_rawIn_normDist_T_144, UInt<4>(0ha), _t_rec_rawIn_normDist_T_165) node _t_rec_rawIn_normDist_T_167 = mux(_t_rec_rawIn_normDist_T_145, UInt<4>(0h9), _t_rec_rawIn_normDist_T_166) node _t_rec_rawIn_normDist_T_168 = mux(_t_rec_rawIn_normDist_T_146, UInt<4>(0h8), _t_rec_rawIn_normDist_T_167) node _t_rec_rawIn_normDist_T_169 = mux(_t_rec_rawIn_normDist_T_147, UInt<3>(0h7), _t_rec_rawIn_normDist_T_168) node _t_rec_rawIn_normDist_T_170 = mux(_t_rec_rawIn_normDist_T_148, UInt<3>(0h6), _t_rec_rawIn_normDist_T_169) node _t_rec_rawIn_normDist_T_171 = mux(_t_rec_rawIn_normDist_T_149, UInt<3>(0h5), _t_rec_rawIn_normDist_T_170) node _t_rec_rawIn_normDist_T_172 = mux(_t_rec_rawIn_normDist_T_150, UInt<3>(0h4), _t_rec_rawIn_normDist_T_171) node _t_rec_rawIn_normDist_T_173 = mux(_t_rec_rawIn_normDist_T_151, UInt<2>(0h3), _t_rec_rawIn_normDist_T_172) node _t_rec_rawIn_normDist_T_174 = mux(_t_rec_rawIn_normDist_T_152, UInt<2>(0h2), _t_rec_rawIn_normDist_T_173) node _t_rec_rawIn_normDist_T_175 = mux(_t_rec_rawIn_normDist_T_153, UInt<1>(0h1), _t_rec_rawIn_normDist_T_174) node t_rec_rawIn_normDist_3 = mux(_t_rec_rawIn_normDist_T_154, UInt<1>(0h0), _t_rec_rawIn_normDist_T_175) node _t_rec_rawIn_subnormFract_T_6 = dshl(t_rec_rawIn_fractIn_3, t_rec_rawIn_normDist_3) node _t_rec_rawIn_subnormFract_T_7 = bits(_t_rec_rawIn_subnormFract_T_6, 21, 0) node t_rec_rawIn_subnormFract_3 = shl(_t_rec_rawIn_subnormFract_T_7, 1) node _t_rec_rawIn_adjustedExp_T_15 = xor(t_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _t_rec_rawIn_adjustedExp_T_16 = mux(t_rec_rawIn_isZeroExpIn_3, _t_rec_rawIn_adjustedExp_T_15, t_rec_rawIn_expIn_3) node _t_rec_rawIn_adjustedExp_T_17 = mux(t_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _t_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _t_rec_rawIn_adjustedExp_T_17) node _t_rec_rawIn_adjustedExp_T_19 = add(_t_rec_rawIn_adjustedExp_T_16, _t_rec_rawIn_adjustedExp_T_18) node t_rec_rawIn_adjustedExp_3 = tail(_t_rec_rawIn_adjustedExp_T_19, 1) node t_rec_rawIn_isZero_3 = and(t_rec_rawIn_isZeroExpIn_3, t_rec_rawIn_isZeroFractIn_3) node _t_rec_rawIn_isSpecial_T_3 = bits(t_rec_rawIn_adjustedExp_3, 8, 7) node t_rec_rawIn_isSpecial_3 = eq(_t_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire t_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _t_rec_rawIn_out_isNaN_T_6 = eq(t_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _t_rec_rawIn_out_isNaN_T_7 = and(t_rec_rawIn_isSpecial_3, _t_rec_rawIn_out_isNaN_T_6) connect t_rec_rawIn_3.isNaN, _t_rec_rawIn_out_isNaN_T_7 node _t_rec_rawIn_out_isInf_T_3 = and(t_rec_rawIn_isSpecial_3, t_rec_rawIn_isZeroFractIn_3) connect t_rec_rawIn_3.isInf, _t_rec_rawIn_out_isInf_T_3 connect t_rec_rawIn_3.isZero, t_rec_rawIn_isZero_3 connect t_rec_rawIn_3.sign, t_rec_rawIn_sign_3 node _t_rec_rawIn_out_sExp_T_6 = bits(t_rec_rawIn_adjustedExp_3, 8, 0) node _t_rec_rawIn_out_sExp_T_7 = cvt(_t_rec_rawIn_out_sExp_T_6) connect t_rec_rawIn_3.sExp, _t_rec_rawIn_out_sExp_T_7 node _t_rec_rawIn_out_sig_T_12 = eq(t_rec_rawIn_isZero_3, UInt<1>(0h0)) node _t_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _t_rec_rawIn_out_sig_T_12) node _t_rec_rawIn_out_sig_T_14 = mux(t_rec_rawIn_isZeroExpIn_3, t_rec_rawIn_subnormFract_3, t_rec_rawIn_fractIn_3) node _t_rec_rawIn_out_sig_T_15 = cat(_t_rec_rawIn_out_sig_T_13, _t_rec_rawIn_out_sig_T_14) connect t_rec_rawIn_3.sig, _t_rec_rawIn_out_sig_T_15 node _t_rec_T_24 = bits(t_rec_rawIn_3.sExp, 8, 6) node _t_rec_T_25 = mux(t_rec_rawIn_3.isZero, UInt<3>(0h0), _t_rec_T_24) node _t_rec_T_26 = mux(t_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _t_rec_T_27 = or(_t_rec_T_25, _t_rec_T_26) node _t_rec_T_28 = cat(t_rec_rawIn_3.sign, _t_rec_T_27) node _t_rec_T_29 = bits(t_rec_rawIn_3.sExp, 5, 0) node _t_rec_T_30 = cat(_t_rec_T_28, _t_rec_T_29) node _t_rec_T_31 = bits(t_rec_rawIn_3.sig, 22, 0) node t_rec_3 = cat(_t_rec_T_30, _t_rec_T_31) node self_rec_rawIn_sign_3 = bits(in.bits.in[3].bits, 31, 31) node self_rec_rawIn_expIn_3 = bits(in.bits.in[3].bits, 30, 23) node self_rec_rawIn_fractIn_3 = bits(in.bits.in[3].bits, 22, 0) node self_rec_rawIn_isZeroExpIn_3 = eq(self_rec_rawIn_expIn_3, UInt<1>(0h0)) node self_rec_rawIn_isZeroFractIn_3 = eq(self_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _self_rec_rawIn_normDist_T_132 = bits(self_rec_rawIn_fractIn_3, 0, 0) node _self_rec_rawIn_normDist_T_133 = bits(self_rec_rawIn_fractIn_3, 1, 1) node _self_rec_rawIn_normDist_T_134 = bits(self_rec_rawIn_fractIn_3, 2, 2) node _self_rec_rawIn_normDist_T_135 = bits(self_rec_rawIn_fractIn_3, 3, 3) node _self_rec_rawIn_normDist_T_136 = bits(self_rec_rawIn_fractIn_3, 4, 4) node _self_rec_rawIn_normDist_T_137 = bits(self_rec_rawIn_fractIn_3, 5, 5) node _self_rec_rawIn_normDist_T_138 = bits(self_rec_rawIn_fractIn_3, 6, 6) node _self_rec_rawIn_normDist_T_139 = bits(self_rec_rawIn_fractIn_3, 7, 7) node _self_rec_rawIn_normDist_T_140 = bits(self_rec_rawIn_fractIn_3, 8, 8) node _self_rec_rawIn_normDist_T_141 = bits(self_rec_rawIn_fractIn_3, 9, 9) node _self_rec_rawIn_normDist_T_142 = bits(self_rec_rawIn_fractIn_3, 10, 10) node _self_rec_rawIn_normDist_T_143 = bits(self_rec_rawIn_fractIn_3, 11, 11) node _self_rec_rawIn_normDist_T_144 = bits(self_rec_rawIn_fractIn_3, 12, 12) node _self_rec_rawIn_normDist_T_145 = bits(self_rec_rawIn_fractIn_3, 13, 13) node _self_rec_rawIn_normDist_T_146 = bits(self_rec_rawIn_fractIn_3, 14, 14) node _self_rec_rawIn_normDist_T_147 = bits(self_rec_rawIn_fractIn_3, 15, 15) node _self_rec_rawIn_normDist_T_148 = bits(self_rec_rawIn_fractIn_3, 16, 16) node _self_rec_rawIn_normDist_T_149 = bits(self_rec_rawIn_fractIn_3, 17, 17) node _self_rec_rawIn_normDist_T_150 = bits(self_rec_rawIn_fractIn_3, 18, 18) node _self_rec_rawIn_normDist_T_151 = bits(self_rec_rawIn_fractIn_3, 19, 19) node _self_rec_rawIn_normDist_T_152 = bits(self_rec_rawIn_fractIn_3, 20, 20) node _self_rec_rawIn_normDist_T_153 = bits(self_rec_rawIn_fractIn_3, 21, 21) node _self_rec_rawIn_normDist_T_154 = bits(self_rec_rawIn_fractIn_3, 22, 22) node _self_rec_rawIn_normDist_T_155 = mux(_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _self_rec_rawIn_normDist_T_156 = mux(_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _self_rec_rawIn_normDist_T_155) node _self_rec_rawIn_normDist_T_157 = mux(_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _self_rec_rawIn_normDist_T_156) node _self_rec_rawIn_normDist_T_158 = mux(_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _self_rec_rawIn_normDist_T_157) node _self_rec_rawIn_normDist_T_159 = mux(_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _self_rec_rawIn_normDist_T_158) node _self_rec_rawIn_normDist_T_160 = mux(_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _self_rec_rawIn_normDist_T_159) node _self_rec_rawIn_normDist_T_161 = mux(_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _self_rec_rawIn_normDist_T_160) node _self_rec_rawIn_normDist_T_162 = mux(_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _self_rec_rawIn_normDist_T_161) node _self_rec_rawIn_normDist_T_163 = mux(_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _self_rec_rawIn_normDist_T_162) node _self_rec_rawIn_normDist_T_164 = mux(_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _self_rec_rawIn_normDist_T_163) node _self_rec_rawIn_normDist_T_165 = mux(_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _self_rec_rawIn_normDist_T_164) node _self_rec_rawIn_normDist_T_166 = mux(_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _self_rec_rawIn_normDist_T_165) node _self_rec_rawIn_normDist_T_167 = mux(_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _self_rec_rawIn_normDist_T_166) node _self_rec_rawIn_normDist_T_168 = mux(_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _self_rec_rawIn_normDist_T_167) node _self_rec_rawIn_normDist_T_169 = mux(_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _self_rec_rawIn_normDist_T_168) node _self_rec_rawIn_normDist_T_170 = mux(_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _self_rec_rawIn_normDist_T_169) node _self_rec_rawIn_normDist_T_171 = mux(_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _self_rec_rawIn_normDist_T_170) node _self_rec_rawIn_normDist_T_172 = mux(_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _self_rec_rawIn_normDist_T_171) node _self_rec_rawIn_normDist_T_173 = mux(_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _self_rec_rawIn_normDist_T_172) node _self_rec_rawIn_normDist_T_174 = mux(_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _self_rec_rawIn_normDist_T_173) node _self_rec_rawIn_normDist_T_175 = mux(_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _self_rec_rawIn_normDist_T_174) node self_rec_rawIn_normDist_3 = mux(_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _self_rec_rawIn_normDist_T_175) node _self_rec_rawIn_subnormFract_T_6 = dshl(self_rec_rawIn_fractIn_3, self_rec_rawIn_normDist_3) node _self_rec_rawIn_subnormFract_T_7 = bits(_self_rec_rawIn_subnormFract_T_6, 21, 0) node self_rec_rawIn_subnormFract_3 = shl(_self_rec_rawIn_subnormFract_T_7, 1) node _self_rec_rawIn_adjustedExp_T_15 = xor(self_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _self_rec_rawIn_adjustedExp_T_16 = mux(self_rec_rawIn_isZeroExpIn_3, _self_rec_rawIn_adjustedExp_T_15, self_rec_rawIn_expIn_3) node _self_rec_rawIn_adjustedExp_T_17 = mux(self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_17) node _self_rec_rawIn_adjustedExp_T_19 = add(_self_rec_rawIn_adjustedExp_T_16, _self_rec_rawIn_adjustedExp_T_18) node self_rec_rawIn_adjustedExp_3 = tail(_self_rec_rawIn_adjustedExp_T_19, 1) node self_rec_rawIn_isZero_3 = and(self_rec_rawIn_isZeroExpIn_3, self_rec_rawIn_isZeroFractIn_3) node _self_rec_rawIn_isSpecial_T_3 = bits(self_rec_rawIn_adjustedExp_3, 8, 7) node self_rec_rawIn_isSpecial_3 = eq(_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _self_rec_rawIn_out_isNaN_T_6 = eq(self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _self_rec_rawIn_out_isNaN_T_7 = and(self_rec_rawIn_isSpecial_3, _self_rec_rawIn_out_isNaN_T_6) connect self_rec_rawIn_3.isNaN, _self_rec_rawIn_out_isNaN_T_7 node _self_rec_rawIn_out_isInf_T_3 = and(self_rec_rawIn_isSpecial_3, self_rec_rawIn_isZeroFractIn_3) connect self_rec_rawIn_3.isInf, _self_rec_rawIn_out_isInf_T_3 connect self_rec_rawIn_3.isZero, self_rec_rawIn_isZero_3 connect self_rec_rawIn_3.sign, self_rec_rawIn_sign_3 node _self_rec_rawIn_out_sExp_T_6 = bits(self_rec_rawIn_adjustedExp_3, 8, 0) node _self_rec_rawIn_out_sExp_T_7 = cvt(_self_rec_rawIn_out_sExp_T_6) connect self_rec_rawIn_3.sExp, _self_rec_rawIn_out_sExp_T_7 node _self_rec_rawIn_out_sig_T_12 = eq(self_rec_rawIn_isZero_3, UInt<1>(0h0)) node _self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_12) node _self_rec_rawIn_out_sig_T_14 = mux(self_rec_rawIn_isZeroExpIn_3, self_rec_rawIn_subnormFract_3, self_rec_rawIn_fractIn_3) node _self_rec_rawIn_out_sig_T_15 = cat(_self_rec_rawIn_out_sig_T_13, _self_rec_rawIn_out_sig_T_14) connect self_rec_rawIn_3.sig, _self_rec_rawIn_out_sig_T_15 node _self_rec_T_24 = bits(self_rec_rawIn_3.sExp, 8, 6) node _self_rec_T_25 = mux(self_rec_rawIn_3.isZero, UInt<3>(0h0), _self_rec_T_24) node _self_rec_T_26 = mux(self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _self_rec_T_27 = or(_self_rec_T_25, _self_rec_T_26) node _self_rec_T_28 = cat(self_rec_rawIn_3.sign, _self_rec_T_27) node _self_rec_T_29 = bits(self_rec_rawIn_3.sExp, 5, 0) node _self_rec_T_30 = cat(_self_rec_T_28, _self_rec_T_29) node _self_rec_T_31 = bits(self_rec_rawIn_3.sig, 22, 0) node self_rec_3 = cat(_self_rec_T_30, _self_rec_T_31) inst t_resizer_3 of RecFNToRecFN_11 connect t_resizer_3.io.in, t_rec_3 connect t_resizer_3.io.roundingMode, UInt<3>(0h0) connect t_resizer_3.io.detectTininess, UInt<1>(0h1) inst muladder_3 of MulRecFN_7 connect muladder_3.io.roundingMode, UInt<3>(0h0) connect muladder_3.io.detectTininess, UInt<1>(0h1) connect muladder_3.io.a, self_rec_3 connect muladder_3.io.b, t_resizer_3.io.out wire out_3 : { bits : UInt<32>} node out_bits_rawIn_exp_3 = bits(muladder_3.io.out, 31, 23) node _out_bits_rawIn_isZero_T_3 = bits(out_bits_rawIn_exp_3, 8, 6) node out_bits_rawIn_isZero_3 = eq(_out_bits_rawIn_isZero_T_3, UInt<1>(0h0)) node _out_bits_rawIn_isSpecial_T_3 = bits(out_bits_rawIn_exp_3, 8, 7) node out_bits_rawIn_isSpecial_3 = eq(_out_bits_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire out_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_rawIn_out_isNaN_T_6 = bits(out_bits_rawIn_exp_3, 6, 6) node _out_bits_rawIn_out_isNaN_T_7 = and(out_bits_rawIn_isSpecial_3, _out_bits_rawIn_out_isNaN_T_6) connect out_bits_rawIn_3.isNaN, _out_bits_rawIn_out_isNaN_T_7 node _out_bits_rawIn_out_isInf_T_9 = bits(out_bits_rawIn_exp_3, 6, 6) node _out_bits_rawIn_out_isInf_T_10 = eq(_out_bits_rawIn_out_isInf_T_9, UInt<1>(0h0)) node _out_bits_rawIn_out_isInf_T_11 = and(out_bits_rawIn_isSpecial_3, _out_bits_rawIn_out_isInf_T_10) connect out_bits_rawIn_3.isInf, _out_bits_rawIn_out_isInf_T_11 connect out_bits_rawIn_3.isZero, out_bits_rawIn_isZero_3 node _out_bits_rawIn_out_sign_T_3 = bits(muladder_3.io.out, 32, 32) connect out_bits_rawIn_3.sign, _out_bits_rawIn_out_sign_T_3 node _out_bits_rawIn_out_sExp_T_3 = cvt(out_bits_rawIn_exp_3) connect out_bits_rawIn_3.sExp, _out_bits_rawIn_out_sExp_T_3 node _out_bits_rawIn_out_sig_T_12 = eq(out_bits_rawIn_isZero_3, UInt<1>(0h0)) node _out_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _out_bits_rawIn_out_sig_T_12) node _out_bits_rawIn_out_sig_T_14 = bits(muladder_3.io.out, 22, 0) node _out_bits_rawIn_out_sig_T_15 = cat(_out_bits_rawIn_out_sig_T_13, _out_bits_rawIn_out_sig_T_14) connect out_bits_rawIn_3.sig, _out_bits_rawIn_out_sig_T_15 node out_bits_isSubnormal_3 = lt(out_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82))) node _out_bits_denormShiftDist_T_6 = bits(out_bits_rawIn_3.sExp, 4, 0) node _out_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _out_bits_denormShiftDist_T_6) node out_bits_denormShiftDist_3 = tail(_out_bits_denormShiftDist_T_7, 1) node _out_bits_denormFract_T_6 = shr(out_bits_rawIn_3.sig, 1) node _out_bits_denormFract_T_7 = dshr(_out_bits_denormFract_T_6, out_bits_denormShiftDist_3) node out_bits_denormFract_3 = bits(_out_bits_denormFract_T_7, 22, 0) node _out_bits_expOut_T_18 = bits(out_bits_rawIn_3.sExp, 7, 0) node _out_bits_expOut_T_19 = sub(_out_bits_expOut_T_18, UInt<8>(0h81)) node _out_bits_expOut_T_20 = tail(_out_bits_expOut_T_19, 1) node _out_bits_expOut_T_21 = mux(out_bits_isSubnormal_3, UInt<1>(0h0), _out_bits_expOut_T_20) node _out_bits_expOut_T_22 = or(out_bits_rawIn_3.isNaN, out_bits_rawIn_3.isInf) node _out_bits_expOut_T_23 = mux(_out_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0)) node out_bits_expOut_3 = or(_out_bits_expOut_T_21, _out_bits_expOut_T_23) node _out_bits_fractOut_T_6 = bits(out_bits_rawIn_3.sig, 22, 0) node _out_bits_fractOut_T_7 = mux(out_bits_rawIn_3.isInf, UInt<1>(0h0), _out_bits_fractOut_T_6) node out_bits_fractOut_3 = mux(out_bits_isSubnormal_3, out_bits_denormFract_3, _out_bits_fractOut_T_7) node out_bits_hi_3 = cat(out_bits_rawIn_3.sign, out_bits_expOut_3) node _out_bits_T_3 = cat(out_bits_hi_3, out_bits_fractOut_3) connect out_3.bits, _out_bits_T_3 connect pipe.io.in.bits.out[0].bits, out.bits connect pipe.io.in.bits.out[1].bits, out_1.bits connect pipe.io.in.bits.out[2].bits, out_2.bits connect pipe.io.in.bits.out[3].bits, out_3.bits

module VectorScalarMultiplier_1( // @[VectorScalarMultiplier.scala:45:7] input clock, // @[VectorScalarMultiplier.scala:45:7] input reset, // @[VectorScalarMultiplier.scala:45:7] output io_req_ready, // @[VectorScalarMultiplier.scala:54:14] input io_req_valid, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_0_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_1_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_2_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_in_3_bits, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_scale_bits, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_repeats, // @[VectorScalarMultiplier.scala:54:14] input [7:0] io_req_bits_pixel_repeats, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_last, // @[VectorScalarMultiplier.scala:54:14] input [127:0] io_req_bits_tag_data, // @[VectorScalarMultiplier.scala:54:14] input [13:0] io_req_bits_tag_addr, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_0, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_1, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_2, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_3, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_4, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_5, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_6, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_7, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_8, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_9, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_10, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_11, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_12, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_13, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_14, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_mask_15, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_is_acc, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_accumulate, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_has_acc_bitwidth, // @[VectorScalarMultiplier.scala:54:14] input [31:0] io_req_bits_tag_scale, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_tag_repeats, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_tag_pixel_repeats, // @[VectorScalarMultiplier.scala:54:14] input [15:0] io_req_bits_tag_len, // @[VectorScalarMultiplier.scala:54:14] input io_req_bits_tag_last, // @[VectorScalarMultiplier.scala:54:14] input [7:0] io_req_bits_tag_bytes_read, // @[VectorScalarMultiplier.scala:54:14] input [7:0] io_req_bits_tag_cmd_id, // @[VectorScalarMultiplier.scala:54:14] input io_resp_ready, // @[VectorScalarMultiplier.scala:54:14] output io_resp_valid, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_0_bits, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_1_bits, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_2_bits, // @[VectorScalarMultiplier.scala:54:14] output [31:0] io_resp_bits_out_3_bits, // @[VectorScalarMultiplier.scala:54:14] output [15:0] io_resp_bits_row, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_last, // @[VectorScalarMultiplier.scala:54:14] output [13:0] io_resp_bits_tag_addr, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_0, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_1, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_2, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_3, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_4, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_5, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_6, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_7, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_8, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_9, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_10, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_11, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_12, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_13, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_14, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_mask_15, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_is_acc, // @[VectorScalarMultiplier.scala:54:14] output io_resp_bits_tag_accumulate, // @[VectorScalarMultiplier.scala:54:14] output [7:0] io_resp_bits_tag_bytes_read, // @[VectorScalarMultiplier.scala:54:14] output [7:0] io_resp_bits_tag_cmd_id // @[VectorScalarMultiplier.scala:54:14] ); wire self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _muladder_3_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_3_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _muladder_2_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_2_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _muladder_1_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_1_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _muladder_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _t_resizer_io_out; // @[Arithmetic.scala:336:32] wire _pipe_io_in_ready; // @[VectorScalarMultiplier.scala:83:22] wire io_req_valid_0 = io_req_valid; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_0_bits_0 = io_req_bits_in_0_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_1_bits_0 = io_req_bits_in_1_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_2_bits_0 = io_req_bits_in_2_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_in_3_bits_0 = io_req_bits_in_3_bits; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_scale_bits_0 = io_req_bits_scale_bits; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_last_0 = io_req_bits_last; // @[VectorScalarMultiplier.scala:45:7] wire [127:0] io_req_bits_tag_data_0 = io_req_bits_tag_data; // @[VectorScalarMultiplier.scala:45:7] wire [13:0] io_req_bits_tag_addr_0 = io_req_bits_tag_addr; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_0_0 = io_req_bits_tag_mask_0; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_1_0 = io_req_bits_tag_mask_1; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_2_0 = io_req_bits_tag_mask_2; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_3_0 = io_req_bits_tag_mask_3; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_4_0 = io_req_bits_tag_mask_4; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_5_0 = io_req_bits_tag_mask_5; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_6_0 = io_req_bits_tag_mask_6; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_7_0 = io_req_bits_tag_mask_7; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_8_0 = io_req_bits_tag_mask_8; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_9_0 = io_req_bits_tag_mask_9; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_10_0 = io_req_bits_tag_mask_10; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_11_0 = io_req_bits_tag_mask_11; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_12_0 = io_req_bits_tag_mask_12; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_13_0 = io_req_bits_tag_mask_13; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_14_0 = io_req_bits_tag_mask_14; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_mask_15_0 = io_req_bits_tag_mask_15; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_is_acc_0 = io_req_bits_tag_is_acc; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_accumulate_0 = io_req_bits_tag_accumulate; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_has_acc_bitwidth_0 = io_req_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_req_bits_tag_scale_0 = io_req_bits_tag_scale; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_tag_repeats_0 = io_req_bits_tag_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_tag_pixel_repeats_0 = io_req_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_req_bits_tag_len_0 = io_req_bits_tag_len; // @[VectorScalarMultiplier.scala:45:7] wire io_req_bits_tag_last_0 = io_req_bits_tag_last; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_req_bits_tag_bytes_read_0 = io_req_bits_tag_bytes_read; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_req_bits_tag_cmd_id_0 = io_req_bits_tag_cmd_id; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_ready_0 = io_resp_ready; // @[VectorScalarMultiplier.scala:45:7] wire _io_req_ready_T_3; // @[VectorScalarMultiplier.scala:67:29] wire io_req_ready_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_0_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_1_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_2_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_out_3_bits_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7] wire [127:0] io_resp_bits_tag_data; // @[VectorScalarMultiplier.scala:45:7] wire [13:0] io_resp_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:45:7] wire [31:0] io_resp_bits_tag_scale; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_tag_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_tag_len; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_tag_last; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_resp_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7] wire [7:0] io_resp_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7] wire [15:0] io_resp_bits_row_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_bits_last_0; // @[VectorScalarMultiplier.scala:45:7] wire io_resp_valid_0; // @[VectorScalarMultiplier.scala:45:7] reg in_valid; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_0_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_1_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_2_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_in_3_bits; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_scale_bits; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_repeats; // @[VectorScalarMultiplier.scala:65:15] reg [7:0] in_bits_pixel_repeats; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_last; // @[VectorScalarMultiplier.scala:65:15] reg [127:0] in_bits_tag_data; // @[VectorScalarMultiplier.scala:65:15] reg [13:0] in_bits_tag_addr; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_0; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_1; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_2; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_3; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_4; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_5; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_6; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_7; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_8; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_9; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_10; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_11; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_12; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_13; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_14; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_mask_15; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_is_acc; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_accumulate; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:65:15] reg [31:0] in_bits_tag_scale; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_tag_repeats; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:65:15] reg [15:0] in_bits_tag_len; // @[VectorScalarMultiplier.scala:65:15] reg in_bits_tag_last; // @[VectorScalarMultiplier.scala:65:15] reg [7:0] in_bits_tag_bytes_read; // @[VectorScalarMultiplier.scala:65:15] reg [7:0] in_bits_tag_cmd_id; // @[VectorScalarMultiplier.scala:65:15] wire _in_fire_T; // @[Decoupled.scala:51:35] wire in_fire; // @[VectorScalarMultiplier.scala:66:25] wire _io_req_ready_T = ~in_valid; // @[VectorScalarMultiplier.scala:65:15, :67:19] wire _T_1 = in_bits_repeats == 16'h0; // @[VectorScalarMultiplier.scala:65:15, :67:49] wire _io_req_ready_T_1; // @[VectorScalarMultiplier.scala:67:49] assign _io_req_ready_T_1 = _T_1; // @[VectorScalarMultiplier.scala:67:49] wire _pipe_io_in_bits_last_T; // @[VectorScalarMultiplier.scala:92:45] assign _pipe_io_in_bits_last_T = _T_1; // @[VectorScalarMultiplier.scala:67:49, :92:45] wire _io_req_ready_T_2 = _io_req_ready_T_1 & in_fire; // @[VectorScalarMultiplier.scala:66:25, :67:{49,57}] assign _io_req_ready_T_3 = _io_req_ready_T | _io_req_ready_T_2; // @[VectorScalarMultiplier.scala:67:{19,29,57}] assign io_req_ready_0 = _io_req_ready_T_3; // @[VectorScalarMultiplier.scala:45:7, :67:29] wire [16:0] _in_bits_repeats_T = {1'h0, in_bits_repeats} - 17'h1; // @[VectorScalarMultiplier.scala:65:15, :76:40] wire [15:0] _in_bits_repeats_T_1 = _in_bits_repeats_T[15:0]; // @[VectorScalarMultiplier.scala:76:40] assign _in_fire_T = _pipe_io_in_ready & in_valid; // @[Decoupled.scala:51:35] assign in_fire = _in_fire_T; // @[Decoupled.scala:51:35] wire _pipe_io_in_bits_last_T_1 = _pipe_io_in_bits_last_T & in_bits_last; // @[VectorScalarMultiplier.scala:65:15, :92:{45,53}] wire t_rec_rawIn_sign = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_1 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_2 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_3 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18] wire t_rec_rawIn_sign_0 = t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] t_rec_rawIn_expIn = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] t_rec_rawIn_expIn_1 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] t_rec_rawIn_expIn_2 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] t_rec_rawIn_expIn_3 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] t_rec_rawIn_fractIn = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] t_rec_rawIn_fractIn_1 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] t_rec_rawIn_fractIn_2 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] t_rec_rawIn_fractIn_3 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire t_rec_rawIn_isZeroExpIn = t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn = t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T = t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_1 = t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_2 = t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_3 = t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_4 = t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_5 = t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_6 = t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_7 = t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_8 = t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_9 = t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_10 = t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_11 = t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_12 = t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_13 = t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_14 = t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_15 = t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_16 = t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_17 = t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_18 = t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_19 = t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_20 = t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_21 = t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_22 = t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_23 = _t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_24 = _t_rec_rawIn_normDist_T_2 ? 5'h14 : _t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_25 = _t_rec_rawIn_normDist_T_3 ? 5'h13 : _t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_26 = _t_rec_rawIn_normDist_T_4 ? 5'h12 : _t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_27 = _t_rec_rawIn_normDist_T_5 ? 5'h11 : _t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_28 = _t_rec_rawIn_normDist_T_6 ? 5'h10 : _t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_29 = _t_rec_rawIn_normDist_T_7 ? 5'hF : _t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_30 = _t_rec_rawIn_normDist_T_8 ? 5'hE : _t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_31 = _t_rec_rawIn_normDist_T_9 ? 5'hD : _t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_32 = _t_rec_rawIn_normDist_T_10 ? 5'hC : _t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_33 = _t_rec_rawIn_normDist_T_11 ? 5'hB : _t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_34 = _t_rec_rawIn_normDist_T_12 ? 5'hA : _t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_35 = _t_rec_rawIn_normDist_T_13 ? 5'h9 : _t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_36 = _t_rec_rawIn_normDist_T_14 ? 5'h8 : _t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_37 = _t_rec_rawIn_normDist_T_15 ? 5'h7 : _t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_38 = _t_rec_rawIn_normDist_T_16 ? 5'h6 : _t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_39 = _t_rec_rawIn_normDist_T_17 ? 5'h5 : _t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_40 = _t_rec_rawIn_normDist_T_18 ? 5'h4 : _t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_41 = _t_rec_rawIn_normDist_T_19 ? 5'h3 : _t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_42 = _t_rec_rawIn_normDist_T_20 ? 5'h2 : _t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_43 = _t_rec_rawIn_normDist_T_21 ? 5'h1 : _t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist = _t_rec_rawIn_normDist_T_22 ? 5'h0 : _t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T = {31'h0, t_rec_rawIn_fractIn} << t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_1 = _t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract = {_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T = {4'hF, ~t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_1 = t_rec_rawIn_isZeroExpIn ? _t_rec_rawIn_adjustedExp_T : {1'h0, t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_2 = t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_3 = {6'h20, _t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_4 = {1'h0, _t_rec_rawIn_adjustedExp_T_1} + {2'h0, _t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp = _t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T = t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero = t_rec_rawIn_isZeroExpIn & t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_isZero_0 = t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T = t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial = &_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_2 = t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T = ~t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_1 = t_rec_rawIn_isSpecial & _t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_isNaN = _t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T = t_rec_rawIn_isSpecial & t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_isInf = _t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_1 = {1'h0, _t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_sExp = _t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T = ~t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_1 = {1'h0, _t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_2 = t_rec_rawIn_isZeroExpIn ? t_rec_rawIn_subnormFract : t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_3 = {_t_rec_rawIn_out_sig_T_1, _t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_sig = _t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T = t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_1 = t_rec_rawIn_isZero_0 ? 3'h0 : _t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_3 = {_t_rec_T_1[2:1], _t_rec_T_1[0] | _t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_4 = {t_rec_rawIn_sign_0, _t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_5 = t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_6 = {_t_rec_T_4, _t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_7 = t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec = {_t_rec_T_6, _t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign = in_bits_in_0_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_sign_0 = self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn = in_bits_in_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn = in_bits_in_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn = self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn = self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T = self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_1 = self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_2 = self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_3 = self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_4 = self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_5 = self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_6 = self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_7 = self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_8 = self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_9 = self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_10 = self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_11 = self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_12 = self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_13 = self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_14 = self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_15 = self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_16 = self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_17 = self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_18 = self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_19 = self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_20 = self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_21 = self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_22 = self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_23 = _self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_24 = _self_rec_rawIn_normDist_T_2 ? 5'h14 : _self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_25 = _self_rec_rawIn_normDist_T_3 ? 5'h13 : _self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_26 = _self_rec_rawIn_normDist_T_4 ? 5'h12 : _self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_27 = _self_rec_rawIn_normDist_T_5 ? 5'h11 : _self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_28 = _self_rec_rawIn_normDist_T_6 ? 5'h10 : _self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_29 = _self_rec_rawIn_normDist_T_7 ? 5'hF : _self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_30 = _self_rec_rawIn_normDist_T_8 ? 5'hE : _self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_31 = _self_rec_rawIn_normDist_T_9 ? 5'hD : _self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_32 = _self_rec_rawIn_normDist_T_10 ? 5'hC : _self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_33 = _self_rec_rawIn_normDist_T_11 ? 5'hB : _self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_34 = _self_rec_rawIn_normDist_T_12 ? 5'hA : _self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_35 = _self_rec_rawIn_normDist_T_13 ? 5'h9 : _self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_36 = _self_rec_rawIn_normDist_T_14 ? 5'h8 : _self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_37 = _self_rec_rawIn_normDist_T_15 ? 5'h7 : _self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_38 = _self_rec_rawIn_normDist_T_16 ? 5'h6 : _self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_39 = _self_rec_rawIn_normDist_T_17 ? 5'h5 : _self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_40 = _self_rec_rawIn_normDist_T_18 ? 5'h4 : _self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_41 = _self_rec_rawIn_normDist_T_19 ? 5'h3 : _self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_42 = _self_rec_rawIn_normDist_T_20 ? 5'h2 : _self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_43 = _self_rec_rawIn_normDist_T_21 ? 5'h1 : _self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist = _self_rec_rawIn_normDist_T_22 ? 5'h0 : _self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T = {31'h0, self_rec_rawIn_fractIn} << self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_1 = _self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract = {_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T = {4'hF, ~self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_1 = self_rec_rawIn_isZeroExpIn ? _self_rec_rawIn_adjustedExp_T : {1'h0, self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_2 = self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_3 = {6'h20, _self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_4 = {1'h0, _self_rec_rawIn_adjustedExp_T_1} + {2'h0, _self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp = _self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T = self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero = self_rec_rawIn_isZeroExpIn & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_isZero_0 = self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T = self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial = &_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_2 = self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T = ~self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_1 = self_rec_rawIn_isSpecial & _self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_isNaN = _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T = self_rec_rawIn_isSpecial & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_isInf = _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_1 = {1'h0, _self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_sExp = _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T = ~self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_1 = {1'h0, _self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_2 = self_rec_rawIn_isZeroExpIn ? self_rec_rawIn_subnormFract : self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_3 = {_self_rec_rawIn_out_sig_T_1, _self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_sig = _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T = self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_1 = self_rec_rawIn_isZero_0 ? 3'h0 : _self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_3 = {_self_rec_T_1[2:1], _self_rec_T_1[0] | _self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_4 = {self_rec_rawIn_sign_0, _self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_5 = self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_6 = {_self_rec_T_4, _self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_7 = self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec = {_self_rec_T_6, _self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] out_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp = _muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T = out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero = _out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_isZero_0 = out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T = out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial = &_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T = out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T = out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_1 = out_bits_rawIn_isSpecial & _out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_isNaN = _out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_1 = ~_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_2 = out_bits_rawIn_isSpecial & _out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_isInf = _out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T = _muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_sign = _out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T = {1'h0, out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_sExp = _out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T = ~out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_1 = {1'h0, _out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_2 = _muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_3 = {_out_bits_rawIn_out_sig_T_1, _out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_sig = _out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal = $signed(out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T = out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist = _out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T = out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_1 = _out_bits_denormFract_T >> out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract = _out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T = out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_1 = {1'h0, _out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_2 = _out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_3 = out_bits_isSubnormal ? 8'h0 : _out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_4 = out_bits_rawIn_isNaN | out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_5 = {8{_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut = _out_bits_expOut_T_3 | _out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T = out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_1 = out_bits_rawIn_isInf ? 23'h0 : _out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut = out_bits_isSubnormal ? out_bits_denormFract : _out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi = {out_bits_rawIn_sign, out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T = {out_bits_hi, out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_bits = _out_bits_T; // @[fNFromRecFN.scala:66:12] wire t_rec_rawIn_1_sign = t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire t_rec_rawIn_isZeroExpIn_1 = t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn_1 = t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T_44 = t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_45 = t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_46 = t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_47 = t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_48 = t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_49 = t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_50 = t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_51 = t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_52 = t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_53 = t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_54 = t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_55 = t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_56 = t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_57 = t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_58 = t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_59 = t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_60 = t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_61 = t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_62 = t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_63 = t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_64 = t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_65 = t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_66 = t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_67 = _t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_68 = _t_rec_rawIn_normDist_T_46 ? 5'h14 : _t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_69 = _t_rec_rawIn_normDist_T_47 ? 5'h13 : _t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_70 = _t_rec_rawIn_normDist_T_48 ? 5'h12 : _t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_71 = _t_rec_rawIn_normDist_T_49 ? 5'h11 : _t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_72 = _t_rec_rawIn_normDist_T_50 ? 5'h10 : _t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_73 = _t_rec_rawIn_normDist_T_51 ? 5'hF : _t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_74 = _t_rec_rawIn_normDist_T_52 ? 5'hE : _t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_75 = _t_rec_rawIn_normDist_T_53 ? 5'hD : _t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_76 = _t_rec_rawIn_normDist_T_54 ? 5'hC : _t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_77 = _t_rec_rawIn_normDist_T_55 ? 5'hB : _t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_78 = _t_rec_rawIn_normDist_T_56 ? 5'hA : _t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_79 = _t_rec_rawIn_normDist_T_57 ? 5'h9 : _t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_80 = _t_rec_rawIn_normDist_T_58 ? 5'h8 : _t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_81 = _t_rec_rawIn_normDist_T_59 ? 5'h7 : _t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_82 = _t_rec_rawIn_normDist_T_60 ? 5'h6 : _t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_83 = _t_rec_rawIn_normDist_T_61 ? 5'h5 : _t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_84 = _t_rec_rawIn_normDist_T_62 ? 5'h4 : _t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_85 = _t_rec_rawIn_normDist_T_63 ? 5'h3 : _t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_86 = _t_rec_rawIn_normDist_T_64 ? 5'h2 : _t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_87 = _t_rec_rawIn_normDist_T_65 ? 5'h1 : _t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist_1 = _t_rec_rawIn_normDist_T_66 ? 5'h0 : _t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T_2 = {31'h0, t_rec_rawIn_fractIn_1} << t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_3 = _t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract_1 = {_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_6 = t_rec_rawIn_isZeroExpIn_1 ? _t_rec_rawIn_adjustedExp_T_5 : {1'h0, t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_7 = t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_8 = {6'h20, _t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_9 = {1'h0, _t_rec_rawIn_adjustedExp_T_6} + {2'h0, _t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp_1 = _t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T_2 = t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero_1 = t_rec_rawIn_isZeroExpIn_1 & t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_1_isZero = t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T_1 = t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial_1 = &_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_10 = t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T_2 = ~t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_3 = t_rec_rawIn_isSpecial_1 & _t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_1_isNaN = _t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T_1 = t_rec_rawIn_isSpecial_1 & t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_1_isInf = _t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_3 = {1'h0, _t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_1_sExp = _t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T_4 = ~t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_5 = {1'h0, _t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_6 = t_rec_rawIn_isZeroExpIn_1 ? t_rec_rawIn_subnormFract_1 : t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_7 = {_t_rec_rawIn_out_sig_T_5, _t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_1_sig = _t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T_8 = t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_9 = t_rec_rawIn_1_isZero ? 3'h0 : _t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_11 = {_t_rec_T_9[2:1], _t_rec_T_9[0] | _t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_12 = {t_rec_rawIn_1_sign, _t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_13 = t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_14 = {_t_rec_T_12, _t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_15 = t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec_1 = {_t_rec_T_14, _t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign_1 = in_bits_in_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_1_sign = self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn_1 = in_bits_in_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn_1 = in_bits_in_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn_1 = self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn_1 = self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T_44 = self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_45 = self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_46 = self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_47 = self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_48 = self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_49 = self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_50 = self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_51 = self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_52 = self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_53 = self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_54 = self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_55 = self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_56 = self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_57 = self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_58 = self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_59 = self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_60 = self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_61 = self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_62 = self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_63 = self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_64 = self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_65 = self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_66 = self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_67 = _self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_68 = _self_rec_rawIn_normDist_T_46 ? 5'h14 : _self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_69 = _self_rec_rawIn_normDist_T_47 ? 5'h13 : _self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_70 = _self_rec_rawIn_normDist_T_48 ? 5'h12 : _self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_71 = _self_rec_rawIn_normDist_T_49 ? 5'h11 : _self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_72 = _self_rec_rawIn_normDist_T_50 ? 5'h10 : _self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_73 = _self_rec_rawIn_normDist_T_51 ? 5'hF : _self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_74 = _self_rec_rawIn_normDist_T_52 ? 5'hE : _self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_75 = _self_rec_rawIn_normDist_T_53 ? 5'hD : _self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_76 = _self_rec_rawIn_normDist_T_54 ? 5'hC : _self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_77 = _self_rec_rawIn_normDist_T_55 ? 5'hB : _self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_78 = _self_rec_rawIn_normDist_T_56 ? 5'hA : _self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_79 = _self_rec_rawIn_normDist_T_57 ? 5'h9 : _self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_80 = _self_rec_rawIn_normDist_T_58 ? 5'h8 : _self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_81 = _self_rec_rawIn_normDist_T_59 ? 5'h7 : _self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_82 = _self_rec_rawIn_normDist_T_60 ? 5'h6 : _self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_83 = _self_rec_rawIn_normDist_T_61 ? 5'h5 : _self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_84 = _self_rec_rawIn_normDist_T_62 ? 5'h4 : _self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_85 = _self_rec_rawIn_normDist_T_63 ? 5'h3 : _self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_86 = _self_rec_rawIn_normDist_T_64 ? 5'h2 : _self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_87 = _self_rec_rawIn_normDist_T_65 ? 5'h1 : _self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist_1 = _self_rec_rawIn_normDist_T_66 ? 5'h0 : _self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T_2 = {31'h0, self_rec_rawIn_fractIn_1} << self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_3 = _self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract_1 = {_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_6 = self_rec_rawIn_isZeroExpIn_1 ? _self_rec_rawIn_adjustedExp_T_5 : {1'h0, self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_7 = self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_8 = {6'h20, _self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_9 = {1'h0, _self_rec_rawIn_adjustedExp_T_6} + {2'h0, _self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp_1 = _self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T_2 = self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero_1 = self_rec_rawIn_isZeroExpIn_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_1_isZero = self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T_1 = self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial_1 = &_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_10 = self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T_2 = ~self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_3 = self_rec_rawIn_isSpecial_1 & _self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_1_isNaN = _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T_1 = self_rec_rawIn_isSpecial_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_1_isInf = _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_3 = {1'h0, _self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_1_sExp = _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T_4 = ~self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_5 = {1'h0, _self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_6 = self_rec_rawIn_isZeroExpIn_1 ? self_rec_rawIn_subnormFract_1 : self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_7 = {_self_rec_rawIn_out_sig_T_5, _self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_1_sig = _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T_8 = self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_9 = self_rec_rawIn_1_isZero ? 3'h0 : _self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_11 = {_self_rec_T_9[2:1], _self_rec_T_9[0] | _self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_12 = {self_rec_rawIn_1_sign, _self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_13 = self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_14 = {_self_rec_T_12, _self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_15 = self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec_1 = {_self_rec_T_14, _self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] out_1_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp_1 = _muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T_1 = out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero_1 = _out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_1_isZero = out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T_1 = out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial_1 = &_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T_2 = out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T_3 = out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_3 = out_bits_rawIn_isSpecial_1 & _out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_1_isNaN = _out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_4 = ~_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_5 = out_bits_rawIn_isSpecial_1 & _out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_1_isInf = _out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T_1 = _muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_1_sign = _out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T_1 = {1'h0, out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_1_sExp = _out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T_4 = ~out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_5 = {1'h0, _out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_6 = _muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_7 = {_out_bits_rawIn_out_sig_T_5, _out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_1_sig = _out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal_1 = $signed(out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T_2 = out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist_1 = _out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T_2 = out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_3 = _out_bits_denormFract_T_2 >> out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract_1 = _out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T_6 = out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_7 = {1'h0, _out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_8 = _out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_9 = out_bits_isSubnormal_1 ? 8'h0 : _out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_10 = out_bits_rawIn_1_isNaN | out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_11 = {8{_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut_1 = _out_bits_expOut_T_9 | _out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T_2 = out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_3 = out_bits_rawIn_1_isInf ? 23'h0 : _out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut_1 = out_bits_isSubnormal_1 ? out_bits_denormFract_1 : _out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi_1 = {out_bits_rawIn_1_sign, out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T_1 = {out_bits_hi_1, out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_1_bits = _out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire t_rec_rawIn_2_sign = t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire t_rec_rawIn_isZeroExpIn_2 = t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn_2 = t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T_88 = t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_89 = t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_90 = t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_91 = t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_92 = t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_93 = t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_94 = t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_95 = t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_96 = t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_97 = t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_98 = t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_99 = t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_100 = t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_101 = t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_102 = t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_103 = t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_104 = t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_105 = t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_106 = t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_107 = t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_108 = t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_109 = t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_110 = t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_111 = _t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_112 = _t_rec_rawIn_normDist_T_90 ? 5'h14 : _t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_113 = _t_rec_rawIn_normDist_T_91 ? 5'h13 : _t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_114 = _t_rec_rawIn_normDist_T_92 ? 5'h12 : _t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_115 = _t_rec_rawIn_normDist_T_93 ? 5'h11 : _t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_116 = _t_rec_rawIn_normDist_T_94 ? 5'h10 : _t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_117 = _t_rec_rawIn_normDist_T_95 ? 5'hF : _t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_118 = _t_rec_rawIn_normDist_T_96 ? 5'hE : _t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_119 = _t_rec_rawIn_normDist_T_97 ? 5'hD : _t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_120 = _t_rec_rawIn_normDist_T_98 ? 5'hC : _t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_121 = _t_rec_rawIn_normDist_T_99 ? 5'hB : _t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_122 = _t_rec_rawIn_normDist_T_100 ? 5'hA : _t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_123 = _t_rec_rawIn_normDist_T_101 ? 5'h9 : _t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_124 = _t_rec_rawIn_normDist_T_102 ? 5'h8 : _t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_125 = _t_rec_rawIn_normDist_T_103 ? 5'h7 : _t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_126 = _t_rec_rawIn_normDist_T_104 ? 5'h6 : _t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_127 = _t_rec_rawIn_normDist_T_105 ? 5'h5 : _t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_128 = _t_rec_rawIn_normDist_T_106 ? 5'h4 : _t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_129 = _t_rec_rawIn_normDist_T_107 ? 5'h3 : _t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_130 = _t_rec_rawIn_normDist_T_108 ? 5'h2 : _t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_131 = _t_rec_rawIn_normDist_T_109 ? 5'h1 : _t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist_2 = _t_rec_rawIn_normDist_T_110 ? 5'h0 : _t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T_4 = {31'h0, t_rec_rawIn_fractIn_2} << t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_5 = _t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract_2 = {_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_11 = t_rec_rawIn_isZeroExpIn_2 ? _t_rec_rawIn_adjustedExp_T_10 : {1'h0, t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_12 = t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_13 = {6'h20, _t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_14 = {1'h0, _t_rec_rawIn_adjustedExp_T_11} + {2'h0, _t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp_2 = _t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T_4 = t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero_2 = t_rec_rawIn_isZeroExpIn_2 & t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_2_isZero = t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T_2 = t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial_2 = &_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_18 = t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T_4 = ~t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_5 = t_rec_rawIn_isSpecial_2 & _t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_2_isNaN = _t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T_2 = t_rec_rawIn_isSpecial_2 & t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_2_isInf = _t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_5 = {1'h0, _t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_2_sExp = _t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T_8 = ~t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_9 = {1'h0, _t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_10 = t_rec_rawIn_isZeroExpIn_2 ? t_rec_rawIn_subnormFract_2 : t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_11 = {_t_rec_rawIn_out_sig_T_9, _t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_2_sig = _t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T_16 = t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_17 = t_rec_rawIn_2_isZero ? 3'h0 : _t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_19 = {_t_rec_T_17[2:1], _t_rec_T_17[0] | _t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_20 = {t_rec_rawIn_2_sign, _t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_21 = t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_22 = {_t_rec_T_20, _t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_23 = t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec_2 = {_t_rec_T_22, _t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign_2 = in_bits_in_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_2_sign = self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn_2 = in_bits_in_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn_2 = in_bits_in_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn_2 = self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn_2 = self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T_88 = self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_89 = self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_90 = self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_91 = self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_92 = self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_93 = self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_94 = self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_95 = self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_96 = self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_97 = self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_98 = self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_99 = self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_100 = self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_101 = self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_102 = self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_103 = self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_104 = self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_105 = self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_106 = self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_107 = self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_108 = self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_109 = self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_110 = self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_111 = _self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_112 = _self_rec_rawIn_normDist_T_90 ? 5'h14 : _self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_113 = _self_rec_rawIn_normDist_T_91 ? 5'h13 : _self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_114 = _self_rec_rawIn_normDist_T_92 ? 5'h12 : _self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_115 = _self_rec_rawIn_normDist_T_93 ? 5'h11 : _self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_116 = _self_rec_rawIn_normDist_T_94 ? 5'h10 : _self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_117 = _self_rec_rawIn_normDist_T_95 ? 5'hF : _self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_118 = _self_rec_rawIn_normDist_T_96 ? 5'hE : _self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_119 = _self_rec_rawIn_normDist_T_97 ? 5'hD : _self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_120 = _self_rec_rawIn_normDist_T_98 ? 5'hC : _self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_121 = _self_rec_rawIn_normDist_T_99 ? 5'hB : _self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_122 = _self_rec_rawIn_normDist_T_100 ? 5'hA : _self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_123 = _self_rec_rawIn_normDist_T_101 ? 5'h9 : _self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_124 = _self_rec_rawIn_normDist_T_102 ? 5'h8 : _self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_125 = _self_rec_rawIn_normDist_T_103 ? 5'h7 : _self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_126 = _self_rec_rawIn_normDist_T_104 ? 5'h6 : _self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_127 = _self_rec_rawIn_normDist_T_105 ? 5'h5 : _self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_128 = _self_rec_rawIn_normDist_T_106 ? 5'h4 : _self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_129 = _self_rec_rawIn_normDist_T_107 ? 5'h3 : _self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_130 = _self_rec_rawIn_normDist_T_108 ? 5'h2 : _self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_131 = _self_rec_rawIn_normDist_T_109 ? 5'h1 : _self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist_2 = _self_rec_rawIn_normDist_T_110 ? 5'h0 : _self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T_4 = {31'h0, self_rec_rawIn_fractIn_2} << self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_5 = _self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract_2 = {_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_11 = self_rec_rawIn_isZeroExpIn_2 ? _self_rec_rawIn_adjustedExp_T_10 : {1'h0, self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_12 = self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_13 = {6'h20, _self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_14 = {1'h0, _self_rec_rawIn_adjustedExp_T_11} + {2'h0, _self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp_2 = _self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T_4 = self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero_2 = self_rec_rawIn_isZeroExpIn_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_2_isZero = self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T_2 = self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial_2 = &_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_18 = self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T_4 = ~self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_5 = self_rec_rawIn_isSpecial_2 & _self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_2_isNaN = _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T_2 = self_rec_rawIn_isSpecial_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_2_isInf = _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_5 = {1'h0, _self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_2_sExp = _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T_8 = ~self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_9 = {1'h0, _self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_10 = self_rec_rawIn_isZeroExpIn_2 ? self_rec_rawIn_subnormFract_2 : self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_11 = {_self_rec_rawIn_out_sig_T_9, _self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_2_sig = _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T_16 = self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_17 = self_rec_rawIn_2_isZero ? 3'h0 : _self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_19 = {_self_rec_T_17[2:1], _self_rec_T_17[0] | _self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_20 = {self_rec_rawIn_2_sign, _self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_21 = self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_22 = {_self_rec_T_20, _self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_23 = self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec_2 = {_self_rec_T_22, _self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] out_2_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp_2 = _muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T_2 = out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero_2 = _out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_2_isZero = out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T_2 = out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial_2 = &_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T_4 = out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T_6 = out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_5 = out_bits_rawIn_isSpecial_2 & _out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_2_isNaN = _out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_7 = ~_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_8 = out_bits_rawIn_isSpecial_2 & _out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_2_isInf = _out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T_2 = _muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_2_sign = _out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T_2 = {1'h0, out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_2_sExp = _out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T_8 = ~out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_9 = {1'h0, _out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_10 = _muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_11 = {_out_bits_rawIn_out_sig_T_9, _out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_2_sig = _out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal_2 = $signed(out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T_4 = out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist_2 = _out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T_4 = out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_5 = _out_bits_denormFract_T_4 >> out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract_2 = _out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T_12 = out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_13 = {1'h0, _out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_14 = _out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_15 = out_bits_isSubnormal_2 ? 8'h0 : _out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_16 = out_bits_rawIn_2_isNaN | out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_17 = {8{_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut_2 = _out_bits_expOut_T_15 | _out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T_4 = out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_5 = out_bits_rawIn_2_isInf ? 23'h0 : _out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut_2 = out_bits_isSubnormal_2 ? out_bits_denormFract_2 : _out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi_2 = {out_bits_rawIn_2_sign, out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T_2 = {out_bits_hi_2, out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_2_bits = _out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire t_rec_rawIn_3_sign = t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire t_rec_rawIn_isZeroExpIn_3 = t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire t_rec_rawIn_isZeroFractIn_3 = t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _t_rec_rawIn_normDist_T_132 = t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_133 = t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_134 = t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_135 = t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_136 = t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_137 = t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_138 = t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_139 = t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_140 = t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_141 = t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_142 = t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_143 = t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_144 = t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_145 = t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_146 = t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_147 = t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_148 = t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_149 = t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_150 = t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_151 = t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_152 = t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_153 = t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _t_rec_rawIn_normDist_T_154 = t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _t_rec_rawIn_normDist_T_155 = _t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_156 = _t_rec_rawIn_normDist_T_134 ? 5'h14 : _t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_157 = _t_rec_rawIn_normDist_T_135 ? 5'h13 : _t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_158 = _t_rec_rawIn_normDist_T_136 ? 5'h12 : _t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_159 = _t_rec_rawIn_normDist_T_137 ? 5'h11 : _t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_160 = _t_rec_rawIn_normDist_T_138 ? 5'h10 : _t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_161 = _t_rec_rawIn_normDist_T_139 ? 5'hF : _t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_162 = _t_rec_rawIn_normDist_T_140 ? 5'hE : _t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_163 = _t_rec_rawIn_normDist_T_141 ? 5'hD : _t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_164 = _t_rec_rawIn_normDist_T_142 ? 5'hC : _t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_165 = _t_rec_rawIn_normDist_T_143 ? 5'hB : _t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_166 = _t_rec_rawIn_normDist_T_144 ? 5'hA : _t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_167 = _t_rec_rawIn_normDist_T_145 ? 5'h9 : _t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_168 = _t_rec_rawIn_normDist_T_146 ? 5'h8 : _t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_169 = _t_rec_rawIn_normDist_T_147 ? 5'h7 : _t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_170 = _t_rec_rawIn_normDist_T_148 ? 5'h6 : _t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_171 = _t_rec_rawIn_normDist_T_149 ? 5'h5 : _t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_172 = _t_rec_rawIn_normDist_T_150 ? 5'h4 : _t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_173 = _t_rec_rawIn_normDist_T_151 ? 5'h3 : _t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_174 = _t_rec_rawIn_normDist_T_152 ? 5'h2 : _t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _t_rec_rawIn_normDist_T_175 = _t_rec_rawIn_normDist_T_153 ? 5'h1 : _t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] t_rec_rawIn_normDist_3 = _t_rec_rawIn_normDist_T_154 ? 5'h0 : _t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _t_rec_rawIn_subnormFract_T_6 = {31'h0, t_rec_rawIn_fractIn_3} << t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _t_rec_rawIn_subnormFract_T_7 = _t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] t_rec_rawIn_subnormFract_3 = {_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _t_rec_rawIn_adjustedExp_T_16 = t_rec_rawIn_isZeroExpIn_3 ? _t_rec_rawIn_adjustedExp_T_15 : {1'h0, t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _t_rec_rawIn_adjustedExp_T_17 = t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _t_rec_rawIn_adjustedExp_T_18 = {6'h20, _t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _t_rec_rawIn_adjustedExp_T_19 = {1'h0, _t_rec_rawIn_adjustedExp_T_16} + {2'h0, _t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] t_rec_rawIn_adjustedExp_3 = _t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _t_rec_rawIn_out_sExp_T_6 = t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire t_rec_rawIn_isZero_3 = t_rec_rawIn_isZeroExpIn_3 & t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire t_rec_rawIn_3_isZero = t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _t_rec_rawIn_isSpecial_T_3 = t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire t_rec_rawIn_isSpecial_3 = &_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _t_rec_T_26 = t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _t_rec_rawIn_out_isNaN_T_6 = ~t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _t_rec_rawIn_out_isNaN_T_7 = t_rec_rawIn_isSpecial_3 & _t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign t_rec_rawIn_3_isNaN = _t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _t_rec_rawIn_out_isInf_T_3 = t_rec_rawIn_isSpecial_3 & t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign t_rec_rawIn_3_isInf = _t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _t_rec_rawIn_out_sExp_T_7 = {1'h0, _t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign t_rec_rawIn_3_sExp = _t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _t_rec_rawIn_out_sig_T_12 = ~t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _t_rec_rawIn_out_sig_T_13 = {1'h0, _t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _t_rec_rawIn_out_sig_T_14 = t_rec_rawIn_isZeroExpIn_3 ? t_rec_rawIn_subnormFract_3 : t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _t_rec_rawIn_out_sig_T_15 = {_t_rec_rawIn_out_sig_T_13, _t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign t_rec_rawIn_3_sig = _t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _t_rec_T_24 = t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _t_rec_T_25 = t_rec_rawIn_3_isZero ? 3'h0 : _t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _t_rec_T_27 = {_t_rec_T_25[2:1], _t_rec_T_25[0] | _t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _t_rec_T_28 = {t_rec_rawIn_3_sign, _t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _t_rec_T_29 = t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _t_rec_T_30 = {_t_rec_T_28, _t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _t_rec_T_31 = t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] t_rec_3 = {_t_rec_T_30, _t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire self_rec_rawIn_sign_3 = in_bits_in_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire self_rec_rawIn_3_sign = self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] self_rec_rawIn_expIn_3 = in_bits_in_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] self_rec_rawIn_fractIn_3 = in_bits_in_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire self_rec_rawIn_isZeroExpIn_3 = self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire self_rec_rawIn_isZeroFractIn_3 = self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _self_rec_rawIn_normDist_T_132 = self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_133 = self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_134 = self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_135 = self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_136 = self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_137 = self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_138 = self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_139 = self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_140 = self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_141 = self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_142 = self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_143 = self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_144 = self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_145 = self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_146 = self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_147 = self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_148 = self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_149 = self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_150 = self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_151 = self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_152 = self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_153 = self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _self_rec_rawIn_normDist_T_154 = self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _self_rec_rawIn_normDist_T_155 = _self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_156 = _self_rec_rawIn_normDist_T_134 ? 5'h14 : _self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_157 = _self_rec_rawIn_normDist_T_135 ? 5'h13 : _self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_158 = _self_rec_rawIn_normDist_T_136 ? 5'h12 : _self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_159 = _self_rec_rawIn_normDist_T_137 ? 5'h11 : _self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_160 = _self_rec_rawIn_normDist_T_138 ? 5'h10 : _self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_161 = _self_rec_rawIn_normDist_T_139 ? 5'hF : _self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_162 = _self_rec_rawIn_normDist_T_140 ? 5'hE : _self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_163 = _self_rec_rawIn_normDist_T_141 ? 5'hD : _self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_164 = _self_rec_rawIn_normDist_T_142 ? 5'hC : _self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_165 = _self_rec_rawIn_normDist_T_143 ? 5'hB : _self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_166 = _self_rec_rawIn_normDist_T_144 ? 5'hA : _self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_167 = _self_rec_rawIn_normDist_T_145 ? 5'h9 : _self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_168 = _self_rec_rawIn_normDist_T_146 ? 5'h8 : _self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_169 = _self_rec_rawIn_normDist_T_147 ? 5'h7 : _self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_170 = _self_rec_rawIn_normDist_T_148 ? 5'h6 : _self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_171 = _self_rec_rawIn_normDist_T_149 ? 5'h5 : _self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_172 = _self_rec_rawIn_normDist_T_150 ? 5'h4 : _self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_173 = _self_rec_rawIn_normDist_T_151 ? 5'h3 : _self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_174 = _self_rec_rawIn_normDist_T_152 ? 5'h2 : _self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _self_rec_rawIn_normDist_T_175 = _self_rec_rawIn_normDist_T_153 ? 5'h1 : _self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] self_rec_rawIn_normDist_3 = _self_rec_rawIn_normDist_T_154 ? 5'h0 : _self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _self_rec_rawIn_subnormFract_T_6 = {31'h0, self_rec_rawIn_fractIn_3} << self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _self_rec_rawIn_subnormFract_T_7 = _self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] self_rec_rawIn_subnormFract_3 = {_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _self_rec_rawIn_adjustedExp_T_16 = self_rec_rawIn_isZeroExpIn_3 ? _self_rec_rawIn_adjustedExp_T_15 : {1'h0, self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _self_rec_rawIn_adjustedExp_T_17 = self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _self_rec_rawIn_adjustedExp_T_18 = {6'h20, _self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _self_rec_rawIn_adjustedExp_T_19 = {1'h0, _self_rec_rawIn_adjustedExp_T_16} + {2'h0, _self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] self_rec_rawIn_adjustedExp_3 = _self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _self_rec_rawIn_out_sExp_T_6 = self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire self_rec_rawIn_isZero_3 = self_rec_rawIn_isZeroExpIn_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire self_rec_rawIn_3_isZero = self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _self_rec_rawIn_isSpecial_T_3 = self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire self_rec_rawIn_isSpecial_3 = &_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _self_rec_T_26 = self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _self_rec_rawIn_out_isNaN_T_6 = ~self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _self_rec_rawIn_out_isNaN_T_7 = self_rec_rawIn_isSpecial_3 & _self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign self_rec_rawIn_3_isNaN = _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _self_rec_rawIn_out_isInf_T_3 = self_rec_rawIn_isSpecial_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign self_rec_rawIn_3_isInf = _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _self_rec_rawIn_out_sExp_T_7 = {1'h0, _self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign self_rec_rawIn_3_sExp = _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _self_rec_rawIn_out_sig_T_12 = ~self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _self_rec_rawIn_out_sig_T_13 = {1'h0, _self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _self_rec_rawIn_out_sig_T_14 = self_rec_rawIn_isZeroExpIn_3 ? self_rec_rawIn_subnormFract_3 : self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _self_rec_rawIn_out_sig_T_15 = {_self_rec_rawIn_out_sig_T_13, _self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign self_rec_rawIn_3_sig = _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _self_rec_T_24 = self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _self_rec_T_25 = self_rec_rawIn_3_isZero ? 3'h0 : _self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _self_rec_T_27 = {_self_rec_T_25[2:1], _self_rec_T_25[0] | _self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _self_rec_T_28 = {self_rec_rawIn_3_sign, _self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _self_rec_T_29 = self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _self_rec_T_30 = {_self_rec_T_28, _self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _self_rec_T_31 = self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] self_rec_3 = {_self_rec_T_30, _self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] out_3_bits; // @[Arithmetic.scala:350:23] wire [8:0] out_bits_rawIn_exp_3 = _muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_rawIn_isZero_T_3 = out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_rawIn_isZero_3 = _out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_rawIn_3_isZero = out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_rawIn_isSpecial_T_3 = out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_rawIn_isSpecial_3 = &_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_rawIn_out_isNaN_T_6 = out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_rawIn_out_isInf_T_9 = out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_rawIn_out_isNaN_T_7 = out_bits_rawIn_isSpecial_3 & _out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_rawIn_3_isNaN = _out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_rawIn_out_isInf_T_10 = ~_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_rawIn_out_isInf_T_11 = out_bits_rawIn_isSpecial_3 & _out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_rawIn_3_isInf = _out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_rawIn_out_sign_T_3 = _muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_rawIn_3_sign = _out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_rawIn_out_sExp_T_3 = {1'h0, out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_rawIn_3_sExp = _out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_rawIn_out_sig_T_12 = ~out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_rawIn_out_sig_T_13 = {1'h0, _out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_rawIn_out_sig_T_14 = _muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_rawIn_out_sig_T_15 = {_out_bits_rawIn_out_sig_T_13, _out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_rawIn_3_sig = _out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire out_bits_isSubnormal_3 = $signed(out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _out_bits_denormShiftDist_T_6 = out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] out_bits_denormShiftDist_3 = _out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _out_bits_denormFract_T_6 = out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _out_bits_denormFract_T_7 = _out_bits_denormFract_T_6 >> out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] out_bits_denormFract_3 = _out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _out_bits_expOut_T_18 = out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _out_bits_expOut_T_19 = {1'h0, _out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _out_bits_expOut_T_20 = _out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _out_bits_expOut_T_21 = out_bits_isSubnormal_3 ? 8'h0 : _out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _out_bits_expOut_T_22 = out_bits_rawIn_3_isNaN | out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_expOut_T_23 = {8{_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] out_bits_expOut_3 = _out_bits_expOut_T_21 | _out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _out_bits_fractOut_T_6 = out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _out_bits_fractOut_T_7 = out_bits_rawIn_3_isInf ? 23'h0 : _out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] out_bits_fractOut_3 = out_bits_isSubnormal_3 ? out_bits_denormFract_3 : _out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] out_bits_hi_3 = {out_bits_rawIn_3_sign, out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _out_bits_T_3 = {out_bits_hi_3, out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign out_3_bits = _out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[VectorScalarMultiplier.scala:45:7] if (reset) // @[VectorScalarMultiplier.scala:45:7] in_valid <= 1'h0; // @[VectorScalarMultiplier.scala:65:15] else // @[VectorScalarMultiplier.scala:45:7] in_valid <= _T ? io_req_valid_0 : ~(in_fire & _T_1) & in_valid; // @[Decoupled.scala:51:35] if (_T) begin // @[Decoupled.scala:51:35] in_bits_in_0_bits <= io_req_bits_in_0_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_in_1_bits <= io_req_bits_in_1_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_in_2_bits <= io_req_bits_in_2_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_in_3_bits <= io_req_bits_in_3_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_scale_bits <= io_req_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_repeats <= io_req_bits_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_pixel_repeats <= io_req_bits_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_last <= io_req_bits_last_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_data <= io_req_bits_tag_data_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_addr <= io_req_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_0 <= io_req_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_1 <= io_req_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_2 <= io_req_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_3 <= io_req_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_4 <= io_req_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_5 <= io_req_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_6 <= io_req_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_7 <= io_req_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_8 <= io_req_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_9 <= io_req_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_10 <= io_req_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_11 <= io_req_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_12 <= io_req_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_13 <= io_req_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_14 <= io_req_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_mask_15 <= io_req_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_is_acc <= io_req_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_accumulate <= io_req_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_has_acc_bitwidth <= io_req_bits_tag_has_acc_bitwidth_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_scale <= io_req_bits_tag_scale_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_repeats <= io_req_bits_tag_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_pixel_repeats <= io_req_bits_tag_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_len <= io_req_bits_tag_len_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_last <= io_req_bits_tag_last_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_bytes_read <= io_req_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] in_bits_tag_cmd_id <= io_req_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7, :65:15] end else if (in_fire) // @[VectorScalarMultiplier.scala:66:25] in_bits_repeats <= _in_bits_repeats_T_1; // @[VectorScalarMultiplier.scala:65:15, :76:40] always @(posedge) Pipeline_1 pipe ( // @[VectorScalarMultiplier.scala:83:22] .clock (clock), .reset (reset), .io_in_ready (_pipe_io_in_ready), .io_in_valid (in_valid), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_out_0_bits (out_bits), // @[Arithmetic.scala:350:23] .io_in_bits_out_1_bits (out_1_bits), // @[Arithmetic.scala:350:23] .io_in_bits_out_2_bits (out_2_bits), // @[Arithmetic.scala:350:23] .io_in_bits_out_3_bits (out_3_bits), // @[Arithmetic.scala:350:23] .io_in_bits_row (in_bits_repeats), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_last (_pipe_io_in_bits_last_T_1), // @[VectorScalarMultiplier.scala:92:53] .io_in_bits_tag_data (in_bits_tag_data), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_addr (in_bits_tag_addr), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_0 (in_bits_tag_mask_0), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_1 (in_bits_tag_mask_1), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_2 (in_bits_tag_mask_2), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_3 (in_bits_tag_mask_3), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_4 (in_bits_tag_mask_4), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_5 (in_bits_tag_mask_5), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_6 (in_bits_tag_mask_6), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_7 (in_bits_tag_mask_7), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_8 (in_bits_tag_mask_8), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_9 (in_bits_tag_mask_9), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_10 (in_bits_tag_mask_10), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_11 (in_bits_tag_mask_11), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_12 (in_bits_tag_mask_12), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_13 (in_bits_tag_mask_13), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_14 (in_bits_tag_mask_14), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_mask_15 (in_bits_tag_mask_15), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_is_acc (in_bits_tag_is_acc), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_accumulate (in_bits_tag_accumulate), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_has_acc_bitwidth (in_bits_tag_has_acc_bitwidth), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_scale (in_bits_tag_scale), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_repeats (in_bits_tag_repeats), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_pixel_repeats (in_bits_tag_pixel_repeats), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_len (in_bits_tag_len), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_last (in_bits_tag_last), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_bytes_read (in_bits_tag_bytes_read), // @[VectorScalarMultiplier.scala:65:15] .io_in_bits_tag_cmd_id (in_bits_tag_cmd_id), // @[VectorScalarMultiplier.scala:65:15] .io_out_ready (io_resp_ready_0), // @[VectorScalarMultiplier.scala:45:7] .io_out_valid (io_resp_valid_0), .io_out_bits_out_0_bits (io_resp_bits_out_0_bits_0), .io_out_bits_out_1_bits (io_resp_bits_out_1_bits_0), .io_out_bits_out_2_bits (io_resp_bits_out_2_bits_0), .io_out_bits_out_3_bits (io_resp_bits_out_3_bits_0), .io_out_bits_row (io_resp_bits_row_0), .io_out_bits_last (io_resp_bits_last_0), .io_out_bits_tag_data (io_resp_bits_tag_data), .io_out_bits_tag_addr (io_resp_bits_tag_addr_0), .io_out_bits_tag_mask_0 (io_resp_bits_tag_mask_0_0), .io_out_bits_tag_mask_1 (io_resp_bits_tag_mask_1_0), .io_out_bits_tag_mask_2 (io_resp_bits_tag_mask_2_0), .io_out_bits_tag_mask_3 (io_resp_bits_tag_mask_3_0), .io_out_bits_tag_mask_4 (io_resp_bits_tag_mask_4_0), .io_out_bits_tag_mask_5 (io_resp_bits_tag_mask_5_0), .io_out_bits_tag_mask_6 (io_resp_bits_tag_mask_6_0), .io_out_bits_tag_mask_7 (io_resp_bits_tag_mask_7_0), .io_out_bits_tag_mask_8 (io_resp_bits_tag_mask_8_0), .io_out_bits_tag_mask_9 (io_resp_bits_tag_mask_9_0), .io_out_bits_tag_mask_10 (io_resp_bits_tag_mask_10_0), .io_out_bits_tag_mask_11 (io_resp_bits_tag_mask_11_0), .io_out_bits_tag_mask_12 (io_resp_bits_tag_mask_12_0), .io_out_bits_tag_mask_13 (io_resp_bits_tag_mask_13_0), .io_out_bits_tag_mask_14 (io_resp_bits_tag_mask_14_0), .io_out_bits_tag_mask_15 (io_resp_bits_tag_mask_15_0), .io_out_bits_tag_is_acc (io_resp_bits_tag_is_acc_0), .io_out_bits_tag_accumulate (io_resp_bits_tag_accumulate_0), .io_out_bits_tag_has_acc_bitwidth (io_resp_bits_tag_has_acc_bitwidth), .io_out_bits_tag_scale (io_resp_bits_tag_scale), .io_out_bits_tag_repeats (io_resp_bits_tag_repeats), .io_out_bits_tag_pixel_repeats (io_resp_bits_tag_pixel_repeats), .io_out_bits_tag_len (io_resp_bits_tag_len), .io_out_bits_tag_last (io_resp_bits_tag_last), .io_out_bits_tag_bytes_read (io_resp_bits_tag_bytes_read_0), .io_out_bits_tag_cmd_id (io_resp_bits_tag_cmd_id_0) ); // @[VectorScalarMultiplier.scala:83:22] RecFNToRecFN_8 t_resizer ( // @[Arithmetic.scala:336:32] .io_in (t_rec), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_4 muladder ( // @[Arithmetic.scala:342:30] .io_a (self_rec), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_9 t_resizer_1 ( // @[Arithmetic.scala:336:32] .io_in (t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_1_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_5 muladder_1 ( // @[Arithmetic.scala:342:30] .io_a (self_rec_1), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_1_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_1_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_10 t_resizer_2 ( // @[Arithmetic.scala:336:32] .io_in (t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_2_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_6 muladder_2 ( // @[Arithmetic.scala:342:30] .io_a (self_rec_2), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_2_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_2_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_11 t_resizer_3 ( // @[Arithmetic.scala:336:32] .io_in (t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_t_resizer_3_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_7 muladder_3 ( // @[Arithmetic.scala:342:30] .io_a (self_rec_3), // @[recFNFromFN.scala:50:41] .io_b (_t_resizer_3_io_out), // @[Arithmetic.scala:336:32] .io_out (_muladder_3_io_out) ); // @[Arithmetic.scala:342:30] assign io_req_ready = io_req_ready_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_valid = io_resp_valid_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_0_bits = io_resp_bits_out_0_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_1_bits = io_resp_bits_out_1_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_2_bits = io_resp_bits_out_2_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_out_3_bits = io_resp_bits_out_3_bits_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_row = io_resp_bits_row_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_last = io_resp_bits_last_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_addr = io_resp_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_0 = io_resp_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_1 = io_resp_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_2 = io_resp_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_3 = io_resp_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_4 = io_resp_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_5 = io_resp_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_6 = io_resp_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_7 = io_resp_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_8 = io_resp_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_9 = io_resp_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_10 = io_resp_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_11 = io_resp_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_12 = io_resp_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_13 = io_resp_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_14 = io_resp_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_mask_15 = io_resp_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_is_acc = io_resp_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_accumulate = io_resp_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_bytes_read = io_resp_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7] assign io_resp_bits_tag_cmd_id = io_resp_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_111 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h70)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h71)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h72)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h73)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<7>(0h7c)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 2) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<7>(0h7b)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 5) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0hd)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_43 = shr(io.in.a.bits.source, 5) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<4>(0hc)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_49 = shr(io.in.a.bits.source, 5) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<4>(0hb)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_55 = shr(io.in.a.bits.source, 5) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<4>(0ha)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_61 = shr(io.in.a.bits.source, 5) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<4>(0h9)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_67 = shr(io.in.a.bits.source, 5) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<4>(0h8)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_73 = shr(io.in.a.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<7>(0h7a)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_79 = shr(io.in.a.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<7>(0h79)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_85 = shr(io.in.a.bits.source, 5) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<3>(0h7)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_91 = shr(io.in.a.bits.source, 5) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<3>(0h6)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_97 = shr(io.in.a.bits.source, 5) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<3>(0h5)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_103 = shr(io.in.a.bits.source, 5) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_109 = shr(io.in.a.bits.source, 5) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<2>(0h3)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_115 = shr(io.in.a.bits.source, 5) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_121 = shr(io.in.a.bits.source, 5) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h1)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_127 = shr(io.in.a.bits.source, 5) node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h0)) node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129) node _source_ok_T_131 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131) node _source_ok_T_133 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _source_ok_T_134 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _source_ok_T_135 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _source_ok_T_136 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[27] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_48 connect _source_ok_WIRE[9], _source_ok_T_54 connect _source_ok_WIRE[10], _source_ok_T_60 connect _source_ok_WIRE[11], _source_ok_T_66 connect _source_ok_WIRE[12], _source_ok_T_72 connect _source_ok_WIRE[13], _source_ok_T_78 connect _source_ok_WIRE[14], _source_ok_T_84 connect _source_ok_WIRE[15], _source_ok_T_90 connect _source_ok_WIRE[16], _source_ok_T_96 connect _source_ok_WIRE[17], _source_ok_T_102 connect _source_ok_WIRE[18], _source_ok_T_108 connect _source_ok_WIRE[19], _source_ok_T_114 connect _source_ok_WIRE[20], _source_ok_T_120 connect _source_ok_WIRE[21], _source_ok_T_126 connect _source_ok_WIRE[22], _source_ok_T_132 connect _source_ok_WIRE[23], _source_ok_T_133 connect _source_ok_WIRE[24], _source_ok_T_134 connect _source_ok_WIRE[25], _source_ok_T_135 connect _source_ok_WIRE[26], _source_ok_T_136 node _source_ok_T_137 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE[2]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE[3]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE[4]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE[5]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE[6]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE[7]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE[8]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE[9]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE[10]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE[11]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE[12]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE[13]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE[14]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE[15]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE[16]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE[17]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE[18]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE[19]) node _source_ok_T_156 = or(_source_ok_T_155, _source_ok_WIRE[20]) node _source_ok_T_157 = or(_source_ok_T_156, _source_ok_WIRE[21]) node _source_ok_T_158 = or(_source_ok_T_157, _source_ok_WIRE[22]) node _source_ok_T_159 = or(_source_ok_T_158, _source_ok_WIRE[23]) node _source_ok_T_160 = or(_source_ok_T_159, _source_ok_WIRE[24]) node _source_ok_T_161 = or(_source_ok_T_160, _source_ok_WIRE[25]) node source_ok = or(_source_ok_T_161, _source_ok_WIRE[26]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h70)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h71)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h72)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h73)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<7>(0h7c)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_77 = shr(io.in.a.bits.source, 2) node _T_78 = eq(_T_77, UInt<7>(0h7b)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_90 = shr(io.in.a.bits.source, 5) node _T_91 = eq(_T_90, UInt<4>(0hd)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_103 = shr(io.in.a.bits.source, 5) node _T_104 = eq(_T_103, UInt<4>(0hc)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_7) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_116 = shr(io.in.a.bits.source, 5) node _T_117 = eq(_T_116, UInt<4>(0hb)) node _T_118 = leq(UInt<1>(0h0), uncommonBits_8) node _T_119 = and(_T_117, _T_118) node _T_120 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_124 = cvt(_T_123) node _T_125 = and(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = asSInt(_T_125) node _T_127 = eq(_T_126, asSInt(UInt<1>(0h0))) node _T_128 = or(_T_122, _T_127) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_129 = shr(io.in.a.bits.source, 5) node _T_130 = eq(_T_129, UInt<4>(0ha)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_9) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(_T_134, UInt<1>(0h0)) node _T_136 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = or(_T_135, _T_140) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_142 = shr(io.in.a.bits.source, 5) node _T_143 = eq(_T_142, UInt<4>(0h9)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_10) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = or(_T_148, _T_153) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_155 = shr(io.in.a.bits.source, 5) node _T_156 = eq(_T_155, UInt<4>(0h8)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_11) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_160 = and(_T_158, _T_159) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_168 = shr(io.in.a.bits.source, 2) node _T_169 = eq(_T_168, UInt<7>(0h7a)) node _T_170 = leq(UInt<1>(0h0), uncommonBits_12) node _T_171 = and(_T_169, _T_170) node _T_172 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_174, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<7>(0h79)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = or(_T_187, _T_192) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_194 = shr(io.in.a.bits.source, 5) node _T_195 = eq(_T_194, UInt<3>(0h7)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_14) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_207 = shr(io.in.a.bits.source, 5) node _T_208 = eq(_T_207, UInt<3>(0h6)) node _T_209 = leq(UInt<1>(0h0), uncommonBits_15) node _T_210 = and(_T_208, _T_209) node _T_211 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(_T_212, UInt<1>(0h0)) node _T_214 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = or(_T_213, _T_218) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_220 = shr(io.in.a.bits.source, 5) node _T_221 = eq(_T_220, UInt<3>(0h5)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_16) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = or(_T_226, _T_231) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_233 = shr(io.in.a.bits.source, 5) node _T_234 = eq(_T_233, UInt<3>(0h4)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_17) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = or(_T_239, _T_244) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_246 = shr(io.in.a.bits.source, 5) node _T_247 = eq(_T_246, UInt<2>(0h3)) node _T_248 = leq(UInt<1>(0h0), uncommonBits_18) node _T_249 = and(_T_247, _T_248) node _T_250 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_254 = cvt(_T_253) node _T_255 = and(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = asSInt(_T_255) node _T_257 = eq(_T_256, asSInt(UInt<1>(0h0))) node _T_258 = or(_T_252, _T_257) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_259 = shr(io.in.a.bits.source, 5) node _T_260 = eq(_T_259, UInt<2>(0h2)) node _T_261 = leq(UInt<1>(0h0), uncommonBits_19) node _T_262 = and(_T_260, _T_261) node _T_263 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_272 = shr(io.in.a.bits.source, 5) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_20) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_278, _T_283) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_285 = shr(io.in.a.bits.source, 5) node _T_286 = eq(_T_285, UInt<1>(0h0)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_21) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(_T_290, UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = or(_T_291, _T_296) node _T_298 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = or(_T_299, _T_304) node _T_306 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_307 = eq(_T_306, UInt<1>(0h0)) node _T_308 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_307, _T_312) node _T_314 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = or(_T_315, _T_320) node _T_322 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_323 = eq(_T_322, UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_11, _T_24) node _T_331 = and(_T_330, _T_37) node _T_332 = and(_T_331, _T_50) node _T_333 = and(_T_332, _T_63) node _T_334 = and(_T_333, _T_76) node _T_335 = and(_T_334, _T_89) node _T_336 = and(_T_335, _T_102) node _T_337 = and(_T_336, _T_115) node _T_338 = and(_T_337, _T_128) node _T_339 = and(_T_338, _T_141) node _T_340 = and(_T_339, _T_154) node _T_341 = and(_T_340, _T_167) node _T_342 = and(_T_341, _T_180) node _T_343 = and(_T_342, _T_193) node _T_344 = and(_T_343, _T_206) node _T_345 = and(_T_344, _T_219) node _T_346 = and(_T_345, _T_232) node _T_347 = and(_T_346, _T_245) node _T_348 = and(_T_347, _T_258) node _T_349 = and(_T_348, _T_271) node _T_350 = and(_T_349, _T_284) node _T_351 = and(_T_350, _T_297) node _T_352 = and(_T_351, _T_305) node _T_353 = and(_T_352, _T_313) node _T_354 = and(_T_353, _T_321) node _T_355 = and(_T_354, _T_329) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_355, UInt<1>(0h1), "") : assert_1 node _T_359 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_359 : node _T_360 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_361 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_362 = and(_T_360, _T_361) node _T_363 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<7>(0h70)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_22) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<7>(0h71)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_23) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_376 = shr(io.in.a.bits.source, 2) node _T_377 = eq(_T_376, UInt<7>(0h72)) node _T_378 = leq(UInt<1>(0h0), uncommonBits_24) node _T_379 = and(_T_377, _T_378) node _T_380 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_381 = and(_T_379, _T_380) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_382 = shr(io.in.a.bits.source, 2) node _T_383 = eq(_T_382, UInt<7>(0h73)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_25) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_387 = and(_T_385, _T_386) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_388 = shr(io.in.a.bits.source, 2) node _T_389 = eq(_T_388, UInt<7>(0h7c)) node _T_390 = leq(UInt<1>(0h0), uncommonBits_26) node _T_391 = and(_T_389, _T_390) node _T_392 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_393 = and(_T_391, _T_392) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<7>(0h7b)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_27) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_400 = shr(io.in.a.bits.source, 5) node _T_401 = eq(_T_400, UInt<4>(0hd)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_28) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<4>(0hc)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_29) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<4>(0hb)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_30) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_418 = shr(io.in.a.bits.source, 5) node _T_419 = eq(_T_418, UInt<4>(0ha)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_31) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_424 = shr(io.in.a.bits.source, 5) node _T_425 = eq(_T_424, UInt<4>(0h9)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_32) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<4>(0h8)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_33) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<7>(0h7a)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_34) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_442 = shr(io.in.a.bits.source, 2) node _T_443 = eq(_T_442, UInt<7>(0h79)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_35) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h7)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_36) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_454 = shr(io.in.a.bits.source, 5) node _T_455 = eq(_T_454, UInt<3>(0h6)) node _T_456 = leq(UInt<1>(0h0), uncommonBits_37) node _T_457 = and(_T_455, _T_456) node _T_458 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_459 = and(_T_457, _T_458) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_460 = shr(io.in.a.bits.source, 5) node _T_461 = eq(_T_460, UInt<3>(0h5)) node _T_462 = leq(UInt<1>(0h0), uncommonBits_38) node _T_463 = and(_T_461, _T_462) node _T_464 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_465 = and(_T_463, _T_464) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_466 = shr(io.in.a.bits.source, 5) node _T_467 = eq(_T_466, UInt<3>(0h4)) node _T_468 = leq(UInt<1>(0h0), uncommonBits_39) node _T_469 = and(_T_467, _T_468) node _T_470 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_471 = and(_T_469, _T_470) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_472 = shr(io.in.a.bits.source, 5) node _T_473 = eq(_T_472, UInt<2>(0h3)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_40) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_478 = shr(io.in.a.bits.source, 5) node _T_479 = eq(_T_478, UInt<2>(0h2)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_41) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_484 = shr(io.in.a.bits.source, 5) node _T_485 = eq(_T_484, UInt<1>(0h1)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_42) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_490 = shr(io.in.a.bits.source, 5) node _T_491 = eq(_T_490, UInt<1>(0h0)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_43) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_495 = and(_T_493, _T_494) node _T_496 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_497 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_498 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_499 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_500 = or(_T_363, _T_369) node _T_501 = or(_T_500, _T_375) node _T_502 = or(_T_501, _T_381) node _T_503 = or(_T_502, _T_387) node _T_504 = or(_T_503, _T_393) node _T_505 = or(_T_504, _T_399) node _T_506 = or(_T_505, _T_405) node _T_507 = or(_T_506, _T_411) node _T_508 = or(_T_507, _T_417) node _T_509 = or(_T_508, _T_423) node _T_510 = or(_T_509, _T_429) node _T_511 = or(_T_510, _T_435) node _T_512 = or(_T_511, _T_441) node _T_513 = or(_T_512, _T_447) node _T_514 = or(_T_513, _T_453) node _T_515 = or(_T_514, _T_459) node _T_516 = or(_T_515, _T_465) node _T_517 = or(_T_516, _T_471) node _T_518 = or(_T_517, _T_477) node _T_519 = or(_T_518, _T_483) node _T_520 = or(_T_519, _T_489) node _T_521 = or(_T_520, _T_495) node _T_522 = or(_T_521, _T_496) node _T_523 = or(_T_522, _T_497) node _T_524 = or(_T_523, _T_498) node _T_525 = or(_T_524, _T_499) node _T_526 = and(_T_362, _T_525) node _T_527 = or(UInt<1>(0h0), _T_526) node _T_528 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<13>(0h1000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = and(_T_528, _T_533) node _T_535 = or(UInt<1>(0h0), _T_534) node _T_536 = and(_T_527, _T_535) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_536, UInt<1>(0h1), "") : assert_2 node _T_540 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_541 = shr(io.in.a.bits.source, 2) node _T_542 = eq(_T_541, UInt<7>(0h70)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_44) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_547 = shr(io.in.a.bits.source, 2) node _T_548 = eq(_T_547, UInt<7>(0h71)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_45) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<7>(0h72)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_46) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<7>(0h73)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_47) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<7>(0h7c)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_48) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<7>(0h7b)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_49) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_577 = shr(io.in.a.bits.source, 5) node _T_578 = eq(_T_577, UInt<4>(0hd)) node _T_579 = leq(UInt<1>(0h0), uncommonBits_50) node _T_580 = and(_T_578, _T_579) node _T_581 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_582 = and(_T_580, _T_581) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_583 = shr(io.in.a.bits.source, 5) node _T_584 = eq(_T_583, UInt<4>(0hc)) node _T_585 = leq(UInt<1>(0h0), uncommonBits_51) node _T_586 = and(_T_584, _T_585) node _T_587 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_588 = and(_T_586, _T_587) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_589 = shr(io.in.a.bits.source, 5) node _T_590 = eq(_T_589, UInt<4>(0hb)) node _T_591 = leq(UInt<1>(0h0), uncommonBits_52) node _T_592 = and(_T_590, _T_591) node _T_593 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_594 = and(_T_592, _T_593) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_595 = shr(io.in.a.bits.source, 5) node _T_596 = eq(_T_595, UInt<4>(0ha)) node _T_597 = leq(UInt<1>(0h0), uncommonBits_53) node _T_598 = and(_T_596, _T_597) node _T_599 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_600 = and(_T_598, _T_599) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_601 = shr(io.in.a.bits.source, 5) node _T_602 = eq(_T_601, UInt<4>(0h9)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_54) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_607 = shr(io.in.a.bits.source, 5) node _T_608 = eq(_T_607, UInt<4>(0h8)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_55) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_613 = shr(io.in.a.bits.source, 2) node _T_614 = eq(_T_613, UInt<7>(0h7a)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_56) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_619 = shr(io.in.a.bits.source, 2) node _T_620 = eq(_T_619, UInt<7>(0h79)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_57) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_624 = and(_T_622, _T_623) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_625 = shr(io.in.a.bits.source, 5) node _T_626 = eq(_T_625, UInt<3>(0h7)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_58) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_631 = shr(io.in.a.bits.source, 5) node _T_632 = eq(_T_631, UInt<3>(0h6)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_59) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_637 = shr(io.in.a.bits.source, 5) node _T_638 = eq(_T_637, UInt<3>(0h5)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_60) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_643 = shr(io.in.a.bits.source, 5) node _T_644 = eq(_T_643, UInt<3>(0h4)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_61) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_649 = shr(io.in.a.bits.source, 5) node _T_650 = eq(_T_649, UInt<2>(0h3)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_62) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_654 = and(_T_652, _T_653) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_655 = shr(io.in.a.bits.source, 5) node _T_656 = eq(_T_655, UInt<2>(0h2)) node _T_657 = leq(UInt<1>(0h0), uncommonBits_63) node _T_658 = and(_T_656, _T_657) node _T_659 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_660 = and(_T_658, _T_659) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_661 = shr(io.in.a.bits.source, 5) node _T_662 = eq(_T_661, UInt<1>(0h1)) node _T_663 = leq(UInt<1>(0h0), uncommonBits_64) node _T_664 = and(_T_662, _T_663) node _T_665 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_666 = and(_T_664, _T_665) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_667 = shr(io.in.a.bits.source, 5) node _T_668 = eq(_T_667, UInt<1>(0h0)) node _T_669 = leq(UInt<1>(0h0), uncommonBits_65) node _T_670 = and(_T_668, _T_669) node _T_671 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_672 = and(_T_670, _T_671) node _T_673 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_674 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_675 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_676 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[27] connect _WIRE[0], _T_540 connect _WIRE[1], _T_546 connect _WIRE[2], _T_552 connect _WIRE[3], _T_558 connect _WIRE[4], _T_564 connect _WIRE[5], _T_570 connect _WIRE[6], _T_576 connect _WIRE[7], _T_582 connect _WIRE[8], _T_588 connect _WIRE[9], _T_594 connect _WIRE[10], _T_600 connect _WIRE[11], _T_606 connect _WIRE[12], _T_612 connect _WIRE[13], _T_618 connect _WIRE[14], _T_624 connect _WIRE[15], _T_630 connect _WIRE[16], _T_636 connect _WIRE[17], _T_642 connect _WIRE[18], _T_648 connect _WIRE[19], _T_654 connect _WIRE[20], _T_660 connect _WIRE[21], _T_666 connect _WIRE[22], _T_672 connect _WIRE[23], _T_673 connect _WIRE[24], _T_674 connect _WIRE[25], _T_675 connect _WIRE[26], _T_676 node _T_677 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_678 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_682 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_685 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_686 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_687 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_688 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_689 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_690 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_691 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_692 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_693 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_695 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_697 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_698 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_699 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_700 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_701 = mux(_WIRE[23], _T_677, UInt<1>(0h0)) node _T_702 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_703 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = mux(_WIRE[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = or(_T_678, _T_679) node _T_706 = or(_T_705, _T_680) node _T_707 = or(_T_706, _T_681) node _T_708 = or(_T_707, _T_682) node _T_709 = or(_T_708, _T_683) node _T_710 = or(_T_709, _T_684) node _T_711 = or(_T_710, _T_685) node _T_712 = or(_T_711, _T_686) node _T_713 = or(_T_712, _T_687) node _T_714 = or(_T_713, _T_688) node _T_715 = or(_T_714, _T_689) node _T_716 = or(_T_715, _T_690) node _T_717 = or(_T_716, _T_691) node _T_718 = or(_T_717, _T_692) node _T_719 = or(_T_718, _T_693) node _T_720 = or(_T_719, _T_694) node _T_721 = or(_T_720, _T_695) node _T_722 = or(_T_721, _T_696) node _T_723 = or(_T_722, _T_697) node _T_724 = or(_T_723, _T_698) node _T_725 = or(_T_724, _T_699) node _T_726 = or(_T_725, _T_700) node _T_727 = or(_T_726, _T_701) node _T_728 = or(_T_727, _T_702) node _T_729 = or(_T_728, _T_703) node _T_730 = or(_T_729, _T_704) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_730 node _T_731 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_732 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_733 = and(_T_731, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<13>(0h1000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = and(_T_734, _T_739) node _T_741 = or(UInt<1>(0h0), _T_740) node _T_742 = and(_WIRE_1, _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_742, UInt<1>(0h1), "") : assert_3 node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(source_ok, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_749 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_749, UInt<1>(0h1), "") : assert_5 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(is_aligned, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_756 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(_T_756, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_756, UInt<1>(0h1), "") : assert_7 node _T_760 = not(io.in.a.bits.mask) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_761, UInt<1>(0h1), "") : assert_8 node _T_765 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_765, UInt<1>(0h1), "") : assert_9 node _T_769 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_769 : node _T_770 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_771 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_772 = and(_T_770, _T_771) node _T_773 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_774 = shr(io.in.a.bits.source, 2) node _T_775 = eq(_T_774, UInt<7>(0h70)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_66) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_780 = shr(io.in.a.bits.source, 2) node _T_781 = eq(_T_780, UInt<7>(0h71)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_67) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_786 = shr(io.in.a.bits.source, 2) node _T_787 = eq(_T_786, UInt<7>(0h72)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_68) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_792 = shr(io.in.a.bits.source, 2) node _T_793 = eq(_T_792, UInt<7>(0h73)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_69) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_797 = and(_T_795, _T_796) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_798 = shr(io.in.a.bits.source, 2) node _T_799 = eq(_T_798, UInt<7>(0h7c)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_70) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_803 = and(_T_801, _T_802) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_804 = shr(io.in.a.bits.source, 2) node _T_805 = eq(_T_804, UInt<7>(0h7b)) node _T_806 = leq(UInt<1>(0h0), uncommonBits_71) node _T_807 = and(_T_805, _T_806) node _T_808 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_809 = and(_T_807, _T_808) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 4, 0) node _T_810 = shr(io.in.a.bits.source, 5) node _T_811 = eq(_T_810, UInt<4>(0hd)) node _T_812 = leq(UInt<1>(0h0), uncommonBits_72) node _T_813 = and(_T_811, _T_812) node _T_814 = leq(uncommonBits_72, UInt<5>(0h1f)) node _T_815 = and(_T_813, _T_814) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 4, 0) node _T_816 = shr(io.in.a.bits.source, 5) node _T_817 = eq(_T_816, UInt<4>(0hc)) node _T_818 = leq(UInt<1>(0h0), uncommonBits_73) node _T_819 = and(_T_817, _T_818) node _T_820 = leq(uncommonBits_73, UInt<5>(0h1f)) node _T_821 = and(_T_819, _T_820) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 4, 0) node _T_822 = shr(io.in.a.bits.source, 5) node _T_823 = eq(_T_822, UInt<4>(0hb)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_74) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_74, UInt<5>(0h1f)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 4, 0) node _T_828 = shr(io.in.a.bits.source, 5) node _T_829 = eq(_T_828, UInt<4>(0ha)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_75) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_75, UInt<5>(0h1f)) node _T_833 = and(_T_831, _T_832) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_834 = shr(io.in.a.bits.source, 5) node _T_835 = eq(_T_834, UInt<4>(0h9)) node _T_836 = leq(UInt<1>(0h0), uncommonBits_76) node _T_837 = and(_T_835, _T_836) node _T_838 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_839 = and(_T_837, _T_838) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_840 = shr(io.in.a.bits.source, 5) node _T_841 = eq(_T_840, UInt<4>(0h8)) node _T_842 = leq(UInt<1>(0h0), uncommonBits_77) node _T_843 = and(_T_841, _T_842) node _T_844 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_845 = and(_T_843, _T_844) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_846 = shr(io.in.a.bits.source, 2) node _T_847 = eq(_T_846, UInt<7>(0h7a)) node _T_848 = leq(UInt<1>(0h0), uncommonBits_78) node _T_849 = and(_T_847, _T_848) node _T_850 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_851 = and(_T_849, _T_850) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0) node _T_852 = shr(io.in.a.bits.source, 2) node _T_853 = eq(_T_852, UInt<7>(0h79)) node _T_854 = leq(UInt<1>(0h0), uncommonBits_79) node _T_855 = and(_T_853, _T_854) node _T_856 = leq(uncommonBits_79, UInt<2>(0h3)) node _T_857 = and(_T_855, _T_856) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_858 = shr(io.in.a.bits.source, 5) node _T_859 = eq(_T_858, UInt<3>(0h7)) node _T_860 = leq(UInt<1>(0h0), uncommonBits_80) node _T_861 = and(_T_859, _T_860) node _T_862 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_863 = and(_T_861, _T_862) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_864 = shr(io.in.a.bits.source, 5) node _T_865 = eq(_T_864, UInt<3>(0h6)) node _T_866 = leq(UInt<1>(0h0), uncommonBits_81) node _T_867 = and(_T_865, _T_866) node _T_868 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_869 = and(_T_867, _T_868) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_870 = shr(io.in.a.bits.source, 5) node _T_871 = eq(_T_870, UInt<3>(0h5)) node _T_872 = leq(UInt<1>(0h0), uncommonBits_82) node _T_873 = and(_T_871, _T_872) node _T_874 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_875 = and(_T_873, _T_874) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_876 = shr(io.in.a.bits.source, 5) node _T_877 = eq(_T_876, UInt<3>(0h4)) node _T_878 = leq(UInt<1>(0h0), uncommonBits_83) node _T_879 = and(_T_877, _T_878) node _T_880 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_881 = and(_T_879, _T_880) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 4, 0) node _T_882 = shr(io.in.a.bits.source, 5) node _T_883 = eq(_T_882, UInt<2>(0h3)) node _T_884 = leq(UInt<1>(0h0), uncommonBits_84) node _T_885 = and(_T_883, _T_884) node _T_886 = leq(uncommonBits_84, UInt<5>(0h1f)) node _T_887 = and(_T_885, _T_886) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 4, 0) node _T_888 = shr(io.in.a.bits.source, 5) node _T_889 = eq(_T_888, UInt<2>(0h2)) node _T_890 = leq(UInt<1>(0h0), uncommonBits_85) node _T_891 = and(_T_889, _T_890) node _T_892 = leq(uncommonBits_85, UInt<5>(0h1f)) node _T_893 = and(_T_891, _T_892) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 4, 0) node _T_894 = shr(io.in.a.bits.source, 5) node _T_895 = eq(_T_894, UInt<1>(0h1)) node _T_896 = leq(UInt<1>(0h0), uncommonBits_86) node _T_897 = and(_T_895, _T_896) node _T_898 = leq(uncommonBits_86, UInt<5>(0h1f)) node _T_899 = and(_T_897, _T_898) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 4, 0) node _T_900 = shr(io.in.a.bits.source, 5) node _T_901 = eq(_T_900, UInt<1>(0h0)) node _T_902 = leq(UInt<1>(0h0), uncommonBits_87) node _T_903 = and(_T_901, _T_902) node _T_904 = leq(uncommonBits_87, UInt<5>(0h1f)) node _T_905 = and(_T_903, _T_904) node _T_906 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_907 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_908 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_909 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_910 = or(_T_773, _T_779) node _T_911 = or(_T_910, _T_785) node _T_912 = or(_T_911, _T_791) node _T_913 = or(_T_912, _T_797) node _T_914 = or(_T_913, _T_803) node _T_915 = or(_T_914, _T_809) node _T_916 = or(_T_915, _T_815) node _T_917 = or(_T_916, _T_821) node _T_918 = or(_T_917, _T_827) node _T_919 = or(_T_918, _T_833) node _T_920 = or(_T_919, _T_839) node _T_921 = or(_T_920, _T_845) node _T_922 = or(_T_921, _T_851) node _T_923 = or(_T_922, _T_857) node _T_924 = or(_T_923, _T_863) node _T_925 = or(_T_924, _T_869) node _T_926 = or(_T_925, _T_875) node _T_927 = or(_T_926, _T_881) node _T_928 = or(_T_927, _T_887) node _T_929 = or(_T_928, _T_893) node _T_930 = or(_T_929, _T_899) node _T_931 = or(_T_930, _T_905) node _T_932 = or(_T_931, _T_906) node _T_933 = or(_T_932, _T_907) node _T_934 = or(_T_933, _T_908) node _T_935 = or(_T_934, _T_909) node _T_936 = and(_T_772, _T_935) node _T_937 = or(UInt<1>(0h0), _T_936) node _T_938 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_939 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = and(_T_938, _T_943) node _T_945 = or(UInt<1>(0h0), _T_944) node _T_946 = and(_T_937, _T_945) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_946, UInt<1>(0h1), "") : assert_10 node _T_950 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<7>(0h70)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_88) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 1, 0) node _T_957 = shr(io.in.a.bits.source, 2) node _T_958 = eq(_T_957, UInt<7>(0h71)) node _T_959 = leq(UInt<1>(0h0), uncommonBits_89) node _T_960 = and(_T_958, _T_959) node _T_961 = leq(uncommonBits_89, UInt<2>(0h3)) node _T_962 = and(_T_960, _T_961) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 1, 0) node _T_963 = shr(io.in.a.bits.source, 2) node _T_964 = eq(_T_963, UInt<7>(0h72)) node _T_965 = leq(UInt<1>(0h0), uncommonBits_90) node _T_966 = and(_T_964, _T_965) node _T_967 = leq(uncommonBits_90, UInt<2>(0h3)) node _T_968 = and(_T_966, _T_967) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0) node _T_969 = shr(io.in.a.bits.source, 2) node _T_970 = eq(_T_969, UInt<7>(0h73)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_91) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_91, UInt<2>(0h3)) node _T_974 = and(_T_972, _T_973) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0) node _T_975 = shr(io.in.a.bits.source, 2) node _T_976 = eq(_T_975, UInt<7>(0h7c)) node _T_977 = leq(UInt<1>(0h0), uncommonBits_92) node _T_978 = and(_T_976, _T_977) node _T_979 = leq(uncommonBits_92, UInt<2>(0h3)) node _T_980 = and(_T_978, _T_979) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0) node _T_981 = shr(io.in.a.bits.source, 2) node _T_982 = eq(_T_981, UInt<7>(0h7b)) node _T_983 = leq(UInt<1>(0h0), uncommonBits_93) node _T_984 = and(_T_982, _T_983) node _T_985 = leq(uncommonBits_93, UInt<2>(0h3)) node _T_986 = and(_T_984, _T_985) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_987 = shr(io.in.a.bits.source, 5) node _T_988 = eq(_T_987, UInt<4>(0hd)) node _T_989 = leq(UInt<1>(0h0), uncommonBits_94) node _T_990 = and(_T_988, _T_989) node _T_991 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_992 = and(_T_990, _T_991) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_993 = shr(io.in.a.bits.source, 5) node _T_994 = eq(_T_993, UInt<4>(0hc)) node _T_995 = leq(UInt<1>(0h0), uncommonBits_95) node _T_996 = and(_T_994, _T_995) node _T_997 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_998 = and(_T_996, _T_997) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 4, 0) node _T_999 = shr(io.in.a.bits.source, 5) node _T_1000 = eq(_T_999, UInt<4>(0hb)) node _T_1001 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1002 = and(_T_1000, _T_1001) node _T_1003 = leq(uncommonBits_96, UInt<5>(0h1f)) node _T_1004 = and(_T_1002, _T_1003) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 4, 0) node _T_1005 = shr(io.in.a.bits.source, 5) node _T_1006 = eq(_T_1005, UInt<4>(0ha)) node _T_1007 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = leq(uncommonBits_97, UInt<5>(0h1f)) node _T_1010 = and(_T_1008, _T_1009) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 4, 0) node _T_1011 = shr(io.in.a.bits.source, 5) node _T_1012 = eq(_T_1011, UInt<4>(0h9)) node _T_1013 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = leq(uncommonBits_98, UInt<5>(0h1f)) node _T_1016 = and(_T_1014, _T_1015) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 4, 0) node _T_1017 = shr(io.in.a.bits.source, 5) node _T_1018 = eq(_T_1017, UInt<4>(0h8)) node _T_1019 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1020 = and(_T_1018, _T_1019) node _T_1021 = leq(uncommonBits_99, UInt<5>(0h1f)) node _T_1022 = and(_T_1020, _T_1021) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 1, 0) node _T_1023 = shr(io.in.a.bits.source, 2) node _T_1024 = eq(_T_1023, UInt<7>(0h7a)) node _T_1025 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = leq(uncommonBits_100, UInt<2>(0h3)) node _T_1028 = and(_T_1026, _T_1027) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 1, 0) node _T_1029 = shr(io.in.a.bits.source, 2) node _T_1030 = eq(_T_1029, UInt<7>(0h79)) node _T_1031 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = leq(uncommonBits_101, UInt<2>(0h3)) node _T_1034 = and(_T_1032, _T_1033) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1035 = shr(io.in.a.bits.source, 5) node _T_1036 = eq(_T_1035, UInt<3>(0h7)) node _T_1037 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1040 = and(_T_1038, _T_1039) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1041 = shr(io.in.a.bits.source, 5) node _T_1042 = eq(_T_1041, UInt<3>(0h6)) node _T_1043 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1046 = and(_T_1044, _T_1045) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1047 = shr(io.in.a.bits.source, 5) node _T_1048 = eq(_T_1047, UInt<3>(0h5)) node _T_1049 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1050 = and(_T_1048, _T_1049) node _T_1051 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1052 = and(_T_1050, _T_1051) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1053 = shr(io.in.a.bits.source, 5) node _T_1054 = eq(_T_1053, UInt<3>(0h4)) node _T_1055 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1056 = and(_T_1054, _T_1055) node _T_1057 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1058 = and(_T_1056, _T_1057) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1059 = shr(io.in.a.bits.source, 5) node _T_1060 = eq(_T_1059, UInt<2>(0h3)) node _T_1061 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1064 = and(_T_1062, _T_1063) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1065 = shr(io.in.a.bits.source, 5) node _T_1066 = eq(_T_1065, UInt<2>(0h2)) node _T_1067 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1070 = and(_T_1068, _T_1069) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 4, 0) node _T_1071 = shr(io.in.a.bits.source, 5) node _T_1072 = eq(_T_1071, UInt<1>(0h1)) node _T_1073 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1074 = and(_T_1072, _T_1073) node _T_1075 = leq(uncommonBits_108, UInt<5>(0h1f)) node _T_1076 = and(_T_1074, _T_1075) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 4, 0) node _T_1077 = shr(io.in.a.bits.source, 5) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) node _T_1079 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1080 = and(_T_1078, _T_1079) node _T_1081 = leq(uncommonBits_109, UInt<5>(0h1f)) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1084 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1085 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1086 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[27] connect _WIRE_2[0], _T_950 connect _WIRE_2[1], _T_956 connect _WIRE_2[2], _T_962 connect _WIRE_2[3], _T_968 connect _WIRE_2[4], _T_974 connect _WIRE_2[5], _T_980 connect _WIRE_2[6], _T_986 connect _WIRE_2[7], _T_992 connect _WIRE_2[8], _T_998 connect _WIRE_2[9], _T_1004 connect _WIRE_2[10], _T_1010 connect _WIRE_2[11], _T_1016 connect _WIRE_2[12], _T_1022 connect _WIRE_2[13], _T_1028 connect _WIRE_2[14], _T_1034 connect _WIRE_2[15], _T_1040 connect _WIRE_2[16], _T_1046 connect _WIRE_2[17], _T_1052 connect _WIRE_2[18], _T_1058 connect _WIRE_2[19], _T_1064 connect _WIRE_2[20], _T_1070 connect _WIRE_2[21], _T_1076 connect _WIRE_2[22], _T_1082 connect _WIRE_2[23], _T_1083 connect _WIRE_2[24], _T_1084 connect _WIRE_2[25], _T_1085 connect _WIRE_2[26], _T_1086 node _T_1087 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1088 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1089 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1090 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1091 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1092 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1094 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1096 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1097 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_1098 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1099 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1100 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1101 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_1102 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_1103 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_1104 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1105 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_1106 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1107 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_1108 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_1109 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_1110 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_1111 = mux(_WIRE_2[23], _T_1087, UInt<1>(0h0)) node _T_1112 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_1113 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_1114 = mux(_WIRE_2[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_1115 = or(_T_1088, _T_1089) node _T_1116 = or(_T_1115, _T_1090) node _T_1117 = or(_T_1116, _T_1091) node _T_1118 = or(_T_1117, _T_1092) node _T_1119 = or(_T_1118, _T_1093) node _T_1120 = or(_T_1119, _T_1094) node _T_1121 = or(_T_1120, _T_1095) node _T_1122 = or(_T_1121, _T_1096) node _T_1123 = or(_T_1122, _T_1097) node _T_1124 = or(_T_1123, _T_1098) node _T_1125 = or(_T_1124, _T_1099) node _T_1126 = or(_T_1125, _T_1100) node _T_1127 = or(_T_1126, _T_1101) node _T_1128 = or(_T_1127, _T_1102) node _T_1129 = or(_T_1128, _T_1103) node _T_1130 = or(_T_1129, _T_1104) node _T_1131 = or(_T_1130, _T_1105) node _T_1132 = or(_T_1131, _T_1106) node _T_1133 = or(_T_1132, _T_1107) node _T_1134 = or(_T_1133, _T_1108) node _T_1135 = or(_T_1134, _T_1109) node _T_1136 = or(_T_1135, _T_1110) node _T_1137 = or(_T_1136, _T_1111) node _T_1138 = or(_T_1137, _T_1112) node _T_1139 = or(_T_1138, _T_1113) node _T_1140 = or(_T_1139, _T_1114) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1140 node _T_1141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1142 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = or(UInt<1>(0h0), _T_1143) node _T_1145 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1146 = cvt(_T_1145) node _T_1147 = and(_T_1146, asSInt(UInt<13>(0h1000))) node _T_1148 = asSInt(_T_1147) node _T_1149 = eq(_T_1148, asSInt(UInt<1>(0h0))) node _T_1150 = and(_T_1144, _T_1149) node _T_1151 = or(UInt<1>(0h0), _T_1150) node _T_1152 = and(_WIRE_3, _T_1151) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_11 node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(source_ok, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1159 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_13 node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(is_aligned, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1166 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_15 node _T_1170 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_16 node _T_1174 = not(io.in.a.bits.mask) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_17 node _T_1179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_18 node _T_1183 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1183 : node _T_1184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1188 = shr(io.in.a.bits.source, 2) node _T_1189 = eq(_T_1188, UInt<7>(0h70)) node _T_1190 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1193 = and(_T_1191, _T_1192) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<7>(0h71)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<7>(0h72)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_112, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 1, 0) node _T_1206 = shr(io.in.a.bits.source, 2) node _T_1207 = eq(_T_1206, UInt<7>(0h73)) node _T_1208 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = leq(uncommonBits_113, UInt<2>(0h3)) node _T_1211 = and(_T_1209, _T_1210) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 1, 0) node _T_1212 = shr(io.in.a.bits.source, 2) node _T_1213 = eq(_T_1212, UInt<7>(0h7c)) node _T_1214 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = leq(uncommonBits_114, UInt<2>(0h3)) node _T_1217 = and(_T_1215, _T_1216) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 1, 0) node _T_1218 = shr(io.in.a.bits.source, 2) node _T_1219 = eq(_T_1218, UInt<7>(0h7b)) node _T_1220 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1221 = and(_T_1219, _T_1220) node _T_1222 = leq(uncommonBits_115, UInt<2>(0h3)) node _T_1223 = and(_T_1221, _T_1222) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1224 = shr(io.in.a.bits.source, 5) node _T_1225 = eq(_T_1224, UInt<4>(0hd)) node _T_1226 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1229 = and(_T_1227, _T_1228) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1230 = shr(io.in.a.bits.source, 5) node _T_1231 = eq(_T_1230, UInt<4>(0hc)) node _T_1232 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1235 = and(_T_1233, _T_1234) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1236 = shr(io.in.a.bits.source, 5) node _T_1237 = eq(_T_1236, UInt<4>(0hb)) node _T_1238 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1241 = and(_T_1239, _T_1240) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1242 = shr(io.in.a.bits.source, 5) node _T_1243 = eq(_T_1242, UInt<4>(0ha)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1247 = and(_T_1245, _T_1246) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 4, 0) node _T_1248 = shr(io.in.a.bits.source, 5) node _T_1249 = eq(_T_1248, UInt<4>(0h9)) node _T_1250 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = leq(uncommonBits_120, UInt<5>(0h1f)) node _T_1253 = and(_T_1251, _T_1252) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 4, 0) node _T_1254 = shr(io.in.a.bits.source, 5) node _T_1255 = eq(_T_1254, UInt<4>(0h8)) node _T_1256 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = leq(uncommonBits_121, UInt<5>(0h1f)) node _T_1259 = and(_T_1257, _T_1258) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1260 = shr(io.in.a.bits.source, 2) node _T_1261 = eq(_T_1260, UInt<7>(0h7a)) node _T_1262 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1265 = and(_T_1263, _T_1264) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1266 = shr(io.in.a.bits.source, 2) node _T_1267 = eq(_T_1266, UInt<7>(0h79)) node _T_1268 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1271 = and(_T_1269, _T_1270) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1272 = shr(io.in.a.bits.source, 5) node _T_1273 = eq(_T_1272, UInt<3>(0h7)) node _T_1274 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1277 = and(_T_1275, _T_1276) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1278 = shr(io.in.a.bits.source, 5) node _T_1279 = eq(_T_1278, UInt<3>(0h6)) node _T_1280 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1281 = and(_T_1279, _T_1280) node _T_1282 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1283 = and(_T_1281, _T_1282) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1284 = shr(io.in.a.bits.source, 5) node _T_1285 = eq(_T_1284, UInt<3>(0h5)) node _T_1286 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1289 = and(_T_1287, _T_1288) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1290 = shr(io.in.a.bits.source, 5) node _T_1291 = eq(_T_1290, UInt<3>(0h4)) node _T_1292 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1293 = and(_T_1291, _T_1292) node _T_1294 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1295 = and(_T_1293, _T_1294) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1296 = shr(io.in.a.bits.source, 5) node _T_1297 = eq(_T_1296, UInt<2>(0h3)) node _T_1298 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1301 = and(_T_1299, _T_1300) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1302 = shr(io.in.a.bits.source, 5) node _T_1303 = eq(_T_1302, UInt<2>(0h2)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1307 = and(_T_1305, _T_1306) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1308 = shr(io.in.a.bits.source, 5) node _T_1309 = eq(_T_1308, UInt<1>(0h1)) node _T_1310 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1313 = and(_T_1311, _T_1312) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1314 = shr(io.in.a.bits.source, 5) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) node _T_1316 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1317 = and(_T_1315, _T_1316) node _T_1318 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1321 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1322 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1323 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1324 = or(_T_1187, _T_1193) node _T_1325 = or(_T_1324, _T_1199) node _T_1326 = or(_T_1325, _T_1205) node _T_1327 = or(_T_1326, _T_1211) node _T_1328 = or(_T_1327, _T_1217) node _T_1329 = or(_T_1328, _T_1223) node _T_1330 = or(_T_1329, _T_1229) node _T_1331 = or(_T_1330, _T_1235) node _T_1332 = or(_T_1331, _T_1241) node _T_1333 = or(_T_1332, _T_1247) node _T_1334 = or(_T_1333, _T_1253) node _T_1335 = or(_T_1334, _T_1259) node _T_1336 = or(_T_1335, _T_1265) node _T_1337 = or(_T_1336, _T_1271) node _T_1338 = or(_T_1337, _T_1277) node _T_1339 = or(_T_1338, _T_1283) node _T_1340 = or(_T_1339, _T_1289) node _T_1341 = or(_T_1340, _T_1295) node _T_1342 = or(_T_1341, _T_1301) node _T_1343 = or(_T_1342, _T_1307) node _T_1344 = or(_T_1343, _T_1313) node _T_1345 = or(_T_1344, _T_1319) node _T_1346 = or(_T_1345, _T_1320) node _T_1347 = or(_T_1346, _T_1321) node _T_1348 = or(_T_1347, _T_1322) node _T_1349 = or(_T_1348, _T_1323) node _T_1350 = and(_T_1186, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1350) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_19 node _T_1355 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1356 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1357 = and(_T_1355, _T_1356) node _T_1358 = or(UInt<1>(0h0), _T_1357) node _T_1359 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1360 = cvt(_T_1359) node _T_1361 = and(_T_1360, asSInt(UInt<13>(0h1000))) node _T_1362 = asSInt(_T_1361) node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0))) node _T_1364 = and(_T_1358, _T_1363) node _T_1365 = or(UInt<1>(0h0), _T_1364) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_20 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(source_ok, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(is_aligned, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1375 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_23 node _T_1379 = eq(io.in.a.bits.mask, mask) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_24 node _T_1383 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_25 node _T_1387 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1387 : node _T_1388 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1389 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_132 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_132 = bits(_uncommonBits_T_132, 1, 0) node _T_1392 = shr(io.in.a.bits.source, 2) node _T_1393 = eq(_T_1392, UInt<7>(0h70)) node _T_1394 = leq(UInt<1>(0h0), uncommonBits_132) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = leq(uncommonBits_132, UInt<2>(0h3)) node _T_1397 = and(_T_1395, _T_1396) node _uncommonBits_T_133 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_133 = bits(_uncommonBits_T_133, 1, 0) node _T_1398 = shr(io.in.a.bits.source, 2) node _T_1399 = eq(_T_1398, UInt<7>(0h71)) node _T_1400 = leq(UInt<1>(0h0), uncommonBits_133) node _T_1401 = and(_T_1399, _T_1400) node _T_1402 = leq(uncommonBits_133, UInt<2>(0h3)) node _T_1403 = and(_T_1401, _T_1402) node _uncommonBits_T_134 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_134 = bits(_uncommonBits_T_134, 1, 0) node _T_1404 = shr(io.in.a.bits.source, 2) node _T_1405 = eq(_T_1404, UInt<7>(0h72)) node _T_1406 = leq(UInt<1>(0h0), uncommonBits_134) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = leq(uncommonBits_134, UInt<2>(0h3)) node _T_1409 = and(_T_1407, _T_1408) node _uncommonBits_T_135 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_135 = bits(_uncommonBits_T_135, 1, 0) node _T_1410 = shr(io.in.a.bits.source, 2) node _T_1411 = eq(_T_1410, UInt<7>(0h73)) node _T_1412 = leq(UInt<1>(0h0), uncommonBits_135) node _T_1413 = and(_T_1411, _T_1412) node _T_1414 = leq(uncommonBits_135, UInt<2>(0h3)) node _T_1415 = and(_T_1413, _T_1414) node _uncommonBits_T_136 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_136 = bits(_uncommonBits_T_136, 1, 0) node _T_1416 = shr(io.in.a.bits.source, 2) node _T_1417 = eq(_T_1416, UInt<7>(0h7c)) node _T_1418 = leq(UInt<1>(0h0), uncommonBits_136) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = leq(uncommonBits_136, UInt<2>(0h3)) node _T_1421 = and(_T_1419, _T_1420) node _uncommonBits_T_137 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_137 = bits(_uncommonBits_T_137, 1, 0) node _T_1422 = shr(io.in.a.bits.source, 2) node _T_1423 = eq(_T_1422, UInt<7>(0h7b)) node _T_1424 = leq(UInt<1>(0h0), uncommonBits_137) node _T_1425 = and(_T_1423, _T_1424) node _T_1426 = leq(uncommonBits_137, UInt<2>(0h3)) node _T_1427 = and(_T_1425, _T_1426) node _uncommonBits_T_138 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_138 = bits(_uncommonBits_T_138, 4, 0) node _T_1428 = shr(io.in.a.bits.source, 5) node _T_1429 = eq(_T_1428, UInt<4>(0hd)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_138) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_138, UInt<5>(0h1f)) node _T_1433 = and(_T_1431, _T_1432) node _uncommonBits_T_139 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_139 = bits(_uncommonBits_T_139, 4, 0) node _T_1434 = shr(io.in.a.bits.source, 5) node _T_1435 = eq(_T_1434, UInt<4>(0hc)) node _T_1436 = leq(UInt<1>(0h0), uncommonBits_139) node _T_1437 = and(_T_1435, _T_1436) node _T_1438 = leq(uncommonBits_139, UInt<5>(0h1f)) node _T_1439 = and(_T_1437, _T_1438) node _uncommonBits_T_140 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_140 = bits(_uncommonBits_T_140, 4, 0) node _T_1440 = shr(io.in.a.bits.source, 5) node _T_1441 = eq(_T_1440, UInt<4>(0hb)) node _T_1442 = leq(UInt<1>(0h0), uncommonBits_140) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = leq(uncommonBits_140, UInt<5>(0h1f)) node _T_1445 = and(_T_1443, _T_1444) node _uncommonBits_T_141 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_141 = bits(_uncommonBits_T_141, 4, 0) node _T_1446 = shr(io.in.a.bits.source, 5) node _T_1447 = eq(_T_1446, UInt<4>(0ha)) node _T_1448 = leq(UInt<1>(0h0), uncommonBits_141) node _T_1449 = and(_T_1447, _T_1448) node _T_1450 = leq(uncommonBits_141, UInt<5>(0h1f)) node _T_1451 = and(_T_1449, _T_1450) node _uncommonBits_T_142 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_142 = bits(_uncommonBits_T_142, 4, 0) node _T_1452 = shr(io.in.a.bits.source, 5) node _T_1453 = eq(_T_1452, UInt<4>(0h9)) node _T_1454 = leq(UInt<1>(0h0), uncommonBits_142) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = leq(uncommonBits_142, UInt<5>(0h1f)) node _T_1457 = and(_T_1455, _T_1456) node _uncommonBits_T_143 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_143 = bits(_uncommonBits_T_143, 4, 0) node _T_1458 = shr(io.in.a.bits.source, 5) node _T_1459 = eq(_T_1458, UInt<4>(0h8)) node _T_1460 = leq(UInt<1>(0h0), uncommonBits_143) node _T_1461 = and(_T_1459, _T_1460) node _T_1462 = leq(uncommonBits_143, UInt<5>(0h1f)) node _T_1463 = and(_T_1461, _T_1462) node _uncommonBits_T_144 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_144 = bits(_uncommonBits_T_144, 1, 0) node _T_1464 = shr(io.in.a.bits.source, 2) node _T_1465 = eq(_T_1464, UInt<7>(0h7a)) node _T_1466 = leq(UInt<1>(0h0), uncommonBits_144) node _T_1467 = and(_T_1465, _T_1466) node _T_1468 = leq(uncommonBits_144, UInt<2>(0h3)) node _T_1469 = and(_T_1467, _T_1468) node _uncommonBits_T_145 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_145 = bits(_uncommonBits_T_145, 1, 0) node _T_1470 = shr(io.in.a.bits.source, 2) node _T_1471 = eq(_T_1470, UInt<7>(0h79)) node _T_1472 = leq(UInt<1>(0h0), uncommonBits_145) node _T_1473 = and(_T_1471, _T_1472) node _T_1474 = leq(uncommonBits_145, UInt<2>(0h3)) node _T_1475 = and(_T_1473, _T_1474) node _uncommonBits_T_146 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_146 = bits(_uncommonBits_T_146, 4, 0) node _T_1476 = shr(io.in.a.bits.source, 5) node _T_1477 = eq(_T_1476, UInt<3>(0h7)) node _T_1478 = leq(UInt<1>(0h0), uncommonBits_146) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = leq(uncommonBits_146, UInt<5>(0h1f)) node _T_1481 = and(_T_1479, _T_1480) node _uncommonBits_T_147 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_147 = bits(_uncommonBits_T_147, 4, 0) node _T_1482 = shr(io.in.a.bits.source, 5) node _T_1483 = eq(_T_1482, UInt<3>(0h6)) node _T_1484 = leq(UInt<1>(0h0), uncommonBits_147) node _T_1485 = and(_T_1483, _T_1484) node _T_1486 = leq(uncommonBits_147, UInt<5>(0h1f)) node _T_1487 = and(_T_1485, _T_1486) node _uncommonBits_T_148 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_148 = bits(_uncommonBits_T_148, 4, 0) node _T_1488 = shr(io.in.a.bits.source, 5) node _T_1489 = eq(_T_1488, UInt<3>(0h5)) node _T_1490 = leq(UInt<1>(0h0), uncommonBits_148) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = leq(uncommonBits_148, UInt<5>(0h1f)) node _T_1493 = and(_T_1491, _T_1492) node _uncommonBits_T_149 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_149 = bits(_uncommonBits_T_149, 4, 0) node _T_1494 = shr(io.in.a.bits.source, 5) node _T_1495 = eq(_T_1494, UInt<3>(0h4)) node _T_1496 = leq(UInt<1>(0h0), uncommonBits_149) node _T_1497 = and(_T_1495, _T_1496) node _T_1498 = leq(uncommonBits_149, UInt<5>(0h1f)) node _T_1499 = and(_T_1497, _T_1498) node _uncommonBits_T_150 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_150 = bits(_uncommonBits_T_150, 4, 0) node _T_1500 = shr(io.in.a.bits.source, 5) node _T_1501 = eq(_T_1500, UInt<2>(0h3)) node _T_1502 = leq(UInt<1>(0h0), uncommonBits_150) node _T_1503 = and(_T_1501, _T_1502) node _T_1504 = leq(uncommonBits_150, UInt<5>(0h1f)) node _T_1505 = and(_T_1503, _T_1504) node _uncommonBits_T_151 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_151 = bits(_uncommonBits_T_151, 4, 0) node _T_1506 = shr(io.in.a.bits.source, 5) node _T_1507 = eq(_T_1506, UInt<2>(0h2)) node _T_1508 = leq(UInt<1>(0h0), uncommonBits_151) node _T_1509 = and(_T_1507, _T_1508) node _T_1510 = leq(uncommonBits_151, UInt<5>(0h1f)) node _T_1511 = and(_T_1509, _T_1510) node _uncommonBits_T_152 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_152 = bits(_uncommonBits_T_152, 4, 0) node _T_1512 = shr(io.in.a.bits.source, 5) node _T_1513 = eq(_T_1512, UInt<1>(0h1)) node _T_1514 = leq(UInt<1>(0h0), uncommonBits_152) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = leq(uncommonBits_152, UInt<5>(0h1f)) node _T_1517 = and(_T_1515, _T_1516) node _uncommonBits_T_153 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_153 = bits(_uncommonBits_T_153, 4, 0) node _T_1518 = shr(io.in.a.bits.source, 5) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) node _T_1520 = leq(UInt<1>(0h0), uncommonBits_153) node _T_1521 = and(_T_1519, _T_1520) node _T_1522 = leq(uncommonBits_153, UInt<5>(0h1f)) node _T_1523 = and(_T_1521, _T_1522) node _T_1524 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1525 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1526 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1527 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1528 = or(_T_1391, _T_1397) node _T_1529 = or(_T_1528, _T_1403) node _T_1530 = or(_T_1529, _T_1409) node _T_1531 = or(_T_1530, _T_1415) node _T_1532 = or(_T_1531, _T_1421) node _T_1533 = or(_T_1532, _T_1427) node _T_1534 = or(_T_1533, _T_1433) node _T_1535 = or(_T_1534, _T_1439) node _T_1536 = or(_T_1535, _T_1445) node _T_1537 = or(_T_1536, _T_1451) node _T_1538 = or(_T_1537, _T_1457) node _T_1539 = or(_T_1538, _T_1463) node _T_1540 = or(_T_1539, _T_1469) node _T_1541 = or(_T_1540, _T_1475) node _T_1542 = or(_T_1541, _T_1481) node _T_1543 = or(_T_1542, _T_1487) node _T_1544 = or(_T_1543, _T_1493) node _T_1545 = or(_T_1544, _T_1499) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1511) node _T_1548 = or(_T_1547, _T_1517) node _T_1549 = or(_T_1548, _T_1523) node _T_1550 = or(_T_1549, _T_1524) node _T_1551 = or(_T_1550, _T_1525) node _T_1552 = or(_T_1551, _T_1526) node _T_1553 = or(_T_1552, _T_1527) node _T_1554 = and(_T_1390, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1557 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = or(UInt<1>(0h0), _T_1558) node _T_1560 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<13>(0h1000))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = and(_T_1559, _T_1564) node _T_1566 = or(UInt<1>(0h0), _T_1565) node _T_1567 = and(_T_1555, _T_1566) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_26 node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(source_ok, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(is_aligned, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1577 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_29 node _T_1581 = eq(io.in.a.bits.mask, mask) node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(_T_1581, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1581, UInt<1>(0h1), "") : assert_30 node _T_1585 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1585 : node _T_1586 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1587 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1588 = and(_T_1586, _T_1587) node _T_1589 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_154 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_154 = bits(_uncommonBits_T_154, 1, 0) node _T_1590 = shr(io.in.a.bits.source, 2) node _T_1591 = eq(_T_1590, UInt<7>(0h70)) node _T_1592 = leq(UInt<1>(0h0), uncommonBits_154) node _T_1593 = and(_T_1591, _T_1592) node _T_1594 = leq(uncommonBits_154, UInt<2>(0h3)) node _T_1595 = and(_T_1593, _T_1594) node _uncommonBits_T_155 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_155 = bits(_uncommonBits_T_155, 1, 0) node _T_1596 = shr(io.in.a.bits.source, 2) node _T_1597 = eq(_T_1596, UInt<7>(0h71)) node _T_1598 = leq(UInt<1>(0h0), uncommonBits_155) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = leq(uncommonBits_155, UInt<2>(0h3)) node _T_1601 = and(_T_1599, _T_1600) node _uncommonBits_T_156 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_156 = bits(_uncommonBits_T_156, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<7>(0h72)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_156) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_156, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_157 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_157 = bits(_uncommonBits_T_157, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<7>(0h73)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_157) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_157, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_158 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_158 = bits(_uncommonBits_T_158, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<7>(0h7c)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_158) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_158, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_159 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_159 = bits(_uncommonBits_T_159, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<7>(0h7b)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_159) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_159, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _uncommonBits_T_160 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_160 = bits(_uncommonBits_T_160, 4, 0) node _T_1626 = shr(io.in.a.bits.source, 5) node _T_1627 = eq(_T_1626, UInt<4>(0hd)) node _T_1628 = leq(UInt<1>(0h0), uncommonBits_160) node _T_1629 = and(_T_1627, _T_1628) node _T_1630 = leq(uncommonBits_160, UInt<5>(0h1f)) node _T_1631 = and(_T_1629, _T_1630) node _uncommonBits_T_161 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_161 = bits(_uncommonBits_T_161, 4, 0) node _T_1632 = shr(io.in.a.bits.source, 5) node _T_1633 = eq(_T_1632, UInt<4>(0hc)) node _T_1634 = leq(UInt<1>(0h0), uncommonBits_161) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = leq(uncommonBits_161, UInt<5>(0h1f)) node _T_1637 = and(_T_1635, _T_1636) node _uncommonBits_T_162 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_162 = bits(_uncommonBits_T_162, 4, 0) node _T_1638 = shr(io.in.a.bits.source, 5) node _T_1639 = eq(_T_1638, UInt<4>(0hb)) node _T_1640 = leq(UInt<1>(0h0), uncommonBits_162) node _T_1641 = and(_T_1639, _T_1640) node _T_1642 = leq(uncommonBits_162, UInt<5>(0h1f)) node _T_1643 = and(_T_1641, _T_1642) node _uncommonBits_T_163 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_163 = bits(_uncommonBits_T_163, 4, 0) node _T_1644 = shr(io.in.a.bits.source, 5) node _T_1645 = eq(_T_1644, UInt<4>(0ha)) node _T_1646 = leq(UInt<1>(0h0), uncommonBits_163) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = leq(uncommonBits_163, UInt<5>(0h1f)) node _T_1649 = and(_T_1647, _T_1648) node _uncommonBits_T_164 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_164 = bits(_uncommonBits_T_164, 4, 0) node _T_1650 = shr(io.in.a.bits.source, 5) node _T_1651 = eq(_T_1650, UInt<4>(0h9)) node _T_1652 = leq(UInt<1>(0h0), uncommonBits_164) node _T_1653 = and(_T_1651, _T_1652) node _T_1654 = leq(uncommonBits_164, UInt<5>(0h1f)) node _T_1655 = and(_T_1653, _T_1654) node _uncommonBits_T_165 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_165 = bits(_uncommonBits_T_165, 4, 0) node _T_1656 = shr(io.in.a.bits.source, 5) node _T_1657 = eq(_T_1656, UInt<4>(0h8)) node _T_1658 = leq(UInt<1>(0h0), uncommonBits_165) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = leq(uncommonBits_165, UInt<5>(0h1f)) node _T_1661 = and(_T_1659, _T_1660) node _uncommonBits_T_166 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_166 = bits(_uncommonBits_T_166, 1, 0) node _T_1662 = shr(io.in.a.bits.source, 2) node _T_1663 = eq(_T_1662, UInt<7>(0h7a)) node _T_1664 = leq(UInt<1>(0h0), uncommonBits_166) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = leq(uncommonBits_166, UInt<2>(0h3)) node _T_1667 = and(_T_1665, _T_1666) node _uncommonBits_T_167 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_167 = bits(_uncommonBits_T_167, 1, 0) node _T_1668 = shr(io.in.a.bits.source, 2) node _T_1669 = eq(_T_1668, UInt<7>(0h79)) node _T_1670 = leq(UInt<1>(0h0), uncommonBits_167) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = leq(uncommonBits_167, UInt<2>(0h3)) node _T_1673 = and(_T_1671, _T_1672) node _uncommonBits_T_168 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_168 = bits(_uncommonBits_T_168, 4, 0) node _T_1674 = shr(io.in.a.bits.source, 5) node _T_1675 = eq(_T_1674, UInt<3>(0h7)) node _T_1676 = leq(UInt<1>(0h0), uncommonBits_168) node _T_1677 = and(_T_1675, _T_1676) node _T_1678 = leq(uncommonBits_168, UInt<5>(0h1f)) node _T_1679 = and(_T_1677, _T_1678) node _uncommonBits_T_169 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_169 = bits(_uncommonBits_T_169, 4, 0) node _T_1680 = shr(io.in.a.bits.source, 5) node _T_1681 = eq(_T_1680, UInt<3>(0h6)) node _T_1682 = leq(UInt<1>(0h0), uncommonBits_169) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = leq(uncommonBits_169, UInt<5>(0h1f)) node _T_1685 = and(_T_1683, _T_1684) node _uncommonBits_T_170 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_170 = bits(_uncommonBits_T_170, 4, 0) node _T_1686 = shr(io.in.a.bits.source, 5) node _T_1687 = eq(_T_1686, UInt<3>(0h5)) node _T_1688 = leq(UInt<1>(0h0), uncommonBits_170) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = leq(uncommonBits_170, UInt<5>(0h1f)) node _T_1691 = and(_T_1689, _T_1690) node _uncommonBits_T_171 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_171 = bits(_uncommonBits_T_171, 4, 0) node _T_1692 = shr(io.in.a.bits.source, 5) node _T_1693 = eq(_T_1692, UInt<3>(0h4)) node _T_1694 = leq(UInt<1>(0h0), uncommonBits_171) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = leq(uncommonBits_171, UInt<5>(0h1f)) node _T_1697 = and(_T_1695, _T_1696) node _uncommonBits_T_172 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_172 = bits(_uncommonBits_T_172, 4, 0) node _T_1698 = shr(io.in.a.bits.source, 5) node _T_1699 = eq(_T_1698, UInt<2>(0h3)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_172) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_172, UInt<5>(0h1f)) node _T_1703 = and(_T_1701, _T_1702) node _uncommonBits_T_173 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_173 = bits(_uncommonBits_T_173, 4, 0) node _T_1704 = shr(io.in.a.bits.source, 5) node _T_1705 = eq(_T_1704, UInt<2>(0h2)) node _T_1706 = leq(UInt<1>(0h0), uncommonBits_173) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = leq(uncommonBits_173, UInt<5>(0h1f)) node _T_1709 = and(_T_1707, _T_1708) node _uncommonBits_T_174 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_174 = bits(_uncommonBits_T_174, 4, 0) node _T_1710 = shr(io.in.a.bits.source, 5) node _T_1711 = eq(_T_1710, UInt<1>(0h1)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_174) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_174, UInt<5>(0h1f)) node _T_1715 = and(_T_1713, _T_1714) node _uncommonBits_T_175 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_175 = bits(_uncommonBits_T_175, 4, 0) node _T_1716 = shr(io.in.a.bits.source, 5) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) node _T_1718 = leq(UInt<1>(0h0), uncommonBits_175) node _T_1719 = and(_T_1717, _T_1718) node _T_1720 = leq(uncommonBits_175, UInt<5>(0h1f)) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1723 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1724 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1725 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1726 = or(_T_1589, _T_1595) node _T_1727 = or(_T_1726, _T_1601) node _T_1728 = or(_T_1727, _T_1607) node _T_1729 = or(_T_1728, _T_1613) node _T_1730 = or(_T_1729, _T_1619) node _T_1731 = or(_T_1730, _T_1625) node _T_1732 = or(_T_1731, _T_1631) node _T_1733 = or(_T_1732, _T_1637) node _T_1734 = or(_T_1733, _T_1643) node _T_1735 = or(_T_1734, _T_1649) node _T_1736 = or(_T_1735, _T_1655) node _T_1737 = or(_T_1736, _T_1661) node _T_1738 = or(_T_1737, _T_1667) node _T_1739 = or(_T_1738, _T_1673) node _T_1740 = or(_T_1739, _T_1679) node _T_1741 = or(_T_1740, _T_1685) node _T_1742 = or(_T_1741, _T_1691) node _T_1743 = or(_T_1742, _T_1697) node _T_1744 = or(_T_1743, _T_1703) node _T_1745 = or(_T_1744, _T_1709) node _T_1746 = or(_T_1745, _T_1715) node _T_1747 = or(_T_1746, _T_1721) node _T_1748 = or(_T_1747, _T_1722) node _T_1749 = or(_T_1748, _T_1723) node _T_1750 = or(_T_1749, _T_1724) node _T_1751 = or(_T_1750, _T_1725) node _T_1752 = and(_T_1588, _T_1751) node _T_1753 = or(UInt<1>(0h0), _T_1752) node _T_1754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1755 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = or(UInt<1>(0h0), _T_1756) node _T_1758 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1759 = cvt(_T_1758) node _T_1760 = and(_T_1759, asSInt(UInt<13>(0h1000))) node _T_1761 = asSInt(_T_1760) node _T_1762 = eq(_T_1761, asSInt(UInt<1>(0h0))) node _T_1763 = and(_T_1757, _T_1762) node _T_1764 = or(UInt<1>(0h0), _T_1763) node _T_1765 = and(_T_1753, _T_1764) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_31 node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(source_ok, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(is_aligned, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1775 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_34 node _T_1779 = not(mask) node _T_1780 = and(io.in.a.bits.mask, _T_1779) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_35 node _T_1785 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1785 : node _T_1786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1787 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1788 = and(_T_1786, _T_1787) node _T_1789 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_176 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_176 = bits(_uncommonBits_T_176, 1, 0) node _T_1790 = shr(io.in.a.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<7>(0h70)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_176) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_176, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_177 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_177 = bits(_uncommonBits_T_177, 1, 0) node _T_1796 = shr(io.in.a.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<7>(0h71)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_177) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_177, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_178 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_178 = bits(_uncommonBits_T_178, 1, 0) node _T_1802 = shr(io.in.a.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<7>(0h72)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_178) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_178, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_179 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_179 = bits(_uncommonBits_T_179, 1, 0) node _T_1808 = shr(io.in.a.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<7>(0h73)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_179) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_179, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_180 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_180 = bits(_uncommonBits_T_180, 1, 0) node _T_1814 = shr(io.in.a.bits.source, 2) node _T_1815 = eq(_T_1814, UInt<7>(0h7c)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_180) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_180, UInt<2>(0h3)) node _T_1819 = and(_T_1817, _T_1818) node _uncommonBits_T_181 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_181 = bits(_uncommonBits_T_181, 1, 0) node _T_1820 = shr(io.in.a.bits.source, 2) node _T_1821 = eq(_T_1820, UInt<7>(0h7b)) node _T_1822 = leq(UInt<1>(0h0), uncommonBits_181) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = leq(uncommonBits_181, UInt<2>(0h3)) node _T_1825 = and(_T_1823, _T_1824) node _uncommonBits_T_182 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_182 = bits(_uncommonBits_T_182, 4, 0) node _T_1826 = shr(io.in.a.bits.source, 5) node _T_1827 = eq(_T_1826, UInt<4>(0hd)) node _T_1828 = leq(UInt<1>(0h0), uncommonBits_182) node _T_1829 = and(_T_1827, _T_1828) node _T_1830 = leq(uncommonBits_182, UInt<5>(0h1f)) node _T_1831 = and(_T_1829, _T_1830) node _uncommonBits_T_183 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_183 = bits(_uncommonBits_T_183, 4, 0) node _T_1832 = shr(io.in.a.bits.source, 5) node _T_1833 = eq(_T_1832, UInt<4>(0hc)) node _T_1834 = leq(UInt<1>(0h0), uncommonBits_183) node _T_1835 = and(_T_1833, _T_1834) node _T_1836 = leq(uncommonBits_183, UInt<5>(0h1f)) node _T_1837 = and(_T_1835, _T_1836) node _uncommonBits_T_184 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_184 = bits(_uncommonBits_T_184, 4, 0) node _T_1838 = shr(io.in.a.bits.source, 5) node _T_1839 = eq(_T_1838, UInt<4>(0hb)) node _T_1840 = leq(UInt<1>(0h0), uncommonBits_184) node _T_1841 = and(_T_1839, _T_1840) node _T_1842 = leq(uncommonBits_184, UInt<5>(0h1f)) node _T_1843 = and(_T_1841, _T_1842) node _uncommonBits_T_185 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_185 = bits(_uncommonBits_T_185, 4, 0) node _T_1844 = shr(io.in.a.bits.source, 5) node _T_1845 = eq(_T_1844, UInt<4>(0ha)) node _T_1846 = leq(UInt<1>(0h0), uncommonBits_185) node _T_1847 = and(_T_1845, _T_1846) node _T_1848 = leq(uncommonBits_185, UInt<5>(0h1f)) node _T_1849 = and(_T_1847, _T_1848) node _uncommonBits_T_186 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_186 = bits(_uncommonBits_T_186, 4, 0) node _T_1850 = shr(io.in.a.bits.source, 5) node _T_1851 = eq(_T_1850, UInt<4>(0h9)) node _T_1852 = leq(UInt<1>(0h0), uncommonBits_186) node _T_1853 = and(_T_1851, _T_1852) node _T_1854 = leq(uncommonBits_186, UInt<5>(0h1f)) node _T_1855 = and(_T_1853, _T_1854) node _uncommonBits_T_187 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_187 = bits(_uncommonBits_T_187, 4, 0) node _T_1856 = shr(io.in.a.bits.source, 5) node _T_1857 = eq(_T_1856, UInt<4>(0h8)) node _T_1858 = leq(UInt<1>(0h0), uncommonBits_187) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = leq(uncommonBits_187, UInt<5>(0h1f)) node _T_1861 = and(_T_1859, _T_1860) node _uncommonBits_T_188 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_188 = bits(_uncommonBits_T_188, 1, 0) node _T_1862 = shr(io.in.a.bits.source, 2) node _T_1863 = eq(_T_1862, UInt<7>(0h7a)) node _T_1864 = leq(UInt<1>(0h0), uncommonBits_188) node _T_1865 = and(_T_1863, _T_1864) node _T_1866 = leq(uncommonBits_188, UInt<2>(0h3)) node _T_1867 = and(_T_1865, _T_1866) node _uncommonBits_T_189 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_189 = bits(_uncommonBits_T_189, 1, 0) node _T_1868 = shr(io.in.a.bits.source, 2) node _T_1869 = eq(_T_1868, UInt<7>(0h79)) node _T_1870 = leq(UInt<1>(0h0), uncommonBits_189) node _T_1871 = and(_T_1869, _T_1870) node _T_1872 = leq(uncommonBits_189, UInt<2>(0h3)) node _T_1873 = and(_T_1871, _T_1872) node _uncommonBits_T_190 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_190 = bits(_uncommonBits_T_190, 4, 0) node _T_1874 = shr(io.in.a.bits.source, 5) node _T_1875 = eq(_T_1874, UInt<3>(0h7)) node _T_1876 = leq(UInt<1>(0h0), uncommonBits_190) node _T_1877 = and(_T_1875, _T_1876) node _T_1878 = leq(uncommonBits_190, UInt<5>(0h1f)) node _T_1879 = and(_T_1877, _T_1878) node _uncommonBits_T_191 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_191 = bits(_uncommonBits_T_191, 4, 0) node _T_1880 = shr(io.in.a.bits.source, 5) node _T_1881 = eq(_T_1880, UInt<3>(0h6)) node _T_1882 = leq(UInt<1>(0h0), uncommonBits_191) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = leq(uncommonBits_191, UInt<5>(0h1f)) node _T_1885 = and(_T_1883, _T_1884) node _uncommonBits_T_192 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_192 = bits(_uncommonBits_T_192, 4, 0) node _T_1886 = shr(io.in.a.bits.source, 5) node _T_1887 = eq(_T_1886, UInt<3>(0h5)) node _T_1888 = leq(UInt<1>(0h0), uncommonBits_192) node _T_1889 = and(_T_1887, _T_1888) node _T_1890 = leq(uncommonBits_192, UInt<5>(0h1f)) node _T_1891 = and(_T_1889, _T_1890) node _uncommonBits_T_193 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_193 = bits(_uncommonBits_T_193, 4, 0) node _T_1892 = shr(io.in.a.bits.source, 5) node _T_1893 = eq(_T_1892, UInt<3>(0h4)) node _T_1894 = leq(UInt<1>(0h0), uncommonBits_193) node _T_1895 = and(_T_1893, _T_1894) node _T_1896 = leq(uncommonBits_193, UInt<5>(0h1f)) node _T_1897 = and(_T_1895, _T_1896) node _uncommonBits_T_194 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_194 = bits(_uncommonBits_T_194, 4, 0) node _T_1898 = shr(io.in.a.bits.source, 5) node _T_1899 = eq(_T_1898, UInt<2>(0h3)) node _T_1900 = leq(UInt<1>(0h0), uncommonBits_194) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = leq(uncommonBits_194, UInt<5>(0h1f)) node _T_1903 = and(_T_1901, _T_1902) node _uncommonBits_T_195 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_195 = bits(_uncommonBits_T_195, 4, 0) node _T_1904 = shr(io.in.a.bits.source, 5) node _T_1905 = eq(_T_1904, UInt<2>(0h2)) node _T_1906 = leq(UInt<1>(0h0), uncommonBits_195) node _T_1907 = and(_T_1905, _T_1906) node _T_1908 = leq(uncommonBits_195, UInt<5>(0h1f)) node _T_1909 = and(_T_1907, _T_1908) node _uncommonBits_T_196 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_196 = bits(_uncommonBits_T_196, 4, 0) node _T_1910 = shr(io.in.a.bits.source, 5) node _T_1911 = eq(_T_1910, UInt<1>(0h1)) node _T_1912 = leq(UInt<1>(0h0), uncommonBits_196) node _T_1913 = and(_T_1911, _T_1912) node _T_1914 = leq(uncommonBits_196, UInt<5>(0h1f)) node _T_1915 = and(_T_1913, _T_1914) node _uncommonBits_T_197 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_197 = bits(_uncommonBits_T_197, 4, 0) node _T_1916 = shr(io.in.a.bits.source, 5) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) node _T_1918 = leq(UInt<1>(0h0), uncommonBits_197) node _T_1919 = and(_T_1917, _T_1918) node _T_1920 = leq(uncommonBits_197, UInt<5>(0h1f)) node _T_1921 = and(_T_1919, _T_1920) node _T_1922 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1923 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_1924 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1925 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1926 = or(_T_1789, _T_1795) node _T_1927 = or(_T_1926, _T_1801) node _T_1928 = or(_T_1927, _T_1807) node _T_1929 = or(_T_1928, _T_1813) node _T_1930 = or(_T_1929, _T_1819) node _T_1931 = or(_T_1930, _T_1825) node _T_1932 = or(_T_1931, _T_1831) node _T_1933 = or(_T_1932, _T_1837) node _T_1934 = or(_T_1933, _T_1843) node _T_1935 = or(_T_1934, _T_1849) node _T_1936 = or(_T_1935, _T_1855) node _T_1937 = or(_T_1936, _T_1861) node _T_1938 = or(_T_1937, _T_1867) node _T_1939 = or(_T_1938, _T_1873) node _T_1940 = or(_T_1939, _T_1879) node _T_1941 = or(_T_1940, _T_1885) node _T_1942 = or(_T_1941, _T_1891) node _T_1943 = or(_T_1942, _T_1897) node _T_1944 = or(_T_1943, _T_1903) node _T_1945 = or(_T_1944, _T_1909) node _T_1946 = or(_T_1945, _T_1915) node _T_1947 = or(_T_1946, _T_1921) node _T_1948 = or(_T_1947, _T_1922) node _T_1949 = or(_T_1948, _T_1923) node _T_1950 = or(_T_1949, _T_1924) node _T_1951 = or(_T_1950, _T_1925) node _T_1952 = and(_T_1788, _T_1951) node _T_1953 = or(UInt<1>(0h0), _T_1952) node _T_1954 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1955 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1956 = cvt(_T_1955) node _T_1957 = and(_T_1956, asSInt(UInt<13>(0h1000))) node _T_1958 = asSInt(_T_1957) node _T_1959 = eq(_T_1958, asSInt(UInt<1>(0h0))) node _T_1960 = and(_T_1954, _T_1959) node _T_1961 = or(UInt<1>(0h0), _T_1960) node _T_1962 = and(_T_1953, _T_1961) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_36 node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(source_ok, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1969 = asUInt(reset) node _T_1970 = eq(_T_1969, UInt<1>(0h0)) when _T_1970 : node _T_1971 = eq(is_aligned, UInt<1>(0h0)) when _T_1971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1972 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(_T_1972, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1972, UInt<1>(0h1), "") : assert_39 node _T_1976 = eq(io.in.a.bits.mask, mask) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_40 node _T_1980 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1980 : node _T_1981 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1982 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1983 = and(_T_1981, _T_1982) node _T_1984 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_198 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_198 = bits(_uncommonBits_T_198, 1, 0) node _T_1985 = shr(io.in.a.bits.source, 2) node _T_1986 = eq(_T_1985, UInt<7>(0h70)) node _T_1987 = leq(UInt<1>(0h0), uncommonBits_198) node _T_1988 = and(_T_1986, _T_1987) node _T_1989 = leq(uncommonBits_198, UInt<2>(0h3)) node _T_1990 = and(_T_1988, _T_1989) node _uncommonBits_T_199 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_199 = bits(_uncommonBits_T_199, 1, 0) node _T_1991 = shr(io.in.a.bits.source, 2) node _T_1992 = eq(_T_1991, UInt<7>(0h71)) node _T_1993 = leq(UInt<1>(0h0), uncommonBits_199) node _T_1994 = and(_T_1992, _T_1993) node _T_1995 = leq(uncommonBits_199, UInt<2>(0h3)) node _T_1996 = and(_T_1994, _T_1995) node _uncommonBits_T_200 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_200 = bits(_uncommonBits_T_200, 1, 0) node _T_1997 = shr(io.in.a.bits.source, 2) node _T_1998 = eq(_T_1997, UInt<7>(0h72)) node _T_1999 = leq(UInt<1>(0h0), uncommonBits_200) node _T_2000 = and(_T_1998, _T_1999) node _T_2001 = leq(uncommonBits_200, UInt<2>(0h3)) node _T_2002 = and(_T_2000, _T_2001) node _uncommonBits_T_201 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_201 = bits(_uncommonBits_T_201, 1, 0) node _T_2003 = shr(io.in.a.bits.source, 2) node _T_2004 = eq(_T_2003, UInt<7>(0h73)) node _T_2005 = leq(UInt<1>(0h0), uncommonBits_201) node _T_2006 = and(_T_2004, _T_2005) node _T_2007 = leq(uncommonBits_201, UInt<2>(0h3)) node _T_2008 = and(_T_2006, _T_2007) node _uncommonBits_T_202 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_202 = bits(_uncommonBits_T_202, 1, 0) node _T_2009 = shr(io.in.a.bits.source, 2) node _T_2010 = eq(_T_2009, UInt<7>(0h7c)) node _T_2011 = leq(UInt<1>(0h0), uncommonBits_202) node _T_2012 = and(_T_2010, _T_2011) node _T_2013 = leq(uncommonBits_202, UInt<2>(0h3)) node _T_2014 = and(_T_2012, _T_2013) node _uncommonBits_T_203 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_203 = bits(_uncommonBits_T_203, 1, 0) node _T_2015 = shr(io.in.a.bits.source, 2) node _T_2016 = eq(_T_2015, UInt<7>(0h7b)) node _T_2017 = leq(UInt<1>(0h0), uncommonBits_203) node _T_2018 = and(_T_2016, _T_2017) node _T_2019 = leq(uncommonBits_203, UInt<2>(0h3)) node _T_2020 = and(_T_2018, _T_2019) node _uncommonBits_T_204 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_204 = bits(_uncommonBits_T_204, 4, 0) node _T_2021 = shr(io.in.a.bits.source, 5) node _T_2022 = eq(_T_2021, UInt<4>(0hd)) node _T_2023 = leq(UInt<1>(0h0), uncommonBits_204) node _T_2024 = and(_T_2022, _T_2023) node _T_2025 = leq(uncommonBits_204, UInt<5>(0h1f)) node _T_2026 = and(_T_2024, _T_2025) node _uncommonBits_T_205 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_205 = bits(_uncommonBits_T_205, 4, 0) node _T_2027 = shr(io.in.a.bits.source, 5) node _T_2028 = eq(_T_2027, UInt<4>(0hc)) node _T_2029 = leq(UInt<1>(0h0), uncommonBits_205) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = leq(uncommonBits_205, UInt<5>(0h1f)) node _T_2032 = and(_T_2030, _T_2031) node _uncommonBits_T_206 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_206 = bits(_uncommonBits_T_206, 4, 0) node _T_2033 = shr(io.in.a.bits.source, 5) node _T_2034 = eq(_T_2033, UInt<4>(0hb)) node _T_2035 = leq(UInt<1>(0h0), uncommonBits_206) node _T_2036 = and(_T_2034, _T_2035) node _T_2037 = leq(uncommonBits_206, UInt<5>(0h1f)) node _T_2038 = and(_T_2036, _T_2037) node _uncommonBits_T_207 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_207 = bits(_uncommonBits_T_207, 4, 0) node _T_2039 = shr(io.in.a.bits.source, 5) node _T_2040 = eq(_T_2039, UInt<4>(0ha)) node _T_2041 = leq(UInt<1>(0h0), uncommonBits_207) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = leq(uncommonBits_207, UInt<5>(0h1f)) node _T_2044 = and(_T_2042, _T_2043) node _uncommonBits_T_208 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_208 = bits(_uncommonBits_T_208, 4, 0) node _T_2045 = shr(io.in.a.bits.source, 5) node _T_2046 = eq(_T_2045, UInt<4>(0h9)) node _T_2047 = leq(UInt<1>(0h0), uncommonBits_208) node _T_2048 = and(_T_2046, _T_2047) node _T_2049 = leq(uncommonBits_208, UInt<5>(0h1f)) node _T_2050 = and(_T_2048, _T_2049) node _uncommonBits_T_209 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_209 = bits(_uncommonBits_T_209, 4, 0) node _T_2051 = shr(io.in.a.bits.source, 5) node _T_2052 = eq(_T_2051, UInt<4>(0h8)) node _T_2053 = leq(UInt<1>(0h0), uncommonBits_209) node _T_2054 = and(_T_2052, _T_2053) node _T_2055 = leq(uncommonBits_209, UInt<5>(0h1f)) node _T_2056 = and(_T_2054, _T_2055) node _uncommonBits_T_210 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_210 = bits(_uncommonBits_T_210, 1, 0) node _T_2057 = shr(io.in.a.bits.source, 2) node _T_2058 = eq(_T_2057, UInt<7>(0h7a)) node _T_2059 = leq(UInt<1>(0h0), uncommonBits_210) node _T_2060 = and(_T_2058, _T_2059) node _T_2061 = leq(uncommonBits_210, UInt<2>(0h3)) node _T_2062 = and(_T_2060, _T_2061) node _uncommonBits_T_211 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_211 = bits(_uncommonBits_T_211, 1, 0) node _T_2063 = shr(io.in.a.bits.source, 2) node _T_2064 = eq(_T_2063, UInt<7>(0h79)) node _T_2065 = leq(UInt<1>(0h0), uncommonBits_211) node _T_2066 = and(_T_2064, _T_2065) node _T_2067 = leq(uncommonBits_211, UInt<2>(0h3)) node _T_2068 = and(_T_2066, _T_2067) node _uncommonBits_T_212 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_212 = bits(_uncommonBits_T_212, 4, 0) node _T_2069 = shr(io.in.a.bits.source, 5) node _T_2070 = eq(_T_2069, UInt<3>(0h7)) node _T_2071 = leq(UInt<1>(0h0), uncommonBits_212) node _T_2072 = and(_T_2070, _T_2071) node _T_2073 = leq(uncommonBits_212, UInt<5>(0h1f)) node _T_2074 = and(_T_2072, _T_2073) node _uncommonBits_T_213 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_213 = bits(_uncommonBits_T_213, 4, 0) node _T_2075 = shr(io.in.a.bits.source, 5) node _T_2076 = eq(_T_2075, UInt<3>(0h6)) node _T_2077 = leq(UInt<1>(0h0), uncommonBits_213) node _T_2078 = and(_T_2076, _T_2077) node _T_2079 = leq(uncommonBits_213, UInt<5>(0h1f)) node _T_2080 = and(_T_2078, _T_2079) node _uncommonBits_T_214 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_214 = bits(_uncommonBits_T_214, 4, 0) node _T_2081 = shr(io.in.a.bits.source, 5) node _T_2082 = eq(_T_2081, UInt<3>(0h5)) node _T_2083 = leq(UInt<1>(0h0), uncommonBits_214) node _T_2084 = and(_T_2082, _T_2083) node _T_2085 = leq(uncommonBits_214, UInt<5>(0h1f)) node _T_2086 = and(_T_2084, _T_2085) node _uncommonBits_T_215 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_215 = bits(_uncommonBits_T_215, 4, 0) node _T_2087 = shr(io.in.a.bits.source, 5) node _T_2088 = eq(_T_2087, UInt<3>(0h4)) node _T_2089 = leq(UInt<1>(0h0), uncommonBits_215) node _T_2090 = and(_T_2088, _T_2089) node _T_2091 = leq(uncommonBits_215, UInt<5>(0h1f)) node _T_2092 = and(_T_2090, _T_2091) node _uncommonBits_T_216 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_216 = bits(_uncommonBits_T_216, 4, 0) node _T_2093 = shr(io.in.a.bits.source, 5) node _T_2094 = eq(_T_2093, UInt<2>(0h3)) node _T_2095 = leq(UInt<1>(0h0), uncommonBits_216) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = leq(uncommonBits_216, UInt<5>(0h1f)) node _T_2098 = and(_T_2096, _T_2097) node _uncommonBits_T_217 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_217 = bits(_uncommonBits_T_217, 4, 0) node _T_2099 = shr(io.in.a.bits.source, 5) node _T_2100 = eq(_T_2099, UInt<2>(0h2)) node _T_2101 = leq(UInt<1>(0h0), uncommonBits_217) node _T_2102 = and(_T_2100, _T_2101) node _T_2103 = leq(uncommonBits_217, UInt<5>(0h1f)) node _T_2104 = and(_T_2102, _T_2103) node _uncommonBits_T_218 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_218 = bits(_uncommonBits_T_218, 4, 0) node _T_2105 = shr(io.in.a.bits.source, 5) node _T_2106 = eq(_T_2105, UInt<1>(0h1)) node _T_2107 = leq(UInt<1>(0h0), uncommonBits_218) node _T_2108 = and(_T_2106, _T_2107) node _T_2109 = leq(uncommonBits_218, UInt<5>(0h1f)) node _T_2110 = and(_T_2108, _T_2109) node _uncommonBits_T_219 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_219 = bits(_uncommonBits_T_219, 4, 0) node _T_2111 = shr(io.in.a.bits.source, 5) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) node _T_2113 = leq(UInt<1>(0h0), uncommonBits_219) node _T_2114 = and(_T_2112, _T_2113) node _T_2115 = leq(uncommonBits_219, UInt<5>(0h1f)) node _T_2116 = and(_T_2114, _T_2115) node _T_2117 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2118 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_2119 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2120 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_2121 = or(_T_1984, _T_1990) node _T_2122 = or(_T_2121, _T_1996) node _T_2123 = or(_T_2122, _T_2002) node _T_2124 = or(_T_2123, _T_2008) node _T_2125 = or(_T_2124, _T_2014) node _T_2126 = or(_T_2125, _T_2020) node _T_2127 = or(_T_2126, _T_2026) node _T_2128 = or(_T_2127, _T_2032) node _T_2129 = or(_T_2128, _T_2038) node _T_2130 = or(_T_2129, _T_2044) node _T_2131 = or(_T_2130, _T_2050) node _T_2132 = or(_T_2131, _T_2056) node _T_2133 = or(_T_2132, _T_2062) node _T_2134 = or(_T_2133, _T_2068) node _T_2135 = or(_T_2134, _T_2074) node _T_2136 = or(_T_2135, _T_2080) node _T_2137 = or(_T_2136, _T_2086) node _T_2138 = or(_T_2137, _T_2092) node _T_2139 = or(_T_2138, _T_2098) node _T_2140 = or(_T_2139, _T_2104) node _T_2141 = or(_T_2140, _T_2110) node _T_2142 = or(_T_2141, _T_2116) node _T_2143 = or(_T_2142, _T_2117) node _T_2144 = or(_T_2143, _T_2118) node _T_2145 = or(_T_2144, _T_2119) node _T_2146 = or(_T_2145, _T_2120) node _T_2147 = and(_T_1983, _T_2146) node _T_2148 = or(UInt<1>(0h0), _T_2147) node _T_2149 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2150 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = and(_T_2149, _T_2154) node _T_2156 = or(UInt<1>(0h0), _T_2155) node _T_2157 = and(_T_2148, _T_2156) node _T_2158 = asUInt(reset) node _T_2159 = eq(_T_2158, UInt<1>(0h0)) when _T_2159 : node _T_2160 = eq(_T_2157, UInt<1>(0h0)) when _T_2160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_2157, UInt<1>(0h1), "") : assert_41 node _T_2161 = asUInt(reset) node _T_2162 = eq(_T_2161, UInt<1>(0h0)) when _T_2162 : node _T_2163 = eq(source_ok, UInt<1>(0h0)) when _T_2163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_2164 = asUInt(reset) node _T_2165 = eq(_T_2164, UInt<1>(0h0)) when _T_2165 : node _T_2166 = eq(is_aligned, UInt<1>(0h0)) when _T_2166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_2167 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_2168 = asUInt(reset) node _T_2169 = eq(_T_2168, UInt<1>(0h0)) when _T_2169 : node _T_2170 = eq(_T_2167, UInt<1>(0h0)) when _T_2170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_2167, UInt<1>(0h1), "") : assert_44 node _T_2171 = eq(io.in.a.bits.mask, mask) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_45 node _T_2175 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_2175 : node _T_2176 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2177 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2178 = and(_T_2176, _T_2177) node _T_2179 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_220 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_220 = bits(_uncommonBits_T_220, 1, 0) node _T_2180 = shr(io.in.a.bits.source, 2) node _T_2181 = eq(_T_2180, UInt<7>(0h70)) node _T_2182 = leq(UInt<1>(0h0), uncommonBits_220) node _T_2183 = and(_T_2181, _T_2182) node _T_2184 = leq(uncommonBits_220, UInt<2>(0h3)) node _T_2185 = and(_T_2183, _T_2184) node _uncommonBits_T_221 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_221 = bits(_uncommonBits_T_221, 1, 0) node _T_2186 = shr(io.in.a.bits.source, 2) node _T_2187 = eq(_T_2186, UInt<7>(0h71)) node _T_2188 = leq(UInt<1>(0h0), uncommonBits_221) node _T_2189 = and(_T_2187, _T_2188) node _T_2190 = leq(uncommonBits_221, UInt<2>(0h3)) node _T_2191 = and(_T_2189, _T_2190) node _uncommonBits_T_222 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_222 = bits(_uncommonBits_T_222, 1, 0) node _T_2192 = shr(io.in.a.bits.source, 2) node _T_2193 = eq(_T_2192, UInt<7>(0h72)) node _T_2194 = leq(UInt<1>(0h0), uncommonBits_222) node _T_2195 = and(_T_2193, _T_2194) node _T_2196 = leq(uncommonBits_222, UInt<2>(0h3)) node _T_2197 = and(_T_2195, _T_2196) node _uncommonBits_T_223 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_223 = bits(_uncommonBits_T_223, 1, 0) node _T_2198 = shr(io.in.a.bits.source, 2) node _T_2199 = eq(_T_2198, UInt<7>(0h73)) node _T_2200 = leq(UInt<1>(0h0), uncommonBits_223) node _T_2201 = and(_T_2199, _T_2200) node _T_2202 = leq(uncommonBits_223, UInt<2>(0h3)) node _T_2203 = and(_T_2201, _T_2202) node _uncommonBits_T_224 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_224 = bits(_uncommonBits_T_224, 1, 0) node _T_2204 = shr(io.in.a.bits.source, 2) node _T_2205 = eq(_T_2204, UInt<7>(0h7c)) node _T_2206 = leq(UInt<1>(0h0), uncommonBits_224) node _T_2207 = and(_T_2205, _T_2206) node _T_2208 = leq(uncommonBits_224, UInt<2>(0h3)) node _T_2209 = and(_T_2207, _T_2208) node _uncommonBits_T_225 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_225 = bits(_uncommonBits_T_225, 1, 0) node _T_2210 = shr(io.in.a.bits.source, 2) node _T_2211 = eq(_T_2210, UInt<7>(0h7b)) node _T_2212 = leq(UInt<1>(0h0), uncommonBits_225) node _T_2213 = and(_T_2211, _T_2212) node _T_2214 = leq(uncommonBits_225, UInt<2>(0h3)) node _T_2215 = and(_T_2213, _T_2214) node _uncommonBits_T_226 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_226 = bits(_uncommonBits_T_226, 4, 0) node _T_2216 = shr(io.in.a.bits.source, 5) node _T_2217 = eq(_T_2216, UInt<4>(0hd)) node _T_2218 = leq(UInt<1>(0h0), uncommonBits_226) node _T_2219 = and(_T_2217, _T_2218) node _T_2220 = leq(uncommonBits_226, UInt<5>(0h1f)) node _T_2221 = and(_T_2219, _T_2220) node _uncommonBits_T_227 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_227 = bits(_uncommonBits_T_227, 4, 0) node _T_2222 = shr(io.in.a.bits.source, 5) node _T_2223 = eq(_T_2222, UInt<4>(0hc)) node _T_2224 = leq(UInt<1>(0h0), uncommonBits_227) node _T_2225 = and(_T_2223, _T_2224) node _T_2226 = leq(uncommonBits_227, UInt<5>(0h1f)) node _T_2227 = and(_T_2225, _T_2226) node _uncommonBits_T_228 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_228 = bits(_uncommonBits_T_228, 4, 0) node _T_2228 = shr(io.in.a.bits.source, 5) node _T_2229 = eq(_T_2228, UInt<4>(0hb)) node _T_2230 = leq(UInt<1>(0h0), uncommonBits_228) node _T_2231 = and(_T_2229, _T_2230) node _T_2232 = leq(uncommonBits_228, UInt<5>(0h1f)) node _T_2233 = and(_T_2231, _T_2232) node _uncommonBits_T_229 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_229 = bits(_uncommonBits_T_229, 4, 0) node _T_2234 = shr(io.in.a.bits.source, 5) node _T_2235 = eq(_T_2234, UInt<4>(0ha)) node _T_2236 = leq(UInt<1>(0h0), uncommonBits_229) node _T_2237 = and(_T_2235, _T_2236) node _T_2238 = leq(uncommonBits_229, UInt<5>(0h1f)) node _T_2239 = and(_T_2237, _T_2238) node _uncommonBits_T_230 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_230 = bits(_uncommonBits_T_230, 4, 0) node _T_2240 = shr(io.in.a.bits.source, 5) node _T_2241 = eq(_T_2240, UInt<4>(0h9)) node _T_2242 = leq(UInt<1>(0h0), uncommonBits_230) node _T_2243 = and(_T_2241, _T_2242) node _T_2244 = leq(uncommonBits_230, UInt<5>(0h1f)) node _T_2245 = and(_T_2243, _T_2244) node _uncommonBits_T_231 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_231 = bits(_uncommonBits_T_231, 4, 0) node _T_2246 = shr(io.in.a.bits.source, 5) node _T_2247 = eq(_T_2246, UInt<4>(0h8)) node _T_2248 = leq(UInt<1>(0h0), uncommonBits_231) node _T_2249 = and(_T_2247, _T_2248) node _T_2250 = leq(uncommonBits_231, UInt<5>(0h1f)) node _T_2251 = and(_T_2249, _T_2250) node _uncommonBits_T_232 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_232 = bits(_uncommonBits_T_232, 1, 0) node _T_2252 = shr(io.in.a.bits.source, 2) node _T_2253 = eq(_T_2252, UInt<7>(0h7a)) node _T_2254 = leq(UInt<1>(0h0), uncommonBits_232) node _T_2255 = and(_T_2253, _T_2254) node _T_2256 = leq(uncommonBits_232, UInt<2>(0h3)) node _T_2257 = and(_T_2255, _T_2256) node _uncommonBits_T_233 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_233 = bits(_uncommonBits_T_233, 1, 0) node _T_2258 = shr(io.in.a.bits.source, 2) node _T_2259 = eq(_T_2258, UInt<7>(0h79)) node _T_2260 = leq(UInt<1>(0h0), uncommonBits_233) node _T_2261 = and(_T_2259, _T_2260) node _T_2262 = leq(uncommonBits_233, UInt<2>(0h3)) node _T_2263 = and(_T_2261, _T_2262) node _uncommonBits_T_234 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_234 = bits(_uncommonBits_T_234, 4, 0) node _T_2264 = shr(io.in.a.bits.source, 5) node _T_2265 = eq(_T_2264, UInt<3>(0h7)) node _T_2266 = leq(UInt<1>(0h0), uncommonBits_234) node _T_2267 = and(_T_2265, _T_2266) node _T_2268 = leq(uncommonBits_234, UInt<5>(0h1f)) node _T_2269 = and(_T_2267, _T_2268) node _uncommonBits_T_235 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_235 = bits(_uncommonBits_T_235, 4, 0) node _T_2270 = shr(io.in.a.bits.source, 5) node _T_2271 = eq(_T_2270, UInt<3>(0h6)) node _T_2272 = leq(UInt<1>(0h0), uncommonBits_235) node _T_2273 = and(_T_2271, _T_2272) node _T_2274 = leq(uncommonBits_235, UInt<5>(0h1f)) node _T_2275 = and(_T_2273, _T_2274) node _uncommonBits_T_236 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_236 = bits(_uncommonBits_T_236, 4, 0) node _T_2276 = shr(io.in.a.bits.source, 5) node _T_2277 = eq(_T_2276, UInt<3>(0h5)) node _T_2278 = leq(UInt<1>(0h0), uncommonBits_236) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = leq(uncommonBits_236, UInt<5>(0h1f)) node _T_2281 = and(_T_2279, _T_2280) node _uncommonBits_T_237 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_237 = bits(_uncommonBits_T_237, 4, 0) node _T_2282 = shr(io.in.a.bits.source, 5) node _T_2283 = eq(_T_2282, UInt<3>(0h4)) node _T_2284 = leq(UInt<1>(0h0), uncommonBits_237) node _T_2285 = and(_T_2283, _T_2284) node _T_2286 = leq(uncommonBits_237, UInt<5>(0h1f)) node _T_2287 = and(_T_2285, _T_2286) node _uncommonBits_T_238 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_238 = bits(_uncommonBits_T_238, 4, 0) node _T_2288 = shr(io.in.a.bits.source, 5) node _T_2289 = eq(_T_2288, UInt<2>(0h3)) node _T_2290 = leq(UInt<1>(0h0), uncommonBits_238) node _T_2291 = and(_T_2289, _T_2290) node _T_2292 = leq(uncommonBits_238, UInt<5>(0h1f)) node _T_2293 = and(_T_2291, _T_2292) node _uncommonBits_T_239 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_239 = bits(_uncommonBits_T_239, 4, 0) node _T_2294 = shr(io.in.a.bits.source, 5) node _T_2295 = eq(_T_2294, UInt<2>(0h2)) node _T_2296 = leq(UInt<1>(0h0), uncommonBits_239) node _T_2297 = and(_T_2295, _T_2296) node _T_2298 = leq(uncommonBits_239, UInt<5>(0h1f)) node _T_2299 = and(_T_2297, _T_2298) node _uncommonBits_T_240 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_240 = bits(_uncommonBits_T_240, 4, 0) node _T_2300 = shr(io.in.a.bits.source, 5) node _T_2301 = eq(_T_2300, UInt<1>(0h1)) node _T_2302 = leq(UInt<1>(0h0), uncommonBits_240) node _T_2303 = and(_T_2301, _T_2302) node _T_2304 = leq(uncommonBits_240, UInt<5>(0h1f)) node _T_2305 = and(_T_2303, _T_2304) node _uncommonBits_T_241 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_241 = bits(_uncommonBits_T_241, 4, 0) node _T_2306 = shr(io.in.a.bits.source, 5) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) node _T_2308 = leq(UInt<1>(0h0), uncommonBits_241) node _T_2309 = and(_T_2307, _T_2308) node _T_2310 = leq(uncommonBits_241, UInt<5>(0h1f)) node _T_2311 = and(_T_2309, _T_2310) node _T_2312 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2313 = eq(io.in.a.bits.source, UInt<9>(0h1e1)) node _T_2314 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2315 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_2316 = or(_T_2179, _T_2185) node _T_2317 = or(_T_2316, _T_2191) node _T_2318 = or(_T_2317, _T_2197) node _T_2319 = or(_T_2318, _T_2203) node _T_2320 = or(_T_2319, _T_2209) node _T_2321 = or(_T_2320, _T_2215) node _T_2322 = or(_T_2321, _T_2221) node _T_2323 = or(_T_2322, _T_2227) node _T_2324 = or(_T_2323, _T_2233) node _T_2325 = or(_T_2324, _T_2239) node _T_2326 = or(_T_2325, _T_2245) node _T_2327 = or(_T_2326, _T_2251) node _T_2328 = or(_T_2327, _T_2257) node _T_2329 = or(_T_2328, _T_2263) node _T_2330 = or(_T_2329, _T_2269) node _T_2331 = or(_T_2330, _T_2275) node _T_2332 = or(_T_2331, _T_2281) node _T_2333 = or(_T_2332, _T_2287) node _T_2334 = or(_T_2333, _T_2293) node _T_2335 = or(_T_2334, _T_2299) node _T_2336 = or(_T_2335, _T_2305) node _T_2337 = or(_T_2336, _T_2311) node _T_2338 = or(_T_2337, _T_2312) node _T_2339 = or(_T_2338, _T_2313) node _T_2340 = or(_T_2339, _T_2314) node _T_2341 = or(_T_2340, _T_2315) node _T_2342 = and(_T_2178, _T_2341) node _T_2343 = or(UInt<1>(0h0), _T_2342) node _T_2344 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2345 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2346 = cvt(_T_2345) node _T_2347 = and(_T_2346, asSInt(UInt<13>(0h1000))) node _T_2348 = asSInt(_T_2347) node _T_2349 = eq(_T_2348, asSInt(UInt<1>(0h0))) node _T_2350 = and(_T_2344, _T_2349) node _T_2351 = or(UInt<1>(0h0), _T_2350) node _T_2352 = and(_T_2343, _T_2351) node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(_T_2352, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2352, UInt<1>(0h1), "") : assert_46 node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(source_ok, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(is_aligned, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2362 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2363 = asUInt(reset) node _T_2364 = eq(_T_2363, UInt<1>(0h0)) when _T_2364 : node _T_2365 = eq(_T_2362, UInt<1>(0h0)) when _T_2365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2362, UInt<1>(0h1), "") : assert_49 node _T_2366 = eq(io.in.a.bits.mask, mask) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_50 node _T_2370 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2371 = asUInt(reset) node _T_2372 = eq(_T_2371, UInt<1>(0h0)) when _T_2372 : node _T_2373 = eq(_T_2370, UInt<1>(0h0)) when _T_2373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2370, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2374 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2375 = asUInt(reset) node _T_2376 = eq(_T_2375, UInt<1>(0h0)) when _T_2376 : node _T_2377 = eq(_T_2374, UInt<1>(0h0)) when _T_2377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2374, UInt<1>(0h1), "") : assert_52 node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 1, 0) node _source_ok_T_163 = shr(io.in.d.bits.source, 2) node _source_ok_T_164 = eq(_source_ok_T_163, UInt<7>(0h70)) node _source_ok_T_165 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_166 = and(_source_ok_T_164, _source_ok_T_165) node _source_ok_T_167 = leq(source_ok_uncommonBits_22, UInt<2>(0h3)) node _source_ok_T_168 = and(_source_ok_T_166, _source_ok_T_167) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 1, 0) node _source_ok_T_169 = shr(io.in.d.bits.source, 2) node _source_ok_T_170 = eq(_source_ok_T_169, UInt<7>(0h71)) node _source_ok_T_171 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_172 = and(_source_ok_T_170, _source_ok_T_171) node _source_ok_T_173 = leq(source_ok_uncommonBits_23, UInt<2>(0h3)) node _source_ok_T_174 = and(_source_ok_T_172, _source_ok_T_173) node _source_ok_uncommonBits_T_24 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_24 = bits(_source_ok_uncommonBits_T_24, 1, 0) node _source_ok_T_175 = shr(io.in.d.bits.source, 2) node _source_ok_T_176 = eq(_source_ok_T_175, UInt<7>(0h72)) node _source_ok_T_177 = leq(UInt<1>(0h0), source_ok_uncommonBits_24) node _source_ok_T_178 = and(_source_ok_T_176, _source_ok_T_177) node _source_ok_T_179 = leq(source_ok_uncommonBits_24, UInt<2>(0h3)) node _source_ok_T_180 = and(_source_ok_T_178, _source_ok_T_179) node _source_ok_uncommonBits_T_25 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_25 = bits(_source_ok_uncommonBits_T_25, 1, 0) node _source_ok_T_181 = shr(io.in.d.bits.source, 2) node _source_ok_T_182 = eq(_source_ok_T_181, UInt<7>(0h73)) node _source_ok_T_183 = leq(UInt<1>(0h0), source_ok_uncommonBits_25) node _source_ok_T_184 = and(_source_ok_T_182, _source_ok_T_183) node _source_ok_T_185 = leq(source_ok_uncommonBits_25, UInt<2>(0h3)) node _source_ok_T_186 = and(_source_ok_T_184, _source_ok_T_185) node _source_ok_uncommonBits_T_26 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_26 = bits(_source_ok_uncommonBits_T_26, 1, 0) node _source_ok_T_187 = shr(io.in.d.bits.source, 2) node _source_ok_T_188 = eq(_source_ok_T_187, UInt<7>(0h7c)) node _source_ok_T_189 = leq(UInt<1>(0h0), source_ok_uncommonBits_26) node _source_ok_T_190 = and(_source_ok_T_188, _source_ok_T_189) node _source_ok_T_191 = leq(source_ok_uncommonBits_26, UInt<2>(0h3)) node _source_ok_T_192 = and(_source_ok_T_190, _source_ok_T_191) node _source_ok_uncommonBits_T_27 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_27 = bits(_source_ok_uncommonBits_T_27, 1, 0) node _source_ok_T_193 = shr(io.in.d.bits.source, 2) node _source_ok_T_194 = eq(_source_ok_T_193, UInt<7>(0h7b)) node _source_ok_T_195 = leq(UInt<1>(0h0), source_ok_uncommonBits_27) node _source_ok_T_196 = and(_source_ok_T_194, _source_ok_T_195) node _source_ok_T_197 = leq(source_ok_uncommonBits_27, UInt<2>(0h3)) node _source_ok_T_198 = and(_source_ok_T_196, _source_ok_T_197) node _source_ok_uncommonBits_T_28 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_28 = bits(_source_ok_uncommonBits_T_28, 4, 0) node _source_ok_T_199 = shr(io.in.d.bits.source, 5) node _source_ok_T_200 = eq(_source_ok_T_199, UInt<4>(0hd)) node _source_ok_T_201 = leq(UInt<1>(0h0), source_ok_uncommonBits_28) node _source_ok_T_202 = and(_source_ok_T_200, _source_ok_T_201) node _source_ok_T_203 = leq(source_ok_uncommonBits_28, UInt<5>(0h1f)) node _source_ok_T_204 = and(_source_ok_T_202, _source_ok_T_203) node _source_ok_uncommonBits_T_29 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_29 = bits(_source_ok_uncommonBits_T_29, 4, 0) node _source_ok_T_205 = shr(io.in.d.bits.source, 5) node _source_ok_T_206 = eq(_source_ok_T_205, UInt<4>(0hc)) node _source_ok_T_207 = leq(UInt<1>(0h0), source_ok_uncommonBits_29) node _source_ok_T_208 = and(_source_ok_T_206, _source_ok_T_207) node _source_ok_T_209 = leq(source_ok_uncommonBits_29, UInt<5>(0h1f)) node _source_ok_T_210 = and(_source_ok_T_208, _source_ok_T_209) node _source_ok_uncommonBits_T_30 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_30 = bits(_source_ok_uncommonBits_T_30, 4, 0) node _source_ok_T_211 = shr(io.in.d.bits.source, 5) node _source_ok_T_212 = eq(_source_ok_T_211, UInt<4>(0hb)) node _source_ok_T_213 = leq(UInt<1>(0h0), source_ok_uncommonBits_30) node _source_ok_T_214 = and(_source_ok_T_212, _source_ok_T_213) node _source_ok_T_215 = leq(source_ok_uncommonBits_30, UInt<5>(0h1f)) node _source_ok_T_216 = and(_source_ok_T_214, _source_ok_T_215) node _source_ok_uncommonBits_T_31 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_31 = bits(_source_ok_uncommonBits_T_31, 4, 0) node _source_ok_T_217 = shr(io.in.d.bits.source, 5) node _source_ok_T_218 = eq(_source_ok_T_217, UInt<4>(0ha)) node _source_ok_T_219 = leq(UInt<1>(0h0), source_ok_uncommonBits_31) node _source_ok_T_220 = and(_source_ok_T_218, _source_ok_T_219) node _source_ok_T_221 = leq(source_ok_uncommonBits_31, UInt<5>(0h1f)) node _source_ok_T_222 = and(_source_ok_T_220, _source_ok_T_221) node _source_ok_uncommonBits_T_32 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_32 = bits(_source_ok_uncommonBits_T_32, 4, 0) node _source_ok_T_223 = shr(io.in.d.bits.source, 5) node _source_ok_T_224 = eq(_source_ok_T_223, UInt<4>(0h9)) node _source_ok_T_225 = leq(UInt<1>(0h0), source_ok_uncommonBits_32) node _source_ok_T_226 = and(_source_ok_T_224, _source_ok_T_225) node _source_ok_T_227 = leq(source_ok_uncommonBits_32, UInt<5>(0h1f)) node _source_ok_T_228 = and(_source_ok_T_226, _source_ok_T_227) node _source_ok_uncommonBits_T_33 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_33 = bits(_source_ok_uncommonBits_T_33, 4, 0) node _source_ok_T_229 = shr(io.in.d.bits.source, 5) node _source_ok_T_230 = eq(_source_ok_T_229, UInt<4>(0h8)) node _source_ok_T_231 = leq(UInt<1>(0h0), source_ok_uncommonBits_33) node _source_ok_T_232 = and(_source_ok_T_230, _source_ok_T_231) node _source_ok_T_233 = leq(source_ok_uncommonBits_33, UInt<5>(0h1f)) node _source_ok_T_234 = and(_source_ok_T_232, _source_ok_T_233) node _source_ok_uncommonBits_T_34 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_34 = bits(_source_ok_uncommonBits_T_34, 1, 0) node _source_ok_T_235 = shr(io.in.d.bits.source, 2) node _source_ok_T_236 = eq(_source_ok_T_235, UInt<7>(0h7a)) node _source_ok_T_237 = leq(UInt<1>(0h0), source_ok_uncommonBits_34) node _source_ok_T_238 = and(_source_ok_T_236, _source_ok_T_237) node _source_ok_T_239 = leq(source_ok_uncommonBits_34, UInt<2>(0h3)) node _source_ok_T_240 = and(_source_ok_T_238, _source_ok_T_239) node _source_ok_uncommonBits_T_35 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_35 = bits(_source_ok_uncommonBits_T_35, 1, 0) node _source_ok_T_241 = shr(io.in.d.bits.source, 2) node _source_ok_T_242 = eq(_source_ok_T_241, UInt<7>(0h79)) node _source_ok_T_243 = leq(UInt<1>(0h0), source_ok_uncommonBits_35) node _source_ok_T_244 = and(_source_ok_T_242, _source_ok_T_243) node _source_ok_T_245 = leq(source_ok_uncommonBits_35, UInt<2>(0h3)) node _source_ok_T_246 = and(_source_ok_T_244, _source_ok_T_245) node _source_ok_uncommonBits_T_36 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_36 = bits(_source_ok_uncommonBits_T_36, 4, 0) node _source_ok_T_247 = shr(io.in.d.bits.source, 5) node _source_ok_T_248 = eq(_source_ok_T_247, UInt<3>(0h7)) node _source_ok_T_249 = leq(UInt<1>(0h0), source_ok_uncommonBits_36) node _source_ok_T_250 = and(_source_ok_T_248, _source_ok_T_249) node _source_ok_T_251 = leq(source_ok_uncommonBits_36, UInt<5>(0h1f)) node _source_ok_T_252 = and(_source_ok_T_250, _source_ok_T_251) node _source_ok_uncommonBits_T_37 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_37 = bits(_source_ok_uncommonBits_T_37, 4, 0) node _source_ok_T_253 = shr(io.in.d.bits.source, 5) node _source_ok_T_254 = eq(_source_ok_T_253, UInt<3>(0h6)) node _source_ok_T_255 = leq(UInt<1>(0h0), source_ok_uncommonBits_37) node _source_ok_T_256 = and(_source_ok_T_254, _source_ok_T_255) node _source_ok_T_257 = leq(source_ok_uncommonBits_37, UInt<5>(0h1f)) node _source_ok_T_258 = and(_source_ok_T_256, _source_ok_T_257) node _source_ok_uncommonBits_T_38 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_38 = bits(_source_ok_uncommonBits_T_38, 4, 0) node _source_ok_T_259 = shr(io.in.d.bits.source, 5) node _source_ok_T_260 = eq(_source_ok_T_259, UInt<3>(0h5)) node _source_ok_T_261 = leq(UInt<1>(0h0), source_ok_uncommonBits_38) node _source_ok_T_262 = and(_source_ok_T_260, _source_ok_T_261) node _source_ok_T_263 = leq(source_ok_uncommonBits_38, UInt<5>(0h1f)) node _source_ok_T_264 = and(_source_ok_T_262, _source_ok_T_263) node _source_ok_uncommonBits_T_39 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_39 = bits(_source_ok_uncommonBits_T_39, 4, 0) node _source_ok_T_265 = shr(io.in.d.bits.source, 5) node _source_ok_T_266 = eq(_source_ok_T_265, UInt<3>(0h4)) node _source_ok_T_267 = leq(UInt<1>(0h0), source_ok_uncommonBits_39) node _source_ok_T_268 = and(_source_ok_T_266, _source_ok_T_267) node _source_ok_T_269 = leq(source_ok_uncommonBits_39, UInt<5>(0h1f)) node _source_ok_T_270 = and(_source_ok_T_268, _source_ok_T_269) node _source_ok_uncommonBits_T_40 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_40 = bits(_source_ok_uncommonBits_T_40, 4, 0) node _source_ok_T_271 = shr(io.in.d.bits.source, 5) node _source_ok_T_272 = eq(_source_ok_T_271, UInt<2>(0h3)) node _source_ok_T_273 = leq(UInt<1>(0h0), source_ok_uncommonBits_40) node _source_ok_T_274 = and(_source_ok_T_272, _source_ok_T_273) node _source_ok_T_275 = leq(source_ok_uncommonBits_40, UInt<5>(0h1f)) node _source_ok_T_276 = and(_source_ok_T_274, _source_ok_T_275) node _source_ok_uncommonBits_T_41 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_41 = bits(_source_ok_uncommonBits_T_41, 4, 0) node _source_ok_T_277 = shr(io.in.d.bits.source, 5) node _source_ok_T_278 = eq(_source_ok_T_277, UInt<2>(0h2)) node _source_ok_T_279 = leq(UInt<1>(0h0), source_ok_uncommonBits_41) node _source_ok_T_280 = and(_source_ok_T_278, _source_ok_T_279) node _source_ok_T_281 = leq(source_ok_uncommonBits_41, UInt<5>(0h1f)) node _source_ok_T_282 = and(_source_ok_T_280, _source_ok_T_281) node _source_ok_uncommonBits_T_42 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_42 = bits(_source_ok_uncommonBits_T_42, 4, 0) node _source_ok_T_283 = shr(io.in.d.bits.source, 5) node _source_ok_T_284 = eq(_source_ok_T_283, UInt<1>(0h1)) node _source_ok_T_285 = leq(UInt<1>(0h0), source_ok_uncommonBits_42) node _source_ok_T_286 = and(_source_ok_T_284, _source_ok_T_285) node _source_ok_T_287 = leq(source_ok_uncommonBits_42, UInt<5>(0h1f)) node _source_ok_T_288 = and(_source_ok_T_286, _source_ok_T_287) node _source_ok_uncommonBits_T_43 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_43 = bits(_source_ok_uncommonBits_T_43, 4, 0) node _source_ok_T_289 = shr(io.in.d.bits.source, 5) node _source_ok_T_290 = eq(_source_ok_T_289, UInt<1>(0h0)) node _source_ok_T_291 = leq(UInt<1>(0h0), source_ok_uncommonBits_43) node _source_ok_T_292 = and(_source_ok_T_290, _source_ok_T_291) node _source_ok_T_293 = leq(source_ok_uncommonBits_43, UInt<5>(0h1f)) node _source_ok_T_294 = and(_source_ok_T_292, _source_ok_T_293) node _source_ok_T_295 = eq(io.in.d.bits.source, UInt<9>(0h1e0)) node _source_ok_T_296 = eq(io.in.d.bits.source, UInt<9>(0h1e1)) node _source_ok_T_297 = eq(io.in.d.bits.source, UInt<9>(0h1e2)) node _source_ok_T_298 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[27] connect _source_ok_WIRE_1[0], _source_ok_T_162 connect _source_ok_WIRE_1[1], _source_ok_T_168 connect _source_ok_WIRE_1[2], _source_ok_T_174 connect _source_ok_WIRE_1[3], _source_ok_T_180 connect _source_ok_WIRE_1[4], _source_ok_T_186 connect _source_ok_WIRE_1[5], _source_ok_T_192 connect _source_ok_WIRE_1[6], _source_ok_T_198 connect _source_ok_WIRE_1[7], _source_ok_T_204 connect _source_ok_WIRE_1[8], _source_ok_T_210 connect _source_ok_WIRE_1[9], _source_ok_T_216 connect _source_ok_WIRE_1[10], _source_ok_T_222 connect _source_ok_WIRE_1[11], _source_ok_T_228 connect _source_ok_WIRE_1[12], _source_ok_T_234 connect _source_ok_WIRE_1[13], _source_ok_T_240 connect _source_ok_WIRE_1[14], _source_ok_T_246 connect _source_ok_WIRE_1[15], _source_ok_T_252 connect _source_ok_WIRE_1[16], _source_ok_T_258 connect _source_ok_WIRE_1[17], _source_ok_T_264 connect _source_ok_WIRE_1[18], _source_ok_T_270 connect _source_ok_WIRE_1[19], _source_ok_T_276 connect _source_ok_WIRE_1[20], _source_ok_T_282 connect _source_ok_WIRE_1[21], _source_ok_T_288 connect _source_ok_WIRE_1[22], _source_ok_T_294 connect _source_ok_WIRE_1[23], _source_ok_T_295 connect _source_ok_WIRE_1[24], _source_ok_T_296 connect _source_ok_WIRE_1[25], _source_ok_T_297 connect _source_ok_WIRE_1[26], _source_ok_T_298 node _source_ok_T_299 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_300 = or(_source_ok_T_299, _source_ok_WIRE_1[2]) node _source_ok_T_301 = or(_source_ok_T_300, _source_ok_WIRE_1[3]) node _source_ok_T_302 = or(_source_ok_T_301, _source_ok_WIRE_1[4]) node _source_ok_T_303 = or(_source_ok_T_302, _source_ok_WIRE_1[5]) node _source_ok_T_304 = or(_source_ok_T_303, _source_ok_WIRE_1[6]) node _source_ok_T_305 = or(_source_ok_T_304, _source_ok_WIRE_1[7]) node _source_ok_T_306 = or(_source_ok_T_305, _source_ok_WIRE_1[8]) node _source_ok_T_307 = or(_source_ok_T_306, _source_ok_WIRE_1[9]) node _source_ok_T_308 = or(_source_ok_T_307, _source_ok_WIRE_1[10]) node _source_ok_T_309 = or(_source_ok_T_308, _source_ok_WIRE_1[11]) node _source_ok_T_310 = or(_source_ok_T_309, _source_ok_WIRE_1[12]) node _source_ok_T_311 = or(_source_ok_T_310, _source_ok_WIRE_1[13]) node _source_ok_T_312 = or(_source_ok_T_311, _source_ok_WIRE_1[14]) node _source_ok_T_313 = or(_source_ok_T_312, _source_ok_WIRE_1[15]) node _source_ok_T_314 = or(_source_ok_T_313, _source_ok_WIRE_1[16]) node _source_ok_T_315 = or(_source_ok_T_314, _source_ok_WIRE_1[17]) node _source_ok_T_316 = or(_source_ok_T_315, _source_ok_WIRE_1[18]) node _source_ok_T_317 = or(_source_ok_T_316, _source_ok_WIRE_1[19]) node _source_ok_T_318 = or(_source_ok_T_317, _source_ok_WIRE_1[20]) node _source_ok_T_319 = or(_source_ok_T_318, _source_ok_WIRE_1[21]) node _source_ok_T_320 = or(_source_ok_T_319, _source_ok_WIRE_1[22]) node _source_ok_T_321 = or(_source_ok_T_320, _source_ok_WIRE_1[23]) node _source_ok_T_322 = or(_source_ok_T_321, _source_ok_WIRE_1[24]) node _source_ok_T_323 = or(_source_ok_T_322, _source_ok_WIRE_1[25]) node source_ok_1 = or(_source_ok_T_323, _source_ok_WIRE_1[26]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2378 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2378 : node _T_2379 = asUInt(reset) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) when _T_2380 : node _T_2381 = eq(source_ok_1, UInt<1>(0h0)) when _T_2381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2382 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2383 = asUInt(reset) node _T_2384 = eq(_T_2383, UInt<1>(0h0)) when _T_2384 : node _T_2385 = eq(_T_2382, UInt<1>(0h0)) when _T_2385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2382, UInt<1>(0h1), "") : assert_54 node _T_2386 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2387 = asUInt(reset) node _T_2388 = eq(_T_2387, UInt<1>(0h0)) when _T_2388 : node _T_2389 = eq(_T_2386, UInt<1>(0h0)) when _T_2389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2386, UInt<1>(0h1), "") : assert_55 node _T_2390 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2391 = asUInt(reset) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) when _T_2392 : node _T_2393 = eq(_T_2390, UInt<1>(0h0)) when _T_2393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2390, UInt<1>(0h1), "") : assert_56 node _T_2394 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2395 = asUInt(reset) node _T_2396 = eq(_T_2395, UInt<1>(0h0)) when _T_2396 : node _T_2397 = eq(_T_2394, UInt<1>(0h0)) when _T_2397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2394, UInt<1>(0h1), "") : assert_57 node _T_2398 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2398 : node _T_2399 = asUInt(reset) node _T_2400 = eq(_T_2399, UInt<1>(0h0)) when _T_2400 : node _T_2401 = eq(source_ok_1, UInt<1>(0h0)) when _T_2401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2402 = asUInt(reset) node _T_2403 = eq(_T_2402, UInt<1>(0h0)) when _T_2403 : node _T_2404 = eq(sink_ok, UInt<1>(0h0)) when _T_2404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_60 node _T_2409 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_61 node _T_2413 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2414 = asUInt(reset) node _T_2415 = eq(_T_2414, UInt<1>(0h0)) when _T_2415 : node _T_2416 = eq(_T_2413, UInt<1>(0h0)) when _T_2416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2413, UInt<1>(0h1), "") : assert_62 node _T_2417 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(_T_2417, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2417, UInt<1>(0h1), "") : assert_63 node _T_2421 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2422 = or(UInt<1>(0h0), _T_2421) node _T_2423 = asUInt(reset) node _T_2424 = eq(_T_2423, UInt<1>(0h0)) when _T_2424 : node _T_2425 = eq(_T_2422, UInt<1>(0h0)) when _T_2425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2422, UInt<1>(0h1), "") : assert_64 node _T_2426 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2426 : node _T_2427 = asUInt(reset) node _T_2428 = eq(_T_2427, UInt<1>(0h0)) when _T_2428 : node _T_2429 = eq(source_ok_1, UInt<1>(0h0)) when _T_2429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(sink_ok, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2433 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_67 node _T_2437 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2438 = asUInt(reset) node _T_2439 = eq(_T_2438, UInt<1>(0h0)) when _T_2439 : node _T_2440 = eq(_T_2437, UInt<1>(0h0)) when _T_2440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2437, UInt<1>(0h1), "") : assert_68 node _T_2441 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_69 node _T_2445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2446 = or(_T_2445, io.in.d.bits.corrupt) node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(_T_2446, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2446, UInt<1>(0h1), "") : assert_70 node _T_2450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2451 = or(UInt<1>(0h0), _T_2450) node _T_2452 = asUInt(reset) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) when _T_2453 : node _T_2454 = eq(_T_2451, UInt<1>(0h0)) when _T_2454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2451, UInt<1>(0h1), "") : assert_71 node _T_2455 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2455 : node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(source_ok_1, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_73 node _T_2463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_74 node _T_2467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2468 = or(UInt<1>(0h0), _T_2467) node _T_2469 = asUInt(reset) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) when _T_2470 : node _T_2471 = eq(_T_2468, UInt<1>(0h0)) when _T_2471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2468, UInt<1>(0h1), "") : assert_75 node _T_2472 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2472 : node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(source_ok_1, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2477 = asUInt(reset) node _T_2478 = eq(_T_2477, UInt<1>(0h0)) when _T_2478 : node _T_2479 = eq(_T_2476, UInt<1>(0h0)) when _T_2479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2476, UInt<1>(0h1), "") : assert_77 node _T_2480 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2481 = or(_T_2480, io.in.d.bits.corrupt) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_78 node _T_2485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2486 = or(UInt<1>(0h0), _T_2485) node _T_2487 = asUInt(reset) node _T_2488 = eq(_T_2487, UInt<1>(0h0)) when _T_2488 : node _T_2489 = eq(_T_2486, UInt<1>(0h0)) when _T_2489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2486, UInt<1>(0h1), "") : assert_79 node _T_2490 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2490 : node _T_2491 = asUInt(reset) node _T_2492 = eq(_T_2491, UInt<1>(0h0)) when _T_2492 : node _T_2493 = eq(source_ok_1, UInt<1>(0h0)) when _T_2493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2494 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2495 = asUInt(reset) node _T_2496 = eq(_T_2495, UInt<1>(0h0)) when _T_2496 : node _T_2497 = eq(_T_2494, UInt<1>(0h0)) when _T_2497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2494, UInt<1>(0h1), "") : assert_81 node _T_2498 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2499 = asUInt(reset) node _T_2500 = eq(_T_2499, UInt<1>(0h0)) when _T_2500 : node _T_2501 = eq(_T_2498, UInt<1>(0h0)) when _T_2501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2498, UInt<1>(0h1), "") : assert_82 node _T_2502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2503 = or(UInt<1>(0h0), _T_2502) node _T_2504 = asUInt(reset) node _T_2505 = eq(_T_2504, UInt<1>(0h0)) when _T_2505 : node _T_2506 = eq(_T_2503, UInt<1>(0h0)) when _T_2506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2503, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2507 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2508 = asUInt(reset) node _T_2509 = eq(_T_2508, UInt<1>(0h0)) when _T_2509 : node _T_2510 = eq(_T_2507, UInt<1>(0h0)) when _T_2510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2507, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2511 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2512 = asUInt(reset) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) when _T_2513 : node _T_2514 = eq(_T_2511, UInt<1>(0h0)) when _T_2514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2511, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2515 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2519 = eq(a_first, UInt<1>(0h0)) node _T_2520 = and(io.in.a.valid, _T_2519) when _T_2520 : node _T_2521 = eq(io.in.a.bits.opcode, opcode) node _T_2522 = asUInt(reset) node _T_2523 = eq(_T_2522, UInt<1>(0h0)) when _T_2523 : node _T_2524 = eq(_T_2521, UInt<1>(0h0)) when _T_2524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2521, UInt<1>(0h1), "") : assert_87 node _T_2525 = eq(io.in.a.bits.param, param) node _T_2526 = asUInt(reset) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) when _T_2527 : node _T_2528 = eq(_T_2525, UInt<1>(0h0)) when _T_2528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2525, UInt<1>(0h1), "") : assert_88 node _T_2529 = eq(io.in.a.bits.size, size) node _T_2530 = asUInt(reset) node _T_2531 = eq(_T_2530, UInt<1>(0h0)) when _T_2531 : node _T_2532 = eq(_T_2529, UInt<1>(0h0)) when _T_2532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2529, UInt<1>(0h1), "") : assert_89 node _T_2533 = eq(io.in.a.bits.source, source) node _T_2534 = asUInt(reset) node _T_2535 = eq(_T_2534, UInt<1>(0h0)) when _T_2535 : node _T_2536 = eq(_T_2533, UInt<1>(0h0)) when _T_2536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2533, UInt<1>(0h1), "") : assert_90 node _T_2537 = eq(io.in.a.bits.address, address) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_91 node _T_2541 = and(io.in.a.ready, io.in.a.valid) node _T_2542 = and(_T_2541, a_first) when _T_2542 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2543 = eq(d_first, UInt<1>(0h0)) node _T_2544 = and(io.in.d.valid, _T_2543) when _T_2544 : node _T_2545 = eq(io.in.d.bits.opcode, opcode_1) node _T_2546 = asUInt(reset) node _T_2547 = eq(_T_2546, UInt<1>(0h0)) when _T_2547 : node _T_2548 = eq(_T_2545, UInt<1>(0h0)) when _T_2548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2545, UInt<1>(0h1), "") : assert_92 node _T_2549 = eq(io.in.d.bits.param, param_1) node _T_2550 = asUInt(reset) node _T_2551 = eq(_T_2550, UInt<1>(0h0)) when _T_2551 : node _T_2552 = eq(_T_2549, UInt<1>(0h0)) when _T_2552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2549, UInt<1>(0h1), "") : assert_93 node _T_2553 = eq(io.in.d.bits.size, size_1) node _T_2554 = asUInt(reset) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) when _T_2555 : node _T_2556 = eq(_T_2553, UInt<1>(0h0)) when _T_2556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2553, UInt<1>(0h1), "") : assert_94 node _T_2557 = eq(io.in.d.bits.source, source_1) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_95 node _T_2561 = eq(io.in.d.bits.sink, sink) node _T_2562 = asUInt(reset) node _T_2563 = eq(_T_2562, UInt<1>(0h0)) when _T_2563 : node _T_2564 = eq(_T_2561, UInt<1>(0h0)) when _T_2564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2561, UInt<1>(0h1), "") : assert_96 node _T_2565 = eq(io.in.d.bits.denied, denied) node _T_2566 = asUInt(reset) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) when _T_2567 : node _T_2568 = eq(_T_2565, UInt<1>(0h0)) when _T_2568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2565, UInt<1>(0h1), "") : assert_97 node _T_2569 = and(io.in.d.ready, io.in.d.valid) node _T_2570 = and(_T_2569, d_first) when _T_2570 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<2052>, clock, reset, UInt<2052>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<2052> connect a_sizes_set, UInt<2052>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2571 = and(io.in.a.valid, a_first_1) node _T_2572 = and(_T_2571, UInt<1>(0h1)) when _T_2572 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2573 = and(io.in.a.ready, io.in.a.valid) node _T_2574 = and(_T_2573, a_first_1) node _T_2575 = and(_T_2574, UInt<1>(0h1)) when _T_2575 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2576 = dshr(inflight, io.in.a.bits.source) node _T_2577 = bits(_T_2576, 0, 0) node _T_2578 = eq(_T_2577, UInt<1>(0h0)) node _T_2579 = asUInt(reset) node _T_2580 = eq(_T_2579, UInt<1>(0h0)) when _T_2580 : node _T_2581 = eq(_T_2578, UInt<1>(0h0)) when _T_2581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2578, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<2052> connect d_sizes_clr, UInt<2052>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2582 = and(io.in.d.valid, d_first_1) node _T_2583 = and(_T_2582, UInt<1>(0h1)) node _T_2584 = eq(d_release_ack, UInt<1>(0h0)) node _T_2585 = and(_T_2583, _T_2584) when _T_2585 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2586 = and(io.in.d.ready, io.in.d.valid) node _T_2587 = and(_T_2586, d_first_1) node _T_2588 = and(_T_2587, UInt<1>(0h1)) node _T_2589 = eq(d_release_ack, UInt<1>(0h0)) node _T_2590 = and(_T_2588, _T_2589) when _T_2590 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2591 = and(io.in.d.valid, d_first_1) node _T_2592 = and(_T_2591, UInt<1>(0h1)) node _T_2593 = eq(d_release_ack, UInt<1>(0h0)) node _T_2594 = and(_T_2592, _T_2593) when _T_2594 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2595 = dshr(inflight, io.in.d.bits.source) node _T_2596 = bits(_T_2595, 0, 0) node _T_2597 = or(_T_2596, same_cycle_resp) node _T_2598 = asUInt(reset) node _T_2599 = eq(_T_2598, UInt<1>(0h0)) when _T_2599 : node _T_2600 = eq(_T_2597, UInt<1>(0h0)) when _T_2600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2597, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2601 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2602 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2603 = or(_T_2601, _T_2602) node _T_2604 = asUInt(reset) node _T_2605 = eq(_T_2604, UInt<1>(0h0)) when _T_2605 : node _T_2606 = eq(_T_2603, UInt<1>(0h0)) when _T_2606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2603, UInt<1>(0h1), "") : assert_100 node _T_2607 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2608 = asUInt(reset) node _T_2609 = eq(_T_2608, UInt<1>(0h0)) when _T_2609 : node _T_2610 = eq(_T_2607, UInt<1>(0h0)) when _T_2610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2607, UInt<1>(0h1), "") : assert_101 else : node _T_2611 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2612 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2613 = or(_T_2611, _T_2612) node _T_2614 = asUInt(reset) node _T_2615 = eq(_T_2614, UInt<1>(0h0)) when _T_2615 : node _T_2616 = eq(_T_2613, UInt<1>(0h0)) when _T_2616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2613, UInt<1>(0h1), "") : assert_102 node _T_2617 = eq(io.in.d.bits.size, a_size_lookup) node _T_2618 = asUInt(reset) node _T_2619 = eq(_T_2618, UInt<1>(0h0)) when _T_2619 : node _T_2620 = eq(_T_2617, UInt<1>(0h0)) when _T_2620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2617, UInt<1>(0h1), "") : assert_103 node _T_2621 = and(io.in.d.valid, d_first_1) node _T_2622 = and(_T_2621, a_first_1) node _T_2623 = and(_T_2622, io.in.a.valid) node _T_2624 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2625 = and(_T_2623, _T_2624) node _T_2626 = eq(d_release_ack, UInt<1>(0h0)) node _T_2627 = and(_T_2625, _T_2626) when _T_2627 : node _T_2628 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2629 = or(_T_2628, io.in.a.ready) node _T_2630 = asUInt(reset) node _T_2631 = eq(_T_2630, UInt<1>(0h0)) when _T_2631 : node _T_2632 = eq(_T_2629, UInt<1>(0h0)) when _T_2632 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2629, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_225 node _T_2633 = orr(inflight) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) node _T_2635 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2636 = or(_T_2634, _T_2635) node _T_2637 = lt(watchdog, plusarg_reader.out) node _T_2638 = or(_T_2636, _T_2637) node _T_2639 = asUInt(reset) node _T_2640 = eq(_T_2639, UInt<1>(0h0)) when _T_2640 : node _T_2641 = eq(_T_2638, UInt<1>(0h0)) when _T_2641 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2638, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2642 = and(io.in.a.ready, io.in.a.valid) node _T_2643 = and(io.in.d.ready, io.in.d.valid) node _T_2644 = or(_T_2642, _T_2643) when _T_2644 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<2052> connect c_sizes_set, UInt<2052>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2645 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2646 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2647 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2648 = and(_T_2646, _T_2647) node _T_2649 = and(_T_2645, _T_2648) when _T_2649 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2650 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2651 = and(_T_2650, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2652 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2653 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2654 = and(_T_2652, _T_2653) node _T_2655 = and(_T_2651, _T_2654) when _T_2655 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2656 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2657 = bits(_T_2656, 0, 0) node _T_2658 = eq(_T_2657, UInt<1>(0h0)) node _T_2659 = asUInt(reset) node _T_2660 = eq(_T_2659, UInt<1>(0h0)) when _T_2660 : node _T_2661 = eq(_T_2658, UInt<1>(0h0)) when _T_2661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2658, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<2052> connect d_sizes_clr_1, UInt<2052>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2662 = and(io.in.d.valid, d_first_2) node _T_2663 = and(_T_2662, UInt<1>(0h1)) node _T_2664 = and(_T_2663, d_release_ack_1) when _T_2664 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2665 = and(io.in.d.ready, io.in.d.valid) node _T_2666 = and(_T_2665, d_first_2) node _T_2667 = and(_T_2666, UInt<1>(0h1)) node _T_2668 = and(_T_2667, d_release_ack_1) when _T_2668 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2669 = and(io.in.d.valid, d_first_2) node _T_2670 = and(_T_2669, UInt<1>(0h1)) node _T_2671 = and(_T_2670, d_release_ack_1) when _T_2671 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2672 = dshr(inflight_1, io.in.d.bits.source) node _T_2673 = bits(_T_2672, 0, 0) node _T_2674 = or(_T_2673, same_cycle_resp_1) node _T_2675 = asUInt(reset) node _T_2676 = eq(_T_2675, UInt<1>(0h0)) when _T_2676 : node _T_2677 = eq(_T_2674, UInt<1>(0h0)) when _T_2677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2674, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2678 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2679 = asUInt(reset) node _T_2680 = eq(_T_2679, UInt<1>(0h0)) when _T_2680 : node _T_2681 = eq(_T_2678, UInt<1>(0h0)) when _T_2681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2678, UInt<1>(0h1), "") : assert_108 else : node _T_2682 = eq(io.in.d.bits.size, c_size_lookup) node _T_2683 = asUInt(reset) node _T_2684 = eq(_T_2683, UInt<1>(0h0)) when _T_2684 : node _T_2685 = eq(_T_2682, UInt<1>(0h0)) when _T_2685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2682, UInt<1>(0h1), "") : assert_109 node _T_2686 = and(io.in.d.valid, d_first_2) node _T_2687 = and(_T_2686, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2688 = and(_T_2687, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2689 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2690 = and(_T_2688, _T_2689) node _T_2691 = and(_T_2690, d_release_ack_1) node _T_2692 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2693 = and(_T_2691, _T_2692) when _T_2693 : node _T_2694 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2695 = or(_T_2694, _WIRE_27.ready) node _T_2696 = asUInt(reset) node _T_2697 = eq(_T_2696, UInt<1>(0h0)) when _T_2697 : node _T_2698 = eq(_T_2695, UInt<1>(0h0)) when _T_2698 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2695, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_226 node _T_2699 = orr(inflight_1) node _T_2700 = eq(_T_2699, UInt<1>(0h0)) node _T_2701 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2702 = or(_T_2700, _T_2701) node _T_2703 = lt(watchdog_1, plusarg_reader_1.out) node _T_2704 = or(_T_2702, _T_2703) node _T_2705 = asUInt(reset) node _T_2706 = eq(_T_2705, UInt<1>(0h0)) when _T_2706 : node _T_2707 = eq(_T_2704, UInt<1>(0h0)) when _T_2707 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2704, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2708 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2709 = and(io.in.d.ready, io.in.d.valid) node _T_2710 = or(_T_2708, _T_2709) when _T_2710 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_111( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_165 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_171 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_177 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_183 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_189 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_195 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_201 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_207 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_213 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_219 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_225 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_231 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_237 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_243 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_249 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_255 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_261 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_267 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_273 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_279 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_285 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_291 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_293 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_wo_ready_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_wo_ready_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_4_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_5_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [8194:0] _c_opcodes_set_T_1 = 8195'h0; // @[Monitor.scala:767:54] wire [8194:0] _c_sizes_set_T_1 = 8195'h0; // @[Monitor.scala:768:52] wire [12:0] _c_opcodes_set_T = 13'h0; // @[Monitor.scala:767:79] wire [12:0] _c_sizes_set_T = 13'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [1023:0] _c_set_wo_ready_T = 1024'h1; // @[OneHot.scala:58:35] wire [1023:0] _c_set_T = 1024'h1; // @[OneHot.scala:58:35] wire [2051:0] c_opcodes_set = 2052'h0; // @[Monitor.scala:740:34] wire [2051:0] c_sizes_set = 2052'h0; // @[Monitor.scala:741:34] wire [512:0] c_set = 513'h0; // @[Monitor.scala:738:34] wire [512:0] c_set_wo_ready = 513'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [9:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_1 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_7 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_13 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_19 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_25 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_31 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_73 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_79 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_67 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_109 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_115 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_121 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_127 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_74 = _source_ok_T_73 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_110 = _source_ok_T_109 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_116 = _source_ok_T_115 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_122 = _source_ok_T_121 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_128 = _source_ok_T_127 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31] wire _source_ok_T_133 = io_in_a_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31] wire _source_ok_T_134 = io_in_a_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31] wire _source_ok_T_135 = io_in_a_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_135; // @[Parameters.scala:1138:31] wire _source_ok_T_136 = io_in_a_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_136; // @[Parameters.scala:1138:31] wire _source_ok_T_137 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_156 = _source_ok_T_155 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_157 = _source_ok_T_156 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_158 = _source_ok_T_157 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_159 = _source_ok_T_158 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_160 = _source_ok_T_159 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_161 = _source_ok_T_160 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_161 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_162 = io_in_d_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_162; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_163 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_169 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_175 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_181 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_187 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_193 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_235 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_241 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_164 = _source_ok_T_163 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_166 = _source_ok_T_164; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_168; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_170 = _source_ok_T_169 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_172 = _source_ok_T_170; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_174; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_176 = _source_ok_T_175 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_178 = _source_ok_T_176; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_180; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_182 = _source_ok_T_181 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_184 = _source_ok_T_182; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_186; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_188 = _source_ok_T_187 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_190 = _source_ok_T_188; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_192; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_194 = _source_ok_T_193 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_196 = _source_ok_T_194; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_198; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_199 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_205 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_211 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_217 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_223 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_229 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_247 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_253 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_259 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_265 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_271 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_277 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_283 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_289 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_200 = _source_ok_T_199 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_202 = _source_ok_T_200; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_204; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_206 = _source_ok_T_205 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_208 = _source_ok_T_206; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_210; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_212 = _source_ok_T_211 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_214 = _source_ok_T_212; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_9 = _source_ok_T_216; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_218 = _source_ok_T_217 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_220 = _source_ok_T_218; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_10 = _source_ok_T_222; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_224 = _source_ok_T_223 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_226 = _source_ok_T_224; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_11 = _source_ok_T_228; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_230 = _source_ok_T_229 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_232 = _source_ok_T_230; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_12 = _source_ok_T_234; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_236 = _source_ok_T_235 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_238 = _source_ok_T_236; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_13 = _source_ok_T_240; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_242 = _source_ok_T_241 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_244 = _source_ok_T_242; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_14 = _source_ok_T_246; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_248 = _source_ok_T_247 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_250 = _source_ok_T_248; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_15 = _source_ok_T_252; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_254 = _source_ok_T_253 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_256 = _source_ok_T_254; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_16 = _source_ok_T_258; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_260 = _source_ok_T_259 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_262 = _source_ok_T_260; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_17 = _source_ok_T_264; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_266 = _source_ok_T_265 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_268 = _source_ok_T_266; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_18 = _source_ok_T_270; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_272 = _source_ok_T_271 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_274 = _source_ok_T_272; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_19 = _source_ok_T_276; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_278 = _source_ok_T_277 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_280 = _source_ok_T_278; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_20 = _source_ok_T_282; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_284 = _source_ok_T_283 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_286 = _source_ok_T_284; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_21 = _source_ok_T_288; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_290 = _source_ok_T_289 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_292 = _source_ok_T_290; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_294 = _source_ok_T_292; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_22 = _source_ok_T_294; // @[Parameters.scala:1138:31] wire _source_ok_T_295 = io_in_d_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_295; // @[Parameters.scala:1138:31] wire _source_ok_T_296 = io_in_d_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_296; // @[Parameters.scala:1138:31] wire _source_ok_T_297 = io_in_d_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_297; // @[Parameters.scala:1138:31] wire _source_ok_T_298 = io_in_d_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_298; // @[Parameters.scala:1138:31] wire _source_ok_T_299 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_300 = _source_ok_T_299 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_301 = _source_ok_T_300 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_302 = _source_ok_T_301 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_303 = _source_ok_T_302 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_304 = _source_ok_T_303 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_305 = _source_ok_T_304 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_306 = _source_ok_T_305 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_307 = _source_ok_T_306 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_308 = _source_ok_T_307 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_309 = _source_ok_T_308 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_310 = _source_ok_T_309 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_311 = _source_ok_T_310 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_312 = _source_ok_T_311 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_313 = _source_ok_T_312 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_314 = _source_ok_T_313 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_315 = _source_ok_T_314 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_316 = _source_ok_T_315 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_317 = _source_ok_T_316 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_318 = _source_ok_T_317 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_319 = _source_ok_T_318 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_320 = _source_ok_T_319 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_321 = _source_ok_T_320 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_322 = _source_ok_T_321 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_323 = _source_ok_T_322 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_323 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _T_2642 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2642; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2642; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_2710 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2710; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2710; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2710; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [512:0] a_set; // @[Monitor.scala:626:34] wire [512:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [2051:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [2051:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [12:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [12:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [12:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [12:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [12:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [12:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [12:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [12:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [12:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [2051:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [2051:0] _a_opcode_lookup_T_6 = {2048'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [2051:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [2051:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [2051:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [2051:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2051:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1023:0] _GEN_2 = 1024'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1023:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2575 = _T_2642 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2575 ? _a_set_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2575 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2575 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [12:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [12:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [12:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [8194:0] _a_opcodes_set_T_1 = {8191'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2575 ? _a_opcodes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8194:0] _a_sizes_set_T_1 = {8191'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2575 ? _a_sizes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [512:0] d_clr; // @[Monitor.scala:664:34] wire [512:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [2051:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [2051:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_2621 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1023:0] _GEN_5 = 1024'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2621 & ~d_release_ack ? _d_clr_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2590 = _T_2710 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2590 ? _d_clr_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_5 = 8207'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2590 ? _d_opcodes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [8206:0] _d_sizes_clr_T_5 = 8207'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2590 ? _d_sizes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [512:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [512:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [512:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [2051:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [2051:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [2051:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [2051:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [2051:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [2051:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [512:0] inflight_1; // @[Monitor.scala:726:35] wire [512:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [2051:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [2051:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [2051:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [2051:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [2051:0] _c_opcode_lookup_T_6 = {2048'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [2051:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [2051:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [2051:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [2051:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2051:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [512:0] d_clr_1; // @[Monitor.scala:774:34] wire [512:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [2051:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [2051:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2686 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2686 & d_release_ack_1 ? _d_clr_wo_ready_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2668 = _T_2710 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2668 ? _d_clr_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_11 = 8207'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2668 ? _d_opcodes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [8206:0] _d_sizes_clr_T_11 = 8207'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2668 ? _d_sizes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 10'h0; // @[Monitor.scala:36:7, :795:113] wire [512:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [512:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [2051:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [2051:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [2051:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [2051:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_243 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_243( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_75 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_75( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_78 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_79 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_39( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_2 = 2'h1 << _GEN_1; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_111 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_111( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TransposePreloadUnroller : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}} regreset state : UInt<2>, clock, reset, UInt<1>(0h0) node garbage_addr = not(UInt<32>(0h0)) inst q of MultiHeadedQueue connect q.clock, clock connect q.reset, reset connect q.io.enq, io.in node _first_preload_T = eq(q.io.deq.bits[0].cmd.inst.funct, UInt<3>(0h6)) node _first_preload_T_1 = and(q.io.deq.valid[0], _first_preload_T) node _first_preload_T_2 = eq(state, UInt<1>(0h0)) node first_preload = and(_first_preload_T_1, _first_preload_T_2) reg b_transposed_and_ws : UInt<1>, clock node _unroll_preload_T = and(b_transposed_and_ws, q.io.deq.valid[1]) node _unroll_preload_T_1 = eq(q.io.deq.bits[1].cmd.inst.funct, UInt<3>(0h4)) node unroll_preload = and(_unroll_preload_T, _unroll_preload_T_1) wire first_preload_cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} connect first_preload_cmd, q.io.deq.bits[0] node _first_preload_cmd_cmd_rs2_T = bits(q.io.deq.bits[0].cmd.rs2, 63, 32) node _first_preload_cmd_cmd_rs2_T_1 = cat(_first_preload_cmd_cmd_rs2_T, garbage_addr) connect first_preload_cmd.cmd.rs2, _first_preload_cmd_cmd_rs2_T_1 connect first_preload_cmd.rob_id.valid, UInt<1>(0h0) wire first_compute_cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} connect first_compute_cmd, q.io.deq.bits[1] node _first_compute_cmd_cmd_inst_rs1_T = bits(q.io.deq.bits[1].cmd.rs1, 63, 32) node _first_compute_cmd_cmd_inst_rs1_T_1 = cat(_first_compute_cmd_cmd_inst_rs1_T, garbage_addr) connect first_compute_cmd.cmd.inst.rs1, _first_compute_cmd_cmd_inst_rs1_T_1 node _first_compute_cmd_cmd_inst_rs2_T = bits(q.io.deq.bits[1].cmd.rs2, 63, 32) node _first_compute_cmd_cmd_inst_rs2_T_1 = cat(_first_compute_cmd_cmd_inst_rs2_T, garbage_addr) connect first_compute_cmd.cmd.inst.rs2, _first_compute_cmd_cmd_inst_rs2_T_1 connect first_compute_cmd.cmd.inst.funct, UInt<3>(0h5) connect first_compute_cmd.rob_id.valid, UInt<1>(0h0) wire second_preload_cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} connect second_preload_cmd, q.io.deq.bits[0] node _second_preload_cmd_cmd_rs1_T = bits(q.io.deq.bits[0].cmd.rs1, 63, 32) node _second_preload_cmd_cmd_rs1_T_1 = cat(_second_preload_cmd_cmd_rs1_T, garbage_addr) connect second_preload_cmd.cmd.rs1, _second_preload_cmd_cmd_rs1_T_1 node config_cmd_type = bits(q.io.deq.bits[0].cmd.rs1, 1, 0) node _is_config_T = eq(q.io.deq.bits[0].cmd.inst.funct, UInt<1>(0h0)) node _is_config_T_1 = eq(config_cmd_type, UInt<1>(0h0)) node is_config = and(_is_config_T, _is_config_T_1) node _io_out_valid_T = eq(b_transposed_and_ws, UInt<1>(0h0)) node _io_out_valid_T_1 = or(_io_out_valid_T, q.io.deq.valid[1]) node _io_out_valid_T_2 = gt(state, UInt<1>(0h1)) node _io_out_valid_T_3 = mux(_io_out_valid_T_2, UInt<1>(0h1), q.io.deq.valid[0]) node _io_out_valid_T_4 = mux(first_preload, _io_out_valid_T_1, _io_out_valid_T_3) connect io.out.valid, _io_out_valid_T_4 node _io_out_bits_T = and(first_preload, unroll_preload) node _io_out_bits_T_1 = eq(state, UInt<1>(0h1)) node _io_out_bits_T_2 = eq(state, UInt<2>(0h2)) node _io_out_bits_T_3 = mux(_io_out_bits_T_2, second_preload_cmd, q.io.deq.bits[0]) node _io_out_bits_T_4 = mux(_io_out_bits_T_1, first_compute_cmd, _io_out_bits_T_3) node _io_out_bits_T_5 = mux(_io_out_bits_T, first_preload_cmd, _io_out_bits_T_4) connect io.out.bits, _io_out_bits_T_5 node _q_io_deq_pop_T = and(io.out.ready, io.out.valid) node _q_io_deq_pop_T_1 = and(first_preload, unroll_preload) node _q_io_deq_pop_T_2 = eq(_q_io_deq_pop_T_1, UInt<1>(0h0)) node _q_io_deq_pop_T_3 = and(_q_io_deq_pop_T, _q_io_deq_pop_T_2) node _q_io_deq_pop_T_4 = neq(state, UInt<1>(0h1)) node _q_io_deq_pop_T_5 = and(_q_io_deq_pop_T_3, _q_io_deq_pop_T_4) node _q_io_deq_pop_T_6 = mux(_q_io_deq_pop_T_5, UInt<1>(0h1), UInt<1>(0h0)) connect q.io.deq.pop, _q_io_deq_pop_T_6 node _T = and(io.out.ready, io.out.valid) when _T : when is_config : node set_only_strides = bits(q.io.deq.bits[0].cmd.rs1, 7, 7) node _T_1 = eq(set_only_strides, UInt<1>(0h0)) when _T_1 : node _b_transposed_and_ws_T = bits(q.io.deq.bits[0].cmd.rs1, 2, 2) node _b_transposed_and_ws_T_1 = eq(_b_transposed_and_ws_T, UInt<1>(0h1)) node _b_transposed_and_ws_T_2 = or(UInt<1>(0h1), _b_transposed_and_ws_T_1) node _b_transposed_and_ws_T_3 = bits(q.io.deq.bits[0].cmd.rs1, 9, 9) node _b_transposed_and_ws_T_4 = and(_b_transposed_and_ws_T_2, _b_transposed_and_ws_T_3) connect b_transposed_and_ws, _b_transposed_and_ws_T_4 else : node _T_2 = and(first_preload, unroll_preload) when _T_2 : connect state, UInt<1>(0h1) else : node _T_3 = geq(state, UInt<1>(0h1)) when _T_3 : node _state_T = eq(state, UInt<1>(0h0)) node _state_T_1 = eq(state, UInt<1>(0h1)) node _state_T_2 = eq(state, UInt<2>(0h2)) node _state_T_3 = mux(_state_T_1, UInt<2>(0h2), UInt<1>(0h0)) node _state_T_4 = mux(_state_T, UInt<1>(0h1), _state_T_3) connect state, _state_T_4 wire _WIRE : UInt<1>[45] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect _WIRE[8], UInt<1>(0h0) connect _WIRE[9], UInt<1>(0h0) connect _WIRE[10], UInt<1>(0h0) connect _WIRE[11], UInt<1>(0h0) connect _WIRE[12], UInt<1>(0h0) connect _WIRE[13], UInt<1>(0h0) connect _WIRE[14], UInt<1>(0h0) connect _WIRE[15], UInt<1>(0h0) connect _WIRE[16], UInt<1>(0h0) connect _WIRE[17], UInt<1>(0h0) connect _WIRE[18], UInt<1>(0h0) connect _WIRE[19], UInt<1>(0h0) connect _WIRE[20], UInt<1>(0h0) connect _WIRE[21], UInt<1>(0h0) connect _WIRE[22], UInt<1>(0h0) connect _WIRE[23], UInt<1>(0h0) connect _WIRE[24], UInt<1>(0h0) connect _WIRE[25], UInt<1>(0h0) connect _WIRE[26], UInt<1>(0h0) connect _WIRE[27], UInt<1>(0h0) connect _WIRE[28], UInt<1>(0h0) connect _WIRE[29], UInt<1>(0h0) connect _WIRE[30], UInt<1>(0h0) connect _WIRE[31], UInt<1>(0h0) connect _WIRE[32], UInt<1>(0h0) connect _WIRE[33], UInt<1>(0h0) connect _WIRE[34], UInt<1>(0h0) connect _WIRE[35], UInt<1>(0h0) connect _WIRE[36], UInt<1>(0h0) connect _WIRE[37], UInt<1>(0h0) connect _WIRE[38], UInt<1>(0h0) connect _WIRE[39], UInt<1>(0h0) connect _WIRE[40], UInt<1>(0h0) connect _WIRE[41], UInt<1>(0h0) connect _WIRE[42], UInt<1>(0h0) connect _WIRE[43], UInt<1>(0h0) connect _WIRE[44], UInt<1>(0h0) connect io.counter.event_signal, _WIRE wire _WIRE_1 : UInt<32>[8] connect _WIRE_1[0], UInt<32>(0h0) connect _WIRE_1[1], UInt<32>(0h0) connect _WIRE_1[2], UInt<32>(0h0) connect _WIRE_1[3], UInt<32>(0h0) connect _WIRE_1[4], UInt<32>(0h0) connect _WIRE_1[5], UInt<32>(0h0) connect _WIRE_1[6], UInt<32>(0h0) connect _WIRE_1[7], UInt<32>(0h0) connect io.counter.external_values, _WIRE_1 node _T_4 = neq(state, UInt<1>(0h0)) connect io.counter.event_signal[44], _T_4

module TransposePreloadUnroller( // @[TransposePreloadUnroller.scala:9:7] input clock, // @[TransposePreloadUnroller.scala:9:7] input reset, // @[TransposePreloadUnroller.scala:9:7] output io_in_ready, // @[TransposePreloadUnroller.scala:14:14] input io_in_valid, // @[TransposePreloadUnroller.scala:14:14] input [6:0] io_in_bits_cmd_inst_funct, // @[TransposePreloadUnroller.scala:14:14] input [4:0] io_in_bits_cmd_inst_rs2, // @[TransposePreloadUnroller.scala:14:14] input [4:0] io_in_bits_cmd_inst_rs1, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_inst_xd, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_inst_xs1, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_inst_xs2, // @[TransposePreloadUnroller.scala:14:14] input [4:0] io_in_bits_cmd_inst_rd, // @[TransposePreloadUnroller.scala:14:14] input [6:0] io_in_bits_cmd_inst_opcode, // @[TransposePreloadUnroller.scala:14:14] input [63:0] io_in_bits_cmd_rs1, // @[TransposePreloadUnroller.scala:14:14] input [63:0] io_in_bits_cmd_rs2, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_debug, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_cease, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_wfi, // @[TransposePreloadUnroller.scala:14:14] input [31:0] io_in_bits_cmd_status_isa, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_dprv, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_dv, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_prv, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_v, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sd, // @[TransposePreloadUnroller.scala:14:14] input [22:0] io_in_bits_cmd_status_zero2, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mpv, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_gva, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mbe, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sbe, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_sxl, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_uxl, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sd_rv32, // @[TransposePreloadUnroller.scala:14:14] input [7:0] io_in_bits_cmd_status_zero1, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_tsr, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_tw, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_tvm, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mxr, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sum, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mprv, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_xs, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_fs, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_mpp, // @[TransposePreloadUnroller.scala:14:14] input [1:0] io_in_bits_cmd_status_vs, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_spp, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mpie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_ube, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_spie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_upie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_mie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_hie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_sie, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_cmd_status_uie, // @[TransposePreloadUnroller.scala:14:14] input [5:0] io_in_bits_rob_id_bits, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_from_matmul_fsm, // @[TransposePreloadUnroller.scala:14:14] input io_in_bits_from_conv_fsm, // @[TransposePreloadUnroller.scala:14:14] input io_out_ready, // @[TransposePreloadUnroller.scala:14:14] output io_out_valid, // @[TransposePreloadUnroller.scala:14:14] output [6:0] io_out_bits_cmd_inst_funct, // @[TransposePreloadUnroller.scala:14:14] output [4:0] io_out_bits_cmd_inst_rs2, // @[TransposePreloadUnroller.scala:14:14] output [4:0] io_out_bits_cmd_inst_rs1, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_inst_xd, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_inst_xs1, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_inst_xs2, // @[TransposePreloadUnroller.scala:14:14] output [4:0] io_out_bits_cmd_inst_rd, // @[TransposePreloadUnroller.scala:14:14] output [6:0] io_out_bits_cmd_inst_opcode, // @[TransposePreloadUnroller.scala:14:14] output [63:0] io_out_bits_cmd_rs1, // @[TransposePreloadUnroller.scala:14:14] output [63:0] io_out_bits_cmd_rs2, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_debug, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_cease, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_wfi, // @[TransposePreloadUnroller.scala:14:14] output [31:0] io_out_bits_cmd_status_isa, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_dprv, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_dv, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_prv, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_v, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sd, // @[TransposePreloadUnroller.scala:14:14] output [22:0] io_out_bits_cmd_status_zero2, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mpv, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_gva, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mbe, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sbe, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_sxl, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_uxl, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sd_rv32, // @[TransposePreloadUnroller.scala:14:14] output [7:0] io_out_bits_cmd_status_zero1, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_tsr, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_tw, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_tvm, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mxr, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sum, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mprv, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_xs, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_fs, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_mpp, // @[TransposePreloadUnroller.scala:14:14] output [1:0] io_out_bits_cmd_status_vs, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_spp, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mpie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_ube, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_spie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_upie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_mie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_hie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_sie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_cmd_status_uie, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_rob_id_valid, // @[TransposePreloadUnroller.scala:14:14] output [5:0] io_out_bits_rob_id_bits, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_from_matmul_fsm, // @[TransposePreloadUnroller.scala:14:14] output io_out_bits_from_conv_fsm, // @[TransposePreloadUnroller.scala:14:14] input io_counter_external_reset // @[TransposePreloadUnroller.scala:14:14] ); wire _q_io_deq_valid_0; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_valid_1; // @[MultiHeadedQueue.scala:53:19] wire [6:0] _q_io_deq_bits_0_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19] wire [4:0] _q_io_deq_bits_0_cmd_inst_rs2; // @[MultiHeadedQueue.scala:53:19] wire [4:0] _q_io_deq_bits_0_cmd_inst_rs1; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_inst_xd; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_inst_xs1; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_inst_xs2; // @[MultiHeadedQueue.scala:53:19] wire [4:0] _q_io_deq_bits_0_cmd_inst_rd; // @[MultiHeadedQueue.scala:53:19] wire [6:0] _q_io_deq_bits_0_cmd_inst_opcode; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_0_cmd_rs1; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_0_cmd_rs2; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_debug; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_cease; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_wfi; // @[MultiHeadedQueue.scala:53:19] wire [31:0] _q_io_deq_bits_0_cmd_status_isa; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_dprv; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_dv; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_prv; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_v; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sd; // @[MultiHeadedQueue.scala:53:19] wire [22:0] _q_io_deq_bits_0_cmd_status_zero2; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mpv; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_gva; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mbe; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sbe; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_sxl; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_uxl; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sd_rv32; // @[MultiHeadedQueue.scala:53:19] wire [7:0] _q_io_deq_bits_0_cmd_status_zero1; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_tsr; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_tw; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_tvm; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mxr; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sum; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mprv; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_xs; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_fs; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_mpp; // @[MultiHeadedQueue.scala:53:19] wire [1:0] _q_io_deq_bits_0_cmd_status_vs; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_spp; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mpie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_ube; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_spie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_upie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_mie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_hie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_sie; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_cmd_status_uie; // @[MultiHeadedQueue.scala:53:19] wire [5:0] _q_io_deq_bits_0_rob_id_bits; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_from_matmul_fsm; // @[MultiHeadedQueue.scala:53:19] wire _q_io_deq_bits_0_from_conv_fsm; // @[MultiHeadedQueue.scala:53:19] wire [6:0] _q_io_deq_bits_1_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_1_cmd_rs1; // @[MultiHeadedQueue.scala:53:19] wire [63:0] _q_io_deq_bits_1_cmd_rs2; // @[MultiHeadedQueue.scala:53:19] wire io_in_valid_0 = io_in_valid; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_in_bits_cmd_inst_rs2_0 = io_in_bits_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_in_bits_cmd_inst_rs1_0 = io_in_bits_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_inst_xd_0 = io_in_bits_cmd_inst_xd; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_inst_xs1_0 = io_in_bits_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_inst_xs2_0 = io_in_bits_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_in_bits_cmd_inst_rd_0 = io_in_bits_cmd_inst_rd; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_in_bits_cmd_inst_opcode_0 = io_in_bits_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_debug_0 = io_in_bits_cmd_status_debug; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_cease_0 = io_in_bits_cmd_status_cease; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_wfi_0 = io_in_bits_cmd_status_wfi; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_in_bits_cmd_status_isa_0 = io_in_bits_cmd_status_isa; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_dprv_0 = io_in_bits_cmd_status_dprv; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_dv_0 = io_in_bits_cmd_status_dv; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_prv_0 = io_in_bits_cmd_status_prv; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_v_0 = io_in_bits_cmd_status_v; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sd_0 = io_in_bits_cmd_status_sd; // @[TransposePreloadUnroller.scala:9:7] wire [22:0] io_in_bits_cmd_status_zero2_0 = io_in_bits_cmd_status_zero2; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mpv_0 = io_in_bits_cmd_status_mpv; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_gva_0 = io_in_bits_cmd_status_gva; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mbe_0 = io_in_bits_cmd_status_mbe; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sbe_0 = io_in_bits_cmd_status_sbe; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_sxl_0 = io_in_bits_cmd_status_sxl; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_uxl_0 = io_in_bits_cmd_status_uxl; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sd_rv32_0 = io_in_bits_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:9:7] wire [7:0] io_in_bits_cmd_status_zero1_0 = io_in_bits_cmd_status_zero1; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_tsr_0 = io_in_bits_cmd_status_tsr; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_tw_0 = io_in_bits_cmd_status_tw; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_tvm_0 = io_in_bits_cmd_status_tvm; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mxr_0 = io_in_bits_cmd_status_mxr; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sum_0 = io_in_bits_cmd_status_sum; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mprv_0 = io_in_bits_cmd_status_mprv; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_xs_0 = io_in_bits_cmd_status_xs; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_fs_0 = io_in_bits_cmd_status_fs; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_mpp_0 = io_in_bits_cmd_status_mpp; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_in_bits_cmd_status_vs_0 = io_in_bits_cmd_status_vs; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_spp_0 = io_in_bits_cmd_status_spp; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mpie_0 = io_in_bits_cmd_status_mpie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_ube_0 = io_in_bits_cmd_status_ube; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_spie_0 = io_in_bits_cmd_status_spie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_upie_0 = io_in_bits_cmd_status_upie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_mie_0 = io_in_bits_cmd_status_mie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_hie_0 = io_in_bits_cmd_status_hie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_sie_0 = io_in_bits_cmd_status_sie; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_cmd_status_uie_0 = io_in_bits_cmd_status_uie; // @[TransposePreloadUnroller.scala:9:7] wire [5:0] io_in_bits_rob_id_bits_0 = io_in_bits_rob_id_bits; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_from_matmul_fsm_0 = io_in_bits_from_matmul_fsm; // @[TransposePreloadUnroller.scala:9:7] wire io_in_bits_from_conv_fsm_0 = io_in_bits_from_conv_fsm; // @[TransposePreloadUnroller.scala:9:7] wire io_out_ready_0 = io_out_ready; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_external_reset_0 = io_counter_external_reset; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] garbage_addr = 32'hFFFFFFFF; // @[TransposePreloadUnroller.scala:27:22] wire [6:0] first_compute_cmd_cmd_inst_funct = 7'h5; // @[TransposePreloadUnroller.scala:44:35] wire [31:0] io_counter_external_values_0 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_1 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_2 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_3 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_4 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_5 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_6 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_counter_external_values_7 = 32'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_0 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_1 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_2 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_3 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_4 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_5 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_6 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_7 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_8 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_9 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_10 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_11 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_12 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_13 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_14 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_15 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_16 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_17 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_18 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_19 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_20 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_21 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_22 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_23 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_24 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_25 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_26 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_27 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_28 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_29 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_30 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_31 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_32 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_33 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_34 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_35 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_36 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_37 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_38 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_39 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_40 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_41 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_42 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_43 = 1'h0; // @[TransposePreloadUnroller.scala:9:7] wire first_preload_cmd_rob_id_valid = 1'h0; // @[TransposePreloadUnroller.scala:40:35] wire first_compute_cmd_rob_id_valid = 1'h0; // @[TransposePreloadUnroller.scala:44:35] wire io_in_bits_rob_id_valid = 1'h1; // @[TransposePreloadUnroller.scala:9:7] wire second_preload_cmd_rob_id_valid = 1'h1; // @[TransposePreloadUnroller.scala:50:36] wire _io_out_bits_T_3_rob_id_valid = 1'h1; // @[Mux.scala:126:16] wire _b_transposed_and_ws_T_2 = 1'h1; // @[TransposePreloadUnroller.scala:73:61] wire _io_out_valid_T_4; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_5_cmd_inst_funct; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_5_cmd_inst_rs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_5_cmd_inst_rs1; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_inst_xd; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_inst_xs1; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_inst_xs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_5_cmd_inst_rd; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_5_cmd_inst_opcode; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_5_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_5_cmd_rs2; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_debug; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_cease; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_wfi; // @[Mux.scala:126:16] wire [31:0] _io_out_bits_T_5_cmd_status_isa; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_dprv; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_dv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_prv; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_v; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sd; // @[Mux.scala:126:16] wire [22:0] _io_out_bits_T_5_cmd_status_zero2; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mpv; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_gva; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mbe; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sbe; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_sxl; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_uxl; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sd_rv32; // @[Mux.scala:126:16] wire [7:0] _io_out_bits_T_5_cmd_status_zero1; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_tsr; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_tw; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_tvm; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mxr; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sum; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mprv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_xs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_fs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_mpp; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_5_cmd_status_vs; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_spp; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mpie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_ube; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_spie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_upie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_mie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_hie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_sie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_cmd_status_uie; // @[Mux.scala:126:16] wire _io_out_bits_T_5_rob_id_valid; // @[Mux.scala:126:16] wire [5:0] _io_out_bits_T_5_rob_id_bits; // @[Mux.scala:126:16] wire _io_out_bits_T_5_from_matmul_fsm; // @[Mux.scala:126:16] wire _io_out_bits_T_5_from_conv_fsm; // @[Mux.scala:126:16] wire io_in_ready_0; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_out_bits_cmd_inst_funct_0; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_inst_xd_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_inst_xs1_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_inst_xs2_0; // @[TransposePreloadUnroller.scala:9:7] wire [4:0] io_out_bits_cmd_inst_rd_0; // @[TransposePreloadUnroller.scala:9:7] wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_debug_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_cease_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_wfi_0; // @[TransposePreloadUnroller.scala:9:7] wire [31:0] io_out_bits_cmd_status_isa_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_dprv_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_dv_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_prv_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_v_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sd_0; // @[TransposePreloadUnroller.scala:9:7] wire [22:0] io_out_bits_cmd_status_zero2_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mpv_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_gva_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mbe_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sbe_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_sxl_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_uxl_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sd_rv32_0; // @[TransposePreloadUnroller.scala:9:7] wire [7:0] io_out_bits_cmd_status_zero1_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_tsr_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_tw_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_tvm_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mxr_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sum_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mprv_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_xs_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_fs_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_mpp_0; // @[TransposePreloadUnroller.scala:9:7] wire [1:0] io_out_bits_cmd_status_vs_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_spp_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mpie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_ube_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_spie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_upie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_mie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_hie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_sie_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_cmd_status_uie_0; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_out_bits_cmd_rs1_0; // @[TransposePreloadUnroller.scala:9:7] wire [63:0] io_out_bits_cmd_rs2_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_rob_id_valid_0; // @[TransposePreloadUnroller.scala:9:7] wire [5:0] io_out_bits_rob_id_bits_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_from_matmul_fsm_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_bits_from_conv_fsm_0; // @[TransposePreloadUnroller.scala:9:7] wire io_out_valid_0; // @[TransposePreloadUnroller.scala:9:7] wire io_counter_event_signal_44; // @[TransposePreloadUnroller.scala:9:7] reg [1:0] state; // @[TransposePreloadUnroller.scala:25:22] wire _first_preload_T = _q_io_deq_bits_0_cmd_inst_funct == 7'h6; // @[TransposePreloadUnroller.scala:35:46] wire _first_preload_T_1 = _q_io_deq_valid_0 & _first_preload_T; // @[TransposePreloadUnroller.scala:35:{33,46}] wire _GEN = state == 2'h0; // @[TransposePreloadUnroller.scala:25:22, :35:71] wire _first_preload_T_2; // @[TransposePreloadUnroller.scala:35:71] assign _first_preload_T_2 = _GEN; // @[TransposePreloadUnroller.scala:35:71] wire _state_T; // @[TransposePreloadUnroller.scala:78:22] assign _state_T = _GEN; // @[TransposePreloadUnroller.scala:35:71, :78:22] wire first_preload = _first_preload_T_1 & _first_preload_T_2; // @[TransposePreloadUnroller.scala:35:{33,62,71}] reg b_transposed_and_ws; // @[TransposePreloadUnroller.scala:37:32] wire _unroll_preload_T = b_transposed_and_ws & _q_io_deq_valid_1; // @[TransposePreloadUnroller.scala:37:32, :38:44] wire _unroll_preload_T_1 = _q_io_deq_bits_1_cmd_inst_funct == 7'h4; // @[TransposePreloadUnroller.scala:38:70] wire unroll_preload = _unroll_preload_T & _unroll_preload_T_1; // @[TransposePreloadUnroller.scala:38:{44,57,70}] wire [63:0] _first_preload_cmd_cmd_rs2_T_1; // @[TransposePreloadUnroller.scala:41:35] wire [6:0] first_preload_cmd_cmd_inst_funct; // @[TransposePreloadUnroller.scala:40:35] wire [4:0] first_preload_cmd_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:40:35] wire [4:0] first_preload_cmd_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_inst_xd; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:40:35] wire [4:0] first_preload_cmd_cmd_inst_rd; // @[TransposePreloadUnroller.scala:40:35] wire [6:0] first_preload_cmd_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_debug; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_cease; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_wfi; // @[TransposePreloadUnroller.scala:40:35] wire [31:0] first_preload_cmd_cmd_status_isa; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_dprv; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_dv; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_prv; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_v; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sd; // @[TransposePreloadUnroller.scala:40:35] wire [22:0] first_preload_cmd_cmd_status_zero2; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mpv; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_gva; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mbe; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sbe; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_sxl; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_uxl; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:40:35] wire [7:0] first_preload_cmd_cmd_status_zero1; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_tsr; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_tw; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_tvm; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mxr; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sum; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mprv; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_xs; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_fs; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_mpp; // @[TransposePreloadUnroller.scala:40:35] wire [1:0] first_preload_cmd_cmd_status_vs; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_spp; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mpie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_ube; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_spie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_upie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_mie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_hie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_sie; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_cmd_status_uie; // @[TransposePreloadUnroller.scala:40:35] wire [63:0] first_preload_cmd_cmd_rs1; // @[TransposePreloadUnroller.scala:40:35] wire [63:0] first_preload_cmd_cmd_rs2; // @[TransposePreloadUnroller.scala:40:35] wire [5:0] first_preload_cmd_rob_id_bits; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_from_matmul_fsm; // @[TransposePreloadUnroller.scala:40:35] wire first_preload_cmd_from_conv_fsm; // @[TransposePreloadUnroller.scala:40:35] wire [31:0] _first_preload_cmd_cmd_rs2_T = _q_io_deq_bits_0_cmd_rs2[63:32]; // @[TransposePreloadUnroller.scala:41:51] assign _first_preload_cmd_cmd_rs2_T_1 = {_first_preload_cmd_cmd_rs2_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:41:{35,51}] assign first_preload_cmd_cmd_rs2 = _first_preload_cmd_cmd_rs2_T_1; // @[TransposePreloadUnroller.scala:40:35, :41:35] wire [4:0] first_compute_cmd_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:44:35] wire [4:0] first_compute_cmd_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_inst_xd; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:44:35] wire [4:0] first_compute_cmd_cmd_inst_rd; // @[TransposePreloadUnroller.scala:44:35] wire [6:0] first_compute_cmd_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_debug; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_cease; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_wfi; // @[TransposePreloadUnroller.scala:44:35] wire [31:0] first_compute_cmd_cmd_status_isa; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_dprv; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_dv; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_prv; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_v; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sd; // @[TransposePreloadUnroller.scala:44:35] wire [22:0] first_compute_cmd_cmd_status_zero2; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mpv; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_gva; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mbe; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sbe; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_sxl; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_uxl; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:44:35] wire [7:0] first_compute_cmd_cmd_status_zero1; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_tsr; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_tw; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_tvm; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mxr; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sum; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mprv; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_xs; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_fs; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_mpp; // @[TransposePreloadUnroller.scala:44:35] wire [1:0] first_compute_cmd_cmd_status_vs; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_spp; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mpie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_ube; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_spie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_upie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_mie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_hie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_sie; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_cmd_status_uie; // @[TransposePreloadUnroller.scala:44:35] wire [63:0] first_compute_cmd_cmd_rs1; // @[TransposePreloadUnroller.scala:44:35] wire [63:0] first_compute_cmd_cmd_rs2; // @[TransposePreloadUnroller.scala:44:35] wire [5:0] first_compute_cmd_rob_id_bits; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_from_matmul_fsm; // @[TransposePreloadUnroller.scala:44:35] wire first_compute_cmd_from_conv_fsm; // @[TransposePreloadUnroller.scala:44:35] wire [31:0] _first_compute_cmd_cmd_inst_rs1_T = _q_io_deq_bits_1_cmd_rs1[63:32]; // @[TransposePreloadUnroller.scala:45:56] wire [63:0] _first_compute_cmd_cmd_inst_rs1_T_1 = {_first_compute_cmd_cmd_inst_rs1_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:45:{40,56}] assign first_compute_cmd_cmd_inst_rs1 = _first_compute_cmd_cmd_inst_rs1_T_1[4:0]; // @[TransposePreloadUnroller.scala:44:35, :45:{34,40}] wire [31:0] _first_compute_cmd_cmd_inst_rs2_T = _q_io_deq_bits_1_cmd_rs2[63:32]; // @[TransposePreloadUnroller.scala:46:56] wire [63:0] _first_compute_cmd_cmd_inst_rs2_T_1 = {_first_compute_cmd_cmd_inst_rs2_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:46:{40,56}] assign first_compute_cmd_cmd_inst_rs2 = _first_compute_cmd_cmd_inst_rs2_T_1[4:0]; // @[TransposePreloadUnroller.scala:44:35, :46:{34,40}] wire [63:0] _second_preload_cmd_cmd_rs1_T_1; // @[TransposePreloadUnroller.scala:51:36] wire [6:0] second_preload_cmd_cmd_inst_funct; // @[TransposePreloadUnroller.scala:50:36] wire [4:0] second_preload_cmd_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:50:36] wire [4:0] second_preload_cmd_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_inst_xd; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:50:36] wire [4:0] second_preload_cmd_cmd_inst_rd; // @[TransposePreloadUnroller.scala:50:36] wire [6:0] second_preload_cmd_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_debug; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_cease; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_wfi; // @[TransposePreloadUnroller.scala:50:36] wire [31:0] second_preload_cmd_cmd_status_isa; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_dprv; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_dv; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_prv; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_v; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sd; // @[TransposePreloadUnroller.scala:50:36] wire [22:0] second_preload_cmd_cmd_status_zero2; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mpv; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_gva; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mbe; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sbe; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_sxl; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_uxl; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:50:36] wire [7:0] second_preload_cmd_cmd_status_zero1; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_tsr; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_tw; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_tvm; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mxr; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sum; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mprv; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_xs; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_fs; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_mpp; // @[TransposePreloadUnroller.scala:50:36] wire [1:0] second_preload_cmd_cmd_status_vs; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_spp; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mpie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_ube; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_spie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_upie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_mie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_hie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_sie; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_cmd_status_uie; // @[TransposePreloadUnroller.scala:50:36] wire [63:0] second_preload_cmd_cmd_rs1; // @[TransposePreloadUnroller.scala:50:36] wire [63:0] second_preload_cmd_cmd_rs2; // @[TransposePreloadUnroller.scala:50:36] wire [5:0] second_preload_cmd_rob_id_bits; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_from_matmul_fsm; // @[TransposePreloadUnroller.scala:50:36] wire second_preload_cmd_from_conv_fsm; // @[TransposePreloadUnroller.scala:50:36] wire [31:0] _second_preload_cmd_cmd_rs1_T = _q_io_deq_bits_0_cmd_rs1[63:32]; // @[TransposePreloadUnroller.scala:51:52] assign _second_preload_cmd_cmd_rs1_T_1 = {_second_preload_cmd_cmd_rs1_T, 32'hFFFFFFFF}; // @[TransposePreloadUnroller.scala:51:{36,52}] assign second_preload_cmd_cmd_rs1 = _second_preload_cmd_cmd_rs1_T_1; // @[TransposePreloadUnroller.scala:50:36, :51:36] wire [1:0] config_cmd_type = _q_io_deq_bits_0_cmd_rs1[1:0]; // @[TransposePreloadUnroller.scala:53:40] wire _is_config_T = _q_io_deq_bits_0_cmd_inst_funct == 7'h0; // @[TransposePreloadUnroller.scala:54:29] wire _is_config_T_1 = config_cmd_type == 2'h0; // @[TransposePreloadUnroller.scala:53:40, :54:63] wire is_config = _is_config_T & _is_config_T_1; // @[TransposePreloadUnroller.scala:54:{29,44,63}] wire _io_out_valid_T = ~b_transposed_and_ws; // @[TransposePreloadUnroller.scala:37:32, :57:23] wire _io_out_valid_T_1 = _io_out_valid_T | _q_io_deq_valid_1; // @[TransposePreloadUnroller.scala:57:{23,44}] wire _io_out_valid_T_2 = state[1]; // @[TransposePreloadUnroller.scala:25:22, :58:12] wire _io_out_valid_T_3 = _io_out_valid_T_2 | _q_io_deq_valid_0; // @[Mux.scala:126:16] assign _io_out_valid_T_4 = first_preload ? _io_out_valid_T_1 : _io_out_valid_T_3; // @[Mux.scala:126:16] assign io_out_valid_0 = _io_out_valid_T_4; // @[Mux.scala:126:16] wire _T_2 = first_preload & unroll_preload; // @[TransposePreloadUnroller.scala:35:62, :38:57, :62:20] wire _io_out_bits_T; // @[TransposePreloadUnroller.scala:62:20] assign _io_out_bits_T = _T_2; // @[TransposePreloadUnroller.scala:62:20] wire _q_io_deq_pop_T_1; // @[TransposePreloadUnroller.scala:67:47] assign _q_io_deq_pop_T_1 = _T_2; // @[TransposePreloadUnroller.scala:62:20, :67:47] wire _GEN_0 = state == 2'h1; // @[TransposePreloadUnroller.scala:25:22, :58:12, :63:12] wire _io_out_bits_T_1; // @[TransposePreloadUnroller.scala:63:12] assign _io_out_bits_T_1 = _GEN_0; // @[TransposePreloadUnroller.scala:63:12] wire _state_T_1; // @[TransposePreloadUnroller.scala:78:22] assign _state_T_1 = _GEN_0; // @[TransposePreloadUnroller.scala:63:12, :78:22] wire _GEN_1 = state == 2'h2; // @[TransposePreloadUnroller.scala:25:22, :64:12] wire _io_out_bits_T_2; // @[TransposePreloadUnroller.scala:64:12] assign _io_out_bits_T_2 = _GEN_1; // @[TransposePreloadUnroller.scala:64:12] wire _state_T_2; // @[TransposePreloadUnroller.scala:78:22] assign _state_T_2 = _GEN_1; // @[TransposePreloadUnroller.scala:64:12, :78:22] wire [6:0] _io_out_bits_T_3_cmd_inst_funct = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_funct : _q_io_deq_bits_0_cmd_inst_funct; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_3_cmd_inst_rs2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_rs2 : _q_io_deq_bits_0_cmd_inst_rs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_3_cmd_inst_rs1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_rs1 : _q_io_deq_bits_0_cmd_inst_rs1; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_inst_xd = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_xd : _q_io_deq_bits_0_cmd_inst_xd; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_inst_xs1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_xs1 : _q_io_deq_bits_0_cmd_inst_xs1; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_inst_xs2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_xs2 : _q_io_deq_bits_0_cmd_inst_xs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_3_cmd_inst_rd = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_rd : _q_io_deq_bits_0_cmd_inst_rd; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_3_cmd_inst_opcode = _io_out_bits_T_2 ? second_preload_cmd_cmd_inst_opcode : _q_io_deq_bits_0_cmd_inst_opcode; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_3_cmd_rs1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_rs1 : _q_io_deq_bits_0_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_3_cmd_rs2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_rs2 : _q_io_deq_bits_0_cmd_rs2; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_debug = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_debug : _q_io_deq_bits_0_cmd_status_debug; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_cease = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_cease : _q_io_deq_bits_0_cmd_status_cease; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_wfi = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_wfi : _q_io_deq_bits_0_cmd_status_wfi; // @[Mux.scala:126:16] wire [31:0] _io_out_bits_T_3_cmd_status_isa = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_isa : _q_io_deq_bits_0_cmd_status_isa; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_dprv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_dprv : _q_io_deq_bits_0_cmd_status_dprv; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_dv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_dv : _q_io_deq_bits_0_cmd_status_dv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_prv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_prv : _q_io_deq_bits_0_cmd_status_prv; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_v = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_v : _q_io_deq_bits_0_cmd_status_v; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sd = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sd : _q_io_deq_bits_0_cmd_status_sd; // @[Mux.scala:126:16] wire [22:0] _io_out_bits_T_3_cmd_status_zero2 = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_zero2 : _q_io_deq_bits_0_cmd_status_zero2; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mpv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mpv : _q_io_deq_bits_0_cmd_status_mpv; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_gva = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_gva : _q_io_deq_bits_0_cmd_status_gva; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mbe = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mbe : _q_io_deq_bits_0_cmd_status_mbe; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sbe = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sbe : _q_io_deq_bits_0_cmd_status_sbe; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_sxl = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sxl : _q_io_deq_bits_0_cmd_status_sxl; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_uxl = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_uxl : _q_io_deq_bits_0_cmd_status_uxl; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sd_rv32 = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sd_rv32 : _q_io_deq_bits_0_cmd_status_sd_rv32; // @[Mux.scala:126:16] wire [7:0] _io_out_bits_T_3_cmd_status_zero1 = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_zero1 : _q_io_deq_bits_0_cmd_status_zero1; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_tsr = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_tsr : _q_io_deq_bits_0_cmd_status_tsr; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_tw = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_tw : _q_io_deq_bits_0_cmd_status_tw; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_tvm = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_tvm : _q_io_deq_bits_0_cmd_status_tvm; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mxr = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mxr : _q_io_deq_bits_0_cmd_status_mxr; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sum = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sum : _q_io_deq_bits_0_cmd_status_sum; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mprv = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mprv : _q_io_deq_bits_0_cmd_status_mprv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_xs = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_xs : _q_io_deq_bits_0_cmd_status_xs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_fs = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_fs : _q_io_deq_bits_0_cmd_status_fs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_mpp = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mpp : _q_io_deq_bits_0_cmd_status_mpp; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_3_cmd_status_vs = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_vs : _q_io_deq_bits_0_cmd_status_vs; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_spp = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_spp : _q_io_deq_bits_0_cmd_status_spp; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mpie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mpie : _q_io_deq_bits_0_cmd_status_mpie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_ube = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_ube : _q_io_deq_bits_0_cmd_status_ube; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_spie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_spie : _q_io_deq_bits_0_cmd_status_spie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_upie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_upie : _q_io_deq_bits_0_cmd_status_upie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_mie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_mie : _q_io_deq_bits_0_cmd_status_mie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_hie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_hie : _q_io_deq_bits_0_cmd_status_hie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_sie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_sie : _q_io_deq_bits_0_cmd_status_sie; // @[Mux.scala:126:16] wire _io_out_bits_T_3_cmd_status_uie = _io_out_bits_T_2 ? second_preload_cmd_cmd_status_uie : _q_io_deq_bits_0_cmd_status_uie; // @[Mux.scala:126:16] wire [5:0] _io_out_bits_T_3_rob_id_bits = _io_out_bits_T_2 ? second_preload_cmd_rob_id_bits : _q_io_deq_bits_0_rob_id_bits; // @[Mux.scala:126:16] wire _io_out_bits_T_3_from_matmul_fsm = _io_out_bits_T_2 ? second_preload_cmd_from_matmul_fsm : _q_io_deq_bits_0_from_matmul_fsm; // @[Mux.scala:126:16] wire _io_out_bits_T_3_from_conv_fsm = _io_out_bits_T_2 ? second_preload_cmd_from_conv_fsm : _q_io_deq_bits_0_from_conv_fsm; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_4_cmd_inst_funct = _io_out_bits_T_1 ? 7'h5 : _io_out_bits_T_3_cmd_inst_funct; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_4_cmd_inst_rs2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_rs2 : _io_out_bits_T_3_cmd_inst_rs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_4_cmd_inst_rs1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_rs1 : _io_out_bits_T_3_cmd_inst_rs1; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_inst_xd = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_xd : _io_out_bits_T_3_cmd_inst_xd; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_inst_xs1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_xs1 : _io_out_bits_T_3_cmd_inst_xs1; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_inst_xs2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_xs2 : _io_out_bits_T_3_cmd_inst_xs2; // @[Mux.scala:126:16] wire [4:0] _io_out_bits_T_4_cmd_inst_rd = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_rd : _io_out_bits_T_3_cmd_inst_rd; // @[Mux.scala:126:16] wire [6:0] _io_out_bits_T_4_cmd_inst_opcode = _io_out_bits_T_1 ? first_compute_cmd_cmd_inst_opcode : _io_out_bits_T_3_cmd_inst_opcode; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_4_cmd_rs1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_rs1 : _io_out_bits_T_3_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_out_bits_T_4_cmd_rs2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_rs2 : _io_out_bits_T_3_cmd_rs2; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_debug = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_debug : _io_out_bits_T_3_cmd_status_debug; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_cease = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_cease : _io_out_bits_T_3_cmd_status_cease; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_wfi = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_wfi : _io_out_bits_T_3_cmd_status_wfi; // @[Mux.scala:126:16] wire [31:0] _io_out_bits_T_4_cmd_status_isa = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_isa : _io_out_bits_T_3_cmd_status_isa; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_dprv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_dprv : _io_out_bits_T_3_cmd_status_dprv; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_dv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_dv : _io_out_bits_T_3_cmd_status_dv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_prv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_prv : _io_out_bits_T_3_cmd_status_prv; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_v = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_v : _io_out_bits_T_3_cmd_status_v; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sd = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sd : _io_out_bits_T_3_cmd_status_sd; // @[Mux.scala:126:16] wire [22:0] _io_out_bits_T_4_cmd_status_zero2 = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_zero2 : _io_out_bits_T_3_cmd_status_zero2; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mpv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mpv : _io_out_bits_T_3_cmd_status_mpv; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_gva = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_gva : _io_out_bits_T_3_cmd_status_gva; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mbe = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mbe : _io_out_bits_T_3_cmd_status_mbe; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sbe = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sbe : _io_out_bits_T_3_cmd_status_sbe; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_sxl = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sxl : _io_out_bits_T_3_cmd_status_sxl; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_uxl = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_uxl : _io_out_bits_T_3_cmd_status_uxl; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sd_rv32 = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sd_rv32 : _io_out_bits_T_3_cmd_status_sd_rv32; // @[Mux.scala:126:16] wire [7:0] _io_out_bits_T_4_cmd_status_zero1 = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_zero1 : _io_out_bits_T_3_cmd_status_zero1; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_tsr = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_tsr : _io_out_bits_T_3_cmd_status_tsr; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_tw = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_tw : _io_out_bits_T_3_cmd_status_tw; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_tvm = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_tvm : _io_out_bits_T_3_cmd_status_tvm; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mxr = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mxr : _io_out_bits_T_3_cmd_status_mxr; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sum = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sum : _io_out_bits_T_3_cmd_status_sum; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mprv = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mprv : _io_out_bits_T_3_cmd_status_mprv; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_xs = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_xs : _io_out_bits_T_3_cmd_status_xs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_fs = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_fs : _io_out_bits_T_3_cmd_status_fs; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_mpp = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mpp : _io_out_bits_T_3_cmd_status_mpp; // @[Mux.scala:126:16] wire [1:0] _io_out_bits_T_4_cmd_status_vs = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_vs : _io_out_bits_T_3_cmd_status_vs; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_spp = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_spp : _io_out_bits_T_3_cmd_status_spp; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mpie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mpie : _io_out_bits_T_3_cmd_status_mpie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_ube = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_ube : _io_out_bits_T_3_cmd_status_ube; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_spie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_spie : _io_out_bits_T_3_cmd_status_spie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_upie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_upie : _io_out_bits_T_3_cmd_status_upie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_mie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_mie : _io_out_bits_T_3_cmd_status_mie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_hie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_hie : _io_out_bits_T_3_cmd_status_hie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_sie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_sie : _io_out_bits_T_3_cmd_status_sie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_cmd_status_uie = _io_out_bits_T_1 ? first_compute_cmd_cmd_status_uie : _io_out_bits_T_3_cmd_status_uie; // @[Mux.scala:126:16] wire _io_out_bits_T_4_rob_id_valid = ~_io_out_bits_T_1; // @[Mux.scala:126:16] wire [5:0] _io_out_bits_T_4_rob_id_bits = _io_out_bits_T_1 ? first_compute_cmd_rob_id_bits : _io_out_bits_T_3_rob_id_bits; // @[Mux.scala:126:16] wire _io_out_bits_T_4_from_matmul_fsm = _io_out_bits_T_1 ? first_compute_cmd_from_matmul_fsm : _io_out_bits_T_3_from_matmul_fsm; // @[Mux.scala:126:16] wire _io_out_bits_T_4_from_conv_fsm = _io_out_bits_T_1 ? first_compute_cmd_from_conv_fsm : _io_out_bits_T_3_from_conv_fsm; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_funct = _io_out_bits_T ? first_preload_cmd_cmd_inst_funct : _io_out_bits_T_4_cmd_inst_funct; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_rs2 = _io_out_bits_T ? first_preload_cmd_cmd_inst_rs2 : _io_out_bits_T_4_cmd_inst_rs2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_rs1 = _io_out_bits_T ? first_preload_cmd_cmd_inst_rs1 : _io_out_bits_T_4_cmd_inst_rs1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_xd = _io_out_bits_T ? first_preload_cmd_cmd_inst_xd : _io_out_bits_T_4_cmd_inst_xd; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_xs1 = _io_out_bits_T ? first_preload_cmd_cmd_inst_xs1 : _io_out_bits_T_4_cmd_inst_xs1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_xs2 = _io_out_bits_T ? first_preload_cmd_cmd_inst_xs2 : _io_out_bits_T_4_cmd_inst_xs2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_rd = _io_out_bits_T ? first_preload_cmd_cmd_inst_rd : _io_out_bits_T_4_cmd_inst_rd; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_inst_opcode = _io_out_bits_T ? first_preload_cmd_cmd_inst_opcode : _io_out_bits_T_4_cmd_inst_opcode; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_rs1 = _io_out_bits_T ? first_preload_cmd_cmd_rs1 : _io_out_bits_T_4_cmd_rs1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_rs2 = _io_out_bits_T ? first_preload_cmd_cmd_rs2 : _io_out_bits_T_4_cmd_rs2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_debug = _io_out_bits_T ? first_preload_cmd_cmd_status_debug : _io_out_bits_T_4_cmd_status_debug; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_cease = _io_out_bits_T ? first_preload_cmd_cmd_status_cease : _io_out_bits_T_4_cmd_status_cease; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_wfi = _io_out_bits_T ? first_preload_cmd_cmd_status_wfi : _io_out_bits_T_4_cmd_status_wfi; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_isa = _io_out_bits_T ? first_preload_cmd_cmd_status_isa : _io_out_bits_T_4_cmd_status_isa; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_dprv = _io_out_bits_T ? first_preload_cmd_cmd_status_dprv : _io_out_bits_T_4_cmd_status_dprv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_dv = _io_out_bits_T ? first_preload_cmd_cmd_status_dv : _io_out_bits_T_4_cmd_status_dv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_prv = _io_out_bits_T ? first_preload_cmd_cmd_status_prv : _io_out_bits_T_4_cmd_status_prv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_v = _io_out_bits_T ? first_preload_cmd_cmd_status_v : _io_out_bits_T_4_cmd_status_v; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sd = _io_out_bits_T ? first_preload_cmd_cmd_status_sd : _io_out_bits_T_4_cmd_status_sd; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_zero2 = _io_out_bits_T ? first_preload_cmd_cmd_status_zero2 : _io_out_bits_T_4_cmd_status_zero2; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mpv = _io_out_bits_T ? first_preload_cmd_cmd_status_mpv : _io_out_bits_T_4_cmd_status_mpv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_gva = _io_out_bits_T ? first_preload_cmd_cmd_status_gva : _io_out_bits_T_4_cmd_status_gva; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mbe = _io_out_bits_T ? first_preload_cmd_cmd_status_mbe : _io_out_bits_T_4_cmd_status_mbe; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sbe = _io_out_bits_T ? first_preload_cmd_cmd_status_sbe : _io_out_bits_T_4_cmd_status_sbe; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sxl = _io_out_bits_T ? first_preload_cmd_cmd_status_sxl : _io_out_bits_T_4_cmd_status_sxl; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_uxl = _io_out_bits_T ? first_preload_cmd_cmd_status_uxl : _io_out_bits_T_4_cmd_status_uxl; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sd_rv32 = _io_out_bits_T ? first_preload_cmd_cmd_status_sd_rv32 : _io_out_bits_T_4_cmd_status_sd_rv32; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_zero1 = _io_out_bits_T ? first_preload_cmd_cmd_status_zero1 : _io_out_bits_T_4_cmd_status_zero1; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_tsr = _io_out_bits_T ? first_preload_cmd_cmd_status_tsr : _io_out_bits_T_4_cmd_status_tsr; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_tw = _io_out_bits_T ? first_preload_cmd_cmd_status_tw : _io_out_bits_T_4_cmd_status_tw; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_tvm = _io_out_bits_T ? first_preload_cmd_cmd_status_tvm : _io_out_bits_T_4_cmd_status_tvm; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mxr = _io_out_bits_T ? first_preload_cmd_cmd_status_mxr : _io_out_bits_T_4_cmd_status_mxr; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sum = _io_out_bits_T ? first_preload_cmd_cmd_status_sum : _io_out_bits_T_4_cmd_status_sum; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mprv = _io_out_bits_T ? first_preload_cmd_cmd_status_mprv : _io_out_bits_T_4_cmd_status_mprv; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_xs = _io_out_bits_T ? first_preload_cmd_cmd_status_xs : _io_out_bits_T_4_cmd_status_xs; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_fs = _io_out_bits_T ? first_preload_cmd_cmd_status_fs : _io_out_bits_T_4_cmd_status_fs; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mpp = _io_out_bits_T ? first_preload_cmd_cmd_status_mpp : _io_out_bits_T_4_cmd_status_mpp; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_vs = _io_out_bits_T ? first_preload_cmd_cmd_status_vs : _io_out_bits_T_4_cmd_status_vs; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_spp = _io_out_bits_T ? first_preload_cmd_cmd_status_spp : _io_out_bits_T_4_cmd_status_spp; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mpie = _io_out_bits_T ? first_preload_cmd_cmd_status_mpie : _io_out_bits_T_4_cmd_status_mpie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_ube = _io_out_bits_T ? first_preload_cmd_cmd_status_ube : _io_out_bits_T_4_cmd_status_ube; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_spie = _io_out_bits_T ? first_preload_cmd_cmd_status_spie : _io_out_bits_T_4_cmd_status_spie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_upie = _io_out_bits_T ? first_preload_cmd_cmd_status_upie : _io_out_bits_T_4_cmd_status_upie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_mie = _io_out_bits_T ? first_preload_cmd_cmd_status_mie : _io_out_bits_T_4_cmd_status_mie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_hie = _io_out_bits_T ? first_preload_cmd_cmd_status_hie : _io_out_bits_T_4_cmd_status_hie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_sie = _io_out_bits_T ? first_preload_cmd_cmd_status_sie : _io_out_bits_T_4_cmd_status_sie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_cmd_status_uie = _io_out_bits_T ? first_preload_cmd_cmd_status_uie : _io_out_bits_T_4_cmd_status_uie; // @[Mux.scala:126:16] assign _io_out_bits_T_5_rob_id_valid = ~_io_out_bits_T & _io_out_bits_T_4_rob_id_valid; // @[Mux.scala:126:16] assign _io_out_bits_T_5_rob_id_bits = _io_out_bits_T ? first_preload_cmd_rob_id_bits : _io_out_bits_T_4_rob_id_bits; // @[Mux.scala:126:16] assign _io_out_bits_T_5_from_matmul_fsm = _io_out_bits_T ? first_preload_cmd_from_matmul_fsm : _io_out_bits_T_4_from_matmul_fsm; // @[Mux.scala:126:16] assign _io_out_bits_T_5_from_conv_fsm = _io_out_bits_T ? first_preload_cmd_from_conv_fsm : _io_out_bits_T_4_from_conv_fsm; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_funct_0 = _io_out_bits_T_5_cmd_inst_funct; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_rs2_0 = _io_out_bits_T_5_cmd_inst_rs2; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_rs1_0 = _io_out_bits_T_5_cmd_inst_rs1; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_xd_0 = _io_out_bits_T_5_cmd_inst_xd; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_xs1_0 = _io_out_bits_T_5_cmd_inst_xs1; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_xs2_0 = _io_out_bits_T_5_cmd_inst_xs2; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_rd_0 = _io_out_bits_T_5_cmd_inst_rd; // @[Mux.scala:126:16] assign io_out_bits_cmd_inst_opcode_0 = _io_out_bits_T_5_cmd_inst_opcode; // @[Mux.scala:126:16] assign io_out_bits_cmd_rs1_0 = _io_out_bits_T_5_cmd_rs1; // @[Mux.scala:126:16] assign io_out_bits_cmd_rs2_0 = _io_out_bits_T_5_cmd_rs2; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_debug_0 = _io_out_bits_T_5_cmd_status_debug; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_cease_0 = _io_out_bits_T_5_cmd_status_cease; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_wfi_0 = _io_out_bits_T_5_cmd_status_wfi; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_isa_0 = _io_out_bits_T_5_cmd_status_isa; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_dprv_0 = _io_out_bits_T_5_cmd_status_dprv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_dv_0 = _io_out_bits_T_5_cmd_status_dv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_prv_0 = _io_out_bits_T_5_cmd_status_prv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_v_0 = _io_out_bits_T_5_cmd_status_v; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sd_0 = _io_out_bits_T_5_cmd_status_sd; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_zero2_0 = _io_out_bits_T_5_cmd_status_zero2; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mpv_0 = _io_out_bits_T_5_cmd_status_mpv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_gva_0 = _io_out_bits_T_5_cmd_status_gva; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mbe_0 = _io_out_bits_T_5_cmd_status_mbe; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sbe_0 = _io_out_bits_T_5_cmd_status_sbe; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sxl_0 = _io_out_bits_T_5_cmd_status_sxl; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_uxl_0 = _io_out_bits_T_5_cmd_status_uxl; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sd_rv32_0 = _io_out_bits_T_5_cmd_status_sd_rv32; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_zero1_0 = _io_out_bits_T_5_cmd_status_zero1; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_tsr_0 = _io_out_bits_T_5_cmd_status_tsr; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_tw_0 = _io_out_bits_T_5_cmd_status_tw; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_tvm_0 = _io_out_bits_T_5_cmd_status_tvm; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mxr_0 = _io_out_bits_T_5_cmd_status_mxr; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sum_0 = _io_out_bits_T_5_cmd_status_sum; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mprv_0 = _io_out_bits_T_5_cmd_status_mprv; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_xs_0 = _io_out_bits_T_5_cmd_status_xs; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_fs_0 = _io_out_bits_T_5_cmd_status_fs; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mpp_0 = _io_out_bits_T_5_cmd_status_mpp; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_vs_0 = _io_out_bits_T_5_cmd_status_vs; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_spp_0 = _io_out_bits_T_5_cmd_status_spp; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mpie_0 = _io_out_bits_T_5_cmd_status_mpie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_ube_0 = _io_out_bits_T_5_cmd_status_ube; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_spie_0 = _io_out_bits_T_5_cmd_status_spie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_upie_0 = _io_out_bits_T_5_cmd_status_upie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_mie_0 = _io_out_bits_T_5_cmd_status_mie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_hie_0 = _io_out_bits_T_5_cmd_status_hie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_sie_0 = _io_out_bits_T_5_cmd_status_sie; // @[Mux.scala:126:16] assign io_out_bits_cmd_status_uie_0 = _io_out_bits_T_5_cmd_status_uie; // @[Mux.scala:126:16] assign io_out_bits_rob_id_valid_0 = _io_out_bits_T_5_rob_id_valid; // @[Mux.scala:126:16] assign io_out_bits_rob_id_bits_0 = _io_out_bits_T_5_rob_id_bits; // @[Mux.scala:126:16] assign io_out_bits_from_matmul_fsm_0 = _io_out_bits_T_5_from_matmul_fsm; // @[Mux.scala:126:16] assign io_out_bits_from_conv_fsm_0 = _io_out_bits_T_5_from_conv_fsm; // @[Mux.scala:126:16] wire _q_io_deq_pop_T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] wire _q_io_deq_pop_T_2 = ~_q_io_deq_pop_T_1; // @[TransposePreloadUnroller.scala:67:{31,47}] wire _q_io_deq_pop_T_3 = _q_io_deq_pop_T & _q_io_deq_pop_T_2; // @[Decoupled.scala:51:35] wire _q_io_deq_pop_T_4 = state != 2'h1; // @[TransposePreloadUnroller.scala:25:22, :58:12, :67:75] wire _q_io_deq_pop_T_5 = _q_io_deq_pop_T_3 & _q_io_deq_pop_T_4; // @[TransposePreloadUnroller.scala:67:{28,66,75}] wire _q_io_deq_pop_T_6 = _q_io_deq_pop_T_5; // @[TransposePreloadUnroller.scala:67:{15,66}] wire set_only_strides = _q_io_deq_bits_0_cmd_rs1[7]; // @[TransposePreloadUnroller.scala:71:45] wire _b_transposed_and_ws_T = _q_io_deq_bits_0_cmd_rs1[2]; // @[TransposePreloadUnroller.scala:73:79] wire _b_transposed_and_ws_T_1 = _b_transposed_and_ws_T; // @[TransposePreloadUnroller.scala:73:{79,83}] wire _b_transposed_and_ws_T_3 = _q_io_deq_bits_0_cmd_rs1[9]; // @[TransposePreloadUnroller.scala:73:123] wire _b_transposed_and_ws_T_4 = _b_transposed_and_ws_T_3; // @[TransposePreloadUnroller.scala:73:{105,123}] wire [1:0] _state_T_3 = {_state_T_1, 1'h0}; // @[TransposePreloadUnroller.scala:78:22] wire [1:0] _state_T_4 = _state_T ? 2'h1 : _state_T_3; // @[TransposePreloadUnroller.scala:58:12, :78:22] assign io_counter_event_signal_44 = |state; // @[TransposePreloadUnroller.scala:9:7, :25:22, :83:94] always @(posedge clock) begin // @[TransposePreloadUnroller.scala:9:7] if (reset) // @[TransposePreloadUnroller.scala:9:7] state <= 2'h0; // @[TransposePreloadUnroller.scala:25:22] else if (~_q_io_deq_pop_T | is_config) begin // @[Decoupled.scala:51:35] end else if (_T_2) // @[TransposePreloadUnroller.scala:62:20] state <= 2'h1; // @[TransposePreloadUnroller.scala:25:22, :58:12] else if (|state) // @[TransposePreloadUnroller.scala:25:22, :77:23] state <= _state_T_4; // @[TransposePreloadUnroller.scala:25:22, :78:22] if (_q_io_deq_pop_T & is_config & ~set_only_strides) // @[Decoupled.scala:51:35] b_transposed_and_ws <= _b_transposed_and_ws_T_4; // @[TransposePreloadUnroller.scala:37:32, :73:105] always @(posedge) MultiHeadedQueue q ( // @[MultiHeadedQueue.scala:53:19] .clock (clock), .reset (reset), .io_enq_ready (io_in_ready_0), .io_enq_valid (io_in_valid_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_funct (io_in_bits_cmd_inst_funct_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_rs2 (io_in_bits_cmd_inst_rs2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_rs1 (io_in_bits_cmd_inst_rs1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_xd (io_in_bits_cmd_inst_xd_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_xs1 (io_in_bits_cmd_inst_xs1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_xs2 (io_in_bits_cmd_inst_xs2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_rd (io_in_bits_cmd_inst_rd_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_inst_opcode (io_in_bits_cmd_inst_opcode_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_rs1 (io_in_bits_cmd_rs1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_rs2 (io_in_bits_cmd_rs2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_debug (io_in_bits_cmd_status_debug_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_cease (io_in_bits_cmd_status_cease_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_wfi (io_in_bits_cmd_status_wfi_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_isa (io_in_bits_cmd_status_isa_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_dprv (io_in_bits_cmd_status_dprv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_dv (io_in_bits_cmd_status_dv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_prv (io_in_bits_cmd_status_prv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_v (io_in_bits_cmd_status_v_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sd (io_in_bits_cmd_status_sd_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_zero2 (io_in_bits_cmd_status_zero2_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mpv (io_in_bits_cmd_status_mpv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_gva (io_in_bits_cmd_status_gva_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mbe (io_in_bits_cmd_status_mbe_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sbe (io_in_bits_cmd_status_sbe_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sxl (io_in_bits_cmd_status_sxl_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_uxl (io_in_bits_cmd_status_uxl_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sd_rv32 (io_in_bits_cmd_status_sd_rv32_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_zero1 (io_in_bits_cmd_status_zero1_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_tsr (io_in_bits_cmd_status_tsr_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_tw (io_in_bits_cmd_status_tw_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_tvm (io_in_bits_cmd_status_tvm_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mxr (io_in_bits_cmd_status_mxr_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sum (io_in_bits_cmd_status_sum_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mprv (io_in_bits_cmd_status_mprv_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_xs (io_in_bits_cmd_status_xs_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_fs (io_in_bits_cmd_status_fs_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mpp (io_in_bits_cmd_status_mpp_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_vs (io_in_bits_cmd_status_vs_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_spp (io_in_bits_cmd_status_spp_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mpie (io_in_bits_cmd_status_mpie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_ube (io_in_bits_cmd_status_ube_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_spie (io_in_bits_cmd_status_spie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_upie (io_in_bits_cmd_status_upie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_mie (io_in_bits_cmd_status_mie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_hie (io_in_bits_cmd_status_hie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_sie (io_in_bits_cmd_status_sie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_cmd_status_uie (io_in_bits_cmd_status_uie_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_rob_id_bits (io_in_bits_rob_id_bits_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_from_matmul_fsm (io_in_bits_from_matmul_fsm_0), // @[TransposePreloadUnroller.scala:9:7] .io_enq_bits_from_conv_fsm (io_in_bits_from_conv_fsm_0), // @[TransposePreloadUnroller.scala:9:7] .io_deq_valid_0 (_q_io_deq_valid_0), .io_deq_valid_1 (_q_io_deq_valid_1), .io_deq_bits_0_cmd_inst_funct (_q_io_deq_bits_0_cmd_inst_funct), .io_deq_bits_0_cmd_inst_rs2 (_q_io_deq_bits_0_cmd_inst_rs2), .io_deq_bits_0_cmd_inst_rs1 (_q_io_deq_bits_0_cmd_inst_rs1), .io_deq_bits_0_cmd_inst_xd (_q_io_deq_bits_0_cmd_inst_xd), .io_deq_bits_0_cmd_inst_xs1 (_q_io_deq_bits_0_cmd_inst_xs1), .io_deq_bits_0_cmd_inst_xs2 (_q_io_deq_bits_0_cmd_inst_xs2), .io_deq_bits_0_cmd_inst_rd (_q_io_deq_bits_0_cmd_inst_rd), .io_deq_bits_0_cmd_inst_opcode (_q_io_deq_bits_0_cmd_inst_opcode), .io_deq_bits_0_cmd_rs1 (_q_io_deq_bits_0_cmd_rs1), .io_deq_bits_0_cmd_rs2 (_q_io_deq_bits_0_cmd_rs2), .io_deq_bits_0_cmd_status_debug (_q_io_deq_bits_0_cmd_status_debug), .io_deq_bits_0_cmd_status_cease (_q_io_deq_bits_0_cmd_status_cease), .io_deq_bits_0_cmd_status_wfi (_q_io_deq_bits_0_cmd_status_wfi), .io_deq_bits_0_cmd_status_isa (_q_io_deq_bits_0_cmd_status_isa), .io_deq_bits_0_cmd_status_dprv (_q_io_deq_bits_0_cmd_status_dprv), .io_deq_bits_0_cmd_status_dv (_q_io_deq_bits_0_cmd_status_dv), .io_deq_bits_0_cmd_status_prv (_q_io_deq_bits_0_cmd_status_prv), .io_deq_bits_0_cmd_status_v (_q_io_deq_bits_0_cmd_status_v), .io_deq_bits_0_cmd_status_sd (_q_io_deq_bits_0_cmd_status_sd), .io_deq_bits_0_cmd_status_zero2 (_q_io_deq_bits_0_cmd_status_zero2), .io_deq_bits_0_cmd_status_mpv (_q_io_deq_bits_0_cmd_status_mpv), .io_deq_bits_0_cmd_status_gva (_q_io_deq_bits_0_cmd_status_gva), .io_deq_bits_0_cmd_status_mbe (_q_io_deq_bits_0_cmd_status_mbe), .io_deq_bits_0_cmd_status_sbe (_q_io_deq_bits_0_cmd_status_sbe), .io_deq_bits_0_cmd_status_sxl (_q_io_deq_bits_0_cmd_status_sxl), .io_deq_bits_0_cmd_status_uxl (_q_io_deq_bits_0_cmd_status_uxl), .io_deq_bits_0_cmd_status_sd_rv32 (_q_io_deq_bits_0_cmd_status_sd_rv32), .io_deq_bits_0_cmd_status_zero1 (_q_io_deq_bits_0_cmd_status_zero1), .io_deq_bits_0_cmd_status_tsr (_q_io_deq_bits_0_cmd_status_tsr), .io_deq_bits_0_cmd_status_tw (_q_io_deq_bits_0_cmd_status_tw), .io_deq_bits_0_cmd_status_tvm (_q_io_deq_bits_0_cmd_status_tvm), .io_deq_bits_0_cmd_status_mxr (_q_io_deq_bits_0_cmd_status_mxr), .io_deq_bits_0_cmd_status_sum (_q_io_deq_bits_0_cmd_status_sum), .io_deq_bits_0_cmd_status_mprv (_q_io_deq_bits_0_cmd_status_mprv), .io_deq_bits_0_cmd_status_xs (_q_io_deq_bits_0_cmd_status_xs), .io_deq_bits_0_cmd_status_fs (_q_io_deq_bits_0_cmd_status_fs), .io_deq_bits_0_cmd_status_mpp (_q_io_deq_bits_0_cmd_status_mpp), .io_deq_bits_0_cmd_status_vs (_q_io_deq_bits_0_cmd_status_vs), .io_deq_bits_0_cmd_status_spp (_q_io_deq_bits_0_cmd_status_spp), .io_deq_bits_0_cmd_status_mpie (_q_io_deq_bits_0_cmd_status_mpie), .io_deq_bits_0_cmd_status_ube (_q_io_deq_bits_0_cmd_status_ube), .io_deq_bits_0_cmd_status_spie (_q_io_deq_bits_0_cmd_status_spie), .io_deq_bits_0_cmd_status_upie (_q_io_deq_bits_0_cmd_status_upie), .io_deq_bits_0_cmd_status_mie (_q_io_deq_bits_0_cmd_status_mie), .io_deq_bits_0_cmd_status_hie (_q_io_deq_bits_0_cmd_status_hie), .io_deq_bits_0_cmd_status_sie (_q_io_deq_bits_0_cmd_status_sie), .io_deq_bits_0_cmd_status_uie (_q_io_deq_bits_0_cmd_status_uie), .io_deq_bits_0_rob_id_bits (_q_io_deq_bits_0_rob_id_bits), .io_deq_bits_0_from_matmul_fsm (_q_io_deq_bits_0_from_matmul_fsm), .io_deq_bits_0_from_conv_fsm (_q_io_deq_bits_0_from_conv_fsm), .io_deq_bits_1_cmd_inst_funct (_q_io_deq_bits_1_cmd_inst_funct), .io_deq_bits_1_cmd_inst_xd (first_compute_cmd_cmd_inst_xd), .io_deq_bits_1_cmd_inst_xs1 (first_compute_cmd_cmd_inst_xs1), .io_deq_bits_1_cmd_inst_xs2 (first_compute_cmd_cmd_inst_xs2), .io_deq_bits_1_cmd_inst_rd (first_compute_cmd_cmd_inst_rd), .io_deq_bits_1_cmd_inst_opcode (first_compute_cmd_cmd_inst_opcode), .io_deq_bits_1_cmd_rs1 (_q_io_deq_bits_1_cmd_rs1), .io_deq_bits_1_cmd_rs2 (_q_io_deq_bits_1_cmd_rs2), .io_deq_bits_1_cmd_status_debug (first_compute_cmd_cmd_status_debug), .io_deq_bits_1_cmd_status_cease (first_compute_cmd_cmd_status_cease), .io_deq_bits_1_cmd_status_wfi (first_compute_cmd_cmd_status_wfi), .io_deq_bits_1_cmd_status_isa (first_compute_cmd_cmd_status_isa), .io_deq_bits_1_cmd_status_dprv (first_compute_cmd_cmd_status_dprv), .io_deq_bits_1_cmd_status_dv (first_compute_cmd_cmd_status_dv), .io_deq_bits_1_cmd_status_prv (first_compute_cmd_cmd_status_prv), .io_deq_bits_1_cmd_status_v (first_compute_cmd_cmd_status_v), .io_deq_bits_1_cmd_status_sd (first_compute_cmd_cmd_status_sd), .io_deq_bits_1_cmd_status_zero2 (first_compute_cmd_cmd_status_zero2), .io_deq_bits_1_cmd_status_mpv (first_compute_cmd_cmd_status_mpv), .io_deq_bits_1_cmd_status_gva (first_compute_cmd_cmd_status_gva), .io_deq_bits_1_cmd_status_mbe (first_compute_cmd_cmd_status_mbe), .io_deq_bits_1_cmd_status_sbe (first_compute_cmd_cmd_status_sbe), .io_deq_bits_1_cmd_status_sxl (first_compute_cmd_cmd_status_sxl), .io_deq_bits_1_cmd_status_uxl (first_compute_cmd_cmd_status_uxl), .io_deq_bits_1_cmd_status_sd_rv32 (first_compute_cmd_cmd_status_sd_rv32), .io_deq_bits_1_cmd_status_zero1 (first_compute_cmd_cmd_status_zero1), .io_deq_bits_1_cmd_status_tsr (first_compute_cmd_cmd_status_tsr), .io_deq_bits_1_cmd_status_tw (first_compute_cmd_cmd_status_tw), .io_deq_bits_1_cmd_status_tvm (first_compute_cmd_cmd_status_tvm), .io_deq_bits_1_cmd_status_mxr (first_compute_cmd_cmd_status_mxr), .io_deq_bits_1_cmd_status_sum (first_compute_cmd_cmd_status_sum), .io_deq_bits_1_cmd_status_mprv (first_compute_cmd_cmd_status_mprv), .io_deq_bits_1_cmd_status_xs (first_compute_cmd_cmd_status_xs), .io_deq_bits_1_cmd_status_fs (first_compute_cmd_cmd_status_fs), .io_deq_bits_1_cmd_status_mpp (first_compute_cmd_cmd_status_mpp), .io_deq_bits_1_cmd_status_vs (first_compute_cmd_cmd_status_vs), .io_deq_bits_1_cmd_status_spp (first_compute_cmd_cmd_status_spp), .io_deq_bits_1_cmd_status_mpie (first_compute_cmd_cmd_status_mpie), .io_deq_bits_1_cmd_status_ube (first_compute_cmd_cmd_status_ube), .io_deq_bits_1_cmd_status_spie (first_compute_cmd_cmd_status_spie), .io_deq_bits_1_cmd_status_upie (first_compute_cmd_cmd_status_upie), .io_deq_bits_1_cmd_status_mie (first_compute_cmd_cmd_status_mie), .io_deq_bits_1_cmd_status_hie (first_compute_cmd_cmd_status_hie), .io_deq_bits_1_cmd_status_sie (first_compute_cmd_cmd_status_sie), .io_deq_bits_1_cmd_status_uie (first_compute_cmd_cmd_status_uie), .io_deq_bits_1_rob_id_bits (first_compute_cmd_rob_id_bits), .io_deq_bits_1_from_matmul_fsm (first_compute_cmd_from_matmul_fsm), .io_deq_bits_1_from_conv_fsm (first_compute_cmd_from_conv_fsm), .io_deq_pop (_q_io_deq_pop_T_6) // @[TransposePreloadUnroller.scala:67:15] ); // @[MultiHeadedQueue.scala:53:19] assign first_preload_cmd_cmd_inst_funct = _q_io_deq_bits_0_cmd_inst_funct; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_rs2 = _q_io_deq_bits_0_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_rs1 = _q_io_deq_bits_0_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_xd = _q_io_deq_bits_0_cmd_inst_xd; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_xs1 = _q_io_deq_bits_0_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_xs2 = _q_io_deq_bits_0_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_rd = _q_io_deq_bits_0_cmd_inst_rd; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_inst_opcode = _q_io_deq_bits_0_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_rs1 = _q_io_deq_bits_0_cmd_rs1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_debug = _q_io_deq_bits_0_cmd_status_debug; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_cease = _q_io_deq_bits_0_cmd_status_cease; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_wfi = _q_io_deq_bits_0_cmd_status_wfi; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_isa = _q_io_deq_bits_0_cmd_status_isa; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_dprv = _q_io_deq_bits_0_cmd_status_dprv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_dv = _q_io_deq_bits_0_cmd_status_dv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_prv = _q_io_deq_bits_0_cmd_status_prv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_v = _q_io_deq_bits_0_cmd_status_v; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sd = _q_io_deq_bits_0_cmd_status_sd; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_zero2 = _q_io_deq_bits_0_cmd_status_zero2; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mpv = _q_io_deq_bits_0_cmd_status_mpv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_gva = _q_io_deq_bits_0_cmd_status_gva; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mbe = _q_io_deq_bits_0_cmd_status_mbe; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sbe = _q_io_deq_bits_0_cmd_status_sbe; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sxl = _q_io_deq_bits_0_cmd_status_sxl; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_uxl = _q_io_deq_bits_0_cmd_status_uxl; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sd_rv32 = _q_io_deq_bits_0_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_zero1 = _q_io_deq_bits_0_cmd_status_zero1; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_tsr = _q_io_deq_bits_0_cmd_status_tsr; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_tw = _q_io_deq_bits_0_cmd_status_tw; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_tvm = _q_io_deq_bits_0_cmd_status_tvm; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mxr = _q_io_deq_bits_0_cmd_status_mxr; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sum = _q_io_deq_bits_0_cmd_status_sum; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mprv = _q_io_deq_bits_0_cmd_status_mprv; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_xs = _q_io_deq_bits_0_cmd_status_xs; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_fs = _q_io_deq_bits_0_cmd_status_fs; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mpp = _q_io_deq_bits_0_cmd_status_mpp; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_vs = _q_io_deq_bits_0_cmd_status_vs; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_spp = _q_io_deq_bits_0_cmd_status_spp; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mpie = _q_io_deq_bits_0_cmd_status_mpie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_ube = _q_io_deq_bits_0_cmd_status_ube; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_spie = _q_io_deq_bits_0_cmd_status_spie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_upie = _q_io_deq_bits_0_cmd_status_upie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_mie = _q_io_deq_bits_0_cmd_status_mie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_hie = _q_io_deq_bits_0_cmd_status_hie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_sie = _q_io_deq_bits_0_cmd_status_sie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_cmd_status_uie = _q_io_deq_bits_0_cmd_status_uie; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_rob_id_bits = _q_io_deq_bits_0_rob_id_bits; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_from_matmul_fsm = _q_io_deq_bits_0_from_matmul_fsm; // @[TransposePreloadUnroller.scala:40:35] assign first_preload_cmd_from_conv_fsm = _q_io_deq_bits_0_from_conv_fsm; // @[TransposePreloadUnroller.scala:40:35] assign first_compute_cmd_cmd_rs1 = _q_io_deq_bits_1_cmd_rs1; // @[TransposePreloadUnroller.scala:44:35] assign first_compute_cmd_cmd_rs2 = _q_io_deq_bits_1_cmd_rs2; // @[TransposePreloadUnroller.scala:44:35] assign second_preload_cmd_cmd_inst_funct = _q_io_deq_bits_0_cmd_inst_funct; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_rs2 = _q_io_deq_bits_0_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_rs1 = _q_io_deq_bits_0_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_xd = _q_io_deq_bits_0_cmd_inst_xd; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_xs1 = _q_io_deq_bits_0_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_xs2 = _q_io_deq_bits_0_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_rd = _q_io_deq_bits_0_cmd_inst_rd; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_inst_opcode = _q_io_deq_bits_0_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_rs2 = _q_io_deq_bits_0_cmd_rs2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_debug = _q_io_deq_bits_0_cmd_status_debug; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_cease = _q_io_deq_bits_0_cmd_status_cease; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_wfi = _q_io_deq_bits_0_cmd_status_wfi; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_isa = _q_io_deq_bits_0_cmd_status_isa; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_dprv = _q_io_deq_bits_0_cmd_status_dprv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_dv = _q_io_deq_bits_0_cmd_status_dv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_prv = _q_io_deq_bits_0_cmd_status_prv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_v = _q_io_deq_bits_0_cmd_status_v; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sd = _q_io_deq_bits_0_cmd_status_sd; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_zero2 = _q_io_deq_bits_0_cmd_status_zero2; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mpv = _q_io_deq_bits_0_cmd_status_mpv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_gva = _q_io_deq_bits_0_cmd_status_gva; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mbe = _q_io_deq_bits_0_cmd_status_mbe; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sbe = _q_io_deq_bits_0_cmd_status_sbe; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sxl = _q_io_deq_bits_0_cmd_status_sxl; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_uxl = _q_io_deq_bits_0_cmd_status_uxl; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sd_rv32 = _q_io_deq_bits_0_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_zero1 = _q_io_deq_bits_0_cmd_status_zero1; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_tsr = _q_io_deq_bits_0_cmd_status_tsr; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_tw = _q_io_deq_bits_0_cmd_status_tw; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_tvm = _q_io_deq_bits_0_cmd_status_tvm; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mxr = _q_io_deq_bits_0_cmd_status_mxr; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sum = _q_io_deq_bits_0_cmd_status_sum; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mprv = _q_io_deq_bits_0_cmd_status_mprv; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_xs = _q_io_deq_bits_0_cmd_status_xs; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_fs = _q_io_deq_bits_0_cmd_status_fs; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mpp = _q_io_deq_bits_0_cmd_status_mpp; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_vs = _q_io_deq_bits_0_cmd_status_vs; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_spp = _q_io_deq_bits_0_cmd_status_spp; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mpie = _q_io_deq_bits_0_cmd_status_mpie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_ube = _q_io_deq_bits_0_cmd_status_ube; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_spie = _q_io_deq_bits_0_cmd_status_spie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_upie = _q_io_deq_bits_0_cmd_status_upie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_mie = _q_io_deq_bits_0_cmd_status_mie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_hie = _q_io_deq_bits_0_cmd_status_hie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_sie = _q_io_deq_bits_0_cmd_status_sie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_cmd_status_uie = _q_io_deq_bits_0_cmd_status_uie; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_rob_id_bits = _q_io_deq_bits_0_rob_id_bits; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_from_matmul_fsm = _q_io_deq_bits_0_from_matmul_fsm; // @[TransposePreloadUnroller.scala:50:36] assign second_preload_cmd_from_conv_fsm = _q_io_deq_bits_0_from_conv_fsm; // @[TransposePreloadUnroller.scala:50:36] assign io_in_ready = io_in_ready_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_valid = io_out_valid_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_funct = io_out_bits_cmd_inst_funct_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_rs2 = io_out_bits_cmd_inst_rs2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_rs1 = io_out_bits_cmd_inst_rs1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_xd = io_out_bits_cmd_inst_xd_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_xs1 = io_out_bits_cmd_inst_xs1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_xs2 = io_out_bits_cmd_inst_xs2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_rd = io_out_bits_cmd_inst_rd_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_inst_opcode = io_out_bits_cmd_inst_opcode_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_rs1 = io_out_bits_cmd_rs1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_rs2 = io_out_bits_cmd_rs2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_debug = io_out_bits_cmd_status_debug_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_cease = io_out_bits_cmd_status_cease_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_wfi = io_out_bits_cmd_status_wfi_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_isa = io_out_bits_cmd_status_isa_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_dprv = io_out_bits_cmd_status_dprv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_dv = io_out_bits_cmd_status_dv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_prv = io_out_bits_cmd_status_prv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_v = io_out_bits_cmd_status_v_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sd = io_out_bits_cmd_status_sd_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_zero2 = io_out_bits_cmd_status_zero2_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mpv = io_out_bits_cmd_status_mpv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_gva = io_out_bits_cmd_status_gva_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mbe = io_out_bits_cmd_status_mbe_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sbe = io_out_bits_cmd_status_sbe_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sxl = io_out_bits_cmd_status_sxl_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_uxl = io_out_bits_cmd_status_uxl_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sd_rv32 = io_out_bits_cmd_status_sd_rv32_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_zero1 = io_out_bits_cmd_status_zero1_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_tsr = io_out_bits_cmd_status_tsr_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_tw = io_out_bits_cmd_status_tw_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_tvm = io_out_bits_cmd_status_tvm_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mxr = io_out_bits_cmd_status_mxr_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sum = io_out_bits_cmd_status_sum_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mprv = io_out_bits_cmd_status_mprv_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_xs = io_out_bits_cmd_status_xs_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_fs = io_out_bits_cmd_status_fs_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mpp = io_out_bits_cmd_status_mpp_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_vs = io_out_bits_cmd_status_vs_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_spp = io_out_bits_cmd_status_spp_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mpie = io_out_bits_cmd_status_mpie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_ube = io_out_bits_cmd_status_ube_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_spie = io_out_bits_cmd_status_spie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_upie = io_out_bits_cmd_status_upie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_mie = io_out_bits_cmd_status_mie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_hie = io_out_bits_cmd_status_hie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_sie = io_out_bits_cmd_status_sie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_cmd_status_uie = io_out_bits_cmd_status_uie_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_rob_id_valid = io_out_bits_rob_id_valid_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_rob_id_bits = io_out_bits_rob_id_bits_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_from_matmul_fsm = io_out_bits_from_matmul_fsm_0; // @[TransposePreloadUnroller.scala:9:7] assign io_out_bits_from_conv_fsm = io_out_bits_from_conv_fsm_0; // @[TransposePreloadUnroller.scala:9:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SodorMasterAdapter : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip dport : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}} inst buffer of TLBuffer_a32d32s1k1z4u connect buffer.clock, clock connect buffer.reset, reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready connect nodeOut, nodeIn wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect buffer.auto.in, masterNodeOut connect buffer.auto.out.d, nodeIn.d connect nodeIn.a.bits, buffer.auto.out.a.bits connect nodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, nodeIn.a.ready connect auto.out, nodeOut regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg a_address_reg : UInt<32>, clock reg a_signed_reg : UInt<1>, clock reg req_address_reg : UInt<32>, clock reg req_size_reg : UInt<2>, clock reg req_data_reg : UInt<32>, clock node _a_signed_T = sub(io.dport.req.bits.typ, UInt<1>(0h1)) node _a_signed_T_1 = tail(_a_signed_T, 1) node _a_signed_T_2 = bits(_a_signed_T_1, 2, 2) node a_signed = not(_a_signed_T_2) node _a_size_T = sub(io.dport.req.bits.typ, UInt<1>(0h1)) node _a_size_T_1 = tail(_a_size_T, 1) node a_size = bits(_a_size_T_1, 1, 0) node _T = eq(state, UInt<2>(0h0)) node _T_1 = and(_T, io.dport.req.valid) when _T_1 : connect state, UInt<2>(0h1) connect req_address_reg, io.dport.req.bits.addr connect req_size_reg, a_size connect req_data_reg, io.dport.req.bits.data node _T_2 = eq(state, UInt<2>(0h1)) node _T_3 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) node _T_4 = and(_T_2, _T_3) when _T_4 : connect state, UInt<2>(0h2) node _T_5 = eq(state, UInt<2>(0h2)) node _T_6 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _T_7 = and(_T_5, _T_6) when _T_7 : connect state, UInt<2>(0h0) node _masterNodeOut_a_valid_T = eq(state, UInt<2>(0h1)) connect masterNodeOut.a.valid, _masterNodeOut_a_valid_T connect masterNodeOut.d.ready, UInt<1>(0h1) node _io_dport_req_ready_T = eq(state, UInt<2>(0h0)) connect io.dport.req.ready, _io_dport_req_ready_T connect io.dport.resp.valid, masterNodeOut.d.valid node _T_8 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_8 : connect a_address_reg, io.dport.req.bits.addr connect a_signed_reg, a_size node _legal_T = leq(UInt<1>(0h0), req_size_reg) node _legal_T_1 = leq(req_size_reg, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(req_address_reg, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h8a113000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), req_size_reg) node _legal_T_11 = leq(req_size_reg, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(req_address_reg, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h8a112000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(req_address_reg, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h8a110000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(req_address_reg, UInt<21>(0h100000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h8a103000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(req_address_reg, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h8a110000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(req_address_reg, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h88000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(req_address_reg, UInt<32>(0h80000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h8a100000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = or(_legal_T_18, _legal_T_23) node _legal_T_45 = or(_legal_T_44, _legal_T_28) node _legal_T_46 = or(_legal_T_45, _legal_T_33) node _legal_T_47 = or(_legal_T_46, _legal_T_38) node _legal_T_48 = or(_legal_T_47, _legal_T_43) node _legal_T_49 = and(_legal_T_13, _legal_T_48) node _legal_T_50 = or(UInt<1>(0h0), _legal_T_9) node legal_get = or(_legal_T_50, _legal_T_49) wire get_bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} connect get_bundle.opcode, UInt<3>(0h4) connect get_bundle.param, UInt<1>(0h0) connect get_bundle.size, req_size_reg connect get_bundle.source, UInt<1>(0h0) connect get_bundle.address, req_address_reg node _a_mask_sizeOH_T = or(req_size_reg, UInt<2>(0h0)) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_T, 0, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 1, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_0_1 = geq(req_size_reg, UInt<2>(0h2)) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(req_address_reg, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(req_address_reg, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_hi = cat(a_mask_acc_3, a_mask_acc_2) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect get_bundle.mask, _a_mask_T invalidate get_bundle.data connect get_bundle.corrupt, UInt<1>(0h0) node _legal_T_51 = leq(UInt<1>(0h0), req_size_reg) node _legal_T_52 = leq(req_size_reg, UInt<4>(0hc)) node _legal_T_53 = and(_legal_T_51, _legal_T_52) node _legal_T_54 = or(UInt<1>(0h0), _legal_T_53) node _legal_T_55 = xor(req_address_reg, UInt<14>(0h3000)) node _legal_T_56 = cvt(_legal_T_55) node _legal_T_57 = and(_legal_T_56, asSInt(UInt<33>(0h8a113000))) node _legal_T_58 = asSInt(_legal_T_57) node _legal_T_59 = eq(_legal_T_58, asSInt(UInt<1>(0h0))) node _legal_T_60 = and(_legal_T_54, _legal_T_59) node _legal_T_61 = leq(UInt<1>(0h0), req_size_reg) node _legal_T_62 = leq(req_size_reg, UInt<3>(0h6)) node _legal_T_63 = and(_legal_T_61, _legal_T_62) node _legal_T_64 = or(UInt<1>(0h0), _legal_T_63) node _legal_T_65 = xor(req_address_reg, UInt<1>(0h0)) node _legal_T_66 = cvt(_legal_T_65) node _legal_T_67 = and(_legal_T_66, asSInt(UInt<33>(0h8a112000))) node _legal_T_68 = asSInt(_legal_T_67) node _legal_T_69 = eq(_legal_T_68, asSInt(UInt<1>(0h0))) node _legal_T_70 = xor(req_address_reg, UInt<21>(0h100000)) node _legal_T_71 = cvt(_legal_T_70) node _legal_T_72 = and(_legal_T_71, asSInt(UInt<33>(0h8a103000))) node _legal_T_73 = asSInt(_legal_T_72) node _legal_T_74 = eq(_legal_T_73, asSInt(UInt<1>(0h0))) node _legal_T_75 = xor(req_address_reg, UInt<26>(0h2000000)) node _legal_T_76 = cvt(_legal_T_75) node _legal_T_77 = and(_legal_T_76, asSInt(UInt<33>(0h8a110000))) node _legal_T_78 = asSInt(_legal_T_77) node _legal_T_79 = eq(_legal_T_78, asSInt(UInt<1>(0h0))) node _legal_T_80 = xor(req_address_reg, UInt<28>(0h8000000)) node _legal_T_81 = cvt(_legal_T_80) node _legal_T_82 = and(_legal_T_81, asSInt(UInt<33>(0h88000000))) node _legal_T_83 = asSInt(_legal_T_82) node _legal_T_84 = eq(_legal_T_83, asSInt(UInt<1>(0h0))) node _legal_T_85 = xor(req_address_reg, UInt<32>(0h80000000)) node _legal_T_86 = cvt(_legal_T_85) node _legal_T_87 = and(_legal_T_86, asSInt(UInt<33>(0h8a100000))) node _legal_T_88 = asSInt(_legal_T_87) node _legal_T_89 = eq(_legal_T_88, asSInt(UInt<1>(0h0))) node _legal_T_90 = or(_legal_T_69, _legal_T_74) node _legal_T_91 = or(_legal_T_90, _legal_T_79) node _legal_T_92 = or(_legal_T_91, _legal_T_84) node _legal_T_93 = or(_legal_T_92, _legal_T_89) node _legal_T_94 = and(_legal_T_64, _legal_T_93) node _legal_T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_96 = xor(req_address_reg, UInt<17>(0h10000)) node _legal_T_97 = cvt(_legal_T_96) node _legal_T_98 = and(_legal_T_97, asSInt(UInt<33>(0h8a110000))) node _legal_T_99 = asSInt(_legal_T_98) node _legal_T_100 = eq(_legal_T_99, asSInt(UInt<1>(0h0))) node _legal_T_101 = and(_legal_T_95, _legal_T_100) node _legal_T_102 = or(UInt<1>(0h0), _legal_T_60) node _legal_T_103 = or(_legal_T_102, _legal_T_94) node legal_put = or(_legal_T_103, _legal_T_101) wire put_bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} connect put_bundle.opcode, UInt<1>(0h0) connect put_bundle.param, UInt<1>(0h0) connect put_bundle.size, req_size_reg connect put_bundle.source, UInt<1>(0h0) connect put_bundle.address, req_address_reg node _a_mask_sizeOH_T_3 = or(req_size_reg, UInt<2>(0h0)) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_T_3, 0, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 1, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_0_1_1 = geq(req_size_reg, UInt<2>(0h2)) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(req_address_reg, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_nbit_1) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_bit_1) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_3) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(req_address_reg, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_4 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_4 = and(a_mask_size_1, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_0_1_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_5 = and(a_mask_size_1, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_0_1_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_6 = and(a_mask_size_1, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_1_1_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_7 = and(a_mask_size_1, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_1_1_1, _a_mask_acc_T_7) node a_mask_lo_1 = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_hi_1 = cat(a_mask_acc_7, a_mask_acc_6) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect put_bundle.mask, _a_mask_T_1 connect put_bundle.data, req_data_reg connect put_bundle.corrupt, UInt<1>(0h0) node _masterNodeOut_a_bits_T = eq(io.dport.req.bits.fcn, UInt<1>(0h0)) node _masterNodeOut_a_bits_T_1 = mux(_masterNodeOut_a_bits_T, get_bundle, put_bundle) connect masterNodeOut.a.bits, _masterNodeOut_a_bits_T_1 wire io_dport_resp_bits_data_size : UInt<2> connect io_dport_resp_bits_data_size, masterNodeOut.d.bits.size node _io_dport_resp_bits_data_shifted_T = bits(a_address_reg, 1, 1) node _io_dport_resp_bits_data_shifted_T_1 = bits(masterNodeOut.d.bits.data, 31, 16) node _io_dport_resp_bits_data_shifted_T_2 = bits(masterNodeOut.d.bits.data, 15, 0) node io_dport_resp_bits_data_shifted = mux(_io_dport_resp_bits_data_shifted_T, _io_dport_resp_bits_data_shifted_T_1, _io_dport_resp_bits_data_shifted_T_2) node io_dport_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_dport_resp_bits_data_zeroed = mux(io_dport_resp_bits_data_doZero, UInt<1>(0h0), io_dport_resp_bits_data_shifted) node _io_dport_resp_bits_data_T = eq(io_dport_resp_bits_data_size, UInt<1>(0h1)) node _io_dport_resp_bits_data_T_1 = or(_io_dport_resp_bits_data_T, io_dport_resp_bits_data_doZero) node _io_dport_resp_bits_data_T_2 = bits(io_dport_resp_bits_data_zeroed, 15, 15) node _io_dport_resp_bits_data_T_3 = and(a_signed_reg, _io_dport_resp_bits_data_T_2) node _io_dport_resp_bits_data_T_4 = mux(_io_dport_resp_bits_data_T_3, UInt<16>(0hffff), UInt<16>(0h0)) node _io_dport_resp_bits_data_T_5 = bits(masterNodeOut.d.bits.data, 31, 16) node _io_dport_resp_bits_data_T_6 = mux(_io_dport_resp_bits_data_T_1, _io_dport_resp_bits_data_T_4, _io_dport_resp_bits_data_T_5) node _io_dport_resp_bits_data_T_7 = cat(_io_dport_resp_bits_data_T_6, io_dport_resp_bits_data_zeroed) node _io_dport_resp_bits_data_shifted_T_3 = bits(a_address_reg, 0, 0) node _io_dport_resp_bits_data_shifted_T_4 = bits(_io_dport_resp_bits_data_T_7, 15, 8) node _io_dport_resp_bits_data_shifted_T_5 = bits(_io_dport_resp_bits_data_T_7, 7, 0) node io_dport_resp_bits_data_shifted_1 = mux(_io_dport_resp_bits_data_shifted_T_3, _io_dport_resp_bits_data_shifted_T_4, _io_dport_resp_bits_data_shifted_T_5) node io_dport_resp_bits_data_doZero_1 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_dport_resp_bits_data_zeroed_1 = mux(io_dport_resp_bits_data_doZero_1, UInt<1>(0h0), io_dport_resp_bits_data_shifted_1) node _io_dport_resp_bits_data_T_8 = eq(io_dport_resp_bits_data_size, UInt<1>(0h0)) node _io_dport_resp_bits_data_T_9 = or(_io_dport_resp_bits_data_T_8, io_dport_resp_bits_data_doZero_1) node _io_dport_resp_bits_data_T_10 = bits(io_dport_resp_bits_data_zeroed_1, 7, 7) node _io_dport_resp_bits_data_T_11 = and(a_signed_reg, _io_dport_resp_bits_data_T_10) node _io_dport_resp_bits_data_T_12 = mux(_io_dport_resp_bits_data_T_11, UInt<24>(0hffffff), UInt<24>(0h0)) node _io_dport_resp_bits_data_T_13 = bits(_io_dport_resp_bits_data_T_7, 31, 8) node _io_dport_resp_bits_data_T_14 = mux(_io_dport_resp_bits_data_T_9, _io_dport_resp_bits_data_T_12, _io_dport_resp_bits_data_T_13) node _io_dport_resp_bits_data_T_15 = cat(_io_dport_resp_bits_data_T_14, io_dport_resp_bits_data_zeroed_1) connect io.dport.resp.bits.data, _io_dport_resp_bits_data_T_15 node _legal_op_T = eq(io.dport.req.bits.fcn, UInt<1>(0h0)) node legal_op = mux(_legal_op_T, legal_get, legal_put) node resp_xp = or(masterNodeOut.d.bits.corrupt, masterNodeOut.d.bits.denied) node _T_9 = eq(masterNodeOut.a.valid, UInt<1>(0h0)) node _T_10 = or(legal_op, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed: Illegal operation\n at master_adapter.scala:101 assert(legal_op | !tl_out.a.valid, \"Illegal operation\")\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = eq(resp_xp, UInt<1>(0h0)) node _T_15 = eq(masterNodeOut.d.valid, UInt<1>(0h0)) node _T_16 = or(_T_14, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: Responds exception\n at master_adapter.scala:102 assert(!resp_xp | !tl_out.d.valid, \"Responds exception\")\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_62 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_63 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module SodorMasterAdapter( // @[master_adapter.scala:38:7] input clock, // @[master_adapter.scala:38:7] input reset, // @[master_adapter.scala:38:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_dport_req_ready, // @[master_adapter.scala:41:14] input io_dport_req_valid, // @[master_adapter.scala:41:14] input [31:0] io_dport_req_bits_addr, // @[master_adapter.scala:41:14] output io_dport_resp_valid, // @[master_adapter.scala:41:14] output [31:0] io_dport_resp_bits_data // @[master_adapter.scala:41:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[master_adapter.scala:38:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[master_adapter.scala:38:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[master_adapter.scala:38:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[master_adapter.scala:38:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[master_adapter.scala:38:7] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[master_adapter.scala:38:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[master_adapter.scala:38:7] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[master_adapter.scala:38:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[master_adapter.scala:38:7] wire io_dport_req_valid_0 = io_dport_req_valid; // @[master_adapter.scala:38:7] wire [31:0] io_dport_req_bits_addr_0 = io_dport_req_bits_addr; // @[master_adapter.scala:38:7] wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _a_signed_T_2 = 1'h1; // @[memory.scala:61:33] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _legal_T_51 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_52 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_53 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_54 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_61 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_62 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_64 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _masterNodeOut_a_bits_T = 1'h1; // @[master_adapter.scala:92:46] wire _legal_op_T = 1'h1; // @[master_adapter.scala:98:44] wire [23:0] _io_dport_resp_bits_data_T_12 = 24'h0; // @[AMOALU.scala:45:49] wire auto_out_d_bits_source = 1'h0; // @[master_adapter.scala:38:7] wire io_dport_req_bits_fcn = 1'h0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire a_signed = 1'h0; // @[memory.scala:61:21] wire get_bundle_source = 1'h0; // @[Edges.scala:460:17] wire get_bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire a_mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _legal_T_95 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_101 = 1'h0; // @[Parameters.scala:684:54] wire put_bundle_source = 1'h0; // @[Edges.scala:480:17] wire put_bundle_corrupt = 1'h0; // @[Edges.scala:480:17] wire a_mask_sizeOH_shiftAmount_1 = 1'h0; // @[OneHot.scala:64:49] wire a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_T_1_source = 1'h0; // @[master_adapter.scala:92:23] wire _masterNodeOut_a_bits_T_1_corrupt = 1'h0; // @[master_adapter.scala:92:23] wire io_dport_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _io_dport_resp_bits_data_T_3 = 1'h0; // @[AMOALU.scala:45:72] wire io_dport_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire _io_dport_resp_bits_data_T_11 = 1'h0; // @[AMOALU.scala:45:72] wire [15:0] _io_dport_resp_bits_data_T_4 = 16'h0; // @[AMOALU.scala:45:49] wire [31:0] io_dport_req_bits_data = 32'h0; // @[master_adapter.scala:38:7] wire [31:0] masterNodeOut_a_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] get_bundle_data = 32'h0; // @[Edges.scala:460:17] wire [31:0] put_bundle_data = 32'h0; // @[Edges.scala:480:17] wire [31:0] _masterNodeOut_a_bits_T_1_data = 32'h0; // @[master_adapter.scala:92:23] wire [3:0] masterNodeOut_a_bits_mask = 4'hF; // @[MixedNode.scala:542:17] wire [3:0] get_bundle_mask = 4'hF; // @[Edges.scala:460:17] wire [3:0] _a_mask_T = 4'hF; // @[Misc.scala:222:10] wire [3:0] put_bundle_mask = 4'hF; // @[Edges.scala:480:17] wire [3:0] _a_mask_T_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] _masterNodeOut_a_bits_T_1_mask = 4'hF; // @[master_adapter.scala:92:23] wire [3:0] masterNodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] get_bundle_size = 4'h2; // @[Edges.scala:460:17] wire [3:0] put_bundle_size = 4'h2; // @[Edges.scala:480:17] wire [3:0] _masterNodeOut_a_bits_T_1_size = 4'h2; // @[master_adapter.scala:92:23] wire [1:0] a_mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _a_mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] a_mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_mask_sizeOH_T_4 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _a_mask_sizeOH_T_5 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] a_mask_sizeOH_1 = 2'h1; // @[Misc.scala:202:81] wire [1:0] a_size = 2'h2; // @[memory.scala:60:30] wire [1:0] _a_mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] _a_mask_sizeOH_T_3 = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_dport_req_bits_typ = 3'h7; // @[master_adapter.scala:38:7] wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] get_bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_bundle_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_bundle_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _masterNodeOut_a_bits_T_1_param = 3'h0; // @[master_adapter.scala:92:23] wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] get_bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] _masterNodeOut_a_bits_T_1_opcode = 3'h4; // @[master_adapter.scala:92:23] wire [2:0] _a_signed_T_1 = 3'h6; // @[memory.scala:61:27] wire [2:0] _a_size_T_1 = 3'h6; // @[memory.scala:60:24] wire [3:0] _a_signed_T = 4'h6; // @[memory.scala:61:27] wire [3:0] _a_size_T = 4'h6; // @[memory.scala:60:24] wire nodeOut_a_ready = auto_out_a_ready_0; // @[master_adapter.scala:38:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[master_adapter.scala:38:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[master_adapter.scala:38:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[master_adapter.scala:38:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[master_adapter.scala:38:7] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[master_adapter.scala:38:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[master_adapter.scala:38:7] wire _io_dport_req_ready_T; // @[master_adapter.scala:77:31] wire masterNodeOut_d_valid; // @[MixedNode.scala:542:17] wire [31:0] _io_dport_resp_bits_data_T_15; // @[AMOALU.scala:45:16] wire [2:0] auto_out_a_bits_opcode_0; // @[master_adapter.scala:38:7] wire [2:0] auto_out_a_bits_param_0; // @[master_adapter.scala:38:7] wire [3:0] auto_out_a_bits_size_0; // @[master_adapter.scala:38:7] wire auto_out_a_bits_source_0; // @[master_adapter.scala:38:7] wire [31:0] auto_out_a_bits_address_0; // @[master_adapter.scala:38:7] wire [3:0] auto_out_a_bits_mask_0; // @[master_adapter.scala:38:7] wire [31:0] auto_out_a_bits_data_0; // @[master_adapter.scala:38:7] wire auto_out_a_bits_corrupt_0; // @[master_adapter.scala:38:7] wire auto_out_a_valid_0; // @[master_adapter.scala:38:7] wire auto_out_d_ready_0; // @[master_adapter.scala:38:7] wire io_dport_req_ready_0; // @[master_adapter.scala:38:7] wire [31:0] io_dport_resp_bits_data_0; // @[master_adapter.scala:38:7] wire io_dport_resp_valid_0; // @[master_adapter.scala:38:7] wire nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[master_adapter.scala:38:7] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[master_adapter.scala:38:7] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[master_adapter.scala:38:7] wire [3:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[master_adapter.scala:38:7] wire nodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[master_adapter.scala:38:7] wire [31:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[master_adapter.scala:38:7] wire [3:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[master_adapter.scala:38:7] wire [31:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[master_adapter.scala:38:7] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[master_adapter.scala:38:7] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[master_adapter.scala:38:7] wire nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [31:0] nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire _masterNodeOut_a_valid_T; // @[master_adapter.scala:75:27] wire [31:0] _masterNodeOut_a_bits_T_1_address; // @[master_adapter.scala:92:23] assign io_dport_resp_valid_0 = masterNodeOut_d_valid; // @[master_adapter.scala:38:7] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire masterNodeOut_a_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] reg [1:0] state; // @[master_adapter.scala:50:22] reg [31:0] a_address_reg; // @[master_adapter.scala:52:26] reg [31:0] req_address_reg; // @[master_adapter.scala:55:28] wire [31:0] _legal_T_14 = req_address_reg; // @[Parameters.scala:137:31] wire [31:0] get_bundle_address = req_address_reg; // @[Edges.scala:460:17] wire [31:0] _legal_T_65 = req_address_reg; // @[Parameters.scala:137:31] wire [31:0] put_bundle_address = req_address_reg; // @[Edges.scala:480:17] assign _io_dport_req_ready_T = state == 2'h0; // @[master_adapter.scala:50:22, :63:15, :77:31] assign _masterNodeOut_a_valid_T = state == 2'h1; // @[master_adapter.scala:50:22, :69:15, :75:27] assign masterNodeOut_a_valid = _masterNodeOut_a_valid_T; // @[master_adapter.scala:75:27] assign io_dport_req_ready_0 = _io_dport_req_ready_T; // @[master_adapter.scala:38:7, :77:31] wire [31:0] _GEN = {req_address_reg[31:14], req_address_reg[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [31:0] _legal_T_55; // @[Parameters.scala:137:31] assign _legal_T_55 = _GEN; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h8A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_50 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h8A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_0 = {req_address_reg[31:17], req_address_reg[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [31:0] _legal_T_96; // @[Parameters.scala:137:31] assign _legal_T_96 = _GEN_0; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {req_address_reg[31:21], req_address_reg[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _legal_T_70; // @[Parameters.scala:137:31] assign _legal_T_70 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h8A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {req_address_reg[31:26], req_address_reg[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_75; // @[Parameters.scala:137:31] assign _legal_T_75 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {req_address_reg[31:28], req_address_reg[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_80; // @[Parameters.scala:137:31] assign _legal_T_80 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h88000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = req_address_reg ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_85; // @[Parameters.scala:137:31] assign _legal_T_85 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h8A100000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_44 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_45 = _legal_T_44 | _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_46 = _legal_T_45 | _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_47 = _legal_T_46 | _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_48 = _legal_T_47 | _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_49 = _legal_T_48; // @[Parameters.scala:684:54, :685:42] wire legal_get = _legal_T_50 | _legal_T_49; // @[Parameters.scala:684:54, :686:26] wire legal_op = legal_get; // @[Parameters.scala:686:26] assign _masterNodeOut_a_bits_T_1_address = get_bundle_address; // @[Edges.scala:460:17] wire a_mask_sub_bit = req_address_reg[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = req_address_reg[1]; // @[Misc.scala:210:26] wire a_mask_sub_1_2 = a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_bit = req_address_reg[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = req_address_reg[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire [32:0] _legal_T_56 = {1'h0, _legal_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_57 = _legal_T_56 & 33'h8A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_58 = _legal_T_57; // @[Parameters.scala:137:46] wire _legal_T_59 = _legal_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_60 = _legal_T_59; // @[Parameters.scala:684:54] wire _legal_T_102 = _legal_T_60; // @[Parameters.scala:684:54, :686:26] wire [32:0] _legal_T_66 = {1'h0, _legal_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_67 = _legal_T_66 & 33'h8A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_68 = _legal_T_67; // @[Parameters.scala:137:46] wire _legal_T_69 = _legal_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_71 = {1'h0, _legal_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_72 = _legal_T_71 & 33'h8A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_73 = _legal_T_72; // @[Parameters.scala:137:46] wire _legal_T_74 = _legal_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_76 = {1'h0, _legal_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_77 = _legal_T_76 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_78 = _legal_T_77; // @[Parameters.scala:137:46] wire _legal_T_79 = _legal_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_81 = {1'h0, _legal_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_82 = _legal_T_81 & 33'h88000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_83 = _legal_T_82; // @[Parameters.scala:137:46] wire _legal_T_84 = _legal_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_86 = {1'h0, _legal_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_87 = _legal_T_86 & 33'h8A100000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_88 = _legal_T_87; // @[Parameters.scala:137:46] wire _legal_T_89 = _legal_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_90 = _legal_T_69 | _legal_T_74; // @[Parameters.scala:685:42] wire _legal_T_91 = _legal_T_90 | _legal_T_79; // @[Parameters.scala:685:42] wire _legal_T_92 = _legal_T_91 | _legal_T_84; // @[Parameters.scala:685:42] wire _legal_T_93 = _legal_T_92 | _legal_T_89; // @[Parameters.scala:685:42] wire _legal_T_94 = _legal_T_93; // @[Parameters.scala:684:54, :685:42] wire [32:0] _legal_T_97 = {1'h0, _legal_T_96}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_98 = _legal_T_97 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_99 = _legal_T_98; // @[Parameters.scala:137:46] wire _legal_T_100 = _legal_T_99 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_103 = _legal_T_102 | _legal_T_94; // @[Parameters.scala:684:54, :686:26] wire legal_put = _legal_T_103; // @[Parameters.scala:686:26] wire a_mask_sub_1_2_1 = a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_4 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign masterNodeOut_a_bits_address = _masterNodeOut_a_bits_T_1_address; // @[master_adapter.scala:92:23] wire [1:0] io_dport_resp_bits_data_size; // @[AMOALU.scala:11:18] assign io_dport_resp_bits_data_size = masterNodeOut_d_bits_size[1:0]; // @[AMOALU.scala:11:18, :12:8] wire _io_dport_resp_bits_data_shifted_T = a_address_reg[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_dport_resp_bits_data_shifted_T_1 = masterNodeOut_d_bits_data[31:16]; // @[AMOALU.scala:42:37] wire [15:0] _io_dport_resp_bits_data_T_5 = masterNodeOut_d_bits_data[31:16]; // @[AMOALU.scala:42:37, :45:94] wire [15:0] _io_dport_resp_bits_data_shifted_T_2 = masterNodeOut_d_bits_data[15:0]; // @[AMOALU.scala:42:55] wire [15:0] io_dport_resp_bits_data_shifted = _io_dport_resp_bits_data_shifted_T ? _io_dport_resp_bits_data_shifted_T_1 : _io_dport_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_dport_resp_bits_data_zeroed = io_dport_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_dport_resp_bits_data_T = io_dport_resp_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_dport_resp_bits_data_T_1 = _io_dport_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_dport_resp_bits_data_T_2 = io_dport_resp_bits_data_zeroed[15]; // @[AMOALU.scala:44:23, :45:81] wire [15:0] _io_dport_resp_bits_data_T_6 = _io_dport_resp_bits_data_T_1 ? 16'h0 : _io_dport_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,94}] wire [31:0] _io_dport_resp_bits_data_T_7 = {_io_dport_resp_bits_data_T_6, io_dport_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_dport_resp_bits_data_shifted_T_3 = a_address_reg[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_dport_resp_bits_data_shifted_T_4 = _io_dport_resp_bits_data_T_7[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_dport_resp_bits_data_shifted_T_5 = _io_dport_resp_bits_data_T_7[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_dport_resp_bits_data_shifted_1 = _io_dport_resp_bits_data_shifted_T_3 ? _io_dport_resp_bits_data_shifted_T_4 : _io_dport_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_dport_resp_bits_data_zeroed_1 = io_dport_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_dport_resp_bits_data_T_8 = io_dport_resp_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_dport_resp_bits_data_T_9 = _io_dport_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_dport_resp_bits_data_T_10 = io_dport_resp_bits_data_zeroed_1[7]; // @[AMOALU.scala:44:23, :45:81] wire [23:0] _io_dport_resp_bits_data_T_13 = _io_dport_resp_bits_data_T_7[31:8]; // @[AMOALU.scala:45:{16,94}] wire [23:0] _io_dport_resp_bits_data_T_14 = _io_dport_resp_bits_data_T_9 ? 24'h0 : _io_dport_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,94}] assign _io_dport_resp_bits_data_T_15 = {_io_dport_resp_bits_data_T_14, io_dport_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_dport_resp_bits_data_0 = _io_dport_resp_bits_data_T_15; // @[AMOALU.scala:45:16] wire resp_xp = masterNodeOut_d_bits_corrupt | masterNodeOut_d_bits_denied; // @[master_adapter.scala:99:39]

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_77 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_77 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_77( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_77 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i32_e8_s24_14 : output io : { flip signedIn : UInt<1>, flip in : UInt<32>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 31, 31) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<32>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 31, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<5>(0h1e), UInt<5>(0h1f)) node _intAsRawFloat_adjustedNormDist_T_33 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_32) node _intAsRawFloat_adjustedNormDist_T_34 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_33) node _intAsRawFloat_adjustedNormDist_T_35 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_34) node _intAsRawFloat_adjustedNormDist_T_36 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_35) node _intAsRawFloat_adjustedNormDist_T_37 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_36) node _intAsRawFloat_adjustedNormDist_T_38 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_37) node _intAsRawFloat_adjustedNormDist_T_39 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_38) node _intAsRawFloat_adjustedNormDist_T_40 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_39) node _intAsRawFloat_adjustedNormDist_T_41 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_40) node _intAsRawFloat_adjustedNormDist_T_42 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_41) node _intAsRawFloat_adjustedNormDist_T_43 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_42) node _intAsRawFloat_adjustedNormDist_T_44 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_43) node _intAsRawFloat_adjustedNormDist_T_45 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_44) node _intAsRawFloat_adjustedNormDist_T_46 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_45) node _intAsRawFloat_adjustedNormDist_T_47 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_46) node _intAsRawFloat_adjustedNormDist_T_48 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_47) node _intAsRawFloat_adjustedNormDist_T_49 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_48) node _intAsRawFloat_adjustedNormDist_T_50 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_49) node _intAsRawFloat_adjustedNormDist_T_51 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_50) node _intAsRawFloat_adjustedNormDist_T_52 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_51) node _intAsRawFloat_adjustedNormDist_T_53 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_52) node _intAsRawFloat_adjustedNormDist_T_54 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_53) node _intAsRawFloat_adjustedNormDist_T_55 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_54) node _intAsRawFloat_adjustedNormDist_T_56 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_55) node _intAsRawFloat_adjustedNormDist_T_57 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_56) node _intAsRawFloat_adjustedNormDist_T_58 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_57) node _intAsRawFloat_adjustedNormDist_T_59 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_58) node _intAsRawFloat_adjustedNormDist_T_60 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_59) node _intAsRawFloat_adjustedNormDist_T_61 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_60) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_61) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 31, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 31, 31) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 4, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_14 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i32_e8_s24_14( // @[INToRecFN.scala:43:7] input [31:0] io_in, // @[INToRecFN.scala:46:16] output [32:0] io_out // @[INToRecFN.scala:46:16] ); wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [32:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31] wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70] wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_14 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_43 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<3>(0h7)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<3>(0h6)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 5) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<3>(0h5)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h13)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 5) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<3>(0h4)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h13)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_24 = shr(io.in.a.bits.source, 5) node _source_ok_T_25 = eq(_source_ok_T_24, UInt<2>(0h3)) node _source_ok_T_26 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_27 = and(_source_ok_T_25, _source_ok_T_26) node _source_ok_T_28 = leq(source_ok_uncommonBits_4, UInt<5>(0h13)) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_30 = shr(io.in.a.bits.source, 5) node _source_ok_T_31 = eq(_source_ok_T_30, UInt<2>(0h2)) node _source_ok_T_32 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_T_34 = leq(source_ok_uncommonBits_5, UInt<5>(0h13)) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_36 = shr(io.in.a.bits.source, 5) node _source_ok_T_37 = eq(_source_ok_T_36, UInt<1>(0h1)) node _source_ok_T_38 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_T_40 = leq(source_ok_uncommonBits_6, UInt<5>(0h13)) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_42 = shr(io.in.a.bits.source, 5) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_7, UInt<5>(0h13)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 connect _source_ok_WIRE[4], _source_ok_T_29 connect _source_ok_WIRE[5], _source_ok_T_35 connect _source_ok_WIRE[6], _source_ok_T_41 connect _source_ok_WIRE[7], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_53, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<3>(0h7)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h13)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<10>(0h1c0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_17 = shr(io.in.a.bits.source, 5) node _T_18 = eq(_T_17, UInt<3>(0h6)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<5>(0h13)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<10>(0h1c0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_30 = shr(io.in.a.bits.source, 5) node _T_31 = eq(_T_30, UInt<3>(0h5)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<5>(0h13)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<10>(0h1c0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_43 = shr(io.in.a.bits.source, 5) node _T_44 = eq(_T_43, UInt<3>(0h4)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<5>(0h13)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<8>(0hc0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<10>(0h1c0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_56 = shr(io.in.a.bits.source, 5) node _T_57 = eq(_T_56, UInt<2>(0h3)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_4) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_4, UInt<5>(0h13)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<10>(0h1c0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_69 = shr(io.in.a.bits.source, 5) node _T_70 = eq(_T_69, UInt<2>(0h2)) node _T_71 = leq(UInt<1>(0h0), uncommonBits_5) node _T_72 = and(_T_70, _T_71) node _T_73 = leq(uncommonBits_5, UInt<5>(0h13)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<9>(0h140)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<10>(0h1c0))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = or(_T_75, _T_80) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_82 = shr(io.in.a.bits.source, 5) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_6) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_6, UInt<5>(0h13)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(_T_87, UInt<1>(0h0)) node _T_89 = xor(io.in.a.bits.address, UInt<9>(0h180)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<10>(0h1c0))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_95 = shr(io.in.a.bits.source, 5) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = leq(UInt<1>(0h0), uncommonBits_7) node _T_98 = and(_T_96, _T_97) node _T_99 = leq(uncommonBits_7, UInt<5>(0h13)) node _T_100 = and(_T_98, _T_99) node _T_101 = eq(_T_100, UInt<1>(0h0)) node _T_102 = xor(io.in.a.bits.address, UInt<9>(0h1c0)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<10>(0h1c0))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = or(_T_101, _T_106) node _T_108 = and(_T_16, _T_29) node _T_109 = and(_T_108, _T_42) node _T_110 = and(_T_109, _T_55) node _T_111 = and(_T_110, _T_68) node _T_112 = and(_T_111, _T_81) node _T_113 = and(_T_112, _T_94) node _T_114 = and(_T_113, _T_107) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_114, UInt<1>(0h1), "") : assert_1 node _T_118 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_118 : node _T_119 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_120 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_121 = and(_T_119, _T_120) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_122 = shr(io.in.a.bits.source, 5) node _T_123 = eq(_T_122, UInt<3>(0h7)) node _T_124 = leq(UInt<1>(0h0), uncommonBits_8) node _T_125 = and(_T_123, _T_124) node _T_126 = leq(uncommonBits_8, UInt<5>(0h13)) node _T_127 = and(_T_125, _T_126) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_128 = shr(io.in.a.bits.source, 5) node _T_129 = eq(_T_128, UInt<3>(0h6)) node _T_130 = leq(UInt<1>(0h0), uncommonBits_9) node _T_131 = and(_T_129, _T_130) node _T_132 = leq(uncommonBits_9, UInt<5>(0h13)) node _T_133 = and(_T_131, _T_132) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_134 = shr(io.in.a.bits.source, 5) node _T_135 = eq(_T_134, UInt<3>(0h5)) node _T_136 = leq(UInt<1>(0h0), uncommonBits_10) node _T_137 = and(_T_135, _T_136) node _T_138 = leq(uncommonBits_10, UInt<5>(0h13)) node _T_139 = and(_T_137, _T_138) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_11) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_11, UInt<5>(0h13)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0) node _T_146 = shr(io.in.a.bits.source, 5) node _T_147 = eq(_T_146, UInt<2>(0h3)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_12) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_12, UInt<5>(0h13)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<2>(0h2)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_13) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_13, UInt<5>(0h13)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_158 = shr(io.in.a.bits.source, 5) node _T_159 = eq(_T_158, UInt<1>(0h1)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_14) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_14, UInt<5>(0h13)) node _T_163 = and(_T_161, _T_162) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_164 = shr(io.in.a.bits.source, 5) node _T_165 = eq(_T_164, UInt<1>(0h0)) node _T_166 = leq(UInt<1>(0h0), uncommonBits_15) node _T_167 = and(_T_165, _T_166) node _T_168 = leq(uncommonBits_15, UInt<5>(0h13)) node _T_169 = and(_T_167, _T_168) node _T_170 = or(_T_127, _T_133) node _T_171 = or(_T_170, _T_139) node _T_172 = or(_T_171, _T_145) node _T_173 = or(_T_172, _T_151) node _T_174 = or(_T_173, _T_157) node _T_175 = or(_T_174, _T_163) node _T_176 = or(_T_175, _T_169) node _T_177 = and(_T_121, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<17>(0h10000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = and(_T_179, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_T_178, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_187, UInt<1>(0h1), "") : assert_2 node _T_191 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_192 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_193 = and(_T_191, _T_192) node _T_194 = or(UInt<1>(0h0), _T_193) node _T_195 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<17>(0h10000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = and(_T_194, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(UInt<1>(0h0), _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_233 = shr(io.in.a.bits.source, 5) node _T_234 = eq(_T_233, UInt<3>(0h7)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_16) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_16, UInt<5>(0h13)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_239 = shr(io.in.a.bits.source, 5) node _T_240 = eq(_T_239, UInt<3>(0h6)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_17) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_17, UInt<5>(0h13)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_245 = shr(io.in.a.bits.source, 5) node _T_246 = eq(_T_245, UInt<3>(0h5)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_18) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_18, UInt<5>(0h13)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<3>(0h4)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_19) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_19, UInt<5>(0h13)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<2>(0h3)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_20) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_20, UInt<5>(0h13)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_21) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_21, UInt<5>(0h13)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<1>(0h1)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_22) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_22, UInt<5>(0h13)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_23) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_23, UInt<5>(0h13)) node _T_280 = and(_T_278, _T_279) node _T_281 = or(_T_238, _T_244) node _T_282 = or(_T_281, _T_250) node _T_283 = or(_T_282, _T_256) node _T_284 = or(_T_283, _T_262) node _T_285 = or(_T_284, _T_268) node _T_286 = or(_T_285, _T_274) node _T_287 = or(_T_286, _T_280) node _T_288 = and(_T_232, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = and(_T_305, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = and(UInt<1>(0h0), _T_312) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_313, UInt<1>(0h1), "") : assert_11 node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(source_ok, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_320 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_T_320, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_320, UInt<1>(0h1), "") : assert_13 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_327 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_327, UInt<1>(0h1), "") : assert_15 node _T_331 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_331, UInt<1>(0h1), "") : assert_16 node _T_335 = not(io.in.a.bits.mask) node _T_336 = eq(_T_335, UInt<1>(0h0)) node _T_337 = asUInt(reset) node _T_338 = eq(_T_337, UInt<1>(0h0)) when _T_338 : node _T_339 = eq(_T_336, UInt<1>(0h0)) when _T_339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_336, UInt<1>(0h1), "") : assert_17 node _T_340 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_T_340, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_340, UInt<1>(0h1), "") : assert_18 node _T_344 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_344 : node _T_345 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_346 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_347 = and(_T_345, _T_346) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0) node _T_348 = shr(io.in.a.bits.source, 5) node _T_349 = eq(_T_348, UInt<3>(0h7)) node _T_350 = leq(UInt<1>(0h0), uncommonBits_24) node _T_351 = and(_T_349, _T_350) node _T_352 = leq(uncommonBits_24, UInt<5>(0h13)) node _T_353 = and(_T_351, _T_352) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0) node _T_354 = shr(io.in.a.bits.source, 5) node _T_355 = eq(_T_354, UInt<3>(0h6)) node _T_356 = leq(UInt<1>(0h0), uncommonBits_25) node _T_357 = and(_T_355, _T_356) node _T_358 = leq(uncommonBits_25, UInt<5>(0h13)) node _T_359 = and(_T_357, _T_358) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0) node _T_360 = shr(io.in.a.bits.source, 5) node _T_361 = eq(_T_360, UInt<3>(0h5)) node _T_362 = leq(UInt<1>(0h0), uncommonBits_26) node _T_363 = and(_T_361, _T_362) node _T_364 = leq(uncommonBits_26, UInt<5>(0h13)) node _T_365 = and(_T_363, _T_364) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0) node _T_366 = shr(io.in.a.bits.source, 5) node _T_367 = eq(_T_366, UInt<3>(0h4)) node _T_368 = leq(UInt<1>(0h0), uncommonBits_27) node _T_369 = and(_T_367, _T_368) node _T_370 = leq(uncommonBits_27, UInt<5>(0h13)) node _T_371 = and(_T_369, _T_370) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_372 = shr(io.in.a.bits.source, 5) node _T_373 = eq(_T_372, UInt<2>(0h3)) node _T_374 = leq(UInt<1>(0h0), uncommonBits_28) node _T_375 = and(_T_373, _T_374) node _T_376 = leq(uncommonBits_28, UInt<5>(0h13)) node _T_377 = and(_T_375, _T_376) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_378 = shr(io.in.a.bits.source, 5) node _T_379 = eq(_T_378, UInt<2>(0h2)) node _T_380 = leq(UInt<1>(0h0), uncommonBits_29) node _T_381 = and(_T_379, _T_380) node _T_382 = leq(uncommonBits_29, UInt<5>(0h13)) node _T_383 = and(_T_381, _T_382) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_384 = shr(io.in.a.bits.source, 5) node _T_385 = eq(_T_384, UInt<1>(0h1)) node _T_386 = leq(UInt<1>(0h0), uncommonBits_30) node _T_387 = and(_T_385, _T_386) node _T_388 = leq(uncommonBits_30, UInt<5>(0h13)) node _T_389 = and(_T_387, _T_388) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_390 = shr(io.in.a.bits.source, 5) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = leq(UInt<1>(0h0), uncommonBits_31) node _T_393 = and(_T_391, _T_392) node _T_394 = leq(uncommonBits_31, UInt<5>(0h13)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(_T_353, _T_359) node _T_397 = or(_T_396, _T_365) node _T_398 = or(_T_397, _T_371) node _T_399 = or(_T_398, _T_377) node _T_400 = or(_T_399, _T_383) node _T_401 = or(_T_400, _T_389) node _T_402 = or(_T_401, _T_395) node _T_403 = and(_T_347, _T_402) node _T_404 = or(UInt<1>(0h0), _T_403) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_404, UInt<1>(0h1), "") : assert_19 node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_409 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_410 = and(_T_408, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<17>(0h10000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = and(_T_411, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_418, UInt<1>(0h1), "") : assert_20 node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(source_ok, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(is_aligned, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_428 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_428, UInt<1>(0h1), "") : assert_23 node _T_432 = eq(io.in.a.bits.mask, mask) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_432, UInt<1>(0h1), "") : assert_24 node _T_436 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_436, UInt<1>(0h1), "") : assert_25 node _T_440 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_440 : node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_444 = shr(io.in.a.bits.source, 5) node _T_445 = eq(_T_444, UInt<3>(0h7)) node _T_446 = leq(UInt<1>(0h0), uncommonBits_32) node _T_447 = and(_T_445, _T_446) node _T_448 = leq(uncommonBits_32, UInt<5>(0h13)) node _T_449 = and(_T_447, _T_448) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_450 = shr(io.in.a.bits.source, 5) node _T_451 = eq(_T_450, UInt<3>(0h6)) node _T_452 = leq(UInt<1>(0h0), uncommonBits_33) node _T_453 = and(_T_451, _T_452) node _T_454 = leq(uncommonBits_33, UInt<5>(0h13)) node _T_455 = and(_T_453, _T_454) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_456 = shr(io.in.a.bits.source, 5) node _T_457 = eq(_T_456, UInt<3>(0h5)) node _T_458 = leq(UInt<1>(0h0), uncommonBits_34) node _T_459 = and(_T_457, _T_458) node _T_460 = leq(uncommonBits_34, UInt<5>(0h13)) node _T_461 = and(_T_459, _T_460) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_462 = shr(io.in.a.bits.source, 5) node _T_463 = eq(_T_462, UInt<3>(0h4)) node _T_464 = leq(UInt<1>(0h0), uncommonBits_35) node _T_465 = and(_T_463, _T_464) node _T_466 = leq(uncommonBits_35, UInt<5>(0h13)) node _T_467 = and(_T_465, _T_466) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_468 = shr(io.in.a.bits.source, 5) node _T_469 = eq(_T_468, UInt<2>(0h3)) node _T_470 = leq(UInt<1>(0h0), uncommonBits_36) node _T_471 = and(_T_469, _T_470) node _T_472 = leq(uncommonBits_36, UInt<5>(0h13)) node _T_473 = and(_T_471, _T_472) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_474 = shr(io.in.a.bits.source, 5) node _T_475 = eq(_T_474, UInt<2>(0h2)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_37) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_37, UInt<5>(0h13)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_38) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_38, UInt<5>(0h13)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_486 = shr(io.in.a.bits.source, 5) node _T_487 = eq(_T_486, UInt<1>(0h0)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_39) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_39, UInt<5>(0h13)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(_T_449, _T_455) node _T_493 = or(_T_492, _T_461) node _T_494 = or(_T_493, _T_467) node _T_495 = or(_T_494, _T_473) node _T_496 = or(_T_495, _T_479) node _T_497 = or(_T_496, _T_485) node _T_498 = or(_T_497, _T_491) node _T_499 = and(_T_443, _T_498) node _T_500 = or(UInt<1>(0h0), _T_499) node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_502 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_503 = and(_T_501, _T_502) node _T_504 = or(UInt<1>(0h0), _T_503) node _T_505 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<17>(0h10000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = and(_T_504, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = and(_T_500, _T_511) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_512, UInt<1>(0h1), "") : assert_26 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_522, UInt<1>(0h1), "") : assert_29 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_526, UInt<1>(0h1), "") : assert_30 node _T_530 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_530 : node _T_531 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_532 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_533 = and(_T_531, _T_532) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_534 = shr(io.in.a.bits.source, 5) node _T_535 = eq(_T_534, UInt<3>(0h7)) node _T_536 = leq(UInt<1>(0h0), uncommonBits_40) node _T_537 = and(_T_535, _T_536) node _T_538 = leq(uncommonBits_40, UInt<5>(0h13)) node _T_539 = and(_T_537, _T_538) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_540 = shr(io.in.a.bits.source, 5) node _T_541 = eq(_T_540, UInt<3>(0h6)) node _T_542 = leq(UInt<1>(0h0), uncommonBits_41) node _T_543 = and(_T_541, _T_542) node _T_544 = leq(uncommonBits_41, UInt<5>(0h13)) node _T_545 = and(_T_543, _T_544) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_546 = shr(io.in.a.bits.source, 5) node _T_547 = eq(_T_546, UInt<3>(0h5)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_42) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_42, UInt<5>(0h13)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_552 = shr(io.in.a.bits.source, 5) node _T_553 = eq(_T_552, UInt<3>(0h4)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_43) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_43, UInt<5>(0h13)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_558 = shr(io.in.a.bits.source, 5) node _T_559 = eq(_T_558, UInt<2>(0h3)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_44) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_44, UInt<5>(0h13)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_564 = shr(io.in.a.bits.source, 5) node _T_565 = eq(_T_564, UInt<2>(0h2)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_45) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_45, UInt<5>(0h13)) node _T_569 = and(_T_567, _T_568) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_570 = shr(io.in.a.bits.source, 5) node _T_571 = eq(_T_570, UInt<1>(0h1)) node _T_572 = leq(UInt<1>(0h0), uncommonBits_46) node _T_573 = and(_T_571, _T_572) node _T_574 = leq(uncommonBits_46, UInt<5>(0h13)) node _T_575 = and(_T_573, _T_574) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_576 = shr(io.in.a.bits.source, 5) node _T_577 = eq(_T_576, UInt<1>(0h0)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_47) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_47, UInt<5>(0h13)) node _T_581 = and(_T_579, _T_580) node _T_582 = or(_T_539, _T_545) node _T_583 = or(_T_582, _T_551) node _T_584 = or(_T_583, _T_557) node _T_585 = or(_T_584, _T_563) node _T_586 = or(_T_585, _T_569) node _T_587 = or(_T_586, _T_575) node _T_588 = or(_T_587, _T_581) node _T_589 = and(_T_533, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_593 = and(_T_591, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_596 = cvt(_T_595) node _T_597 = and(_T_596, asSInt(UInt<17>(0h10000))) node _T_598 = asSInt(_T_597) node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0))) node _T_600 = and(_T_594, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = and(_T_590, _T_601) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_602, UInt<1>(0h1), "") : assert_31 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(source_ok, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(is_aligned, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_612 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_612, UInt<1>(0h1), "") : assert_34 node _T_616 = not(mask) node _T_617 = and(io.in.a.bits.mask, _T_616) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_618, UInt<1>(0h1), "") : assert_35 node _T_622 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_622 : node _T_623 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_624 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 4, 0) node _T_626 = shr(io.in.a.bits.source, 5) node _T_627 = eq(_T_626, UInt<3>(0h7)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_48) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_48, UInt<5>(0h13)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 4, 0) node _T_632 = shr(io.in.a.bits.source, 5) node _T_633 = eq(_T_632, UInt<3>(0h6)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_49) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_49, UInt<5>(0h13)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_638 = shr(io.in.a.bits.source, 5) node _T_639 = eq(_T_638, UInt<3>(0h5)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_50) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_50, UInt<5>(0h13)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_644 = shr(io.in.a.bits.source, 5) node _T_645 = eq(_T_644, UInt<3>(0h4)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_51) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_51, UInt<5>(0h13)) node _T_649 = and(_T_647, _T_648) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_650 = shr(io.in.a.bits.source, 5) node _T_651 = eq(_T_650, UInt<2>(0h3)) node _T_652 = leq(UInt<1>(0h0), uncommonBits_52) node _T_653 = and(_T_651, _T_652) node _T_654 = leq(uncommonBits_52, UInt<5>(0h13)) node _T_655 = and(_T_653, _T_654) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_656 = shr(io.in.a.bits.source, 5) node _T_657 = eq(_T_656, UInt<2>(0h2)) node _T_658 = leq(UInt<1>(0h0), uncommonBits_53) node _T_659 = and(_T_657, _T_658) node _T_660 = leq(uncommonBits_53, UInt<5>(0h13)) node _T_661 = and(_T_659, _T_660) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_662 = shr(io.in.a.bits.source, 5) node _T_663 = eq(_T_662, UInt<1>(0h1)) node _T_664 = leq(UInt<1>(0h0), uncommonBits_54) node _T_665 = and(_T_663, _T_664) node _T_666 = leq(uncommonBits_54, UInt<5>(0h13)) node _T_667 = and(_T_665, _T_666) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_668 = shr(io.in.a.bits.source, 5) node _T_669 = eq(_T_668, UInt<1>(0h0)) node _T_670 = leq(UInt<1>(0h0), uncommonBits_55) node _T_671 = and(_T_669, _T_670) node _T_672 = leq(uncommonBits_55, UInt<5>(0h13)) node _T_673 = and(_T_671, _T_672) node _T_674 = or(_T_631, _T_637) node _T_675 = or(_T_674, _T_643) node _T_676 = or(_T_675, _T_649) node _T_677 = or(_T_676, _T_655) node _T_678 = or(_T_677, _T_661) node _T_679 = or(_T_678, _T_667) node _T_680 = or(_T_679, _T_673) node _T_681 = and(_T_625, _T_680) node _T_682 = or(UInt<1>(0h0), _T_681) node _T_683 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_685 = cvt(_T_684) node _T_686 = and(_T_685, asSInt(UInt<17>(0h10000))) node _T_687 = asSInt(_T_686) node _T_688 = eq(_T_687, asSInt(UInt<1>(0h0))) node _T_689 = and(_T_683, _T_688) node _T_690 = or(UInt<1>(0h0), _T_689) node _T_691 = and(_T_682, _T_690) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_691, UInt<1>(0h1), "") : assert_36 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(source_ok, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(is_aligned, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_701 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_701, UInt<1>(0h1), "") : assert_39 node _T_705 = eq(io.in.a.bits.mask, mask) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_705, UInt<1>(0h1), "") : assert_40 node _T_709 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_709 : node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_711 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_712 = and(_T_710, _T_711) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_713 = shr(io.in.a.bits.source, 5) node _T_714 = eq(_T_713, UInt<3>(0h7)) node _T_715 = leq(UInt<1>(0h0), uncommonBits_56) node _T_716 = and(_T_714, _T_715) node _T_717 = leq(uncommonBits_56, UInt<5>(0h13)) node _T_718 = and(_T_716, _T_717) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_719 = shr(io.in.a.bits.source, 5) node _T_720 = eq(_T_719, UInt<3>(0h6)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_57) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_57, UInt<5>(0h13)) node _T_724 = and(_T_722, _T_723) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_725 = shr(io.in.a.bits.source, 5) node _T_726 = eq(_T_725, UInt<3>(0h5)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_58) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_58, UInt<5>(0h13)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_731 = shr(io.in.a.bits.source, 5) node _T_732 = eq(_T_731, UInt<3>(0h4)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_59) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_59, UInt<5>(0h13)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_737 = shr(io.in.a.bits.source, 5) node _T_738 = eq(_T_737, UInt<2>(0h3)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_60) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_60, UInt<5>(0h13)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_743 = shr(io.in.a.bits.source, 5) node _T_744 = eq(_T_743, UInt<2>(0h2)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_61) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_61, UInt<5>(0h13)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_749 = shr(io.in.a.bits.source, 5) node _T_750 = eq(_T_749, UInt<1>(0h1)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_62) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_62, UInt<5>(0h13)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_755 = shr(io.in.a.bits.source, 5) node _T_756 = eq(_T_755, UInt<1>(0h0)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_63) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_63, UInt<5>(0h13)) node _T_760 = and(_T_758, _T_759) node _T_761 = or(_T_718, _T_724) node _T_762 = or(_T_761, _T_730) node _T_763 = or(_T_762, _T_736) node _T_764 = or(_T_763, _T_742) node _T_765 = or(_T_764, _T_748) node _T_766 = or(_T_765, _T_754) node _T_767 = or(_T_766, _T_760) node _T_768 = and(_T_712, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = and(_T_770, _T_775) node _T_777 = or(UInt<1>(0h0), _T_776) node _T_778 = and(_T_769, _T_777) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_778, UInt<1>(0h1), "") : assert_41 node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(source_ok, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(is_aligned, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_788 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(_T_788, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_788, UInt<1>(0h1), "") : assert_44 node _T_792 = eq(io.in.a.bits.mask, mask) node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(_T_792, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_792, UInt<1>(0h1), "") : assert_45 node _T_796 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_796 : node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_799 = and(_T_797, _T_798) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_800 = shr(io.in.a.bits.source, 5) node _T_801 = eq(_T_800, UInt<3>(0h7)) node _T_802 = leq(UInt<1>(0h0), uncommonBits_64) node _T_803 = and(_T_801, _T_802) node _T_804 = leq(uncommonBits_64, UInt<5>(0h13)) node _T_805 = and(_T_803, _T_804) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_806 = shr(io.in.a.bits.source, 5) node _T_807 = eq(_T_806, UInt<3>(0h6)) node _T_808 = leq(UInt<1>(0h0), uncommonBits_65) node _T_809 = and(_T_807, _T_808) node _T_810 = leq(uncommonBits_65, UInt<5>(0h13)) node _T_811 = and(_T_809, _T_810) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_812 = shr(io.in.a.bits.source, 5) node _T_813 = eq(_T_812, UInt<3>(0h5)) node _T_814 = leq(UInt<1>(0h0), uncommonBits_66) node _T_815 = and(_T_813, _T_814) node _T_816 = leq(uncommonBits_66, UInt<5>(0h13)) node _T_817 = and(_T_815, _T_816) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_818 = shr(io.in.a.bits.source, 5) node _T_819 = eq(_T_818, UInt<3>(0h4)) node _T_820 = leq(UInt<1>(0h0), uncommonBits_67) node _T_821 = and(_T_819, _T_820) node _T_822 = leq(uncommonBits_67, UInt<5>(0h13)) node _T_823 = and(_T_821, _T_822) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_824 = shr(io.in.a.bits.source, 5) node _T_825 = eq(_T_824, UInt<2>(0h3)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_68) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_68, UInt<5>(0h13)) node _T_829 = and(_T_827, _T_828) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_830 = shr(io.in.a.bits.source, 5) node _T_831 = eq(_T_830, UInt<2>(0h2)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_69) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_69, UInt<5>(0h13)) node _T_835 = and(_T_833, _T_834) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_836 = shr(io.in.a.bits.source, 5) node _T_837 = eq(_T_836, UInt<1>(0h1)) node _T_838 = leq(UInt<1>(0h0), uncommonBits_70) node _T_839 = and(_T_837, _T_838) node _T_840 = leq(uncommonBits_70, UInt<5>(0h13)) node _T_841 = and(_T_839, _T_840) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_842 = shr(io.in.a.bits.source, 5) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_71) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_71, UInt<5>(0h13)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(_T_805, _T_811) node _T_849 = or(_T_848, _T_817) node _T_850 = or(_T_849, _T_823) node _T_851 = or(_T_850, _T_829) node _T_852 = or(_T_851, _T_835) node _T_853 = or(_T_852, _T_841) node _T_854 = or(_T_853, _T_847) node _T_855 = and(_T_799, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_858 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_859 = cvt(_T_858) node _T_860 = and(_T_859, asSInt(UInt<17>(0h10000))) node _T_861 = asSInt(_T_860) node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0))) node _T_863 = and(_T_857, _T_862) node _T_864 = or(UInt<1>(0h0), _T_863) node _T_865 = and(_T_856, _T_864) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_865, UInt<1>(0h1), "") : assert_46 node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(source_ok, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(is_aligned, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_875 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_875, UInt<1>(0h1), "") : assert_49 node _T_879 = eq(io.in.a.bits.mask, mask) node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(_T_879, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_879, UInt<1>(0h1), "") : assert_50 node _T_883 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_883, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_887 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_887, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 5) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<3>(0h7)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_8, UInt<5>(0h13)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 5) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<3>(0h6)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_9, UInt<5>(0h13)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 5) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h5)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_10, UInt<5>(0h13)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 5) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<3>(0h4)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_11, UInt<5>(0h13)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 4, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 5) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<2>(0h3)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_12, UInt<5>(0h13)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 4, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 5) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<2>(0h2)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_13, UInt<5>(0h13)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 5) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<1>(0h1)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_14, UInt<5>(0h13)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_96 = shr(io.in.d.bits.source, 5) node _source_ok_T_97 = eq(_source_ok_T_96, UInt<1>(0h0)) node _source_ok_T_98 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_99 = and(_source_ok_T_97, _source_ok_T_98) node _source_ok_T_100 = leq(source_ok_uncommonBits_15, UInt<5>(0h13)) node _source_ok_T_101 = and(_source_ok_T_99, _source_ok_T_100) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_59 connect _source_ok_WIRE_1[1], _source_ok_T_65 connect _source_ok_WIRE_1[2], _source_ok_T_71 connect _source_ok_WIRE_1[3], _source_ok_T_77 connect _source_ok_WIRE_1[4], _source_ok_T_83 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_95 connect _source_ok_WIRE_1[7], _source_ok_T_101 node _source_ok_T_102 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[2]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[3]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[4]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[5]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_891 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_891 : node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(source_ok_1, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_895 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_895, UInt<1>(0h1), "") : assert_54 node _T_899 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_899, UInt<1>(0h1), "") : assert_55 node _T_903 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_903, UInt<1>(0h1), "") : assert_56 node _T_907 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_907, UInt<1>(0h1), "") : assert_57 node _T_911 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_911 : node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(source_ok_1, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(sink_ok, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_918 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_918, UInt<1>(0h1), "") : assert_60 node _T_922 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_922, UInt<1>(0h1), "") : assert_61 node _T_926 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_926, UInt<1>(0h1), "") : assert_62 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_930, UInt<1>(0h1), "") : assert_63 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h0), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_935, UInt<1>(0h1), "") : assert_64 node _T_939 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_939 : node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(source_ok_1, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(sink_ok, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_946 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_946, UInt<1>(0h1), "") : assert_67 node _T_950 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_950, UInt<1>(0h1), "") : assert_68 node _T_954 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(_T_954, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_954, UInt<1>(0h1), "") : assert_69 node _T_958 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_959 = or(_T_958, io.in.d.bits.corrupt) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_959, UInt<1>(0h1), "") : assert_70 node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_964 = or(UInt<1>(0h0), _T_963) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_964, UInt<1>(0h1), "") : assert_71 node _T_968 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_968 : node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(source_ok_1, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_972 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_972, UInt<1>(0h1), "") : assert_73 node _T_976 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_976, UInt<1>(0h1), "") : assert_74 node _T_980 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_981 = or(UInt<1>(0h0), _T_980) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_981, UInt<1>(0h1), "") : assert_75 node _T_985 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_985 : node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(source_ok_1, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_989 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_989, UInt<1>(0h1), "") : assert_77 node _T_993 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_994 = or(_T_993, io.in.d.bits.corrupt) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_994, UInt<1>(0h1), "") : assert_78 node _T_998 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_999, UInt<1>(0h1), "") : assert_79 node _T_1003 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1003 : node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(source_ok_1, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1007 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_81 node _T_1011 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_82 node _T_1015 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1016 = or(UInt<1>(0h0), _T_1015) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1020 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1024 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1028 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1032 = eq(a_first, UInt<1>(0h0)) node _T_1033 = and(io.in.a.valid, _T_1032) when _T_1033 : node _T_1034 = eq(io.in.a.bits.opcode, opcode) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_87 node _T_1038 = eq(io.in.a.bits.param, param) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_88 node _T_1042 = eq(io.in.a.bits.size, size) node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(_T_1042, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1042, UInt<1>(0h1), "") : assert_89 node _T_1046 = eq(io.in.a.bits.source, source) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_90 node _T_1050 = eq(io.in.a.bits.address, address) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_91 node _T_1054 = and(io.in.a.ready, io.in.a.valid) node _T_1055 = and(_T_1054, a_first) when _T_1055 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1056 = eq(d_first, UInt<1>(0h0)) node _T_1057 = and(io.in.d.valid, _T_1056) when _T_1057 : node _T_1058 = eq(io.in.d.bits.opcode, opcode_1) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_92 node _T_1062 = eq(io.in.d.bits.param, param_1) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_93 node _T_1066 = eq(io.in.d.bits.size, size_1) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_94 node _T_1070 = eq(io.in.d.bits.source, source_1) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_95 node _T_1074 = eq(io.in.d.bits.sink, sink) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_96 node _T_1078 = eq(io.in.d.bits.denied, denied) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_97 node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = and(_T_1082, d_first) when _T_1083 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<244>, clock, reset, UInt<244>(0h0) regreset inflight_opcodes : UInt<976>, clock, reset, UInt<976>(0h0) regreset inflight_sizes : UInt<976>, clock, reset, UInt<976>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<244> connect a_set, UInt<244>(0h0) wire a_set_wo_ready : UInt<244> connect a_set_wo_ready, UInt<244>(0h0) wire a_opcodes_set : UInt<976> connect a_opcodes_set, UInt<976>(0h0) wire a_sizes_set : UInt<976> connect a_sizes_set, UInt<976>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1084 = and(io.in.a.valid, a_first_1) node _T_1085 = and(_T_1084, UInt<1>(0h1)) when _T_1085 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1086 = and(io.in.a.ready, io.in.a.valid) node _T_1087 = and(_T_1086, a_first_1) node _T_1088 = and(_T_1087, UInt<1>(0h1)) when _T_1088 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1089 = dshr(inflight, io.in.a.bits.source) node _T_1090 = bits(_T_1089, 0, 0) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<244> connect d_clr, UInt<244>(0h0) wire d_clr_wo_ready : UInt<244> connect d_clr_wo_ready, UInt<244>(0h0) wire d_opcodes_clr : UInt<976> connect d_opcodes_clr, UInt<976>(0h0) wire d_sizes_clr : UInt<976> connect d_sizes_clr, UInt<976>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1095 = and(io.in.d.valid, d_first_1) node _T_1096 = and(_T_1095, UInt<1>(0h1)) node _T_1097 = eq(d_release_ack, UInt<1>(0h0)) node _T_1098 = and(_T_1096, _T_1097) when _T_1098 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1099 = and(io.in.d.ready, io.in.d.valid) node _T_1100 = and(_T_1099, d_first_1) node _T_1101 = and(_T_1100, UInt<1>(0h1)) node _T_1102 = eq(d_release_ack, UInt<1>(0h0)) node _T_1103 = and(_T_1101, _T_1102) when _T_1103 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1104 = and(io.in.d.valid, d_first_1) node _T_1105 = and(_T_1104, UInt<1>(0h1)) node _T_1106 = eq(d_release_ack, UInt<1>(0h0)) node _T_1107 = and(_T_1105, _T_1106) when _T_1107 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1108 = dshr(inflight, io.in.d.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = or(_T_1109, same_cycle_resp) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1114 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1115 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1116 = or(_T_1114, _T_1115) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_100 node _T_1120 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_101 else : node _T_1124 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1125 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1126 = or(_T_1124, _T_1125) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_102 node _T_1130 = eq(io.in.d.bits.size, a_size_lookup) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_103 node _T_1134 = and(io.in.d.valid, d_first_1) node _T_1135 = and(_T_1134, a_first_1) node _T_1136 = and(_T_1135, io.in.a.valid) node _T_1137 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1138 = and(_T_1136, _T_1137) node _T_1139 = eq(d_release_ack, UInt<1>(0h0)) node _T_1140 = and(_T_1138, _T_1139) when _T_1140 : node _T_1141 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1142 = or(_T_1141, io.in.a.ready) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_104 node _T_1146 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1147 = orr(a_set_wo_ready) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) node _T_1149 = or(_T_1146, _T_1148) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_86 node _T_1153 = orr(inflight) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) node _T_1155 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = lt(watchdog, plusarg_reader.out) node _T_1158 = or(_T_1156, _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1162 = and(io.in.a.ready, io.in.a.valid) node _T_1163 = and(io.in.d.ready, io.in.d.valid) node _T_1164 = or(_T_1162, _T_1163) when _T_1164 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<244>, clock, reset, UInt<244>(0h0) regreset inflight_opcodes_1 : UInt<976>, clock, reset, UInt<976>(0h0) regreset inflight_sizes_1 : UInt<976>, clock, reset, UInt<976>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<244> connect c_set, UInt<244>(0h0) wire c_set_wo_ready : UInt<244> connect c_set_wo_ready, UInt<244>(0h0) wire c_opcodes_set : UInt<976> connect c_opcodes_set, UInt<976>(0h0) wire c_sizes_set : UInt<976> connect c_sizes_set, UInt<976>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1165 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1166 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1167 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = and(_T_1165, _T_1168) when _T_1169 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1170 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1171 = and(_T_1170, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1172 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1173 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = and(_T_1171, _T_1174) when _T_1175 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1176 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1177 = bits(_T_1176, 0, 0) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<244> connect d_clr_1, UInt<244>(0h0) wire d_clr_wo_ready_1 : UInt<244> connect d_clr_wo_ready_1, UInt<244>(0h0) wire d_opcodes_clr_1 : UInt<976> connect d_opcodes_clr_1, UInt<976>(0h0) wire d_sizes_clr_1 : UInt<976> connect d_sizes_clr_1, UInt<976>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1182 = and(io.in.d.valid, d_first_2) node _T_1183 = and(_T_1182, UInt<1>(0h1)) node _T_1184 = and(_T_1183, d_release_ack_1) when _T_1184 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1185 = and(io.in.d.ready, io.in.d.valid) node _T_1186 = and(_T_1185, d_first_2) node _T_1187 = and(_T_1186, UInt<1>(0h1)) node _T_1188 = and(_T_1187, d_release_ack_1) when _T_1188 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1189 = and(io.in.d.valid, d_first_2) node _T_1190 = and(_T_1189, UInt<1>(0h1)) node _T_1191 = and(_T_1190, d_release_ack_1) when _T_1191 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1192 = dshr(inflight_1, io.in.d.bits.source) node _T_1193 = bits(_T_1192, 0, 0) node _T_1194 = or(_T_1193, same_cycle_resp_1) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1198 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_109 else : node _T_1202 = eq(io.in.d.bits.size, c_size_lookup) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110 node _T_1206 = and(io.in.d.valid, d_first_2) node _T_1207 = and(_T_1206, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1208 = and(_T_1207, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1209 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = and(_T_1210, d_release_ack_1) node _T_1212 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1213 = and(_T_1211, _T_1212) when _T_1213 : node _T_1214 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1215 = or(_T_1214, _WIRE_23.ready) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_111 node _T_1219 = orr(c_set_wo_ready) when _T_1219 : node _T_1220 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_87 node _T_1224 = orr(inflight_1) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) node _T_1226 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1227 = or(_T_1225, _T_1226) node _T_1228 = lt(watchdog_1, plusarg_reader_1.out) node _T_1229 = or(_T_1227, _T_1228) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1233 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1234 = and(io.in.d.ready, io.in.d.valid) node _T_1235 = or(_T_1233, _T_1234) when _T_1235 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_43( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_26 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_38 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_98 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [975:0] c_opcodes_set = 976'h0; // @[Monitor.scala:740:34] wire [975:0] c_sizes_set = 976'h0; // @[Monitor.scala:741:34] wire [243:0] c_set = 244'h0; // @[Monitor.scala:738:34] wire [243:0] c_set_wo_ready = 244'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_14 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_15 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_6 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_12 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_18 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_24 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_30 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_36 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_42 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = &_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 3'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_9 & _source_ok_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 3'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_15 & _source_ok_T_16; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = _source_ok_T_18 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_3 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_25 = _source_ok_T_24 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_27 = _source_ok_T_25; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_28 = source_ok_uncommonBits_4 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_29 = _source_ok_T_27 & _source_ok_T_28; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_4 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_31 = _source_ok_T_30 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = source_ok_uncommonBits_5 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_35 = _source_ok_T_33 & _source_ok_T_34; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_37 = _source_ok_T_36 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_39 = _source_ok_T_37; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = source_ok_uncommonBits_6 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_41 = _source_ok_T_39 & _source_ok_T_40; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_6 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_43 = _source_ok_T_42 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = source_ok_uncommonBits_7 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_47 = _source_ok_T_45 & _source_ok_T_46; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_12 = _uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_13 = _uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_24 = _uncommonBits_T_24[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_25 = _uncommonBits_T_25[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_26 = _uncommonBits_T_26[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_27 = _uncommonBits_T_27[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_44 = _uncommonBits_T_44[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_45 = _uncommonBits_T_45[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_48 = _uncommonBits_T_48[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_49 = _uncommonBits_T_49[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_56 = _uncommonBits_T_56[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_57 = _uncommonBits_T_57[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_66 = _uncommonBits_T_66[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_67 = _uncommonBits_T_67[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_68 = _uncommonBits_T_68[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_69 = _uncommonBits_T_69[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_70 = _uncommonBits_T_70[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_71 = _uncommonBits_T_71[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_54 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_60 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_66 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_72 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_78 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_84 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_90 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_96 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire _source_ok_T_55 = &_source_ok_T_54; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = source_ok_uncommonBits_8 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_59 = _source_ok_T_57 & _source_ok_T_58; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 3'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = source_ok_uncommonBits_9 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_65 = _source_ok_T_63 & _source_ok_T_64; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_1 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 3'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_10 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_2 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_73 = _source_ok_T_72 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = source_ok_uncommonBits_11 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_77 = _source_ok_T_75 & _source_ok_T_76; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_3 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_79 = _source_ok_T_78 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = source_ok_uncommonBits_12 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_83 = _source_ok_T_81 & _source_ok_T_82; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_4 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_85 = _source_ok_T_84 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = source_ok_uncommonBits_13 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_89 = _source_ok_T_87 & _source_ok_T_88; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_91 = _source_ok_T_90 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_94 = source_ok_uncommonBits_14 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_6 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_97 = _source_ok_T_96 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_99 = _source_ok_T_97; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_100 = source_ok_uncommonBits_15 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_101 = _source_ok_T_99 & _source_ok_T_100; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_107 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1162 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1235 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1235; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1235; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1235; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [243:0] inflight; // @[Monitor.scala:614:27] reg [975:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [975:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [243:0] a_set; // @[Monitor.scala:626:34] wire [243:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [975:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [975:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [975:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [975:0] _a_opcode_lookup_T_6 = {972'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [975:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [975:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [975:0] _a_size_lookup_T_6 = {972'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [975:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[975:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_1088 = _T_1162 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1088 ? _a_set_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1088 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1088 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1088 ? _a_opcodes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1088 ? _a_sizes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [243:0] d_clr; // @[Monitor.scala:664:34] wire [243:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [975:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [975:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1134 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1134 & ~d_release_ack ? _d_clr_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_1103 = _T_1235 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1103 ? _d_clr_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1103 ? _d_opcodes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1103 ? _d_sizes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [243:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [243:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [243:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [975:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [975:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [975:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [975:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [975:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [975:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [243:0] inflight_1; // @[Monitor.scala:726:35] wire [243:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [975:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [975:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [975:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [975:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [975:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [975:0] _c_opcode_lookup_T_6 = {972'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [975:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [975:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [975:0] _c_size_lookup_T_6 = {972'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [975:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[975:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [243:0] d_clr_1; // @[Monitor.scala:774:34] wire [243:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [975:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [975:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1206 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1206 & d_release_ack_1 ? _d_clr_wo_ready_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_1188 = _T_1235 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1188 ? _d_clr_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1188 ? _d_opcodes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1188 ? _d_sizes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [243:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [243:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [975:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [975:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [975:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [975:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_41 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready

module TLBuffer_a32d64s2k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLROM : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in wire rom : UInt<64>[512] connect rom[0], UInt<64>(0h405051300000517) connect rom[1], UInt<64>(0h301022f330551073) connect rom[2], UInt<64>(0h12f2934122d293) connect rom[3], UInt<64>(0h3030107300028863) connect rom[4], UInt<64>(0h3445307322200513) connect rom[5], UInt<64>(0h3045107300800513) connect rom[6], UInt<64>(0h1050007330052073) connect rom[7], UInt<64>(0hffdff06f) connect rom[8], UInt<64>(0hf1402573020005b7) connect rom[9], UInt<64>(0h380006f00050463) connect rom[10], UInt<64>(0h10069300458613) connect rom[11], UInt<64>(0h46061300d62023) connect rom[12], UInt<64>(0hfe069ae3ffc62683) connect rom[13], UInt<64>(0h2c0006f) connect rom[14], UInt<64>(0h0) connect rom[15], UInt<64>(0h0) connect rom[16], UInt<64>(0h5a283f81ff06f) connect rom[17], UInt<64>(0h251513fe029ee3) connect rom[18], UInt<64>(0h5a02300b505b3) connect rom[19], UInt<64>(0h5350300001537) connect rom[20], UInt<64>(0hf140257334151073) connect rom[21], UInt<64>(0h185859300000597) connect rom[22], UInt<64>(0h3006307308000613) connect rom[23], UInt<64>(0h1330200073) connect rom[24], UInt<64>(0h2b0b0000edfe0dd0) connect rom[25], UInt<64>(0h6809000038000000) connect rom[26], UInt<64>(0h1100000028000000) connect rom[27], UInt<64>(0h10000000) connect rom[28], UInt<64>(0h30090000c3010000) connect rom[29], UInt<64>(0h0) connect rom[30], UInt<64>(0h0) connect rom[31], UInt<64>(0h1000000) connect rom[32], UInt<64>(0h400000003000000) connect rom[33], UInt<64>(0h100000000000000) connect rom[34], UInt<64>(0h400000003000000) connect rom[35], UInt<64>(0h10000000f000000) connect rom[36], UInt<64>(0h1500000003000000) connect rom[37], UInt<64>(0h2d6263751b000000) connect rom[38], UInt<64>(0h706968632c726162) connect rom[39], UInt<64>(0h7665642d64726179) connect rom[40], UInt<64>(0h300000000000000) connect rom[41], UInt<64>(0h2600000011000000) connect rom[42], UInt<64>(0h2c7261622d626375) connect rom[43], UInt<64>(0h6472617970696863) connect rom[44], UInt<64>(0h100000000000000) connect rom[45], UInt<64>(0h73657361696c61) connect rom[46], UInt<64>(0h1500000003000000) connect rom[47], UInt<64>(0h636f732f2c000000) connect rom[48], UInt<64>(0h406c61697265732f) connect rom[49], UInt<64>(0h3030303032303031) connect rom[50], UInt<64>(0h200000000000000) connect rom[51], UInt<64>(0h736f686301000000) connect rom[52], UInt<64>(0h300000000006e65) connect rom[53], UInt<64>(0h3400000015000000) connect rom[54], UInt<64>(0h7265732f636f732f) connect rom[55], UInt<64>(0h32303031406c6169) connect rom[56], UInt<64>(0h30303030) connect rom[57], UInt<64>(0h100000002000000) connect rom[58], UInt<64>(0h73757063) connect rom[59], UInt<64>(0h400000003000000) connect rom[60], UInt<64>(0h100000000000000) connect rom[61], UInt<64>(0h400000003000000) connect rom[62], UInt<64>(0hf000000) connect rom[63], UInt<64>(0h400000003000000) connect rom[64], UInt<64>(0h20a1070040000000) connect rom[65], UInt<64>(0h4075706301000000) connect rom[66], UInt<64>(0h300000000000030) connect rom[67], UInt<64>(0h5300000004000000) connect rom[68], UInt<64>(0h300000000000000) connect rom[69], UInt<64>(0h1b00000015000000) connect rom[70], UInt<64>(0h722c657669666973) connect rom[71], UInt<64>(0h72003074656b636f) connect rom[72], UInt<64>(0h76637369) connect rom[73], UInt<64>(0h400000003000000) connect rom[74], UInt<64>(0h75706363000000) connect rom[75], UInt<64>(0h400000003000000) connect rom[76], UInt<64>(0h10000006f000000) connect rom[77], UInt<64>(0h400000003000000) connect rom[78], UInt<64>(0h400000008e000000) connect rom[79], UInt<64>(0h400000003000000) connect rom[80], UInt<64>(0h40000000a1000000) connect rom[81], UInt<64>(0h400000003000000) connect rom[82], UInt<64>(0h800000ae000000) connect rom[83], UInt<64>(0h400000003000000) connect rom[84], UInt<64>(0hbb000000) connect rom[85], UInt<64>(0h3800000003000000) connect rom[86], UInt<64>(0h34367672bf000000) connect rom[87], UInt<64>(0h7a62636466616d69) connect rom[88], UInt<64>(0h66697a5f72736369) connect rom[89], UInt<64>(0h697a5f6965636e65) connect rom[90], UInt<64>(0h5f68667a5f6d7068) connect rom[91], UInt<64>(0h5f62627a5f61627a) connect rom[92], UInt<64>(0h636f72785f73627a) connect rom[93], UInt<64>(0h30000000074656b) connect rom[94], UInt<64>(0hc900000004000000) connect rom[95], UInt<64>(0h300000004000000) connect rom[96], UInt<64>(0hde00000004000000) connect rom[97], UInt<64>(0h300000008000000) connect rom[98], UInt<64>(0hef00000004000000) connect rom[99], UInt<64>(0h300000001000000) connect rom[100], UInt<64>(0hfb00000005000000) connect rom[101], UInt<64>(0h79616b6f) connect rom[102], UInt<64>(0h400000003000000) connect rom[103], UInt<64>(0h20a1070040000000) connect rom[104], UInt<64>(0h65746e6901000000) connect rom[105], UInt<64>(0h6f632d7470757272) connect rom[106], UInt<64>(0h72656c6c6f72746e) connect rom[107], UInt<64>(0h300000000000000) connect rom[108], UInt<64>(0h201000004000000) connect rom[109], UInt<64>(0h300000001000000) connect rom[110], UInt<64>(0h1b0000000f000000) connect rom[111], UInt<64>(0h70632c7663736972) connect rom[112], UInt<64>(0h63746e692d75) connect rom[113], UInt<64>(0h3000000) connect rom[114], UInt<64>(0h300000013010000) connect rom[115], UInt<64>(0h2801000004000000) connect rom[116], UInt<64>(0h200000002000000) connect rom[117], UInt<64>(0h200000002000000) connect rom[118], UInt<64>(0h6669746801000000) connect rom[119], UInt<64>(0h300000000000000) connect rom[120], UInt<64>(0h1b0000000a000000) connect rom[121], UInt<64>(0h666974682c626375) connect rom[122], UInt<64>(0h200000000000030) connect rom[123], UInt<64>(0h636f7301000000) connect rom[124], UInt<64>(0h400000003000000) connect rom[125], UInt<64>(0h100000000000000) connect rom[126], UInt<64>(0h400000003000000) connect rom[127], UInt<64>(0h10000000f000000) connect rom[128], UInt<64>(0h2000000003000000) connect rom[129], UInt<64>(0h2d6263751b000000) connect rom[130], UInt<64>(0h706968632c726162) connect rom[131], UInt<64>(0h636f732d64726179) connect rom[132], UInt<64>(0h2d656c706d697300) connect rom[133], UInt<64>(0h300000000737562) connect rom[134], UInt<64>(0h3001000000000000) connect rom[135], UInt<64>(0h746f6f6201000000) connect rom[136], UInt<64>(0h737365726464612d) connect rom[137], UInt<64>(0h303031406765722d) connect rom[138], UInt<64>(0h300000000000030) connect rom[139], UInt<64>(0hbb00000008000000) connect rom[140], UInt<64>(0h10000000100000) connect rom[141], UInt<64>(0h800000003000000) connect rom[142], UInt<64>(0h746e6f6337010000) connect rom[143], UInt<64>(0h2000000006c6f72) connect rom[144], UInt<64>(0h7375626301000000) connect rom[145], UInt<64>(0h6b636f6c635f) connect rom[146], UInt<64>(0h400000003000000) connect rom[147], UInt<64>(0h41010000) connect rom[148], UInt<64>(0h400000003000000) connect rom[149], UInt<64>(0h65cd1d53000000) connect rom[150], UInt<64>(0hb00000003000000) connect rom[151], UInt<64>(0h737562634e010000) connect rom[152], UInt<64>(0h6b636f6c635f) connect rom[153], UInt<64>(0hc00000003000000) connect rom[154], UInt<64>(0h657869661b000000) connect rom[155], UInt<64>(0h6b636f6c632d64) connect rom[156], UInt<64>(0h100000002000000) connect rom[157], UInt<64>(0h303240746e696c63) connect rom[158], UInt<64>(0h3030303030) connect rom[159], UInt<64>(0hd00000003000000) connect rom[160], UInt<64>(0h637369721b000000) connect rom[161], UInt<64>(0h30746e696c632c76) connect rom[162], UInt<64>(0h300000000000000) connect rom[163], UInt<64>(0h6101000010000000) connect rom[164], UInt<64>(0h300000002000000) connect rom[165], UInt<64>(0h700000002000000) connect rom[166], UInt<64>(0h800000003000000) connect rom[167], UInt<64>(0h2bb000000) connect rom[168], UInt<64>(0h300000000000100) connect rom[169], UInt<64>(0h3701000008000000) connect rom[170], UInt<64>(0h6c6f72746e6f63) connect rom[171], UInt<64>(0h100000002000000) connect rom[172], UInt<64>(0h61672d6b636f6c63) connect rom[173], UInt<64>(0h3030303140726574) connect rom[174], UInt<64>(0h300000000003030) connect rom[175], UInt<64>(0hbb00000008000000) connect rom[176], UInt<64>(0h10000000001000) connect rom[177], UInt<64>(0h800000003000000) connect rom[178], UInt<64>(0h746e6f6337010000) connect rom[179], UInt<64>(0h2000000006c6f72) connect rom[180], UInt<64>(0h7562656401000000) connect rom[181], UInt<64>(0h6f72746e6f632d67) connect rom[182], UInt<64>(0h304072656c6c) connect rom[183], UInt<64>(0h2100000003000000) connect rom[184], UInt<64>(0h696669731b000000) connect rom[185], UInt<64>(0h67756265642c6576) connect rom[186], UInt<64>(0h736972003331302d) connect rom[187], UInt<64>(0h67756265642c7663) connect rom[188], UInt<64>(0h3331302d) connect rom[189], UInt<64>(0h500000003000000) connect rom[190], UInt<64>(0h6761746a75010000) connect rom[191], UInt<64>(0h300000000000000) connect rom[192], UInt<64>(0h6101000008000000) connect rom[193], UInt<64>(0hffff000002000000) connect rom[194], UInt<64>(0h800000003000000) connect rom[195], UInt<64>(0hbb000000) connect rom[196], UInt<64>(0h300000000100000) connect rom[197], UInt<64>(0h3701000008000000) connect rom[198], UInt<64>(0h6c6f72746e6f63) connect rom[199], UInt<64>(0h100000002000000) connect rom[200], UInt<64>(0h303038406d697464) connect rom[201], UInt<64>(0h3030303030) connect rom[202], UInt<64>(0hd00000003000000) connect rom[203], UInt<64>(0h696669731b000000) connect rom[204], UInt<64>(0h306d6974642c6576) connect rom[205], UInt<64>(0h300000000000000) connect rom[206], UInt<64>(0hbb00000008000000) connect rom[207], UInt<64>(0h40000000000080) connect rom[208], UInt<64>(0h400000003000000) connect rom[209], UInt<64>(0h6d656d37010000) connect rom[210], UInt<64>(0h400000003000000) connect rom[211], UInt<64>(0h100000028010000) connect rom[212], UInt<64>(0h100000002000000) connect rom[213], UInt<64>(0h65642d726f727265) connect rom[214], UInt<64>(0h3030334065636976) connect rom[215], UInt<64>(0h300000000000030) connect rom[216], UInt<64>(0h1b0000000e000000) connect rom[217], UInt<64>(0h652c657669666973) connect rom[218], UInt<64>(0h30726f7272) connect rom[219], UInt<64>(0h800000003000000) connect rom[220], UInt<64>(0h300000bb000000) connect rom[221], UInt<64>(0h200000000100000) connect rom[222], UInt<64>(0h7375626601000000) connect rom[223], UInt<64>(0h6b636f6c635f) connect rom[224], UInt<64>(0h400000003000000) connect rom[225], UInt<64>(0h41010000) connect rom[226], UInt<64>(0h400000003000000) connect rom[227], UInt<64>(0h65cd1d53000000) connect rom[228], UInt<64>(0hb00000003000000) connect rom[229], UInt<64>(0h737562664e010000) connect rom[230], UInt<64>(0h6b636f6c635f) connect rom[231], UInt<64>(0hc00000003000000) connect rom[232], UInt<64>(0h657869661b000000) connect rom[233], UInt<64>(0h6b636f6c632d64) connect rom[234], UInt<64>(0h100000002000000) connect rom[235], UInt<64>(0h7075727265746e69) connect rom[236], UInt<64>(0h6f72746e6f632d74) connect rom[237], UInt<64>(0h3030634072656c6c) connect rom[238], UInt<64>(0h30303030) connect rom[239], UInt<64>(0h400000003000000) connect rom[240], UInt<64>(0h100000002010000) connect rom[241], UInt<64>(0hc00000003000000) connect rom[242], UInt<64>(0h637369721b000000) connect rom[243], UInt<64>(0h3063696c702c76) connect rom[244], UInt<64>(0h3000000) connect rom[245], UInt<64>(0h300000013010000) connect rom[246], UInt<64>(0h6101000008000000) connect rom[247], UInt<64>(0hb00000002000000) connect rom[248], UInt<64>(0h800000003000000) connect rom[249], UInt<64>(0hcbb000000) connect rom[250], UInt<64>(0h300000000000004) connect rom[251], UInt<64>(0h3701000008000000) connect rom[252], UInt<64>(0h6c6f72746e6f63) connect rom[253], UInt<64>(0h400000003000000) connect rom[254], UInt<64>(0h100000082010000) connect rom[255], UInt<64>(0h400000003000000) connect rom[256], UInt<64>(0h100000095010000) connect rom[257], UInt<64>(0h400000003000000) connect rom[258], UInt<64>(0h400000028010000) connect rom[259], UInt<64>(0h100000002000000) connect rom[260], UInt<64>(0h6f6c635f73756270) connect rom[261], UInt<64>(0h300000000006b63) connect rom[262], UInt<64>(0h4101000004000000) connect rom[263], UInt<64>(0h300000000000000) connect rom[264], UInt<64>(0h5300000004000000) connect rom[265], UInt<64>(0h30000000065cd1d) connect rom[266], UInt<64>(0h4e0100000b000000) connect rom[267], UInt<64>(0h6f6c635f73756270) connect rom[268], UInt<64>(0h300000000006b63) connect rom[269], UInt<64>(0h1b0000000c000000) connect rom[270], UInt<64>(0h6c632d6465786966) connect rom[271], UInt<64>(0h3000000006b636f) connect rom[272], UInt<64>(0h2801000004000000) connect rom[273], UInt<64>(0h200000003000000) connect rom[274], UInt<64>(0h406d6f7201000000) connect rom[275], UInt<64>(0h3030303031) connect rom[276], UInt<64>(0hc00000003000000) connect rom[277], UInt<64>(0h696669731b000000) connect rom[278], UInt<64>(0h306d6f722c6576) connect rom[279], UInt<64>(0h800000003000000) connect rom[280], UInt<64>(0h100bb000000) connect rom[281], UInt<64>(0h300000000000100) connect rom[282], UInt<64>(0h3701000004000000) connect rom[283], UInt<64>(0h2000000006d656d) connect rom[284], UInt<64>(0h7375627301000000) connect rom[285], UInt<64>(0h6b636f6c635f) connect rom[286], UInt<64>(0h400000003000000) connect rom[287], UInt<64>(0h41010000) connect rom[288], UInt<64>(0h400000003000000) connect rom[289], UInt<64>(0h65cd1d53000000) connect rom[290], UInt<64>(0hb00000003000000) connect rom[291], UInt<64>(0h737562734e010000) connect rom[292], UInt<64>(0h6b636f6c635f) connect rom[293], UInt<64>(0hc00000003000000) connect rom[294], UInt<64>(0h657869661b000000) connect rom[295], UInt<64>(0h6b636f6c632d64) connect rom[296], UInt<64>(0h100000002000000) connect rom[297], UInt<64>(0h31406c6169726573) connect rom[298], UInt<64>(0h30303030323030) connect rom[299], UInt<64>(0h400000003000000) connect rom[300], UInt<64>(0h3000000a0010000) connect rom[301], UInt<64>(0hd00000003000000) connect rom[302], UInt<64>(0h696669731b000000) connect rom[303], UInt<64>(0h30747261752c6576) connect rom[304], UInt<64>(0h300000000000000) connect rom[305], UInt<64>(0ha701000004000000) connect rom[306], UInt<64>(0h300000004000000) connect rom[307], UInt<64>(0hb801000004000000) connect rom[308], UInt<64>(0h300000001000000) connect rom[309], UInt<64>(0hbb00000008000000) connect rom[310], UInt<64>(0h10000000000210) connect rom[311], UInt<64>(0h800000003000000) connect rom[312], UInt<64>(0h746e6f6337010000) connect rom[313], UInt<64>(0h2000000006c6f72) connect rom[314], UInt<64>(0h656c697401000000) connect rom[315], UInt<64>(0h732d74657365722d) connect rom[316], UInt<64>(0h3131407265747465) connect rom[317], UInt<64>(0h30303030) connect rom[318], UInt<64>(0h800000003000000) connect rom[319], UInt<64>(0h1100bb000000) connect rom[320], UInt<64>(0h300000000100000) connect rom[321], UInt<64>(0h3701000008000000) connect rom[322], UInt<64>(0h6c6f72746e6f63) connect rom[323], UInt<64>(0h200000002000000) connect rom[324], UInt<64>(0h900000002000000) connect rom[325], UInt<64>(0h7373657264646123) connect rom[326], UInt<64>(0h2300736c6c65632d) connect rom[327], UInt<64>(0h6c65632d657a6973) connect rom[328], UInt<64>(0h61706d6f6300736c) connect rom[329], UInt<64>(0h6f6d00656c626974) connect rom[330], UInt<64>(0h69726573006c6564) connect rom[331], UInt<64>(0h6f64747300306c61) connect rom[332], UInt<64>(0h687461702d7475) connect rom[333], UInt<64>(0h65736162656d6974) connect rom[334], UInt<64>(0h6e6575716572662d) connect rom[335], UInt<64>(0h6b636f6c63007963) connect rom[336], UInt<64>(0h6e6575716572662d) connect rom[337], UInt<64>(0h6369766564007963) connect rom[338], UInt<64>(0h6800657079745f65) connect rom[339], UInt<64>(0h2d65726177647261) connect rom[340], UInt<64>(0h6572622d63657865) connect rom[341], UInt<64>(0h2d746e696f706b61) connect rom[342], UInt<64>(0h2d6900746e756f63) connect rom[343], UInt<64>(0h6c622d6568636163) connect rom[344], UInt<64>(0h657a69732d6b636f) connect rom[345], UInt<64>(0h65686361632d6900) connect rom[346], UInt<64>(0h2d6900737465732d) connect rom[347], UInt<64>(0h69732d6568636163) connect rom[348], UInt<64>(0h720067657200657a) connect rom[349], UInt<64>(0h6173692c76637369) connect rom[350], UInt<64>(0h702c766373697200) connect rom[351], UInt<64>(0h6c756e617267706d) connect rom[352], UInt<64>(0h6972007974697261) connect rom[353], UInt<64>(0h72706d702c766373) connect rom[354], UInt<64>(0h7300736e6f696765) connect rom[355], UInt<64>(0h74642c6576696669) connect rom[356], UInt<64>(0h7574617473006d69) connect rom[357], UInt<64>(0h7265746e69230073) connect rom[358], UInt<64>(0h6c65632d74707572) connect rom[359], UInt<64>(0h7265746e6900736c) connect rom[360], UInt<64>(0h6e6f632d74707572) connect rom[361], UInt<64>(0h72656c6c6f7274) connect rom[362], UInt<64>(0h656c646e616870) connect rom[363], UInt<64>(0h72007365676e6172) connect rom[364], UInt<64>(0h73656d616e2d6765) connect rom[365], UInt<64>(0h2d6b636f6c632300) connect rom[366], UInt<64>(0h6c6300736c6c6563) connect rom[367], UInt<64>(0h7074756f2d6b636f) connect rom[368], UInt<64>(0h73656d616e2d7475) connect rom[369], UInt<64>(0h75727265746e6900) connect rom[370], UInt<64>(0h657478652d737470) connect rom[371], UInt<64>(0h626564006465646e) connect rom[372], UInt<64>(0h63617474612d6775) connect rom[373], UInt<64>(0h2c76637369720068) connect rom[374], UInt<64>(0h6f6972702d78616d) connect rom[375], UInt<64>(0h7369720079746972) connect rom[376], UInt<64>(0h7665646e2c7663) connect rom[377], UInt<64>(0h6900736b636f6c63) connect rom[378], UInt<64>(0h747075727265746e) connect rom[379], UInt<64>(0h746e657261702d) connect rom[380], UInt<64>(0h7075727265746e69) connect rom[381], UInt<64>(0h7374) connect rom[382], UInt<64>(0h0) connect rom[383], UInt<64>(0h0) connect rom[384], UInt<64>(0h0) connect rom[385], UInt<64>(0h0) connect rom[386], UInt<64>(0h0) connect rom[387], UInt<64>(0h0) connect rom[388], UInt<64>(0h0) connect rom[389], UInt<64>(0h0) connect rom[390], UInt<64>(0h0) connect rom[391], UInt<64>(0h0) connect rom[392], UInt<64>(0h0) connect rom[393], UInt<64>(0h0) connect rom[394], UInt<64>(0h0) connect rom[395], UInt<64>(0h0) connect rom[396], UInt<64>(0h0) connect rom[397], UInt<64>(0h0) connect rom[398], UInt<64>(0h0) connect rom[399], UInt<64>(0h0) connect rom[400], UInt<64>(0h0) connect rom[401], UInt<64>(0h0) connect rom[402], UInt<64>(0h0) connect rom[403], UInt<64>(0h0) connect rom[404], UInt<64>(0h0) connect rom[405], UInt<64>(0h0) connect rom[406], UInt<64>(0h0) connect rom[407], UInt<64>(0h0) connect rom[408], UInt<64>(0h0) connect rom[409], UInt<64>(0h0) connect rom[410], UInt<64>(0h0) connect rom[411], UInt<64>(0h0) connect rom[412], UInt<64>(0h0) connect rom[413], UInt<64>(0h0) connect rom[414], UInt<64>(0h0) connect rom[415], UInt<64>(0h0) connect rom[416], UInt<64>(0h0) connect rom[417], UInt<64>(0h0) connect rom[418], UInt<64>(0h0) connect rom[419], UInt<64>(0h0) connect rom[420], UInt<64>(0h0) connect rom[421], UInt<64>(0h0) connect rom[422], UInt<64>(0h0) connect rom[423], UInt<64>(0h0) connect rom[424], UInt<64>(0h0) connect rom[425], UInt<64>(0h0) connect rom[426], UInt<64>(0h0) connect rom[427], UInt<64>(0h0) connect rom[428], UInt<64>(0h0) connect rom[429], UInt<64>(0h0) connect rom[430], UInt<64>(0h0) connect rom[431], UInt<64>(0h0) connect rom[432], UInt<64>(0h0) connect rom[433], UInt<64>(0h0) connect rom[434], UInt<64>(0h0) connect rom[435], UInt<64>(0h0) connect rom[436], UInt<64>(0h0) connect rom[437], UInt<64>(0h0) connect rom[438], UInt<64>(0h0) connect rom[439], UInt<64>(0h0) connect rom[440], UInt<64>(0h0) connect rom[441], UInt<64>(0h0) connect rom[442], UInt<64>(0h0) connect rom[443], UInt<64>(0h0) connect rom[444], UInt<64>(0h0) connect rom[445], UInt<64>(0h0) connect rom[446], UInt<64>(0h0) connect rom[447], UInt<64>(0h0) connect rom[448], UInt<64>(0h0) connect rom[449], UInt<64>(0h0) connect rom[450], UInt<64>(0h0) connect rom[451], UInt<64>(0h0) connect rom[452], UInt<64>(0h0) connect rom[453], UInt<64>(0h0) connect rom[454], UInt<64>(0h0) connect rom[455], UInt<64>(0h0) connect rom[456], UInt<64>(0h0) connect rom[457], UInt<64>(0h0) connect rom[458], UInt<64>(0h0) connect rom[459], UInt<64>(0h0) connect rom[460], UInt<64>(0h0) connect rom[461], UInt<64>(0h0) connect rom[462], UInt<64>(0h0) connect rom[463], UInt<64>(0h0) connect rom[464], UInt<64>(0h0) connect rom[465], UInt<64>(0h0) connect rom[466], UInt<64>(0h0) connect rom[467], UInt<64>(0h0) connect rom[468], UInt<64>(0h0) connect rom[469], UInt<64>(0h0) connect rom[470], UInt<64>(0h0) connect rom[471], UInt<64>(0h0) connect rom[472], UInt<64>(0h0) connect rom[473], UInt<64>(0h0) connect rom[474], UInt<64>(0h0) connect rom[475], UInt<64>(0h0) connect rom[476], UInt<64>(0h0) connect rom[477], UInt<64>(0h0) connect rom[478], UInt<64>(0h0) connect rom[479], UInt<64>(0h0) connect rom[480], UInt<64>(0h0) connect rom[481], UInt<64>(0h0) connect rom[482], UInt<64>(0h0) connect rom[483], UInt<64>(0h0) connect rom[484], UInt<64>(0h0) connect rom[485], UInt<64>(0h0) connect rom[486], UInt<64>(0h0) connect rom[487], UInt<64>(0h0) connect rom[488], UInt<64>(0h0) connect rom[489], UInt<64>(0h0) connect rom[490], UInt<64>(0h0) connect rom[491], UInt<64>(0h0) connect rom[492], UInt<64>(0h0) connect rom[493], UInt<64>(0h0) connect rom[494], UInt<64>(0h0) connect rom[495], UInt<64>(0h0) connect rom[496], UInt<64>(0h0) connect rom[497], UInt<64>(0h0) connect rom[498], UInt<64>(0h0) connect rom[499], UInt<64>(0h0) connect rom[500], UInt<64>(0h0) connect rom[501], UInt<64>(0h0) connect rom[502], UInt<64>(0h0) connect rom[503], UInt<64>(0h0) connect rom[504], UInt<64>(0h0) connect rom[505], UInt<64>(0h0) connect rom[506], UInt<64>(0h0) connect rom[507], UInt<64>(0h0) connect rom[508], UInt<64>(0h0) connect rom[509], UInt<64>(0h0) connect rom[510], UInt<64>(0h0) connect rom[511], UInt<64>(0h0) connect nodeIn.d.valid, nodeIn.a.valid connect nodeIn.a.ready, nodeIn.d.ready node index = bits(nodeIn.a.bits.address, 11, 3) node high = bits(nodeIn.a.bits.address, 15, 12) node _nodeIn_d_bits_T = orr(high) node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, nodeIn.a.bits.size connect nodeIn_d_bits_d.source, nodeIn.a.bits.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)

module TLROM( // @[BootROM.scala:41:9] input clock, // @[BootROM.scala:41:9] input reset, // @[BootROM.scala:41:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9] wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9] wire [511:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h7374, 64'h7075727265746E69, 64'h746E657261702D, 64'h747075727265746E, 64'h6900736B636F6C63, 64'h7665646E2C7663, 64'h7369720079746972, 64'h6F6972702D78616D, 64'h2C76637369720068, 64'h63617474612D6775, 64'h626564006465646E, 64'h657478652D737470, 64'h75727265746E6900, 64'h73656D616E2D7475, 64'h7074756F2D6B636F, 64'h6C6300736C6C6563, 64'h2D6B636F6C632300, 64'h73656D616E2D6765, 64'h72007365676E6172, 64'h656C646E616870, 64'h72656C6C6F7274, 64'h6E6F632D74707572, 64'h7265746E6900736C, 64'h6C65632D74707572, 64'h7265746E69230073, 64'h7574617473006D69, 64'h74642C6576696669, 64'h7300736E6F696765, 64'h72706D702C766373, 64'h6972007974697261, 64'h6C756E617267706D, 64'h702C766373697200, 64'h6173692C76637369, 64'h720067657200657A, 64'h69732D6568636163, 64'h2D6900737465732D, 64'h65686361632D6900, 64'h657A69732D6B636F, 64'h6C622D6568636163, 64'h2D6900746E756F63, 64'h2D746E696F706B61, 64'h6572622D63657865, 64'h2D65726177647261, 64'h6800657079745F65, 64'h6369766564007963, 64'h6E6575716572662D, 64'h6B636F6C63007963, 64'h6E6575716572662D, 64'h65736162656D6974, 64'h687461702D7475, 64'h6F64747300306C61, 64'h69726573006C6564, 64'h6F6D00656C626974, 64'h61706D6F6300736C, 64'h6C65632D657A6973, 64'h2300736C6C65632D, 64'h7373657264646123, 64'h900000002000000, 64'h200000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000100000, 64'h1100BB000000, 64'h800000003000000, 64'h30303030, 64'h3131407265747465, 64'h732D74657365722D, 64'h656C697401000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000000210, 64'hBB00000008000000, 64'h300000001000000, 64'hB801000004000000, 64'h300000004000000, 64'hA701000004000000, 64'h300000000000000, 64'h30747261752C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h3000000A0010000, 64'h400000003000000, 64'h30303030323030, 64'h31406C6169726573, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562734E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375627301000000, 64'h2000000006D656D, 64'h3701000004000000, 64'h300000000000100, 64'h100BB000000, 64'h800000003000000, 64'h306D6F722C6576, 64'h696669731B000000, 64'hC00000003000000, 64'h3030303031, 64'h406D6F7201000000, 64'h200000003000000, 64'h2801000004000000, 64'h3000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h4E0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'h4101000004000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h100000002000000, 64'h400000028010000, 64'h400000003000000, 64'h100000095010000, 64'h400000003000000, 64'h100000082010000, 64'h400000003000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000000004, 64'hCBB000000, 64'h800000003000000, 64'hB00000002000000, 64'h6101000008000000, 64'h300000013010000, 64'h3000000, 64'h3063696C702C76, 64'h637369721B000000, 64'hC00000003000000, 64'h100000002010000, 64'h400000003000000, 64'h30303030, 64'h3030634072656C6C, 64'h6F72746E6F632D74, 64'h7075727265746E69, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562664E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626601000000, 64'h200000000100000, 64'h300000BB000000, 64'h800000003000000, 64'h30726F7272, 64'h652C657669666973, 64'h1B0000000E000000, 64'h300000000000030, 64'h3030334065636976, 64'h65642D726F727265, 64'h100000002000000, 64'h100000028010000, 64'h400000003000000, 64'h6D656D37010000, 64'h400000003000000, 64'h40000000000080, 64'hBB00000008000000, 64'h300000000000000, 64'h306D6974642C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h3030303030, 64'h303038406D697464, 64'h100000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000100000, 64'hBB000000, 64'h800000003000000, 64'hFFFF000002000000, 64'h6101000008000000, 64'h300000000000000, 64'h6761746A75010000, 64'h500000003000000, 64'h3331302D, 64'h67756265642C7663, 64'h736972003331302D, 64'h67756265642C6576, 64'h696669731B000000, 64'h2100000003000000, 64'h304072656C6C, 64'h6F72746E6F632D67, 64'h7562656401000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000001000, 64'hBB00000008000000, 64'h300000000003030, 64'h3030303140726574, 64'h61672D6B636F6C63, 64'h100000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000000100, 64'h2BB000000, 64'h800000003000000, 64'h700000002000000, 64'h300000002000000, 64'h6101000010000000, 64'h300000000000000, 64'h30746E696C632C76, 64'h637369721B000000, 64'hD00000003000000, 64'h3030303030, 64'h303240746E696C63, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562634E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626301000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000100000, 64'hBB00000008000000, 64'h300000000000030, 64'h303031406765722D, 64'h737365726464612D, 64'h746F6F6201000000, 64'h3001000000000000, 64'h300000000737562, 64'h2D656C706D697300, 64'h636F732D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h2000000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h636F7301000000, 64'h200000000000030, 64'h666974682C626375, 64'h1B0000000A000000, 64'h300000000000000, 64'h6669746801000000, 64'h200000002000000, 64'h200000002000000, 64'h2801000004000000, 64'h300000013010000, 64'h3000000, 64'h63746E692D75, 64'h70632C7663736972, 64'h1B0000000F000000, 64'h300000001000000, 64'h201000004000000, 64'h300000000000000, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6901000000, 64'h20A1070040000000, 64'h400000003000000, 64'h79616B6F, 64'hFB00000005000000, 64'h300000001000000, 64'hEF00000004000000, 64'h300000008000000, 64'hDE00000004000000, 64'h300000004000000, 64'hC900000004000000, 64'h30000000074656B, 64'h636F72785F73627A, 64'h5F62627A5F61627A, 64'h5F68667A5F6D7068, 64'h697A5F6965636E65, 64'h66697A5F72736369, 64'h7A62636466616D69, 64'h34367672BF000000, 64'h3800000003000000, 64'hBB000000, 64'h400000003000000, 64'h800000AE000000, 64'h400000003000000, 64'h40000000A1000000, 64'h400000003000000, 64'h400000008E000000, 64'h400000003000000, 64'h10000006F000000, 64'h400000003000000, 64'h75706363000000, 64'h400000003000000, 64'h76637369, 64'h72003074656B636F, 64'h722C657669666973, 64'h1B00000015000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000030, 64'h4075706301000000, 64'h20A1070040000000, 64'h400000003000000, 64'hF000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h73757063, 64'h100000002000000, 64'h30303030, 64'h32303031406C6169, 64'h7265732F636F732F, 64'h3400000015000000, 64'h300000000006E65, 64'h736F686301000000, 64'h200000000000000, 64'h3030303032303031, 64'h406C61697265732F, 64'h636F732F2C000000, 64'h1500000003000000, 64'h73657361696C61, 64'h100000000000000, 64'h6472617970696863, 64'h2C7261622D626375, 64'h2600000011000000, 64'h300000000000000, 64'h7665642D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h1500000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h1000000, 64'h0, 64'h0, 64'h30090000C3010000, 64'h10000000, 64'h1100000028000000, 64'h6809000038000000, 64'h2B0B0000EDFE0DD0, 64'h1330200073, 64'h3006307308000613, 64'h185859300000597, 64'hF140257334151073, 64'h5350300001537, 64'h5A02300B505B3, 64'h251513FE029EE3, 64'h5A283F81FF06F, 64'h0, 64'h0, 64'h2C0006F, 64'hFE069AE3FFC62683, 64'h46061300D62023, 64'h10069300458613, 64'h380006F00050463, 64'hF1402573020005B7, 64'hFFDFF06F, 64'h1050007330052073, 64'h3045107300800513, 64'h3445307322200513, 64'h3030107300028863, 64'h12F2934122D293, 64'h301022F330551073, 64'h405051300000517}; wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22] wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22] wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22] wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22] wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22] wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22] wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22] wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22] wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22] wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22] wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22] wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22] wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22] wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22] wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22] wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22] wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22] wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22] wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22] wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22] wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22] wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22] wire [63:0] rom_24 = 64'h2B0B0000EDFE0DD0; // @[BootROM.scala:50:22] wire [63:0] rom_25 = 64'h6809000038000000; // @[BootROM.scala:50:22] wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22] wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22] wire [63:0] rom_28 = 64'h30090000C3010000; // @[BootROM.scala:50:22] wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22] wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22] wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22] wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22] wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22] wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22] wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22] wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22] wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22] wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22] wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22] wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22] wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22] wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22] wire [63:0] rom_74 = 64'h75706363000000; // @[BootROM.scala:50:22] wire [63:0] rom_76 = 64'h10000006F000000; // @[BootROM.scala:50:22] wire [63:0] rom_78 = 64'h400000008E000000; // @[BootROM.scala:50:22] wire [63:0] rom_80 = 64'h40000000A1000000; // @[BootROM.scala:50:22] wire [63:0] rom_82 = 64'h800000AE000000; // @[BootROM.scala:50:22] wire [63:0] rom_85 = 64'h3800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_86 = 64'h34367672BF000000; // @[BootROM.scala:50:22] wire [63:0] rom_87 = 64'h7A62636466616D69; // @[BootROM.scala:50:22] wire [63:0] rom_88 = 64'h66697A5F72736369; // @[BootROM.scala:50:22] wire [63:0] rom_89 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22] wire [63:0] rom_90 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22] wire [63:0] rom_91 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22] wire [63:0] rom_92 = 64'h636F72785F73627A; // @[BootROM.scala:50:22] wire [63:0] rom_93 = 64'h30000000074656B; // @[BootROM.scala:50:22] wire [63:0] rom_94 = 64'hC900000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_96 = 64'hDE00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_97 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_98 = 64'hEF00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_100 = 64'hFB00000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_101 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_103 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_104 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_105 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_106 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_108 = 64'h201000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_110 = 64'h1B0000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_111 = 64'h70632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_112 = 64'h63746E692D75; // @[BootROM.scala:50:22] wire [63:0] rom_118 = 64'h6669746801000000; // @[BootROM.scala:50:22] wire [63:0] rom_120 = 64'h1B0000000A000000; // @[BootROM.scala:50:22] wire [63:0] rom_121 = 64'h666974682C626375; // @[BootROM.scala:50:22] wire [63:0] rom_122 = 64'h200000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_123 = 64'h636F7301000000; // @[BootROM.scala:50:22] wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_125 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_127 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_128 = 64'h2000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_129 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_130 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_131 = 64'h636F732D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_132 = 64'h2D656C706D697300; // @[BootROM.scala:50:22] wire [63:0] rom_133 = 64'h300000000737562; // @[BootROM.scala:50:22] wire [63:0] rom_134 = 64'h3001000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_135 = 64'h746F6F6201000000; // @[BootROM.scala:50:22] wire [63:0] rom_136 = 64'h737365726464612D; // @[BootROM.scala:50:22] wire [63:0] rom_137 = 64'h303031406765722D; // @[BootROM.scala:50:22] wire [63:0] rom_140 = 64'h10000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_144 = 64'h7375626301000000; // @[BootROM.scala:50:22] wire [63:0] rom_151 = 64'h737562634E010000; // @[BootROM.scala:50:22] wire [63:0] rom_157 = 64'h303240746E696C63; // @[BootROM.scala:50:22] wire [63:0] rom_161 = 64'h30746E696C632C76; // @[BootROM.scala:50:22] wire [63:0] rom_163 = 64'h6101000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_164 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_165 = 64'h700000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_167 = 64'h2BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_172 = 64'h61672D6B636F6C63; // @[BootROM.scala:50:22] wire [63:0] rom_173 = 64'h3030303140726574; // @[BootROM.scala:50:22] wire [63:0] rom_174 = 64'h300000000003030; // @[BootROM.scala:50:22] wire [63:0] rom_176 = 64'h10000000001000; // @[BootROM.scala:50:22] wire [63:0] rom_180 = 64'h7562656401000000; // @[BootROM.scala:50:22] wire [63:0] rom_181 = 64'h6F72746E6F632D67; // @[BootROM.scala:50:22] wire [63:0] rom_182 = 64'h304072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_183 = 64'h2100000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_185 = 64'h67756265642C6576; // @[BootROM.scala:50:22] wire [63:0] rom_186 = 64'h736972003331302D; // @[BootROM.scala:50:22] wire [63:0] rom_187 = 64'h67756265642C7663; // @[BootROM.scala:50:22] wire [63:0] rom_188 = 64'h3331302D; // @[BootROM.scala:50:22] wire [63:0] rom_189 = 64'h500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_190 = 64'h6761746A75010000; // @[BootROM.scala:50:22] wire [63:0] rom_193 = 64'hFFFF000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_84 = 64'hBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_195 = 64'hBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_200 = 64'h303038406D697464; // @[BootROM.scala:50:22] wire [63:0] rom_158 = 64'h3030303030; // @[BootROM.scala:50:22] wire [63:0] rom_201 = 64'h3030303030; // @[BootROM.scala:50:22] wire [63:0] rom_204 = 64'h306D6974642C6576; // @[BootROM.scala:50:22] wire [63:0] rom_207 = 64'h40000000000080; // @[BootROM.scala:50:22] wire [63:0] rom_209 = 64'h6D656D37010000; // @[BootROM.scala:50:22] wire [63:0] rom_211 = 64'h100000028010000; // @[BootROM.scala:50:22] wire [63:0] rom_213 = 64'h65642D726F727265; // @[BootROM.scala:50:22] wire [63:0] rom_214 = 64'h3030334065636976; // @[BootROM.scala:50:22] wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_138 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_215 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_216 = 64'h1B0000000E000000; // @[BootROM.scala:50:22] wire [63:0] rom_217 = 64'h652C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_218 = 64'h30726F7272; // @[BootROM.scala:50:22] wire [63:0] rom_220 = 64'h300000BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_221 = 64'h200000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_222 = 64'h7375626601000000; // @[BootROM.scala:50:22] wire [63:0] rom_229 = 64'h737562664E010000; // @[BootROM.scala:50:22] wire [63:0] rom_236 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_237 = 64'h3030634072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_240 = 64'h100000002010000; // @[BootROM.scala:50:22] wire [63:0] rom_160 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_242 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_243 = 64'h3063696C702C76; // @[BootROM.scala:50:22] wire [63:0] rom_113 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_244 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_114 = 64'h300000013010000; // @[BootROM.scala:50:22] wire [63:0] rom_245 = 64'h300000013010000; // @[BootROM.scala:50:22] wire [63:0] rom_192 = 64'h6101000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_246 = 64'h6101000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_247 = 64'hB00000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_249 = 64'hCBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_250 = 64'h300000000000004; // @[BootROM.scala:50:22] wire [63:0] rom_254 = 64'h100000082010000; // @[BootROM.scala:50:22] wire [63:0] rom_256 = 64'h100000095010000; // @[BootROM.scala:50:22] wire [63:0] rom_258 = 64'h400000028010000; // @[BootROM.scala:50:22] wire [63:0] rom_262 = 64'h4101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_264 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_265 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_266 = 64'h4E0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_260 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_267 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_261 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_268 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_269 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_270 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_271 = 64'h3000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_115 = 64'h2801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_272 = 64'h2801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_273 = 64'h200000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_274 = 64'h406D6F7201000000; // @[BootROM.scala:50:22] wire [63:0] rom_275 = 64'h3030303031; // @[BootROM.scala:50:22] wire [63:0] rom_278 = 64'h306D6F722C6576; // @[BootROM.scala:50:22] wire [63:0] rom_280 = 64'h100BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_168 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_281 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_282 = 64'h3701000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_283 = 64'h2000000006D656D; // @[BootROM.scala:50:22] wire [63:0] rom_284 = 64'h7375627301000000; // @[BootROM.scala:50:22] wire [63:0] rom_147 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_225 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_287 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_149 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_227 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_289 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_150 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_228 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_290 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_291 = 64'h737562734E010000; // @[BootROM.scala:50:22] wire [63:0] rom_145 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_152 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_223 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_230 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_285 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_292 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_153 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_231 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_241 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_276 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_293 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_154 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_232 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_294 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_155 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_233 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_295 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_156 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_171 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_199 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_212 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_234 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_259 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_296 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_297 = 64'h31406C6169726573; // @[BootROM.scala:50:22] wire [63:0] rom_298 = 64'h30303030323030; // @[BootROM.scala:50:22] wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_102 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_124 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_126 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_146 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_148 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_208 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_210 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_224 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_226 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_239 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_253 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_255 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_257 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_286 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_288 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_299 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_300 = 64'h3000000A0010000; // @[BootROM.scala:50:22] wire [63:0] rom_159 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_202 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_301 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_184 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_203 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_277 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_302 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_303 = 64'h30747261752C6576; // @[BootROM.scala:50:22] wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_107 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_119 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_162 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_191 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_205 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_263 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_304 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_305 = 64'hA701000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_95 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_306 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_307 = 64'hB801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_99 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_109 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_308 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_139 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_175 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_206 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_309 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_310 = 64'h10000000000210; // @[BootROM.scala:50:22] wire [63:0] rom_142 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_178 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_312 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_143 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_179 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_313 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_314 = 64'h656C697401000000; // @[BootROM.scala:50:22] wire [63:0] rom_315 = 64'h732D74657365722D; // @[BootROM.scala:50:22] wire [63:0] rom_316 = 64'h3131407265747465; // @[BootROM.scala:50:22] wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_238 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_317 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_141 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_166 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_177 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_194 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_219 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_248 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_279 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_311 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_318 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_319 = 64'h1100BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_196 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_320 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_169 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_197 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_251 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_321 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_170 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_198 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_252 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_322 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_116 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_117 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_323 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_324 = 64'h900000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_325 = 64'h7373657264646123; // @[BootROM.scala:50:22] wire [63:0] rom_326 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22] wire [63:0] rom_327 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22] wire [63:0] rom_328 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_329 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22] wire [63:0] rom_330 = 64'h69726573006C6564; // @[BootROM.scala:50:22] wire [63:0] rom_331 = 64'h6F64747300306C61; // @[BootROM.scala:50:22] wire [63:0] rom_332 = 64'h687461702D7475; // @[BootROM.scala:50:22] wire [63:0] rom_333 = 64'h65736162656D6974; // @[BootROM.scala:50:22] wire [63:0] rom_335 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22] wire [63:0] rom_334 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_336 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_337 = 64'h6369766564007963; // @[BootROM.scala:50:22] wire [63:0] rom_338 = 64'h6800657079745F65; // @[BootROM.scala:50:22] wire [63:0] rom_339 = 64'h2D65726177647261; // @[BootROM.scala:50:22] wire [63:0] rom_340 = 64'h6572622D63657865; // @[BootROM.scala:50:22] wire [63:0] rom_341 = 64'h2D746E696F706B61; // @[BootROM.scala:50:22] wire [63:0] rom_342 = 64'h2D6900746E756F63; // @[BootROM.scala:50:22] wire [63:0] rom_343 = 64'h6C622D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_344 = 64'h657A69732D6B636F; // @[BootROM.scala:50:22] wire [63:0] rom_345 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_346 = 64'h2D6900737465732D; // @[BootROM.scala:50:22] wire [63:0] rom_347 = 64'h69732D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_348 = 64'h720067657200657A; // @[BootROM.scala:50:22] wire [63:0] rom_349 = 64'h6173692C76637369; // @[BootROM.scala:50:22] wire [63:0] rom_350 = 64'h702C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_351 = 64'h6C756E617267706D; // @[BootROM.scala:50:22] wire [63:0] rom_352 = 64'h6972007974697261; // @[BootROM.scala:50:22] wire [63:0] rom_353 = 64'h72706D702C766373; // @[BootROM.scala:50:22] wire [63:0] rom_354 = 64'h7300736E6F696765; // @[BootROM.scala:50:22] wire [63:0] rom_355 = 64'h74642C6576696669; // @[BootROM.scala:50:22] wire [63:0] rom_356 = 64'h7574617473006D69; // @[BootROM.scala:50:22] wire [63:0] rom_357 = 64'h7265746E69230073; // @[BootROM.scala:50:22] wire [63:0] rom_358 = 64'h6C65632D74707572; // @[BootROM.scala:50:22] wire [63:0] rom_359 = 64'h7265746E6900736C; // @[BootROM.scala:50:22] wire [63:0] rom_360 = 64'h6E6F632D74707572; // @[BootROM.scala:50:22] wire [63:0] rom_361 = 64'h72656C6C6F7274; // @[BootROM.scala:50:22] wire [63:0] rom_362 = 64'h656C646E616870; // @[BootROM.scala:50:22] wire [63:0] rom_363 = 64'h72007365676E6172; // @[BootROM.scala:50:22] wire [63:0] rom_364 = 64'h73656D616E2D6765; // @[BootROM.scala:50:22] wire [63:0] rom_365 = 64'h2D6B636F6C632300; // @[BootROM.scala:50:22] wire [63:0] rom_366 = 64'h6C6300736C6C6563; // @[BootROM.scala:50:22] wire [63:0] rom_367 = 64'h7074756F2D6B636F; // @[BootROM.scala:50:22] wire [63:0] rom_368 = 64'h73656D616E2D7475; // @[BootROM.scala:50:22] wire [63:0] rom_369 = 64'h75727265746E6900; // @[BootROM.scala:50:22] wire [63:0] rom_370 = 64'h657478652D737470; // @[BootROM.scala:50:22] wire [63:0] rom_371 = 64'h626564006465646E; // @[BootROM.scala:50:22] wire [63:0] rom_372 = 64'h63617474612D6775; // @[BootROM.scala:50:22] wire [63:0] rom_373 = 64'h2C76637369720068; // @[BootROM.scala:50:22] wire [63:0] rom_374 = 64'h6F6972702D78616D; // @[BootROM.scala:50:22] wire [63:0] rom_375 = 64'h7369720079746972; // @[BootROM.scala:50:22] wire [63:0] rom_376 = 64'h7665646E2C7663; // @[BootROM.scala:50:22] wire [63:0] rom_377 = 64'h6900736B636F6C63; // @[BootROM.scala:50:22] wire [63:0] rom_378 = 64'h747075727265746E; // @[BootROM.scala:50:22] wire [63:0] rom_379 = 64'h746E657261702D; // @[BootROM.scala:50:22] wire [63:0] rom_235 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_380 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_381 = 64'h7374; // @[BootROM.scala:50:22] wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_382 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_383 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_384 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_385 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_386 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_387 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_388 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_389 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_390 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_391 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_392 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_393 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_394 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_395 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_396 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_397 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_398 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_399 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_400 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_401 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_402 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_403 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_404 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_405 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_406 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_407 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_408 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_409 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_410 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_411 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_412 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_413 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_414 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_415 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_416 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_417 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_418 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_419 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_420 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_421 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_422 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_423 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_424 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_425 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_426 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_427 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_428 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_429 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_430 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_431 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_432 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_433 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_434 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_435 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_436 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_437 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_438 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_439 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_440 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_441 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_442 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_443 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_444 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_445 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_446 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_447 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_448 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_449 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_450 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_451 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_452 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_453 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_454 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_455 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_456 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_457 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_458 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_459 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_460 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_461 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_462 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_463 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_464 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_465 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_466 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_467 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_468 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_469 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_470 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_471 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_472 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_473 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22] wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17] wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9] wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[BootROM.scala:41:9] wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9] wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9] wire auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9] assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17] wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17] assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9] wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9] wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34] wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64] wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53] wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}] assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17] assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17] TLMonitor_38 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[41] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 node _source_ok_T_61 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[2]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[3]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[4]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[5]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[6]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[7]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[8]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[9]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[10]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[11]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[12]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[13]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[14]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[15]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[16]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[17]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[18]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[19]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[20]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[21]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[22]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[23]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[24]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[25]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[26]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[27]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[28]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[29]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[30]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[31]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[32]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[33]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[34]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[35]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[36]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[37]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[38]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[39]) node source_ok = or(_source_ok_T_99, _source_ok_WIRE[40]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = and(_T_11, _T_24) node _T_353 = and(_T_352, _T_37) node _T_354 = and(_T_353, _T_50) node _T_355 = and(_T_354, _T_63) node _T_356 = and(_T_355, _T_71) node _T_357 = and(_T_356, _T_79) node _T_358 = and(_T_357, _T_87) node _T_359 = and(_T_358, _T_95) node _T_360 = and(_T_359, _T_103) node _T_361 = and(_T_360, _T_111) node _T_362 = and(_T_361, _T_119) node _T_363 = and(_T_362, _T_127) node _T_364 = and(_T_363, _T_135) node _T_365 = and(_T_364, _T_143) node _T_366 = and(_T_365, _T_151) node _T_367 = and(_T_366, _T_159) node _T_368 = and(_T_367, _T_167) node _T_369 = and(_T_368, _T_175) node _T_370 = and(_T_369, _T_183) node _T_371 = and(_T_370, _T_191) node _T_372 = and(_T_371, _T_199) node _T_373 = and(_T_372, _T_207) node _T_374 = and(_T_373, _T_215) node _T_375 = and(_T_374, _T_223) node _T_376 = and(_T_375, _T_231) node _T_377 = and(_T_376, _T_239) node _T_378 = and(_T_377, _T_247) node _T_379 = and(_T_378, _T_255) node _T_380 = and(_T_379, _T_263) node _T_381 = and(_T_380, _T_271) node _T_382 = and(_T_381, _T_279) node _T_383 = and(_T_382, _T_287) node _T_384 = and(_T_383, _T_295) node _T_385 = and(_T_384, _T_303) node _T_386 = and(_T_385, _T_311) node _T_387 = and(_T_386, _T_319) node _T_388 = and(_T_387, _T_327) node _T_389 = and(_T_388, _T_335) node _T_390 = and(_T_389, _T_343) node _T_391 = and(_T_390, _T_351) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_391, UInt<1>(0h1), "") : assert_1 node _T_395 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_397 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h0)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_4) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<1>(0h1)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_5) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h2)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_6) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_418 = shr(io.in.a.bits.source, 2) node _T_419 = eq(_T_418, UInt<2>(0h3)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_7) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_425 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_426 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_427 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_428 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_429 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_430 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_431 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_432 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_460 = or(_T_399, _T_405) node _T_461 = or(_T_460, _T_411) node _T_462 = or(_T_461, _T_417) node _T_463 = or(_T_462, _T_423) node _T_464 = or(_T_463, _T_424) node _T_465 = or(_T_464, _T_425) node _T_466 = or(_T_465, _T_426) node _T_467 = or(_T_466, _T_427) node _T_468 = or(_T_467, _T_428) node _T_469 = or(_T_468, _T_429) node _T_470 = or(_T_469, _T_430) node _T_471 = or(_T_470, _T_431) node _T_472 = or(_T_471, _T_432) node _T_473 = or(_T_472, _T_433) node _T_474 = or(_T_473, _T_434) node _T_475 = or(_T_474, _T_435) node _T_476 = or(_T_475, _T_436) node _T_477 = or(_T_476, _T_437) node _T_478 = or(_T_477, _T_438) node _T_479 = or(_T_478, _T_439) node _T_480 = or(_T_479, _T_440) node _T_481 = or(_T_480, _T_441) node _T_482 = or(_T_481, _T_442) node _T_483 = or(_T_482, _T_443) node _T_484 = or(_T_483, _T_444) node _T_485 = or(_T_484, _T_445) node _T_486 = or(_T_485, _T_446) node _T_487 = or(_T_486, _T_447) node _T_488 = or(_T_487, _T_448) node _T_489 = or(_T_488, _T_449) node _T_490 = or(_T_489, _T_450) node _T_491 = or(_T_490, _T_451) node _T_492 = or(_T_491, _T_452) node _T_493 = or(_T_492, _T_453) node _T_494 = or(_T_493, _T_454) node _T_495 = or(_T_494, _T_455) node _T_496 = or(_T_495, _T_456) node _T_497 = or(_T_496, _T_457) node _T_498 = or(_T_497, _T_458) node _T_499 = or(_T_498, _T_459) node _T_500 = and(_T_398, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_503 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<14>(0h2000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<13>(0h1000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_519 = cvt(_T_518) node _T_520 = and(_T_519, asSInt(UInt<18>(0h2f000))) node _T_521 = asSInt(_T_520) node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0))) node _T_523 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_524 = cvt(_T_523) node _T_525 = and(_T_524, asSInt(UInt<17>(0h10000))) node _T_526 = asSInt(_T_525) node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0))) node _T_528 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_529 = cvt(_T_528) node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000))) node _T_531 = asSInt(_T_530) node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0))) node _T_533 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<27>(0h4000000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_539 = cvt(_T_538) node _T_540 = and(_T_539, asSInt(UInt<13>(0h1000))) node _T_541 = asSInt(_T_540) node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0))) node _T_543 = or(_T_507, _T_512) node _T_544 = or(_T_543, _T_517) node _T_545 = or(_T_544, _T_522) node _T_546 = or(_T_545, _T_527) node _T_547 = or(_T_546, _T_532) node _T_548 = or(_T_547, _T_537) node _T_549 = or(_T_548, _T_542) node _T_550 = and(_T_502, _T_549) node _T_551 = or(UInt<1>(0h0), _T_550) node _T_552 = and(_T_501, _T_551) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_552, UInt<1>(0h1), "") : assert_2 node _T_556 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_8) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_563 = shr(io.in.a.bits.source, 2) node _T_564 = eq(_T_563, UInt<1>(0h1)) node _T_565 = leq(UInt<1>(0h0), uncommonBits_9) node _T_566 = and(_T_564, _T_565) node _T_567 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_568 = and(_T_566, _T_567) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<2>(0h2)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_10) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<2>(0h3)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_11) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _T_581 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_582 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_583 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_584 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_585 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_586 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_587 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_588 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_589 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_590 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_591 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_592 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_602 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_603 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_613 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_615 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_616 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[41] connect _WIRE[0], _T_556 connect _WIRE[1], _T_562 connect _WIRE[2], _T_568 connect _WIRE[3], _T_574 connect _WIRE[4], _T_580 connect _WIRE[5], _T_581 connect _WIRE[6], _T_582 connect _WIRE[7], _T_583 connect _WIRE[8], _T_584 connect _WIRE[9], _T_585 connect _WIRE[10], _T_586 connect _WIRE[11], _T_587 connect _WIRE[12], _T_588 connect _WIRE[13], _T_589 connect _WIRE[14], _T_590 connect _WIRE[15], _T_591 connect _WIRE[16], _T_592 connect _WIRE[17], _T_593 connect _WIRE[18], _T_594 connect _WIRE[19], _T_595 connect _WIRE[20], _T_596 connect _WIRE[21], _T_597 connect _WIRE[22], _T_598 connect _WIRE[23], _T_599 connect _WIRE[24], _T_600 connect _WIRE[25], _T_601 connect _WIRE[26], _T_602 connect _WIRE[27], _T_603 connect _WIRE[28], _T_604 connect _WIRE[29], _T_605 connect _WIRE[30], _T_606 connect _WIRE[31], _T_607 connect _WIRE[32], _T_608 connect _WIRE[33], _T_609 connect _WIRE[34], _T_610 connect _WIRE[35], _T_611 connect _WIRE[36], _T_612 connect _WIRE[37], _T_613 connect _WIRE[38], _T_614 connect _WIRE[39], _T_615 connect _WIRE[40], _T_616 node _T_617 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_618 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_619 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_620 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_621 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_622 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_623 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_624 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_625 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_626 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_627 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_628 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_629 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_632 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[5], _T_617, UInt<1>(0h0)) node _T_635 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[8], _T_618, UInt<1>(0h0)) node _T_638 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[11], _T_619, UInt<1>(0h0)) node _T_641 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_642 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_643 = mux(_WIRE[14], _T_620, UInt<1>(0h0)) node _T_644 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_645 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_646 = mux(_WIRE[17], _T_621, UInt<1>(0h0)) node _T_647 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_648 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_649 = mux(_WIRE[20], _T_622, UInt<1>(0h0)) node _T_650 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_651 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_652 = mux(_WIRE[23], _T_623, UInt<1>(0h0)) node _T_653 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_654 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_655 = mux(_WIRE[26], _T_624, UInt<1>(0h0)) node _T_656 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_657 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_658 = mux(_WIRE[29], _T_625, UInt<1>(0h0)) node _T_659 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_660 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_661 = mux(_WIRE[32], _T_626, UInt<1>(0h0)) node _T_662 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_663 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_664 = mux(_WIRE[35], _T_627, UInt<1>(0h0)) node _T_665 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_666 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = mux(_WIRE[38], _T_628, UInt<1>(0h0)) node _T_668 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = or(_T_629, _T_630) node _T_671 = or(_T_670, _T_631) node _T_672 = or(_T_671, _T_632) node _T_673 = or(_T_672, _T_633) node _T_674 = or(_T_673, _T_634) node _T_675 = or(_T_674, _T_635) node _T_676 = or(_T_675, _T_636) node _T_677 = or(_T_676, _T_637) node _T_678 = or(_T_677, _T_638) node _T_679 = or(_T_678, _T_639) node _T_680 = or(_T_679, _T_640) node _T_681 = or(_T_680, _T_641) node _T_682 = or(_T_681, _T_642) node _T_683 = or(_T_682, _T_643) node _T_684 = or(_T_683, _T_644) node _T_685 = or(_T_684, _T_645) node _T_686 = or(_T_685, _T_646) node _T_687 = or(_T_686, _T_647) node _T_688 = or(_T_687, _T_648) node _T_689 = or(_T_688, _T_649) node _T_690 = or(_T_689, _T_650) node _T_691 = or(_T_690, _T_651) node _T_692 = or(_T_691, _T_652) node _T_693 = or(_T_692, _T_653) node _T_694 = or(_T_693, _T_654) node _T_695 = or(_T_694, _T_655) node _T_696 = or(_T_695, _T_656) node _T_697 = or(_T_696, _T_657) node _T_698 = or(_T_697, _T_658) node _T_699 = or(_T_698, _T_659) node _T_700 = or(_T_699, _T_660) node _T_701 = or(_T_700, _T_661) node _T_702 = or(_T_701, _T_662) node _T_703 = or(_T_702, _T_663) node _T_704 = or(_T_703, _T_664) node _T_705 = or(_T_704, _T_665) node _T_706 = or(_T_705, _T_666) node _T_707 = or(_T_706, _T_667) node _T_708 = or(_T_707, _T_668) node _T_709 = or(_T_708, _T_669) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_709 node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_711 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_712 = and(_T_710, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_715 = cvt(_T_714) node _T_716 = and(_T_715, asSInt(UInt<14>(0h2000))) node _T_717 = asSInt(_T_716) node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0))) node _T_719 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<13>(0h1000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_725 = cvt(_T_724) node _T_726 = and(_T_725, asSInt(UInt<17>(0h10000))) node _T_727 = asSInt(_T_726) node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) node _T_729 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<18>(0h2f000))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_735 = cvt(_T_734) node _T_736 = and(_T_735, asSInt(UInt<17>(0h10000))) node _T_737 = asSInt(_T_736) node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0))) node _T_739 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_745 = cvt(_T_744) node _T_746 = and(_T_745, asSInt(UInt<27>(0h4000000))) node _T_747 = asSInt(_T_746) node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0))) node _T_749 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<13>(0h1000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = or(_T_718, _T_723) node _T_755 = or(_T_754, _T_728) node _T_756 = or(_T_755, _T_733) node _T_757 = or(_T_756, _T_738) node _T_758 = or(_T_757, _T_743) node _T_759 = or(_T_758, _T_748) node _T_760 = or(_T_759, _T_753) node _T_761 = and(_T_713, _T_760) node _T_762 = or(UInt<1>(0h0), _T_761) node _T_763 = and(_WIRE_1, _T_762) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_763, UInt<1>(0h1), "") : assert_3 node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(source_ok, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_770 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_770, UInt<1>(0h1), "") : assert_5 node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(is_aligned, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_777 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_777, UInt<1>(0h1), "") : assert_7 node _T_781 = not(io.in.a.bits.mask) node _T_782 = eq(_T_781, UInt<1>(0h0)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_782, UInt<1>(0h1), "") : assert_8 node _T_786 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_786, UInt<1>(0h1), "") : assert_9 node _T_790 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_790 : node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_795 = shr(io.in.a.bits.source, 2) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = leq(UInt<1>(0h0), uncommonBits_12) node _T_798 = and(_T_796, _T_797) node _T_799 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_800 = and(_T_798, _T_799) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_801 = shr(io.in.a.bits.source, 2) node _T_802 = eq(_T_801, UInt<1>(0h1)) node _T_803 = leq(UInt<1>(0h0), uncommonBits_13) node _T_804 = and(_T_802, _T_803) node _T_805 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_806 = and(_T_804, _T_805) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_807 = shr(io.in.a.bits.source, 2) node _T_808 = eq(_T_807, UInt<2>(0h2)) node _T_809 = leq(UInt<1>(0h0), uncommonBits_14) node _T_810 = and(_T_808, _T_809) node _T_811 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_812 = and(_T_810, _T_811) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_813 = shr(io.in.a.bits.source, 2) node _T_814 = eq(_T_813, UInt<2>(0h3)) node _T_815 = leq(UInt<1>(0h0), uncommonBits_15) node _T_816 = and(_T_814, _T_815) node _T_817 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_821 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_822 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_823 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_824 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_825 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_826 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_827 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_828 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_829 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_830 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_831 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_855 = or(_T_794, _T_800) node _T_856 = or(_T_855, _T_806) node _T_857 = or(_T_856, _T_812) node _T_858 = or(_T_857, _T_818) node _T_859 = or(_T_858, _T_819) node _T_860 = or(_T_859, _T_820) node _T_861 = or(_T_860, _T_821) node _T_862 = or(_T_861, _T_822) node _T_863 = or(_T_862, _T_823) node _T_864 = or(_T_863, _T_824) node _T_865 = or(_T_864, _T_825) node _T_866 = or(_T_865, _T_826) node _T_867 = or(_T_866, _T_827) node _T_868 = or(_T_867, _T_828) node _T_869 = or(_T_868, _T_829) node _T_870 = or(_T_869, _T_830) node _T_871 = or(_T_870, _T_831) node _T_872 = or(_T_871, _T_832) node _T_873 = or(_T_872, _T_833) node _T_874 = or(_T_873, _T_834) node _T_875 = or(_T_874, _T_835) node _T_876 = or(_T_875, _T_836) node _T_877 = or(_T_876, _T_837) node _T_878 = or(_T_877, _T_838) node _T_879 = or(_T_878, _T_839) node _T_880 = or(_T_879, _T_840) node _T_881 = or(_T_880, _T_841) node _T_882 = or(_T_881, _T_842) node _T_883 = or(_T_882, _T_843) node _T_884 = or(_T_883, _T_844) node _T_885 = or(_T_884, _T_845) node _T_886 = or(_T_885, _T_846) node _T_887 = or(_T_886, _T_847) node _T_888 = or(_T_887, _T_848) node _T_889 = or(_T_888, _T_849) node _T_890 = or(_T_889, _T_850) node _T_891 = or(_T_890, _T_851) node _T_892 = or(_T_891, _T_852) node _T_893 = or(_T_892, _T_853) node _T_894 = or(_T_893, _T_854) node _T_895 = and(_T_793, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_898 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_899 = cvt(_T_898) node _T_900 = and(_T_899, asSInt(UInt<14>(0h2000))) node _T_901 = asSInt(_T_900) node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0))) node _T_903 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_904 = cvt(_T_903) node _T_905 = and(_T_904, asSInt(UInt<13>(0h1000))) node _T_906 = asSInt(_T_905) node _T_907 = eq(_T_906, asSInt(UInt<1>(0h0))) node _T_908 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_909 = cvt(_T_908) node _T_910 = and(_T_909, asSInt(UInt<17>(0h10000))) node _T_911 = asSInt(_T_910) node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0))) node _T_913 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<18>(0h2f000))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<17>(0h10000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<13>(0h1000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<27>(0h4000000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<13>(0h1000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = or(_T_902, _T_907) node _T_939 = or(_T_938, _T_912) node _T_940 = or(_T_939, _T_917) node _T_941 = or(_T_940, _T_922) node _T_942 = or(_T_941, _T_927) node _T_943 = or(_T_942, _T_932) node _T_944 = or(_T_943, _T_937) node _T_945 = and(_T_897, _T_944) node _T_946 = or(UInt<1>(0h0), _T_945) node _T_947 = and(_T_896, _T_946) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_947, UInt<1>(0h1), "") : assert_10 node _T_951 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<1>(0h0)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_16) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<1>(0h1)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_17) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_964 = shr(io.in.a.bits.source, 2) node _T_965 = eq(_T_964, UInt<2>(0h2)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_18) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_969 = and(_T_967, _T_968) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_970 = shr(io.in.a.bits.source, 2) node _T_971 = eq(_T_970, UInt<2>(0h3)) node _T_972 = leq(UInt<1>(0h0), uncommonBits_19) node _T_973 = and(_T_971, _T_972) node _T_974 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_975 = and(_T_973, _T_974) node _T_976 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_978 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_979 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_980 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_981 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_982 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_983 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_984 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_985 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_986 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_987 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_990 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_991 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_992 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_993 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_994 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_995 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_996 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_997 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_998 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_999 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1000 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1001 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[41] connect _WIRE_2[0], _T_951 connect _WIRE_2[1], _T_957 connect _WIRE_2[2], _T_963 connect _WIRE_2[3], _T_969 connect _WIRE_2[4], _T_975 connect _WIRE_2[5], _T_976 connect _WIRE_2[6], _T_977 connect _WIRE_2[7], _T_978 connect _WIRE_2[8], _T_979 connect _WIRE_2[9], _T_980 connect _WIRE_2[10], _T_981 connect _WIRE_2[11], _T_982 connect _WIRE_2[12], _T_983 connect _WIRE_2[13], _T_984 connect _WIRE_2[14], _T_985 connect _WIRE_2[15], _T_986 connect _WIRE_2[16], _T_987 connect _WIRE_2[17], _T_988 connect _WIRE_2[18], _T_989 connect _WIRE_2[19], _T_990 connect _WIRE_2[20], _T_991 connect _WIRE_2[21], _T_992 connect _WIRE_2[22], _T_993 connect _WIRE_2[23], _T_994 connect _WIRE_2[24], _T_995 connect _WIRE_2[25], _T_996 connect _WIRE_2[26], _T_997 connect _WIRE_2[27], _T_998 connect _WIRE_2[28], _T_999 connect _WIRE_2[29], _T_1000 connect _WIRE_2[30], _T_1001 connect _WIRE_2[31], _T_1002 connect _WIRE_2[32], _T_1003 connect _WIRE_2[33], _T_1004 connect _WIRE_2[34], _T_1005 connect _WIRE_2[35], _T_1006 connect _WIRE_2[36], _T_1007 connect _WIRE_2[37], _T_1008 connect _WIRE_2[38], _T_1009 connect _WIRE_2[39], _T_1010 connect _WIRE_2[40], _T_1011 node _T_1012 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1013 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1014 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1015 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1016 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1017 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1018 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1019 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1020 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1021 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1022 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1023 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1024 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1025 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1026 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1027 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1028 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1029 = mux(_WIRE_2[5], _T_1012, UInt<1>(0h0)) node _T_1030 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1031 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1032 = mux(_WIRE_2[8], _T_1013, UInt<1>(0h0)) node _T_1033 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_1034 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1035 = mux(_WIRE_2[11], _T_1014, UInt<1>(0h0)) node _T_1036 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1037 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_1038 = mux(_WIRE_2[14], _T_1015, UInt<1>(0h0)) node _T_1039 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_1040 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1041 = mux(_WIRE_2[17], _T_1016, UInt<1>(0h0)) node _T_1042 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1043 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_1044 = mux(_WIRE_2[20], _T_1017, UInt<1>(0h0)) node _T_1045 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_1046 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_1047 = mux(_WIRE_2[23], _T_1018, UInt<1>(0h0)) node _T_1048 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_1049 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_1050 = mux(_WIRE_2[26], _T_1019, UInt<1>(0h0)) node _T_1051 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_1052 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_1053 = mux(_WIRE_2[29], _T_1020, UInt<1>(0h0)) node _T_1054 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_1055 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_1056 = mux(_WIRE_2[32], _T_1021, UInt<1>(0h0)) node _T_1057 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_1058 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_1059 = mux(_WIRE_2[35], _T_1022, UInt<1>(0h0)) node _T_1060 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_1061 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_1062 = mux(_WIRE_2[38], _T_1023, UInt<1>(0h0)) node _T_1063 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_1064 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_1065 = or(_T_1024, _T_1025) node _T_1066 = or(_T_1065, _T_1026) node _T_1067 = or(_T_1066, _T_1027) node _T_1068 = or(_T_1067, _T_1028) node _T_1069 = or(_T_1068, _T_1029) node _T_1070 = or(_T_1069, _T_1030) node _T_1071 = or(_T_1070, _T_1031) node _T_1072 = or(_T_1071, _T_1032) node _T_1073 = or(_T_1072, _T_1033) node _T_1074 = or(_T_1073, _T_1034) node _T_1075 = or(_T_1074, _T_1035) node _T_1076 = or(_T_1075, _T_1036) node _T_1077 = or(_T_1076, _T_1037) node _T_1078 = or(_T_1077, _T_1038) node _T_1079 = or(_T_1078, _T_1039) node _T_1080 = or(_T_1079, _T_1040) node _T_1081 = or(_T_1080, _T_1041) node _T_1082 = or(_T_1081, _T_1042) node _T_1083 = or(_T_1082, _T_1043) node _T_1084 = or(_T_1083, _T_1044) node _T_1085 = or(_T_1084, _T_1045) node _T_1086 = or(_T_1085, _T_1046) node _T_1087 = or(_T_1086, _T_1047) node _T_1088 = or(_T_1087, _T_1048) node _T_1089 = or(_T_1088, _T_1049) node _T_1090 = or(_T_1089, _T_1050) node _T_1091 = or(_T_1090, _T_1051) node _T_1092 = or(_T_1091, _T_1052) node _T_1093 = or(_T_1092, _T_1053) node _T_1094 = or(_T_1093, _T_1054) node _T_1095 = or(_T_1094, _T_1055) node _T_1096 = or(_T_1095, _T_1056) node _T_1097 = or(_T_1096, _T_1057) node _T_1098 = or(_T_1097, _T_1058) node _T_1099 = or(_T_1098, _T_1059) node _T_1100 = or(_T_1099, _T_1060) node _T_1101 = or(_T_1100, _T_1061) node _T_1102 = or(_T_1101, _T_1062) node _T_1103 = or(_T_1102, _T_1063) node _T_1104 = or(_T_1103, _T_1064) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1104 node _T_1105 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1106 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = or(UInt<1>(0h0), _T_1107) node _T_1109 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1110 = cvt(_T_1109) node _T_1111 = and(_T_1110, asSInt(UInt<14>(0h2000))) node _T_1112 = asSInt(_T_1111) node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0))) node _T_1114 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<13>(0h1000))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<17>(0h10000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<18>(0h2f000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1130 = cvt(_T_1129) node _T_1131 = and(_T_1130, asSInt(UInt<17>(0h10000))) node _T_1132 = asSInt(_T_1131) node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0))) node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<13>(0h1000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<27>(0h4000000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<13>(0h1000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1113, _T_1118) node _T_1150 = or(_T_1149, _T_1123) node _T_1151 = or(_T_1150, _T_1128) node _T_1152 = or(_T_1151, _T_1133) node _T_1153 = or(_T_1152, _T_1138) node _T_1154 = or(_T_1153, _T_1143) node _T_1155 = or(_T_1154, _T_1148) node _T_1156 = and(_T_1108, _T_1155) node _T_1157 = or(UInt<1>(0h0), _T_1156) node _T_1158 = and(_WIRE_3, _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_11 node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(source_ok, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1165 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_13 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1172 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_15 node _T_1176 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_16 node _T_1180 = not(io.in.a.bits.mask) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_17 node _T_1185 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_18 node _T_1189 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1189 : node _T_1190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<1>(0h1)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1206 = shr(io.in.a.bits.source, 2) node _T_1207 = eq(_T_1206, UInt<2>(0h2)) node _T_1208 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1211 = and(_T_1209, _T_1210) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1212 = shr(io.in.a.bits.source, 2) node _T_1213 = eq(_T_1212, UInt<2>(0h3)) node _T_1214 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1217 = and(_T_1215, _T_1216) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1225 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1226 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1227 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1228 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1229 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1249 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1250 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1251 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1252 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1253 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1254 = or(_T_1193, _T_1199) node _T_1255 = or(_T_1254, _T_1205) node _T_1256 = or(_T_1255, _T_1211) node _T_1257 = or(_T_1256, _T_1217) node _T_1258 = or(_T_1257, _T_1218) node _T_1259 = or(_T_1258, _T_1219) node _T_1260 = or(_T_1259, _T_1220) node _T_1261 = or(_T_1260, _T_1221) node _T_1262 = or(_T_1261, _T_1222) node _T_1263 = or(_T_1262, _T_1223) node _T_1264 = or(_T_1263, _T_1224) node _T_1265 = or(_T_1264, _T_1225) node _T_1266 = or(_T_1265, _T_1226) node _T_1267 = or(_T_1266, _T_1227) node _T_1268 = or(_T_1267, _T_1228) node _T_1269 = or(_T_1268, _T_1229) node _T_1270 = or(_T_1269, _T_1230) node _T_1271 = or(_T_1270, _T_1231) node _T_1272 = or(_T_1271, _T_1232) node _T_1273 = or(_T_1272, _T_1233) node _T_1274 = or(_T_1273, _T_1234) node _T_1275 = or(_T_1274, _T_1235) node _T_1276 = or(_T_1275, _T_1236) node _T_1277 = or(_T_1276, _T_1237) node _T_1278 = or(_T_1277, _T_1238) node _T_1279 = or(_T_1278, _T_1239) node _T_1280 = or(_T_1279, _T_1240) node _T_1281 = or(_T_1280, _T_1241) node _T_1282 = or(_T_1281, _T_1242) node _T_1283 = or(_T_1282, _T_1243) node _T_1284 = or(_T_1283, _T_1244) node _T_1285 = or(_T_1284, _T_1245) node _T_1286 = or(_T_1285, _T_1246) node _T_1287 = or(_T_1286, _T_1247) node _T_1288 = or(_T_1287, _T_1248) node _T_1289 = or(_T_1288, _T_1249) node _T_1290 = or(_T_1289, _T_1250) node _T_1291 = or(_T_1290, _T_1251) node _T_1292 = or(_T_1291, _T_1252) node _T_1293 = or(_T_1292, _T_1253) node _T_1294 = and(_T_1192, _T_1293) node _T_1295 = or(UInt<1>(0h0), _T_1294) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_19 node _T_1299 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1300 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1301 = and(_T_1299, _T_1300) node _T_1302 = or(UInt<1>(0h0), _T_1301) node _T_1303 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1304 = cvt(_T_1303) node _T_1305 = and(_T_1304, asSInt(UInt<13>(0h1000))) node _T_1306 = asSInt(_T_1305) node _T_1307 = eq(_T_1306, asSInt(UInt<1>(0h0))) node _T_1308 = and(_T_1302, _T_1307) node _T_1309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1310 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = or(UInt<1>(0h0), _T_1311) node _T_1313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1314 = cvt(_T_1313) node _T_1315 = and(_T_1314, asSInt(UInt<14>(0h2000))) node _T_1316 = asSInt(_T_1315) node _T_1317 = eq(_T_1316, asSInt(UInt<1>(0h0))) node _T_1318 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<17>(0h10000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<18>(0h2f000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<17>(0h10000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<13>(0h1000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<27>(0h4000000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<13>(0h1000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = or(_T_1317, _T_1322) node _T_1349 = or(_T_1348, _T_1327) node _T_1350 = or(_T_1349, _T_1332) node _T_1351 = or(_T_1350, _T_1337) node _T_1352 = or(_T_1351, _T_1342) node _T_1353 = or(_T_1352, _T_1347) node _T_1354 = and(_T_1312, _T_1353) node _T_1355 = or(UInt<1>(0h0), _T_1308) node _T_1356 = or(_T_1355, _T_1354) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_20 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(source_ok, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(is_aligned, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1366 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1367 = asUInt(reset) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) when _T_1368 : node _T_1369 = eq(_T_1366, UInt<1>(0h0)) when _T_1369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1366, UInt<1>(0h1), "") : assert_23 node _T_1370 = eq(io.in.a.bits.mask, mask) node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(_T_1370, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1370, UInt<1>(0h1), "") : assert_24 node _T_1374 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_25 node _T_1378 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1378 : node _T_1379 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1380 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1381 = and(_T_1379, _T_1380) node _T_1382 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1383 = shr(io.in.a.bits.source, 2) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) node _T_1385 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1388 = and(_T_1386, _T_1387) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1389 = shr(io.in.a.bits.source, 2) node _T_1390 = eq(_T_1389, UInt<1>(0h1)) node _T_1391 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1392 = and(_T_1390, _T_1391) node _T_1393 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1394 = and(_T_1392, _T_1393) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1395 = shr(io.in.a.bits.source, 2) node _T_1396 = eq(_T_1395, UInt<2>(0h2)) node _T_1397 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1398 = and(_T_1396, _T_1397) node _T_1399 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1400 = and(_T_1398, _T_1399) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1401 = shr(io.in.a.bits.source, 2) node _T_1402 = eq(_T_1401, UInt<2>(0h3)) node _T_1403 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1404 = and(_T_1402, _T_1403) node _T_1405 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1406 = and(_T_1404, _T_1405) node _T_1407 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1408 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1409 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1410 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1411 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1412 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1413 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1414 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1415 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1416 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1417 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1418 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1429 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1430 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1431 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1434 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1435 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1436 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1437 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1438 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1439 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1440 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1441 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1442 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1443 = or(_T_1382, _T_1388) node _T_1444 = or(_T_1443, _T_1394) node _T_1445 = or(_T_1444, _T_1400) node _T_1446 = or(_T_1445, _T_1406) node _T_1447 = or(_T_1446, _T_1407) node _T_1448 = or(_T_1447, _T_1408) node _T_1449 = or(_T_1448, _T_1409) node _T_1450 = or(_T_1449, _T_1410) node _T_1451 = or(_T_1450, _T_1411) node _T_1452 = or(_T_1451, _T_1412) node _T_1453 = or(_T_1452, _T_1413) node _T_1454 = or(_T_1453, _T_1414) node _T_1455 = or(_T_1454, _T_1415) node _T_1456 = or(_T_1455, _T_1416) node _T_1457 = or(_T_1456, _T_1417) node _T_1458 = or(_T_1457, _T_1418) node _T_1459 = or(_T_1458, _T_1419) node _T_1460 = or(_T_1459, _T_1420) node _T_1461 = or(_T_1460, _T_1421) node _T_1462 = or(_T_1461, _T_1422) node _T_1463 = or(_T_1462, _T_1423) node _T_1464 = or(_T_1463, _T_1424) node _T_1465 = or(_T_1464, _T_1425) node _T_1466 = or(_T_1465, _T_1426) node _T_1467 = or(_T_1466, _T_1427) node _T_1468 = or(_T_1467, _T_1428) node _T_1469 = or(_T_1468, _T_1429) node _T_1470 = or(_T_1469, _T_1430) node _T_1471 = or(_T_1470, _T_1431) node _T_1472 = or(_T_1471, _T_1432) node _T_1473 = or(_T_1472, _T_1433) node _T_1474 = or(_T_1473, _T_1434) node _T_1475 = or(_T_1474, _T_1435) node _T_1476 = or(_T_1475, _T_1436) node _T_1477 = or(_T_1476, _T_1437) node _T_1478 = or(_T_1477, _T_1438) node _T_1479 = or(_T_1478, _T_1439) node _T_1480 = or(_T_1479, _T_1440) node _T_1481 = or(_T_1480, _T_1441) node _T_1482 = or(_T_1481, _T_1442) node _T_1483 = and(_T_1381, _T_1482) node _T_1484 = or(UInt<1>(0h0), _T_1483) node _T_1485 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1486 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = or(UInt<1>(0h0), _T_1487) node _T_1489 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<13>(0h1000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = and(_T_1488, _T_1493) node _T_1495 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1496 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1497 = and(_T_1495, _T_1496) node _T_1498 = or(UInt<1>(0h0), _T_1497) node _T_1499 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<14>(0h2000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1505 = cvt(_T_1504) node _T_1506 = and(_T_1505, asSInt(UInt<18>(0h2f000))) node _T_1507 = asSInt(_T_1506) node _T_1508 = eq(_T_1507, asSInt(UInt<1>(0h0))) node _T_1509 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1510 = cvt(_T_1509) node _T_1511 = and(_T_1510, asSInt(UInt<17>(0h10000))) node _T_1512 = asSInt(_T_1511) node _T_1513 = eq(_T_1512, asSInt(UInt<1>(0h0))) node _T_1514 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1515 = cvt(_T_1514) node _T_1516 = and(_T_1515, asSInt(UInt<13>(0h1000))) node _T_1517 = asSInt(_T_1516) node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0))) node _T_1519 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1520 = cvt(_T_1519) node _T_1521 = and(_T_1520, asSInt(UInt<27>(0h4000000))) node _T_1522 = asSInt(_T_1521) node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1525 = cvt(_T_1524) node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000))) node _T_1527 = asSInt(_T_1526) node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) node _T_1529 = or(_T_1503, _T_1508) node _T_1530 = or(_T_1529, _T_1513) node _T_1531 = or(_T_1530, _T_1518) node _T_1532 = or(_T_1531, _T_1523) node _T_1533 = or(_T_1532, _T_1528) node _T_1534 = and(_T_1498, _T_1533) node _T_1535 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1536 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1537 = cvt(_T_1536) node _T_1538 = and(_T_1537, asSInt(UInt<17>(0h10000))) node _T_1539 = asSInt(_T_1538) node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = and(_T_1535, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1494) node _T_1543 = or(_T_1542, _T_1534) node _T_1544 = or(_T_1543, _T_1541) node _T_1545 = and(_T_1484, _T_1544) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_26 node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(source_ok, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(is_aligned, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1555 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_29 node _T_1559 = eq(io.in.a.bits.mask, mask) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_30 node _T_1563 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1563 : node _T_1564 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1565 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1566 = and(_T_1564, _T_1565) node _T_1567 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1568 = shr(io.in.a.bits.source, 2) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) node _T_1570 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1571 = and(_T_1569, _T_1570) node _T_1572 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1573 = and(_T_1571, _T_1572) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1574 = shr(io.in.a.bits.source, 2) node _T_1575 = eq(_T_1574, UInt<1>(0h1)) node _T_1576 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1577 = and(_T_1575, _T_1576) node _T_1578 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1579 = and(_T_1577, _T_1578) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1580 = shr(io.in.a.bits.source, 2) node _T_1581 = eq(_T_1580, UInt<2>(0h2)) node _T_1582 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1583 = and(_T_1581, _T_1582) node _T_1584 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1585 = and(_T_1583, _T_1584) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1586 = shr(io.in.a.bits.source, 2) node _T_1587 = eq(_T_1586, UInt<2>(0h3)) node _T_1588 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1589 = and(_T_1587, _T_1588) node _T_1590 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1593 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1594 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1595 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1596 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1597 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1598 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1599 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1600 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1602 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1603 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1604 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1605 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1606 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1607 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1608 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1609 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1610 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1611 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1612 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1613 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1614 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1615 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1616 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1617 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1618 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1619 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1620 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1621 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1622 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1623 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1624 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1625 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1626 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1627 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1628 = or(_T_1567, _T_1573) node _T_1629 = or(_T_1628, _T_1579) node _T_1630 = or(_T_1629, _T_1585) node _T_1631 = or(_T_1630, _T_1591) node _T_1632 = or(_T_1631, _T_1592) node _T_1633 = or(_T_1632, _T_1593) node _T_1634 = or(_T_1633, _T_1594) node _T_1635 = or(_T_1634, _T_1595) node _T_1636 = or(_T_1635, _T_1596) node _T_1637 = or(_T_1636, _T_1597) node _T_1638 = or(_T_1637, _T_1598) node _T_1639 = or(_T_1638, _T_1599) node _T_1640 = or(_T_1639, _T_1600) node _T_1641 = or(_T_1640, _T_1601) node _T_1642 = or(_T_1641, _T_1602) node _T_1643 = or(_T_1642, _T_1603) node _T_1644 = or(_T_1643, _T_1604) node _T_1645 = or(_T_1644, _T_1605) node _T_1646 = or(_T_1645, _T_1606) node _T_1647 = or(_T_1646, _T_1607) node _T_1648 = or(_T_1647, _T_1608) node _T_1649 = or(_T_1648, _T_1609) node _T_1650 = or(_T_1649, _T_1610) node _T_1651 = or(_T_1650, _T_1611) node _T_1652 = or(_T_1651, _T_1612) node _T_1653 = or(_T_1652, _T_1613) node _T_1654 = or(_T_1653, _T_1614) node _T_1655 = or(_T_1654, _T_1615) node _T_1656 = or(_T_1655, _T_1616) node _T_1657 = or(_T_1656, _T_1617) node _T_1658 = or(_T_1657, _T_1618) node _T_1659 = or(_T_1658, _T_1619) node _T_1660 = or(_T_1659, _T_1620) node _T_1661 = or(_T_1660, _T_1621) node _T_1662 = or(_T_1661, _T_1622) node _T_1663 = or(_T_1662, _T_1623) node _T_1664 = or(_T_1663, _T_1624) node _T_1665 = or(_T_1664, _T_1625) node _T_1666 = or(_T_1665, _T_1626) node _T_1667 = or(_T_1666, _T_1627) node _T_1668 = and(_T_1566, _T_1667) node _T_1669 = or(UInt<1>(0h0), _T_1668) node _T_1670 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1671 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1675 = cvt(_T_1674) node _T_1676 = and(_T_1675, asSInt(UInt<13>(0h1000))) node _T_1677 = asSInt(_T_1676) node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0))) node _T_1679 = and(_T_1673, _T_1678) node _T_1680 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1681 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = or(UInt<1>(0h0), _T_1682) node _T_1684 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1685 = cvt(_T_1684) node _T_1686 = and(_T_1685, asSInt(UInt<14>(0h2000))) node _T_1687 = asSInt(_T_1686) node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1690 = cvt(_T_1689) node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000))) node _T_1692 = asSInt(_T_1691) node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1695 = cvt(_T_1694) node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000))) node _T_1697 = asSInt(_T_1696) node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0))) node _T_1699 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1705 = cvt(_T_1704) node _T_1706 = and(_T_1705, asSInt(UInt<27>(0h4000000))) node _T_1707 = asSInt(_T_1706) node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1710 = cvt(_T_1709) node _T_1711 = and(_T_1710, asSInt(UInt<13>(0h1000))) node _T_1712 = asSInt(_T_1711) node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0))) node _T_1714 = or(_T_1688, _T_1693) node _T_1715 = or(_T_1714, _T_1698) node _T_1716 = or(_T_1715, _T_1703) node _T_1717 = or(_T_1716, _T_1708) node _T_1718 = or(_T_1717, _T_1713) node _T_1719 = and(_T_1683, _T_1718) node _T_1720 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1721 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1722 = cvt(_T_1721) node _T_1723 = and(_T_1722, asSInt(UInt<17>(0h10000))) node _T_1724 = asSInt(_T_1723) node _T_1725 = eq(_T_1724, asSInt(UInt<1>(0h0))) node _T_1726 = and(_T_1720, _T_1725) node _T_1727 = or(UInt<1>(0h0), _T_1679) node _T_1728 = or(_T_1727, _T_1719) node _T_1729 = or(_T_1728, _T_1726) node _T_1730 = and(_T_1669, _T_1729) node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(_T_1730, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1730, UInt<1>(0h1), "") : assert_31 node _T_1734 = asUInt(reset) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) when _T_1735 : node _T_1736 = eq(source_ok, UInt<1>(0h0)) when _T_1736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(is_aligned, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1740 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1741 = asUInt(reset) node _T_1742 = eq(_T_1741, UInt<1>(0h0)) when _T_1742 : node _T_1743 = eq(_T_1740, UInt<1>(0h0)) when _T_1743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1740, UInt<1>(0h1), "") : assert_34 node _T_1744 = not(mask) node _T_1745 = and(io.in.a.bits.mask, _T_1744) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) node _T_1747 = asUInt(reset) node _T_1748 = eq(_T_1747, UInt<1>(0h0)) when _T_1748 : node _T_1749 = eq(_T_1746, UInt<1>(0h0)) when _T_1749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1746, UInt<1>(0h1), "") : assert_35 node _T_1750 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1750 : node _T_1751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1752 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1753 = and(_T_1751, _T_1752) node _T_1754 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1761 = shr(io.in.a.bits.source, 2) node _T_1762 = eq(_T_1761, UInt<1>(0h1)) node _T_1763 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1764 = and(_T_1762, _T_1763) node _T_1765 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1766 = and(_T_1764, _T_1765) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1767 = shr(io.in.a.bits.source, 2) node _T_1768 = eq(_T_1767, UInt<2>(0h2)) node _T_1769 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1770 = and(_T_1768, _T_1769) node _T_1771 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1772 = and(_T_1770, _T_1771) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1773 = shr(io.in.a.bits.source, 2) node _T_1774 = eq(_T_1773, UInt<2>(0h3)) node _T_1775 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1776 = and(_T_1774, _T_1775) node _T_1777 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1778 = and(_T_1776, _T_1777) node _T_1779 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1780 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1781 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1782 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1783 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1784 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1785 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1786 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1787 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1788 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1789 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1790 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1797 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1798 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1799 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1800 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1801 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1802 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1803 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1804 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1805 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1806 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1807 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1808 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1809 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1810 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1811 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1812 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1813 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1814 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1815 = or(_T_1754, _T_1760) node _T_1816 = or(_T_1815, _T_1766) node _T_1817 = or(_T_1816, _T_1772) node _T_1818 = or(_T_1817, _T_1778) node _T_1819 = or(_T_1818, _T_1779) node _T_1820 = or(_T_1819, _T_1780) node _T_1821 = or(_T_1820, _T_1781) node _T_1822 = or(_T_1821, _T_1782) node _T_1823 = or(_T_1822, _T_1783) node _T_1824 = or(_T_1823, _T_1784) node _T_1825 = or(_T_1824, _T_1785) node _T_1826 = or(_T_1825, _T_1786) node _T_1827 = or(_T_1826, _T_1787) node _T_1828 = or(_T_1827, _T_1788) node _T_1829 = or(_T_1828, _T_1789) node _T_1830 = or(_T_1829, _T_1790) node _T_1831 = or(_T_1830, _T_1791) node _T_1832 = or(_T_1831, _T_1792) node _T_1833 = or(_T_1832, _T_1793) node _T_1834 = or(_T_1833, _T_1794) node _T_1835 = or(_T_1834, _T_1795) node _T_1836 = or(_T_1835, _T_1796) node _T_1837 = or(_T_1836, _T_1797) node _T_1838 = or(_T_1837, _T_1798) node _T_1839 = or(_T_1838, _T_1799) node _T_1840 = or(_T_1839, _T_1800) node _T_1841 = or(_T_1840, _T_1801) node _T_1842 = or(_T_1841, _T_1802) node _T_1843 = or(_T_1842, _T_1803) node _T_1844 = or(_T_1843, _T_1804) node _T_1845 = or(_T_1844, _T_1805) node _T_1846 = or(_T_1845, _T_1806) node _T_1847 = or(_T_1846, _T_1807) node _T_1848 = or(_T_1847, _T_1808) node _T_1849 = or(_T_1848, _T_1809) node _T_1850 = or(_T_1849, _T_1810) node _T_1851 = or(_T_1850, _T_1811) node _T_1852 = or(_T_1851, _T_1812) node _T_1853 = or(_T_1852, _T_1813) node _T_1854 = or(_T_1853, _T_1814) node _T_1855 = and(_T_1753, _T_1854) node _T_1856 = or(UInt<1>(0h0), _T_1855) node _T_1857 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1858 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = or(UInt<1>(0h0), _T_1859) node _T_1861 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1862 = cvt(_T_1861) node _T_1863 = and(_T_1862, asSInt(UInt<14>(0h2000))) node _T_1864 = asSInt(_T_1863) node _T_1865 = eq(_T_1864, asSInt(UInt<1>(0h0))) node _T_1866 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1867 = cvt(_T_1866) node _T_1868 = and(_T_1867, asSInt(UInt<13>(0h1000))) node _T_1869 = asSInt(_T_1868) node _T_1870 = eq(_T_1869, asSInt(UInt<1>(0h0))) node _T_1871 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1872 = cvt(_T_1871) node _T_1873 = and(_T_1872, asSInt(UInt<18>(0h2f000))) node _T_1874 = asSInt(_T_1873) node _T_1875 = eq(_T_1874, asSInt(UInt<1>(0h0))) node _T_1876 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1877 = cvt(_T_1876) node _T_1878 = and(_T_1877, asSInt(UInt<17>(0h10000))) node _T_1879 = asSInt(_T_1878) node _T_1880 = eq(_T_1879, asSInt(UInt<1>(0h0))) node _T_1881 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1882 = cvt(_T_1881) node _T_1883 = and(_T_1882, asSInt(UInt<13>(0h1000))) node _T_1884 = asSInt(_T_1883) node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1887 = cvt(_T_1886) node _T_1888 = and(_T_1887, asSInt(UInt<27>(0h4000000))) node _T_1889 = asSInt(_T_1888) node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0))) node _T_1891 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<13>(0h1000))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = or(_T_1865, _T_1870) node _T_1897 = or(_T_1896, _T_1875) node _T_1898 = or(_T_1897, _T_1880) node _T_1899 = or(_T_1898, _T_1885) node _T_1900 = or(_T_1899, _T_1890) node _T_1901 = or(_T_1900, _T_1895) node _T_1902 = and(_T_1860, _T_1901) node _T_1903 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = and(_T_1903, _T_1908) node _T_1910 = or(UInt<1>(0h0), _T_1902) node _T_1911 = or(_T_1910, _T_1909) node _T_1912 = and(_T_1856, _T_1911) node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(_T_1912, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1912, UInt<1>(0h1), "") : assert_36 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(source_ok, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(is_aligned, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1922 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(_T_1922, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1922, UInt<1>(0h1), "") : assert_39 node _T_1926 = eq(io.in.a.bits.mask, mask) node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(_T_1926, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1926, UInt<1>(0h1), "") : assert_40 node _T_1930 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1930 : node _T_1931 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1932 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1933 = and(_T_1931, _T_1932) node _T_1934 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1935 = shr(io.in.a.bits.source, 2) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) node _T_1937 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1938 = and(_T_1936, _T_1937) node _T_1939 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1940 = and(_T_1938, _T_1939) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1941 = shr(io.in.a.bits.source, 2) node _T_1942 = eq(_T_1941, UInt<1>(0h1)) node _T_1943 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1944 = and(_T_1942, _T_1943) node _T_1945 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1946 = and(_T_1944, _T_1945) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1947 = shr(io.in.a.bits.source, 2) node _T_1948 = eq(_T_1947, UInt<2>(0h2)) node _T_1949 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1950 = and(_T_1948, _T_1949) node _T_1951 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1952 = and(_T_1950, _T_1951) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1953 = shr(io.in.a.bits.source, 2) node _T_1954 = eq(_T_1953, UInt<2>(0h3)) node _T_1955 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1956 = and(_T_1954, _T_1955) node _T_1957 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1958 = and(_T_1956, _T_1957) node _T_1959 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1960 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1961 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1962 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1963 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1964 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1965 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1966 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1967 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1968 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1969 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1970 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1971 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1972 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1973 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1974 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1975 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1976 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1977 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1978 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1979 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1980 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1981 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1982 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1983 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1984 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1985 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1986 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1987 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1988 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1989 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1990 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1991 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1992 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1993 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1994 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1995 = or(_T_1934, _T_1940) node _T_1996 = or(_T_1995, _T_1946) node _T_1997 = or(_T_1996, _T_1952) node _T_1998 = or(_T_1997, _T_1958) node _T_1999 = or(_T_1998, _T_1959) node _T_2000 = or(_T_1999, _T_1960) node _T_2001 = or(_T_2000, _T_1961) node _T_2002 = or(_T_2001, _T_1962) node _T_2003 = or(_T_2002, _T_1963) node _T_2004 = or(_T_2003, _T_1964) node _T_2005 = or(_T_2004, _T_1965) node _T_2006 = or(_T_2005, _T_1966) node _T_2007 = or(_T_2006, _T_1967) node _T_2008 = or(_T_2007, _T_1968) node _T_2009 = or(_T_2008, _T_1969) node _T_2010 = or(_T_2009, _T_1970) node _T_2011 = or(_T_2010, _T_1971) node _T_2012 = or(_T_2011, _T_1972) node _T_2013 = or(_T_2012, _T_1973) node _T_2014 = or(_T_2013, _T_1974) node _T_2015 = or(_T_2014, _T_1975) node _T_2016 = or(_T_2015, _T_1976) node _T_2017 = or(_T_2016, _T_1977) node _T_2018 = or(_T_2017, _T_1978) node _T_2019 = or(_T_2018, _T_1979) node _T_2020 = or(_T_2019, _T_1980) node _T_2021 = or(_T_2020, _T_1981) node _T_2022 = or(_T_2021, _T_1982) node _T_2023 = or(_T_2022, _T_1983) node _T_2024 = or(_T_2023, _T_1984) node _T_2025 = or(_T_2024, _T_1985) node _T_2026 = or(_T_2025, _T_1986) node _T_2027 = or(_T_2026, _T_1987) node _T_2028 = or(_T_2027, _T_1988) node _T_2029 = or(_T_2028, _T_1989) node _T_2030 = or(_T_2029, _T_1990) node _T_2031 = or(_T_2030, _T_1991) node _T_2032 = or(_T_2031, _T_1992) node _T_2033 = or(_T_2032, _T_1993) node _T_2034 = or(_T_2033, _T_1994) node _T_2035 = and(_T_1933, _T_2034) node _T_2036 = or(UInt<1>(0h0), _T_2035) node _T_2037 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2038 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_2039 = and(_T_2037, _T_2038) node _T_2040 = or(UInt<1>(0h0), _T_2039) node _T_2041 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_2042 = cvt(_T_2041) node _T_2043 = and(_T_2042, asSInt(UInt<14>(0h2000))) node _T_2044 = asSInt(_T_2043) node _T_2045 = eq(_T_2044, asSInt(UInt<1>(0h0))) node _T_2046 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_2047 = cvt(_T_2046) node _T_2048 = and(_T_2047, asSInt(UInt<13>(0h1000))) node _T_2049 = asSInt(_T_2048) node _T_2050 = eq(_T_2049, asSInt(UInt<1>(0h0))) node _T_2051 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2052 = cvt(_T_2051) node _T_2053 = and(_T_2052, asSInt(UInt<18>(0h2f000))) node _T_2054 = asSInt(_T_2053) node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0))) node _T_2056 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_2057 = cvt(_T_2056) node _T_2058 = and(_T_2057, asSInt(UInt<17>(0h10000))) node _T_2059 = asSInt(_T_2058) node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0))) node _T_2061 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_2062 = cvt(_T_2061) node _T_2063 = and(_T_2062, asSInt(UInt<13>(0h1000))) node _T_2064 = asSInt(_T_2063) node _T_2065 = eq(_T_2064, asSInt(UInt<1>(0h0))) node _T_2066 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_2067 = cvt(_T_2066) node _T_2068 = and(_T_2067, asSInt(UInt<27>(0h4000000))) node _T_2069 = asSInt(_T_2068) node _T_2070 = eq(_T_2069, asSInt(UInt<1>(0h0))) node _T_2071 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_2072 = cvt(_T_2071) node _T_2073 = and(_T_2072, asSInt(UInt<13>(0h1000))) node _T_2074 = asSInt(_T_2073) node _T_2075 = eq(_T_2074, asSInt(UInt<1>(0h0))) node _T_2076 = or(_T_2045, _T_2050) node _T_2077 = or(_T_2076, _T_2055) node _T_2078 = or(_T_2077, _T_2060) node _T_2079 = or(_T_2078, _T_2065) node _T_2080 = or(_T_2079, _T_2070) node _T_2081 = or(_T_2080, _T_2075) node _T_2082 = and(_T_2040, _T_2081) node _T_2083 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2084 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<17>(0h10000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = and(_T_2083, _T_2088) node _T_2090 = or(UInt<1>(0h0), _T_2082) node _T_2091 = or(_T_2090, _T_2089) node _T_2092 = and(_T_2036, _T_2091) node _T_2093 = asUInt(reset) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) when _T_2094 : node _T_2095 = eq(_T_2092, UInt<1>(0h0)) when _T_2095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_2092, UInt<1>(0h1), "") : assert_41 node _T_2096 = asUInt(reset) node _T_2097 = eq(_T_2096, UInt<1>(0h0)) when _T_2097 : node _T_2098 = eq(source_ok, UInt<1>(0h0)) when _T_2098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_2099 = asUInt(reset) node _T_2100 = eq(_T_2099, UInt<1>(0h0)) when _T_2100 : node _T_2101 = eq(is_aligned, UInt<1>(0h0)) when _T_2101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_2102 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_2103 = asUInt(reset) node _T_2104 = eq(_T_2103, UInt<1>(0h0)) when _T_2104 : node _T_2105 = eq(_T_2102, UInt<1>(0h0)) when _T_2105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_2102, UInt<1>(0h1), "") : assert_44 node _T_2106 = eq(io.in.a.bits.mask, mask) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_45 node _T_2110 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_2110 : node _T_2111 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2112 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2113 = and(_T_2111, _T_2112) node _T_2114 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_2115 = shr(io.in.a.bits.source, 2) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) node _T_2117 = leq(UInt<1>(0h0), uncommonBits_40) node _T_2118 = and(_T_2116, _T_2117) node _T_2119 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_2120 = and(_T_2118, _T_2119) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_2121 = shr(io.in.a.bits.source, 2) node _T_2122 = eq(_T_2121, UInt<1>(0h1)) node _T_2123 = leq(UInt<1>(0h0), uncommonBits_41) node _T_2124 = and(_T_2122, _T_2123) node _T_2125 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_2126 = and(_T_2124, _T_2125) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_2127 = shr(io.in.a.bits.source, 2) node _T_2128 = eq(_T_2127, UInt<2>(0h2)) node _T_2129 = leq(UInt<1>(0h0), uncommonBits_42) node _T_2130 = and(_T_2128, _T_2129) node _T_2131 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_2132 = and(_T_2130, _T_2131) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_2133 = shr(io.in.a.bits.source, 2) node _T_2134 = eq(_T_2133, UInt<2>(0h3)) node _T_2135 = leq(UInt<1>(0h0), uncommonBits_43) node _T_2136 = and(_T_2134, _T_2135) node _T_2137 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_2138 = and(_T_2136, _T_2137) node _T_2139 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_2140 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_2141 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_2142 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_2143 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_2144 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_2145 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_2146 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_2147 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_2148 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_2149 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_2150 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_2151 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_2152 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_2153 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_2154 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_2155 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_2156 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_2157 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_2158 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_2159 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_2160 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_2161 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_2162 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_2163 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_2164 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_2165 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_2166 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_2167 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_2168 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_2169 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_2170 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_2171 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_2172 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_2173 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_2174 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_2175 = or(_T_2114, _T_2120) node _T_2176 = or(_T_2175, _T_2126) node _T_2177 = or(_T_2176, _T_2132) node _T_2178 = or(_T_2177, _T_2138) node _T_2179 = or(_T_2178, _T_2139) node _T_2180 = or(_T_2179, _T_2140) node _T_2181 = or(_T_2180, _T_2141) node _T_2182 = or(_T_2181, _T_2142) node _T_2183 = or(_T_2182, _T_2143) node _T_2184 = or(_T_2183, _T_2144) node _T_2185 = or(_T_2184, _T_2145) node _T_2186 = or(_T_2185, _T_2146) node _T_2187 = or(_T_2186, _T_2147) node _T_2188 = or(_T_2187, _T_2148) node _T_2189 = or(_T_2188, _T_2149) node _T_2190 = or(_T_2189, _T_2150) node _T_2191 = or(_T_2190, _T_2151) node _T_2192 = or(_T_2191, _T_2152) node _T_2193 = or(_T_2192, _T_2153) node _T_2194 = or(_T_2193, _T_2154) node _T_2195 = or(_T_2194, _T_2155) node _T_2196 = or(_T_2195, _T_2156) node _T_2197 = or(_T_2196, _T_2157) node _T_2198 = or(_T_2197, _T_2158) node _T_2199 = or(_T_2198, _T_2159) node _T_2200 = or(_T_2199, _T_2160) node _T_2201 = or(_T_2200, _T_2161) node _T_2202 = or(_T_2201, _T_2162) node _T_2203 = or(_T_2202, _T_2163) node _T_2204 = or(_T_2203, _T_2164) node _T_2205 = or(_T_2204, _T_2165) node _T_2206 = or(_T_2205, _T_2166) node _T_2207 = or(_T_2206, _T_2167) node _T_2208 = or(_T_2207, _T_2168) node _T_2209 = or(_T_2208, _T_2169) node _T_2210 = or(_T_2209, _T_2170) node _T_2211 = or(_T_2210, _T_2171) node _T_2212 = or(_T_2211, _T_2172) node _T_2213 = or(_T_2212, _T_2173) node _T_2214 = or(_T_2213, _T_2174) node _T_2215 = and(_T_2113, _T_2214) node _T_2216 = or(UInt<1>(0h0), _T_2215) node _T_2217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2219 = and(_T_2217, _T_2218) node _T_2220 = or(UInt<1>(0h0), _T_2219) node _T_2221 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_2222 = cvt(_T_2221) node _T_2223 = and(_T_2222, asSInt(UInt<13>(0h1000))) node _T_2224 = asSInt(_T_2223) node _T_2225 = eq(_T_2224, asSInt(UInt<1>(0h0))) node _T_2226 = and(_T_2220, _T_2225) node _T_2227 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2228 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_2229 = cvt(_T_2228) node _T_2230 = and(_T_2229, asSInt(UInt<14>(0h2000))) node _T_2231 = asSInt(_T_2230) node _T_2232 = eq(_T_2231, asSInt(UInt<1>(0h0))) node _T_2233 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_2234 = cvt(_T_2233) node _T_2235 = and(_T_2234, asSInt(UInt<17>(0h10000))) node _T_2236 = asSInt(_T_2235) node _T_2237 = eq(_T_2236, asSInt(UInt<1>(0h0))) node _T_2238 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2239 = cvt(_T_2238) node _T_2240 = and(_T_2239, asSInt(UInt<18>(0h2f000))) node _T_2241 = asSInt(_T_2240) node _T_2242 = eq(_T_2241, asSInt(UInt<1>(0h0))) node _T_2243 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_2244 = cvt(_T_2243) node _T_2245 = and(_T_2244, asSInt(UInt<17>(0h10000))) node _T_2246 = asSInt(_T_2245) node _T_2247 = eq(_T_2246, asSInt(UInt<1>(0h0))) node _T_2248 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_2249 = cvt(_T_2248) node _T_2250 = and(_T_2249, asSInt(UInt<13>(0h1000))) node _T_2251 = asSInt(_T_2250) node _T_2252 = eq(_T_2251, asSInt(UInt<1>(0h0))) node _T_2253 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_2254 = cvt(_T_2253) node _T_2255 = and(_T_2254, asSInt(UInt<27>(0h4000000))) node _T_2256 = asSInt(_T_2255) node _T_2257 = eq(_T_2256, asSInt(UInt<1>(0h0))) node _T_2258 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_2259 = cvt(_T_2258) node _T_2260 = and(_T_2259, asSInt(UInt<13>(0h1000))) node _T_2261 = asSInt(_T_2260) node _T_2262 = eq(_T_2261, asSInt(UInt<1>(0h0))) node _T_2263 = or(_T_2232, _T_2237) node _T_2264 = or(_T_2263, _T_2242) node _T_2265 = or(_T_2264, _T_2247) node _T_2266 = or(_T_2265, _T_2252) node _T_2267 = or(_T_2266, _T_2257) node _T_2268 = or(_T_2267, _T_2262) node _T_2269 = and(_T_2227, _T_2268) node _T_2270 = or(UInt<1>(0h0), _T_2226) node _T_2271 = or(_T_2270, _T_2269) node _T_2272 = and(_T_2216, _T_2271) node _T_2273 = asUInt(reset) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(_T_2272, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2272, UInt<1>(0h1), "") : assert_46 node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(source_ok, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2279 = asUInt(reset) node _T_2280 = eq(_T_2279, UInt<1>(0h0)) when _T_2280 : node _T_2281 = eq(is_aligned, UInt<1>(0h0)) when _T_2281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2282 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2283 = asUInt(reset) node _T_2284 = eq(_T_2283, UInt<1>(0h0)) when _T_2284 : node _T_2285 = eq(_T_2282, UInt<1>(0h0)) when _T_2285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2282, UInt<1>(0h1), "") : assert_49 node _T_2286 = eq(io.in.a.bits.mask, mask) node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(_T_2286, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2286, UInt<1>(0h1), "") : assert_50 node _T_2290 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2294 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_52 node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_101 = shr(io.in.d.bits.source, 2) node _source_ok_T_102 = eq(_source_ok_T_101, UInt<1>(0h0)) node _source_ok_T_103 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_T_105 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_107 = shr(io.in.d.bits.source, 2) node _source_ok_T_108 = eq(_source_ok_T_107, UInt<1>(0h1)) node _source_ok_T_109 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_T_111 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_113 = shr(io.in.d.bits.source, 2) node _source_ok_T_114 = eq(_source_ok_T_113, UInt<2>(0h2)) node _source_ok_T_115 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_119 = shr(io.in.d.bits.source, 2) node _source_ok_T_120 = eq(_source_ok_T_119, UInt<2>(0h3)) node _source_ok_T_121 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_122 = and(_source_ok_T_120, _source_ok_T_121) node _source_ok_T_123 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[41] connect _source_ok_WIRE_1[0], _source_ok_T_100 connect _source_ok_WIRE_1[1], _source_ok_T_106 connect _source_ok_WIRE_1[2], _source_ok_T_112 connect _source_ok_WIRE_1[3], _source_ok_T_118 connect _source_ok_WIRE_1[4], _source_ok_T_124 connect _source_ok_WIRE_1[5], _source_ok_T_125 connect _source_ok_WIRE_1[6], _source_ok_T_126 connect _source_ok_WIRE_1[7], _source_ok_T_127 connect _source_ok_WIRE_1[8], _source_ok_T_128 connect _source_ok_WIRE_1[9], _source_ok_T_129 connect _source_ok_WIRE_1[10], _source_ok_T_130 connect _source_ok_WIRE_1[11], _source_ok_T_131 connect _source_ok_WIRE_1[12], _source_ok_T_132 connect _source_ok_WIRE_1[13], _source_ok_T_133 connect _source_ok_WIRE_1[14], _source_ok_T_134 connect _source_ok_WIRE_1[15], _source_ok_T_135 connect _source_ok_WIRE_1[16], _source_ok_T_136 connect _source_ok_WIRE_1[17], _source_ok_T_137 connect _source_ok_WIRE_1[18], _source_ok_T_138 connect _source_ok_WIRE_1[19], _source_ok_T_139 connect _source_ok_WIRE_1[20], _source_ok_T_140 connect _source_ok_WIRE_1[21], _source_ok_T_141 connect _source_ok_WIRE_1[22], _source_ok_T_142 connect _source_ok_WIRE_1[23], _source_ok_T_143 connect _source_ok_WIRE_1[24], _source_ok_T_144 connect _source_ok_WIRE_1[25], _source_ok_T_145 connect _source_ok_WIRE_1[26], _source_ok_T_146 connect _source_ok_WIRE_1[27], _source_ok_T_147 connect _source_ok_WIRE_1[28], _source_ok_T_148 connect _source_ok_WIRE_1[29], _source_ok_T_149 connect _source_ok_WIRE_1[30], _source_ok_T_150 connect _source_ok_WIRE_1[31], _source_ok_T_151 connect _source_ok_WIRE_1[32], _source_ok_T_152 connect _source_ok_WIRE_1[33], _source_ok_T_153 connect _source_ok_WIRE_1[34], _source_ok_T_154 connect _source_ok_WIRE_1[35], _source_ok_T_155 connect _source_ok_WIRE_1[36], _source_ok_T_156 connect _source_ok_WIRE_1[37], _source_ok_T_157 connect _source_ok_WIRE_1[38], _source_ok_T_158 connect _source_ok_WIRE_1[39], _source_ok_T_159 connect _source_ok_WIRE_1[40], _source_ok_T_160 node _source_ok_T_161 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_162 = or(_source_ok_T_161, _source_ok_WIRE_1[2]) node _source_ok_T_163 = or(_source_ok_T_162, _source_ok_WIRE_1[3]) node _source_ok_T_164 = or(_source_ok_T_163, _source_ok_WIRE_1[4]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[5]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[6]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[7]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[8]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[9]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[10]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[11]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[12]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[13]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[14]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[15]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[16]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[17]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[18]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[19]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[20]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[21]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[22]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[23]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[24]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[25]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[26]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[27]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[28]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[29]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[30]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[31]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[32]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[33]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[34]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[35]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[36]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[37]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[38]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[39]) node source_ok_1 = or(_source_ok_T_199, _source_ok_WIRE_1[40]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2298 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2298 : node _T_2299 = asUInt(reset) node _T_2300 = eq(_T_2299, UInt<1>(0h0)) when _T_2300 : node _T_2301 = eq(source_ok_1, UInt<1>(0h0)) when _T_2301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2302 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_54 node _T_2306 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2307 = asUInt(reset) node _T_2308 = eq(_T_2307, UInt<1>(0h0)) when _T_2308 : node _T_2309 = eq(_T_2306, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2306, UInt<1>(0h1), "") : assert_55 node _T_2310 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2311 = asUInt(reset) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) when _T_2312 : node _T_2313 = eq(_T_2310, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2310, UInt<1>(0h1), "") : assert_56 node _T_2314 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2315 = asUInt(reset) node _T_2316 = eq(_T_2315, UInt<1>(0h0)) when _T_2316 : node _T_2317 = eq(_T_2314, UInt<1>(0h0)) when _T_2317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2314, UInt<1>(0h1), "") : assert_57 node _T_2318 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2318 : node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(source_ok_1, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2322 = asUInt(reset) node _T_2323 = eq(_T_2322, UInt<1>(0h0)) when _T_2323 : node _T_2324 = eq(sink_ok, UInt<1>(0h0)) when _T_2324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2325 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2326 = asUInt(reset) node _T_2327 = eq(_T_2326, UInt<1>(0h0)) when _T_2327 : node _T_2328 = eq(_T_2325, UInt<1>(0h0)) when _T_2328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2325, UInt<1>(0h1), "") : assert_60 node _T_2329 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2330 = asUInt(reset) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) when _T_2331 : node _T_2332 = eq(_T_2329, UInt<1>(0h0)) when _T_2332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2329, UInt<1>(0h1), "") : assert_61 node _T_2333 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2334 = asUInt(reset) node _T_2335 = eq(_T_2334, UInt<1>(0h0)) when _T_2335 : node _T_2336 = eq(_T_2333, UInt<1>(0h0)) when _T_2336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2333, UInt<1>(0h1), "") : assert_62 node _T_2337 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_63 node _T_2341 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2342 = or(UInt<1>(0h1), _T_2341) node _T_2343 = asUInt(reset) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) when _T_2344 : node _T_2345 = eq(_T_2342, UInt<1>(0h0)) when _T_2345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2342, UInt<1>(0h1), "") : assert_64 node _T_2346 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2346 : node _T_2347 = asUInt(reset) node _T_2348 = eq(_T_2347, UInt<1>(0h0)) when _T_2348 : node _T_2349 = eq(source_ok_1, UInt<1>(0h0)) when _T_2349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2350 = asUInt(reset) node _T_2351 = eq(_T_2350, UInt<1>(0h0)) when _T_2351 : node _T_2352 = eq(sink_ok, UInt<1>(0h0)) when _T_2352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2353 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2354 = asUInt(reset) node _T_2355 = eq(_T_2354, UInt<1>(0h0)) when _T_2355 : node _T_2356 = eq(_T_2353, UInt<1>(0h0)) when _T_2356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2353, UInt<1>(0h1), "") : assert_67 node _T_2357 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2358 = asUInt(reset) node _T_2359 = eq(_T_2358, UInt<1>(0h0)) when _T_2359 : node _T_2360 = eq(_T_2357, UInt<1>(0h0)) when _T_2360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2357, UInt<1>(0h1), "") : assert_68 node _T_2361 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2362 = asUInt(reset) node _T_2363 = eq(_T_2362, UInt<1>(0h0)) when _T_2363 : node _T_2364 = eq(_T_2361, UInt<1>(0h0)) when _T_2364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2361, UInt<1>(0h1), "") : assert_69 node _T_2365 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2366 = or(_T_2365, io.in.d.bits.corrupt) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_70 node _T_2370 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2371 = or(UInt<1>(0h1), _T_2370) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_71 node _T_2375 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2375 : node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(source_ok_1, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2379 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_73 node _T_2383 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_74 node _T_2387 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2388 = or(UInt<1>(0h1), _T_2387) node _T_2389 = asUInt(reset) node _T_2390 = eq(_T_2389, UInt<1>(0h0)) when _T_2390 : node _T_2391 = eq(_T_2388, UInt<1>(0h0)) when _T_2391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2388, UInt<1>(0h1), "") : assert_75 node _T_2392 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2392 : node _T_2393 = asUInt(reset) node _T_2394 = eq(_T_2393, UInt<1>(0h0)) when _T_2394 : node _T_2395 = eq(source_ok_1, UInt<1>(0h0)) when _T_2395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2396 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2397 = asUInt(reset) node _T_2398 = eq(_T_2397, UInt<1>(0h0)) when _T_2398 : node _T_2399 = eq(_T_2396, UInt<1>(0h0)) when _T_2399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2396, UInt<1>(0h1), "") : assert_77 node _T_2400 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2401 = or(_T_2400, io.in.d.bits.corrupt) node _T_2402 = asUInt(reset) node _T_2403 = eq(_T_2402, UInt<1>(0h0)) when _T_2403 : node _T_2404 = eq(_T_2401, UInt<1>(0h0)) when _T_2404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2401, UInt<1>(0h1), "") : assert_78 node _T_2405 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2406 = or(UInt<1>(0h1), _T_2405) node _T_2407 = asUInt(reset) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) when _T_2408 : node _T_2409 = eq(_T_2406, UInt<1>(0h0)) when _T_2409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2406, UInt<1>(0h1), "") : assert_79 node _T_2410 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2410 : node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(source_ok_1, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2414 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_81 node _T_2418 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2419 = asUInt(reset) node _T_2420 = eq(_T_2419, UInt<1>(0h0)) when _T_2420 : node _T_2421 = eq(_T_2418, UInt<1>(0h0)) when _T_2421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2418, UInt<1>(0h1), "") : assert_82 node _T_2422 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2423 = or(UInt<1>(0h1), _T_2422) node _T_2424 = asUInt(reset) node _T_2425 = eq(_T_2424, UInt<1>(0h0)) when _T_2425 : node _T_2426 = eq(_T_2423, UInt<1>(0h0)) when _T_2426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2423, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2427 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2431 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2435 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2439 = eq(a_first, UInt<1>(0h0)) node _T_2440 = and(io.in.a.valid, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.a.bits.opcode, opcode) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_87 node _T_2445 = eq(io.in.a.bits.param, param) node _T_2446 = asUInt(reset) node _T_2447 = eq(_T_2446, UInt<1>(0h0)) when _T_2447 : node _T_2448 = eq(_T_2445, UInt<1>(0h0)) when _T_2448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2445, UInt<1>(0h1), "") : assert_88 node _T_2449 = eq(io.in.a.bits.size, size) node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(_T_2449, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2449, UInt<1>(0h1), "") : assert_89 node _T_2453 = eq(io.in.a.bits.source, source) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_90 node _T_2457 = eq(io.in.a.bits.address, address) node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(_T_2457, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2457, UInt<1>(0h1), "") : assert_91 node _T_2461 = and(io.in.a.ready, io.in.a.valid) node _T_2462 = and(_T_2461, a_first) when _T_2462 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2463 = eq(d_first, UInt<1>(0h0)) node _T_2464 = and(io.in.d.valid, _T_2463) when _T_2464 : node _T_2465 = eq(io.in.d.bits.opcode, opcode_1) node _T_2466 = asUInt(reset) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) when _T_2467 : node _T_2468 = eq(_T_2465, UInt<1>(0h0)) when _T_2468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2465, UInt<1>(0h1), "") : assert_92 node _T_2469 = eq(io.in.d.bits.param, param_1) node _T_2470 = asUInt(reset) node _T_2471 = eq(_T_2470, UInt<1>(0h0)) when _T_2471 : node _T_2472 = eq(_T_2469, UInt<1>(0h0)) when _T_2472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2469, UInt<1>(0h1), "") : assert_93 node _T_2473 = eq(io.in.d.bits.size, size_1) node _T_2474 = asUInt(reset) node _T_2475 = eq(_T_2474, UInt<1>(0h0)) when _T_2475 : node _T_2476 = eq(_T_2473, UInt<1>(0h0)) when _T_2476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2473, UInt<1>(0h1), "") : assert_94 node _T_2477 = eq(io.in.d.bits.source, source_1) node _T_2478 = asUInt(reset) node _T_2479 = eq(_T_2478, UInt<1>(0h0)) when _T_2479 : node _T_2480 = eq(_T_2477, UInt<1>(0h0)) when _T_2480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2477, UInt<1>(0h1), "") : assert_95 node _T_2481 = eq(io.in.d.bits.sink, sink) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_96 node _T_2485 = eq(io.in.d.bits.denied, denied) node _T_2486 = asUInt(reset) node _T_2487 = eq(_T_2486, UInt<1>(0h0)) when _T_2487 : node _T_2488 = eq(_T_2485, UInt<1>(0h0)) when _T_2488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2485, UInt<1>(0h1), "") : assert_97 node _T_2489 = and(io.in.d.ready, io.in.d.valid) node _T_2490 = and(_T_2489, d_first) when _T_2490 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<79>, clock, reset, UInt<79>(0h0) regreset inflight_opcodes : UInt<316>, clock, reset, UInt<316>(0h0) regreset inflight_sizes : UInt<632>, clock, reset, UInt<632>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<79> connect a_set, UInt<79>(0h0) wire a_set_wo_ready : UInt<79> connect a_set_wo_ready, UInt<79>(0h0) wire a_opcodes_set : UInt<316> connect a_opcodes_set, UInt<316>(0h0) wire a_sizes_set : UInt<632> connect a_sizes_set, UInt<632>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2491 = and(io.in.a.valid, a_first_1) node _T_2492 = and(_T_2491, UInt<1>(0h1)) when _T_2492 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2493 = and(io.in.a.ready, io.in.a.valid) node _T_2494 = and(_T_2493, a_first_1) node _T_2495 = and(_T_2494, UInt<1>(0h1)) when _T_2495 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2496 = dshr(inflight, io.in.a.bits.source) node _T_2497 = bits(_T_2496, 0, 0) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) node _T_2499 = asUInt(reset) node _T_2500 = eq(_T_2499, UInt<1>(0h0)) when _T_2500 : node _T_2501 = eq(_T_2498, UInt<1>(0h0)) when _T_2501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2498, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<79> connect d_clr, UInt<79>(0h0) wire d_clr_wo_ready : UInt<79> connect d_clr_wo_ready, UInt<79>(0h0) wire d_opcodes_clr : UInt<316> connect d_opcodes_clr, UInt<316>(0h0) wire d_sizes_clr : UInt<632> connect d_sizes_clr, UInt<632>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2502 = and(io.in.d.valid, d_first_1) node _T_2503 = and(_T_2502, UInt<1>(0h1)) node _T_2504 = eq(d_release_ack, UInt<1>(0h0)) node _T_2505 = and(_T_2503, _T_2504) when _T_2505 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2506 = and(io.in.d.ready, io.in.d.valid) node _T_2507 = and(_T_2506, d_first_1) node _T_2508 = and(_T_2507, UInt<1>(0h1)) node _T_2509 = eq(d_release_ack, UInt<1>(0h0)) node _T_2510 = and(_T_2508, _T_2509) when _T_2510 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2511 = and(io.in.d.valid, d_first_1) node _T_2512 = and(_T_2511, UInt<1>(0h1)) node _T_2513 = eq(d_release_ack, UInt<1>(0h0)) node _T_2514 = and(_T_2512, _T_2513) when _T_2514 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2515 = dshr(inflight, io.in.d.bits.source) node _T_2516 = bits(_T_2515, 0, 0) node _T_2517 = or(_T_2516, same_cycle_resp) node _T_2518 = asUInt(reset) node _T_2519 = eq(_T_2518, UInt<1>(0h0)) when _T_2519 : node _T_2520 = eq(_T_2517, UInt<1>(0h0)) when _T_2520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2517, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2521 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2522 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2523 = or(_T_2521, _T_2522) node _T_2524 = asUInt(reset) node _T_2525 = eq(_T_2524, UInt<1>(0h0)) when _T_2525 : node _T_2526 = eq(_T_2523, UInt<1>(0h0)) when _T_2526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2523, UInt<1>(0h1), "") : assert_100 node _T_2527 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2528 = asUInt(reset) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) when _T_2529 : node _T_2530 = eq(_T_2527, UInt<1>(0h0)) when _T_2530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2527, UInt<1>(0h1), "") : assert_101 else : node _T_2531 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2532 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2533 = or(_T_2531, _T_2532) node _T_2534 = asUInt(reset) node _T_2535 = eq(_T_2534, UInt<1>(0h0)) when _T_2535 : node _T_2536 = eq(_T_2533, UInt<1>(0h0)) when _T_2536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2533, UInt<1>(0h1), "") : assert_102 node _T_2537 = eq(io.in.d.bits.size, a_size_lookup) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_103 node _T_2541 = and(io.in.d.valid, d_first_1) node _T_2542 = and(_T_2541, a_first_1) node _T_2543 = and(_T_2542, io.in.a.valid) node _T_2544 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2545 = and(_T_2543, _T_2544) node _T_2546 = eq(d_release_ack, UInt<1>(0h0)) node _T_2547 = and(_T_2545, _T_2546) when _T_2547 : node _T_2548 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2549 = or(_T_2548, io.in.a.ready) node _T_2550 = asUInt(reset) node _T_2551 = eq(_T_2550, UInt<1>(0h0)) when _T_2551 : node _T_2552 = eq(_T_2549, UInt<1>(0h0)) when _T_2552 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2549, UInt<1>(0h1), "") : assert_104 node _T_2553 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2554 = orr(a_set_wo_ready) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) node _T_2556 = or(_T_2553, _T_2555) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_86 node _T_2560 = orr(inflight) node _T_2561 = eq(_T_2560, UInt<1>(0h0)) node _T_2562 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2563 = or(_T_2561, _T_2562) node _T_2564 = lt(watchdog, plusarg_reader.out) node _T_2565 = or(_T_2563, _T_2564) node _T_2566 = asUInt(reset) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) when _T_2567 : node _T_2568 = eq(_T_2565, UInt<1>(0h0)) when _T_2568 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2565, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2569 = and(io.in.a.ready, io.in.a.valid) node _T_2570 = and(io.in.d.ready, io.in.d.valid) node _T_2571 = or(_T_2569, _T_2570) when _T_2571 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<79>, clock, reset, UInt<79>(0h0) regreset inflight_opcodes_1 : UInt<316>, clock, reset, UInt<316>(0h0) regreset inflight_sizes_1 : UInt<632>, clock, reset, UInt<632>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<79> connect c_set, UInt<79>(0h0) wire c_set_wo_ready : UInt<79> connect c_set_wo_ready, UInt<79>(0h0) wire c_opcodes_set : UInt<316> connect c_opcodes_set, UInt<316>(0h0) wire c_sizes_set : UInt<632> connect c_sizes_set, UInt<632>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2572 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2573 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2574 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2575 = and(_T_2573, _T_2574) node _T_2576 = and(_T_2572, _T_2575) when _T_2576 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2577 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2578 = and(_T_2577, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2579 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2580 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2581 = and(_T_2579, _T_2580) node _T_2582 = and(_T_2578, _T_2581) when _T_2582 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2583 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2584 = bits(_T_2583, 0, 0) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<79> connect d_clr_1, UInt<79>(0h0) wire d_clr_wo_ready_1 : UInt<79> connect d_clr_wo_ready_1, UInt<79>(0h0) wire d_opcodes_clr_1 : UInt<316> connect d_opcodes_clr_1, UInt<316>(0h0) wire d_sizes_clr_1 : UInt<632> connect d_sizes_clr_1, UInt<632>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2589 = and(io.in.d.valid, d_first_2) node _T_2590 = and(_T_2589, UInt<1>(0h1)) node _T_2591 = and(_T_2590, d_release_ack_1) when _T_2591 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2592 = and(io.in.d.ready, io.in.d.valid) node _T_2593 = and(_T_2592, d_first_2) node _T_2594 = and(_T_2593, UInt<1>(0h1)) node _T_2595 = and(_T_2594, d_release_ack_1) when _T_2595 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2596 = and(io.in.d.valid, d_first_2) node _T_2597 = and(_T_2596, UInt<1>(0h1)) node _T_2598 = and(_T_2597, d_release_ack_1) when _T_2598 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2599 = dshr(inflight_1, io.in.d.bits.source) node _T_2600 = bits(_T_2599, 0, 0) node _T_2601 = or(_T_2600, same_cycle_resp_1) node _T_2602 = asUInt(reset) node _T_2603 = eq(_T_2602, UInt<1>(0h0)) when _T_2603 : node _T_2604 = eq(_T_2601, UInt<1>(0h0)) when _T_2604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2601, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2605 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2606 = asUInt(reset) node _T_2607 = eq(_T_2606, UInt<1>(0h0)) when _T_2607 : node _T_2608 = eq(_T_2605, UInt<1>(0h0)) when _T_2608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2605, UInt<1>(0h1), "") : assert_109 else : node _T_2609 = eq(io.in.d.bits.size, c_size_lookup) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_110 node _T_2613 = and(io.in.d.valid, d_first_2) node _T_2614 = and(_T_2613, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2615 = and(_T_2614, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2616 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2617 = and(_T_2615, _T_2616) node _T_2618 = and(_T_2617, d_release_ack_1) node _T_2619 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2620 = and(_T_2618, _T_2619) when _T_2620 : node _T_2621 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2622 = or(_T_2621, _WIRE_27.ready) node _T_2623 = asUInt(reset) node _T_2624 = eq(_T_2623, UInt<1>(0h0)) when _T_2624 : node _T_2625 = eq(_T_2622, UInt<1>(0h0)) when _T_2625 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_2622, UInt<1>(0h1), "") : assert_111 node _T_2626 = orr(c_set_wo_ready) when _T_2626 : node _T_2627 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2628 = asUInt(reset) node _T_2629 = eq(_T_2628, UInt<1>(0h0)) when _T_2629 : node _T_2630 = eq(_T_2627, UInt<1>(0h0)) when _T_2630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_2627, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_87 node _T_2631 = orr(inflight_1) node _T_2632 = eq(_T_2631, UInt<1>(0h0)) node _T_2633 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2634 = or(_T_2632, _T_2633) node _T_2635 = lt(watchdog_1, plusarg_reader_1.out) node _T_2636 = or(_T_2634, _T_2635) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2640 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2641 = and(io.in.d.ready, io.in.d.valid) node _T_2642 = or(_T_2640, _T_2641) when _T_2642 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_89 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [78:0] inflight; // @[Monitor.scala:614:27] reg [315:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [631:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [78:0] inflight_1; // @[Monitor.scala:726:35] reg [631:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_104 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, flip out_credit_available : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} inst input_buffer of InputBuffer_104 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) inst route_arbiter of Arbiter5_RouteComputerReq_32 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h11)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id connect route_arbiter.io.in[4].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[4].bits.flow.egress_node_id invalidate route_arbiter.io.in[4].bits.flow.egress_node invalidate route_arbiter.io.in[4].bits.flow.ingress_node_id invalidate route_arbiter.io.in[4].bits.flow.ingress_node invalidate route_arbiter.io.in[4].bits.flow.vnet_id invalidate route_arbiter.io.in[4].bits.src_virt_id node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}[5] wire vcalloc_vals : UInt<1>[5] node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0)) node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23) node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_20 = and(io.router_req.ready, io.router_req.valid) when _T_20 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_22 = or(_T_21, vcalloc_vals[2]) node _T_23 = or(_T_22, vcalloc_vals[3]) node _T_24 = or(_T_23, vcalloc_vals[4]) when _T_24 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = bits(vcalloc_sel, 0, 0) node _mask_T_9 = bits(vcalloc_sel, 1, 1) node _mask_T_10 = bits(vcalloc_sel, 2, 2) node _mask_T_11 = bits(vcalloc_sel, 3, 3) node _mask_T_12 = bits(vcalloc_sel, 4, 4) node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0)) node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0)) node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0)) node _mask_T_18 = or(_mask_T_13, _mask_T_14) node _mask_T_19 = or(_mask_T_18, _mask_T_15) node _mask_T_20 = or(_mask_T_19, _mask_T_16) node _mask_T_21 = or(_mask_T_20, _mask_T_17) wire _mask_WIRE : UInt<5> connect _mask_WIRE, _mask_T_21 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}} wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5] node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[5] node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_76 connect _io_vcalloc_req_bits_WIRE_8[2], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_8[3], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_94 connect _io_vcalloc_req_bits_WIRE_8[4], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_14 : UInt<3> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_103 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_15 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_15.egress_node_id, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117) wire _io_vcalloc_req_bits_WIRE_17 : UInt<5> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_121 connect _io_vcalloc_req_bits_WIRE_15.egress_node, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123) node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124) node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_130 connect _io_vcalloc_req_bits_WIRE_15.ingress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_131, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_19 : UInt<5> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_139 connect _io_vcalloc_req_bits_WIRE_15.ingress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_143) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_144) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_15.vnet_id, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_15 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].flow, states[1].flow node _T_25 = bits(vcalloc_sel, 1, 1) node _T_26 = and(vcalloc_vals[1], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[1].g, UInt<3>(0h3) connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id connect vcalloc_vals[4], UInt<1>(0h0) invalidate vcalloc_reqs[4].vc_sel.`0`[0] invalidate vcalloc_reqs[4].vc_sel.`0`[1] invalidate vcalloc_reqs[4].vc_sel.`0`[2] invalidate vcalloc_reqs[4].vc_sel.`0`[3] invalidate vcalloc_reqs[4].vc_sel.`0`[4] invalidate vcalloc_reqs[4].vc_sel.`1`[0] invalidate vcalloc_reqs[4].vc_sel.`1`[1] invalidate vcalloc_reqs[4].vc_sel.`1`[2] invalidate vcalloc_reqs[4].vc_sel.`1`[3] invalidate vcalloc_reqs[4].vc_sel.`1`[4] invalidate vcalloc_reqs[4].in_vc invalidate vcalloc_reqs[4].flow.egress_node_id invalidate vcalloc_reqs[4].flow.egress_node invalidate vcalloc_reqs[4].flow.ingress_node_id invalidate vcalloc_reqs[4].flow.ingress_node invalidate vcalloc_reqs[4].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready) node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1) connect io.debug.va_stall, _io_debug_va_stall_T_9 node _T_28 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_28 : node _T_29 = bits(vcalloc_sel, 0, 0) when _T_29 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].g, UInt<3>(0h3) node _T_30 = eq(states[0].g, UInt<3>(0h2)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].g, UInt<3>(0h3) node _T_35 = eq(states[1].g, UInt<3>(0h2)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_35, UInt<1>(0h1), "") : assert_4 node _T_39 = bits(vcalloc_sel, 2, 2) when _T_39 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].g, UInt<3>(0h3) node _T_40 = eq(states[2].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = bits(vcalloc_sel, 3, 3) when _T_44 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].g, UInt<3>(0h3) node _T_45 = eq(states[3].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_45, UInt<1>(0h1), "") : assert_6 node _T_49 = bits(vcalloc_sel, 4, 4) when _T_49 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].g, UInt<3>(0h3) node _T_50 = eq(states[4].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_50, UInt<1>(0h1), "") : assert_7 inst salloc_arb of SwitchArbiter_267 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] node credit_available_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[4], states[1].vc_sel.`0`[3]) node credit_available_hi = cat(credit_available_hi_hi, states[1].vc_sel.`0`[2]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[4], states[1].vc_sel.`1`[3]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[1].vc_sel.`1`[2]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_2 = cat(_credit_available_T_1, _credit_available_T) node credit_available_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_hi_hi_2 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, io.out_credit_available.`0`[2]) node _credit_available_T_3 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_3 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`1`[2]) node _credit_available_T_4 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_5 = cat(_credit_available_T_4, _credit_available_T_3) node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5) node credit_available = neq(_credit_available_T_6, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_54 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_55 = and(_T_54, input_buffer.io.deq[1].bits.tail) when _T_55 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] connect salloc_arb.io.in[4].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[4].bits.tail invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[4] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_17 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7) node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14 node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_16 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _vc_sel_WIRE : UInt<1>[5] node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6) node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_13 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_22 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25) node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26) node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_31 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34) node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_40 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_49 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_6 : UInt<1>[5] node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_58 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_67 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70) node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71) node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_76 connect _vc_sel_WIRE_6[2], _vc_sel_WIRE_9 node _vc_sel_T_77 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_78 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_79 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_80 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_81 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_82 = or(_vc_sel_T_77, _vc_sel_T_78) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_79) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_80) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_81) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_85 connect _vc_sel_WIRE_6[3], _vc_sel_WIRE_10 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_88) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_89) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_90) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_94 connect _vc_sel_WIRE_6[4], _vc_sel_WIRE_11 connect vc_sel.`1`, _vc_sel_WIRE_6 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_3 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`1`[2]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`1`[3]) node channel_oh_1 = or(_channel_oh_T_5, vc_sel.`1`[4]) node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_3 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, vc_sel.`1`[2]) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 4, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node _virt_channel_T_16 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_18 = or(_virt_channel_T_16, _virt_channel_T_17) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_18 node _T_56 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_56 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6) node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6) node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6) node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[1], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].g invalidate states[4].fifo_deps invalidate states[4].flow.egress_node_id invalidate states[4].flow.egress_node invalidate states[4].flow.ingress_node_id invalidate states[4].flow.ingress_node invalidate states[4].flow.vnet_id invalidate states[4].vc_sel.`0`[0] invalidate states[4].vc_sel.`0`[1] invalidate states[4].vc_sel.`0`[2] invalidate states[4].vc_sel.`0`[3] invalidate states[4].vc_sel.`0`[4] invalidate states[4].vc_sel.`1`[0] invalidate states[4].vc_sel.`1`[1] invalidate states[4].vc_sel.`1`[2] invalidate states[4].vc_sel.`1`[3] invalidate states[4].vc_sel.`1`[4] invalidate states[4].g node _T_57 = asUInt(reset) when _T_57 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0)

module InputUnit_104( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {3'h0, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {3'h0, vcalloc_vals_1, 6'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_1; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_64 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_129 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_130 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_31 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_31 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_31 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h14)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_10 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_11 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_12 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_13 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_14 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_15 : connect states[7].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) node _T_35 = or(_T_34, vcalloc_vals[6]) node _T_36 = or(_T_35, vcalloc_vals[7]) when _T_36 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_38 : UInt<3> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38 wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<2> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<5> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<2> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<5> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<3> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[3] invalidate vcalloc_reqs[0].vc_sel.`3`[4] invalidate vcalloc_reqs[0].vc_sel.`3`[5] invalidate vcalloc_reqs[0].vc_sel.`3`[6] invalidate vcalloc_reqs[0].vc_sel.`3`[7] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_37 = bits(vcalloc_sel, 1, 1) node _T_38 = and(vcalloc_vals[1], _T_37) node _T_39 = and(_T_38, io.vcalloc_req.ready) when _T_39 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].flow, states[2].flow node _T_40 = bits(vcalloc_sel, 2, 2) node _T_41 = and(vcalloc_vals[2], _T_40) node _T_42 = and(_T_41, io.vcalloc_req.ready) when _T_42 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_43 = bits(vcalloc_sel, 3, 3) node _T_44 = and(vcalloc_vals[3], _T_43) node _T_45 = and(_T_44, io.vcalloc_req.ready) when _T_45 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_46 = bits(vcalloc_sel, 4, 4) node _T_47 = and(vcalloc_vals[4], _T_46) node _T_48 = and(_T_47, io.vcalloc_req.ready) when _T_48 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_49 = bits(vcalloc_sel, 5, 5) node _T_50 = and(vcalloc_vals[5], _T_49) node _T_51 = and(_T_50, io.vcalloc_req.ready) when _T_51 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].flow, states[6].flow node _T_52 = bits(vcalloc_sel, 6, 6) node _T_53 = and(vcalloc_vals[6], _T_52) node _T_54 = and(_T_53, io.vcalloc_req.ready) when _T_54 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].flow, states[7].flow node _T_55 = bits(vcalloc_sel, 7, 7) node _T_56 = and(vcalloc_vals[7], _T_55) node _T_57 = and(_T_56, io.vcalloc_req.ready) when _T_57 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_58 : node _T_59 = bits(vcalloc_sel, 0, 0) when _T_59 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_60 = eq(states[0].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_60, UInt<1>(0h1), "") : assert_3 node _T_64 = bits(vcalloc_sel, 1, 1) when _T_64 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_65 = eq(states[1].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_65, UInt<1>(0h1), "") : assert_4 node _T_69 = bits(vcalloc_sel, 2, 2) when _T_69 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_70 = eq(states[2].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _T_74 = bits(vcalloc_sel, 3, 3) when _T_74 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_75 = eq(states[3].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_75, UInt<1>(0h1), "") : assert_6 node _T_79 = bits(vcalloc_sel, 4, 4) when _T_79 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_80 = eq(states[4].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_80, UInt<1>(0h1), "") : assert_7 node _T_84 = bits(vcalloc_sel, 5, 5) when _T_84 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_85 = eq(states[5].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_85, UInt<1>(0h1), "") : assert_8 node _T_89 = bits(vcalloc_sel, 6, 6) when _T_89 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].g, UInt<3>(0h3) node _T_90 = eq(states[6].g, UInt<3>(0h2)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = bits(vcalloc_sel, 7, 7) when _T_94 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].g, UInt<3>(0h3) node _T_95 = eq(states[7].g, UInt<3>(0h2)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_95, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_92 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[7] node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5) node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail) when _T_100 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_8 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_8 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_8 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_lo_9 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_9 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_9 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11) node credit_available_lo_lo_10 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_10 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_10 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_11 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_11 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11) node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail) when _T_102 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_16 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_16 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_16 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_17 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_17 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_17 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_18 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_18 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_18 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_lo_19 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_19 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_19 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23) node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27) node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31) node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail) when _T_104 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_24 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_24 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_25 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_25 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_26 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_26 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_27 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_27 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33) node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35) node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35) node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38) node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42) node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail) when _T_106 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_32 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_32 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_32 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_lo_33 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_33 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_33 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_34 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_34 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_34 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_35 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_35 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_35 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44) node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47) node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49) node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53) node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail) when _T_108 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_40 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_40 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_41 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_41 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_42 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_42 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42) node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_lo_43 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_43 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43) node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57) node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44) node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45) node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46) node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47) node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60) node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62) node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64) node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail) when _T_110 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_48 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_48 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48) node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_49 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_49 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49) node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_50 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_50 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50) node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_51 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_51 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51) node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66) node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68) node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52) node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53) node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54) node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55) node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73) node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69) node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75) node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail) when _T_112 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34) node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_38 node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_113 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`3`[3] invalidate states[0].vc_sel.`3`[4] invalidate states[0].vc_sel.`3`[5] invalidate states[0].vc_sel.`3`[6] invalidate states[0].vc_sel.`3`[7] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[3], UInt<1>(0h0) connect states[1].vc_sel.`3`[4], UInt<1>(0h0) connect states[1].vc_sel.`3`[5], UInt<1>(0h0) connect states[1].vc_sel.`3`[6], UInt<1>(0h0) connect states[1].vc_sel.`3`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[3], UInt<1>(0h0) connect states[2].vc_sel.`3`[4], UInt<1>(0h0) connect states[2].vc_sel.`3`[5], UInt<1>(0h0) connect states[2].vc_sel.`3`[6], UInt<1>(0h0) connect states[2].vc_sel.`3`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[1], UInt<1>(0h0) connect states[3].vc_sel.`3`[2], UInt<1>(0h0) connect states[3].vc_sel.`3`[3], UInt<1>(0h0) connect states[3].vc_sel.`3`[4], UInt<1>(0h0) connect states[3].vc_sel.`3`[5], UInt<1>(0h0) connect states[3].vc_sel.`3`[6], UInt<1>(0h0) connect states[3].vc_sel.`3`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[1], UInt<1>(0h0) connect states[4].vc_sel.`3`[2], UInt<1>(0h0) connect states[4].vc_sel.`3`[3], UInt<1>(0h0) connect states[4].vc_sel.`3`[4], UInt<1>(0h0) connect states[4].vc_sel.`3`[5], UInt<1>(0h0) connect states[4].vc_sel.`3`[6], UInt<1>(0h0) connect states[4].vc_sel.`3`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[1], UInt<1>(0h0) connect states[5].vc_sel.`3`[2], UInt<1>(0h0) connect states[5].vc_sel.`3`[3], UInt<1>(0h0) connect states[5].vc_sel.`3`[4], UInt<1>(0h0) connect states[5].vc_sel.`3`[5], UInt<1>(0h0) connect states[5].vc_sel.`3`[6], UInt<1>(0h0) connect states[5].vc_sel.`3`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[1], UInt<1>(0h0) connect states[6].vc_sel.`3`[2], UInt<1>(0h0) connect states[6].vc_sel.`3`[3], UInt<1>(0h0) connect states[6].vc_sel.`3`[4], UInt<1>(0h0) connect states[6].vc_sel.`3`[5], UInt<1>(0h0) connect states[6].vc_sel.`3`[6], UInt<1>(0h0) connect states[6].vc_sel.`3`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[1], UInt<1>(0h0) connect states[7].vc_sel.`3`[2], UInt<1>(0h0) connect states[7].vc_sel.`3`[3], UInt<1>(0h0) connect states[7].vc_sel.`3`[4], UInt<1>(0h0) connect states[7].vc_sel.`3`[5], UInt<1>(0h0) connect states[7].vc_sel.`3`[6], UInt<1>(0h0) connect states[7].vc_sel.`3`[7], UInt<1>(0h0) node _T_114 = asUInt(reset) when _T_114 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)

module InputUnit_31( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_95 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_96 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PE_14 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg

module PE_14( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_199 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_455 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_199( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_455 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<10>(0h200))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<10>(0h200))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<10>(0h200))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<10>(0h200))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<10>(0h200))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<10>(0h200))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<10>(0h200))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<10>(0h200))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<10>(0h200))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<10>(0h200))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_121 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_122 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:137)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_200 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_200( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_190 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_350 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_190( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_350 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_15 : output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_7 node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51) node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0)) node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1) connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2 connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RecFNToRecFN_15( // @[RecFNToRecFN.scala:44:5] input [64:0] io_in, // @[RecFNToRecFN.scala:48:16] input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out, // @[RecFNToRecFN.scala:48:16] output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23] RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_7 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23] .io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23] .io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RecFNToRecFN.scala:72:19] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_T = eq(request.source, UInt<6>(0h24)) node _req_clientBit_T_1 = eq(request.source, UInt<6>(0h20)) node req_clientBit = cat(_req_clientBit_T_1, _req_clientBit_T) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_T = eq(io.sinkc.bits.source, UInt<6>(0h24)) node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<6>(0h20)) node probe_bit = cat(_probe_bit_T_1, _probe_bit_T) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_T = eq(new_request.source, UInt<6>(0h24)) node _new_clientBit_T_1 = eq(new_request.source, UInt<6>(0h20)) node new_clientBit = cat(_new_clientBit_T_1, _new_clientBit_T) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53] wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s2k3z4u_3 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a32d256s2k3z4u_3( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [1:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [1:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [1:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [31:0] saved_mask; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_8 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_16 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_8 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h2) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<2>(0h2) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h7), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_16 = eq(UInt<3>(0h6), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<3>(0h7), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(route_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_17 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_8 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_24 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_25 = and(vcalloc_q.io.enq.valid, _T_24) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_26, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_14, _out_bundle_bits_out_virt_channel_T_13) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_15 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_8( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_WIRE = {_route_buffer_io_enq_bits_flow_egress_node_id_T_3, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0) | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_2}}}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_WIRE == 4'h2; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_WIRE != 4'h2; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_107 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_107 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_107( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_107 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_414 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_158 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_414( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_158 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e5_s11_6 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e5_s11_6 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e5_s11_6 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<23>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<23>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11_12 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulAddRecFNPipe_l2_e5_s11_6( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [16:0] io_a, // @[FPU.scala:638:16] input [16:0] io_b, // @[FPU.scala:638:16] input [16:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [16:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [16:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [16:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [16:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [16:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [21:0] _mulAddResult_T = {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [22:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [6:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [13:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e5_s11_6 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e5_s11_6 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e5_s11_12 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_197 = shr(io.in.a.bits.source, 3) node _T_198 = eq(_T_197, UInt<3>(0h4)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_291 = shr(io.in.a.bits.source, 3) node _T_292 = eq(_T_291, UInt<3>(0h4)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_347 = shr(io.in.a.bits.source, 3) node _T_348 = eq(_T_347, UInt<3>(0h4)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_445 = shr(io.in.a.bits.source, 3) node _T_446 = eq(_T_445, UInt<3>(0h4)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_528 = shr(io.in.a.bits.source, 3) node _T_529 = eq(_T_528, UInt<3>(0h4)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_549 = and(_T_547, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_556) node _T_558 = and(_T_546, _T_557) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_558, UInt<1>(0h1), "") : assert_26 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(source_ok, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(is_aligned, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_568, UInt<1>(0h1), "") : assert_29 node _T_572 = eq(io.in.a.bits.mask, mask) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_572, UInt<1>(0h1), "") : assert_30 node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_576 : node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_35) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<1>(0h1)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_36) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_593 = shr(io.in.a.bits.source, 2) node _T_594 = eq(_T_593, UInt<2>(0h2)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_37) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_598 = and(_T_596, _T_597) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_599 = shr(io.in.a.bits.source, 2) node _T_600 = eq(_T_599, UInt<2>(0h3)) node _T_601 = leq(UInt<1>(0h0), uncommonBits_38) node _T_602 = and(_T_600, _T_601) node _T_603 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_604 = and(_T_602, _T_603) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_605 = shr(io.in.a.bits.source, 3) node _T_606 = eq(_T_605, UInt<3>(0h4)) node _T_607 = leq(UInt<1>(0h0), uncommonBits_39) node _T_608 = and(_T_606, _T_607) node _T_609 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_614 = or(_T_580, _T_586) node _T_615 = or(_T_614, _T_592) node _T_616 = or(_T_615, _T_598) node _T_617 = or(_T_616, _T_604) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_579, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = and(_T_627, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_635, UInt<1>(0h1), "") : assert_31 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(source_ok, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(is_aligned, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_645, UInt<1>(0h1), "") : assert_34 node _T_649 = not(mask) node _T_650 = and(io.in.a.bits.mask, _T_649) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_651, UInt<1>(0h1), "") : assert_35 node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_655 : node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_40) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h1)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_41) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h2)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_42) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h3)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_43) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_684 = shr(io.in.a.bits.source, 3) node _T_685 = eq(_T_684, UInt<3>(0h4)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_44) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_693 = or(_T_659, _T_665) node _T_694 = or(_T_693, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = and(_T_658, _T_700) node _T_702 = or(UInt<1>(0h0), _T_701) node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_705 = cvt(_T_704) node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000))) node _T_707 = asSInt(_T_706) node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0))) node _T_709 = and(_T_703, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = and(_T_702, _T_710) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_711, UInt<1>(0h1), "") : assert_36 node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(source_ok, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(is_aligned, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_721, UInt<1>(0h1), "") : assert_39 node _T_725 = eq(io.in.a.bits.mask, mask) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_725, UInt<1>(0h1), "") : assert_40 node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_729 : node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_45) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<1>(0h1)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_46) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<2>(0h2)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_47) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<2>(0h3)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_48) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_757 = and(_T_755, _T_756) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_758 = shr(io.in.a.bits.source, 3) node _T_759 = eq(_T_758, UInt<3>(0h4)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_49) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_763 = and(_T_761, _T_762) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_767 = or(_T_733, _T_739) node _T_768 = or(_T_767, _T_745) node _T_769 = or(_T_768, _T_751) node _T_770 = or(_T_769, _T_757) node _T_771 = or(_T_770, _T_763) node _T_772 = or(_T_771, _T_764) node _T_773 = or(_T_772, _T_765) node _T_774 = or(_T_773, _T_766) node _T_775 = and(_T_732, _T_774) node _T_776 = or(UInt<1>(0h0), _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_783) node _T_785 = and(_T_776, _T_784) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_785, UInt<1>(0h1), "") : assert_41 node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(source_ok, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(is_aligned, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_795, UInt<1>(0h1), "") : assert_44 node _T_799 = eq(io.in.a.bits.mask, mask) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_799, UInt<1>(0h1), "") : assert_45 node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_803 : node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_806 = and(_T_804, _T_805) node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<1>(0h0)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_50) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<1>(0h1)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_51) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<2>(0h2)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_52) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<2>(0h3)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_53) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_832 = shr(io.in.a.bits.source, 3) node _T_833 = eq(_T_832, UInt<3>(0h4)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_54) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_837 = and(_T_835, _T_836) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_841 = or(_T_807, _T_813) node _T_842 = or(_T_841, _T_819) node _T_843 = or(_T_842, _T_825) node _T_844 = or(_T_843, _T_831) node _T_845 = or(_T_844, _T_837) node _T_846 = or(_T_845, _T_838) node _T_847 = or(_T_846, _T_839) node _T_848 = or(_T_847, _T_840) node _T_849 = and(_T_806, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_852 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_853 = cvt(_T_852) node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000))) node _T_855 = asSInt(_T_854) node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0))) node _T_857 = and(_T_851, _T_856) node _T_858 = or(UInt<1>(0h0), _T_857) node _T_859 = and(_T_850, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_859, UInt<1>(0h1), "") : assert_46 node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(source_ok, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(is_aligned, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_869, UInt<1>(0h1), "") : assert_49 node _T_873 = eq(io.in.a.bits.mask, mask) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_873, UInt<1>(0h1), "") : assert_50 node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_877, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_881, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 3) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_885 : node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok_1, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_889, UInt<1>(0h1), "") : assert_54 node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_893, UInt<1>(0h1), "") : assert_55 node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_897, UInt<1>(0h1), "") : assert_56 node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_901, UInt<1>(0h1), "") : assert_57 node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_905 : node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok_1, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(sink_ok, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_912, UInt<1>(0h1), "") : assert_60 node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_916, UInt<1>(0h1), "") : assert_61 node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_920, UInt<1>(0h1), "") : assert_62 node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_924, UInt<1>(0h1), "") : assert_63 node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_929 = or(UInt<1>(0h0), _T_928) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_929, UInt<1>(0h1), "") : assert_64 node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_933 : node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(source_ok_1, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(sink_ok, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_940, UInt<1>(0h1), "") : assert_67 node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_944, UInt<1>(0h1), "") : assert_68 node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_948, UInt<1>(0h1), "") : assert_69 node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_953 = or(_T_952, io.in.d.bits.corrupt) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_953, UInt<1>(0h1), "") : assert_70 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = or(UInt<1>(0h0), _T_957) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_958, UInt<1>(0h1), "") : assert_71 node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_962 : node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(source_ok_1, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_966, UInt<1>(0h1), "") : assert_73 node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_970, UInt<1>(0h1), "") : assert_74 node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_975, UInt<1>(0h1), "") : assert_75 node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_979 : node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok_1, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_983, UInt<1>(0h1), "") : assert_77 node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_988 = or(_T_987, io.in.d.bits.corrupt) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_988, UInt<1>(0h1), "") : assert_78 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(UInt<1>(0h0), _T_992) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_993, UInt<1>(0h1), "") : assert_79 node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_997 : node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(source_ok_1, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81 node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82 node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1010 = or(UInt<1>(0h0), _T_1009) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1026 = eq(a_first, UInt<1>(0h0)) node _T_1027 = and(io.in.a.valid, _T_1026) when _T_1027 : node _T_1028 = eq(io.in.a.bits.opcode, opcode) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87 node _T_1032 = eq(io.in.a.bits.param, param) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88 node _T_1036 = eq(io.in.a.bits.size, size) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89 node _T_1040 = eq(io.in.a.bits.source, source) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90 node _T_1044 = eq(io.in.a.bits.address, address) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91 node _T_1048 = and(io.in.a.ready, io.in.a.valid) node _T_1049 = and(_T_1048, a_first) when _T_1049 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1050 = eq(d_first, UInt<1>(0h0)) node _T_1051 = and(io.in.d.valid, _T_1050) when _T_1051 : node _T_1052 = eq(io.in.d.bits.opcode, opcode_1) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92 node _T_1056 = eq(io.in.d.bits.param, param_1) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93 node _T_1060 = eq(io.in.d.bits.size, size_1) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94 node _T_1064 = eq(io.in.d.bits.source, source_1) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95 node _T_1068 = eq(io.in.d.bits.sink, sink) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96 node _T_1072 = eq(io.in.d.bits.denied, denied) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97 node _T_1076 = and(io.in.d.ready, io.in.d.valid) node _T_1077 = and(_T_1076, d_first) when _T_1077 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1078 = and(io.in.a.valid, a_first_1) node _T_1079 = and(_T_1078, UInt<1>(0h1)) when _T_1079 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1080 = and(io.in.a.ready, io.in.a.valid) node _T_1081 = and(_T_1080, a_first_1) node _T_1082 = and(_T_1081, UInt<1>(0h1)) when _T_1082 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1083 = dshr(inflight, io.in.a.bits.source) node _T_1084 = bits(_T_1083, 0, 0) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(_T_1085, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1089 = and(io.in.d.valid, d_first_1) node _T_1090 = and(_T_1089, UInt<1>(0h1)) node _T_1091 = eq(d_release_ack, UInt<1>(0h0)) node _T_1092 = and(_T_1090, _T_1091) when _T_1092 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1093 = and(io.in.d.ready, io.in.d.valid) node _T_1094 = and(_T_1093, d_first_1) node _T_1095 = and(_T_1094, UInt<1>(0h1)) node _T_1096 = eq(d_release_ack, UInt<1>(0h0)) node _T_1097 = and(_T_1095, _T_1096) when _T_1097 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1098 = and(io.in.d.valid, d_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) node _T_1100 = eq(d_release_ack, UInt<1>(0h0)) node _T_1101 = and(_T_1099, _T_1100) when _T_1101 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1102 = dshr(inflight, io.in.d.bits.source) node _T_1103 = bits(_T_1102, 0, 0) node _T_1104 = or(_T_1103, same_cycle_resp) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1110 = or(_T_1108, _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100 node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101 else : node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1120 = or(_T_1118, _T_1119) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102 node _T_1124 = eq(io.in.d.bits.size, a_size_lookup) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103 node _T_1128 = and(io.in.d.valid, d_first_1) node _T_1129 = and(_T_1128, a_first_1) node _T_1130 = and(_T_1129, io.in.a.valid) node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1132 = and(_T_1130, _T_1131) node _T_1133 = eq(d_release_ack, UInt<1>(0h0)) node _T_1134 = and(_T_1132, _T_1133) when _T_1134 : node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.a.ready) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_54 node _T_1140 = orr(inflight) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1143 = or(_T_1141, _T_1142) node _T_1144 = lt(watchdog, plusarg_reader.out) node _T_1145 = or(_T_1143, _T_1144) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(io.in.d.ready, io.in.d.valid) node _T_1151 = or(_T_1149, _T_1150) when _T_1151 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1152 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1153 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1154 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = and(_T_1152, _T_1155) when _T_1156 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1157 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1158 = and(_T_1157, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1159 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1160 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = and(_T_1158, _T_1161) when _T_1162 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1163 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1164 = bits(_T_1163, 0, 0) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1169 = and(io.in.d.valid, d_first_2) node _T_1170 = and(_T_1169, UInt<1>(0h1)) node _T_1171 = and(_T_1170, d_release_ack_1) when _T_1171 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1172 = and(io.in.d.ready, io.in.d.valid) node _T_1173 = and(_T_1172, d_first_2) node _T_1174 = and(_T_1173, UInt<1>(0h1)) node _T_1175 = and(_T_1174, d_release_ack_1) when _T_1175 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1176 = and(io.in.d.valid, d_first_2) node _T_1177 = and(_T_1176, UInt<1>(0h1)) node _T_1178 = and(_T_1177, d_release_ack_1) when _T_1178 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1179 = dshr(inflight_1, io.in.d.bits.source) node _T_1180 = bits(_T_1179, 0, 0) node _T_1181 = or(_T_1180, same_cycle_resp_1) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1185 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_108 else : node _T_1189 = eq(io.in.d.bits.size, c_size_lookup) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_109 node _T_1193 = and(io.in.d.valid, d_first_2) node _T_1194 = and(_T_1193, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1195 = and(_T_1194, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1196 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = and(_T_1197, d_release_ack_1) node _T_1199 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1202 = or(_T_1201, _WIRE_27.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_55 node _T_1206 = orr(inflight_1) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) node _T_1208 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1209 = or(_T_1207, _T_1208) node _T_1210 = lt(watchdog_1, plusarg_reader_1.out) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1215 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1216 = and(io.in.d.ready, io.in.d.valid) node _T_1217 = or(_T_1215, _T_1216) when _T_1217 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_99 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_99( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_76 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_76( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_155 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_172 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_155( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_172 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_5 : output auto : { flip rerocc_tile_ctrl_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rerocc_tile_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip rerocc_tile_re_ro_cc_in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, flip rerocc_tile_rerocc_manager_id_sink_in : UInt<7>, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst rerocc_tile of ReRoCCManagerTile_3 connect rerocc_tile.clock, childClock connect rerocc_tile.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect rerocc_tile.auto.rerocc_manager_id_sink_in, auto.rerocc_tile_rerocc_manager_id_sink_in connect rerocc_tile.auto.re_ro_cc_in, auto.rerocc_tile_re_ro_cc_in connect auto.rerocc_tile_buffer_out.e.bits, rerocc_tile.auto.buffer_out.e.bits connect auto.rerocc_tile_buffer_out.e.valid, rerocc_tile.auto.buffer_out.e.valid connect rerocc_tile.auto.buffer_out.e.ready, auto.rerocc_tile_buffer_out.e.ready connect rerocc_tile.auto.buffer_out.d, auto.rerocc_tile_buffer_out.d connect auto.rerocc_tile_buffer_out.c.bits, rerocc_tile.auto.buffer_out.c.bits connect auto.rerocc_tile_buffer_out.c.valid, rerocc_tile.auto.buffer_out.c.valid connect rerocc_tile.auto.buffer_out.c.ready, auto.rerocc_tile_buffer_out.c.ready connect rerocc_tile.auto.buffer_out.b, auto.rerocc_tile_buffer_out.b connect auto.rerocc_tile_buffer_out.a.bits, rerocc_tile.auto.buffer_out.a.bits connect auto.rerocc_tile_buffer_out.a.valid, rerocc_tile.auto.buffer_out.a.valid connect rerocc_tile.auto.buffer_out.a.ready, auto.rerocc_tile_buffer_out.a.ready connect rerocc_tile.auto.ctrl_ctrl_in, auto.rerocc_tile_ctrl_ctrl_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset

module ClockSinkDomain_5( // @[ClockDomain.scala:14:9] output auto_rerocc_tile_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_rerocc_tile_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_rerocc_tile_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire auto_rerocc_tile_ctrl_ctrl_in_a_valid_0 = auto_rerocc_tile_ctrl_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_ready_0 = auto_rerocc_tile_ctrl_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_ready_0 = auto_rerocc_tile_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_valid_0 = auto_rerocc_tile_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode_0 = auto_rerocc_tile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_b_bits_param_0 = auto_rerocc_tile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_b_bits_size_0 = auto_rerocc_tile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_source_0 = auto_rerocc_tile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_b_bits_address_0 = auto_rerocc_tile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_b_bits_mask_0 = auto_rerocc_tile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_b_bits_data_0 = auto_rerocc_tile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_corrupt_0 = auto_rerocc_tile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_ready_0 = auto_rerocc_tile_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_valid_0 = auto_rerocc_tile_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode_0 = auto_rerocc_tile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_d_bits_param_0 = auto_rerocc_tile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_d_bits_size_0 = auto_rerocc_tile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_source_0 = auto_rerocc_tile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_sink_0 = auto_rerocc_tile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_denied_0 = auto_rerocc_tile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_d_bits_data_0 = auto_rerocc_tile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_corrupt_0 = auto_rerocc_tile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_ready_0 = auto_rerocc_tile_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_valid_0 = auto_rerocc_tile_re_ro_cc_in_req_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_opcode; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_client_id; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_ready_0 = auto_rerocc_tile_re_ro_cc_in_resp_ready; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in_0 = auto_rerocc_tile_rerocc_manager_id_sink_in; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] ReRoCCManagerTile_3 rerocc_tile ( // @[Integration.scala:45:54] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrl_ctrl_in_a_ready (auto_rerocc_tile_ctrl_ctrl_in_a_ready_0), .auto_ctrl_ctrl_in_a_valid (auto_rerocc_tile_ctrl_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_param (auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_size (auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_source (auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_address (auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_mask (auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_data (auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_corrupt (auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_ready (auto_rerocc_tile_ctrl_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_valid (auto_rerocc_tile_ctrl_ctrl_in_d_valid_0), .auto_ctrl_ctrl_in_d_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0), .auto_ctrl_ctrl_in_d_bits_size (auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0), .auto_ctrl_ctrl_in_d_bits_source (auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0), .auto_ctrl_ctrl_in_d_bits_data (auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0), .auto_buffer_out_a_ready (auto_rerocc_tile_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_rerocc_tile_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_rerocc_tile_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_rerocc_tile_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_rerocc_tile_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_rerocc_tile_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_rerocc_tile_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_rerocc_tile_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_rerocc_tile_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_rerocc_tile_buffer_out_a_bits_corrupt_0), .auto_buffer_out_b_ready (auto_rerocc_tile_buffer_out_b_ready_0), .auto_buffer_out_b_valid (auto_rerocc_tile_buffer_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (auto_rerocc_tile_buffer_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (auto_rerocc_tile_buffer_out_b_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (auto_rerocc_tile_buffer_out_b_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (auto_rerocc_tile_buffer_out_b_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (auto_rerocc_tile_buffer_out_b_bits_address_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (auto_rerocc_tile_buffer_out_b_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (auto_rerocc_tile_buffer_out_b_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (auto_rerocc_tile_buffer_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (auto_rerocc_tile_buffer_out_c_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (auto_rerocc_tile_buffer_out_c_valid_0), .auto_buffer_out_c_bits_opcode (auto_rerocc_tile_buffer_out_c_bits_opcode_0), .auto_buffer_out_c_bits_param (auto_rerocc_tile_buffer_out_c_bits_param_0), .auto_buffer_out_c_bits_size (auto_rerocc_tile_buffer_out_c_bits_size_0), .auto_buffer_out_c_bits_source (auto_rerocc_tile_buffer_out_c_bits_source_0), .auto_buffer_out_c_bits_address (auto_rerocc_tile_buffer_out_c_bits_address_0), .auto_buffer_out_c_bits_data (auto_rerocc_tile_buffer_out_c_bits_data_0), .auto_buffer_out_c_bits_corrupt (auto_rerocc_tile_buffer_out_c_bits_corrupt_0), .auto_buffer_out_d_ready (auto_rerocc_tile_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_rerocc_tile_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_rerocc_tile_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (auto_rerocc_tile_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_rerocc_tile_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_rerocc_tile_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (auto_rerocc_tile_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (auto_rerocc_tile_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_rerocc_tile_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (auto_rerocc_tile_buffer_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (auto_rerocc_tile_buffer_out_e_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (auto_rerocc_tile_buffer_out_e_valid_0), .auto_buffer_out_e_bits_sink (auto_rerocc_tile_buffer_out_e_bits_sink_0), .auto_re_ro_cc_in_req_ready (auto_rerocc_tile_re_ro_cc_in_req_ready_0), .auto_re_ro_cc_in_req_valid (auto_rerocc_tile_re_ro_cc_in_req_valid_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_opcode (auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_client_id (auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_data (auto_rerocc_tile_re_ro_cc_in_req_bits_data_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_ready (auto_rerocc_tile_re_ro_cc_in_resp_ready_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_valid (auto_rerocc_tile_re_ro_cc_in_resp_valid_0), .auto_re_ro_cc_in_resp_bits_opcode (auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0), .auto_re_ro_cc_in_resp_bits_client_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0), .auto_re_ro_cc_in_resp_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0), .auto_re_ro_cc_in_resp_bits_data (auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0), .auto_rerocc_manager_id_sink_in (auto_rerocc_tile_rerocc_manager_id_sink_in_0) // @[ClockDomain.scala:14:9] ); // @[Integration.scala:45:54] assign auto_rerocc_tile_ctrl_ctrl_in_a_ready = auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_valid = auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode = auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_size = auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_source = auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_data = auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_valid = auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_opcode = auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_param = auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_size = auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_source = auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_address = auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_mask = auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_data = auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_corrupt = auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_b_ready = auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_valid = auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_opcode = auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_param = auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_size = auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_source = auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_address = auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_data = auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_corrupt = auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_d_ready = auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_valid = auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_bits_sink = auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_req_ready = auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_valid = auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode = auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_data = auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<14>(0h2000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<17>(0h10000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<18>(0h2f000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<27>(0h4000000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<13>(0h1000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<19>(0h40000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_144, _T_149) node _T_181 = or(_T_180, _T_154) node _T_182 = or(_T_181, _T_159) node _T_183 = or(_T_182, _T_164) node _T_184 = or(_T_183, _T_169) node _T_185 = or(_T_184, _T_174) node _T_186 = or(_T_185, _T_179) node _T_187 = and(_T_139, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_138, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_189, UInt<1>(0h1), "") : assert_2 node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_195 = and(_T_193, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<14>(0h2000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<13>(0h1000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<17>(0h10000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<18>(0h2f000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<17>(0h10000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<27>(0h4000000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<19>(0h40000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_201, _T_206) node _T_238 = or(_T_237, _T_211) node _T_239 = or(_T_238, _T_216) node _T_240 = or(_T_239, _T_221) node _T_241 = or(_T_240, _T_226) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_236) node _T_244 = and(_T_196, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = and(UInt<1>(0h0), _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_246, UInt<1>(0h1), "") : assert_3 node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(source_ok, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_253 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_253, UInt<1>(0h1), "") : assert_5 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(is_aligned, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_260 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_260, UInt<1>(0h1), "") : assert_7 node _T_264 = not(io.in.a.bits.mask) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_265, UInt<1>(0h1), "") : assert_8 node _T_269 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_269, UInt<1>(0h1), "") : assert_9 node _T_273 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h0)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_8) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h1)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_9) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h2)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_10) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h3)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_11) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_305 = or(_T_277, _T_283) node _T_306 = or(_T_305, _T_289) node _T_307 = or(_T_306, _T_295) node _T_308 = or(_T_307, _T_301) node _T_309 = or(_T_308, _T_302) node _T_310 = or(_T_309, _T_303) node _T_311 = or(_T_310, _T_304) node _T_312 = and(_T_276, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_315 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<14>(0h2000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<13>(0h1000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<17>(0h10000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<18>(0h2f000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<17>(0h10000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<27>(0h4000000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<19>(0h40000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = or(_T_319, _T_324) node _T_356 = or(_T_355, _T_329) node _T_357 = or(_T_356, _T_334) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_344) node _T_360 = or(_T_359, _T_349) node _T_361 = or(_T_360, _T_354) node _T_362 = and(_T_314, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = and(_T_313, _T_363) node _T_365 = asUInt(reset) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(_T_364, UInt<1>(0h0)) when _T_367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_364, UInt<1>(0h1), "") : assert_10 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<14>(0h2000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<13>(0h1000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<18>(0h2f000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<19>(0h40000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_376, _T_381) node _T_413 = or(_T_412, _T_386) node _T_414 = or(_T_413, _T_391) node _T_415 = or(_T_414, _T_396) node _T_416 = or(_T_415, _T_401) node _T_417 = or(_T_416, _T_406) node _T_418 = or(_T_417, _T_411) node _T_419 = and(_T_371, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = and(UInt<1>(0h0), _T_420) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_421, UInt<1>(0h1), "") : assert_11 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(source_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_428 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_428, UInt<1>(0h1), "") : assert_13 node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(is_aligned, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_435 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_435, UInt<1>(0h1), "") : assert_15 node _T_439 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_439, UInt<1>(0h1), "") : assert_16 node _T_443 = not(io.in.a.bits.mask) node _T_444 = eq(_T_443, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_444, UInt<1>(0h1), "") : assert_17 node _T_448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_448, UInt<1>(0h1), "") : assert_18 node _T_452 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_452 : node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<1>(0h0)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_12) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<1>(0h1)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_13) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_469 = shr(io.in.a.bits.source, 2) node _T_470 = eq(_T_469, UInt<2>(0h2)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_14) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_474 = and(_T_472, _T_473) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_475 = shr(io.in.a.bits.source, 2) node _T_476 = eq(_T_475, UInt<2>(0h3)) node _T_477 = leq(UInt<1>(0h0), uncommonBits_15) node _T_478 = and(_T_476, _T_477) node _T_479 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_484 = or(_T_456, _T_462) node _T_485 = or(_T_484, _T_468) node _T_486 = or(_T_485, _T_474) node _T_487 = or(_T_486, _T_480) node _T_488 = or(_T_487, _T_481) node _T_489 = or(_T_488, _T_482) node _T_490 = or(_T_489, _T_483) node _T_491 = and(_T_455, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_492, UInt<1>(0h1), "") : assert_19 node _T_496 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_497 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_498 = and(_T_496, _T_497) node _T_499 = or(UInt<1>(0h0), _T_498) node _T_500 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = and(_T_499, _T_504) node _T_506 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_507 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_508 = and(_T_506, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<14>(0h2000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<17>(0h10000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<18>(0h2f000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<17>(0h10000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_531 = cvt(_T_530) node _T_532 = and(_T_531, asSInt(UInt<27>(0h4000000))) node _T_533 = asSInt(_T_532) node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0))) node _T_535 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<13>(0h1000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<19>(0h40000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = or(_T_514, _T_519) node _T_546 = or(_T_545, _T_524) node _T_547 = or(_T_546, _T_529) node _T_548 = or(_T_547, _T_534) node _T_549 = or(_T_548, _T_539) node _T_550 = or(_T_549, _T_544) node _T_551 = and(_T_509, _T_550) node _T_552 = or(UInt<1>(0h0), _T_505) node _T_553 = or(_T_552, _T_551) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_553, UInt<1>(0h1), "") : assert_20 node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(source_ok, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(is_aligned, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_563 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_563, UInt<1>(0h1), "") : assert_23 node _T_567 = eq(io.in.a.bits.mask, mask) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_567, UInt<1>(0h1), "") : assert_24 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_571, UInt<1>(0h1), "") : assert_25 node _T_575 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h0)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_16) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h1)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_17) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h2)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_18) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h3)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_19) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_607 = or(_T_579, _T_585) node _T_608 = or(_T_607, _T_591) node _T_609 = or(_T_608, _T_597) node _T_610 = or(_T_609, _T_603) node _T_611 = or(_T_610, _T_604) node _T_612 = or(_T_611, _T_605) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_578, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<27>(0h4000000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<13>(0h1000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<19>(0h40000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_634, _T_639) node _T_661 = or(_T_660, _T_644) node _T_662 = or(_T_661, _T_649) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_659) node _T_665 = and(_T_629, _T_664) node _T_666 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_625) node _T_674 = or(_T_673, _T_665) node _T_675 = or(_T_674, _T_672) node _T_676 = and(_T_615, _T_675) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_676, UInt<1>(0h1), "") : assert_26 node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(source_ok, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(is_aligned, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_686 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_686, UInt<1>(0h1), "") : assert_29 node _T_690 = eq(io.in.a.bits.mask, mask) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_690, UInt<1>(0h1), "") : assert_30 node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_699 = shr(io.in.a.bits.source, 2) node _T_700 = eq(_T_699, UInt<1>(0h0)) node _T_701 = leq(UInt<1>(0h0), uncommonBits_20) node _T_702 = and(_T_700, _T_701) node _T_703 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_704 = and(_T_702, _T_703) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_705 = shr(io.in.a.bits.source, 2) node _T_706 = eq(_T_705, UInt<1>(0h1)) node _T_707 = leq(UInt<1>(0h0), uncommonBits_21) node _T_708 = and(_T_706, _T_707) node _T_709 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_710 = and(_T_708, _T_709) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_711 = shr(io.in.a.bits.source, 2) node _T_712 = eq(_T_711, UInt<2>(0h2)) node _T_713 = leq(UInt<1>(0h0), uncommonBits_22) node _T_714 = and(_T_712, _T_713) node _T_715 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_716 = and(_T_714, _T_715) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_717 = shr(io.in.a.bits.source, 2) node _T_718 = eq(_T_717, UInt<2>(0h3)) node _T_719 = leq(UInt<1>(0h0), uncommonBits_23) node _T_720 = and(_T_718, _T_719) node _T_721 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_722 = and(_T_720, _T_721) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_726 = or(_T_698, _T_704) node _T_727 = or(_T_726, _T_710) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = and(_T_697, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_736 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_737 = and(_T_735, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = and(_T_738, _T_743) node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<14>(0h2000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<18>(0h2f000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<27>(0h4000000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<13>(0h1000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<19>(0h40000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = or(_T_753, _T_758) node _T_780 = or(_T_779, _T_763) node _T_781 = or(_T_780, _T_768) node _T_782 = or(_T_781, _T_773) node _T_783 = or(_T_782, _T_778) node _T_784 = and(_T_748, _T_783) node _T_785 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_786 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = and(_T_785, _T_790) node _T_792 = or(UInt<1>(0h0), _T_744) node _T_793 = or(_T_792, _T_784) node _T_794 = or(_T_793, _T_791) node _T_795 = and(_T_734, _T_794) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_795, UInt<1>(0h1), "") : assert_31 node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(source_ok, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(is_aligned, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_805 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_805, UInt<1>(0h1), "") : assert_34 node _T_809 = not(mask) node _T_810 = and(io.in.a.bits.mask, _T_809) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_811, UInt<1>(0h1), "") : assert_35 node _T_815 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_815 : node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h0)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_24) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h1)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_25) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h2)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_26) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_838 = shr(io.in.a.bits.source, 2) node _T_839 = eq(_T_838, UInt<2>(0h3)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_27) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_819, _T_825) node _T_848 = or(_T_847, _T_831) node _T_849 = or(_T_848, _T_837) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = and(_T_818, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<15>(0h5000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<13>(0h1000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = or(_T_864, _T_869) node _T_871 = and(_T_859, _T_870) node _T_872 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<18>(0h2f000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<17>(0h10000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<27>(0h4000000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_899 = cvt(_T_898) node _T_900 = and(_T_899, asSInt(UInt<19>(0h40000))) node _T_901 = asSInt(_T_900) node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0))) node _T_903 = or(_T_877, _T_882) node _T_904 = or(_T_903, _T_887) node _T_905 = or(_T_904, _T_892) node _T_906 = or(_T_905, _T_897) node _T_907 = or(_T_906, _T_902) node _T_908 = and(_T_872, _T_907) node _T_909 = or(UInt<1>(0h0), _T_871) node _T_910 = or(_T_909, _T_908) node _T_911 = and(_T_855, _T_910) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_911, UInt<1>(0h1), "") : assert_36 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(source_ok, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(is_aligned, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_921 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_921, UInt<1>(0h1), "") : assert_39 node _T_925 = eq(io.in.a.bits.mask, mask) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_925, UInt<1>(0h1), "") : assert_40 node _T_929 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_929 : node _T_930 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_931 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_932 = and(_T_930, _T_931) node _T_933 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_934 = shr(io.in.a.bits.source, 2) node _T_935 = eq(_T_934, UInt<1>(0h0)) node _T_936 = leq(UInt<1>(0h0), uncommonBits_28) node _T_937 = and(_T_935, _T_936) node _T_938 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_939 = and(_T_937, _T_938) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<1>(0h1)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_29) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<2>(0h2)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_30) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<2>(0h3)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_31) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_961 = or(_T_933, _T_939) node _T_962 = or(_T_961, _T_945) node _T_963 = or(_T_962, _T_951) node _T_964 = or(_T_963, _T_957) node _T_965 = or(_T_964, _T_958) node _T_966 = or(_T_965, _T_959) node _T_967 = or(_T_966, _T_960) node _T_968 = and(_T_932, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_971 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_972 = and(_T_970, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_975 = cvt(_T_974) node _T_976 = and(_T_975, asSInt(UInt<15>(0h5000))) node _T_977 = asSInt(_T_976) node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0))) node _T_979 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<13>(0h1000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = or(_T_978, _T_983) node _T_985 = and(_T_973, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<13>(0h1000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<27>(0h4000000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<19>(0h40000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = or(_T_991, _T_996) node _T_1018 = or(_T_1017, _T_1001) node _T_1019 = or(_T_1018, _T_1006) node _T_1020 = or(_T_1019, _T_1011) node _T_1021 = or(_T_1020, _T_1016) node _T_1022 = and(_T_986, _T_1021) node _T_1023 = or(UInt<1>(0h0), _T_985) node _T_1024 = or(_T_1023, _T_1022) node _T_1025 = and(_T_969, _T_1024) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_41 node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(source_ok, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(is_aligned, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1035 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_44 node _T_1039 = eq(io.in.a.bits.mask, mask) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_45 node _T_1043 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1043 : node _T_1044 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1045 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1048 = shr(io.in.a.bits.source, 2) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) node _T_1050 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1053 = and(_T_1051, _T_1052) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<1>(0h1)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<2>(0h2)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1066 = shr(io.in.a.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<2>(0h3)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1075 = or(_T_1047, _T_1053) node _T_1076 = or(_T_1075, _T_1059) node _T_1077 = or(_T_1076, _T_1065) node _T_1078 = or(_T_1077, _T_1071) node _T_1079 = or(_T_1078, _T_1072) node _T_1080 = or(_T_1079, _T_1073) node _T_1081 = or(_T_1080, _T_1074) node _T_1082 = and(_T_1046, _T_1081) node _T_1083 = or(UInt<1>(0h0), _T_1082) node _T_1084 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1085 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = or(UInt<1>(0h0), _T_1086) node _T_1088 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1089 = cvt(_T_1088) node _T_1090 = and(_T_1089, asSInt(UInt<13>(0h1000))) node _T_1091 = asSInt(_T_1090) node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = and(_T_1087, _T_1092) node _T_1094 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1096 = cvt(_T_1095) node _T_1097 = and(_T_1096, asSInt(UInt<14>(0h2000))) node _T_1098 = asSInt(_T_1097) node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0))) node _T_1100 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1101 = cvt(_T_1100) node _T_1102 = and(_T_1101, asSInt(UInt<17>(0h10000))) node _T_1103 = asSInt(_T_1102) node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0))) node _T_1105 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1106 = cvt(_T_1105) node _T_1107 = and(_T_1106, asSInt(UInt<18>(0h2f000))) node _T_1108 = asSInt(_T_1107) node _T_1109 = eq(_T_1108, asSInt(UInt<1>(0h0))) node _T_1110 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1111 = cvt(_T_1110) node _T_1112 = and(_T_1111, asSInt(UInt<17>(0h10000))) node _T_1113 = asSInt(_T_1112) node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1116 = cvt(_T_1115) node _T_1117 = and(_T_1116, asSInt(UInt<27>(0h4000000))) node _T_1118 = asSInt(_T_1117) node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0))) node _T_1120 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1121 = cvt(_T_1120) node _T_1122 = and(_T_1121, asSInt(UInt<13>(0h1000))) node _T_1123 = asSInt(_T_1122) node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0))) node _T_1125 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<19>(0h40000))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1099, _T_1104) node _T_1131 = or(_T_1130, _T_1109) node _T_1132 = or(_T_1131, _T_1114) node _T_1133 = or(_T_1132, _T_1119) node _T_1134 = or(_T_1133, _T_1124) node _T_1135 = or(_T_1134, _T_1129) node _T_1136 = and(_T_1094, _T_1135) node _T_1137 = or(UInt<1>(0h0), _T_1093) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = and(_T_1083, _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_46 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(source_ok, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(is_aligned, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1149 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_49 node _T_1153 = eq(io.in.a.bits.mask, mask) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_50 node _T_1157 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1161 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1165 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1165 : node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok_1, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1169 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_54 node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_55 node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_56 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_57 node _T_1185 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1185 : node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(source_ok_1, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(sink_ok, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1192 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_60 node _T_1196 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_61 node _T_1200 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_62 node _T_1204 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_63 node _T_1208 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1209 = or(UInt<1>(0h1), _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_64 node _T_1213 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1213 : node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(source_ok_1, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(sink_ok, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1220 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_67 node _T_1224 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_68 node _T_1228 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_69 node _T_1232 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1233 = or(_T_1232, io.in.d.bits.corrupt) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_70 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_71 node _T_1242 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1242 : node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(source_ok_1, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1246 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_73 node _T_1250 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_74 node _T_1254 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1255 = or(UInt<1>(0h1), _T_1254) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_75 node _T_1259 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1259 : node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(source_ok_1, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1263 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_77 node _T_1267 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1268 = or(_T_1267, io.in.d.bits.corrupt) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_78 node _T_1272 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1273 = or(UInt<1>(0h1), _T_1272) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_79 node _T_1277 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1277 : node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(source_ok_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1281 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_81 node _T_1285 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_82 node _T_1289 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1290 = or(UInt<1>(0h1), _T_1289) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1294 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1298 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1302 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(_T_1302, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1302, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1306 = eq(a_first, UInt<1>(0h0)) node _T_1307 = and(io.in.a.valid, _T_1306) when _T_1307 : node _T_1308 = eq(io.in.a.bits.opcode, opcode) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_87 node _T_1312 = eq(io.in.a.bits.param, param) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_88 node _T_1316 = eq(io.in.a.bits.size, size) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_89 node _T_1320 = eq(io.in.a.bits.source, source) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_90 node _T_1324 = eq(io.in.a.bits.address, address) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_91 node _T_1328 = and(io.in.a.ready, io.in.a.valid) node _T_1329 = and(_T_1328, a_first) when _T_1329 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1330 = eq(d_first, UInt<1>(0h0)) node _T_1331 = and(io.in.d.valid, _T_1330) when _T_1331 : node _T_1332 = eq(io.in.d.bits.opcode, opcode_1) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92 node _T_1336 = eq(io.in.d.bits.param, param_1) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_93 node _T_1340 = eq(io.in.d.bits.size, size_1) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_94 node _T_1344 = eq(io.in.d.bits.source, source_1) node _T_1345 = asUInt(reset) node _T_1346 = eq(_T_1345, UInt<1>(0h0)) when _T_1346 : node _T_1347 = eq(_T_1344, UInt<1>(0h0)) when _T_1347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1344, UInt<1>(0h1), "") : assert_95 node _T_1348 = eq(io.in.d.bits.sink, sink) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_96 node _T_1352 = eq(io.in.d.bits.denied, denied) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_97 node _T_1356 = and(io.in.d.ready, io.in.d.valid) node _T_1357 = and(_T_1356, d_first) when _T_1357 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1358 = and(io.in.a.valid, a_first_1) node _T_1359 = and(_T_1358, UInt<1>(0h1)) when _T_1359 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1360 = and(io.in.a.ready, io.in.a.valid) node _T_1361 = and(_T_1360, a_first_1) node _T_1362 = and(_T_1361, UInt<1>(0h1)) when _T_1362 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1363 = dshr(inflight, io.in.a.bits.source) node _T_1364 = bits(_T_1363, 0, 0) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1369 = and(io.in.d.valid, d_first_1) node _T_1370 = and(_T_1369, UInt<1>(0h1)) node _T_1371 = eq(d_release_ack, UInt<1>(0h0)) node _T_1372 = and(_T_1370, _T_1371) when _T_1372 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1373 = and(io.in.d.ready, io.in.d.valid) node _T_1374 = and(_T_1373, d_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) node _T_1376 = eq(d_release_ack, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1378 = and(io.in.d.valid, d_first_1) node _T_1379 = and(_T_1378, UInt<1>(0h1)) node _T_1380 = eq(d_release_ack, UInt<1>(0h0)) node _T_1381 = and(_T_1379, _T_1380) when _T_1381 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1382 = dshr(inflight, io.in.d.bits.source) node _T_1383 = bits(_T_1382, 0, 0) node _T_1384 = or(_T_1383, same_cycle_resp) node _T_1385 = asUInt(reset) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(_T_1384, UInt<1>(0h0)) when _T_1387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1384, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1388 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1389 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1390 = or(_T_1388, _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_100 node _T_1394 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_101 else : node _T_1398 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1399 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_102 node _T_1404 = eq(io.in.d.bits.size, a_size_lookup) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_103 node _T_1408 = and(io.in.d.valid, d_first_1) node _T_1409 = and(_T_1408, a_first_1) node _T_1410 = and(_T_1409, io.in.a.valid) node _T_1411 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1412 = and(_T_1410, _T_1411) node _T_1413 = eq(d_release_ack, UInt<1>(0h0)) node _T_1414 = and(_T_1412, _T_1413) when _T_1414 : node _T_1415 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1416 = or(_T_1415, io.in.a.ready) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_36 node _T_1420 = orr(inflight) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) node _T_1422 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1423 = or(_T_1421, _T_1422) node _T_1424 = lt(watchdog, plusarg_reader.out) node _T_1425 = or(_T_1423, _T_1424) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1429 = and(io.in.a.ready, io.in.a.valid) node _T_1430 = and(io.in.d.ready, io.in.d.valid) node _T_1431 = or(_T_1429, _T_1430) when _T_1431 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1432 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1433 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1434 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1435 = and(_T_1433, _T_1434) node _T_1436 = and(_T_1432, _T_1435) when _T_1436 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1437 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1438 = and(_T_1437, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1439 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1440 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1441 = and(_T_1439, _T_1440) node _T_1442 = and(_T_1438, _T_1441) when _T_1442 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1443 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1444 = bits(_T_1443, 0, 0) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1449 = and(io.in.d.valid, d_first_2) node _T_1450 = and(_T_1449, UInt<1>(0h1)) node _T_1451 = and(_T_1450, d_release_ack_1) when _T_1451 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1452 = and(io.in.d.ready, io.in.d.valid) node _T_1453 = and(_T_1452, d_first_2) node _T_1454 = and(_T_1453, UInt<1>(0h1)) node _T_1455 = and(_T_1454, d_release_ack_1) when _T_1455 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1456 = and(io.in.d.valid, d_first_2) node _T_1457 = and(_T_1456, UInt<1>(0h1)) node _T_1458 = and(_T_1457, d_release_ack_1) when _T_1458 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1459 = dshr(inflight_1, io.in.d.bits.source) node _T_1460 = bits(_T_1459, 0, 0) node _T_1461 = or(_T_1460, same_cycle_resp_1) node _T_1462 = asUInt(reset) node _T_1463 = eq(_T_1462, UInt<1>(0h0)) when _T_1463 : node _T_1464 = eq(_T_1461, UInt<1>(0h0)) when _T_1464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1461, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1465 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1466 = asUInt(reset) node _T_1467 = eq(_T_1466, UInt<1>(0h0)) when _T_1467 : node _T_1468 = eq(_T_1465, UInt<1>(0h0)) when _T_1468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1465, UInt<1>(0h1), "") : assert_108 else : node _T_1469 = eq(io.in.d.bits.size, c_size_lookup) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_109 node _T_1473 = and(io.in.d.valid, d_first_2) node _T_1474 = and(_T_1473, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1475 = and(_T_1474, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1476 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1477 = and(_T_1475, _T_1476) node _T_1478 = and(_T_1477, d_release_ack_1) node _T_1479 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1480 = and(_T_1478, _T_1479) when _T_1480 : node _T_1481 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1482 = or(_T_1481, _WIRE_23.ready) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_37 node _T_1486 = orr(inflight_1) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) node _T_1488 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1489 = or(_T_1487, _T_1488) node _T_1490 = lt(watchdog_1, plusarg_reader_1.out) node _T_1491 = or(_T_1489, _T_1490) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1495 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1496 = and(io.in.d.ready, io.in.d.valid) node _T_1497 = or(_T_1495, _T_1496) when _T_1497 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1429 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1429; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1429; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1497 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1497; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1497; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1497; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1362 = _T_1429 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1362 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1362 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1362 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1362 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1362 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1408 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1408 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1377 = _T_1497 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1377 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1377 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1377 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1473 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1473 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1455 = _T_1497 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1455 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1455 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1455 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<13>(0h1000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = and(_T_381, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = and(_T_380, _T_388) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_389, UInt<1>(0h1), "") : assert_2 node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<1>(0h0)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_8) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h1)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_9) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<2>(0h2)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_10) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h3)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_11) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_393 connect _WIRE[1], _T_399 connect _WIRE[2], _T_405 connect _WIRE[3], _T_411 connect _WIRE[4], _T_417 connect _WIRE[5], _T_418 connect _WIRE[6], _T_419 connect _WIRE[7], _T_420 connect _WIRE[8], _T_421 connect _WIRE[9], _T_422 connect _WIRE[10], _T_423 connect _WIRE[11], _T_424 connect _WIRE[12], _T_425 connect _WIRE[13], _T_426 connect _WIRE[14], _T_427 connect _WIRE[15], _T_428 connect _WIRE[16], _T_429 connect _WIRE[17], _T_430 connect _WIRE[18], _T_431 connect _WIRE[19], _T_432 connect _WIRE[20], _T_433 connect _WIRE[21], _T_434 connect _WIRE[22], _T_435 connect _WIRE[23], _T_436 connect _WIRE[24], _T_437 connect _WIRE[25], _T_438 connect _WIRE[26], _T_439 connect _WIRE[27], _T_440 connect _WIRE[28], _T_441 connect _WIRE[29], _T_442 node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0)) node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0)) node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0)) node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0)) node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0)) node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0)) node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0)) node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0)) node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_481 = or(_T_451, _T_452) node _T_482 = or(_T_481, _T_453) node _T_483 = or(_T_482, _T_454) node _T_484 = or(_T_483, _T_455) node _T_485 = or(_T_484, _T_456) node _T_486 = or(_T_485, _T_457) node _T_487 = or(_T_486, _T_458) node _T_488 = or(_T_487, _T_459) node _T_489 = or(_T_488, _T_460) node _T_490 = or(_T_489, _T_461) node _T_491 = or(_T_490, _T_462) node _T_492 = or(_T_491, _T_463) node _T_493 = or(_T_492, _T_464) node _T_494 = or(_T_493, _T_465) node _T_495 = or(_T_494, _T_466) node _T_496 = or(_T_495, _T_467) node _T_497 = or(_T_496, _T_468) node _T_498 = or(_T_497, _T_469) node _T_499 = or(_T_498, _T_470) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_472) node _T_502 = or(_T_501, _T_473) node _T_503 = or(_T_502, _T_474) node _T_504 = or(_T_503, _T_475) node _T_505 = or(_T_504, _T_476) node _T_506 = or(_T_505, _T_477) node _T_507 = or(_T_506, _T_478) node _T_508 = or(_T_507, _T_479) node _T_509 = or(_T_508, _T_480) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_509 node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(UInt<1>(0h0), _T_512) node _T_514 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_WIRE_1, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_521, UInt<1>(0h1), "") : assert_3 node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(source_ok, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_528, UInt<1>(0h1), "") : assert_5 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(is_aligned, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_535, UInt<1>(0h1), "") : assert_7 node _T_539 = not(io.in.a.bits.mask) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_540, UInt<1>(0h1), "") : assert_8 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_544, UInt<1>(0h1), "") : assert_9 node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<1>(0h0)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_12) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<1>(0h1)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_13) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<2>(0h2)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_14) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<2>(0h3)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_15) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_602 = or(_T_552, _T_558) node _T_603 = or(_T_602, _T_564) node _T_604 = or(_T_603, _T_570) node _T_605 = or(_T_604, _T_576) node _T_606 = or(_T_605, _T_577) node _T_607 = or(_T_606, _T_578) node _T_608 = or(_T_607, _T_579) node _T_609 = or(_T_608, _T_580) node _T_610 = or(_T_609, _T_581) node _T_611 = or(_T_610, _T_582) node _T_612 = or(_T_611, _T_583) node _T_613 = or(_T_612, _T_584) node _T_614 = or(_T_613, _T_585) node _T_615 = or(_T_614, _T_586) node _T_616 = or(_T_615, _T_587) node _T_617 = or(_T_616, _T_588) node _T_618 = or(_T_617, _T_589) node _T_619 = or(_T_618, _T_590) node _T_620 = or(_T_619, _T_591) node _T_621 = or(_T_620, _T_592) node _T_622 = or(_T_621, _T_593) node _T_623 = or(_T_622, _T_594) node _T_624 = or(_T_623, _T_595) node _T_625 = or(_T_624, _T_596) node _T_626 = or(_T_625, _T_597) node _T_627 = or(_T_626, _T_598) node _T_628 = or(_T_627, _T_599) node _T_629 = or(_T_628, _T_600) node _T_630 = or(_T_629, _T_601) node _T_631 = and(_T_551, _T_630) node _T_632 = or(UInt<1>(0h0), _T_631) node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = and(_T_633, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = and(_T_632, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_641, UInt<1>(0h1), "") : assert_10 node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_646 = shr(io.in.a.bits.source, 2) node _T_647 = eq(_T_646, UInt<1>(0h0)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_16) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_652 = shr(io.in.a.bits.source, 2) node _T_653 = eq(_T_652, UInt<1>(0h1)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_17) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_658 = shr(io.in.a.bits.source, 2) node _T_659 = eq(_T_658, UInt<2>(0h2)) node _T_660 = leq(UInt<1>(0h0), uncommonBits_18) node _T_661 = and(_T_659, _T_660) node _T_662 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<2>(0h3)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_19) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_645 connect _WIRE_2[1], _T_651 connect _WIRE_2[2], _T_657 connect _WIRE_2[3], _T_663 connect _WIRE_2[4], _T_669 connect _WIRE_2[5], _T_670 connect _WIRE_2[6], _T_671 connect _WIRE_2[7], _T_672 connect _WIRE_2[8], _T_673 connect _WIRE_2[9], _T_674 connect _WIRE_2[10], _T_675 connect _WIRE_2[11], _T_676 connect _WIRE_2[12], _T_677 connect _WIRE_2[13], _T_678 connect _WIRE_2[14], _T_679 connect _WIRE_2[15], _T_680 connect _WIRE_2[16], _T_681 connect _WIRE_2[17], _T_682 connect _WIRE_2[18], _T_683 connect _WIRE_2[19], _T_684 connect _WIRE_2[20], _T_685 connect _WIRE_2[21], _T_686 connect _WIRE_2[22], _T_687 connect _WIRE_2[23], _T_688 connect _WIRE_2[24], _T_689 connect _WIRE_2[25], _T_690 connect _WIRE_2[26], _T_691 connect _WIRE_2[27], _T_692 connect _WIRE_2[28], _T_693 connect _WIRE_2[29], _T_694 node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0)) node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0)) node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0)) node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0)) node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0)) node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0)) node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0)) node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0)) node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_733 = or(_T_703, _T_704) node _T_734 = or(_T_733, _T_705) node _T_735 = or(_T_734, _T_706) node _T_736 = or(_T_735, _T_707) node _T_737 = or(_T_736, _T_708) node _T_738 = or(_T_737, _T_709) node _T_739 = or(_T_738, _T_710) node _T_740 = or(_T_739, _T_711) node _T_741 = or(_T_740, _T_712) node _T_742 = or(_T_741, _T_713) node _T_743 = or(_T_742, _T_714) node _T_744 = or(_T_743, _T_715) node _T_745 = or(_T_744, _T_716) node _T_746 = or(_T_745, _T_717) node _T_747 = or(_T_746, _T_718) node _T_748 = or(_T_747, _T_719) node _T_749 = or(_T_748, _T_720) node _T_750 = or(_T_749, _T_721) node _T_751 = or(_T_750, _T_722) node _T_752 = or(_T_751, _T_723) node _T_753 = or(_T_752, _T_724) node _T_754 = or(_T_753, _T_725) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_727) node _T_757 = or(_T_756, _T_728) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_730) node _T_760 = or(_T_759, _T_731) node _T_761 = or(_T_760, _T_732) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_761 node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_764 = and(_T_762, _T_763) node _T_765 = or(UInt<1>(0h0), _T_764) node _T_766 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_771) node _T_773 = and(_WIRE_3, _T_772) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_773, UInt<1>(0h1), "") : assert_11 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(source_ok, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_780, UInt<1>(0h1), "") : assert_13 node _T_784 = asUInt(reset) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(is_aligned, UInt<1>(0h0)) when _T_786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_787, UInt<1>(0h1), "") : assert_15 node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_791, UInt<1>(0h1), "") : assert_16 node _T_795 = not(io.in.a.bits.mask) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_796, UInt<1>(0h1), "") : assert_17 node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_800, UInt<1>(0h1), "") : assert_18 node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_20) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_21) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_22) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_23) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_858 = or(_T_808, _T_814) node _T_859 = or(_T_858, _T_820) node _T_860 = or(_T_859, _T_826) node _T_861 = or(_T_860, _T_832) node _T_862 = or(_T_861, _T_833) node _T_863 = or(_T_862, _T_834) node _T_864 = or(_T_863, _T_835) node _T_865 = or(_T_864, _T_836) node _T_866 = or(_T_865, _T_837) node _T_867 = or(_T_866, _T_838) node _T_868 = or(_T_867, _T_839) node _T_869 = or(_T_868, _T_840) node _T_870 = or(_T_869, _T_841) node _T_871 = or(_T_870, _T_842) node _T_872 = or(_T_871, _T_843) node _T_873 = or(_T_872, _T_844) node _T_874 = or(_T_873, _T_845) node _T_875 = or(_T_874, _T_846) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_848) node _T_878 = or(_T_877, _T_849) node _T_879 = or(_T_878, _T_850) node _T_880 = or(_T_879, _T_851) node _T_881 = or(_T_880, _T_852) node _T_882 = or(_T_881, _T_853) node _T_883 = or(_T_882, _T_854) node _T_884 = or(_T_883, _T_855) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = and(_T_807, _T_886) node _T_888 = or(UInt<1>(0h0), _T_887) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_888, UInt<1>(0h1), "") : assert_19 node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_893 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_894 = and(_T_892, _T_893) node _T_895 = or(UInt<1>(0h0), _T_894) node _T_896 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = and(_T_895, _T_900) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_902, UInt<1>(0h1), "") : assert_20 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(is_aligned, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_912, UInt<1>(0h1), "") : assert_23 node _T_916 = eq(io.in.a.bits.mask, mask) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_916, UInt<1>(0h1), "") : assert_24 node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_920, UInt<1>(0h1), "") : assert_25 node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_924 : node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_927 = and(_T_925, _T_926) node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_929 = shr(io.in.a.bits.source, 2) node _T_930 = eq(_T_929, UInt<1>(0h0)) node _T_931 = leq(UInt<1>(0h0), uncommonBits_24) node _T_932 = and(_T_930, _T_931) node _T_933 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_934 = and(_T_932, _T_933) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_935 = shr(io.in.a.bits.source, 2) node _T_936 = eq(_T_935, UInt<1>(0h1)) node _T_937 = leq(UInt<1>(0h0), uncommonBits_25) node _T_938 = and(_T_936, _T_937) node _T_939 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_940 = and(_T_938, _T_939) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_941 = shr(io.in.a.bits.source, 2) node _T_942 = eq(_T_941, UInt<2>(0h2)) node _T_943 = leq(UInt<1>(0h0), uncommonBits_26) node _T_944 = and(_T_942, _T_943) node _T_945 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_946 = and(_T_944, _T_945) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_947 = shr(io.in.a.bits.source, 2) node _T_948 = eq(_T_947, UInt<2>(0h3)) node _T_949 = leq(UInt<1>(0h0), uncommonBits_27) node _T_950 = and(_T_948, _T_949) node _T_951 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_952 = and(_T_950, _T_951) node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_978 = or(_T_928, _T_934) node _T_979 = or(_T_978, _T_940) node _T_980 = or(_T_979, _T_946) node _T_981 = or(_T_980, _T_952) node _T_982 = or(_T_981, _T_953) node _T_983 = or(_T_982, _T_954) node _T_984 = or(_T_983, _T_955) node _T_985 = or(_T_984, _T_956) node _T_986 = or(_T_985, _T_957) node _T_987 = or(_T_986, _T_958) node _T_988 = or(_T_987, _T_959) node _T_989 = or(_T_988, _T_960) node _T_990 = or(_T_989, _T_961) node _T_991 = or(_T_990, _T_962) node _T_992 = or(_T_991, _T_963) node _T_993 = or(_T_992, _T_964) node _T_994 = or(_T_993, _T_965) node _T_995 = or(_T_994, _T_966) node _T_996 = or(_T_995, _T_967) node _T_997 = or(_T_996, _T_968) node _T_998 = or(_T_997, _T_969) node _T_999 = or(_T_998, _T_970) node _T_1000 = or(_T_999, _T_971) node _T_1001 = or(_T_1000, _T_972) node _T_1002 = or(_T_1001, _T_973) node _T_1003 = or(_T_1002, _T_974) node _T_1004 = or(_T_1003, _T_975) node _T_1005 = or(_T_1004, _T_976) node _T_1006 = or(_T_1005, _T_977) node _T_1007 = and(_T_927, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1010 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = and(_T_1012, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = and(_T_1008, _T_1019) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_26 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(source_ok, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(is_aligned, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1030 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_29 node _T_1034 = eq(io.in.a.bits.mask, mask) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_30 node _T_1038 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1038 : node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1040 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1043 = shr(io.in.a.bits.source, 2) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1048 = and(_T_1046, _T_1047) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1049 = shr(io.in.a.bits.source, 2) node _T_1050 = eq(_T_1049, UInt<1>(0h1)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1055 = shr(io.in.a.bits.source, 2) node _T_1056 = eq(_T_1055, UInt<2>(0h2)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1061 = shr(io.in.a.bits.source, 2) node _T_1062 = eq(_T_1061, UInt<2>(0h3)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1092 = or(_T_1042, _T_1048) node _T_1093 = or(_T_1092, _T_1054) node _T_1094 = or(_T_1093, _T_1060) node _T_1095 = or(_T_1094, _T_1066) node _T_1096 = or(_T_1095, _T_1067) node _T_1097 = or(_T_1096, _T_1068) node _T_1098 = or(_T_1097, _T_1069) node _T_1099 = or(_T_1098, _T_1070) node _T_1100 = or(_T_1099, _T_1071) node _T_1101 = or(_T_1100, _T_1072) node _T_1102 = or(_T_1101, _T_1073) node _T_1103 = or(_T_1102, _T_1074) node _T_1104 = or(_T_1103, _T_1075) node _T_1105 = or(_T_1104, _T_1076) node _T_1106 = or(_T_1105, _T_1077) node _T_1107 = or(_T_1106, _T_1078) node _T_1108 = or(_T_1107, _T_1079) node _T_1109 = or(_T_1108, _T_1080) node _T_1110 = or(_T_1109, _T_1081) node _T_1111 = or(_T_1110, _T_1082) node _T_1112 = or(_T_1111, _T_1083) node _T_1113 = or(_T_1112, _T_1084) node _T_1114 = or(_T_1113, _T_1085) node _T_1115 = or(_T_1114, _T_1086) node _T_1116 = or(_T_1115, _T_1087) node _T_1117 = or(_T_1116, _T_1088) node _T_1118 = or(_T_1117, _T_1089) node _T_1119 = or(_T_1118, _T_1090) node _T_1120 = or(_T_1119, _T_1091) node _T_1121 = and(_T_1041, _T_1120) node _T_1122 = or(UInt<1>(0h0), _T_1121) node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = or(UInt<1>(0h0), _T_1125) node _T_1127 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = and(_T_1126, _T_1131) node _T_1133 = or(UInt<1>(0h0), _T_1132) node _T_1134 = and(_T_1122, _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_31 node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(source_ok, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(is_aligned, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1144 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_34 node _T_1148 = not(mask) node _T_1149 = and(io.in.a.bits.mask, _T_1148) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_35 node _T_1154 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1154 : node _T_1155 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1156 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1159 = shr(io.in.a.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1165 = shr(io.in.a.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1171 = shr(io.in.a.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1177 = shr(io.in.a.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1201 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1202 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1203 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1204 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1205 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1207 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1208 = or(_T_1158, _T_1164) node _T_1209 = or(_T_1208, _T_1170) node _T_1210 = or(_T_1209, _T_1176) node _T_1211 = or(_T_1210, _T_1182) node _T_1212 = or(_T_1211, _T_1183) node _T_1213 = or(_T_1212, _T_1184) node _T_1214 = or(_T_1213, _T_1185) node _T_1215 = or(_T_1214, _T_1186) node _T_1216 = or(_T_1215, _T_1187) node _T_1217 = or(_T_1216, _T_1188) node _T_1218 = or(_T_1217, _T_1189) node _T_1219 = or(_T_1218, _T_1190) node _T_1220 = or(_T_1219, _T_1191) node _T_1221 = or(_T_1220, _T_1192) node _T_1222 = or(_T_1221, _T_1193) node _T_1223 = or(_T_1222, _T_1194) node _T_1224 = or(_T_1223, _T_1195) node _T_1225 = or(_T_1224, _T_1196) node _T_1226 = or(_T_1225, _T_1197) node _T_1227 = or(_T_1226, _T_1198) node _T_1228 = or(_T_1227, _T_1199) node _T_1229 = or(_T_1228, _T_1200) node _T_1230 = or(_T_1229, _T_1201) node _T_1231 = or(_T_1230, _T_1202) node _T_1232 = or(_T_1231, _T_1203) node _T_1233 = or(_T_1232, _T_1204) node _T_1234 = or(_T_1233, _T_1205) node _T_1235 = or(_T_1234, _T_1206) node _T_1236 = or(_T_1235, _T_1207) node _T_1237 = and(_T_1157, _T_1236) node _T_1238 = or(UInt<1>(0h0), _T_1237) node _T_1239 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1240 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1241 = and(_T_1239, _T_1240) node _T_1242 = or(UInt<1>(0h0), _T_1241) node _T_1243 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<13>(0h1000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = and(_T_1242, _T_1247) node _T_1249 = or(UInt<1>(0h0), _T_1248) node _T_1250 = and(_T_1238, _T_1249) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_36 node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(source_ok, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(is_aligned, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1260 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_39 node _T_1264 = eq(io.in.a.bits.mask, mask) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_40 node _T_1268 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1268 : node _T_1269 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1270 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1271 = and(_T_1269, _T_1270) node _T_1272 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1273 = shr(io.in.a.bits.source, 2) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) node _T_1275 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1276 = and(_T_1274, _T_1275) node _T_1277 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1278 = and(_T_1276, _T_1277) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1279 = shr(io.in.a.bits.source, 2) node _T_1280 = eq(_T_1279, UInt<1>(0h1)) node _T_1281 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1284 = and(_T_1282, _T_1283) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1285 = shr(io.in.a.bits.source, 2) node _T_1286 = eq(_T_1285, UInt<2>(0h2)) node _T_1287 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1288 = and(_T_1286, _T_1287) node _T_1289 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1290 = and(_T_1288, _T_1289) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1291 = shr(io.in.a.bits.source, 2) node _T_1292 = eq(_T_1291, UInt<2>(0h3)) node _T_1293 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1294 = and(_T_1292, _T_1293) node _T_1295 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1312 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1313 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1315 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1316 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1317 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1318 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1319 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1320 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1321 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1322 = or(_T_1272, _T_1278) node _T_1323 = or(_T_1322, _T_1284) node _T_1324 = or(_T_1323, _T_1290) node _T_1325 = or(_T_1324, _T_1296) node _T_1326 = or(_T_1325, _T_1297) node _T_1327 = or(_T_1326, _T_1298) node _T_1328 = or(_T_1327, _T_1299) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1301) node _T_1331 = or(_T_1330, _T_1302) node _T_1332 = or(_T_1331, _T_1303) node _T_1333 = or(_T_1332, _T_1304) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1306) node _T_1336 = or(_T_1335, _T_1307) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1309) node _T_1339 = or(_T_1338, _T_1310) node _T_1340 = or(_T_1339, _T_1311) node _T_1341 = or(_T_1340, _T_1312) node _T_1342 = or(_T_1341, _T_1313) node _T_1343 = or(_T_1342, _T_1314) node _T_1344 = or(_T_1343, _T_1315) node _T_1345 = or(_T_1344, _T_1316) node _T_1346 = or(_T_1345, _T_1317) node _T_1347 = or(_T_1346, _T_1318) node _T_1348 = or(_T_1347, _T_1319) node _T_1349 = or(_T_1348, _T_1320) node _T_1350 = or(_T_1349, _T_1321) node _T_1351 = and(_T_1271, _T_1350) node _T_1352 = or(UInt<1>(0h0), _T_1351) node _T_1353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1354 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1355 = and(_T_1353, _T_1354) node _T_1356 = or(UInt<1>(0h0), _T_1355) node _T_1357 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1358 = cvt(_T_1357) node _T_1359 = and(_T_1358, asSInt(UInt<13>(0h1000))) node _T_1360 = asSInt(_T_1359) node _T_1361 = eq(_T_1360, asSInt(UInt<1>(0h0))) node _T_1362 = and(_T_1356, _T_1361) node _T_1363 = or(UInt<1>(0h0), _T_1362) node _T_1364 = and(_T_1352, _T_1363) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_41 node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(source_ok, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(is_aligned, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1374 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_44 node _T_1378 = eq(io.in.a.bits.mask, mask) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_45 node _T_1382 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1382 : node _T_1383 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1384 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1385 = and(_T_1383, _T_1384) node _T_1386 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1387 = shr(io.in.a.bits.source, 2) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1393 = shr(io.in.a.bits.source, 2) node _T_1394 = eq(_T_1393, UInt<1>(0h1)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1399 = shr(io.in.a.bits.source, 2) node _T_1400 = eq(_T_1399, UInt<2>(0h2)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1405 = shr(io.in.a.bits.source, 2) node _T_1406 = eq(_T_1405, UInt<2>(0h3)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1410 = and(_T_1408, _T_1409) node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1429 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1430 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1431 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1434 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1435 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1436 = or(_T_1386, _T_1392) node _T_1437 = or(_T_1436, _T_1398) node _T_1438 = or(_T_1437, _T_1404) node _T_1439 = or(_T_1438, _T_1410) node _T_1440 = or(_T_1439, _T_1411) node _T_1441 = or(_T_1440, _T_1412) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1414) node _T_1444 = or(_T_1443, _T_1415) node _T_1445 = or(_T_1444, _T_1416) node _T_1446 = or(_T_1445, _T_1417) node _T_1447 = or(_T_1446, _T_1418) node _T_1448 = or(_T_1447, _T_1419) node _T_1449 = or(_T_1448, _T_1420) node _T_1450 = or(_T_1449, _T_1421) node _T_1451 = or(_T_1450, _T_1422) node _T_1452 = or(_T_1451, _T_1423) node _T_1453 = or(_T_1452, _T_1424) node _T_1454 = or(_T_1453, _T_1425) node _T_1455 = or(_T_1454, _T_1426) node _T_1456 = or(_T_1455, _T_1427) node _T_1457 = or(_T_1456, _T_1428) node _T_1458 = or(_T_1457, _T_1429) node _T_1459 = or(_T_1458, _T_1430) node _T_1460 = or(_T_1459, _T_1431) node _T_1461 = or(_T_1460, _T_1432) node _T_1462 = or(_T_1461, _T_1433) node _T_1463 = or(_T_1462, _T_1434) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = and(_T_1385, _T_1464) node _T_1466 = or(UInt<1>(0h0), _T_1465) node _T_1467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = or(UInt<1>(0h0), _T_1469) node _T_1471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = and(_T_1470, _T_1475) node _T_1477 = or(UInt<1>(0h0), _T_1476) node _T_1478 = and(_T_1466, _T_1477) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_46 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(source_ok, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(is_aligned, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1488 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_49 node _T_1492 = eq(io.in.a.bits.mask, mask) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_50 node _T_1496 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(_T_1496, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1496, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1500 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1504 : node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok_1, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1508 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_54 node _T_1512 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_55 node _T_1516 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_56 node _T_1520 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_57 node _T_1524 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1524 : node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(source_ok_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(sink_ok, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1531 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(_T_1531, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1531, UInt<1>(0h1), "") : assert_60 node _T_1535 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_61 node _T_1539 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_62 node _T_1543 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_63 node _T_1547 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1548 = or(UInt<1>(0h1), _T_1547) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_64 node _T_1552 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1552 : node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(source_ok_1, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(sink_ok, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1559 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_67 node _T_1563 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_68 node _T_1567 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_69 node _T_1571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1572 = or(_T_1571, io.in.d.bits.corrupt) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_70 node _T_1576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1577 = or(UInt<1>(0h1), _T_1576) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_71 node _T_1581 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1581 : node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(source_ok_1, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_73 node _T_1589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_74 node _T_1593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1594 = or(UInt<1>(0h1), _T_1593) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_75 node _T_1598 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1598 : node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(source_ok_1, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1602 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(_T_1602, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1602, UInt<1>(0h1), "") : assert_77 node _T_1606 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1607 = or(_T_1606, io.in.d.bits.corrupt) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_78 node _T_1611 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1612 = or(UInt<1>(0h1), _T_1611) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_79 node _T_1616 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1616 : node _T_1617 = asUInt(reset) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) when _T_1618 : node _T_1619 = eq(source_ok_1, UInt<1>(0h0)) when _T_1619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1620 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(_T_1620, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1620, UInt<1>(0h1), "") : assert_81 node _T_1624 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(_T_1624, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1624, UInt<1>(0h1), "") : assert_82 node _T_1628 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1629 = or(UInt<1>(0h1), _T_1628) node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(_T_1629, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1629, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1633 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(_T_1633, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1633, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1637 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1641 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1642 = asUInt(reset) node _T_1643 = eq(_T_1642, UInt<1>(0h0)) when _T_1643 : node _T_1644 = eq(_T_1641, UInt<1>(0h0)) when _T_1644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1641, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1645 = eq(a_first, UInt<1>(0h0)) node _T_1646 = and(io.in.a.valid, _T_1645) when _T_1646 : node _T_1647 = eq(io.in.a.bits.opcode, opcode) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_87 node _T_1651 = eq(io.in.a.bits.param, param) node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(_T_1651, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1651, UInt<1>(0h1), "") : assert_88 node _T_1655 = eq(io.in.a.bits.size, size) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_89 node _T_1659 = eq(io.in.a.bits.source, source) node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(_T_1659, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1659, UInt<1>(0h1), "") : assert_90 node _T_1663 = eq(io.in.a.bits.address, address) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_91 node _T_1667 = and(io.in.a.ready, io.in.a.valid) node _T_1668 = and(_T_1667, a_first) when _T_1668 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1669 = eq(d_first, UInt<1>(0h0)) node _T_1670 = and(io.in.d.valid, _T_1669) when _T_1670 : node _T_1671 = eq(io.in.d.bits.opcode, opcode_1) node _T_1672 = asUInt(reset) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(_T_1671, UInt<1>(0h0)) when _T_1674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1671, UInt<1>(0h1), "") : assert_92 node _T_1675 = eq(io.in.d.bits.param, param_1) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_93 node _T_1679 = eq(io.in.d.bits.size, size_1) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_94 node _T_1683 = eq(io.in.d.bits.source, source_1) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_95 node _T_1687 = eq(io.in.d.bits.sink, sink) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_96 node _T_1691 = eq(io.in.d.bits.denied, denied) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_97 node _T_1695 = and(io.in.d.ready, io.in.d.valid) node _T_1696 = and(_T_1695, d_first) when _T_1696 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1697 = and(io.in.a.valid, a_first_1) node _T_1698 = and(_T_1697, UInt<1>(0h1)) when _T_1698 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first_1) node _T_1701 = and(_T_1700, UInt<1>(0h1)) when _T_1701 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1702 = dshr(inflight, io.in.a.bits.source) node _T_1703 = bits(_T_1702, 0, 0) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1708 = and(io.in.d.valid, d_first_1) node _T_1709 = and(_T_1708, UInt<1>(0h1)) node _T_1710 = eq(d_release_ack, UInt<1>(0h0)) node _T_1711 = and(_T_1709, _T_1710) when _T_1711 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1712 = and(io.in.d.ready, io.in.d.valid) node _T_1713 = and(_T_1712, d_first_1) node _T_1714 = and(_T_1713, UInt<1>(0h1)) node _T_1715 = eq(d_release_ack, UInt<1>(0h0)) node _T_1716 = and(_T_1714, _T_1715) when _T_1716 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1717 = and(io.in.d.valid, d_first_1) node _T_1718 = and(_T_1717, UInt<1>(0h1)) node _T_1719 = eq(d_release_ack, UInt<1>(0h0)) node _T_1720 = and(_T_1718, _T_1719) when _T_1720 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1721 = dshr(inflight, io.in.d.bits.source) node _T_1722 = bits(_T_1721, 0, 0) node _T_1723 = or(_T_1722, same_cycle_resp) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1727 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1728 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1729 = or(_T_1727, _T_1728) node _T_1730 = asUInt(reset) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) when _T_1731 : node _T_1732 = eq(_T_1729, UInt<1>(0h0)) when _T_1732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1729, UInt<1>(0h1), "") : assert_100 node _T_1733 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1734 = asUInt(reset) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) when _T_1735 : node _T_1736 = eq(_T_1733, UInt<1>(0h0)) when _T_1736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1733, UInt<1>(0h1), "") : assert_101 else : node _T_1737 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1738 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1739 = or(_T_1737, _T_1738) node _T_1740 = asUInt(reset) node _T_1741 = eq(_T_1740, UInt<1>(0h0)) when _T_1741 : node _T_1742 = eq(_T_1739, UInt<1>(0h0)) when _T_1742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1739, UInt<1>(0h1), "") : assert_102 node _T_1743 = eq(io.in.d.bits.size, a_size_lookup) node _T_1744 = asUInt(reset) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) when _T_1745 : node _T_1746 = eq(_T_1743, UInt<1>(0h0)) when _T_1746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1743, UInt<1>(0h1), "") : assert_103 node _T_1747 = and(io.in.d.valid, d_first_1) node _T_1748 = and(_T_1747, a_first_1) node _T_1749 = and(_T_1748, io.in.a.valid) node _T_1750 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1751 = and(_T_1749, _T_1750) node _T_1752 = eq(d_release_ack, UInt<1>(0h0)) node _T_1753 = and(_T_1751, _T_1752) when _T_1753 : node _T_1754 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1755 = or(_T_1754, io.in.a.ready) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_104 node _T_1759 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1760 = orr(a_set_wo_ready) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = or(_T_1759, _T_1761) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_42 node _T_1766 = orr(inflight) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) node _T_1768 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1769 = or(_T_1767, _T_1768) node _T_1770 = lt(watchdog, plusarg_reader.out) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1775 = and(io.in.a.ready, io.in.a.valid) node _T_1776 = and(io.in.d.ready, io.in.d.valid) node _T_1777 = or(_T_1775, _T_1776) when _T_1777 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1778 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1779 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1780 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1781 = and(_T_1779, _T_1780) node _T_1782 = and(_T_1778, _T_1781) when _T_1782 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1783 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1784 = and(_T_1783, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1785 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1786 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = and(_T_1784, _T_1787) when _T_1788 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1789 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1790 = bits(_T_1789, 0, 0) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1795 = and(io.in.d.valid, d_first_2) node _T_1796 = and(_T_1795, UInt<1>(0h1)) node _T_1797 = and(_T_1796, d_release_ack_1) when _T_1797 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1798 = and(io.in.d.ready, io.in.d.valid) node _T_1799 = and(_T_1798, d_first_2) node _T_1800 = and(_T_1799, UInt<1>(0h1)) node _T_1801 = and(_T_1800, d_release_ack_1) when _T_1801 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1802 = and(io.in.d.valid, d_first_2) node _T_1803 = and(_T_1802, UInt<1>(0h1)) node _T_1804 = and(_T_1803, d_release_ack_1) when _T_1804 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1805 = dshr(inflight_1, io.in.d.bits.source) node _T_1806 = bits(_T_1805, 0, 0) node _T_1807 = or(_T_1806, same_cycle_resp_1) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1811 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1812 = asUInt(reset) node _T_1813 = eq(_T_1812, UInt<1>(0h0)) when _T_1813 : node _T_1814 = eq(_T_1811, UInt<1>(0h0)) when _T_1814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1811, UInt<1>(0h1), "") : assert_109 else : node _T_1815 = eq(io.in.d.bits.size, c_size_lookup) node _T_1816 = asUInt(reset) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) when _T_1817 : node _T_1818 = eq(_T_1815, UInt<1>(0h0)) when _T_1818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1815, UInt<1>(0h1), "") : assert_110 node _T_1819 = and(io.in.d.valid, d_first_2) node _T_1820 = and(_T_1819, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1821 = and(_T_1820, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1822 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = and(_T_1823, d_release_ack_1) node _T_1825 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1826 = and(_T_1824, _T_1825) when _T_1826 : node _T_1827 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1828 = or(_T_1827, _WIRE_27.ready) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_111 node _T_1832 = orr(c_set_wo_ready) when _T_1832 : node _T_1833 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1834 = asUInt(reset) node _T_1835 = eq(_T_1834, UInt<1>(0h0)) when _T_1835 : node _T_1836 = eq(_T_1833, UInt<1>(0h0)) when _T_1836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1833, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_43 node _T_1837 = orr(inflight_1) node _T_1838 = eq(_T_1837, UInt<1>(0h0)) node _T_1839 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1840 = or(_T_1838, _T_1839) node _T_1841 = lt(watchdog_1, plusarg_reader_1.out) node _T_1842 = or(_T_1840, _T_1841) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1846 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1847 = and(io.in.d.ready, io.in.d.valid) node _T_1848 = or(_T_1846, _T_1847) when _T_1848 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1775 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1775; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1775; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1848 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1848; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1701 = _T_1775 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1701 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1701 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1701 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1701 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1701 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1747 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1747 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1716 = _T_1848 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1716 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1716 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1716 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1819 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1819 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1801 = _T_1848 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1801 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1801 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1801 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MSHR_80 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_80( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_38 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_38 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_38( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_38 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_75 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_75( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_69 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_69( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_257 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_257( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_66 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_valid, slot_uop.iw_issued) when _T_40 : connect next_valid, rebusied

module IssueSlot_66( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]

Generate the Verilog code corresponding to this FIRRTL code module PE_206 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_206( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_54 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_54( // @[MulAddRecFN.scala:71:7] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [9:0] rawA_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawA_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [24:0] rawA_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawA_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [10:0] _sExpAlignedProd_T = 11'h12B; // @[MulAddRecFN.scala:100:19] wire [11:0] _sExpAlignedProd_T_1 = 12'h46; // @[MulAddRecFN.scala:100:32] wire [10:0] _sExpAlignedProd_T_2 = 11'h46; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = 11'h46; // @[MulAddRecFN.scala:100:32] wire [32:0] reduced4CExtra_shift = 33'h100000000; // @[primitives.scala:76:56] wire [3:0] _reduced4CExtra_T_4 = 4'h0; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = 4'h0; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_3 = 6'h0; // @[primitives.scala:77:20, :78:22] wire [5:0] _reduced4CExtra_T_18 = 6'h0; // @[primitives.scala:77:20, :78:22] wire [6:0] CAlignDist = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68] wire [11:0] _io_toPostMul_sExpSum_T = 12'h2E; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = 11'h2E; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = 11'h2E; // @[MulAddRecFN.scala:158:53] wire [4:0] io_toPostMul_CDom_CAlignDist = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47] wire [4:0] _reduced4CExtra_T_2 = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47] wire [4:0] _io_toPostMul_CDom_CAlignDist_T = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47] wire io_toPostMul_isZeroA = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawA_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawA_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawA_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawA_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _signProd_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _isMinCAlign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire isMinCAlign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _CIsDominant_T_2 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_isNaNAOrB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _reduced4CExtra_T_6 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_15 = 1'h0; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = 1'h0; // @[primitives.scala:77:20] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_2 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_6 = 1'h0; // @[MulAddRecFN.scala:146:32] wire _io_toPostMul_isNaNAOrB_T = 1'h0; // @[MulAddRecFN.scala:148:42] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [23:0] io_mulAddA = 24'h0; // @[MulAddRecFN.scala:71:7, :74:16, :141:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawA_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawA_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_5 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_8 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_9 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_12 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_14 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _reduced4CExtra_T_17 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _doSubMags_T = ~rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = 12'h46 - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] assign CIsDominant = _CIsDominant_T; // @[MulAddRecFN.scala:110:{9,23}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = _mainAlignedSigC_T_4; // @[MulAddRecFN.scala:120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:53:28, :55:23, :61:32] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : 11'h2E; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_2 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_2( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_1 : input clock : Clock input reset : Reset output auto : { } wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0]

module TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_1( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset // @[Xbar.scala:74:9] ); endmodule

Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_1 : output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}, last : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset output io : { gcd_busy : UInt<1>} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready connect clockNodeIn, auto.clock_in connect nodeIn, auto.in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset reg x : UInt<32>, clock wire y : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>} wire gcd : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>} wire status : UInt<2> inst impl_io_impl of GCDMMIOBlackBox connect impl_io_impl.clock, clock node _impl_impl_io_reset_T = asUInt(reset) connect impl_io_impl.reset, _impl_impl_io_reset_T connect impl_io_impl.x, x connect impl_io_impl.y, y.bits connect impl_io_impl.input_valid, y.valid connect y.ready, impl_io_impl.input_ready connect gcd.bits, impl_io_impl.gcd connect gcd.valid, impl_io_impl.output_valid connect impl_io_impl.output_ready, gcd.ready node _status_T = cat(impl_io_impl.input_ready, impl_io_impl.output_valid) connect status, _status_T connect io.gcd_busy, impl_io_impl.busy wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} wire ar_extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>} wire aw_extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>} node _in_valid_T = and(nodeIn.aw.valid, nodeIn.w.valid) node _in_valid_T_1 = or(nodeIn.ar.valid, _in_valid_T) connect in.valid, _in_valid_T_1 connect nodeIn.ar.ready, in.ready node _nodeIn_aw_ready_T = eq(nodeIn.ar.valid, UInt<1>(0h0)) node _nodeIn_aw_ready_T_1 = and(in.ready, _nodeIn_aw_ready_T) node _nodeIn_aw_ready_T_2 = and(_nodeIn_aw_ready_T_1, nodeIn.w.valid) connect nodeIn.aw.ready, _nodeIn_aw_ready_T_2 node _nodeIn_w_ready_T = eq(nodeIn.ar.valid, UInt<1>(0h0)) node _nodeIn_w_ready_T_1 = and(in.ready, _nodeIn_w_ready_T) node _nodeIn_w_ready_T_2 = and(_nodeIn_w_ready_T_1, nodeIn.aw.valid) connect nodeIn.w.ready, _nodeIn_w_ready_T_2 connect ar_extra.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect ar_extra.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect aw_extra.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect aw_extra.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect ar_extra.extra_id, nodeIn.ar.bits.id connect aw_extra.extra_id, nodeIn.aw.bits.id node addr = mux(nodeIn.ar.valid, nodeIn.ar.bits.addr, nodeIn.aw.bits.addr) node _mask_sizeOH_T = or(nodeIn.ar.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(nodeIn.ar.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(nodeIn.ar.bits.addr, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(nodeIn.ar.bits.addr, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(nodeIn.ar.bits.addr, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) connect in.bits.read, nodeIn.ar.valid node _in_bits_index_T = shr(addr, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.w.bits.data node _in_bits_mask_T = mux(nodeIn.ar.valid, mask, nodeIn.w.bits.strb) connect in.bits.mask, _in_bits_mask_T node _in_bits_extra_T = mux(nodeIn.ar.valid, ar_extra, aw_extra) connect in.bits.extra, _in_bits_extra_T wire out_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h1)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[4] wire out_wivalid : UInt<1>[4] wire out_roready : UInt<1>[4] wire out_woready : UInt<1>[4] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 1, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 1, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 1, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 1, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_4 = bits(out_front.bits.data, 1, 0) node _out_T_5 = eq(out_rimask, UInt<1>(0h0)) node _out_T_6 = eq(out_wimask, UInt<1>(0h0)) node _out_T_7 = eq(out_romask, UInt<1>(0h0)) node _out_T_8 = eq(out_womask, UInt<1>(0h0)) node _out_T_9 = or(status, UInt<2>(0h0)) node _out_T_10 = bits(_out_T_9, 1, 0) node _out_rimask_T_1 = bits(out_frontMask, 63, 32) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 63, 32) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 63, 32) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 63, 32) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_11 = bits(out_front.bits.data, 63, 32) when out_f_woready_1 : connect x, _out_T_11 node _out_T_12 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_14 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_15 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_10, UInt<32>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_16 = or(out_prepend, UInt<64>(0h0)) node _out_T_17 = bits(_out_T_16, 63, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_18 = bits(out_front.bits.data, 31, 0) connect y.valid, out_f_woready_2 connect y.bits, _out_T_18 node _out_T_19 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_21 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_22 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_23 = or(y.ready, _out_T_22) node _out_T_24 = or(UInt<1>(0h0), UInt<32>(0h0)) node _out_T_25 = bits(_out_T_24, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 63, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 63, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 63, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 63, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect gcd.ready, out_f_roready_3 node _out_T_26 = bits(out_front.bits.data, 63, 32) node _out_T_27 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_28 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_29 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_30 = or(gcd.valid, _out_T_29) node _out_T_31 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<32>(0h0)) node out_prepend_1 = cat(gcd.bits, _out_prepend_T_1) node _out_T_32 = or(out_prepend_1, UInt<64>(0h0)) node _out_T_33 = bits(_out_T_32, 63, 0) node out_iindex = bits(out_front.bits.index, 0, 0) node _out_iindex_T = bits(out_front.bits.index, 1, 1) node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_4 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_5 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_6 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_7 = bits(out_front.bits.index, 8, 8) node out_oindex = bits(out_front.bits.index, 0, 0) node _out_oindex_T = bits(out_front.bits.index, 1, 1) node _out_oindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_4 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_5 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_6 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_7 = bits(out_front.bits.index, 8, 8) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_7 connect out_rivalid[2], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) wire _out_rifireMux_WIRE : UInt<1>[2] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_8 connect out_wivalid[2], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) wire _out_wifireMux_WIRE : UInt<1>[2] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out_out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) node out_rofireMux_all = and(_out_rofireMux_T_7, _out_T_30) connect out_rofireMux_out_1, _out_T_30 connect out_roready[3], _out_rofireMux_T_7 connect out_roready[2], out_rofireMux_all node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) wire _out_rofireMux_WIRE : UInt<1>[2] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out_out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) node out_wofireMux_all = and(_out_wofireMux_T_8, _out_T_23) connect out_wofireMux_out_1, _out_T_23 connect out_woready[3], out_wofireMux_all connect out_woready[2], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) wire _out_wofireMux_WIRE : UInt<1>[2] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out_out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out_out.valid, _out_out_valid_T connect out_out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE : UInt<1>[2] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE_1 : UInt<64>[2] connect _out_out_bits_data_WIRE_1[0], _out_T_17 connect _out_out_bits_data_WIRE_1[1], _out_T_33 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out_out.bits.data, _out_out_bits_data_T_4 connect out_out.bits.extra, out_front.bits.extra inst out_deq_q of Queue2_RegMapperOutput connect out_deq_q.clock, clock connect out_deq_q.reset, reset connect out_deq_q.io.enq.valid, out_out.valid connect out_deq_q.io.enq.bits.extra.extra_id, out_out.bits.extra.extra_id connect out_deq_q.io.enq.bits.extra.tl_state.source, out_out.bits.extra.tl_state.source connect out_deq_q.io.enq.bits.extra.tl_state.size, out_out.bits.extra.tl_state.size connect out_deq_q.io.enq.bits.data, out_out.bits.data connect out_deq_q.io.enq.bits.read, out_out.bits.read connect out_out.ready, out_deq_q.io.enq.ready wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tl_state : { size : UInt<4>, source : UInt<11>}, extra_id : UInt<1>}}} connect out.bits, out_deq_q.io.deq.bits connect out.valid, out_deq_q.io.deq.valid connect out_deq_q.io.deq.ready, out.ready node _out_ready_T = mux(out.bits.read, nodeIn.r.ready, nodeIn.b.ready) connect out.ready, _out_ready_T node _nodeIn_r_valid_T = and(out.valid, out.bits.read) connect nodeIn.r.valid, _nodeIn_r_valid_T node _nodeIn_b_valid_T = eq(out.bits.read, UInt<1>(0h0)) node _nodeIn_b_valid_T_1 = and(out.valid, _nodeIn_b_valid_T) connect nodeIn.b.valid, _nodeIn_b_valid_T_1 connect nodeIn.r.bits.id, out.bits.extra.extra_id connect nodeIn.r.bits.data, out.bits.data connect nodeIn.r.bits.last, UInt<1>(0h1) connect nodeIn.r.bits.resp, UInt<2>(0h0) connect nodeIn.r.bits.echo.tl_state.source, out.bits.extra.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, out.bits.extra.tl_state.size connect nodeIn.b.bits.id, out.bits.extra.extra_id connect nodeIn.b.bits.resp, UInt<2>(0h0) connect nodeIn.b.bits.echo.tl_state.source, out.bits.extra.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, out.bits.extra.tl_state.size extmodule plusarg_reader_117 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_118 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module ClockSinkDomain_1( // @[GCD.scala:179:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [14:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [14:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] output io_gcd_busy // @[GCD.scala:180:16] ); wire out_front_ready; // @[RegisterRouter.scala:72:16] wire _out_wofireMux_T_2; // @[RegisterRouter.scala:72:16] wire _out_wofireMux_T; // @[RegisterRouter.scala:72:16] wire out_iindex; // @[RegisterRouter.scala:72:16] wire _out_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _out_deq_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _out_deq_q_io_deq_bits_read; // @[Decoupled.scala:362:21] wire [3:0] _out_deq_q_io_deq_bits_extra_tl_state_size; // @[Decoupled.scala:362:21] wire [10:0] _out_deq_q_io_deq_bits_extra_tl_state_source; // @[Decoupled.scala:362:21] wire _out_deq_q_io_deq_bits_extra_extra_id; // @[Decoupled.scala:362:21] wire _impl_io_impl_input_ready; // @[GCD.scala:189:26] wire _impl_io_impl_output_valid; // @[GCD.scala:189:26] wire [31:0] _impl_io_impl_gcd; // @[GCD.scala:189:26] reg [31:0] x; // @[GCD.scala:183:18] wire in_valid = auto_in_ar_valid | auto_in_aw_valid & auto_in_w_valid; // @[RegisterRouter.scala:52:{26,39}] wire [8:0] addr = auto_in_ar_valid ? auto_in_ar_bits_addr[11:3] : auto_in_aw_bits_addr[11:3]; // @[RegisterRouter.scala:61:19] wire mask_sub_sub_sub_0_1 = auto_in_ar_bits_size > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = auto_in_ar_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | mask_sub_sub_size & ~(auto_in_ar_bits_addr[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | mask_sub_sub_size & auto_in_ar_bits_addr[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}] wire mask_sub_size = auto_in_ar_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49] wire mask_sub_0_2 = ~(auto_in_ar_bits_addr[2]) & ~(auto_in_ar_bits_addr[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire mask_sub_0_1 = mask_sub_sub_0_1 | mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire mask_sub_1_2 = ~(auto_in_ar_bits_addr[2]) & auto_in_ar_bits_addr[1]; // @[Misc.scala:210:26, :211:20, :214:27] wire mask_sub_1_1 = mask_sub_sub_0_1 | mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire mask_sub_2_2 = auto_in_ar_bits_addr[2] & ~(auto_in_ar_bits_addr[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire mask_sub_2_1 = mask_sub_sub_1_1 | mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire mask_sub_3_2 = auto_in_ar_bits_addr[2] & auto_in_ar_bits_addr[1]; // @[Misc.scala:210:26, :214:27] wire mask_sub_3_1 = mask_sub_sub_1_1 | mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire [7:0] in_bits_mask = auto_in_ar_valid ? {mask_sub_3_1 | mask_sub_3_2 & auto_in_ar_bits_addr[0], mask_sub_3_1 | mask_sub_3_2 & ~(auto_in_ar_bits_addr[0]), mask_sub_2_1 | mask_sub_2_2 & auto_in_ar_bits_addr[0], mask_sub_2_1 | mask_sub_2_2 & ~(auto_in_ar_bits_addr[0]), mask_sub_1_1 | mask_sub_1_2 & auto_in_ar_bits_addr[0], mask_sub_1_1 | mask_sub_1_2 & ~(auto_in_ar_bits_addr[0]), mask_sub_0_1 | mask_sub_0_2 & auto_in_ar_bits_addr[0], mask_sub_0_1 | mask_sub_0_2 & ~(auto_in_ar_bits_addr[0])} : auto_in_w_bits_strb; // @[Misc.scala:210:26, :211:20, :214:27, :215:29, :222:10] wire _out_T_3 = addr[8:1] == 8'h0; // @[RegisterRouter.scala:61:19, :72:16] wire [31:0] _out_womask_T_3 = {{8{in_bits_mask[7]}}, {8{in_bits_mask[6]}}, {8{in_bits_mask[5]}}, {8{in_bits_mask[4]}}}; // @[RegisterRouter.scala:67:25, :72:16] wire [31:0] _out_womask_T_2 = {{8{in_bits_mask[3]}}, {8{in_bits_mask[2]}}, {8{in_bits_mask[1]}}, {8{in_bits_mask[0]}}}; // @[RegisterRouter.scala:67:25, :72:16] assign out_iindex = addr[0]; // @[RegisterRouter.scala:61:19, :72:16] assign _out_wofireMux_T = in_valid & _out_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] assign _out_wofireMux_T_2 = _out_wofireMux_T & ~auto_in_ar_valid; // @[RegisterRouter.scala:72:16] wire out_oready = auto_in_ar_valid ? ~out_iindex | (|{_impl_io_impl_output_valid | ~(|_out_womask_T_3), addr[8:1]}) : ~out_iindex | (|{_impl_io_impl_input_ready | ~(&_out_womask_T_2), addr[8:1]}); // @[MuxLiteral.scala:49:10] assign out_front_ready = _out_deq_q_io_enq_ready & out_oready; // @[Decoupled.scala:362:21] always @(posedge auto_clock_in_clock) begin // @[LazyModuleImp.scala:107:25] if (_out_wofireMux_T_2 & ~out_iindex & _out_T_3 & (&_out_womask_T_3)) // @[RegisterRouter.scala:72:16] x <= auto_in_w_bits_data[63:32]; // @[RegisterRouter.scala:72:16] always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<13>(0h1000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = and(_T_139, _T_144) node _T_146 = or(UInt<1>(0h0), _T_145) node _T_147 = and(_T_138, _T_146) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_147, UInt<1>(0h1), "") : assert_2 node _T_151 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_152 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_153 = and(_T_151, _T_152) node _T_154 = or(UInt<1>(0h0), _T_153) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<13>(0h1000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = and(_T_154, _T_159) node _T_161 = or(UInt<1>(0h0), _T_160) node _T_162 = and(UInt<1>(0h0), _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_162, UInt<1>(0h1), "") : assert_3 node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(source_ok, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_169 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_169, UInt<1>(0h1), "") : assert_5 node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(is_aligned, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_176 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_176, UInt<1>(0h1), "") : assert_7 node _T_180 = not(io.in.a.bits.mask) node _T_181 = eq(_T_180, UInt<1>(0h0)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_181, UInt<1>(0h1), "") : assert_8 node _T_185 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_185, UInt<1>(0h1), "") : assert_9 node _T_189 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_189 : node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_194 = shr(io.in.a.bits.source, 2) node _T_195 = eq(_T_194, UInt<1>(0h0)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_8) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_199 = and(_T_197, _T_198) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_200 = shr(io.in.a.bits.source, 2) node _T_201 = eq(_T_200, UInt<1>(0h1)) node _T_202 = leq(UInt<1>(0h0), uncommonBits_9) node _T_203 = and(_T_201, _T_202) node _T_204 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_205 = and(_T_203, _T_204) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<2>(0h2)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_10) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<2>(0h3)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_11) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_220 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_221 = or(_T_193, _T_199) node _T_222 = or(_T_221, _T_205) node _T_223 = or(_T_222, _T_211) node _T_224 = or(_T_223, _T_217) node _T_225 = or(_T_224, _T_218) node _T_226 = or(_T_225, _T_219) node _T_227 = or(_T_226, _T_220) node _T_228 = and(_T_192, _T_227) node _T_229 = or(UInt<1>(0h0), _T_228) node _T_230 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = and(_T_230, _T_235) node _T_237 = or(UInt<1>(0h0), _T_236) node _T_238 = and(_T_229, _T_237) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_238, UInt<1>(0h1), "") : assert_10 node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(UInt<1>(0h0), _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_253, UInt<1>(0h1), "") : assert_11 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(source_ok, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_260 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_260, UInt<1>(0h1), "") : assert_13 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(is_aligned, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_267 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_267, UInt<1>(0h1), "") : assert_15 node _T_271 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : node _T_274 = eq(_T_271, UInt<1>(0h0)) when _T_274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_271, UInt<1>(0h1), "") : assert_16 node _T_275 = not(io.in.a.bits.mask) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_276, UInt<1>(0h1), "") : assert_17 node _T_280 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(_T_280, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_280, UInt<1>(0h1), "") : assert_18 node _T_284 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_284 : node _T_285 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_286 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_287 = and(_T_285, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_289 = shr(io.in.a.bits.source, 2) node _T_290 = eq(_T_289, UInt<1>(0h0)) node _T_291 = leq(UInt<1>(0h0), uncommonBits_12) node _T_292 = and(_T_290, _T_291) node _T_293 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_294 = and(_T_292, _T_293) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h1)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_13) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<2>(0h2)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_14) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h3)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_15) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_315 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_316 = or(_T_288, _T_294) node _T_317 = or(_T_316, _T_300) node _T_318 = or(_T_317, _T_306) node _T_319 = or(_T_318, _T_312) node _T_320 = or(_T_319, _T_313) node _T_321 = or(_T_320, _T_314) node _T_322 = or(_T_321, _T_315) node _T_323 = and(_T_287, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_324, UInt<1>(0h1), "") : assert_19 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = and(_T_331, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_338, UInt<1>(0h1), "") : assert_20 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(source_ok, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(is_aligned, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_348 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_348, UInt<1>(0h1), "") : assert_23 node _T_352 = eq(io.in.a.bits.mask, mask) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_352, UInt<1>(0h1), "") : assert_24 node _T_356 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_356, UInt<1>(0h1), "") : assert_25 node _T_360 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_360 : node _T_361 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_362 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_365 = shr(io.in.a.bits.source, 2) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = leq(UInt<1>(0h0), uncommonBits_16) node _T_368 = and(_T_366, _T_367) node _T_369 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_370 = and(_T_368, _T_369) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_371 = shr(io.in.a.bits.source, 2) node _T_372 = eq(_T_371, UInt<1>(0h1)) node _T_373 = leq(UInt<1>(0h0), uncommonBits_17) node _T_374 = and(_T_372, _T_373) node _T_375 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_377 = shr(io.in.a.bits.source, 2) node _T_378 = eq(_T_377, UInt<2>(0h2)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_18) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_382 = and(_T_380, _T_381) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_383 = shr(io.in.a.bits.source, 2) node _T_384 = eq(_T_383, UInt<2>(0h3)) node _T_385 = leq(UInt<1>(0h0), uncommonBits_19) node _T_386 = and(_T_384, _T_385) node _T_387 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_390 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_392 = or(_T_364, _T_370) node _T_393 = or(_T_392, _T_376) node _T_394 = or(_T_393, _T_382) node _T_395 = or(_T_394, _T_388) node _T_396 = or(_T_395, _T_389) node _T_397 = or(_T_396, _T_390) node _T_398 = or(_T_397, _T_391) node _T_399 = and(_T_363, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_402 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_403 = and(_T_401, _T_402) node _T_404 = or(UInt<1>(0h0), _T_403) node _T_405 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<13>(0h1000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = and(_T_404, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = and(_T_400, _T_411) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_412, UInt<1>(0h1), "") : assert_26 node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(source_ok, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_422 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_422, UInt<1>(0h1), "") : assert_29 node _T_426 = eq(io.in.a.bits.mask, mask) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_426, UInt<1>(0h1), "") : assert_30 node _T_430 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_430 : node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_432 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_435 = shr(io.in.a.bits.source, 2) node _T_436 = eq(_T_435, UInt<1>(0h0)) node _T_437 = leq(UInt<1>(0h0), uncommonBits_20) node _T_438 = and(_T_436, _T_437) node _T_439 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_440 = and(_T_438, _T_439) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_441 = shr(io.in.a.bits.source, 2) node _T_442 = eq(_T_441, UInt<1>(0h1)) node _T_443 = leq(UInt<1>(0h0), uncommonBits_21) node _T_444 = and(_T_442, _T_443) node _T_445 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_446 = and(_T_444, _T_445) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_447 = shr(io.in.a.bits.source, 2) node _T_448 = eq(_T_447, UInt<2>(0h2)) node _T_449 = leq(UInt<1>(0h0), uncommonBits_22) node _T_450 = and(_T_448, _T_449) node _T_451 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_452 = and(_T_450, _T_451) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_453 = shr(io.in.a.bits.source, 2) node _T_454 = eq(_T_453, UInt<2>(0h3)) node _T_455 = leq(UInt<1>(0h0), uncommonBits_23) node _T_456 = and(_T_454, _T_455) node _T_457 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_461 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_462 = or(_T_434, _T_440) node _T_463 = or(_T_462, _T_446) node _T_464 = or(_T_463, _T_452) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = or(_T_466, _T_460) node _T_468 = or(_T_467, _T_461) node _T_469 = and(_T_433, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_472 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_473 = and(_T_471, _T_472) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<13>(0h1000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = and(_T_474, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = and(_T_470, _T_481) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_482, UInt<1>(0h1), "") : assert_31 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_492, UInt<1>(0h1), "") : assert_34 node _T_496 = not(mask) node _T_497 = and(io.in.a.bits.mask, _T_496) node _T_498 = eq(_T_497, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_498, UInt<1>(0h1), "") : assert_35 node _T_502 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_502 : node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_505 = and(_T_503, _T_504) node _T_506 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<1>(0h0)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_24) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<1>(0h1)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_25) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_519 = shr(io.in.a.bits.source, 2) node _T_520 = eq(_T_519, UInt<2>(0h2)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_26) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_524 = and(_T_522, _T_523) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_525 = shr(io.in.a.bits.source, 2) node _T_526 = eq(_T_525, UInt<2>(0h3)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_27) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_533 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_534 = or(_T_506, _T_512) node _T_535 = or(_T_534, _T_518) node _T_536 = or(_T_535, _T_524) node _T_537 = or(_T_536, _T_530) node _T_538 = or(_T_537, _T_531) node _T_539 = or(_T_538, _T_532) node _T_540 = or(_T_539, _T_533) node _T_541 = and(_T_505, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_544 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = and(_T_543, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = and(_T_542, _T_550) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_551, UInt<1>(0h1), "") : assert_36 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(source_ok, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_558 = asUInt(reset) node _T_559 = eq(_T_558, UInt<1>(0h0)) when _T_559 : node _T_560 = eq(is_aligned, UInt<1>(0h0)) when _T_560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_561 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_561, UInt<1>(0h1), "") : assert_39 node _T_565 = eq(io.in.a.bits.mask, mask) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_565, UInt<1>(0h1), "") : assert_40 node _T_569 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_569 : node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_574 = shr(io.in.a.bits.source, 2) node _T_575 = eq(_T_574, UInt<1>(0h0)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_28) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_579 = and(_T_577, _T_578) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h1)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_29) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<2>(0h2)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_30) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h3)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_31) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_601 = or(_T_573, _T_579) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_591) node _T_604 = or(_T_603, _T_597) node _T_605 = or(_T_604, _T_598) node _T_606 = or(_T_605, _T_599) node _T_607 = or(_T_606, _T_600) node _T_608 = and(_T_572, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_611 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_612 = cvt(_T_611) node _T_613 = and(_T_612, asSInt(UInt<13>(0h1000))) node _T_614 = asSInt(_T_613) node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0))) node _T_616 = and(_T_610, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = and(_T_609, _T_617) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_618, UInt<1>(0h1), "") : assert_41 node _T_622 = asUInt(reset) node _T_623 = eq(_T_622, UInt<1>(0h0)) when _T_623 : node _T_624 = eq(source_ok, UInt<1>(0h0)) when _T_624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(is_aligned, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_628 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_628, UInt<1>(0h1), "") : assert_44 node _T_632 = eq(io.in.a.bits.mask, mask) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_632, UInt<1>(0h1), "") : assert_45 node _T_636 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_636 : node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_639 = and(_T_637, _T_638) node _T_640 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_641 = shr(io.in.a.bits.source, 2) node _T_642 = eq(_T_641, UInt<1>(0h0)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_32) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_646 = and(_T_644, _T_645) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_647 = shr(io.in.a.bits.source, 2) node _T_648 = eq(_T_647, UInt<1>(0h1)) node _T_649 = leq(UInt<1>(0h0), uncommonBits_33) node _T_650 = and(_T_648, _T_649) node _T_651 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_652 = and(_T_650, _T_651) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_653 = shr(io.in.a.bits.source, 2) node _T_654 = eq(_T_653, UInt<2>(0h2)) node _T_655 = leq(UInt<1>(0h0), uncommonBits_34) node _T_656 = and(_T_654, _T_655) node _T_657 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_658 = and(_T_656, _T_657) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_659 = shr(io.in.a.bits.source, 2) node _T_660 = eq(_T_659, UInt<2>(0h3)) node _T_661 = leq(UInt<1>(0h0), uncommonBits_35) node _T_662 = and(_T_660, _T_661) node _T_663 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_666 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_667 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_668 = or(_T_640, _T_646) node _T_669 = or(_T_668, _T_652) node _T_670 = or(_T_669, _T_658) node _T_671 = or(_T_670, _T_664) node _T_672 = or(_T_671, _T_665) node _T_673 = or(_T_672, _T_666) node _T_674 = or(_T_673, _T_667) node _T_675 = and(_T_639, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = and(_T_677, _T_682) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = and(_T_676, _T_684) node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(_T_685, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_685, UInt<1>(0h1), "") : assert_46 node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(source_ok, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(is_aligned, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_695 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_695, UInt<1>(0h1), "") : assert_49 node _T_699 = eq(io.in.a.bits.mask, mask) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_699, UInt<1>(0h1), "") : assert_50 node _T_703 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_703, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_707 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_707, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_711 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(source_ok_1, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_715 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_715, UInt<1>(0h1), "") : assert_54 node _T_719 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_719, UInt<1>(0h1), "") : assert_55 node _T_723 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_723, UInt<1>(0h1), "") : assert_56 node _T_727 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_727, UInt<1>(0h1), "") : assert_57 node _T_731 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_731 : node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok_1, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(sink_ok, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_738 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_738, UInt<1>(0h1), "") : assert_60 node _T_742 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_742, UInt<1>(0h1), "") : assert_61 node _T_746 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_746, UInt<1>(0h1), "") : assert_62 node _T_750 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_750, UInt<1>(0h1), "") : assert_63 node _T_754 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_755, UInt<1>(0h1), "") : assert_64 node _T_759 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_759 : node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(source_ok_1, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(sink_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_766 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(_T_766, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_766, UInt<1>(0h1), "") : assert_67 node _T_770 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_770, UInt<1>(0h1), "") : assert_68 node _T_774 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_774, UInt<1>(0h1), "") : assert_69 node _T_778 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_779 = or(_T_778, io.in.d.bits.corrupt) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_779, UInt<1>(0h1), "") : assert_70 node _T_783 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_784 = or(UInt<1>(0h0), _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_784, UInt<1>(0h1), "") : assert_71 node _T_788 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_788 : node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(source_ok_1, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_792 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(_T_792, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_792, UInt<1>(0h1), "") : assert_73 node _T_796 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_796, UInt<1>(0h1), "") : assert_74 node _T_800 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_801, UInt<1>(0h1), "") : assert_75 node _T_805 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_805 : node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(source_ok_1, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_809 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_809, UInt<1>(0h1), "") : assert_77 node _T_813 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_814 = or(_T_813, io.in.d.bits.corrupt) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_814, UInt<1>(0h1), "") : assert_78 node _T_818 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_819, UInt<1>(0h1), "") : assert_79 node _T_823 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_823 : node _T_824 = asUInt(reset) node _T_825 = eq(_T_824, UInt<1>(0h0)) when _T_825 : node _T_826 = eq(source_ok_1, UInt<1>(0h0)) when _T_826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_827 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(_T_827, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_827, UInt<1>(0h1), "") : assert_81 node _T_831 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_T_831, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_831, UInt<1>(0h1), "") : assert_82 node _T_835 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_836, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_840 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_840, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_844 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_844, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_848 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(_T_848, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_848, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_852 = eq(a_first, UInt<1>(0h0)) node _T_853 = and(io.in.a.valid, _T_852) when _T_853 : node _T_854 = eq(io.in.a.bits.opcode, opcode) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_854, UInt<1>(0h1), "") : assert_87 node _T_858 = eq(io.in.a.bits.param, param) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_858, UInt<1>(0h1), "") : assert_88 node _T_862 = eq(io.in.a.bits.size, size) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_862, UInt<1>(0h1), "") : assert_89 node _T_866 = eq(io.in.a.bits.source, source) node _T_867 = asUInt(reset) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : node _T_869 = eq(_T_866, UInt<1>(0h0)) when _T_869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_866, UInt<1>(0h1), "") : assert_90 node _T_870 = eq(io.in.a.bits.address, address) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_870, UInt<1>(0h1), "") : assert_91 node _T_874 = and(io.in.a.ready, io.in.a.valid) node _T_875 = and(_T_874, a_first) when _T_875 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_876 = eq(d_first, UInt<1>(0h0)) node _T_877 = and(io.in.d.valid, _T_876) when _T_877 : node _T_878 = eq(io.in.d.bits.opcode, opcode_1) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_878, UInt<1>(0h1), "") : assert_92 node _T_882 = eq(io.in.d.bits.param, param_1) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_882, UInt<1>(0h1), "") : assert_93 node _T_886 = eq(io.in.d.bits.size, size_1) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_886, UInt<1>(0h1), "") : assert_94 node _T_890 = eq(io.in.d.bits.source, source_1) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_890, UInt<1>(0h1), "") : assert_95 node _T_894 = eq(io.in.d.bits.sink, sink) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_894, UInt<1>(0h1), "") : assert_96 node _T_898 = eq(io.in.d.bits.denied, denied) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_898, UInt<1>(0h1), "") : assert_97 node _T_902 = and(io.in.d.ready, io.in.d.valid) node _T_903 = and(_T_902, d_first) when _T_903 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_904 = and(io.in.a.valid, a_first_1) node _T_905 = and(_T_904, UInt<1>(0h1)) when _T_905 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_906 = and(io.in.a.ready, io.in.a.valid) node _T_907 = and(_T_906, a_first_1) node _T_908 = and(_T_907, UInt<1>(0h1)) when _T_908 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_909 = dshr(inflight, io.in.a.bits.source) node _T_910 = bits(_T_909, 0, 0) node _T_911 = eq(_T_910, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_911, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_915 = and(io.in.d.valid, d_first_1) node _T_916 = and(_T_915, UInt<1>(0h1)) node _T_917 = eq(d_release_ack, UInt<1>(0h0)) node _T_918 = and(_T_916, _T_917) when _T_918 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_919 = and(io.in.d.ready, io.in.d.valid) node _T_920 = and(_T_919, d_first_1) node _T_921 = and(_T_920, UInt<1>(0h1)) node _T_922 = eq(d_release_ack, UInt<1>(0h0)) node _T_923 = and(_T_921, _T_922) when _T_923 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_924 = and(io.in.d.valid, d_first_1) node _T_925 = and(_T_924, UInt<1>(0h1)) node _T_926 = eq(d_release_ack, UInt<1>(0h0)) node _T_927 = and(_T_925, _T_926) when _T_927 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_928 = dshr(inflight, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_930, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_934 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_935 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_936 = or(_T_934, _T_935) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_936, UInt<1>(0h1), "") : assert_100 node _T_940 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_940, UInt<1>(0h1), "") : assert_101 else : node _T_944 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_945 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_946 = or(_T_944, _T_945) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_946, UInt<1>(0h1), "") : assert_102 node _T_950 = eq(io.in.d.bits.size, a_size_lookup) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_950, UInt<1>(0h1), "") : assert_103 node _T_954 = and(io.in.d.valid, d_first_1) node _T_955 = and(_T_954, a_first_1) node _T_956 = and(_T_955, io.in.a.valid) node _T_957 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_958 = and(_T_956, _T_957) node _T_959 = eq(d_release_ack, UInt<1>(0h0)) node _T_960 = and(_T_958, _T_959) when _T_960 : node _T_961 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_962 = or(_T_961, io.in.a.ready) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_962, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_124 node _T_966 = orr(inflight) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_969 = or(_T_967, _T_968) node _T_970 = lt(watchdog, plusarg_reader.out) node _T_971 = or(_T_969, _T_970) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_971, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_975 = and(io.in.a.ready, io.in.a.valid) node _T_976 = and(io.in.d.ready, io.in.d.valid) node _T_977 = or(_T_975, _T_976) when _T_977 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_978 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_979 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_980 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_981 = and(_T_979, _T_980) node _T_982 = and(_T_978, _T_981) when _T_982 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_983 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_984 = and(_T_983, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_985 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_986 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_987 = and(_T_985, _T_986) node _T_988 = and(_T_984, _T_987) when _T_988 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_989 = dshr(inflight_1, _WIRE_15.bits.source) node _T_990 = bits(_T_989, 0, 0) node _T_991 = eq(_T_990, UInt<1>(0h0)) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_991, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_995 = and(io.in.d.valid, d_first_2) node _T_996 = and(_T_995, UInt<1>(0h1)) node _T_997 = and(_T_996, d_release_ack_1) when _T_997 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_998 = and(io.in.d.ready, io.in.d.valid) node _T_999 = and(_T_998, d_first_2) node _T_1000 = and(_T_999, UInt<1>(0h1)) node _T_1001 = and(_T_1000, d_release_ack_1) when _T_1001 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1002 = and(io.in.d.valid, d_first_2) node _T_1003 = and(_T_1002, UInt<1>(0h1)) node _T_1004 = and(_T_1003, d_release_ack_1) when _T_1004 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1005 = dshr(inflight_1, io.in.d.bits.source) node _T_1006 = bits(_T_1005, 0, 0) node _T_1007 = or(_T_1006, same_cycle_resp_1) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1011 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_108 else : node _T_1015 = eq(io.in.d.bits.size, c_size_lookup) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_109 node _T_1019 = and(io.in.d.valid, d_first_2) node _T_1020 = and(_T_1019, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1021 = and(_T_1020, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1022 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = and(_T_1023, d_release_ack_1) node _T_1025 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _T_1027 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1028 = or(_T_1027, _WIRE_23.ready) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_125 node _T_1032 = orr(inflight_1) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) node _T_1034 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = lt(watchdog_1, plusarg_reader_1.out) node _T_1037 = or(_T_1035, _T_1036) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1041 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1042 = and(io.in.d.ready, io.in.d.valid) node _T_1043 = or(_T_1041, _T_1042) when _T_1043 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_975; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_128 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_145 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_128( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_145 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_146 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_146( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NullPrefetcher : input clock : Clock input reset : Reset output io : { flip mshr_avail : UInt<1>, flip req_val : UInt<1>, flip req_addr : UInt<40>, flip req_coh : { state : UInt<2>}, prefetch : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}} connect io.prefetch.valid, UInt<1>(0h0) invalidate io.prefetch.bits.is_hella invalidate io.prefetch.bits.data invalidate io.prefetch.bits.addr invalidate io.prefetch.bits.uop.debug_tsrc invalidate io.prefetch.bits.uop.debug_fsrc invalidate io.prefetch.bits.uop.bp_xcpt_if invalidate io.prefetch.bits.uop.bp_debug_if invalidate io.prefetch.bits.uop.xcpt_ma_if invalidate io.prefetch.bits.uop.xcpt_ae_if invalidate io.prefetch.bits.uop.xcpt_pf_if invalidate io.prefetch.bits.uop.fp_typ invalidate io.prefetch.bits.uop.fp_rm invalidate io.prefetch.bits.uop.fp_val invalidate io.prefetch.bits.uop.fcn_op invalidate io.prefetch.bits.uop.fcn_dw invalidate io.prefetch.bits.uop.frs3_en invalidate io.prefetch.bits.uop.lrs2_rtype invalidate io.prefetch.bits.uop.lrs1_rtype invalidate io.prefetch.bits.uop.dst_rtype invalidate io.prefetch.bits.uop.lrs3 invalidate io.prefetch.bits.uop.lrs2 invalidate io.prefetch.bits.uop.lrs1 invalidate io.prefetch.bits.uop.ldst invalidate io.prefetch.bits.uop.ldst_is_rs1 invalidate io.prefetch.bits.uop.csr_cmd invalidate io.prefetch.bits.uop.flush_on_commit invalidate io.prefetch.bits.uop.is_unique invalidate io.prefetch.bits.uop.uses_stq invalidate io.prefetch.bits.uop.uses_ldq invalidate io.prefetch.bits.uop.mem_signed invalidate io.prefetch.bits.uop.mem_size invalidate io.prefetch.bits.uop.mem_cmd invalidate io.prefetch.bits.uop.exc_cause invalidate io.prefetch.bits.uop.exception invalidate io.prefetch.bits.uop.stale_pdst invalidate io.prefetch.bits.uop.ppred_busy invalidate io.prefetch.bits.uop.prs3_busy invalidate io.prefetch.bits.uop.prs2_busy invalidate io.prefetch.bits.uop.prs1_busy invalidate io.prefetch.bits.uop.ppred invalidate io.prefetch.bits.uop.prs3 invalidate io.prefetch.bits.uop.prs2 invalidate io.prefetch.bits.uop.prs1 invalidate io.prefetch.bits.uop.pdst invalidate io.prefetch.bits.uop.rxq_idx invalidate io.prefetch.bits.uop.stq_idx invalidate io.prefetch.bits.uop.ldq_idx invalidate io.prefetch.bits.uop.rob_idx invalidate io.prefetch.bits.uop.fp_ctrl.vec invalidate io.prefetch.bits.uop.fp_ctrl.wflags invalidate io.prefetch.bits.uop.fp_ctrl.sqrt invalidate io.prefetch.bits.uop.fp_ctrl.div invalidate io.prefetch.bits.uop.fp_ctrl.fma invalidate io.prefetch.bits.uop.fp_ctrl.fastpipe invalidate io.prefetch.bits.uop.fp_ctrl.toint invalidate io.prefetch.bits.uop.fp_ctrl.fromint invalidate io.prefetch.bits.uop.fp_ctrl.typeTagOut invalidate io.prefetch.bits.uop.fp_ctrl.typeTagIn invalidate io.prefetch.bits.uop.fp_ctrl.swap23 invalidate io.prefetch.bits.uop.fp_ctrl.swap12 invalidate io.prefetch.bits.uop.fp_ctrl.ren3 invalidate io.prefetch.bits.uop.fp_ctrl.ren2 invalidate io.prefetch.bits.uop.fp_ctrl.ren1 invalidate io.prefetch.bits.uop.fp_ctrl.wen invalidate io.prefetch.bits.uop.fp_ctrl.ldst invalidate io.prefetch.bits.uop.op2_sel invalidate io.prefetch.bits.uop.op1_sel invalidate io.prefetch.bits.uop.imm_packed invalidate io.prefetch.bits.uop.pimm invalidate io.prefetch.bits.uop.imm_sel invalidate io.prefetch.bits.uop.imm_rename invalidate io.prefetch.bits.uop.taken invalidate io.prefetch.bits.uop.pc_lob invalidate io.prefetch.bits.uop.edge_inst invalidate io.prefetch.bits.uop.ftq_idx invalidate io.prefetch.bits.uop.is_mov invalidate io.prefetch.bits.uop.is_rocc invalidate io.prefetch.bits.uop.is_sys_pc2epc invalidate io.prefetch.bits.uop.is_eret invalidate io.prefetch.bits.uop.is_amo invalidate io.prefetch.bits.uop.is_sfence invalidate io.prefetch.bits.uop.is_fencei invalidate io.prefetch.bits.uop.is_fence invalidate io.prefetch.bits.uop.is_sfb invalidate io.prefetch.bits.uop.br_type invalidate io.prefetch.bits.uop.br_tag invalidate io.prefetch.bits.uop.br_mask invalidate io.prefetch.bits.uop.dis_col_sel invalidate io.prefetch.bits.uop.iw_p3_bypass_hint invalidate io.prefetch.bits.uop.iw_p2_bypass_hint invalidate io.prefetch.bits.uop.iw_p1_bypass_hint invalidate io.prefetch.bits.uop.iw_p2_speculative_child invalidate io.prefetch.bits.uop.iw_p1_speculative_child invalidate io.prefetch.bits.uop.iw_issued_partial_dgen invalidate io.prefetch.bits.uop.iw_issued_partial_agen invalidate io.prefetch.bits.uop.iw_issued invalidate io.prefetch.bits.uop.fu_code[0] invalidate io.prefetch.bits.uop.fu_code[1] invalidate io.prefetch.bits.uop.fu_code[2] invalidate io.prefetch.bits.uop.fu_code[3] invalidate io.prefetch.bits.uop.fu_code[4] invalidate io.prefetch.bits.uop.fu_code[5] invalidate io.prefetch.bits.uop.fu_code[6] invalidate io.prefetch.bits.uop.fu_code[7] invalidate io.prefetch.bits.uop.fu_code[8] invalidate io.prefetch.bits.uop.fu_code[9] invalidate io.prefetch.bits.uop.iq_type[0] invalidate io.prefetch.bits.uop.iq_type[1] invalidate io.prefetch.bits.uop.iq_type[2] invalidate io.prefetch.bits.uop.iq_type[3] invalidate io.prefetch.bits.uop.debug_pc invalidate io.prefetch.bits.uop.is_rvc invalidate io.prefetch.bits.uop.debug_inst invalidate io.prefetch.bits.uop.inst

module NullPrefetcher( // @[prefetcher.scala:39:7] input clock, // @[prefetcher.scala:39:7] input reset, // @[prefetcher.scala:39:7] input io_mshr_avail, // @[prefetcher.scala:26:14] input io_req_val, // @[prefetcher.scala:26:14] input [39:0] io_req_addr, // @[prefetcher.scala:26:14] input [1:0] io_req_coh_state, // @[prefetcher.scala:26:14] input io_prefetch_ready // @[prefetcher.scala:26:14] ); wire io_mshr_avail_0 = io_mshr_avail; // @[prefetcher.scala:39:7] wire io_req_val_0 = io_req_val; // @[prefetcher.scala:39:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[prefetcher.scala:39:7] wire [1:0] io_req_coh_state_0 = io_req_coh_state; // @[prefetcher.scala:39:7] wire io_prefetch_ready_0 = io_prefetch_ready; // @[prefetcher.scala:39:7] wire [63:0] io_prefetch_bits_uop_exc_cause = 64'h0; // @[prefetcher.scala:39:7] wire [63:0] io_prefetch_bits_data = 64'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_rob_idx = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_pdst = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_prs1 = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_prs2 = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_prs3 = 7'h0; // @[prefetcher.scala:39:7] wire [6:0] io_prefetch_bits_uop_stale_pdst = 7'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_op1_sel = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_rxq_idx = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_mem_size = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_dst_rtype = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_lrs1_rtype = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_lrs2_rtype = 2'h0; // @[prefetcher.scala:39:7] wire [1:0] io_prefetch_bits_uop_fp_typ = 2'h0; // @[prefetcher.scala:39:7] wire [19:0] io_prefetch_bits_uop_imm_packed = 20'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_pc_lob = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_ldst = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_lrs1 = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_lrs2 = 6'h0; // @[prefetcher.scala:39:7] wire [5:0] io_prefetch_bits_uop_lrs3 = 6'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_ftq_idx = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_pimm = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_ldq_idx = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_stq_idx = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_ppred = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_mem_cmd = 5'h0; // @[prefetcher.scala:39:7] wire [4:0] io_prefetch_bits_uop_fcn_op = 5'h0; // @[prefetcher.scala:39:7] wire [3:0] io_prefetch_bits_uop_br_tag = 4'h0; // @[prefetcher.scala:39:7] wire [3:0] io_prefetch_bits_uop_br_type = 4'h0; // @[prefetcher.scala:39:7] wire [15:0] io_prefetch_bits_uop_br_mask = 16'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_iw_p1_speculative_child = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_iw_p2_speculative_child = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_dis_col_sel = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_imm_sel = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_op2_sel = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_csr_cmd = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_fp_rm = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_debug_fsrc = 3'h0; // @[prefetcher.scala:39:7] wire [2:0] io_prefetch_bits_uop_debug_tsrc = 3'h0; // @[prefetcher.scala:39:7] wire [39:0] io_prefetch_bits_uop_debug_pc = 40'h0; // @[prefetcher.scala:39:7] wire [39:0] io_prefetch_bits_addr = 40'h0; // @[prefetcher.scala:39:7] wire [31:0] io_prefetch_bits_uop_inst = 32'h0; // @[prefetcher.scala:39:7] wire [31:0] io_prefetch_bits_uop_debug_inst = 32'h0; // @[prefetcher.scala:39:7] wire io_prefetch_valid = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_rvc = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_0 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_2 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iq_type_3 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_0 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_2 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_3 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_4 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_5 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_6 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_7 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_8 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fu_code_9 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_issued = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_issued_partial_agen = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_issued_partial_dgen = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_p1_bypass_hint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_p2_bypass_hint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_iw_p3_bypass_hint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_sfb = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_fence = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_fencei = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_sfence = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_amo = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_eret = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_sys_pc2epc = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_rocc = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_mov = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_edge_inst = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_taken = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_imm_rename = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ldst = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_wen = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ren1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ren2 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_ren3 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_swap12 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_swap23 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_fromint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_toint = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_fma = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_div = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_sqrt = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_wflags = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_ctrl_vec = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_prs1_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_prs2_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_prs3_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_ppred_busy = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_exception = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_mem_signed = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_uses_ldq = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_uses_stq = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_is_unique = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_flush_on_commit = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_ldst_is_rs1 = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_frs3_en = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fcn_dw = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_fp_val = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_xcpt_pf_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_xcpt_ae_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_xcpt_ma_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_bp_debug_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_uop_bp_xcpt_if = 1'h0; // @[prefetcher.scala:39:7] wire io_prefetch_bits_is_hella = 1'h0; // @[prefetcher.scala:39:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s12k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_34 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s12k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s12k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_102 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_103 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBuffer_a26d64s12k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_34 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s12k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s12k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_data (auto_out_d_bits_data), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d64s6k5z4c connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<4> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<1>(0h0)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T

module TLDToNoC( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d32s6k3z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_37 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a32d32s6k3z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a32d32s6k3z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLBuffer_a32d32s6k3z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_37 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a32d32s6k3z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a32d32s6k3z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_325 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_69 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_325( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_69 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ZstdCompressorMemWriter_1 : input clock : Clock input reset : Reset output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, l2io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip dest_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>, cmpval : UInt<64>}}, bufs_completed : UInt<64>, no_writes_inflight : UInt<1>} inst incoming_writes_Q of Queue4_WriterBundle_1 connect incoming_writes_Q.clock, clock connect incoming_writes_Q.reset, reset connect incoming_writes_Q.io.enq, io.memwrites_in inst dest_info_Q of Queue4_DstWithValInfo_5 connect dest_info_Q.clock, clock connect dest_info_Q.reset, reset connect dest_info_Q.io.enq, io.dest_info node _decompress_dest_last_fire_T = and(dest_info_Q.io.deq.ready, dest_info_Q.io.deq.valid) reg decompress_dest_last_fire : UInt<1>, clock connect decompress_dest_last_fire, _decompress_dest_last_fire_T reg decompress_dest_last_valid : UInt<1>, clock connect decompress_dest_last_valid, dest_info_Q.io.deq.valid node _decompress_dest_printhelp_T = eq(decompress_dest_last_valid, UInt<1>(0h0)) node _decompress_dest_printhelp_T_1 = or(decompress_dest_last_fire, _decompress_dest_printhelp_T) node decompress_dest_printhelp = and(dest_info_Q.io.deq.valid, _decompress_dest_printhelp_T_1) when decompress_dest_printhelp : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[config-memwriter] got dest info op: 0x%x, cmpflag 0x%x\n", dest_info_Q.io.deq.bits.op, dest_info_Q.io.deq.bits.cmpflag) : printf_1 inst buf_lens_Q of Queue10_UInt64_1 connect buf_lens_Q.clock, clock connect buf_lens_Q.reset, reset node _T_4 = and(buf_lens_Q.io.enq.ready, buf_lens_Q.io.enq.valid) when _T_4 : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits) : printf_3 regreset buf_len_tracker : UInt<64>, clock, reset, UInt<64>(0h0) node _T_9 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_9 : when incoming_writes_Q.io.deq.bits.end_of_message : connect buf_len_tracker, UInt<1>(0h0) else : node _buf_len_tracker_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_len_tracker, _buf_len_tracker_T node _T_10 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T_10 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_5 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue2_UInt8 of Queue2_UInt8_32 connect Queue2_UInt8.clock, clock connect Queue2_UInt8.reset, reset inst Queue2_UInt8_1 of Queue2_UInt8_33 connect Queue2_UInt8_1.clock, clock connect Queue2_UInt8_1.reset, reset inst Queue2_UInt8_2 of Queue2_UInt8_34 connect Queue2_UInt8_2.clock, clock connect Queue2_UInt8_2.reset, reset inst Queue2_UInt8_3 of Queue2_UInt8_35 connect Queue2_UInt8_3.clock, clock connect Queue2_UInt8_3.reset, reset inst Queue2_UInt8_4 of Queue2_UInt8_36 connect Queue2_UInt8_4.clock, clock connect Queue2_UInt8_4.reset, reset inst Queue2_UInt8_5 of Queue2_UInt8_37 connect Queue2_UInt8_5.clock, clock connect Queue2_UInt8_5.reset, reset inst Queue2_UInt8_6 of Queue2_UInt8_38 connect Queue2_UInt8_6.clock, clock connect Queue2_UInt8_6.reset, reset inst Queue2_UInt8_7 of Queue2_UInt8_39 connect Queue2_UInt8_7.clock, clock connect Queue2_UInt8_7.reset, reset inst Queue2_UInt8_8 of Queue2_UInt8_40 connect Queue2_UInt8_8.clock, clock connect Queue2_UInt8_8.reset, reset inst Queue2_UInt8_9 of Queue2_UInt8_41 connect Queue2_UInt8_9.clock, clock connect Queue2_UInt8_9.reset, reset inst Queue2_UInt8_10 of Queue2_UInt8_42 connect Queue2_UInt8_10.clock, clock connect Queue2_UInt8_10.reset, reset inst Queue2_UInt8_11 of Queue2_UInt8_43 connect Queue2_UInt8_11.clock, clock connect Queue2_UInt8_11.reset, reset inst Queue2_UInt8_12 of Queue2_UInt8_44 connect Queue2_UInt8_12.clock, clock connect Queue2_UInt8_12.reset, reset inst Queue2_UInt8_13 of Queue2_UInt8_45 connect Queue2_UInt8_13.clock, clock connect Queue2_UInt8_13.reset, reset inst Queue2_UInt8_14 of Queue2_UInt8_46 connect Queue2_UInt8_14.clock, clock connect Queue2_UInt8_14.reset, reset inst Queue2_UInt8_15 of Queue2_UInt8_47 connect Queue2_UInt8_15.clock, clock connect Queue2_UInt8_15.reset, reset inst Queue2_UInt8_16 of Queue2_UInt8_48 connect Queue2_UInt8_16.clock, clock connect Queue2_UInt8_16.reset, reset inst Queue2_UInt8_17 of Queue2_UInt8_49 connect Queue2_UInt8_17.clock, clock connect Queue2_UInt8_17.reset, reset inst Queue2_UInt8_18 of Queue2_UInt8_50 connect Queue2_UInt8_18.clock, clock connect Queue2_UInt8_18.reset, reset inst Queue2_UInt8_19 of Queue2_UInt8_51 connect Queue2_UInt8_19.clock, clock connect Queue2_UInt8_19.reset, reset inst Queue2_UInt8_20 of Queue2_UInt8_52 connect Queue2_UInt8_20.clock, clock connect Queue2_UInt8_20.reset, reset inst Queue2_UInt8_21 of Queue2_UInt8_53 connect Queue2_UInt8_21.clock, clock connect Queue2_UInt8_21.reset, reset inst Queue2_UInt8_22 of Queue2_UInt8_54 connect Queue2_UInt8_22.clock, clock connect Queue2_UInt8_22.reset, reset inst Queue2_UInt8_23 of Queue2_UInt8_55 connect Queue2_UInt8_23.clock, clock connect Queue2_UInt8_23.reset, reset inst Queue2_UInt8_24 of Queue2_UInt8_56 connect Queue2_UInt8_24.clock, clock connect Queue2_UInt8_24.reset, reset inst Queue2_UInt8_25 of Queue2_UInt8_57 connect Queue2_UInt8_25.clock, clock connect Queue2_UInt8_25.reset, reset inst Queue2_UInt8_26 of Queue2_UInt8_58 connect Queue2_UInt8_26.clock, clock connect Queue2_UInt8_26.reset, reset inst Queue2_UInt8_27 of Queue2_UInt8_59 connect Queue2_UInt8_27.clock, clock connect Queue2_UInt8_27.reset, reset inst Queue2_UInt8_28 of Queue2_UInt8_60 connect Queue2_UInt8_28.clock, clock connect Queue2_UInt8_28.reset, reset inst Queue2_UInt8_29 of Queue2_UInt8_61 connect Queue2_UInt8_29.clock, clock connect Queue2_UInt8_29.reset, reset inst Queue2_UInt8_30 of Queue2_UInt8_62 connect Queue2_UInt8_30.clock, clock connect Queue2_UInt8_30.reset, reset inst Queue2_UInt8_31 of Queue2_UInt8_63 connect Queue2_UInt8_31.clock, clock connect Queue2_UInt8_31.reset, reset connect Queue2_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue2_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_15 = eq(UInt<1>(0h0), idx) when _T_15 : node _T_16 = shl(UInt<1>(0h0), 3) node _T_17 = dshr(incoming_writes_Q.io.deq.bits.data, _T_16) node _T_18 = bits(_T_17, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_18 node _T_19 = eq(UInt<1>(0h1), idx) when _T_19 : node _T_20 = shl(UInt<1>(0h0), 3) node _T_21 = dshr(incoming_writes_Q.io.deq.bits.data, _T_20) node _T_22 = bits(_T_21, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_22 node _T_23 = eq(UInt<2>(0h2), idx) when _T_23 : node _T_24 = shl(UInt<1>(0h0), 3) node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24) node _T_26 = bits(_T_25, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_26 node _T_27 = eq(UInt<2>(0h3), idx) when _T_27 : node _T_28 = shl(UInt<1>(0h0), 3) node _T_29 = dshr(incoming_writes_Q.io.deq.bits.data, _T_28) node _T_30 = bits(_T_29, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_30 node _T_31 = eq(UInt<3>(0h4), idx) when _T_31 : node _T_32 = shl(UInt<1>(0h0), 3) node _T_33 = dshr(incoming_writes_Q.io.deq.bits.data, _T_32) node _T_34 = bits(_T_33, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_34 node _T_35 = eq(UInt<3>(0h5), idx) when _T_35 : node _T_36 = shl(UInt<1>(0h0), 3) node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36) node _T_38 = bits(_T_37, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_38 node _T_39 = eq(UInt<3>(0h6), idx) when _T_39 : node _T_40 = shl(UInt<1>(0h0), 3) node _T_41 = dshr(incoming_writes_Q.io.deq.bits.data, _T_40) node _T_42 = bits(_T_41, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_42 node _T_43 = eq(UInt<3>(0h7), idx) when _T_43 : node _T_44 = shl(UInt<1>(0h0), 3) node _T_45 = dshr(incoming_writes_Q.io.deq.bits.data, _T_44) node _T_46 = bits(_T_45, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_46 node _T_47 = eq(UInt<4>(0h8), idx) when _T_47 : node _T_48 = shl(UInt<1>(0h0), 3) node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48) node _T_50 = bits(_T_49, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_50 node _T_51 = eq(UInt<4>(0h9), idx) when _T_51 : node _T_52 = shl(UInt<1>(0h0), 3) node _T_53 = dshr(incoming_writes_Q.io.deq.bits.data, _T_52) node _T_54 = bits(_T_53, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_54 node _T_55 = eq(UInt<4>(0ha), idx) when _T_55 : node _T_56 = shl(UInt<1>(0h0), 3) node _T_57 = dshr(incoming_writes_Q.io.deq.bits.data, _T_56) node _T_58 = bits(_T_57, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_58 node _T_59 = eq(UInt<4>(0hb), idx) when _T_59 : node _T_60 = shl(UInt<1>(0h0), 3) node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60) node _T_62 = bits(_T_61, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_62 node _T_63 = eq(UInt<4>(0hc), idx) when _T_63 : node _T_64 = shl(UInt<1>(0h0), 3) node _T_65 = dshr(incoming_writes_Q.io.deq.bits.data, _T_64) node _T_66 = bits(_T_65, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_66 node _T_67 = eq(UInt<4>(0hd), idx) when _T_67 : node _T_68 = shl(UInt<1>(0h0), 3) node _T_69 = dshr(incoming_writes_Q.io.deq.bits.data, _T_68) node _T_70 = bits(_T_69, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_70 node _T_71 = eq(UInt<4>(0he), idx) when _T_71 : node _T_72 = shl(UInt<1>(0h0), 3) node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72) node _T_74 = bits(_T_73, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_74 node _T_75 = eq(UInt<4>(0hf), idx) when _T_75 : node _T_76 = shl(UInt<1>(0h0), 3) node _T_77 = dshr(incoming_writes_Q.io.deq.bits.data, _T_76) node _T_78 = bits(_T_77, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_78 node _T_79 = eq(UInt<5>(0h10), idx) when _T_79 : node _T_80 = shl(UInt<1>(0h0), 3) node _T_81 = dshr(incoming_writes_Q.io.deq.bits.data, _T_80) node _T_82 = bits(_T_81, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_82 node _T_83 = eq(UInt<5>(0h11), idx) when _T_83 : node _T_84 = shl(UInt<1>(0h0), 3) node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84) node _T_86 = bits(_T_85, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_86 node _T_87 = eq(UInt<5>(0h12), idx) when _T_87 : node _T_88 = shl(UInt<1>(0h0), 3) node _T_89 = dshr(incoming_writes_Q.io.deq.bits.data, _T_88) node _T_90 = bits(_T_89, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_90 node _T_91 = eq(UInt<5>(0h13), idx) when _T_91 : node _T_92 = shl(UInt<1>(0h0), 3) node _T_93 = dshr(incoming_writes_Q.io.deq.bits.data, _T_92) node _T_94 = bits(_T_93, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_94 node _T_95 = eq(UInt<5>(0h14), idx) when _T_95 : node _T_96 = shl(UInt<1>(0h0), 3) node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96) node _T_98 = bits(_T_97, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_98 node _T_99 = eq(UInt<5>(0h15), idx) when _T_99 : node _T_100 = shl(UInt<1>(0h0), 3) node _T_101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_100) node _T_102 = bits(_T_101, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_102 node _T_103 = eq(UInt<5>(0h16), idx) when _T_103 : node _T_104 = shl(UInt<1>(0h0), 3) node _T_105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_104) node _T_106 = bits(_T_105, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_106 node _T_107 = eq(UInt<5>(0h17), idx) when _T_107 : node _T_108 = shl(UInt<1>(0h0), 3) node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108) node _T_110 = bits(_T_109, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_110 node _T_111 = eq(UInt<5>(0h18), idx) when _T_111 : node _T_112 = shl(UInt<1>(0h0), 3) node _T_113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_112) node _T_114 = bits(_T_113, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_114 node _T_115 = eq(UInt<5>(0h19), idx) when _T_115 : node _T_116 = shl(UInt<1>(0h0), 3) node _T_117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_116) node _T_118 = bits(_T_117, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_118 node _T_119 = eq(UInt<5>(0h1a), idx) when _T_119 : node _T_120 = shl(UInt<1>(0h0), 3) node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120) node _T_122 = bits(_T_121, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_122 node _T_123 = eq(UInt<5>(0h1b), idx) when _T_123 : node _T_124 = shl(UInt<1>(0h0), 3) node _T_125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_124) node _T_126 = bits(_T_125, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_126 node _T_127 = eq(UInt<5>(0h1c), idx) when _T_127 : node _T_128 = shl(UInt<1>(0h0), 3) node _T_129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_128) node _T_130 = bits(_T_129, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_130 node _T_131 = eq(UInt<5>(0h1d), idx) when _T_131 : node _T_132 = shl(UInt<1>(0h0), 3) node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132) node _T_134 = bits(_T_133, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_134 node _T_135 = eq(UInt<5>(0h1e), idx) when _T_135 : node _T_136 = shl(UInt<1>(0h0), 3) node _T_137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_136) node _T_138 = bits(_T_137, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_138 node _T_139 = eq(UInt<5>(0h1f), idx) when _T_139 : node _T_140 = shl(UInt<1>(0h0), 3) node _T_141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_140) node _T_142 = bits(_T_141, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_142 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_143 = eq(UInt<1>(0h0), idx_1) when _T_143 : node _T_144 = shl(UInt<1>(0h1), 3) node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144) node _T_146 = bits(_T_145, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_146 node _T_147 = eq(UInt<1>(0h1), idx_1) when _T_147 : node _T_148 = shl(UInt<1>(0h1), 3) node _T_149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_148) node _T_150 = bits(_T_149, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_150 node _T_151 = eq(UInt<2>(0h2), idx_1) when _T_151 : node _T_152 = shl(UInt<1>(0h1), 3) node _T_153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_152) node _T_154 = bits(_T_153, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_154 node _T_155 = eq(UInt<2>(0h3), idx_1) when _T_155 : node _T_156 = shl(UInt<1>(0h1), 3) node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156) node _T_158 = bits(_T_157, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_158 node _T_159 = eq(UInt<3>(0h4), idx_1) when _T_159 : node _T_160 = shl(UInt<1>(0h1), 3) node _T_161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_160) node _T_162 = bits(_T_161, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_162 node _T_163 = eq(UInt<3>(0h5), idx_1) when _T_163 : node _T_164 = shl(UInt<1>(0h1), 3) node _T_165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_164) node _T_166 = bits(_T_165, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_166 node _T_167 = eq(UInt<3>(0h6), idx_1) when _T_167 : node _T_168 = shl(UInt<1>(0h1), 3) node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168) node _T_170 = bits(_T_169, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_170 node _T_171 = eq(UInt<3>(0h7), idx_1) when _T_171 : node _T_172 = shl(UInt<1>(0h1), 3) node _T_173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_172) node _T_174 = bits(_T_173, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_174 node _T_175 = eq(UInt<4>(0h8), idx_1) when _T_175 : node _T_176 = shl(UInt<1>(0h1), 3) node _T_177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_176) node _T_178 = bits(_T_177, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_178 node _T_179 = eq(UInt<4>(0h9), idx_1) when _T_179 : node _T_180 = shl(UInt<1>(0h1), 3) node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180) node _T_182 = bits(_T_181, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_182 node _T_183 = eq(UInt<4>(0ha), idx_1) when _T_183 : node _T_184 = shl(UInt<1>(0h1), 3) node _T_185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_184) node _T_186 = bits(_T_185, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_186 node _T_187 = eq(UInt<4>(0hb), idx_1) when _T_187 : node _T_188 = shl(UInt<1>(0h1), 3) node _T_189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_188) node _T_190 = bits(_T_189, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_190 node _T_191 = eq(UInt<4>(0hc), idx_1) when _T_191 : node _T_192 = shl(UInt<1>(0h1), 3) node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192) node _T_194 = bits(_T_193, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_194 node _T_195 = eq(UInt<4>(0hd), idx_1) when _T_195 : node _T_196 = shl(UInt<1>(0h1), 3) node _T_197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_196) node _T_198 = bits(_T_197, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_198 node _T_199 = eq(UInt<4>(0he), idx_1) when _T_199 : node _T_200 = shl(UInt<1>(0h1), 3) node _T_201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_200) node _T_202 = bits(_T_201, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_202 node _T_203 = eq(UInt<4>(0hf), idx_1) when _T_203 : node _T_204 = shl(UInt<1>(0h1), 3) node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204) node _T_206 = bits(_T_205, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_206 node _T_207 = eq(UInt<5>(0h10), idx_1) when _T_207 : node _T_208 = shl(UInt<1>(0h1), 3) node _T_209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_208) node _T_210 = bits(_T_209, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_210 node _T_211 = eq(UInt<5>(0h11), idx_1) when _T_211 : node _T_212 = shl(UInt<1>(0h1), 3) node _T_213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_212) node _T_214 = bits(_T_213, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_214 node _T_215 = eq(UInt<5>(0h12), idx_1) when _T_215 : node _T_216 = shl(UInt<1>(0h1), 3) node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216) node _T_218 = bits(_T_217, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_218 node _T_219 = eq(UInt<5>(0h13), idx_1) when _T_219 : node _T_220 = shl(UInt<1>(0h1), 3) node _T_221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_220) node _T_222 = bits(_T_221, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_222 node _T_223 = eq(UInt<5>(0h14), idx_1) when _T_223 : node _T_224 = shl(UInt<1>(0h1), 3) node _T_225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_224) node _T_226 = bits(_T_225, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_226 node _T_227 = eq(UInt<5>(0h15), idx_1) when _T_227 : node _T_228 = shl(UInt<1>(0h1), 3) node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228) node _T_230 = bits(_T_229, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_230 node _T_231 = eq(UInt<5>(0h16), idx_1) when _T_231 : node _T_232 = shl(UInt<1>(0h1), 3) node _T_233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_232) node _T_234 = bits(_T_233, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_234 node _T_235 = eq(UInt<5>(0h17), idx_1) when _T_235 : node _T_236 = shl(UInt<1>(0h1), 3) node _T_237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_236) node _T_238 = bits(_T_237, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_238 node _T_239 = eq(UInt<5>(0h18), idx_1) when _T_239 : node _T_240 = shl(UInt<1>(0h1), 3) node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240) node _T_242 = bits(_T_241, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_242 node _T_243 = eq(UInt<5>(0h19), idx_1) when _T_243 : node _T_244 = shl(UInt<1>(0h1), 3) node _T_245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_244) node _T_246 = bits(_T_245, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_246 node _T_247 = eq(UInt<5>(0h1a), idx_1) when _T_247 : node _T_248 = shl(UInt<1>(0h1), 3) node _T_249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_248) node _T_250 = bits(_T_249, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_250 node _T_251 = eq(UInt<5>(0h1b), idx_1) when _T_251 : node _T_252 = shl(UInt<1>(0h1), 3) node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252) node _T_254 = bits(_T_253, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_254 node _T_255 = eq(UInt<5>(0h1c), idx_1) when _T_255 : node _T_256 = shl(UInt<1>(0h1), 3) node _T_257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_256) node _T_258 = bits(_T_257, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_258 node _T_259 = eq(UInt<5>(0h1d), idx_1) when _T_259 : node _T_260 = shl(UInt<1>(0h1), 3) node _T_261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_260) node _T_262 = bits(_T_261, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_262 node _T_263 = eq(UInt<5>(0h1e), idx_1) when _T_263 : node _T_264 = shl(UInt<1>(0h1), 3) node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264) node _T_266 = bits(_T_265, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_266 node _T_267 = eq(UInt<5>(0h1f), idx_1) when _T_267 : node _T_268 = shl(UInt<1>(0h1), 3) node _T_269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_268) node _T_270 = bits(_T_269, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_270 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_271 = eq(UInt<1>(0h0), idx_2) when _T_271 : node _T_272 = shl(UInt<2>(0h2), 3) node _T_273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_272) node _T_274 = bits(_T_273, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_274 node _T_275 = eq(UInt<1>(0h1), idx_2) when _T_275 : node _T_276 = shl(UInt<2>(0h2), 3) node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276) node _T_278 = bits(_T_277, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_278 node _T_279 = eq(UInt<2>(0h2), idx_2) when _T_279 : node _T_280 = shl(UInt<2>(0h2), 3) node _T_281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_280) node _T_282 = bits(_T_281, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_282 node _T_283 = eq(UInt<2>(0h3), idx_2) when _T_283 : node _T_284 = shl(UInt<2>(0h2), 3) node _T_285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_284) node _T_286 = bits(_T_285, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_286 node _T_287 = eq(UInt<3>(0h4), idx_2) when _T_287 : node _T_288 = shl(UInt<2>(0h2), 3) node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288) node _T_290 = bits(_T_289, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_290 node _T_291 = eq(UInt<3>(0h5), idx_2) when _T_291 : node _T_292 = shl(UInt<2>(0h2), 3) node _T_293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_292) node _T_294 = bits(_T_293, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_294 node _T_295 = eq(UInt<3>(0h6), idx_2) when _T_295 : node _T_296 = shl(UInt<2>(0h2), 3) node _T_297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_296) node _T_298 = bits(_T_297, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_298 node _T_299 = eq(UInt<3>(0h7), idx_2) when _T_299 : node _T_300 = shl(UInt<2>(0h2), 3) node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300) node _T_302 = bits(_T_301, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_302 node _T_303 = eq(UInt<4>(0h8), idx_2) when _T_303 : node _T_304 = shl(UInt<2>(0h2), 3) node _T_305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_304) node _T_306 = bits(_T_305, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_306 node _T_307 = eq(UInt<4>(0h9), idx_2) when _T_307 : node _T_308 = shl(UInt<2>(0h2), 3) node _T_309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_308) node _T_310 = bits(_T_309, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_310 node _T_311 = eq(UInt<4>(0ha), idx_2) when _T_311 : node _T_312 = shl(UInt<2>(0h2), 3) node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312) node _T_314 = bits(_T_313, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_314 node _T_315 = eq(UInt<4>(0hb), idx_2) when _T_315 : node _T_316 = shl(UInt<2>(0h2), 3) node _T_317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_316) node _T_318 = bits(_T_317, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_318 node _T_319 = eq(UInt<4>(0hc), idx_2) when _T_319 : node _T_320 = shl(UInt<2>(0h2), 3) node _T_321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_320) node _T_322 = bits(_T_321, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_322 node _T_323 = eq(UInt<4>(0hd), idx_2) when _T_323 : node _T_324 = shl(UInt<2>(0h2), 3) node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324) node _T_326 = bits(_T_325, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_326 node _T_327 = eq(UInt<4>(0he), idx_2) when _T_327 : node _T_328 = shl(UInt<2>(0h2), 3) node _T_329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_328) node _T_330 = bits(_T_329, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_330 node _T_331 = eq(UInt<4>(0hf), idx_2) when _T_331 : node _T_332 = shl(UInt<2>(0h2), 3) node _T_333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_332) node _T_334 = bits(_T_333, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_334 node _T_335 = eq(UInt<5>(0h10), idx_2) when _T_335 : node _T_336 = shl(UInt<2>(0h2), 3) node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336) node _T_338 = bits(_T_337, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_338 node _T_339 = eq(UInt<5>(0h11), idx_2) when _T_339 : node _T_340 = shl(UInt<2>(0h2), 3) node _T_341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_340) node _T_342 = bits(_T_341, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_342 node _T_343 = eq(UInt<5>(0h12), idx_2) when _T_343 : node _T_344 = shl(UInt<2>(0h2), 3) node _T_345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_344) node _T_346 = bits(_T_345, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_346 node _T_347 = eq(UInt<5>(0h13), idx_2) when _T_347 : node _T_348 = shl(UInt<2>(0h2), 3) node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348) node _T_350 = bits(_T_349, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_350 node _T_351 = eq(UInt<5>(0h14), idx_2) when _T_351 : node _T_352 = shl(UInt<2>(0h2), 3) node _T_353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_352) node _T_354 = bits(_T_353, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_354 node _T_355 = eq(UInt<5>(0h15), idx_2) when _T_355 : node _T_356 = shl(UInt<2>(0h2), 3) node _T_357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_356) node _T_358 = bits(_T_357, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_358 node _T_359 = eq(UInt<5>(0h16), idx_2) when _T_359 : node _T_360 = shl(UInt<2>(0h2), 3) node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360) node _T_362 = bits(_T_361, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_362 node _T_363 = eq(UInt<5>(0h17), idx_2) when _T_363 : node _T_364 = shl(UInt<2>(0h2), 3) node _T_365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_364) node _T_366 = bits(_T_365, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_366 node _T_367 = eq(UInt<5>(0h18), idx_2) when _T_367 : node _T_368 = shl(UInt<2>(0h2), 3) node _T_369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_368) node _T_370 = bits(_T_369, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_370 node _T_371 = eq(UInt<5>(0h19), idx_2) when _T_371 : node _T_372 = shl(UInt<2>(0h2), 3) node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372) node _T_374 = bits(_T_373, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_374 node _T_375 = eq(UInt<5>(0h1a), idx_2) when _T_375 : node _T_376 = shl(UInt<2>(0h2), 3) node _T_377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_376) node _T_378 = bits(_T_377, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_378 node _T_379 = eq(UInt<5>(0h1b), idx_2) when _T_379 : node _T_380 = shl(UInt<2>(0h2), 3) node _T_381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_380) node _T_382 = bits(_T_381, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_382 node _T_383 = eq(UInt<5>(0h1c), idx_2) when _T_383 : node _T_384 = shl(UInt<2>(0h2), 3) node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384) node _T_386 = bits(_T_385, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_386 node _T_387 = eq(UInt<5>(0h1d), idx_2) when _T_387 : node _T_388 = shl(UInt<2>(0h2), 3) node _T_389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_388) node _T_390 = bits(_T_389, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_390 node _T_391 = eq(UInt<5>(0h1e), idx_2) when _T_391 : node _T_392 = shl(UInt<2>(0h2), 3) node _T_393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_392) node _T_394 = bits(_T_393, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_394 node _T_395 = eq(UInt<5>(0h1f), idx_2) when _T_395 : node _T_396 = shl(UInt<2>(0h2), 3) node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396) node _T_398 = bits(_T_397, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_398 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_399 = eq(UInt<1>(0h0), idx_3) when _T_399 : node _T_400 = shl(UInt<2>(0h3), 3) node _T_401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_400) node _T_402 = bits(_T_401, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_402 node _T_403 = eq(UInt<1>(0h1), idx_3) when _T_403 : node _T_404 = shl(UInt<2>(0h3), 3) node _T_405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_404) node _T_406 = bits(_T_405, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_406 node _T_407 = eq(UInt<2>(0h2), idx_3) when _T_407 : node _T_408 = shl(UInt<2>(0h3), 3) node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408) node _T_410 = bits(_T_409, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_410 node _T_411 = eq(UInt<2>(0h3), idx_3) when _T_411 : node _T_412 = shl(UInt<2>(0h3), 3) node _T_413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_412) node _T_414 = bits(_T_413, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_414 node _T_415 = eq(UInt<3>(0h4), idx_3) when _T_415 : node _T_416 = shl(UInt<2>(0h3), 3) node _T_417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_416) node _T_418 = bits(_T_417, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_418 node _T_419 = eq(UInt<3>(0h5), idx_3) when _T_419 : node _T_420 = shl(UInt<2>(0h3), 3) node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420) node _T_422 = bits(_T_421, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_422 node _T_423 = eq(UInt<3>(0h6), idx_3) when _T_423 : node _T_424 = shl(UInt<2>(0h3), 3) node _T_425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_424) node _T_426 = bits(_T_425, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_426 node _T_427 = eq(UInt<3>(0h7), idx_3) when _T_427 : node _T_428 = shl(UInt<2>(0h3), 3) node _T_429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_428) node _T_430 = bits(_T_429, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_430 node _T_431 = eq(UInt<4>(0h8), idx_3) when _T_431 : node _T_432 = shl(UInt<2>(0h3), 3) node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432) node _T_434 = bits(_T_433, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_434 node _T_435 = eq(UInt<4>(0h9), idx_3) when _T_435 : node _T_436 = shl(UInt<2>(0h3), 3) node _T_437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_436) node _T_438 = bits(_T_437, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_438 node _T_439 = eq(UInt<4>(0ha), idx_3) when _T_439 : node _T_440 = shl(UInt<2>(0h3), 3) node _T_441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_440) node _T_442 = bits(_T_441, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_442 node _T_443 = eq(UInt<4>(0hb), idx_3) when _T_443 : node _T_444 = shl(UInt<2>(0h3), 3) node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444) node _T_446 = bits(_T_445, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_446 node _T_447 = eq(UInt<4>(0hc), idx_3) when _T_447 : node _T_448 = shl(UInt<2>(0h3), 3) node _T_449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_448) node _T_450 = bits(_T_449, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_450 node _T_451 = eq(UInt<4>(0hd), idx_3) when _T_451 : node _T_452 = shl(UInt<2>(0h3), 3) node _T_453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_452) node _T_454 = bits(_T_453, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_454 node _T_455 = eq(UInt<4>(0he), idx_3) when _T_455 : node _T_456 = shl(UInt<2>(0h3), 3) node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456) node _T_458 = bits(_T_457, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_458 node _T_459 = eq(UInt<4>(0hf), idx_3) when _T_459 : node _T_460 = shl(UInt<2>(0h3), 3) node _T_461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_460) node _T_462 = bits(_T_461, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_462 node _T_463 = eq(UInt<5>(0h10), idx_3) when _T_463 : node _T_464 = shl(UInt<2>(0h3), 3) node _T_465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_464) node _T_466 = bits(_T_465, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_466 node _T_467 = eq(UInt<5>(0h11), idx_3) when _T_467 : node _T_468 = shl(UInt<2>(0h3), 3) node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468) node _T_470 = bits(_T_469, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_470 node _T_471 = eq(UInt<5>(0h12), idx_3) when _T_471 : node _T_472 = shl(UInt<2>(0h3), 3) node _T_473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_472) node _T_474 = bits(_T_473, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_474 node _T_475 = eq(UInt<5>(0h13), idx_3) when _T_475 : node _T_476 = shl(UInt<2>(0h3), 3) node _T_477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_476) node _T_478 = bits(_T_477, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_478 node _T_479 = eq(UInt<5>(0h14), idx_3) when _T_479 : node _T_480 = shl(UInt<2>(0h3), 3) node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480) node _T_482 = bits(_T_481, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_482 node _T_483 = eq(UInt<5>(0h15), idx_3) when _T_483 : node _T_484 = shl(UInt<2>(0h3), 3) node _T_485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_484) node _T_486 = bits(_T_485, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_486 node _T_487 = eq(UInt<5>(0h16), idx_3) when _T_487 : node _T_488 = shl(UInt<2>(0h3), 3) node _T_489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_488) node _T_490 = bits(_T_489, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_490 node _T_491 = eq(UInt<5>(0h17), idx_3) when _T_491 : node _T_492 = shl(UInt<2>(0h3), 3) node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492) node _T_494 = bits(_T_493, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_494 node _T_495 = eq(UInt<5>(0h18), idx_3) when _T_495 : node _T_496 = shl(UInt<2>(0h3), 3) node _T_497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_496) node _T_498 = bits(_T_497, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_498 node _T_499 = eq(UInt<5>(0h19), idx_3) when _T_499 : node _T_500 = shl(UInt<2>(0h3), 3) node _T_501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_500) node _T_502 = bits(_T_501, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_502 node _T_503 = eq(UInt<5>(0h1a), idx_3) when _T_503 : node _T_504 = shl(UInt<2>(0h3), 3) node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504) node _T_506 = bits(_T_505, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_506 node _T_507 = eq(UInt<5>(0h1b), idx_3) when _T_507 : node _T_508 = shl(UInt<2>(0h3), 3) node _T_509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_508) node _T_510 = bits(_T_509, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_510 node _T_511 = eq(UInt<5>(0h1c), idx_3) when _T_511 : node _T_512 = shl(UInt<2>(0h3), 3) node _T_513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_512) node _T_514 = bits(_T_513, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_514 node _T_515 = eq(UInt<5>(0h1d), idx_3) when _T_515 : node _T_516 = shl(UInt<2>(0h3), 3) node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516) node _T_518 = bits(_T_517, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_518 node _T_519 = eq(UInt<5>(0h1e), idx_3) when _T_519 : node _T_520 = shl(UInt<2>(0h3), 3) node _T_521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_520) node _T_522 = bits(_T_521, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_522 node _T_523 = eq(UInt<5>(0h1f), idx_3) when _T_523 : node _T_524 = shl(UInt<2>(0h3), 3) node _T_525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_524) node _T_526 = bits(_T_525, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_526 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_527 = eq(UInt<1>(0h0), idx_4) when _T_527 : node _T_528 = shl(UInt<3>(0h4), 3) node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528) node _T_530 = bits(_T_529, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_530 node _T_531 = eq(UInt<1>(0h1), idx_4) when _T_531 : node _T_532 = shl(UInt<3>(0h4), 3) node _T_533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_532) node _T_534 = bits(_T_533, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_534 node _T_535 = eq(UInt<2>(0h2), idx_4) when _T_535 : node _T_536 = shl(UInt<3>(0h4), 3) node _T_537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_536) node _T_538 = bits(_T_537, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_538 node _T_539 = eq(UInt<2>(0h3), idx_4) when _T_539 : node _T_540 = shl(UInt<3>(0h4), 3) node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540) node _T_542 = bits(_T_541, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_542 node _T_543 = eq(UInt<3>(0h4), idx_4) when _T_543 : node _T_544 = shl(UInt<3>(0h4), 3) node _T_545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_544) node _T_546 = bits(_T_545, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_546 node _T_547 = eq(UInt<3>(0h5), idx_4) when _T_547 : node _T_548 = shl(UInt<3>(0h4), 3) node _T_549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_548) node _T_550 = bits(_T_549, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_550 node _T_551 = eq(UInt<3>(0h6), idx_4) when _T_551 : node _T_552 = shl(UInt<3>(0h4), 3) node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552) node _T_554 = bits(_T_553, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_554 node _T_555 = eq(UInt<3>(0h7), idx_4) when _T_555 : node _T_556 = shl(UInt<3>(0h4), 3) node _T_557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_556) node _T_558 = bits(_T_557, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_558 node _T_559 = eq(UInt<4>(0h8), idx_4) when _T_559 : node _T_560 = shl(UInt<3>(0h4), 3) node _T_561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_560) node _T_562 = bits(_T_561, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_562 node _T_563 = eq(UInt<4>(0h9), idx_4) when _T_563 : node _T_564 = shl(UInt<3>(0h4), 3) node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564) node _T_566 = bits(_T_565, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_566 node _T_567 = eq(UInt<4>(0ha), idx_4) when _T_567 : node _T_568 = shl(UInt<3>(0h4), 3) node _T_569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_568) node _T_570 = bits(_T_569, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_570 node _T_571 = eq(UInt<4>(0hb), idx_4) when _T_571 : node _T_572 = shl(UInt<3>(0h4), 3) node _T_573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_572) node _T_574 = bits(_T_573, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_574 node _T_575 = eq(UInt<4>(0hc), idx_4) when _T_575 : node _T_576 = shl(UInt<3>(0h4), 3) node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576) node _T_578 = bits(_T_577, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_578 node _T_579 = eq(UInt<4>(0hd), idx_4) when _T_579 : node _T_580 = shl(UInt<3>(0h4), 3) node _T_581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_580) node _T_582 = bits(_T_581, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_582 node _T_583 = eq(UInt<4>(0he), idx_4) when _T_583 : node _T_584 = shl(UInt<3>(0h4), 3) node _T_585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_584) node _T_586 = bits(_T_585, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_586 node _T_587 = eq(UInt<4>(0hf), idx_4) when _T_587 : node _T_588 = shl(UInt<3>(0h4), 3) node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588) node _T_590 = bits(_T_589, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_590 node _T_591 = eq(UInt<5>(0h10), idx_4) when _T_591 : node _T_592 = shl(UInt<3>(0h4), 3) node _T_593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_592) node _T_594 = bits(_T_593, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_594 node _T_595 = eq(UInt<5>(0h11), idx_4) when _T_595 : node _T_596 = shl(UInt<3>(0h4), 3) node _T_597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_596) node _T_598 = bits(_T_597, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_598 node _T_599 = eq(UInt<5>(0h12), idx_4) when _T_599 : node _T_600 = shl(UInt<3>(0h4), 3) node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600) node _T_602 = bits(_T_601, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_602 node _T_603 = eq(UInt<5>(0h13), idx_4) when _T_603 : node _T_604 = shl(UInt<3>(0h4), 3) node _T_605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_604) node _T_606 = bits(_T_605, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_606 node _T_607 = eq(UInt<5>(0h14), idx_4) when _T_607 : node _T_608 = shl(UInt<3>(0h4), 3) node _T_609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_608) node _T_610 = bits(_T_609, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_610 node _T_611 = eq(UInt<5>(0h15), idx_4) when _T_611 : node _T_612 = shl(UInt<3>(0h4), 3) node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612) node _T_614 = bits(_T_613, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_614 node _T_615 = eq(UInt<5>(0h16), idx_4) when _T_615 : node _T_616 = shl(UInt<3>(0h4), 3) node _T_617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_616) node _T_618 = bits(_T_617, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_618 node _T_619 = eq(UInt<5>(0h17), idx_4) when _T_619 : node _T_620 = shl(UInt<3>(0h4), 3) node _T_621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_620) node _T_622 = bits(_T_621, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_622 node _T_623 = eq(UInt<5>(0h18), idx_4) when _T_623 : node _T_624 = shl(UInt<3>(0h4), 3) node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624) node _T_626 = bits(_T_625, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_626 node _T_627 = eq(UInt<5>(0h19), idx_4) when _T_627 : node _T_628 = shl(UInt<3>(0h4), 3) node _T_629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_628) node _T_630 = bits(_T_629, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_630 node _T_631 = eq(UInt<5>(0h1a), idx_4) when _T_631 : node _T_632 = shl(UInt<3>(0h4), 3) node _T_633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_632) node _T_634 = bits(_T_633, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_634 node _T_635 = eq(UInt<5>(0h1b), idx_4) when _T_635 : node _T_636 = shl(UInt<3>(0h4), 3) node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636) node _T_638 = bits(_T_637, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_638 node _T_639 = eq(UInt<5>(0h1c), idx_4) when _T_639 : node _T_640 = shl(UInt<3>(0h4), 3) node _T_641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_640) node _T_642 = bits(_T_641, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_642 node _T_643 = eq(UInt<5>(0h1d), idx_4) when _T_643 : node _T_644 = shl(UInt<3>(0h4), 3) node _T_645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_644) node _T_646 = bits(_T_645, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_646 node _T_647 = eq(UInt<5>(0h1e), idx_4) when _T_647 : node _T_648 = shl(UInt<3>(0h4), 3) node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648) node _T_650 = bits(_T_649, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_650 node _T_651 = eq(UInt<5>(0h1f), idx_4) when _T_651 : node _T_652 = shl(UInt<3>(0h4), 3) node _T_653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_652) node _T_654 = bits(_T_653, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_654 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_655 = eq(UInt<1>(0h0), idx_5) when _T_655 : node _T_656 = shl(UInt<3>(0h5), 3) node _T_657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_656) node _T_658 = bits(_T_657, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_658 node _T_659 = eq(UInt<1>(0h1), idx_5) when _T_659 : node _T_660 = shl(UInt<3>(0h5), 3) node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660) node _T_662 = bits(_T_661, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_662 node _T_663 = eq(UInt<2>(0h2), idx_5) when _T_663 : node _T_664 = shl(UInt<3>(0h5), 3) node _T_665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_664) node _T_666 = bits(_T_665, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_666 node _T_667 = eq(UInt<2>(0h3), idx_5) when _T_667 : node _T_668 = shl(UInt<3>(0h5), 3) node _T_669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_668) node _T_670 = bits(_T_669, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_670 node _T_671 = eq(UInt<3>(0h4), idx_5) when _T_671 : node _T_672 = shl(UInt<3>(0h5), 3) node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672) node _T_674 = bits(_T_673, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_674 node _T_675 = eq(UInt<3>(0h5), idx_5) when _T_675 : node _T_676 = shl(UInt<3>(0h5), 3) node _T_677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_676) node _T_678 = bits(_T_677, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_678 node _T_679 = eq(UInt<3>(0h6), idx_5) when _T_679 : node _T_680 = shl(UInt<3>(0h5), 3) node _T_681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_680) node _T_682 = bits(_T_681, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_682 node _T_683 = eq(UInt<3>(0h7), idx_5) when _T_683 : node _T_684 = shl(UInt<3>(0h5), 3) node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684) node _T_686 = bits(_T_685, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_686 node _T_687 = eq(UInt<4>(0h8), idx_5) when _T_687 : node _T_688 = shl(UInt<3>(0h5), 3) node _T_689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_688) node _T_690 = bits(_T_689, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_690 node _T_691 = eq(UInt<4>(0h9), idx_5) when _T_691 : node _T_692 = shl(UInt<3>(0h5), 3) node _T_693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_692) node _T_694 = bits(_T_693, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_694 node _T_695 = eq(UInt<4>(0ha), idx_5) when _T_695 : node _T_696 = shl(UInt<3>(0h5), 3) node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696) node _T_698 = bits(_T_697, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_698 node _T_699 = eq(UInt<4>(0hb), idx_5) when _T_699 : node _T_700 = shl(UInt<3>(0h5), 3) node _T_701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_700) node _T_702 = bits(_T_701, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_702 node _T_703 = eq(UInt<4>(0hc), idx_5) when _T_703 : node _T_704 = shl(UInt<3>(0h5), 3) node _T_705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_704) node _T_706 = bits(_T_705, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_706 node _T_707 = eq(UInt<4>(0hd), idx_5) when _T_707 : node _T_708 = shl(UInt<3>(0h5), 3) node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708) node _T_710 = bits(_T_709, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_710 node _T_711 = eq(UInt<4>(0he), idx_5) when _T_711 : node _T_712 = shl(UInt<3>(0h5), 3) node _T_713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_712) node _T_714 = bits(_T_713, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_714 node _T_715 = eq(UInt<4>(0hf), idx_5) when _T_715 : node _T_716 = shl(UInt<3>(0h5), 3) node _T_717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_716) node _T_718 = bits(_T_717, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_718 node _T_719 = eq(UInt<5>(0h10), idx_5) when _T_719 : node _T_720 = shl(UInt<3>(0h5), 3) node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720) node _T_722 = bits(_T_721, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_722 node _T_723 = eq(UInt<5>(0h11), idx_5) when _T_723 : node _T_724 = shl(UInt<3>(0h5), 3) node _T_725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_724) node _T_726 = bits(_T_725, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_726 node _T_727 = eq(UInt<5>(0h12), idx_5) when _T_727 : node _T_728 = shl(UInt<3>(0h5), 3) node _T_729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_728) node _T_730 = bits(_T_729, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_730 node _T_731 = eq(UInt<5>(0h13), idx_5) when _T_731 : node _T_732 = shl(UInt<3>(0h5), 3) node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732) node _T_734 = bits(_T_733, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_734 node _T_735 = eq(UInt<5>(0h14), idx_5) when _T_735 : node _T_736 = shl(UInt<3>(0h5), 3) node _T_737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_736) node _T_738 = bits(_T_737, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_738 node _T_739 = eq(UInt<5>(0h15), idx_5) when _T_739 : node _T_740 = shl(UInt<3>(0h5), 3) node _T_741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_740) node _T_742 = bits(_T_741, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_742 node _T_743 = eq(UInt<5>(0h16), idx_5) when _T_743 : node _T_744 = shl(UInt<3>(0h5), 3) node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744) node _T_746 = bits(_T_745, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_746 node _T_747 = eq(UInt<5>(0h17), idx_5) when _T_747 : node _T_748 = shl(UInt<3>(0h5), 3) node _T_749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_748) node _T_750 = bits(_T_749, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_750 node _T_751 = eq(UInt<5>(0h18), idx_5) when _T_751 : node _T_752 = shl(UInt<3>(0h5), 3) node _T_753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_752) node _T_754 = bits(_T_753, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_754 node _T_755 = eq(UInt<5>(0h19), idx_5) when _T_755 : node _T_756 = shl(UInt<3>(0h5), 3) node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756) node _T_758 = bits(_T_757, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_758 node _T_759 = eq(UInt<5>(0h1a), idx_5) when _T_759 : node _T_760 = shl(UInt<3>(0h5), 3) node _T_761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_760) node _T_762 = bits(_T_761, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_762 node _T_763 = eq(UInt<5>(0h1b), idx_5) when _T_763 : node _T_764 = shl(UInt<3>(0h5), 3) node _T_765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_764) node _T_766 = bits(_T_765, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_766 node _T_767 = eq(UInt<5>(0h1c), idx_5) when _T_767 : node _T_768 = shl(UInt<3>(0h5), 3) node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768) node _T_770 = bits(_T_769, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_770 node _T_771 = eq(UInt<5>(0h1d), idx_5) when _T_771 : node _T_772 = shl(UInt<3>(0h5), 3) node _T_773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_772) node _T_774 = bits(_T_773, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_774 node _T_775 = eq(UInt<5>(0h1e), idx_5) when _T_775 : node _T_776 = shl(UInt<3>(0h5), 3) node _T_777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_776) node _T_778 = bits(_T_777, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_778 node _T_779 = eq(UInt<5>(0h1f), idx_5) when _T_779 : node _T_780 = shl(UInt<3>(0h5), 3) node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780) node _T_782 = bits(_T_781, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_782 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_783 = eq(UInt<1>(0h0), idx_6) when _T_783 : node _T_784 = shl(UInt<3>(0h6), 3) node _T_785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_784) node _T_786 = bits(_T_785, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_786 node _T_787 = eq(UInt<1>(0h1), idx_6) when _T_787 : node _T_788 = shl(UInt<3>(0h6), 3) node _T_789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_788) node _T_790 = bits(_T_789, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_790 node _T_791 = eq(UInt<2>(0h2), idx_6) when _T_791 : node _T_792 = shl(UInt<3>(0h6), 3) node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792) node _T_794 = bits(_T_793, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_794 node _T_795 = eq(UInt<2>(0h3), idx_6) when _T_795 : node _T_796 = shl(UInt<3>(0h6), 3) node _T_797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_796) node _T_798 = bits(_T_797, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_798 node _T_799 = eq(UInt<3>(0h4), idx_6) when _T_799 : node _T_800 = shl(UInt<3>(0h6), 3) node _T_801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_800) node _T_802 = bits(_T_801, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_802 node _T_803 = eq(UInt<3>(0h5), idx_6) when _T_803 : node _T_804 = shl(UInt<3>(0h6), 3) node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804) node _T_806 = bits(_T_805, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_806 node _T_807 = eq(UInt<3>(0h6), idx_6) when _T_807 : node _T_808 = shl(UInt<3>(0h6), 3) node _T_809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_808) node _T_810 = bits(_T_809, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_810 node _T_811 = eq(UInt<3>(0h7), idx_6) when _T_811 : node _T_812 = shl(UInt<3>(0h6), 3) node _T_813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_812) node _T_814 = bits(_T_813, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_814 node _T_815 = eq(UInt<4>(0h8), idx_6) when _T_815 : node _T_816 = shl(UInt<3>(0h6), 3) node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816) node _T_818 = bits(_T_817, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_818 node _T_819 = eq(UInt<4>(0h9), idx_6) when _T_819 : node _T_820 = shl(UInt<3>(0h6), 3) node _T_821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_820) node _T_822 = bits(_T_821, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_822 node _T_823 = eq(UInt<4>(0ha), idx_6) when _T_823 : node _T_824 = shl(UInt<3>(0h6), 3) node _T_825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_824) node _T_826 = bits(_T_825, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_826 node _T_827 = eq(UInt<4>(0hb), idx_6) when _T_827 : node _T_828 = shl(UInt<3>(0h6), 3) node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828) node _T_830 = bits(_T_829, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_830 node _T_831 = eq(UInt<4>(0hc), idx_6) when _T_831 : node _T_832 = shl(UInt<3>(0h6), 3) node _T_833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_832) node _T_834 = bits(_T_833, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_834 node _T_835 = eq(UInt<4>(0hd), idx_6) when _T_835 : node _T_836 = shl(UInt<3>(0h6), 3) node _T_837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_836) node _T_838 = bits(_T_837, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_838 node _T_839 = eq(UInt<4>(0he), idx_6) when _T_839 : node _T_840 = shl(UInt<3>(0h6), 3) node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840) node _T_842 = bits(_T_841, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_842 node _T_843 = eq(UInt<4>(0hf), idx_6) when _T_843 : node _T_844 = shl(UInt<3>(0h6), 3) node _T_845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_844) node _T_846 = bits(_T_845, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_846 node _T_847 = eq(UInt<5>(0h10), idx_6) when _T_847 : node _T_848 = shl(UInt<3>(0h6), 3) node _T_849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_848) node _T_850 = bits(_T_849, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_850 node _T_851 = eq(UInt<5>(0h11), idx_6) when _T_851 : node _T_852 = shl(UInt<3>(0h6), 3) node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852) node _T_854 = bits(_T_853, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_854 node _T_855 = eq(UInt<5>(0h12), idx_6) when _T_855 : node _T_856 = shl(UInt<3>(0h6), 3) node _T_857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_856) node _T_858 = bits(_T_857, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_858 node _T_859 = eq(UInt<5>(0h13), idx_6) when _T_859 : node _T_860 = shl(UInt<3>(0h6), 3) node _T_861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_860) node _T_862 = bits(_T_861, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_862 node _T_863 = eq(UInt<5>(0h14), idx_6) when _T_863 : node _T_864 = shl(UInt<3>(0h6), 3) node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864) node _T_866 = bits(_T_865, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_866 node _T_867 = eq(UInt<5>(0h15), idx_6) when _T_867 : node _T_868 = shl(UInt<3>(0h6), 3) node _T_869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_868) node _T_870 = bits(_T_869, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_870 node _T_871 = eq(UInt<5>(0h16), idx_6) when _T_871 : node _T_872 = shl(UInt<3>(0h6), 3) node _T_873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_872) node _T_874 = bits(_T_873, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_874 node _T_875 = eq(UInt<5>(0h17), idx_6) when _T_875 : node _T_876 = shl(UInt<3>(0h6), 3) node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876) node _T_878 = bits(_T_877, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_878 node _T_879 = eq(UInt<5>(0h18), idx_6) when _T_879 : node _T_880 = shl(UInt<3>(0h6), 3) node _T_881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_880) node _T_882 = bits(_T_881, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_882 node _T_883 = eq(UInt<5>(0h19), idx_6) when _T_883 : node _T_884 = shl(UInt<3>(0h6), 3) node _T_885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_884) node _T_886 = bits(_T_885, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_886 node _T_887 = eq(UInt<5>(0h1a), idx_6) when _T_887 : node _T_888 = shl(UInt<3>(0h6), 3) node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888) node _T_890 = bits(_T_889, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_890 node _T_891 = eq(UInt<5>(0h1b), idx_6) when _T_891 : node _T_892 = shl(UInt<3>(0h6), 3) node _T_893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_892) node _T_894 = bits(_T_893, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_894 node _T_895 = eq(UInt<5>(0h1c), idx_6) when _T_895 : node _T_896 = shl(UInt<3>(0h6), 3) node _T_897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_896) node _T_898 = bits(_T_897, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_898 node _T_899 = eq(UInt<5>(0h1d), idx_6) when _T_899 : node _T_900 = shl(UInt<3>(0h6), 3) node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900) node _T_902 = bits(_T_901, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_902 node _T_903 = eq(UInt<5>(0h1e), idx_6) when _T_903 : node _T_904 = shl(UInt<3>(0h6), 3) node _T_905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_904) node _T_906 = bits(_T_905, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_906 node _T_907 = eq(UInt<5>(0h1f), idx_6) when _T_907 : node _T_908 = shl(UInt<3>(0h6), 3) node _T_909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_908) node _T_910 = bits(_T_909, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_910 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_911 = eq(UInt<1>(0h0), idx_7) when _T_911 : node _T_912 = shl(UInt<3>(0h7), 3) node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912) node _T_914 = bits(_T_913, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_914 node _T_915 = eq(UInt<1>(0h1), idx_7) when _T_915 : node _T_916 = shl(UInt<3>(0h7), 3) node _T_917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_916) node _T_918 = bits(_T_917, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_918 node _T_919 = eq(UInt<2>(0h2), idx_7) when _T_919 : node _T_920 = shl(UInt<3>(0h7), 3) node _T_921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_920) node _T_922 = bits(_T_921, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_922 node _T_923 = eq(UInt<2>(0h3), idx_7) when _T_923 : node _T_924 = shl(UInt<3>(0h7), 3) node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924) node _T_926 = bits(_T_925, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_926 node _T_927 = eq(UInt<3>(0h4), idx_7) when _T_927 : node _T_928 = shl(UInt<3>(0h7), 3) node _T_929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_928) node _T_930 = bits(_T_929, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_930 node _T_931 = eq(UInt<3>(0h5), idx_7) when _T_931 : node _T_932 = shl(UInt<3>(0h7), 3) node _T_933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_932) node _T_934 = bits(_T_933, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_934 node _T_935 = eq(UInt<3>(0h6), idx_7) when _T_935 : node _T_936 = shl(UInt<3>(0h7), 3) node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936) node _T_938 = bits(_T_937, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_938 node _T_939 = eq(UInt<3>(0h7), idx_7) when _T_939 : node _T_940 = shl(UInt<3>(0h7), 3) node _T_941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_940) node _T_942 = bits(_T_941, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_942 node _T_943 = eq(UInt<4>(0h8), idx_7) when _T_943 : node _T_944 = shl(UInt<3>(0h7), 3) node _T_945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_944) node _T_946 = bits(_T_945, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_946 node _T_947 = eq(UInt<4>(0h9), idx_7) when _T_947 : node _T_948 = shl(UInt<3>(0h7), 3) node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948) node _T_950 = bits(_T_949, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_950 node _T_951 = eq(UInt<4>(0ha), idx_7) when _T_951 : node _T_952 = shl(UInt<3>(0h7), 3) node _T_953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_952) node _T_954 = bits(_T_953, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_954 node _T_955 = eq(UInt<4>(0hb), idx_7) when _T_955 : node _T_956 = shl(UInt<3>(0h7), 3) node _T_957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_956) node _T_958 = bits(_T_957, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_958 node _T_959 = eq(UInt<4>(0hc), idx_7) when _T_959 : node _T_960 = shl(UInt<3>(0h7), 3) node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960) node _T_962 = bits(_T_961, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_962 node _T_963 = eq(UInt<4>(0hd), idx_7) when _T_963 : node _T_964 = shl(UInt<3>(0h7), 3) node _T_965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_964) node _T_966 = bits(_T_965, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_966 node _T_967 = eq(UInt<4>(0he), idx_7) when _T_967 : node _T_968 = shl(UInt<3>(0h7), 3) node _T_969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_968) node _T_970 = bits(_T_969, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_970 node _T_971 = eq(UInt<4>(0hf), idx_7) when _T_971 : node _T_972 = shl(UInt<3>(0h7), 3) node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972) node _T_974 = bits(_T_973, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_974 node _T_975 = eq(UInt<5>(0h10), idx_7) when _T_975 : node _T_976 = shl(UInt<3>(0h7), 3) node _T_977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_976) node _T_978 = bits(_T_977, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_978 node _T_979 = eq(UInt<5>(0h11), idx_7) when _T_979 : node _T_980 = shl(UInt<3>(0h7), 3) node _T_981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_980) node _T_982 = bits(_T_981, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_982 node _T_983 = eq(UInt<5>(0h12), idx_7) when _T_983 : node _T_984 = shl(UInt<3>(0h7), 3) node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984) node _T_986 = bits(_T_985, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_986 node _T_987 = eq(UInt<5>(0h13), idx_7) when _T_987 : node _T_988 = shl(UInt<3>(0h7), 3) node _T_989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_988) node _T_990 = bits(_T_989, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_990 node _T_991 = eq(UInt<5>(0h14), idx_7) when _T_991 : node _T_992 = shl(UInt<3>(0h7), 3) node _T_993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_992) node _T_994 = bits(_T_993, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_994 node _T_995 = eq(UInt<5>(0h15), idx_7) when _T_995 : node _T_996 = shl(UInt<3>(0h7), 3) node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996) node _T_998 = bits(_T_997, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_998 node _T_999 = eq(UInt<5>(0h16), idx_7) when _T_999 : node _T_1000 = shl(UInt<3>(0h7), 3) node _T_1001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1000) node _T_1002 = bits(_T_1001, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1002 node _T_1003 = eq(UInt<5>(0h17), idx_7) when _T_1003 : node _T_1004 = shl(UInt<3>(0h7), 3) node _T_1005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1004) node _T_1006 = bits(_T_1005, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1006 node _T_1007 = eq(UInt<5>(0h18), idx_7) when _T_1007 : node _T_1008 = shl(UInt<3>(0h7), 3) node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008) node _T_1010 = bits(_T_1009, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1010 node _T_1011 = eq(UInt<5>(0h19), idx_7) when _T_1011 : node _T_1012 = shl(UInt<3>(0h7), 3) node _T_1013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1012) node _T_1014 = bits(_T_1013, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1014 node _T_1015 = eq(UInt<5>(0h1a), idx_7) when _T_1015 : node _T_1016 = shl(UInt<3>(0h7), 3) node _T_1017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1016) node _T_1018 = bits(_T_1017, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1018 node _T_1019 = eq(UInt<5>(0h1b), idx_7) when _T_1019 : node _T_1020 = shl(UInt<3>(0h7), 3) node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020) node _T_1022 = bits(_T_1021, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1022 node _T_1023 = eq(UInt<5>(0h1c), idx_7) when _T_1023 : node _T_1024 = shl(UInt<3>(0h7), 3) node _T_1025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1024) node _T_1026 = bits(_T_1025, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1026 node _T_1027 = eq(UInt<5>(0h1d), idx_7) when _T_1027 : node _T_1028 = shl(UInt<3>(0h7), 3) node _T_1029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1028) node _T_1030 = bits(_T_1029, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1030 node _T_1031 = eq(UInt<5>(0h1e), idx_7) when _T_1031 : node _T_1032 = shl(UInt<3>(0h7), 3) node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032) node _T_1034 = bits(_T_1033, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1034 node _T_1035 = eq(UInt<5>(0h1f), idx_7) when _T_1035 : node _T_1036 = shl(UInt<3>(0h7), 3) node _T_1037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1036) node _T_1038 = bits(_T_1037, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1038 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_1039 = eq(UInt<1>(0h0), idx_8) when _T_1039 : node _T_1040 = shl(UInt<4>(0h8), 3) node _T_1041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1040) node _T_1042 = bits(_T_1041, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1042 node _T_1043 = eq(UInt<1>(0h1), idx_8) when _T_1043 : node _T_1044 = shl(UInt<4>(0h8), 3) node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044) node _T_1046 = bits(_T_1045, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1046 node _T_1047 = eq(UInt<2>(0h2), idx_8) when _T_1047 : node _T_1048 = shl(UInt<4>(0h8), 3) node _T_1049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1048) node _T_1050 = bits(_T_1049, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1050 node _T_1051 = eq(UInt<2>(0h3), idx_8) when _T_1051 : node _T_1052 = shl(UInt<4>(0h8), 3) node _T_1053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1052) node _T_1054 = bits(_T_1053, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1054 node _T_1055 = eq(UInt<3>(0h4), idx_8) when _T_1055 : node _T_1056 = shl(UInt<4>(0h8), 3) node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056) node _T_1058 = bits(_T_1057, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1058 node _T_1059 = eq(UInt<3>(0h5), idx_8) when _T_1059 : node _T_1060 = shl(UInt<4>(0h8), 3) node _T_1061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1060) node _T_1062 = bits(_T_1061, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1062 node _T_1063 = eq(UInt<3>(0h6), idx_8) when _T_1063 : node _T_1064 = shl(UInt<4>(0h8), 3) node _T_1065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1064) node _T_1066 = bits(_T_1065, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1066 node _T_1067 = eq(UInt<3>(0h7), idx_8) when _T_1067 : node _T_1068 = shl(UInt<4>(0h8), 3) node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068) node _T_1070 = bits(_T_1069, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1070 node _T_1071 = eq(UInt<4>(0h8), idx_8) when _T_1071 : node _T_1072 = shl(UInt<4>(0h8), 3) node _T_1073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1072) node _T_1074 = bits(_T_1073, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1074 node _T_1075 = eq(UInt<4>(0h9), idx_8) when _T_1075 : node _T_1076 = shl(UInt<4>(0h8), 3) node _T_1077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1076) node _T_1078 = bits(_T_1077, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1078 node _T_1079 = eq(UInt<4>(0ha), idx_8) when _T_1079 : node _T_1080 = shl(UInt<4>(0h8), 3) node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080) node _T_1082 = bits(_T_1081, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1082 node _T_1083 = eq(UInt<4>(0hb), idx_8) when _T_1083 : node _T_1084 = shl(UInt<4>(0h8), 3) node _T_1085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1084) node _T_1086 = bits(_T_1085, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1086 node _T_1087 = eq(UInt<4>(0hc), idx_8) when _T_1087 : node _T_1088 = shl(UInt<4>(0h8), 3) node _T_1089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1088) node _T_1090 = bits(_T_1089, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1090 node _T_1091 = eq(UInt<4>(0hd), idx_8) when _T_1091 : node _T_1092 = shl(UInt<4>(0h8), 3) node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092) node _T_1094 = bits(_T_1093, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1094 node _T_1095 = eq(UInt<4>(0he), idx_8) when _T_1095 : node _T_1096 = shl(UInt<4>(0h8), 3) node _T_1097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1096) node _T_1098 = bits(_T_1097, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1098 node _T_1099 = eq(UInt<4>(0hf), idx_8) when _T_1099 : node _T_1100 = shl(UInt<4>(0h8), 3) node _T_1101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1100) node _T_1102 = bits(_T_1101, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1102 node _T_1103 = eq(UInt<5>(0h10), idx_8) when _T_1103 : node _T_1104 = shl(UInt<4>(0h8), 3) node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104) node _T_1106 = bits(_T_1105, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1106 node _T_1107 = eq(UInt<5>(0h11), idx_8) when _T_1107 : node _T_1108 = shl(UInt<4>(0h8), 3) node _T_1109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1108) node _T_1110 = bits(_T_1109, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1110 node _T_1111 = eq(UInt<5>(0h12), idx_8) when _T_1111 : node _T_1112 = shl(UInt<4>(0h8), 3) node _T_1113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1112) node _T_1114 = bits(_T_1113, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1114 node _T_1115 = eq(UInt<5>(0h13), idx_8) when _T_1115 : node _T_1116 = shl(UInt<4>(0h8), 3) node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116) node _T_1118 = bits(_T_1117, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1118 node _T_1119 = eq(UInt<5>(0h14), idx_8) when _T_1119 : node _T_1120 = shl(UInt<4>(0h8), 3) node _T_1121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1120) node _T_1122 = bits(_T_1121, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1122 node _T_1123 = eq(UInt<5>(0h15), idx_8) when _T_1123 : node _T_1124 = shl(UInt<4>(0h8), 3) node _T_1125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1124) node _T_1126 = bits(_T_1125, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1126 node _T_1127 = eq(UInt<5>(0h16), idx_8) when _T_1127 : node _T_1128 = shl(UInt<4>(0h8), 3) node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128) node _T_1130 = bits(_T_1129, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1130 node _T_1131 = eq(UInt<5>(0h17), idx_8) when _T_1131 : node _T_1132 = shl(UInt<4>(0h8), 3) node _T_1133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1132) node _T_1134 = bits(_T_1133, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1134 node _T_1135 = eq(UInt<5>(0h18), idx_8) when _T_1135 : node _T_1136 = shl(UInt<4>(0h8), 3) node _T_1137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1136) node _T_1138 = bits(_T_1137, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1138 node _T_1139 = eq(UInt<5>(0h19), idx_8) when _T_1139 : node _T_1140 = shl(UInt<4>(0h8), 3) node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140) node _T_1142 = bits(_T_1141, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1142 node _T_1143 = eq(UInt<5>(0h1a), idx_8) when _T_1143 : node _T_1144 = shl(UInt<4>(0h8), 3) node _T_1145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1144) node _T_1146 = bits(_T_1145, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1146 node _T_1147 = eq(UInt<5>(0h1b), idx_8) when _T_1147 : node _T_1148 = shl(UInt<4>(0h8), 3) node _T_1149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1148) node _T_1150 = bits(_T_1149, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1150 node _T_1151 = eq(UInt<5>(0h1c), idx_8) when _T_1151 : node _T_1152 = shl(UInt<4>(0h8), 3) node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152) node _T_1154 = bits(_T_1153, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1154 node _T_1155 = eq(UInt<5>(0h1d), idx_8) when _T_1155 : node _T_1156 = shl(UInt<4>(0h8), 3) node _T_1157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1156) node _T_1158 = bits(_T_1157, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1158 node _T_1159 = eq(UInt<5>(0h1e), idx_8) when _T_1159 : node _T_1160 = shl(UInt<4>(0h8), 3) node _T_1161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1160) node _T_1162 = bits(_T_1161, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1162 node _T_1163 = eq(UInt<5>(0h1f), idx_8) when _T_1163 : node _T_1164 = shl(UInt<4>(0h8), 3) node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164) node _T_1166 = bits(_T_1165, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1166 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_1167 = eq(UInt<1>(0h0), idx_9) when _T_1167 : node _T_1168 = shl(UInt<4>(0h9), 3) node _T_1169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1168) node _T_1170 = bits(_T_1169, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1170 node _T_1171 = eq(UInt<1>(0h1), idx_9) when _T_1171 : node _T_1172 = shl(UInt<4>(0h9), 3) node _T_1173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1172) node _T_1174 = bits(_T_1173, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1174 node _T_1175 = eq(UInt<2>(0h2), idx_9) when _T_1175 : node _T_1176 = shl(UInt<4>(0h9), 3) node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176) node _T_1178 = bits(_T_1177, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1178 node _T_1179 = eq(UInt<2>(0h3), idx_9) when _T_1179 : node _T_1180 = shl(UInt<4>(0h9), 3) node _T_1181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1180) node _T_1182 = bits(_T_1181, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1182 node _T_1183 = eq(UInt<3>(0h4), idx_9) when _T_1183 : node _T_1184 = shl(UInt<4>(0h9), 3) node _T_1185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1184) node _T_1186 = bits(_T_1185, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1186 node _T_1187 = eq(UInt<3>(0h5), idx_9) when _T_1187 : node _T_1188 = shl(UInt<4>(0h9), 3) node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188) node _T_1190 = bits(_T_1189, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1190 node _T_1191 = eq(UInt<3>(0h6), idx_9) when _T_1191 : node _T_1192 = shl(UInt<4>(0h9), 3) node _T_1193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1192) node _T_1194 = bits(_T_1193, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1194 node _T_1195 = eq(UInt<3>(0h7), idx_9) when _T_1195 : node _T_1196 = shl(UInt<4>(0h9), 3) node _T_1197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1196) node _T_1198 = bits(_T_1197, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1198 node _T_1199 = eq(UInt<4>(0h8), idx_9) when _T_1199 : node _T_1200 = shl(UInt<4>(0h9), 3) node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200) node _T_1202 = bits(_T_1201, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1202 node _T_1203 = eq(UInt<4>(0h9), idx_9) when _T_1203 : node _T_1204 = shl(UInt<4>(0h9), 3) node _T_1205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1204) node _T_1206 = bits(_T_1205, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1206 node _T_1207 = eq(UInt<4>(0ha), idx_9) when _T_1207 : node _T_1208 = shl(UInt<4>(0h9), 3) node _T_1209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1208) node _T_1210 = bits(_T_1209, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1210 node _T_1211 = eq(UInt<4>(0hb), idx_9) when _T_1211 : node _T_1212 = shl(UInt<4>(0h9), 3) node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212) node _T_1214 = bits(_T_1213, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1214 node _T_1215 = eq(UInt<4>(0hc), idx_9) when _T_1215 : node _T_1216 = shl(UInt<4>(0h9), 3) node _T_1217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1216) node _T_1218 = bits(_T_1217, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1218 node _T_1219 = eq(UInt<4>(0hd), idx_9) when _T_1219 : node _T_1220 = shl(UInt<4>(0h9), 3) node _T_1221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1220) node _T_1222 = bits(_T_1221, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1222 node _T_1223 = eq(UInt<4>(0he), idx_9) when _T_1223 : node _T_1224 = shl(UInt<4>(0h9), 3) node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224) node _T_1226 = bits(_T_1225, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1226 node _T_1227 = eq(UInt<4>(0hf), idx_9) when _T_1227 : node _T_1228 = shl(UInt<4>(0h9), 3) node _T_1229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1228) node _T_1230 = bits(_T_1229, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1230 node _T_1231 = eq(UInt<5>(0h10), idx_9) when _T_1231 : node _T_1232 = shl(UInt<4>(0h9), 3) node _T_1233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1232) node _T_1234 = bits(_T_1233, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1234 node _T_1235 = eq(UInt<5>(0h11), idx_9) when _T_1235 : node _T_1236 = shl(UInt<4>(0h9), 3) node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236) node _T_1238 = bits(_T_1237, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1238 node _T_1239 = eq(UInt<5>(0h12), idx_9) when _T_1239 : node _T_1240 = shl(UInt<4>(0h9), 3) node _T_1241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1240) node _T_1242 = bits(_T_1241, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1242 node _T_1243 = eq(UInt<5>(0h13), idx_9) when _T_1243 : node _T_1244 = shl(UInt<4>(0h9), 3) node _T_1245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1244) node _T_1246 = bits(_T_1245, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1246 node _T_1247 = eq(UInt<5>(0h14), idx_9) when _T_1247 : node _T_1248 = shl(UInt<4>(0h9), 3) node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248) node _T_1250 = bits(_T_1249, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1250 node _T_1251 = eq(UInt<5>(0h15), idx_9) when _T_1251 : node _T_1252 = shl(UInt<4>(0h9), 3) node _T_1253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1252) node _T_1254 = bits(_T_1253, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1254 node _T_1255 = eq(UInt<5>(0h16), idx_9) when _T_1255 : node _T_1256 = shl(UInt<4>(0h9), 3) node _T_1257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1256) node _T_1258 = bits(_T_1257, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1258 node _T_1259 = eq(UInt<5>(0h17), idx_9) when _T_1259 : node _T_1260 = shl(UInt<4>(0h9), 3) node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260) node _T_1262 = bits(_T_1261, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1262 node _T_1263 = eq(UInt<5>(0h18), idx_9) when _T_1263 : node _T_1264 = shl(UInt<4>(0h9), 3) node _T_1265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1264) node _T_1266 = bits(_T_1265, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1266 node _T_1267 = eq(UInt<5>(0h19), idx_9) when _T_1267 : node _T_1268 = shl(UInt<4>(0h9), 3) node _T_1269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1268) node _T_1270 = bits(_T_1269, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1270 node _T_1271 = eq(UInt<5>(0h1a), idx_9) when _T_1271 : node _T_1272 = shl(UInt<4>(0h9), 3) node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272) node _T_1274 = bits(_T_1273, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1274 node _T_1275 = eq(UInt<5>(0h1b), idx_9) when _T_1275 : node _T_1276 = shl(UInt<4>(0h9), 3) node _T_1277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1276) node _T_1278 = bits(_T_1277, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1278 node _T_1279 = eq(UInt<5>(0h1c), idx_9) when _T_1279 : node _T_1280 = shl(UInt<4>(0h9), 3) node _T_1281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1280) node _T_1282 = bits(_T_1281, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1282 node _T_1283 = eq(UInt<5>(0h1d), idx_9) when _T_1283 : node _T_1284 = shl(UInt<4>(0h9), 3) node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284) node _T_1286 = bits(_T_1285, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1286 node _T_1287 = eq(UInt<5>(0h1e), idx_9) when _T_1287 : node _T_1288 = shl(UInt<4>(0h9), 3) node _T_1289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1288) node _T_1290 = bits(_T_1289, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1290 node _T_1291 = eq(UInt<5>(0h1f), idx_9) when _T_1291 : node _T_1292 = shl(UInt<4>(0h9), 3) node _T_1293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1292) node _T_1294 = bits(_T_1293, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1294 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_1295 = eq(UInt<1>(0h0), idx_10) when _T_1295 : node _T_1296 = shl(UInt<4>(0ha), 3) node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296) node _T_1298 = bits(_T_1297, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1298 node _T_1299 = eq(UInt<1>(0h1), idx_10) when _T_1299 : node _T_1300 = shl(UInt<4>(0ha), 3) node _T_1301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1300) node _T_1302 = bits(_T_1301, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1302 node _T_1303 = eq(UInt<2>(0h2), idx_10) when _T_1303 : node _T_1304 = shl(UInt<4>(0ha), 3) node _T_1305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1304) node _T_1306 = bits(_T_1305, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1306 node _T_1307 = eq(UInt<2>(0h3), idx_10) when _T_1307 : node _T_1308 = shl(UInt<4>(0ha), 3) node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308) node _T_1310 = bits(_T_1309, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1310 node _T_1311 = eq(UInt<3>(0h4), idx_10) when _T_1311 : node _T_1312 = shl(UInt<4>(0ha), 3) node _T_1313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1312) node _T_1314 = bits(_T_1313, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1314 node _T_1315 = eq(UInt<3>(0h5), idx_10) when _T_1315 : node _T_1316 = shl(UInt<4>(0ha), 3) node _T_1317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1316) node _T_1318 = bits(_T_1317, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1318 node _T_1319 = eq(UInt<3>(0h6), idx_10) when _T_1319 : node _T_1320 = shl(UInt<4>(0ha), 3) node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320) node _T_1322 = bits(_T_1321, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1322 node _T_1323 = eq(UInt<3>(0h7), idx_10) when _T_1323 : node _T_1324 = shl(UInt<4>(0ha), 3) node _T_1325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1324) node _T_1326 = bits(_T_1325, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1326 node _T_1327 = eq(UInt<4>(0h8), idx_10) when _T_1327 : node _T_1328 = shl(UInt<4>(0ha), 3) node _T_1329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1328) node _T_1330 = bits(_T_1329, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1330 node _T_1331 = eq(UInt<4>(0h9), idx_10) when _T_1331 : node _T_1332 = shl(UInt<4>(0ha), 3) node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332) node _T_1334 = bits(_T_1333, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1334 node _T_1335 = eq(UInt<4>(0ha), idx_10) when _T_1335 : node _T_1336 = shl(UInt<4>(0ha), 3) node _T_1337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1336) node _T_1338 = bits(_T_1337, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1338 node _T_1339 = eq(UInt<4>(0hb), idx_10) when _T_1339 : node _T_1340 = shl(UInt<4>(0ha), 3) node _T_1341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1340) node _T_1342 = bits(_T_1341, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1342 node _T_1343 = eq(UInt<4>(0hc), idx_10) when _T_1343 : node _T_1344 = shl(UInt<4>(0ha), 3) node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344) node _T_1346 = bits(_T_1345, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1346 node _T_1347 = eq(UInt<4>(0hd), idx_10) when _T_1347 : node _T_1348 = shl(UInt<4>(0ha), 3) node _T_1349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1348) node _T_1350 = bits(_T_1349, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1350 node _T_1351 = eq(UInt<4>(0he), idx_10) when _T_1351 : node _T_1352 = shl(UInt<4>(0ha), 3) node _T_1353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1352) node _T_1354 = bits(_T_1353, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1354 node _T_1355 = eq(UInt<4>(0hf), idx_10) when _T_1355 : node _T_1356 = shl(UInt<4>(0ha), 3) node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356) node _T_1358 = bits(_T_1357, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1358 node _T_1359 = eq(UInt<5>(0h10), idx_10) when _T_1359 : node _T_1360 = shl(UInt<4>(0ha), 3) node _T_1361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1360) node _T_1362 = bits(_T_1361, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1362 node _T_1363 = eq(UInt<5>(0h11), idx_10) when _T_1363 : node _T_1364 = shl(UInt<4>(0ha), 3) node _T_1365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1364) node _T_1366 = bits(_T_1365, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1366 node _T_1367 = eq(UInt<5>(0h12), idx_10) when _T_1367 : node _T_1368 = shl(UInt<4>(0ha), 3) node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368) node _T_1370 = bits(_T_1369, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1370 node _T_1371 = eq(UInt<5>(0h13), idx_10) when _T_1371 : node _T_1372 = shl(UInt<4>(0ha), 3) node _T_1373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1372) node _T_1374 = bits(_T_1373, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1374 node _T_1375 = eq(UInt<5>(0h14), idx_10) when _T_1375 : node _T_1376 = shl(UInt<4>(0ha), 3) node _T_1377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1376) node _T_1378 = bits(_T_1377, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1378 node _T_1379 = eq(UInt<5>(0h15), idx_10) when _T_1379 : node _T_1380 = shl(UInt<4>(0ha), 3) node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380) node _T_1382 = bits(_T_1381, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1382 node _T_1383 = eq(UInt<5>(0h16), idx_10) when _T_1383 : node _T_1384 = shl(UInt<4>(0ha), 3) node _T_1385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1384) node _T_1386 = bits(_T_1385, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1386 node _T_1387 = eq(UInt<5>(0h17), idx_10) when _T_1387 : node _T_1388 = shl(UInt<4>(0ha), 3) node _T_1389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1388) node _T_1390 = bits(_T_1389, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1390 node _T_1391 = eq(UInt<5>(0h18), idx_10) when _T_1391 : node _T_1392 = shl(UInt<4>(0ha), 3) node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392) node _T_1394 = bits(_T_1393, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1394 node _T_1395 = eq(UInt<5>(0h19), idx_10) when _T_1395 : node _T_1396 = shl(UInt<4>(0ha), 3) node _T_1397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1396) node _T_1398 = bits(_T_1397, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1398 node _T_1399 = eq(UInt<5>(0h1a), idx_10) when _T_1399 : node _T_1400 = shl(UInt<4>(0ha), 3) node _T_1401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1400) node _T_1402 = bits(_T_1401, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1402 node _T_1403 = eq(UInt<5>(0h1b), idx_10) when _T_1403 : node _T_1404 = shl(UInt<4>(0ha), 3) node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404) node _T_1406 = bits(_T_1405, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1406 node _T_1407 = eq(UInt<5>(0h1c), idx_10) when _T_1407 : node _T_1408 = shl(UInt<4>(0ha), 3) node _T_1409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1408) node _T_1410 = bits(_T_1409, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1410 node _T_1411 = eq(UInt<5>(0h1d), idx_10) when _T_1411 : node _T_1412 = shl(UInt<4>(0ha), 3) node _T_1413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1412) node _T_1414 = bits(_T_1413, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1414 node _T_1415 = eq(UInt<5>(0h1e), idx_10) when _T_1415 : node _T_1416 = shl(UInt<4>(0ha), 3) node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416) node _T_1418 = bits(_T_1417, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1418 node _T_1419 = eq(UInt<5>(0h1f), idx_10) when _T_1419 : node _T_1420 = shl(UInt<4>(0ha), 3) node _T_1421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1420) node _T_1422 = bits(_T_1421, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1422 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_1423 = eq(UInt<1>(0h0), idx_11) when _T_1423 : node _T_1424 = shl(UInt<4>(0hb), 3) node _T_1425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1424) node _T_1426 = bits(_T_1425, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1426 node _T_1427 = eq(UInt<1>(0h1), idx_11) when _T_1427 : node _T_1428 = shl(UInt<4>(0hb), 3) node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428) node _T_1430 = bits(_T_1429, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1430 node _T_1431 = eq(UInt<2>(0h2), idx_11) when _T_1431 : node _T_1432 = shl(UInt<4>(0hb), 3) node _T_1433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1432) node _T_1434 = bits(_T_1433, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1434 node _T_1435 = eq(UInt<2>(0h3), idx_11) when _T_1435 : node _T_1436 = shl(UInt<4>(0hb), 3) node _T_1437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1436) node _T_1438 = bits(_T_1437, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1438 node _T_1439 = eq(UInt<3>(0h4), idx_11) when _T_1439 : node _T_1440 = shl(UInt<4>(0hb), 3) node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440) node _T_1442 = bits(_T_1441, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1442 node _T_1443 = eq(UInt<3>(0h5), idx_11) when _T_1443 : node _T_1444 = shl(UInt<4>(0hb), 3) node _T_1445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1444) node _T_1446 = bits(_T_1445, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1446 node _T_1447 = eq(UInt<3>(0h6), idx_11) when _T_1447 : node _T_1448 = shl(UInt<4>(0hb), 3) node _T_1449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1448) node _T_1450 = bits(_T_1449, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1450 node _T_1451 = eq(UInt<3>(0h7), idx_11) when _T_1451 : node _T_1452 = shl(UInt<4>(0hb), 3) node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452) node _T_1454 = bits(_T_1453, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1454 node _T_1455 = eq(UInt<4>(0h8), idx_11) when _T_1455 : node _T_1456 = shl(UInt<4>(0hb), 3) node _T_1457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1456) node _T_1458 = bits(_T_1457, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1458 node _T_1459 = eq(UInt<4>(0h9), idx_11) when _T_1459 : node _T_1460 = shl(UInt<4>(0hb), 3) node _T_1461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1460) node _T_1462 = bits(_T_1461, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1462 node _T_1463 = eq(UInt<4>(0ha), idx_11) when _T_1463 : node _T_1464 = shl(UInt<4>(0hb), 3) node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464) node _T_1466 = bits(_T_1465, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1466 node _T_1467 = eq(UInt<4>(0hb), idx_11) when _T_1467 : node _T_1468 = shl(UInt<4>(0hb), 3) node _T_1469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1468) node _T_1470 = bits(_T_1469, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1470 node _T_1471 = eq(UInt<4>(0hc), idx_11) when _T_1471 : node _T_1472 = shl(UInt<4>(0hb), 3) node _T_1473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1472) node _T_1474 = bits(_T_1473, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1474 node _T_1475 = eq(UInt<4>(0hd), idx_11) when _T_1475 : node _T_1476 = shl(UInt<4>(0hb), 3) node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476) node _T_1478 = bits(_T_1477, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1478 node _T_1479 = eq(UInt<4>(0he), idx_11) when _T_1479 : node _T_1480 = shl(UInt<4>(0hb), 3) node _T_1481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1480) node _T_1482 = bits(_T_1481, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1482 node _T_1483 = eq(UInt<4>(0hf), idx_11) when _T_1483 : node _T_1484 = shl(UInt<4>(0hb), 3) node _T_1485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1484) node _T_1486 = bits(_T_1485, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1486 node _T_1487 = eq(UInt<5>(0h10), idx_11) when _T_1487 : node _T_1488 = shl(UInt<4>(0hb), 3) node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488) node _T_1490 = bits(_T_1489, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1490 node _T_1491 = eq(UInt<5>(0h11), idx_11) when _T_1491 : node _T_1492 = shl(UInt<4>(0hb), 3) node _T_1493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1492) node _T_1494 = bits(_T_1493, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1494 node _T_1495 = eq(UInt<5>(0h12), idx_11) when _T_1495 : node _T_1496 = shl(UInt<4>(0hb), 3) node _T_1497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1496) node _T_1498 = bits(_T_1497, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1498 node _T_1499 = eq(UInt<5>(0h13), idx_11) when _T_1499 : node _T_1500 = shl(UInt<4>(0hb), 3) node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500) node _T_1502 = bits(_T_1501, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1502 node _T_1503 = eq(UInt<5>(0h14), idx_11) when _T_1503 : node _T_1504 = shl(UInt<4>(0hb), 3) node _T_1505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1504) node _T_1506 = bits(_T_1505, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1506 node _T_1507 = eq(UInt<5>(0h15), idx_11) when _T_1507 : node _T_1508 = shl(UInt<4>(0hb), 3) node _T_1509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1508) node _T_1510 = bits(_T_1509, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1510 node _T_1511 = eq(UInt<5>(0h16), idx_11) when _T_1511 : node _T_1512 = shl(UInt<4>(0hb), 3) node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512) node _T_1514 = bits(_T_1513, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1514 node _T_1515 = eq(UInt<5>(0h17), idx_11) when _T_1515 : node _T_1516 = shl(UInt<4>(0hb), 3) node _T_1517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1516) node _T_1518 = bits(_T_1517, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1518 node _T_1519 = eq(UInt<5>(0h18), idx_11) when _T_1519 : node _T_1520 = shl(UInt<4>(0hb), 3) node _T_1521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1520) node _T_1522 = bits(_T_1521, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1522 node _T_1523 = eq(UInt<5>(0h19), idx_11) when _T_1523 : node _T_1524 = shl(UInt<4>(0hb), 3) node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524) node _T_1526 = bits(_T_1525, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1526 node _T_1527 = eq(UInt<5>(0h1a), idx_11) when _T_1527 : node _T_1528 = shl(UInt<4>(0hb), 3) node _T_1529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1528) node _T_1530 = bits(_T_1529, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1530 node _T_1531 = eq(UInt<5>(0h1b), idx_11) when _T_1531 : node _T_1532 = shl(UInt<4>(0hb), 3) node _T_1533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1532) node _T_1534 = bits(_T_1533, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1534 node _T_1535 = eq(UInt<5>(0h1c), idx_11) when _T_1535 : node _T_1536 = shl(UInt<4>(0hb), 3) node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536) node _T_1538 = bits(_T_1537, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1538 node _T_1539 = eq(UInt<5>(0h1d), idx_11) when _T_1539 : node _T_1540 = shl(UInt<4>(0hb), 3) node _T_1541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1540) node _T_1542 = bits(_T_1541, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1542 node _T_1543 = eq(UInt<5>(0h1e), idx_11) when _T_1543 : node _T_1544 = shl(UInt<4>(0hb), 3) node _T_1545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1544) node _T_1546 = bits(_T_1545, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1546 node _T_1547 = eq(UInt<5>(0h1f), idx_11) when _T_1547 : node _T_1548 = shl(UInt<4>(0hb), 3) node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548) node _T_1550 = bits(_T_1549, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1550 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_1551 = eq(UInt<1>(0h0), idx_12) when _T_1551 : node _T_1552 = shl(UInt<4>(0hc), 3) node _T_1553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1552) node _T_1554 = bits(_T_1553, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1554 node _T_1555 = eq(UInt<1>(0h1), idx_12) when _T_1555 : node _T_1556 = shl(UInt<4>(0hc), 3) node _T_1557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1556) node _T_1558 = bits(_T_1557, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1558 node _T_1559 = eq(UInt<2>(0h2), idx_12) when _T_1559 : node _T_1560 = shl(UInt<4>(0hc), 3) node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560) node _T_1562 = bits(_T_1561, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1562 node _T_1563 = eq(UInt<2>(0h3), idx_12) when _T_1563 : node _T_1564 = shl(UInt<4>(0hc), 3) node _T_1565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1564) node _T_1566 = bits(_T_1565, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1566 node _T_1567 = eq(UInt<3>(0h4), idx_12) when _T_1567 : node _T_1568 = shl(UInt<4>(0hc), 3) node _T_1569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1568) node _T_1570 = bits(_T_1569, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1570 node _T_1571 = eq(UInt<3>(0h5), idx_12) when _T_1571 : node _T_1572 = shl(UInt<4>(0hc), 3) node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572) node _T_1574 = bits(_T_1573, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1574 node _T_1575 = eq(UInt<3>(0h6), idx_12) when _T_1575 : node _T_1576 = shl(UInt<4>(0hc), 3) node _T_1577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1576) node _T_1578 = bits(_T_1577, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1578 node _T_1579 = eq(UInt<3>(0h7), idx_12) when _T_1579 : node _T_1580 = shl(UInt<4>(0hc), 3) node _T_1581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1580) node _T_1582 = bits(_T_1581, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1582 node _T_1583 = eq(UInt<4>(0h8), idx_12) when _T_1583 : node _T_1584 = shl(UInt<4>(0hc), 3) node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584) node _T_1586 = bits(_T_1585, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1586 node _T_1587 = eq(UInt<4>(0h9), idx_12) when _T_1587 : node _T_1588 = shl(UInt<4>(0hc), 3) node _T_1589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1588) node _T_1590 = bits(_T_1589, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1590 node _T_1591 = eq(UInt<4>(0ha), idx_12) when _T_1591 : node _T_1592 = shl(UInt<4>(0hc), 3) node _T_1593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1592) node _T_1594 = bits(_T_1593, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1594 node _T_1595 = eq(UInt<4>(0hb), idx_12) when _T_1595 : node _T_1596 = shl(UInt<4>(0hc), 3) node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596) node _T_1598 = bits(_T_1597, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1598 node _T_1599 = eq(UInt<4>(0hc), idx_12) when _T_1599 : node _T_1600 = shl(UInt<4>(0hc), 3) node _T_1601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1600) node _T_1602 = bits(_T_1601, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1602 node _T_1603 = eq(UInt<4>(0hd), idx_12) when _T_1603 : node _T_1604 = shl(UInt<4>(0hc), 3) node _T_1605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1604) node _T_1606 = bits(_T_1605, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1606 node _T_1607 = eq(UInt<4>(0he), idx_12) when _T_1607 : node _T_1608 = shl(UInt<4>(0hc), 3) node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608) node _T_1610 = bits(_T_1609, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1610 node _T_1611 = eq(UInt<4>(0hf), idx_12) when _T_1611 : node _T_1612 = shl(UInt<4>(0hc), 3) node _T_1613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1612) node _T_1614 = bits(_T_1613, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1614 node _T_1615 = eq(UInt<5>(0h10), idx_12) when _T_1615 : node _T_1616 = shl(UInt<4>(0hc), 3) node _T_1617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1616) node _T_1618 = bits(_T_1617, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1618 node _T_1619 = eq(UInt<5>(0h11), idx_12) when _T_1619 : node _T_1620 = shl(UInt<4>(0hc), 3) node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620) node _T_1622 = bits(_T_1621, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1622 node _T_1623 = eq(UInt<5>(0h12), idx_12) when _T_1623 : node _T_1624 = shl(UInt<4>(0hc), 3) node _T_1625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1624) node _T_1626 = bits(_T_1625, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1626 node _T_1627 = eq(UInt<5>(0h13), idx_12) when _T_1627 : node _T_1628 = shl(UInt<4>(0hc), 3) node _T_1629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1628) node _T_1630 = bits(_T_1629, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1630 node _T_1631 = eq(UInt<5>(0h14), idx_12) when _T_1631 : node _T_1632 = shl(UInt<4>(0hc), 3) node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632) node _T_1634 = bits(_T_1633, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1634 node _T_1635 = eq(UInt<5>(0h15), idx_12) when _T_1635 : node _T_1636 = shl(UInt<4>(0hc), 3) node _T_1637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1636) node _T_1638 = bits(_T_1637, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1638 node _T_1639 = eq(UInt<5>(0h16), idx_12) when _T_1639 : node _T_1640 = shl(UInt<4>(0hc), 3) node _T_1641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1640) node _T_1642 = bits(_T_1641, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1642 node _T_1643 = eq(UInt<5>(0h17), idx_12) when _T_1643 : node _T_1644 = shl(UInt<4>(0hc), 3) node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644) node _T_1646 = bits(_T_1645, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1646 node _T_1647 = eq(UInt<5>(0h18), idx_12) when _T_1647 : node _T_1648 = shl(UInt<4>(0hc), 3) node _T_1649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1648) node _T_1650 = bits(_T_1649, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1650 node _T_1651 = eq(UInt<5>(0h19), idx_12) when _T_1651 : node _T_1652 = shl(UInt<4>(0hc), 3) node _T_1653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1652) node _T_1654 = bits(_T_1653, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1654 node _T_1655 = eq(UInt<5>(0h1a), idx_12) when _T_1655 : node _T_1656 = shl(UInt<4>(0hc), 3) node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656) node _T_1658 = bits(_T_1657, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1658 node _T_1659 = eq(UInt<5>(0h1b), idx_12) when _T_1659 : node _T_1660 = shl(UInt<4>(0hc), 3) node _T_1661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1660) node _T_1662 = bits(_T_1661, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1662 node _T_1663 = eq(UInt<5>(0h1c), idx_12) when _T_1663 : node _T_1664 = shl(UInt<4>(0hc), 3) node _T_1665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1664) node _T_1666 = bits(_T_1665, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1666 node _T_1667 = eq(UInt<5>(0h1d), idx_12) when _T_1667 : node _T_1668 = shl(UInt<4>(0hc), 3) node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668) node _T_1670 = bits(_T_1669, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1670 node _T_1671 = eq(UInt<5>(0h1e), idx_12) when _T_1671 : node _T_1672 = shl(UInt<4>(0hc), 3) node _T_1673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1672) node _T_1674 = bits(_T_1673, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1674 node _T_1675 = eq(UInt<5>(0h1f), idx_12) when _T_1675 : node _T_1676 = shl(UInt<4>(0hc), 3) node _T_1677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1676) node _T_1678 = bits(_T_1677, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1678 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_1679 = eq(UInt<1>(0h0), idx_13) when _T_1679 : node _T_1680 = shl(UInt<4>(0hd), 3) node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680) node _T_1682 = bits(_T_1681, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1682 node _T_1683 = eq(UInt<1>(0h1), idx_13) when _T_1683 : node _T_1684 = shl(UInt<4>(0hd), 3) node _T_1685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1684) node _T_1686 = bits(_T_1685, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1686 node _T_1687 = eq(UInt<2>(0h2), idx_13) when _T_1687 : node _T_1688 = shl(UInt<4>(0hd), 3) node _T_1689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1688) node _T_1690 = bits(_T_1689, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1690 node _T_1691 = eq(UInt<2>(0h3), idx_13) when _T_1691 : node _T_1692 = shl(UInt<4>(0hd), 3) node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692) node _T_1694 = bits(_T_1693, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1694 node _T_1695 = eq(UInt<3>(0h4), idx_13) when _T_1695 : node _T_1696 = shl(UInt<4>(0hd), 3) node _T_1697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1696) node _T_1698 = bits(_T_1697, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1698 node _T_1699 = eq(UInt<3>(0h5), idx_13) when _T_1699 : node _T_1700 = shl(UInt<4>(0hd), 3) node _T_1701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1700) node _T_1702 = bits(_T_1701, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1702 node _T_1703 = eq(UInt<3>(0h6), idx_13) when _T_1703 : node _T_1704 = shl(UInt<4>(0hd), 3) node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704) node _T_1706 = bits(_T_1705, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1706 node _T_1707 = eq(UInt<3>(0h7), idx_13) when _T_1707 : node _T_1708 = shl(UInt<4>(0hd), 3) node _T_1709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1708) node _T_1710 = bits(_T_1709, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1710 node _T_1711 = eq(UInt<4>(0h8), idx_13) when _T_1711 : node _T_1712 = shl(UInt<4>(0hd), 3) node _T_1713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1712) node _T_1714 = bits(_T_1713, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1714 node _T_1715 = eq(UInt<4>(0h9), idx_13) when _T_1715 : node _T_1716 = shl(UInt<4>(0hd), 3) node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716) node _T_1718 = bits(_T_1717, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1718 node _T_1719 = eq(UInt<4>(0ha), idx_13) when _T_1719 : node _T_1720 = shl(UInt<4>(0hd), 3) node _T_1721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1720) node _T_1722 = bits(_T_1721, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1722 node _T_1723 = eq(UInt<4>(0hb), idx_13) when _T_1723 : node _T_1724 = shl(UInt<4>(0hd), 3) node _T_1725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1724) node _T_1726 = bits(_T_1725, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1726 node _T_1727 = eq(UInt<4>(0hc), idx_13) when _T_1727 : node _T_1728 = shl(UInt<4>(0hd), 3) node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728) node _T_1730 = bits(_T_1729, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1730 node _T_1731 = eq(UInt<4>(0hd), idx_13) when _T_1731 : node _T_1732 = shl(UInt<4>(0hd), 3) node _T_1733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1732) node _T_1734 = bits(_T_1733, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1734 node _T_1735 = eq(UInt<4>(0he), idx_13) when _T_1735 : node _T_1736 = shl(UInt<4>(0hd), 3) node _T_1737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1736) node _T_1738 = bits(_T_1737, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1738 node _T_1739 = eq(UInt<4>(0hf), idx_13) when _T_1739 : node _T_1740 = shl(UInt<4>(0hd), 3) node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740) node _T_1742 = bits(_T_1741, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1742 node _T_1743 = eq(UInt<5>(0h10), idx_13) when _T_1743 : node _T_1744 = shl(UInt<4>(0hd), 3) node _T_1745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1744) node _T_1746 = bits(_T_1745, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1746 node _T_1747 = eq(UInt<5>(0h11), idx_13) when _T_1747 : node _T_1748 = shl(UInt<4>(0hd), 3) node _T_1749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1748) node _T_1750 = bits(_T_1749, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1750 node _T_1751 = eq(UInt<5>(0h12), idx_13) when _T_1751 : node _T_1752 = shl(UInt<4>(0hd), 3) node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752) node _T_1754 = bits(_T_1753, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1754 node _T_1755 = eq(UInt<5>(0h13), idx_13) when _T_1755 : node _T_1756 = shl(UInt<4>(0hd), 3) node _T_1757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1756) node _T_1758 = bits(_T_1757, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1758 node _T_1759 = eq(UInt<5>(0h14), idx_13) when _T_1759 : node _T_1760 = shl(UInt<4>(0hd), 3) node _T_1761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1760) node _T_1762 = bits(_T_1761, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1762 node _T_1763 = eq(UInt<5>(0h15), idx_13) when _T_1763 : node _T_1764 = shl(UInt<4>(0hd), 3) node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764) node _T_1766 = bits(_T_1765, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1766 node _T_1767 = eq(UInt<5>(0h16), idx_13) when _T_1767 : node _T_1768 = shl(UInt<4>(0hd), 3) node _T_1769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1768) node _T_1770 = bits(_T_1769, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1770 node _T_1771 = eq(UInt<5>(0h17), idx_13) when _T_1771 : node _T_1772 = shl(UInt<4>(0hd), 3) node _T_1773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1772) node _T_1774 = bits(_T_1773, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1774 node _T_1775 = eq(UInt<5>(0h18), idx_13) when _T_1775 : node _T_1776 = shl(UInt<4>(0hd), 3) node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776) node _T_1778 = bits(_T_1777, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1778 node _T_1779 = eq(UInt<5>(0h19), idx_13) when _T_1779 : node _T_1780 = shl(UInt<4>(0hd), 3) node _T_1781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1780) node _T_1782 = bits(_T_1781, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1782 node _T_1783 = eq(UInt<5>(0h1a), idx_13) when _T_1783 : node _T_1784 = shl(UInt<4>(0hd), 3) node _T_1785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1784) node _T_1786 = bits(_T_1785, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1786 node _T_1787 = eq(UInt<5>(0h1b), idx_13) when _T_1787 : node _T_1788 = shl(UInt<4>(0hd), 3) node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788) node _T_1790 = bits(_T_1789, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1790 node _T_1791 = eq(UInt<5>(0h1c), idx_13) when _T_1791 : node _T_1792 = shl(UInt<4>(0hd), 3) node _T_1793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1792) node _T_1794 = bits(_T_1793, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1794 node _T_1795 = eq(UInt<5>(0h1d), idx_13) when _T_1795 : node _T_1796 = shl(UInt<4>(0hd), 3) node _T_1797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1796) node _T_1798 = bits(_T_1797, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1798 node _T_1799 = eq(UInt<5>(0h1e), idx_13) when _T_1799 : node _T_1800 = shl(UInt<4>(0hd), 3) node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800) node _T_1802 = bits(_T_1801, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1802 node _T_1803 = eq(UInt<5>(0h1f), idx_13) when _T_1803 : node _T_1804 = shl(UInt<4>(0hd), 3) node _T_1805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1804) node _T_1806 = bits(_T_1805, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1806 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_1807 = eq(UInt<1>(0h0), idx_14) when _T_1807 : node _T_1808 = shl(UInt<4>(0he), 3) node _T_1809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1808) node _T_1810 = bits(_T_1809, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1810 node _T_1811 = eq(UInt<1>(0h1), idx_14) when _T_1811 : node _T_1812 = shl(UInt<4>(0he), 3) node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812) node _T_1814 = bits(_T_1813, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1814 node _T_1815 = eq(UInt<2>(0h2), idx_14) when _T_1815 : node _T_1816 = shl(UInt<4>(0he), 3) node _T_1817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1816) node _T_1818 = bits(_T_1817, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1818 node _T_1819 = eq(UInt<2>(0h3), idx_14) when _T_1819 : node _T_1820 = shl(UInt<4>(0he), 3) node _T_1821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1820) node _T_1822 = bits(_T_1821, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1822 node _T_1823 = eq(UInt<3>(0h4), idx_14) when _T_1823 : node _T_1824 = shl(UInt<4>(0he), 3) node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824) node _T_1826 = bits(_T_1825, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1826 node _T_1827 = eq(UInt<3>(0h5), idx_14) when _T_1827 : node _T_1828 = shl(UInt<4>(0he), 3) node _T_1829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1828) node _T_1830 = bits(_T_1829, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1830 node _T_1831 = eq(UInt<3>(0h6), idx_14) when _T_1831 : node _T_1832 = shl(UInt<4>(0he), 3) node _T_1833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1832) node _T_1834 = bits(_T_1833, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1834 node _T_1835 = eq(UInt<3>(0h7), idx_14) when _T_1835 : node _T_1836 = shl(UInt<4>(0he), 3) node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836) node _T_1838 = bits(_T_1837, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1838 node _T_1839 = eq(UInt<4>(0h8), idx_14) when _T_1839 : node _T_1840 = shl(UInt<4>(0he), 3) node _T_1841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1840) node _T_1842 = bits(_T_1841, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1842 node _T_1843 = eq(UInt<4>(0h9), idx_14) when _T_1843 : node _T_1844 = shl(UInt<4>(0he), 3) node _T_1845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1844) node _T_1846 = bits(_T_1845, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1846 node _T_1847 = eq(UInt<4>(0ha), idx_14) when _T_1847 : node _T_1848 = shl(UInt<4>(0he), 3) node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848) node _T_1850 = bits(_T_1849, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1850 node _T_1851 = eq(UInt<4>(0hb), idx_14) when _T_1851 : node _T_1852 = shl(UInt<4>(0he), 3) node _T_1853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1852) node _T_1854 = bits(_T_1853, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1854 node _T_1855 = eq(UInt<4>(0hc), idx_14) when _T_1855 : node _T_1856 = shl(UInt<4>(0he), 3) node _T_1857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1856) node _T_1858 = bits(_T_1857, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1858 node _T_1859 = eq(UInt<4>(0hd), idx_14) when _T_1859 : node _T_1860 = shl(UInt<4>(0he), 3) node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860) node _T_1862 = bits(_T_1861, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1862 node _T_1863 = eq(UInt<4>(0he), idx_14) when _T_1863 : node _T_1864 = shl(UInt<4>(0he), 3) node _T_1865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1864) node _T_1866 = bits(_T_1865, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1866 node _T_1867 = eq(UInt<4>(0hf), idx_14) when _T_1867 : node _T_1868 = shl(UInt<4>(0he), 3) node _T_1869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1868) node _T_1870 = bits(_T_1869, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1870 node _T_1871 = eq(UInt<5>(0h10), idx_14) when _T_1871 : node _T_1872 = shl(UInt<4>(0he), 3) node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872) node _T_1874 = bits(_T_1873, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_1874 node _T_1875 = eq(UInt<5>(0h11), idx_14) when _T_1875 : node _T_1876 = shl(UInt<4>(0he), 3) node _T_1877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1876) node _T_1878 = bits(_T_1877, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_1878 node _T_1879 = eq(UInt<5>(0h12), idx_14) when _T_1879 : node _T_1880 = shl(UInt<4>(0he), 3) node _T_1881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1880) node _T_1882 = bits(_T_1881, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_1882 node _T_1883 = eq(UInt<5>(0h13), idx_14) when _T_1883 : node _T_1884 = shl(UInt<4>(0he), 3) node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884) node _T_1886 = bits(_T_1885, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_1886 node _T_1887 = eq(UInt<5>(0h14), idx_14) when _T_1887 : node _T_1888 = shl(UInt<4>(0he), 3) node _T_1889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1888) node _T_1890 = bits(_T_1889, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_1890 node _T_1891 = eq(UInt<5>(0h15), idx_14) when _T_1891 : node _T_1892 = shl(UInt<4>(0he), 3) node _T_1893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1892) node _T_1894 = bits(_T_1893, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_1894 node _T_1895 = eq(UInt<5>(0h16), idx_14) when _T_1895 : node _T_1896 = shl(UInt<4>(0he), 3) node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896) node _T_1898 = bits(_T_1897, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_1898 node _T_1899 = eq(UInt<5>(0h17), idx_14) when _T_1899 : node _T_1900 = shl(UInt<4>(0he), 3) node _T_1901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1900) node _T_1902 = bits(_T_1901, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_1902 node _T_1903 = eq(UInt<5>(0h18), idx_14) when _T_1903 : node _T_1904 = shl(UInt<4>(0he), 3) node _T_1905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1904) node _T_1906 = bits(_T_1905, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_1906 node _T_1907 = eq(UInt<5>(0h19), idx_14) when _T_1907 : node _T_1908 = shl(UInt<4>(0he), 3) node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908) node _T_1910 = bits(_T_1909, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_1910 node _T_1911 = eq(UInt<5>(0h1a), idx_14) when _T_1911 : node _T_1912 = shl(UInt<4>(0he), 3) node _T_1913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1912) node _T_1914 = bits(_T_1913, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_1914 node _T_1915 = eq(UInt<5>(0h1b), idx_14) when _T_1915 : node _T_1916 = shl(UInt<4>(0he), 3) node _T_1917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1916) node _T_1918 = bits(_T_1917, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_1918 node _T_1919 = eq(UInt<5>(0h1c), idx_14) when _T_1919 : node _T_1920 = shl(UInt<4>(0he), 3) node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920) node _T_1922 = bits(_T_1921, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_1922 node _T_1923 = eq(UInt<5>(0h1d), idx_14) when _T_1923 : node _T_1924 = shl(UInt<4>(0he), 3) node _T_1925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1924) node _T_1926 = bits(_T_1925, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_1926 node _T_1927 = eq(UInt<5>(0h1e), idx_14) when _T_1927 : node _T_1928 = shl(UInt<4>(0he), 3) node _T_1929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1928) node _T_1930 = bits(_T_1929, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_1930 node _T_1931 = eq(UInt<5>(0h1f), idx_14) when _T_1931 : node _T_1932 = shl(UInt<4>(0he), 3) node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932) node _T_1934 = bits(_T_1933, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_1934 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1935 = eq(UInt<1>(0h0), idx_15) when _T_1935 : node _T_1936 = shl(UInt<4>(0hf), 3) node _T_1937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1936) node _T_1938 = bits(_T_1937, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_1938 node _T_1939 = eq(UInt<1>(0h1), idx_15) when _T_1939 : node _T_1940 = shl(UInt<4>(0hf), 3) node _T_1941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1940) node _T_1942 = bits(_T_1941, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_1942 node _T_1943 = eq(UInt<2>(0h2), idx_15) when _T_1943 : node _T_1944 = shl(UInt<4>(0hf), 3) node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944) node _T_1946 = bits(_T_1945, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_1946 node _T_1947 = eq(UInt<2>(0h3), idx_15) when _T_1947 : node _T_1948 = shl(UInt<4>(0hf), 3) node _T_1949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1948) node _T_1950 = bits(_T_1949, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_1950 node _T_1951 = eq(UInt<3>(0h4), idx_15) when _T_1951 : node _T_1952 = shl(UInt<4>(0hf), 3) node _T_1953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1952) node _T_1954 = bits(_T_1953, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_1954 node _T_1955 = eq(UInt<3>(0h5), idx_15) when _T_1955 : node _T_1956 = shl(UInt<4>(0hf), 3) node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956) node _T_1958 = bits(_T_1957, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_1958 node _T_1959 = eq(UInt<3>(0h6), idx_15) when _T_1959 : node _T_1960 = shl(UInt<4>(0hf), 3) node _T_1961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1960) node _T_1962 = bits(_T_1961, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_1962 node _T_1963 = eq(UInt<3>(0h7), idx_15) when _T_1963 : node _T_1964 = shl(UInt<4>(0hf), 3) node _T_1965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1964) node _T_1966 = bits(_T_1965, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_1966 node _T_1967 = eq(UInt<4>(0h8), idx_15) when _T_1967 : node _T_1968 = shl(UInt<4>(0hf), 3) node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968) node _T_1970 = bits(_T_1969, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_1970 node _T_1971 = eq(UInt<4>(0h9), idx_15) when _T_1971 : node _T_1972 = shl(UInt<4>(0hf), 3) node _T_1973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1972) node _T_1974 = bits(_T_1973, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_1974 node _T_1975 = eq(UInt<4>(0ha), idx_15) when _T_1975 : node _T_1976 = shl(UInt<4>(0hf), 3) node _T_1977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1976) node _T_1978 = bits(_T_1977, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_1978 node _T_1979 = eq(UInt<4>(0hb), idx_15) when _T_1979 : node _T_1980 = shl(UInt<4>(0hf), 3) node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980) node _T_1982 = bits(_T_1981, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_1982 node _T_1983 = eq(UInt<4>(0hc), idx_15) when _T_1983 : node _T_1984 = shl(UInt<4>(0hf), 3) node _T_1985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1984) node _T_1986 = bits(_T_1985, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_1986 node _T_1987 = eq(UInt<4>(0hd), idx_15) when _T_1987 : node _T_1988 = shl(UInt<4>(0hf), 3) node _T_1989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1988) node _T_1990 = bits(_T_1989, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_1990 node _T_1991 = eq(UInt<4>(0he), idx_15) when _T_1991 : node _T_1992 = shl(UInt<4>(0hf), 3) node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992) node _T_1994 = bits(_T_1993, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_1994 node _T_1995 = eq(UInt<4>(0hf), idx_15) when _T_1995 : node _T_1996 = shl(UInt<4>(0hf), 3) node _T_1997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1996) node _T_1998 = bits(_T_1997, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_1998 node _T_1999 = eq(UInt<5>(0h10), idx_15) when _T_1999 : node _T_2000 = shl(UInt<4>(0hf), 3) node _T_2001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2000) node _T_2002 = bits(_T_2001, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2002 node _T_2003 = eq(UInt<5>(0h11), idx_15) when _T_2003 : node _T_2004 = shl(UInt<4>(0hf), 3) node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004) node _T_2006 = bits(_T_2005, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2006 node _T_2007 = eq(UInt<5>(0h12), idx_15) when _T_2007 : node _T_2008 = shl(UInt<4>(0hf), 3) node _T_2009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2008) node _T_2010 = bits(_T_2009, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2010 node _T_2011 = eq(UInt<5>(0h13), idx_15) when _T_2011 : node _T_2012 = shl(UInt<4>(0hf), 3) node _T_2013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2012) node _T_2014 = bits(_T_2013, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2014 node _T_2015 = eq(UInt<5>(0h14), idx_15) when _T_2015 : node _T_2016 = shl(UInt<4>(0hf), 3) node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016) node _T_2018 = bits(_T_2017, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2018 node _T_2019 = eq(UInt<5>(0h15), idx_15) when _T_2019 : node _T_2020 = shl(UInt<4>(0hf), 3) node _T_2021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2020) node _T_2022 = bits(_T_2021, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2022 node _T_2023 = eq(UInt<5>(0h16), idx_15) when _T_2023 : node _T_2024 = shl(UInt<4>(0hf), 3) node _T_2025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2024) node _T_2026 = bits(_T_2025, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2026 node _T_2027 = eq(UInt<5>(0h17), idx_15) when _T_2027 : node _T_2028 = shl(UInt<4>(0hf), 3) node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028) node _T_2030 = bits(_T_2029, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2030 node _T_2031 = eq(UInt<5>(0h18), idx_15) when _T_2031 : node _T_2032 = shl(UInt<4>(0hf), 3) node _T_2033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2032) node _T_2034 = bits(_T_2033, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2034 node _T_2035 = eq(UInt<5>(0h19), idx_15) when _T_2035 : node _T_2036 = shl(UInt<4>(0hf), 3) node _T_2037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2036) node _T_2038 = bits(_T_2037, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2038 node _T_2039 = eq(UInt<5>(0h1a), idx_15) when _T_2039 : node _T_2040 = shl(UInt<4>(0hf), 3) node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040) node _T_2042 = bits(_T_2041, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2042 node _T_2043 = eq(UInt<5>(0h1b), idx_15) when _T_2043 : node _T_2044 = shl(UInt<4>(0hf), 3) node _T_2045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2044) node _T_2046 = bits(_T_2045, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2046 node _T_2047 = eq(UInt<5>(0h1c), idx_15) when _T_2047 : node _T_2048 = shl(UInt<4>(0hf), 3) node _T_2049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2048) node _T_2050 = bits(_T_2049, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2050 node _T_2051 = eq(UInt<5>(0h1d), idx_15) when _T_2051 : node _T_2052 = shl(UInt<4>(0hf), 3) node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052) node _T_2054 = bits(_T_2053, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2054 node _T_2055 = eq(UInt<5>(0h1e), idx_15) when _T_2055 : node _T_2056 = shl(UInt<4>(0hf), 3) node _T_2057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2056) node _T_2058 = bits(_T_2057, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2058 node _T_2059 = eq(UInt<5>(0h1f), idx_15) when _T_2059 : node _T_2060 = shl(UInt<4>(0hf), 3) node _T_2061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2060) node _T_2062 = bits(_T_2061, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2062 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_2063 = eq(UInt<1>(0h0), idx_16) when _T_2063 : node _T_2064 = shl(UInt<5>(0h10), 3) node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064) node _T_2066 = bits(_T_2065, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2066 node _T_2067 = eq(UInt<1>(0h1), idx_16) when _T_2067 : node _T_2068 = shl(UInt<5>(0h10), 3) node _T_2069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2068) node _T_2070 = bits(_T_2069, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2070 node _T_2071 = eq(UInt<2>(0h2), idx_16) when _T_2071 : node _T_2072 = shl(UInt<5>(0h10), 3) node _T_2073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2072) node _T_2074 = bits(_T_2073, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2074 node _T_2075 = eq(UInt<2>(0h3), idx_16) when _T_2075 : node _T_2076 = shl(UInt<5>(0h10), 3) node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076) node _T_2078 = bits(_T_2077, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2078 node _T_2079 = eq(UInt<3>(0h4), idx_16) when _T_2079 : node _T_2080 = shl(UInt<5>(0h10), 3) node _T_2081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2080) node _T_2082 = bits(_T_2081, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2082 node _T_2083 = eq(UInt<3>(0h5), idx_16) when _T_2083 : node _T_2084 = shl(UInt<5>(0h10), 3) node _T_2085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2084) node _T_2086 = bits(_T_2085, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2086 node _T_2087 = eq(UInt<3>(0h6), idx_16) when _T_2087 : node _T_2088 = shl(UInt<5>(0h10), 3) node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088) node _T_2090 = bits(_T_2089, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2090 node _T_2091 = eq(UInt<3>(0h7), idx_16) when _T_2091 : node _T_2092 = shl(UInt<5>(0h10), 3) node _T_2093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2092) node _T_2094 = bits(_T_2093, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2094 node _T_2095 = eq(UInt<4>(0h8), idx_16) when _T_2095 : node _T_2096 = shl(UInt<5>(0h10), 3) node _T_2097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2096) node _T_2098 = bits(_T_2097, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2098 node _T_2099 = eq(UInt<4>(0h9), idx_16) when _T_2099 : node _T_2100 = shl(UInt<5>(0h10), 3) node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100) node _T_2102 = bits(_T_2101, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2102 node _T_2103 = eq(UInt<4>(0ha), idx_16) when _T_2103 : node _T_2104 = shl(UInt<5>(0h10), 3) node _T_2105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2104) node _T_2106 = bits(_T_2105, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2106 node _T_2107 = eq(UInt<4>(0hb), idx_16) when _T_2107 : node _T_2108 = shl(UInt<5>(0h10), 3) node _T_2109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2108) node _T_2110 = bits(_T_2109, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2110 node _T_2111 = eq(UInt<4>(0hc), idx_16) when _T_2111 : node _T_2112 = shl(UInt<5>(0h10), 3) node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112) node _T_2114 = bits(_T_2113, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2114 node _T_2115 = eq(UInt<4>(0hd), idx_16) when _T_2115 : node _T_2116 = shl(UInt<5>(0h10), 3) node _T_2117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2116) node _T_2118 = bits(_T_2117, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2118 node _T_2119 = eq(UInt<4>(0he), idx_16) when _T_2119 : node _T_2120 = shl(UInt<5>(0h10), 3) node _T_2121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2120) node _T_2122 = bits(_T_2121, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2122 node _T_2123 = eq(UInt<4>(0hf), idx_16) when _T_2123 : node _T_2124 = shl(UInt<5>(0h10), 3) node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124) node _T_2126 = bits(_T_2125, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2126 node _T_2127 = eq(UInt<5>(0h10), idx_16) when _T_2127 : node _T_2128 = shl(UInt<5>(0h10), 3) node _T_2129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2128) node _T_2130 = bits(_T_2129, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2130 node _T_2131 = eq(UInt<5>(0h11), idx_16) when _T_2131 : node _T_2132 = shl(UInt<5>(0h10), 3) node _T_2133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2132) node _T_2134 = bits(_T_2133, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2134 node _T_2135 = eq(UInt<5>(0h12), idx_16) when _T_2135 : node _T_2136 = shl(UInt<5>(0h10), 3) node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136) node _T_2138 = bits(_T_2137, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2138 node _T_2139 = eq(UInt<5>(0h13), idx_16) when _T_2139 : node _T_2140 = shl(UInt<5>(0h10), 3) node _T_2141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2140) node _T_2142 = bits(_T_2141, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2142 node _T_2143 = eq(UInt<5>(0h14), idx_16) when _T_2143 : node _T_2144 = shl(UInt<5>(0h10), 3) node _T_2145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2144) node _T_2146 = bits(_T_2145, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2146 node _T_2147 = eq(UInt<5>(0h15), idx_16) when _T_2147 : node _T_2148 = shl(UInt<5>(0h10), 3) node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148) node _T_2150 = bits(_T_2149, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2150 node _T_2151 = eq(UInt<5>(0h16), idx_16) when _T_2151 : node _T_2152 = shl(UInt<5>(0h10), 3) node _T_2153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2152) node _T_2154 = bits(_T_2153, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2154 node _T_2155 = eq(UInt<5>(0h17), idx_16) when _T_2155 : node _T_2156 = shl(UInt<5>(0h10), 3) node _T_2157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2156) node _T_2158 = bits(_T_2157, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2158 node _T_2159 = eq(UInt<5>(0h18), idx_16) when _T_2159 : node _T_2160 = shl(UInt<5>(0h10), 3) node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160) node _T_2162 = bits(_T_2161, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2162 node _T_2163 = eq(UInt<5>(0h19), idx_16) when _T_2163 : node _T_2164 = shl(UInt<5>(0h10), 3) node _T_2165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2164) node _T_2166 = bits(_T_2165, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2166 node _T_2167 = eq(UInt<5>(0h1a), idx_16) when _T_2167 : node _T_2168 = shl(UInt<5>(0h10), 3) node _T_2169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2168) node _T_2170 = bits(_T_2169, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2170 node _T_2171 = eq(UInt<5>(0h1b), idx_16) when _T_2171 : node _T_2172 = shl(UInt<5>(0h10), 3) node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172) node _T_2174 = bits(_T_2173, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2174 node _T_2175 = eq(UInt<5>(0h1c), idx_16) when _T_2175 : node _T_2176 = shl(UInt<5>(0h10), 3) node _T_2177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2176) node _T_2178 = bits(_T_2177, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2178 node _T_2179 = eq(UInt<5>(0h1d), idx_16) when _T_2179 : node _T_2180 = shl(UInt<5>(0h10), 3) node _T_2181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2180) node _T_2182 = bits(_T_2181, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2182 node _T_2183 = eq(UInt<5>(0h1e), idx_16) when _T_2183 : node _T_2184 = shl(UInt<5>(0h10), 3) node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184) node _T_2186 = bits(_T_2185, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2186 node _T_2187 = eq(UInt<5>(0h1f), idx_16) when _T_2187 : node _T_2188 = shl(UInt<5>(0h10), 3) node _T_2189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2188) node _T_2190 = bits(_T_2189, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2190 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_2191 = eq(UInt<1>(0h0), idx_17) when _T_2191 : node _T_2192 = shl(UInt<5>(0h11), 3) node _T_2193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2192) node _T_2194 = bits(_T_2193, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2194 node _T_2195 = eq(UInt<1>(0h1), idx_17) when _T_2195 : node _T_2196 = shl(UInt<5>(0h11), 3) node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196) node _T_2198 = bits(_T_2197, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2198 node _T_2199 = eq(UInt<2>(0h2), idx_17) when _T_2199 : node _T_2200 = shl(UInt<5>(0h11), 3) node _T_2201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2200) node _T_2202 = bits(_T_2201, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2202 node _T_2203 = eq(UInt<2>(0h3), idx_17) when _T_2203 : node _T_2204 = shl(UInt<5>(0h11), 3) node _T_2205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2204) node _T_2206 = bits(_T_2205, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2206 node _T_2207 = eq(UInt<3>(0h4), idx_17) when _T_2207 : node _T_2208 = shl(UInt<5>(0h11), 3) node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208) node _T_2210 = bits(_T_2209, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2210 node _T_2211 = eq(UInt<3>(0h5), idx_17) when _T_2211 : node _T_2212 = shl(UInt<5>(0h11), 3) node _T_2213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2212) node _T_2214 = bits(_T_2213, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2214 node _T_2215 = eq(UInt<3>(0h6), idx_17) when _T_2215 : node _T_2216 = shl(UInt<5>(0h11), 3) node _T_2217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2216) node _T_2218 = bits(_T_2217, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2218 node _T_2219 = eq(UInt<3>(0h7), idx_17) when _T_2219 : node _T_2220 = shl(UInt<5>(0h11), 3) node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220) node _T_2222 = bits(_T_2221, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2222 node _T_2223 = eq(UInt<4>(0h8), idx_17) when _T_2223 : node _T_2224 = shl(UInt<5>(0h11), 3) node _T_2225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2224) node _T_2226 = bits(_T_2225, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2226 node _T_2227 = eq(UInt<4>(0h9), idx_17) when _T_2227 : node _T_2228 = shl(UInt<5>(0h11), 3) node _T_2229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2228) node _T_2230 = bits(_T_2229, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2230 node _T_2231 = eq(UInt<4>(0ha), idx_17) when _T_2231 : node _T_2232 = shl(UInt<5>(0h11), 3) node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232) node _T_2234 = bits(_T_2233, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2234 node _T_2235 = eq(UInt<4>(0hb), idx_17) when _T_2235 : node _T_2236 = shl(UInt<5>(0h11), 3) node _T_2237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2236) node _T_2238 = bits(_T_2237, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2238 node _T_2239 = eq(UInt<4>(0hc), idx_17) when _T_2239 : node _T_2240 = shl(UInt<5>(0h11), 3) node _T_2241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2240) node _T_2242 = bits(_T_2241, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2242 node _T_2243 = eq(UInt<4>(0hd), idx_17) when _T_2243 : node _T_2244 = shl(UInt<5>(0h11), 3) node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244) node _T_2246 = bits(_T_2245, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2246 node _T_2247 = eq(UInt<4>(0he), idx_17) when _T_2247 : node _T_2248 = shl(UInt<5>(0h11), 3) node _T_2249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2248) node _T_2250 = bits(_T_2249, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2250 node _T_2251 = eq(UInt<4>(0hf), idx_17) when _T_2251 : node _T_2252 = shl(UInt<5>(0h11), 3) node _T_2253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2252) node _T_2254 = bits(_T_2253, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2254 node _T_2255 = eq(UInt<5>(0h10), idx_17) when _T_2255 : node _T_2256 = shl(UInt<5>(0h11), 3) node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256) node _T_2258 = bits(_T_2257, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2258 node _T_2259 = eq(UInt<5>(0h11), idx_17) when _T_2259 : node _T_2260 = shl(UInt<5>(0h11), 3) node _T_2261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2260) node _T_2262 = bits(_T_2261, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2262 node _T_2263 = eq(UInt<5>(0h12), idx_17) when _T_2263 : node _T_2264 = shl(UInt<5>(0h11), 3) node _T_2265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2264) node _T_2266 = bits(_T_2265, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2266 node _T_2267 = eq(UInt<5>(0h13), idx_17) when _T_2267 : node _T_2268 = shl(UInt<5>(0h11), 3) node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268) node _T_2270 = bits(_T_2269, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2270 node _T_2271 = eq(UInt<5>(0h14), idx_17) when _T_2271 : node _T_2272 = shl(UInt<5>(0h11), 3) node _T_2273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2272) node _T_2274 = bits(_T_2273, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2274 node _T_2275 = eq(UInt<5>(0h15), idx_17) when _T_2275 : node _T_2276 = shl(UInt<5>(0h11), 3) node _T_2277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2276) node _T_2278 = bits(_T_2277, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2278 node _T_2279 = eq(UInt<5>(0h16), idx_17) when _T_2279 : node _T_2280 = shl(UInt<5>(0h11), 3) node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280) node _T_2282 = bits(_T_2281, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2282 node _T_2283 = eq(UInt<5>(0h17), idx_17) when _T_2283 : node _T_2284 = shl(UInt<5>(0h11), 3) node _T_2285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2284) node _T_2286 = bits(_T_2285, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2286 node _T_2287 = eq(UInt<5>(0h18), idx_17) when _T_2287 : node _T_2288 = shl(UInt<5>(0h11), 3) node _T_2289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2288) node _T_2290 = bits(_T_2289, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2290 node _T_2291 = eq(UInt<5>(0h19), idx_17) when _T_2291 : node _T_2292 = shl(UInt<5>(0h11), 3) node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292) node _T_2294 = bits(_T_2293, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2294 node _T_2295 = eq(UInt<5>(0h1a), idx_17) when _T_2295 : node _T_2296 = shl(UInt<5>(0h11), 3) node _T_2297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2296) node _T_2298 = bits(_T_2297, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2298 node _T_2299 = eq(UInt<5>(0h1b), idx_17) when _T_2299 : node _T_2300 = shl(UInt<5>(0h11), 3) node _T_2301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2300) node _T_2302 = bits(_T_2301, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2302 node _T_2303 = eq(UInt<5>(0h1c), idx_17) when _T_2303 : node _T_2304 = shl(UInt<5>(0h11), 3) node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304) node _T_2306 = bits(_T_2305, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2306 node _T_2307 = eq(UInt<5>(0h1d), idx_17) when _T_2307 : node _T_2308 = shl(UInt<5>(0h11), 3) node _T_2309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2308) node _T_2310 = bits(_T_2309, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2310 node _T_2311 = eq(UInt<5>(0h1e), idx_17) when _T_2311 : node _T_2312 = shl(UInt<5>(0h11), 3) node _T_2313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2312) node _T_2314 = bits(_T_2313, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2314 node _T_2315 = eq(UInt<5>(0h1f), idx_17) when _T_2315 : node _T_2316 = shl(UInt<5>(0h11), 3) node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316) node _T_2318 = bits(_T_2317, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2318 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_2319 = eq(UInt<1>(0h0), idx_18) when _T_2319 : node _T_2320 = shl(UInt<5>(0h12), 3) node _T_2321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2320) node _T_2322 = bits(_T_2321, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2322 node _T_2323 = eq(UInt<1>(0h1), idx_18) when _T_2323 : node _T_2324 = shl(UInt<5>(0h12), 3) node _T_2325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2324) node _T_2326 = bits(_T_2325, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2326 node _T_2327 = eq(UInt<2>(0h2), idx_18) when _T_2327 : node _T_2328 = shl(UInt<5>(0h12), 3) node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328) node _T_2330 = bits(_T_2329, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2330 node _T_2331 = eq(UInt<2>(0h3), idx_18) when _T_2331 : node _T_2332 = shl(UInt<5>(0h12), 3) node _T_2333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2332) node _T_2334 = bits(_T_2333, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2334 node _T_2335 = eq(UInt<3>(0h4), idx_18) when _T_2335 : node _T_2336 = shl(UInt<5>(0h12), 3) node _T_2337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2336) node _T_2338 = bits(_T_2337, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2338 node _T_2339 = eq(UInt<3>(0h5), idx_18) when _T_2339 : node _T_2340 = shl(UInt<5>(0h12), 3) node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340) node _T_2342 = bits(_T_2341, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2342 node _T_2343 = eq(UInt<3>(0h6), idx_18) when _T_2343 : node _T_2344 = shl(UInt<5>(0h12), 3) node _T_2345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2344) node _T_2346 = bits(_T_2345, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2346 node _T_2347 = eq(UInt<3>(0h7), idx_18) when _T_2347 : node _T_2348 = shl(UInt<5>(0h12), 3) node _T_2349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2348) node _T_2350 = bits(_T_2349, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2350 node _T_2351 = eq(UInt<4>(0h8), idx_18) when _T_2351 : node _T_2352 = shl(UInt<5>(0h12), 3) node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352) node _T_2354 = bits(_T_2353, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2354 node _T_2355 = eq(UInt<4>(0h9), idx_18) when _T_2355 : node _T_2356 = shl(UInt<5>(0h12), 3) node _T_2357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2356) node _T_2358 = bits(_T_2357, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2358 node _T_2359 = eq(UInt<4>(0ha), idx_18) when _T_2359 : node _T_2360 = shl(UInt<5>(0h12), 3) node _T_2361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2360) node _T_2362 = bits(_T_2361, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2362 node _T_2363 = eq(UInt<4>(0hb), idx_18) when _T_2363 : node _T_2364 = shl(UInt<5>(0h12), 3) node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364) node _T_2366 = bits(_T_2365, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2366 node _T_2367 = eq(UInt<4>(0hc), idx_18) when _T_2367 : node _T_2368 = shl(UInt<5>(0h12), 3) node _T_2369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2368) node _T_2370 = bits(_T_2369, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2370 node _T_2371 = eq(UInt<4>(0hd), idx_18) when _T_2371 : node _T_2372 = shl(UInt<5>(0h12), 3) node _T_2373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2372) node _T_2374 = bits(_T_2373, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2374 node _T_2375 = eq(UInt<4>(0he), idx_18) when _T_2375 : node _T_2376 = shl(UInt<5>(0h12), 3) node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376) node _T_2378 = bits(_T_2377, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2378 node _T_2379 = eq(UInt<4>(0hf), idx_18) when _T_2379 : node _T_2380 = shl(UInt<5>(0h12), 3) node _T_2381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2380) node _T_2382 = bits(_T_2381, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2382 node _T_2383 = eq(UInt<5>(0h10), idx_18) when _T_2383 : node _T_2384 = shl(UInt<5>(0h12), 3) node _T_2385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2384) node _T_2386 = bits(_T_2385, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2386 node _T_2387 = eq(UInt<5>(0h11), idx_18) when _T_2387 : node _T_2388 = shl(UInt<5>(0h12), 3) node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388) node _T_2390 = bits(_T_2389, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2390 node _T_2391 = eq(UInt<5>(0h12), idx_18) when _T_2391 : node _T_2392 = shl(UInt<5>(0h12), 3) node _T_2393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2392) node _T_2394 = bits(_T_2393, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2394 node _T_2395 = eq(UInt<5>(0h13), idx_18) when _T_2395 : node _T_2396 = shl(UInt<5>(0h12), 3) node _T_2397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2396) node _T_2398 = bits(_T_2397, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2398 node _T_2399 = eq(UInt<5>(0h14), idx_18) when _T_2399 : node _T_2400 = shl(UInt<5>(0h12), 3) node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400) node _T_2402 = bits(_T_2401, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2402 node _T_2403 = eq(UInt<5>(0h15), idx_18) when _T_2403 : node _T_2404 = shl(UInt<5>(0h12), 3) node _T_2405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2404) node _T_2406 = bits(_T_2405, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2406 node _T_2407 = eq(UInt<5>(0h16), idx_18) when _T_2407 : node _T_2408 = shl(UInt<5>(0h12), 3) node _T_2409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2408) node _T_2410 = bits(_T_2409, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2410 node _T_2411 = eq(UInt<5>(0h17), idx_18) when _T_2411 : node _T_2412 = shl(UInt<5>(0h12), 3) node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412) node _T_2414 = bits(_T_2413, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2414 node _T_2415 = eq(UInt<5>(0h18), idx_18) when _T_2415 : node _T_2416 = shl(UInt<5>(0h12), 3) node _T_2417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2416) node _T_2418 = bits(_T_2417, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2418 node _T_2419 = eq(UInt<5>(0h19), idx_18) when _T_2419 : node _T_2420 = shl(UInt<5>(0h12), 3) node _T_2421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2420) node _T_2422 = bits(_T_2421, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2422 node _T_2423 = eq(UInt<5>(0h1a), idx_18) when _T_2423 : node _T_2424 = shl(UInt<5>(0h12), 3) node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424) node _T_2426 = bits(_T_2425, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2426 node _T_2427 = eq(UInt<5>(0h1b), idx_18) when _T_2427 : node _T_2428 = shl(UInt<5>(0h12), 3) node _T_2429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2428) node _T_2430 = bits(_T_2429, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2430 node _T_2431 = eq(UInt<5>(0h1c), idx_18) when _T_2431 : node _T_2432 = shl(UInt<5>(0h12), 3) node _T_2433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2432) node _T_2434 = bits(_T_2433, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2434 node _T_2435 = eq(UInt<5>(0h1d), idx_18) when _T_2435 : node _T_2436 = shl(UInt<5>(0h12), 3) node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436) node _T_2438 = bits(_T_2437, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2438 node _T_2439 = eq(UInt<5>(0h1e), idx_18) when _T_2439 : node _T_2440 = shl(UInt<5>(0h12), 3) node _T_2441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2440) node _T_2442 = bits(_T_2441, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2442 node _T_2443 = eq(UInt<5>(0h1f), idx_18) when _T_2443 : node _T_2444 = shl(UInt<5>(0h12), 3) node _T_2445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2444) node _T_2446 = bits(_T_2445, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2446 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_2447 = eq(UInt<1>(0h0), idx_19) when _T_2447 : node _T_2448 = shl(UInt<5>(0h13), 3) node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448) node _T_2450 = bits(_T_2449, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2450 node _T_2451 = eq(UInt<1>(0h1), idx_19) when _T_2451 : node _T_2452 = shl(UInt<5>(0h13), 3) node _T_2453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2452) node _T_2454 = bits(_T_2453, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2454 node _T_2455 = eq(UInt<2>(0h2), idx_19) when _T_2455 : node _T_2456 = shl(UInt<5>(0h13), 3) node _T_2457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2456) node _T_2458 = bits(_T_2457, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2458 node _T_2459 = eq(UInt<2>(0h3), idx_19) when _T_2459 : node _T_2460 = shl(UInt<5>(0h13), 3) node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460) node _T_2462 = bits(_T_2461, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2462 node _T_2463 = eq(UInt<3>(0h4), idx_19) when _T_2463 : node _T_2464 = shl(UInt<5>(0h13), 3) node _T_2465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2464) node _T_2466 = bits(_T_2465, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2466 node _T_2467 = eq(UInt<3>(0h5), idx_19) when _T_2467 : node _T_2468 = shl(UInt<5>(0h13), 3) node _T_2469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2468) node _T_2470 = bits(_T_2469, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2470 node _T_2471 = eq(UInt<3>(0h6), idx_19) when _T_2471 : node _T_2472 = shl(UInt<5>(0h13), 3) node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472) node _T_2474 = bits(_T_2473, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2474 node _T_2475 = eq(UInt<3>(0h7), idx_19) when _T_2475 : node _T_2476 = shl(UInt<5>(0h13), 3) node _T_2477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2476) node _T_2478 = bits(_T_2477, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2478 node _T_2479 = eq(UInt<4>(0h8), idx_19) when _T_2479 : node _T_2480 = shl(UInt<5>(0h13), 3) node _T_2481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2480) node _T_2482 = bits(_T_2481, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2482 node _T_2483 = eq(UInt<4>(0h9), idx_19) when _T_2483 : node _T_2484 = shl(UInt<5>(0h13), 3) node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484) node _T_2486 = bits(_T_2485, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2486 node _T_2487 = eq(UInt<4>(0ha), idx_19) when _T_2487 : node _T_2488 = shl(UInt<5>(0h13), 3) node _T_2489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2488) node _T_2490 = bits(_T_2489, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2490 node _T_2491 = eq(UInt<4>(0hb), idx_19) when _T_2491 : node _T_2492 = shl(UInt<5>(0h13), 3) node _T_2493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2492) node _T_2494 = bits(_T_2493, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2494 node _T_2495 = eq(UInt<4>(0hc), idx_19) when _T_2495 : node _T_2496 = shl(UInt<5>(0h13), 3) node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496) node _T_2498 = bits(_T_2497, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2498 node _T_2499 = eq(UInt<4>(0hd), idx_19) when _T_2499 : node _T_2500 = shl(UInt<5>(0h13), 3) node _T_2501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2500) node _T_2502 = bits(_T_2501, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2502 node _T_2503 = eq(UInt<4>(0he), idx_19) when _T_2503 : node _T_2504 = shl(UInt<5>(0h13), 3) node _T_2505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2504) node _T_2506 = bits(_T_2505, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2506 node _T_2507 = eq(UInt<4>(0hf), idx_19) when _T_2507 : node _T_2508 = shl(UInt<5>(0h13), 3) node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508) node _T_2510 = bits(_T_2509, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2510 node _T_2511 = eq(UInt<5>(0h10), idx_19) when _T_2511 : node _T_2512 = shl(UInt<5>(0h13), 3) node _T_2513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2512) node _T_2514 = bits(_T_2513, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2514 node _T_2515 = eq(UInt<5>(0h11), idx_19) when _T_2515 : node _T_2516 = shl(UInt<5>(0h13), 3) node _T_2517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2516) node _T_2518 = bits(_T_2517, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2518 node _T_2519 = eq(UInt<5>(0h12), idx_19) when _T_2519 : node _T_2520 = shl(UInt<5>(0h13), 3) node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520) node _T_2522 = bits(_T_2521, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2522 node _T_2523 = eq(UInt<5>(0h13), idx_19) when _T_2523 : node _T_2524 = shl(UInt<5>(0h13), 3) node _T_2525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2524) node _T_2526 = bits(_T_2525, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2526 node _T_2527 = eq(UInt<5>(0h14), idx_19) when _T_2527 : node _T_2528 = shl(UInt<5>(0h13), 3) node _T_2529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2528) node _T_2530 = bits(_T_2529, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2530 node _T_2531 = eq(UInt<5>(0h15), idx_19) when _T_2531 : node _T_2532 = shl(UInt<5>(0h13), 3) node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532) node _T_2534 = bits(_T_2533, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2534 node _T_2535 = eq(UInt<5>(0h16), idx_19) when _T_2535 : node _T_2536 = shl(UInt<5>(0h13), 3) node _T_2537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2536) node _T_2538 = bits(_T_2537, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2538 node _T_2539 = eq(UInt<5>(0h17), idx_19) when _T_2539 : node _T_2540 = shl(UInt<5>(0h13), 3) node _T_2541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2540) node _T_2542 = bits(_T_2541, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2542 node _T_2543 = eq(UInt<5>(0h18), idx_19) when _T_2543 : node _T_2544 = shl(UInt<5>(0h13), 3) node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544) node _T_2546 = bits(_T_2545, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2546 node _T_2547 = eq(UInt<5>(0h19), idx_19) when _T_2547 : node _T_2548 = shl(UInt<5>(0h13), 3) node _T_2549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2548) node _T_2550 = bits(_T_2549, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2550 node _T_2551 = eq(UInt<5>(0h1a), idx_19) when _T_2551 : node _T_2552 = shl(UInt<5>(0h13), 3) node _T_2553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2552) node _T_2554 = bits(_T_2553, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2554 node _T_2555 = eq(UInt<5>(0h1b), idx_19) when _T_2555 : node _T_2556 = shl(UInt<5>(0h13), 3) node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556) node _T_2558 = bits(_T_2557, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2558 node _T_2559 = eq(UInt<5>(0h1c), idx_19) when _T_2559 : node _T_2560 = shl(UInt<5>(0h13), 3) node _T_2561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2560) node _T_2562 = bits(_T_2561, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2562 node _T_2563 = eq(UInt<5>(0h1d), idx_19) when _T_2563 : node _T_2564 = shl(UInt<5>(0h13), 3) node _T_2565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2564) node _T_2566 = bits(_T_2565, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2566 node _T_2567 = eq(UInt<5>(0h1e), idx_19) when _T_2567 : node _T_2568 = shl(UInt<5>(0h13), 3) node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568) node _T_2570 = bits(_T_2569, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2570 node _T_2571 = eq(UInt<5>(0h1f), idx_19) when _T_2571 : node _T_2572 = shl(UInt<5>(0h13), 3) node _T_2573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2572) node _T_2574 = bits(_T_2573, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2574 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_2575 = eq(UInt<1>(0h0), idx_20) when _T_2575 : node _T_2576 = shl(UInt<5>(0h14), 3) node _T_2577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2576) node _T_2578 = bits(_T_2577, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2578 node _T_2579 = eq(UInt<1>(0h1), idx_20) when _T_2579 : node _T_2580 = shl(UInt<5>(0h14), 3) node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580) node _T_2582 = bits(_T_2581, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2582 node _T_2583 = eq(UInt<2>(0h2), idx_20) when _T_2583 : node _T_2584 = shl(UInt<5>(0h14), 3) node _T_2585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2584) node _T_2586 = bits(_T_2585, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2586 node _T_2587 = eq(UInt<2>(0h3), idx_20) when _T_2587 : node _T_2588 = shl(UInt<5>(0h14), 3) node _T_2589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2588) node _T_2590 = bits(_T_2589, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2590 node _T_2591 = eq(UInt<3>(0h4), idx_20) when _T_2591 : node _T_2592 = shl(UInt<5>(0h14), 3) node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592) node _T_2594 = bits(_T_2593, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2594 node _T_2595 = eq(UInt<3>(0h5), idx_20) when _T_2595 : node _T_2596 = shl(UInt<5>(0h14), 3) node _T_2597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2596) node _T_2598 = bits(_T_2597, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2598 node _T_2599 = eq(UInt<3>(0h6), idx_20) when _T_2599 : node _T_2600 = shl(UInt<5>(0h14), 3) node _T_2601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2600) node _T_2602 = bits(_T_2601, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2602 node _T_2603 = eq(UInt<3>(0h7), idx_20) when _T_2603 : node _T_2604 = shl(UInt<5>(0h14), 3) node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604) node _T_2606 = bits(_T_2605, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2606 node _T_2607 = eq(UInt<4>(0h8), idx_20) when _T_2607 : node _T_2608 = shl(UInt<5>(0h14), 3) node _T_2609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2608) node _T_2610 = bits(_T_2609, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2610 node _T_2611 = eq(UInt<4>(0h9), idx_20) when _T_2611 : node _T_2612 = shl(UInt<5>(0h14), 3) node _T_2613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2612) node _T_2614 = bits(_T_2613, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2614 node _T_2615 = eq(UInt<4>(0ha), idx_20) when _T_2615 : node _T_2616 = shl(UInt<5>(0h14), 3) node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616) node _T_2618 = bits(_T_2617, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2618 node _T_2619 = eq(UInt<4>(0hb), idx_20) when _T_2619 : node _T_2620 = shl(UInt<5>(0h14), 3) node _T_2621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2620) node _T_2622 = bits(_T_2621, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2622 node _T_2623 = eq(UInt<4>(0hc), idx_20) when _T_2623 : node _T_2624 = shl(UInt<5>(0h14), 3) node _T_2625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2624) node _T_2626 = bits(_T_2625, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2626 node _T_2627 = eq(UInt<4>(0hd), idx_20) when _T_2627 : node _T_2628 = shl(UInt<5>(0h14), 3) node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628) node _T_2630 = bits(_T_2629, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2630 node _T_2631 = eq(UInt<4>(0he), idx_20) when _T_2631 : node _T_2632 = shl(UInt<5>(0h14), 3) node _T_2633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2632) node _T_2634 = bits(_T_2633, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2634 node _T_2635 = eq(UInt<4>(0hf), idx_20) when _T_2635 : node _T_2636 = shl(UInt<5>(0h14), 3) node _T_2637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2636) node _T_2638 = bits(_T_2637, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2638 node _T_2639 = eq(UInt<5>(0h10), idx_20) when _T_2639 : node _T_2640 = shl(UInt<5>(0h14), 3) node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640) node _T_2642 = bits(_T_2641, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2642 node _T_2643 = eq(UInt<5>(0h11), idx_20) when _T_2643 : node _T_2644 = shl(UInt<5>(0h14), 3) node _T_2645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2644) node _T_2646 = bits(_T_2645, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2646 node _T_2647 = eq(UInt<5>(0h12), idx_20) when _T_2647 : node _T_2648 = shl(UInt<5>(0h14), 3) node _T_2649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2648) node _T_2650 = bits(_T_2649, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2650 node _T_2651 = eq(UInt<5>(0h13), idx_20) when _T_2651 : node _T_2652 = shl(UInt<5>(0h14), 3) node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652) node _T_2654 = bits(_T_2653, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2654 node _T_2655 = eq(UInt<5>(0h14), idx_20) when _T_2655 : node _T_2656 = shl(UInt<5>(0h14), 3) node _T_2657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2656) node _T_2658 = bits(_T_2657, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2658 node _T_2659 = eq(UInt<5>(0h15), idx_20) when _T_2659 : node _T_2660 = shl(UInt<5>(0h14), 3) node _T_2661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2660) node _T_2662 = bits(_T_2661, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2662 node _T_2663 = eq(UInt<5>(0h16), idx_20) when _T_2663 : node _T_2664 = shl(UInt<5>(0h14), 3) node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664) node _T_2666 = bits(_T_2665, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2666 node _T_2667 = eq(UInt<5>(0h17), idx_20) when _T_2667 : node _T_2668 = shl(UInt<5>(0h14), 3) node _T_2669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2668) node _T_2670 = bits(_T_2669, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2670 node _T_2671 = eq(UInt<5>(0h18), idx_20) when _T_2671 : node _T_2672 = shl(UInt<5>(0h14), 3) node _T_2673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2672) node _T_2674 = bits(_T_2673, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2674 node _T_2675 = eq(UInt<5>(0h19), idx_20) when _T_2675 : node _T_2676 = shl(UInt<5>(0h14), 3) node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676) node _T_2678 = bits(_T_2677, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2678 node _T_2679 = eq(UInt<5>(0h1a), idx_20) when _T_2679 : node _T_2680 = shl(UInt<5>(0h14), 3) node _T_2681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2680) node _T_2682 = bits(_T_2681, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2682 node _T_2683 = eq(UInt<5>(0h1b), idx_20) when _T_2683 : node _T_2684 = shl(UInt<5>(0h14), 3) node _T_2685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2684) node _T_2686 = bits(_T_2685, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2686 node _T_2687 = eq(UInt<5>(0h1c), idx_20) when _T_2687 : node _T_2688 = shl(UInt<5>(0h14), 3) node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688) node _T_2690 = bits(_T_2689, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2690 node _T_2691 = eq(UInt<5>(0h1d), idx_20) when _T_2691 : node _T_2692 = shl(UInt<5>(0h14), 3) node _T_2693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2692) node _T_2694 = bits(_T_2693, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2694 node _T_2695 = eq(UInt<5>(0h1e), idx_20) when _T_2695 : node _T_2696 = shl(UInt<5>(0h14), 3) node _T_2697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2696) node _T_2698 = bits(_T_2697, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2698 node _T_2699 = eq(UInt<5>(0h1f), idx_20) when _T_2699 : node _T_2700 = shl(UInt<5>(0h14), 3) node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700) node _T_2702 = bits(_T_2701, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2702 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_2703 = eq(UInt<1>(0h0), idx_21) when _T_2703 : node _T_2704 = shl(UInt<5>(0h15), 3) node _T_2705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2704) node _T_2706 = bits(_T_2705, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2706 node _T_2707 = eq(UInt<1>(0h1), idx_21) when _T_2707 : node _T_2708 = shl(UInt<5>(0h15), 3) node _T_2709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2708) node _T_2710 = bits(_T_2709, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2710 node _T_2711 = eq(UInt<2>(0h2), idx_21) when _T_2711 : node _T_2712 = shl(UInt<5>(0h15), 3) node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712) node _T_2714 = bits(_T_2713, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2714 node _T_2715 = eq(UInt<2>(0h3), idx_21) when _T_2715 : node _T_2716 = shl(UInt<5>(0h15), 3) node _T_2717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2716) node _T_2718 = bits(_T_2717, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2718 node _T_2719 = eq(UInt<3>(0h4), idx_21) when _T_2719 : node _T_2720 = shl(UInt<5>(0h15), 3) node _T_2721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2720) node _T_2722 = bits(_T_2721, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2722 node _T_2723 = eq(UInt<3>(0h5), idx_21) when _T_2723 : node _T_2724 = shl(UInt<5>(0h15), 3) node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724) node _T_2726 = bits(_T_2725, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2726 node _T_2727 = eq(UInt<3>(0h6), idx_21) when _T_2727 : node _T_2728 = shl(UInt<5>(0h15), 3) node _T_2729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2728) node _T_2730 = bits(_T_2729, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2730 node _T_2731 = eq(UInt<3>(0h7), idx_21) when _T_2731 : node _T_2732 = shl(UInt<5>(0h15), 3) node _T_2733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2732) node _T_2734 = bits(_T_2733, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2734 node _T_2735 = eq(UInt<4>(0h8), idx_21) when _T_2735 : node _T_2736 = shl(UInt<5>(0h15), 3) node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736) node _T_2738 = bits(_T_2737, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2738 node _T_2739 = eq(UInt<4>(0h9), idx_21) when _T_2739 : node _T_2740 = shl(UInt<5>(0h15), 3) node _T_2741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2740) node _T_2742 = bits(_T_2741, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2742 node _T_2743 = eq(UInt<4>(0ha), idx_21) when _T_2743 : node _T_2744 = shl(UInt<5>(0h15), 3) node _T_2745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2744) node _T_2746 = bits(_T_2745, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2746 node _T_2747 = eq(UInt<4>(0hb), idx_21) when _T_2747 : node _T_2748 = shl(UInt<5>(0h15), 3) node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748) node _T_2750 = bits(_T_2749, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2750 node _T_2751 = eq(UInt<4>(0hc), idx_21) when _T_2751 : node _T_2752 = shl(UInt<5>(0h15), 3) node _T_2753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2752) node _T_2754 = bits(_T_2753, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2754 node _T_2755 = eq(UInt<4>(0hd), idx_21) when _T_2755 : node _T_2756 = shl(UInt<5>(0h15), 3) node _T_2757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2756) node _T_2758 = bits(_T_2757, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2758 node _T_2759 = eq(UInt<4>(0he), idx_21) when _T_2759 : node _T_2760 = shl(UInt<5>(0h15), 3) node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760) node _T_2762 = bits(_T_2761, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2762 node _T_2763 = eq(UInt<4>(0hf), idx_21) when _T_2763 : node _T_2764 = shl(UInt<5>(0h15), 3) node _T_2765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2764) node _T_2766 = bits(_T_2765, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2766 node _T_2767 = eq(UInt<5>(0h10), idx_21) when _T_2767 : node _T_2768 = shl(UInt<5>(0h15), 3) node _T_2769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2768) node _T_2770 = bits(_T_2769, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2770 node _T_2771 = eq(UInt<5>(0h11), idx_21) when _T_2771 : node _T_2772 = shl(UInt<5>(0h15), 3) node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772) node _T_2774 = bits(_T_2773, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2774 node _T_2775 = eq(UInt<5>(0h12), idx_21) when _T_2775 : node _T_2776 = shl(UInt<5>(0h15), 3) node _T_2777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2776) node _T_2778 = bits(_T_2777, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2778 node _T_2779 = eq(UInt<5>(0h13), idx_21) when _T_2779 : node _T_2780 = shl(UInt<5>(0h15), 3) node _T_2781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2780) node _T_2782 = bits(_T_2781, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2782 node _T_2783 = eq(UInt<5>(0h14), idx_21) when _T_2783 : node _T_2784 = shl(UInt<5>(0h15), 3) node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784) node _T_2786 = bits(_T_2785, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2786 node _T_2787 = eq(UInt<5>(0h15), idx_21) when _T_2787 : node _T_2788 = shl(UInt<5>(0h15), 3) node _T_2789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2788) node _T_2790 = bits(_T_2789, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2790 node _T_2791 = eq(UInt<5>(0h16), idx_21) when _T_2791 : node _T_2792 = shl(UInt<5>(0h15), 3) node _T_2793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2792) node _T_2794 = bits(_T_2793, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2794 node _T_2795 = eq(UInt<5>(0h17), idx_21) when _T_2795 : node _T_2796 = shl(UInt<5>(0h15), 3) node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796) node _T_2798 = bits(_T_2797, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2798 node _T_2799 = eq(UInt<5>(0h18), idx_21) when _T_2799 : node _T_2800 = shl(UInt<5>(0h15), 3) node _T_2801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2800) node _T_2802 = bits(_T_2801, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2802 node _T_2803 = eq(UInt<5>(0h19), idx_21) when _T_2803 : node _T_2804 = shl(UInt<5>(0h15), 3) node _T_2805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2804) node _T_2806 = bits(_T_2805, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2806 node _T_2807 = eq(UInt<5>(0h1a), idx_21) when _T_2807 : node _T_2808 = shl(UInt<5>(0h15), 3) node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808) node _T_2810 = bits(_T_2809, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2810 node _T_2811 = eq(UInt<5>(0h1b), idx_21) when _T_2811 : node _T_2812 = shl(UInt<5>(0h15), 3) node _T_2813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2812) node _T_2814 = bits(_T_2813, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2814 node _T_2815 = eq(UInt<5>(0h1c), idx_21) when _T_2815 : node _T_2816 = shl(UInt<5>(0h15), 3) node _T_2817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2816) node _T_2818 = bits(_T_2817, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2818 node _T_2819 = eq(UInt<5>(0h1d), idx_21) when _T_2819 : node _T_2820 = shl(UInt<5>(0h15), 3) node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820) node _T_2822 = bits(_T_2821, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2822 node _T_2823 = eq(UInt<5>(0h1e), idx_21) when _T_2823 : node _T_2824 = shl(UInt<5>(0h15), 3) node _T_2825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2824) node _T_2826 = bits(_T_2825, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2826 node _T_2827 = eq(UInt<5>(0h1f), idx_21) when _T_2827 : node _T_2828 = shl(UInt<5>(0h15), 3) node _T_2829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2828) node _T_2830 = bits(_T_2829, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2830 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_2831 = eq(UInt<1>(0h0), idx_22) when _T_2831 : node _T_2832 = shl(UInt<5>(0h16), 3) node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832) node _T_2834 = bits(_T_2833, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2834 node _T_2835 = eq(UInt<1>(0h1), idx_22) when _T_2835 : node _T_2836 = shl(UInt<5>(0h16), 3) node _T_2837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2836) node _T_2838 = bits(_T_2837, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2838 node _T_2839 = eq(UInt<2>(0h2), idx_22) when _T_2839 : node _T_2840 = shl(UInt<5>(0h16), 3) node _T_2841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2840) node _T_2842 = bits(_T_2841, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2842 node _T_2843 = eq(UInt<2>(0h3), idx_22) when _T_2843 : node _T_2844 = shl(UInt<5>(0h16), 3) node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844) node _T_2846 = bits(_T_2845, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2846 node _T_2847 = eq(UInt<3>(0h4), idx_22) when _T_2847 : node _T_2848 = shl(UInt<5>(0h16), 3) node _T_2849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2848) node _T_2850 = bits(_T_2849, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2850 node _T_2851 = eq(UInt<3>(0h5), idx_22) when _T_2851 : node _T_2852 = shl(UInt<5>(0h16), 3) node _T_2853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2852) node _T_2854 = bits(_T_2853, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2854 node _T_2855 = eq(UInt<3>(0h6), idx_22) when _T_2855 : node _T_2856 = shl(UInt<5>(0h16), 3) node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856) node _T_2858 = bits(_T_2857, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2858 node _T_2859 = eq(UInt<3>(0h7), idx_22) when _T_2859 : node _T_2860 = shl(UInt<5>(0h16), 3) node _T_2861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2860) node _T_2862 = bits(_T_2861, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2862 node _T_2863 = eq(UInt<4>(0h8), idx_22) when _T_2863 : node _T_2864 = shl(UInt<5>(0h16), 3) node _T_2865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2864) node _T_2866 = bits(_T_2865, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2866 node _T_2867 = eq(UInt<4>(0h9), idx_22) when _T_2867 : node _T_2868 = shl(UInt<5>(0h16), 3) node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868) node _T_2870 = bits(_T_2869, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2870 node _T_2871 = eq(UInt<4>(0ha), idx_22) when _T_2871 : node _T_2872 = shl(UInt<5>(0h16), 3) node _T_2873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2872) node _T_2874 = bits(_T_2873, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_2874 node _T_2875 = eq(UInt<4>(0hb), idx_22) when _T_2875 : node _T_2876 = shl(UInt<5>(0h16), 3) node _T_2877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2876) node _T_2878 = bits(_T_2877, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_2878 node _T_2879 = eq(UInt<4>(0hc), idx_22) when _T_2879 : node _T_2880 = shl(UInt<5>(0h16), 3) node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880) node _T_2882 = bits(_T_2881, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_2882 node _T_2883 = eq(UInt<4>(0hd), idx_22) when _T_2883 : node _T_2884 = shl(UInt<5>(0h16), 3) node _T_2885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2884) node _T_2886 = bits(_T_2885, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_2886 node _T_2887 = eq(UInt<4>(0he), idx_22) when _T_2887 : node _T_2888 = shl(UInt<5>(0h16), 3) node _T_2889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2888) node _T_2890 = bits(_T_2889, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_2890 node _T_2891 = eq(UInt<4>(0hf), idx_22) when _T_2891 : node _T_2892 = shl(UInt<5>(0h16), 3) node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892) node _T_2894 = bits(_T_2893, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_2894 node _T_2895 = eq(UInt<5>(0h10), idx_22) when _T_2895 : node _T_2896 = shl(UInt<5>(0h16), 3) node _T_2897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2896) node _T_2898 = bits(_T_2897, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_2898 node _T_2899 = eq(UInt<5>(0h11), idx_22) when _T_2899 : node _T_2900 = shl(UInt<5>(0h16), 3) node _T_2901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2900) node _T_2902 = bits(_T_2901, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_2902 node _T_2903 = eq(UInt<5>(0h12), idx_22) when _T_2903 : node _T_2904 = shl(UInt<5>(0h16), 3) node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904) node _T_2906 = bits(_T_2905, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_2906 node _T_2907 = eq(UInt<5>(0h13), idx_22) when _T_2907 : node _T_2908 = shl(UInt<5>(0h16), 3) node _T_2909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2908) node _T_2910 = bits(_T_2909, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_2910 node _T_2911 = eq(UInt<5>(0h14), idx_22) when _T_2911 : node _T_2912 = shl(UInt<5>(0h16), 3) node _T_2913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2912) node _T_2914 = bits(_T_2913, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_2914 node _T_2915 = eq(UInt<5>(0h15), idx_22) when _T_2915 : node _T_2916 = shl(UInt<5>(0h16), 3) node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916) node _T_2918 = bits(_T_2917, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_2918 node _T_2919 = eq(UInt<5>(0h16), idx_22) when _T_2919 : node _T_2920 = shl(UInt<5>(0h16), 3) node _T_2921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2920) node _T_2922 = bits(_T_2921, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_2922 node _T_2923 = eq(UInt<5>(0h17), idx_22) when _T_2923 : node _T_2924 = shl(UInt<5>(0h16), 3) node _T_2925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2924) node _T_2926 = bits(_T_2925, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_2926 node _T_2927 = eq(UInt<5>(0h18), idx_22) when _T_2927 : node _T_2928 = shl(UInt<5>(0h16), 3) node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928) node _T_2930 = bits(_T_2929, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_2930 node _T_2931 = eq(UInt<5>(0h19), idx_22) when _T_2931 : node _T_2932 = shl(UInt<5>(0h16), 3) node _T_2933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2932) node _T_2934 = bits(_T_2933, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_2934 node _T_2935 = eq(UInt<5>(0h1a), idx_22) when _T_2935 : node _T_2936 = shl(UInt<5>(0h16), 3) node _T_2937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2936) node _T_2938 = bits(_T_2937, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_2938 node _T_2939 = eq(UInt<5>(0h1b), idx_22) when _T_2939 : node _T_2940 = shl(UInt<5>(0h16), 3) node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940) node _T_2942 = bits(_T_2941, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_2942 node _T_2943 = eq(UInt<5>(0h1c), idx_22) when _T_2943 : node _T_2944 = shl(UInt<5>(0h16), 3) node _T_2945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2944) node _T_2946 = bits(_T_2945, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_2946 node _T_2947 = eq(UInt<5>(0h1d), idx_22) when _T_2947 : node _T_2948 = shl(UInt<5>(0h16), 3) node _T_2949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2948) node _T_2950 = bits(_T_2949, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_2950 node _T_2951 = eq(UInt<5>(0h1e), idx_22) when _T_2951 : node _T_2952 = shl(UInt<5>(0h16), 3) node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952) node _T_2954 = bits(_T_2953, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_2954 node _T_2955 = eq(UInt<5>(0h1f), idx_22) when _T_2955 : node _T_2956 = shl(UInt<5>(0h16), 3) node _T_2957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2956) node _T_2958 = bits(_T_2957, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_2958 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_2959 = eq(UInt<1>(0h0), idx_23) when _T_2959 : node _T_2960 = shl(UInt<5>(0h17), 3) node _T_2961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2960) node _T_2962 = bits(_T_2961, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_2962 node _T_2963 = eq(UInt<1>(0h1), idx_23) when _T_2963 : node _T_2964 = shl(UInt<5>(0h17), 3) node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964) node _T_2966 = bits(_T_2965, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_2966 node _T_2967 = eq(UInt<2>(0h2), idx_23) when _T_2967 : node _T_2968 = shl(UInt<5>(0h17), 3) node _T_2969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2968) node _T_2970 = bits(_T_2969, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_2970 node _T_2971 = eq(UInt<2>(0h3), idx_23) when _T_2971 : node _T_2972 = shl(UInt<5>(0h17), 3) node _T_2973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2972) node _T_2974 = bits(_T_2973, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_2974 node _T_2975 = eq(UInt<3>(0h4), idx_23) when _T_2975 : node _T_2976 = shl(UInt<5>(0h17), 3) node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976) node _T_2978 = bits(_T_2977, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_2978 node _T_2979 = eq(UInt<3>(0h5), idx_23) when _T_2979 : node _T_2980 = shl(UInt<5>(0h17), 3) node _T_2981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2980) node _T_2982 = bits(_T_2981, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_2982 node _T_2983 = eq(UInt<3>(0h6), idx_23) when _T_2983 : node _T_2984 = shl(UInt<5>(0h17), 3) node _T_2985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2984) node _T_2986 = bits(_T_2985, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_2986 node _T_2987 = eq(UInt<3>(0h7), idx_23) when _T_2987 : node _T_2988 = shl(UInt<5>(0h17), 3) node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988) node _T_2990 = bits(_T_2989, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_2990 node _T_2991 = eq(UInt<4>(0h8), idx_23) when _T_2991 : node _T_2992 = shl(UInt<5>(0h17), 3) node _T_2993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2992) node _T_2994 = bits(_T_2993, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_2994 node _T_2995 = eq(UInt<4>(0h9), idx_23) when _T_2995 : node _T_2996 = shl(UInt<5>(0h17), 3) node _T_2997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2996) node _T_2998 = bits(_T_2997, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_2998 node _T_2999 = eq(UInt<4>(0ha), idx_23) when _T_2999 : node _T_3000 = shl(UInt<5>(0h17), 3) node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000) node _T_3002 = bits(_T_3001, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3002 node _T_3003 = eq(UInt<4>(0hb), idx_23) when _T_3003 : node _T_3004 = shl(UInt<5>(0h17), 3) node _T_3005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3004) node _T_3006 = bits(_T_3005, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3006 node _T_3007 = eq(UInt<4>(0hc), idx_23) when _T_3007 : node _T_3008 = shl(UInt<5>(0h17), 3) node _T_3009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3008) node _T_3010 = bits(_T_3009, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3010 node _T_3011 = eq(UInt<4>(0hd), idx_23) when _T_3011 : node _T_3012 = shl(UInt<5>(0h17), 3) node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012) node _T_3014 = bits(_T_3013, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3014 node _T_3015 = eq(UInt<4>(0he), idx_23) when _T_3015 : node _T_3016 = shl(UInt<5>(0h17), 3) node _T_3017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3016) node _T_3018 = bits(_T_3017, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3018 node _T_3019 = eq(UInt<4>(0hf), idx_23) when _T_3019 : node _T_3020 = shl(UInt<5>(0h17), 3) node _T_3021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3020) node _T_3022 = bits(_T_3021, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3022 node _T_3023 = eq(UInt<5>(0h10), idx_23) when _T_3023 : node _T_3024 = shl(UInt<5>(0h17), 3) node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024) node _T_3026 = bits(_T_3025, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3026 node _T_3027 = eq(UInt<5>(0h11), idx_23) when _T_3027 : node _T_3028 = shl(UInt<5>(0h17), 3) node _T_3029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3028) node _T_3030 = bits(_T_3029, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3030 node _T_3031 = eq(UInt<5>(0h12), idx_23) when _T_3031 : node _T_3032 = shl(UInt<5>(0h17), 3) node _T_3033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3032) node _T_3034 = bits(_T_3033, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3034 node _T_3035 = eq(UInt<5>(0h13), idx_23) when _T_3035 : node _T_3036 = shl(UInt<5>(0h17), 3) node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036) node _T_3038 = bits(_T_3037, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3038 node _T_3039 = eq(UInt<5>(0h14), idx_23) when _T_3039 : node _T_3040 = shl(UInt<5>(0h17), 3) node _T_3041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3040) node _T_3042 = bits(_T_3041, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3042 node _T_3043 = eq(UInt<5>(0h15), idx_23) when _T_3043 : node _T_3044 = shl(UInt<5>(0h17), 3) node _T_3045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3044) node _T_3046 = bits(_T_3045, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3046 node _T_3047 = eq(UInt<5>(0h16), idx_23) when _T_3047 : node _T_3048 = shl(UInt<5>(0h17), 3) node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048) node _T_3050 = bits(_T_3049, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3050 node _T_3051 = eq(UInt<5>(0h17), idx_23) when _T_3051 : node _T_3052 = shl(UInt<5>(0h17), 3) node _T_3053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3052) node _T_3054 = bits(_T_3053, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3054 node _T_3055 = eq(UInt<5>(0h18), idx_23) when _T_3055 : node _T_3056 = shl(UInt<5>(0h17), 3) node _T_3057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3056) node _T_3058 = bits(_T_3057, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3058 node _T_3059 = eq(UInt<5>(0h19), idx_23) when _T_3059 : node _T_3060 = shl(UInt<5>(0h17), 3) node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060) node _T_3062 = bits(_T_3061, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3062 node _T_3063 = eq(UInt<5>(0h1a), idx_23) when _T_3063 : node _T_3064 = shl(UInt<5>(0h17), 3) node _T_3065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3064) node _T_3066 = bits(_T_3065, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3066 node _T_3067 = eq(UInt<5>(0h1b), idx_23) when _T_3067 : node _T_3068 = shl(UInt<5>(0h17), 3) node _T_3069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3068) node _T_3070 = bits(_T_3069, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3070 node _T_3071 = eq(UInt<5>(0h1c), idx_23) when _T_3071 : node _T_3072 = shl(UInt<5>(0h17), 3) node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072) node _T_3074 = bits(_T_3073, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3074 node _T_3075 = eq(UInt<5>(0h1d), idx_23) when _T_3075 : node _T_3076 = shl(UInt<5>(0h17), 3) node _T_3077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3076) node _T_3078 = bits(_T_3077, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3078 node _T_3079 = eq(UInt<5>(0h1e), idx_23) when _T_3079 : node _T_3080 = shl(UInt<5>(0h17), 3) node _T_3081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3080) node _T_3082 = bits(_T_3081, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3082 node _T_3083 = eq(UInt<5>(0h1f), idx_23) when _T_3083 : node _T_3084 = shl(UInt<5>(0h17), 3) node _T_3085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3084) node _T_3086 = bits(_T_3085, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3086 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_3087 = eq(UInt<1>(0h0), idx_24) when _T_3087 : node _T_3088 = shl(UInt<5>(0h18), 3) node _T_3089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3088) node _T_3090 = bits(_T_3089, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3090 node _T_3091 = eq(UInt<1>(0h1), idx_24) when _T_3091 : node _T_3092 = shl(UInt<5>(0h18), 3) node _T_3093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3092) node _T_3094 = bits(_T_3093, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3094 node _T_3095 = eq(UInt<2>(0h2), idx_24) when _T_3095 : node _T_3096 = shl(UInt<5>(0h18), 3) node _T_3097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3096) node _T_3098 = bits(_T_3097, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3098 node _T_3099 = eq(UInt<2>(0h3), idx_24) when _T_3099 : node _T_3100 = shl(UInt<5>(0h18), 3) node _T_3101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3100) node _T_3102 = bits(_T_3101, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3102 node _T_3103 = eq(UInt<3>(0h4), idx_24) when _T_3103 : node _T_3104 = shl(UInt<5>(0h18), 3) node _T_3105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3104) node _T_3106 = bits(_T_3105, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3106 node _T_3107 = eq(UInt<3>(0h5), idx_24) when _T_3107 : node _T_3108 = shl(UInt<5>(0h18), 3) node _T_3109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3108) node _T_3110 = bits(_T_3109, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3110 node _T_3111 = eq(UInt<3>(0h6), idx_24) when _T_3111 : node _T_3112 = shl(UInt<5>(0h18), 3) node _T_3113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3112) node _T_3114 = bits(_T_3113, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3114 node _T_3115 = eq(UInt<3>(0h7), idx_24) when _T_3115 : node _T_3116 = shl(UInt<5>(0h18), 3) node _T_3117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3116) node _T_3118 = bits(_T_3117, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3118 node _T_3119 = eq(UInt<4>(0h8), idx_24) when _T_3119 : node _T_3120 = shl(UInt<5>(0h18), 3) node _T_3121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3120) node _T_3122 = bits(_T_3121, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3122 node _T_3123 = eq(UInt<4>(0h9), idx_24) when _T_3123 : node _T_3124 = shl(UInt<5>(0h18), 3) node _T_3125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3124) node _T_3126 = bits(_T_3125, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3126 node _T_3127 = eq(UInt<4>(0ha), idx_24) when _T_3127 : node _T_3128 = shl(UInt<5>(0h18), 3) node _T_3129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3128) node _T_3130 = bits(_T_3129, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3130 node _T_3131 = eq(UInt<4>(0hb), idx_24) when _T_3131 : node _T_3132 = shl(UInt<5>(0h18), 3) node _T_3133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3132) node _T_3134 = bits(_T_3133, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3134 node _T_3135 = eq(UInt<4>(0hc), idx_24) when _T_3135 : node _T_3136 = shl(UInt<5>(0h18), 3) node _T_3137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3136) node _T_3138 = bits(_T_3137, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3138 node _T_3139 = eq(UInt<4>(0hd), idx_24) when _T_3139 : node _T_3140 = shl(UInt<5>(0h18), 3) node _T_3141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3140) node _T_3142 = bits(_T_3141, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3142 node _T_3143 = eq(UInt<4>(0he), idx_24) when _T_3143 : node _T_3144 = shl(UInt<5>(0h18), 3) node _T_3145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3144) node _T_3146 = bits(_T_3145, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3146 node _T_3147 = eq(UInt<4>(0hf), idx_24) when _T_3147 : node _T_3148 = shl(UInt<5>(0h18), 3) node _T_3149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3148) node _T_3150 = bits(_T_3149, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3150 node _T_3151 = eq(UInt<5>(0h10), idx_24) when _T_3151 : node _T_3152 = shl(UInt<5>(0h18), 3) node _T_3153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3152) node _T_3154 = bits(_T_3153, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3154 node _T_3155 = eq(UInt<5>(0h11), idx_24) when _T_3155 : node _T_3156 = shl(UInt<5>(0h18), 3) node _T_3157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3156) node _T_3158 = bits(_T_3157, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3158 node _T_3159 = eq(UInt<5>(0h12), idx_24) when _T_3159 : node _T_3160 = shl(UInt<5>(0h18), 3) node _T_3161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3160) node _T_3162 = bits(_T_3161, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3162 node _T_3163 = eq(UInt<5>(0h13), idx_24) when _T_3163 : node _T_3164 = shl(UInt<5>(0h18), 3) node _T_3165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3164) node _T_3166 = bits(_T_3165, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3166 node _T_3167 = eq(UInt<5>(0h14), idx_24) when _T_3167 : node _T_3168 = shl(UInt<5>(0h18), 3) node _T_3169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3168) node _T_3170 = bits(_T_3169, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3170 node _T_3171 = eq(UInt<5>(0h15), idx_24) when _T_3171 : node _T_3172 = shl(UInt<5>(0h18), 3) node _T_3173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3172) node _T_3174 = bits(_T_3173, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3174 node _T_3175 = eq(UInt<5>(0h16), idx_24) when _T_3175 : node _T_3176 = shl(UInt<5>(0h18), 3) node _T_3177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3176) node _T_3178 = bits(_T_3177, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3178 node _T_3179 = eq(UInt<5>(0h17), idx_24) when _T_3179 : node _T_3180 = shl(UInt<5>(0h18), 3) node _T_3181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3180) node _T_3182 = bits(_T_3181, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3182 node _T_3183 = eq(UInt<5>(0h18), idx_24) when _T_3183 : node _T_3184 = shl(UInt<5>(0h18), 3) node _T_3185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3184) node _T_3186 = bits(_T_3185, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3186 node _T_3187 = eq(UInt<5>(0h19), idx_24) when _T_3187 : node _T_3188 = shl(UInt<5>(0h18), 3) node _T_3189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3188) node _T_3190 = bits(_T_3189, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3190 node _T_3191 = eq(UInt<5>(0h1a), idx_24) when _T_3191 : node _T_3192 = shl(UInt<5>(0h18), 3) node _T_3193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3192) node _T_3194 = bits(_T_3193, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3194 node _T_3195 = eq(UInt<5>(0h1b), idx_24) when _T_3195 : node _T_3196 = shl(UInt<5>(0h18), 3) node _T_3197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3196) node _T_3198 = bits(_T_3197, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3198 node _T_3199 = eq(UInt<5>(0h1c), idx_24) when _T_3199 : node _T_3200 = shl(UInt<5>(0h18), 3) node _T_3201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3200) node _T_3202 = bits(_T_3201, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3202 node _T_3203 = eq(UInt<5>(0h1d), idx_24) when _T_3203 : node _T_3204 = shl(UInt<5>(0h18), 3) node _T_3205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3204) node _T_3206 = bits(_T_3205, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3206 node _T_3207 = eq(UInt<5>(0h1e), idx_24) when _T_3207 : node _T_3208 = shl(UInt<5>(0h18), 3) node _T_3209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3208) node _T_3210 = bits(_T_3209, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3210 node _T_3211 = eq(UInt<5>(0h1f), idx_24) when _T_3211 : node _T_3212 = shl(UInt<5>(0h18), 3) node _T_3213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3212) node _T_3214 = bits(_T_3213, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3214 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_3215 = eq(UInt<1>(0h0), idx_25) when _T_3215 : node _T_3216 = shl(UInt<5>(0h19), 3) node _T_3217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3216) node _T_3218 = bits(_T_3217, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3218 node _T_3219 = eq(UInt<1>(0h1), idx_25) when _T_3219 : node _T_3220 = shl(UInt<5>(0h19), 3) node _T_3221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3220) node _T_3222 = bits(_T_3221, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3222 node _T_3223 = eq(UInt<2>(0h2), idx_25) when _T_3223 : node _T_3224 = shl(UInt<5>(0h19), 3) node _T_3225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3224) node _T_3226 = bits(_T_3225, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3226 node _T_3227 = eq(UInt<2>(0h3), idx_25) when _T_3227 : node _T_3228 = shl(UInt<5>(0h19), 3) node _T_3229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3228) node _T_3230 = bits(_T_3229, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3230 node _T_3231 = eq(UInt<3>(0h4), idx_25) when _T_3231 : node _T_3232 = shl(UInt<5>(0h19), 3) node _T_3233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3232) node _T_3234 = bits(_T_3233, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3234 node _T_3235 = eq(UInt<3>(0h5), idx_25) when _T_3235 : node _T_3236 = shl(UInt<5>(0h19), 3) node _T_3237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3236) node _T_3238 = bits(_T_3237, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3238 node _T_3239 = eq(UInt<3>(0h6), idx_25) when _T_3239 : node _T_3240 = shl(UInt<5>(0h19), 3) node _T_3241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3240) node _T_3242 = bits(_T_3241, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3242 node _T_3243 = eq(UInt<3>(0h7), idx_25) when _T_3243 : node _T_3244 = shl(UInt<5>(0h19), 3) node _T_3245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3244) node _T_3246 = bits(_T_3245, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3246 node _T_3247 = eq(UInt<4>(0h8), idx_25) when _T_3247 : node _T_3248 = shl(UInt<5>(0h19), 3) node _T_3249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3248) node _T_3250 = bits(_T_3249, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3250 node _T_3251 = eq(UInt<4>(0h9), idx_25) when _T_3251 : node _T_3252 = shl(UInt<5>(0h19), 3) node _T_3253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3252) node _T_3254 = bits(_T_3253, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3254 node _T_3255 = eq(UInt<4>(0ha), idx_25) when _T_3255 : node _T_3256 = shl(UInt<5>(0h19), 3) node _T_3257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3256) node _T_3258 = bits(_T_3257, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3258 node _T_3259 = eq(UInt<4>(0hb), idx_25) when _T_3259 : node _T_3260 = shl(UInt<5>(0h19), 3) node _T_3261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3260) node _T_3262 = bits(_T_3261, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3262 node _T_3263 = eq(UInt<4>(0hc), idx_25) when _T_3263 : node _T_3264 = shl(UInt<5>(0h19), 3) node _T_3265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3264) node _T_3266 = bits(_T_3265, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3266 node _T_3267 = eq(UInt<4>(0hd), idx_25) when _T_3267 : node _T_3268 = shl(UInt<5>(0h19), 3) node _T_3269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3268) node _T_3270 = bits(_T_3269, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3270 node _T_3271 = eq(UInt<4>(0he), idx_25) when _T_3271 : node _T_3272 = shl(UInt<5>(0h19), 3) node _T_3273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3272) node _T_3274 = bits(_T_3273, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3274 node _T_3275 = eq(UInt<4>(0hf), idx_25) when _T_3275 : node _T_3276 = shl(UInt<5>(0h19), 3) node _T_3277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3276) node _T_3278 = bits(_T_3277, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3278 node _T_3279 = eq(UInt<5>(0h10), idx_25) when _T_3279 : node _T_3280 = shl(UInt<5>(0h19), 3) node _T_3281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3280) node _T_3282 = bits(_T_3281, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3282 node _T_3283 = eq(UInt<5>(0h11), idx_25) when _T_3283 : node _T_3284 = shl(UInt<5>(0h19), 3) node _T_3285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3284) node _T_3286 = bits(_T_3285, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3286 node _T_3287 = eq(UInt<5>(0h12), idx_25) when _T_3287 : node _T_3288 = shl(UInt<5>(0h19), 3) node _T_3289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3288) node _T_3290 = bits(_T_3289, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3290 node _T_3291 = eq(UInt<5>(0h13), idx_25) when _T_3291 : node _T_3292 = shl(UInt<5>(0h19), 3) node _T_3293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3292) node _T_3294 = bits(_T_3293, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3294 node _T_3295 = eq(UInt<5>(0h14), idx_25) when _T_3295 : node _T_3296 = shl(UInt<5>(0h19), 3) node _T_3297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3296) node _T_3298 = bits(_T_3297, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3298 node _T_3299 = eq(UInt<5>(0h15), idx_25) when _T_3299 : node _T_3300 = shl(UInt<5>(0h19), 3) node _T_3301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3300) node _T_3302 = bits(_T_3301, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3302 node _T_3303 = eq(UInt<5>(0h16), idx_25) when _T_3303 : node _T_3304 = shl(UInt<5>(0h19), 3) node _T_3305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3304) node _T_3306 = bits(_T_3305, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3306 node _T_3307 = eq(UInt<5>(0h17), idx_25) when _T_3307 : node _T_3308 = shl(UInt<5>(0h19), 3) node _T_3309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3308) node _T_3310 = bits(_T_3309, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3310 node _T_3311 = eq(UInt<5>(0h18), idx_25) when _T_3311 : node _T_3312 = shl(UInt<5>(0h19), 3) node _T_3313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3312) node _T_3314 = bits(_T_3313, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3314 node _T_3315 = eq(UInt<5>(0h19), idx_25) when _T_3315 : node _T_3316 = shl(UInt<5>(0h19), 3) node _T_3317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3316) node _T_3318 = bits(_T_3317, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3318 node _T_3319 = eq(UInt<5>(0h1a), idx_25) when _T_3319 : node _T_3320 = shl(UInt<5>(0h19), 3) node _T_3321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3320) node _T_3322 = bits(_T_3321, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3322 node _T_3323 = eq(UInt<5>(0h1b), idx_25) when _T_3323 : node _T_3324 = shl(UInt<5>(0h19), 3) node _T_3325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3324) node _T_3326 = bits(_T_3325, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3326 node _T_3327 = eq(UInt<5>(0h1c), idx_25) when _T_3327 : node _T_3328 = shl(UInt<5>(0h19), 3) node _T_3329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3328) node _T_3330 = bits(_T_3329, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3330 node _T_3331 = eq(UInt<5>(0h1d), idx_25) when _T_3331 : node _T_3332 = shl(UInt<5>(0h19), 3) node _T_3333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3332) node _T_3334 = bits(_T_3333, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3334 node _T_3335 = eq(UInt<5>(0h1e), idx_25) when _T_3335 : node _T_3336 = shl(UInt<5>(0h19), 3) node _T_3337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3336) node _T_3338 = bits(_T_3337, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3338 node _T_3339 = eq(UInt<5>(0h1f), idx_25) when _T_3339 : node _T_3340 = shl(UInt<5>(0h19), 3) node _T_3341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3340) node _T_3342 = bits(_T_3341, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3342 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_3343 = eq(UInt<1>(0h0), idx_26) when _T_3343 : node _T_3344 = shl(UInt<5>(0h1a), 3) node _T_3345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3344) node _T_3346 = bits(_T_3345, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3346 node _T_3347 = eq(UInt<1>(0h1), idx_26) when _T_3347 : node _T_3348 = shl(UInt<5>(0h1a), 3) node _T_3349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3348) node _T_3350 = bits(_T_3349, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3350 node _T_3351 = eq(UInt<2>(0h2), idx_26) when _T_3351 : node _T_3352 = shl(UInt<5>(0h1a), 3) node _T_3353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3352) node _T_3354 = bits(_T_3353, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3354 node _T_3355 = eq(UInt<2>(0h3), idx_26) when _T_3355 : node _T_3356 = shl(UInt<5>(0h1a), 3) node _T_3357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3356) node _T_3358 = bits(_T_3357, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3358 node _T_3359 = eq(UInt<3>(0h4), idx_26) when _T_3359 : node _T_3360 = shl(UInt<5>(0h1a), 3) node _T_3361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3360) node _T_3362 = bits(_T_3361, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3362 node _T_3363 = eq(UInt<3>(0h5), idx_26) when _T_3363 : node _T_3364 = shl(UInt<5>(0h1a), 3) node _T_3365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3364) node _T_3366 = bits(_T_3365, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3366 node _T_3367 = eq(UInt<3>(0h6), idx_26) when _T_3367 : node _T_3368 = shl(UInt<5>(0h1a), 3) node _T_3369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3368) node _T_3370 = bits(_T_3369, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3370 node _T_3371 = eq(UInt<3>(0h7), idx_26) when _T_3371 : node _T_3372 = shl(UInt<5>(0h1a), 3) node _T_3373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3372) node _T_3374 = bits(_T_3373, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3374 node _T_3375 = eq(UInt<4>(0h8), idx_26) when _T_3375 : node _T_3376 = shl(UInt<5>(0h1a), 3) node _T_3377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3376) node _T_3378 = bits(_T_3377, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3378 node _T_3379 = eq(UInt<4>(0h9), idx_26) when _T_3379 : node _T_3380 = shl(UInt<5>(0h1a), 3) node _T_3381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3380) node _T_3382 = bits(_T_3381, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3382 node _T_3383 = eq(UInt<4>(0ha), idx_26) when _T_3383 : node _T_3384 = shl(UInt<5>(0h1a), 3) node _T_3385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3384) node _T_3386 = bits(_T_3385, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3386 node _T_3387 = eq(UInt<4>(0hb), idx_26) when _T_3387 : node _T_3388 = shl(UInt<5>(0h1a), 3) node _T_3389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3388) node _T_3390 = bits(_T_3389, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3390 node _T_3391 = eq(UInt<4>(0hc), idx_26) when _T_3391 : node _T_3392 = shl(UInt<5>(0h1a), 3) node _T_3393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3392) node _T_3394 = bits(_T_3393, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3394 node _T_3395 = eq(UInt<4>(0hd), idx_26) when _T_3395 : node _T_3396 = shl(UInt<5>(0h1a), 3) node _T_3397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3396) node _T_3398 = bits(_T_3397, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3398 node _T_3399 = eq(UInt<4>(0he), idx_26) when _T_3399 : node _T_3400 = shl(UInt<5>(0h1a), 3) node _T_3401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3400) node _T_3402 = bits(_T_3401, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3402 node _T_3403 = eq(UInt<4>(0hf), idx_26) when _T_3403 : node _T_3404 = shl(UInt<5>(0h1a), 3) node _T_3405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3404) node _T_3406 = bits(_T_3405, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3406 node _T_3407 = eq(UInt<5>(0h10), idx_26) when _T_3407 : node _T_3408 = shl(UInt<5>(0h1a), 3) node _T_3409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3408) node _T_3410 = bits(_T_3409, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3410 node _T_3411 = eq(UInt<5>(0h11), idx_26) when _T_3411 : node _T_3412 = shl(UInt<5>(0h1a), 3) node _T_3413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3412) node _T_3414 = bits(_T_3413, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3414 node _T_3415 = eq(UInt<5>(0h12), idx_26) when _T_3415 : node _T_3416 = shl(UInt<5>(0h1a), 3) node _T_3417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3416) node _T_3418 = bits(_T_3417, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3418 node _T_3419 = eq(UInt<5>(0h13), idx_26) when _T_3419 : node _T_3420 = shl(UInt<5>(0h1a), 3) node _T_3421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3420) node _T_3422 = bits(_T_3421, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3422 node _T_3423 = eq(UInt<5>(0h14), idx_26) when _T_3423 : node _T_3424 = shl(UInt<5>(0h1a), 3) node _T_3425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3424) node _T_3426 = bits(_T_3425, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3426 node _T_3427 = eq(UInt<5>(0h15), idx_26) when _T_3427 : node _T_3428 = shl(UInt<5>(0h1a), 3) node _T_3429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3428) node _T_3430 = bits(_T_3429, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3430 node _T_3431 = eq(UInt<5>(0h16), idx_26) when _T_3431 : node _T_3432 = shl(UInt<5>(0h1a), 3) node _T_3433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3432) node _T_3434 = bits(_T_3433, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3434 node _T_3435 = eq(UInt<5>(0h17), idx_26) when _T_3435 : node _T_3436 = shl(UInt<5>(0h1a), 3) node _T_3437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3436) node _T_3438 = bits(_T_3437, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3438 node _T_3439 = eq(UInt<5>(0h18), idx_26) when _T_3439 : node _T_3440 = shl(UInt<5>(0h1a), 3) node _T_3441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3440) node _T_3442 = bits(_T_3441, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3442 node _T_3443 = eq(UInt<5>(0h19), idx_26) when _T_3443 : node _T_3444 = shl(UInt<5>(0h1a), 3) node _T_3445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3444) node _T_3446 = bits(_T_3445, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3446 node _T_3447 = eq(UInt<5>(0h1a), idx_26) when _T_3447 : node _T_3448 = shl(UInt<5>(0h1a), 3) node _T_3449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3448) node _T_3450 = bits(_T_3449, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3450 node _T_3451 = eq(UInt<5>(0h1b), idx_26) when _T_3451 : node _T_3452 = shl(UInt<5>(0h1a), 3) node _T_3453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3452) node _T_3454 = bits(_T_3453, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3454 node _T_3455 = eq(UInt<5>(0h1c), idx_26) when _T_3455 : node _T_3456 = shl(UInt<5>(0h1a), 3) node _T_3457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3456) node _T_3458 = bits(_T_3457, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3458 node _T_3459 = eq(UInt<5>(0h1d), idx_26) when _T_3459 : node _T_3460 = shl(UInt<5>(0h1a), 3) node _T_3461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3460) node _T_3462 = bits(_T_3461, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3462 node _T_3463 = eq(UInt<5>(0h1e), idx_26) when _T_3463 : node _T_3464 = shl(UInt<5>(0h1a), 3) node _T_3465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3464) node _T_3466 = bits(_T_3465, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3466 node _T_3467 = eq(UInt<5>(0h1f), idx_26) when _T_3467 : node _T_3468 = shl(UInt<5>(0h1a), 3) node _T_3469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3468) node _T_3470 = bits(_T_3469, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3470 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_3471 = eq(UInt<1>(0h0), idx_27) when _T_3471 : node _T_3472 = shl(UInt<5>(0h1b), 3) node _T_3473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3472) node _T_3474 = bits(_T_3473, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3474 node _T_3475 = eq(UInt<1>(0h1), idx_27) when _T_3475 : node _T_3476 = shl(UInt<5>(0h1b), 3) node _T_3477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3476) node _T_3478 = bits(_T_3477, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3478 node _T_3479 = eq(UInt<2>(0h2), idx_27) when _T_3479 : node _T_3480 = shl(UInt<5>(0h1b), 3) node _T_3481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3480) node _T_3482 = bits(_T_3481, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3482 node _T_3483 = eq(UInt<2>(0h3), idx_27) when _T_3483 : node _T_3484 = shl(UInt<5>(0h1b), 3) node _T_3485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3484) node _T_3486 = bits(_T_3485, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3486 node _T_3487 = eq(UInt<3>(0h4), idx_27) when _T_3487 : node _T_3488 = shl(UInt<5>(0h1b), 3) node _T_3489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3488) node _T_3490 = bits(_T_3489, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3490 node _T_3491 = eq(UInt<3>(0h5), idx_27) when _T_3491 : node _T_3492 = shl(UInt<5>(0h1b), 3) node _T_3493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3492) node _T_3494 = bits(_T_3493, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3494 node _T_3495 = eq(UInt<3>(0h6), idx_27) when _T_3495 : node _T_3496 = shl(UInt<5>(0h1b), 3) node _T_3497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3496) node _T_3498 = bits(_T_3497, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3498 node _T_3499 = eq(UInt<3>(0h7), idx_27) when _T_3499 : node _T_3500 = shl(UInt<5>(0h1b), 3) node _T_3501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3500) node _T_3502 = bits(_T_3501, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3502 node _T_3503 = eq(UInt<4>(0h8), idx_27) when _T_3503 : node _T_3504 = shl(UInt<5>(0h1b), 3) node _T_3505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3504) node _T_3506 = bits(_T_3505, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3506 node _T_3507 = eq(UInt<4>(0h9), idx_27) when _T_3507 : node _T_3508 = shl(UInt<5>(0h1b), 3) node _T_3509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3508) node _T_3510 = bits(_T_3509, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3510 node _T_3511 = eq(UInt<4>(0ha), idx_27) when _T_3511 : node _T_3512 = shl(UInt<5>(0h1b), 3) node _T_3513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3512) node _T_3514 = bits(_T_3513, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3514 node _T_3515 = eq(UInt<4>(0hb), idx_27) when _T_3515 : node _T_3516 = shl(UInt<5>(0h1b), 3) node _T_3517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3516) node _T_3518 = bits(_T_3517, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3518 node _T_3519 = eq(UInt<4>(0hc), idx_27) when _T_3519 : node _T_3520 = shl(UInt<5>(0h1b), 3) node _T_3521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3520) node _T_3522 = bits(_T_3521, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3522 node _T_3523 = eq(UInt<4>(0hd), idx_27) when _T_3523 : node _T_3524 = shl(UInt<5>(0h1b), 3) node _T_3525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3524) node _T_3526 = bits(_T_3525, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3526 node _T_3527 = eq(UInt<4>(0he), idx_27) when _T_3527 : node _T_3528 = shl(UInt<5>(0h1b), 3) node _T_3529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3528) node _T_3530 = bits(_T_3529, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3530 node _T_3531 = eq(UInt<4>(0hf), idx_27) when _T_3531 : node _T_3532 = shl(UInt<5>(0h1b), 3) node _T_3533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3532) node _T_3534 = bits(_T_3533, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3534 node _T_3535 = eq(UInt<5>(0h10), idx_27) when _T_3535 : node _T_3536 = shl(UInt<5>(0h1b), 3) node _T_3537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3536) node _T_3538 = bits(_T_3537, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3538 node _T_3539 = eq(UInt<5>(0h11), idx_27) when _T_3539 : node _T_3540 = shl(UInt<5>(0h1b), 3) node _T_3541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3540) node _T_3542 = bits(_T_3541, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3542 node _T_3543 = eq(UInt<5>(0h12), idx_27) when _T_3543 : node _T_3544 = shl(UInt<5>(0h1b), 3) node _T_3545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3544) node _T_3546 = bits(_T_3545, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3546 node _T_3547 = eq(UInt<5>(0h13), idx_27) when _T_3547 : node _T_3548 = shl(UInt<5>(0h1b), 3) node _T_3549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3548) node _T_3550 = bits(_T_3549, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3550 node _T_3551 = eq(UInt<5>(0h14), idx_27) when _T_3551 : node _T_3552 = shl(UInt<5>(0h1b), 3) node _T_3553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3552) node _T_3554 = bits(_T_3553, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3554 node _T_3555 = eq(UInt<5>(0h15), idx_27) when _T_3555 : node _T_3556 = shl(UInt<5>(0h1b), 3) node _T_3557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3556) node _T_3558 = bits(_T_3557, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3558 node _T_3559 = eq(UInt<5>(0h16), idx_27) when _T_3559 : node _T_3560 = shl(UInt<5>(0h1b), 3) node _T_3561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3560) node _T_3562 = bits(_T_3561, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3562 node _T_3563 = eq(UInt<5>(0h17), idx_27) when _T_3563 : node _T_3564 = shl(UInt<5>(0h1b), 3) node _T_3565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3564) node _T_3566 = bits(_T_3565, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3566 node _T_3567 = eq(UInt<5>(0h18), idx_27) when _T_3567 : node _T_3568 = shl(UInt<5>(0h1b), 3) node _T_3569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3568) node _T_3570 = bits(_T_3569, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3570 node _T_3571 = eq(UInt<5>(0h19), idx_27) when _T_3571 : node _T_3572 = shl(UInt<5>(0h1b), 3) node _T_3573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3572) node _T_3574 = bits(_T_3573, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3574 node _T_3575 = eq(UInt<5>(0h1a), idx_27) when _T_3575 : node _T_3576 = shl(UInt<5>(0h1b), 3) node _T_3577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3576) node _T_3578 = bits(_T_3577, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3578 node _T_3579 = eq(UInt<5>(0h1b), idx_27) when _T_3579 : node _T_3580 = shl(UInt<5>(0h1b), 3) node _T_3581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3580) node _T_3582 = bits(_T_3581, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3582 node _T_3583 = eq(UInt<5>(0h1c), idx_27) when _T_3583 : node _T_3584 = shl(UInt<5>(0h1b), 3) node _T_3585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3584) node _T_3586 = bits(_T_3585, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3586 node _T_3587 = eq(UInt<5>(0h1d), idx_27) when _T_3587 : node _T_3588 = shl(UInt<5>(0h1b), 3) node _T_3589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3588) node _T_3590 = bits(_T_3589, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3590 node _T_3591 = eq(UInt<5>(0h1e), idx_27) when _T_3591 : node _T_3592 = shl(UInt<5>(0h1b), 3) node _T_3593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3592) node _T_3594 = bits(_T_3593, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3594 node _T_3595 = eq(UInt<5>(0h1f), idx_27) when _T_3595 : node _T_3596 = shl(UInt<5>(0h1b), 3) node _T_3597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3596) node _T_3598 = bits(_T_3597, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3598 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_3599 = eq(UInt<1>(0h0), idx_28) when _T_3599 : node _T_3600 = shl(UInt<5>(0h1c), 3) node _T_3601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3600) node _T_3602 = bits(_T_3601, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3602 node _T_3603 = eq(UInt<1>(0h1), idx_28) when _T_3603 : node _T_3604 = shl(UInt<5>(0h1c), 3) node _T_3605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3604) node _T_3606 = bits(_T_3605, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3606 node _T_3607 = eq(UInt<2>(0h2), idx_28) when _T_3607 : node _T_3608 = shl(UInt<5>(0h1c), 3) node _T_3609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3608) node _T_3610 = bits(_T_3609, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3610 node _T_3611 = eq(UInt<2>(0h3), idx_28) when _T_3611 : node _T_3612 = shl(UInt<5>(0h1c), 3) node _T_3613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3612) node _T_3614 = bits(_T_3613, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3614 node _T_3615 = eq(UInt<3>(0h4), idx_28) when _T_3615 : node _T_3616 = shl(UInt<5>(0h1c), 3) node _T_3617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3616) node _T_3618 = bits(_T_3617, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3618 node _T_3619 = eq(UInt<3>(0h5), idx_28) when _T_3619 : node _T_3620 = shl(UInt<5>(0h1c), 3) node _T_3621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3620) node _T_3622 = bits(_T_3621, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3622 node _T_3623 = eq(UInt<3>(0h6), idx_28) when _T_3623 : node _T_3624 = shl(UInt<5>(0h1c), 3) node _T_3625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3624) node _T_3626 = bits(_T_3625, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3626 node _T_3627 = eq(UInt<3>(0h7), idx_28) when _T_3627 : node _T_3628 = shl(UInt<5>(0h1c), 3) node _T_3629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3628) node _T_3630 = bits(_T_3629, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3630 node _T_3631 = eq(UInt<4>(0h8), idx_28) when _T_3631 : node _T_3632 = shl(UInt<5>(0h1c), 3) node _T_3633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3632) node _T_3634 = bits(_T_3633, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3634 node _T_3635 = eq(UInt<4>(0h9), idx_28) when _T_3635 : node _T_3636 = shl(UInt<5>(0h1c), 3) node _T_3637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3636) node _T_3638 = bits(_T_3637, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3638 node _T_3639 = eq(UInt<4>(0ha), idx_28) when _T_3639 : node _T_3640 = shl(UInt<5>(0h1c), 3) node _T_3641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3640) node _T_3642 = bits(_T_3641, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3642 node _T_3643 = eq(UInt<4>(0hb), idx_28) when _T_3643 : node _T_3644 = shl(UInt<5>(0h1c), 3) node _T_3645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3644) node _T_3646 = bits(_T_3645, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3646 node _T_3647 = eq(UInt<4>(0hc), idx_28) when _T_3647 : node _T_3648 = shl(UInt<5>(0h1c), 3) node _T_3649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3648) node _T_3650 = bits(_T_3649, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3650 node _T_3651 = eq(UInt<4>(0hd), idx_28) when _T_3651 : node _T_3652 = shl(UInt<5>(0h1c), 3) node _T_3653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3652) node _T_3654 = bits(_T_3653, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3654 node _T_3655 = eq(UInt<4>(0he), idx_28) when _T_3655 : node _T_3656 = shl(UInt<5>(0h1c), 3) node _T_3657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3656) node _T_3658 = bits(_T_3657, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3658 node _T_3659 = eq(UInt<4>(0hf), idx_28) when _T_3659 : node _T_3660 = shl(UInt<5>(0h1c), 3) node _T_3661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3660) node _T_3662 = bits(_T_3661, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3662 node _T_3663 = eq(UInt<5>(0h10), idx_28) when _T_3663 : node _T_3664 = shl(UInt<5>(0h1c), 3) node _T_3665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3664) node _T_3666 = bits(_T_3665, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3666 node _T_3667 = eq(UInt<5>(0h11), idx_28) when _T_3667 : node _T_3668 = shl(UInt<5>(0h1c), 3) node _T_3669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3668) node _T_3670 = bits(_T_3669, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3670 node _T_3671 = eq(UInt<5>(0h12), idx_28) when _T_3671 : node _T_3672 = shl(UInt<5>(0h1c), 3) node _T_3673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3672) node _T_3674 = bits(_T_3673, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3674 node _T_3675 = eq(UInt<5>(0h13), idx_28) when _T_3675 : node _T_3676 = shl(UInt<5>(0h1c), 3) node _T_3677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3676) node _T_3678 = bits(_T_3677, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3678 node _T_3679 = eq(UInt<5>(0h14), idx_28) when _T_3679 : node _T_3680 = shl(UInt<5>(0h1c), 3) node _T_3681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3680) node _T_3682 = bits(_T_3681, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3682 node _T_3683 = eq(UInt<5>(0h15), idx_28) when _T_3683 : node _T_3684 = shl(UInt<5>(0h1c), 3) node _T_3685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3684) node _T_3686 = bits(_T_3685, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3686 node _T_3687 = eq(UInt<5>(0h16), idx_28) when _T_3687 : node _T_3688 = shl(UInt<5>(0h1c), 3) node _T_3689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3688) node _T_3690 = bits(_T_3689, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3690 node _T_3691 = eq(UInt<5>(0h17), idx_28) when _T_3691 : node _T_3692 = shl(UInt<5>(0h1c), 3) node _T_3693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3692) node _T_3694 = bits(_T_3693, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3694 node _T_3695 = eq(UInt<5>(0h18), idx_28) when _T_3695 : node _T_3696 = shl(UInt<5>(0h1c), 3) node _T_3697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3696) node _T_3698 = bits(_T_3697, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3698 node _T_3699 = eq(UInt<5>(0h19), idx_28) when _T_3699 : node _T_3700 = shl(UInt<5>(0h1c), 3) node _T_3701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3700) node _T_3702 = bits(_T_3701, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3702 node _T_3703 = eq(UInt<5>(0h1a), idx_28) when _T_3703 : node _T_3704 = shl(UInt<5>(0h1c), 3) node _T_3705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3704) node _T_3706 = bits(_T_3705, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3706 node _T_3707 = eq(UInt<5>(0h1b), idx_28) when _T_3707 : node _T_3708 = shl(UInt<5>(0h1c), 3) node _T_3709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3708) node _T_3710 = bits(_T_3709, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3710 node _T_3711 = eq(UInt<5>(0h1c), idx_28) when _T_3711 : node _T_3712 = shl(UInt<5>(0h1c), 3) node _T_3713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3712) node _T_3714 = bits(_T_3713, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3714 node _T_3715 = eq(UInt<5>(0h1d), idx_28) when _T_3715 : node _T_3716 = shl(UInt<5>(0h1c), 3) node _T_3717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3716) node _T_3718 = bits(_T_3717, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3718 node _T_3719 = eq(UInt<5>(0h1e), idx_28) when _T_3719 : node _T_3720 = shl(UInt<5>(0h1c), 3) node _T_3721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3720) node _T_3722 = bits(_T_3721, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3722 node _T_3723 = eq(UInt<5>(0h1f), idx_28) when _T_3723 : node _T_3724 = shl(UInt<5>(0h1c), 3) node _T_3725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3724) node _T_3726 = bits(_T_3725, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3726 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_3727 = eq(UInt<1>(0h0), idx_29) when _T_3727 : node _T_3728 = shl(UInt<5>(0h1d), 3) node _T_3729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3728) node _T_3730 = bits(_T_3729, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3730 node _T_3731 = eq(UInt<1>(0h1), idx_29) when _T_3731 : node _T_3732 = shl(UInt<5>(0h1d), 3) node _T_3733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3732) node _T_3734 = bits(_T_3733, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3734 node _T_3735 = eq(UInt<2>(0h2), idx_29) when _T_3735 : node _T_3736 = shl(UInt<5>(0h1d), 3) node _T_3737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3736) node _T_3738 = bits(_T_3737, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3738 node _T_3739 = eq(UInt<2>(0h3), idx_29) when _T_3739 : node _T_3740 = shl(UInt<5>(0h1d), 3) node _T_3741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3740) node _T_3742 = bits(_T_3741, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3742 node _T_3743 = eq(UInt<3>(0h4), idx_29) when _T_3743 : node _T_3744 = shl(UInt<5>(0h1d), 3) node _T_3745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3744) node _T_3746 = bits(_T_3745, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3746 node _T_3747 = eq(UInt<3>(0h5), idx_29) when _T_3747 : node _T_3748 = shl(UInt<5>(0h1d), 3) node _T_3749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3748) node _T_3750 = bits(_T_3749, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3750 node _T_3751 = eq(UInt<3>(0h6), idx_29) when _T_3751 : node _T_3752 = shl(UInt<5>(0h1d), 3) node _T_3753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3752) node _T_3754 = bits(_T_3753, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3754 node _T_3755 = eq(UInt<3>(0h7), idx_29) when _T_3755 : node _T_3756 = shl(UInt<5>(0h1d), 3) node _T_3757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3756) node _T_3758 = bits(_T_3757, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3758 node _T_3759 = eq(UInt<4>(0h8), idx_29) when _T_3759 : node _T_3760 = shl(UInt<5>(0h1d), 3) node _T_3761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3760) node _T_3762 = bits(_T_3761, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3762 node _T_3763 = eq(UInt<4>(0h9), idx_29) when _T_3763 : node _T_3764 = shl(UInt<5>(0h1d), 3) node _T_3765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3764) node _T_3766 = bits(_T_3765, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3766 node _T_3767 = eq(UInt<4>(0ha), idx_29) when _T_3767 : node _T_3768 = shl(UInt<5>(0h1d), 3) node _T_3769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3768) node _T_3770 = bits(_T_3769, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3770 node _T_3771 = eq(UInt<4>(0hb), idx_29) when _T_3771 : node _T_3772 = shl(UInt<5>(0h1d), 3) node _T_3773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3772) node _T_3774 = bits(_T_3773, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3774 node _T_3775 = eq(UInt<4>(0hc), idx_29) when _T_3775 : node _T_3776 = shl(UInt<5>(0h1d), 3) node _T_3777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3776) node _T_3778 = bits(_T_3777, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3778 node _T_3779 = eq(UInt<4>(0hd), idx_29) when _T_3779 : node _T_3780 = shl(UInt<5>(0h1d), 3) node _T_3781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3780) node _T_3782 = bits(_T_3781, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3782 node _T_3783 = eq(UInt<4>(0he), idx_29) when _T_3783 : node _T_3784 = shl(UInt<5>(0h1d), 3) node _T_3785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3784) node _T_3786 = bits(_T_3785, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3786 node _T_3787 = eq(UInt<4>(0hf), idx_29) when _T_3787 : node _T_3788 = shl(UInt<5>(0h1d), 3) node _T_3789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3788) node _T_3790 = bits(_T_3789, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3790 node _T_3791 = eq(UInt<5>(0h10), idx_29) when _T_3791 : node _T_3792 = shl(UInt<5>(0h1d), 3) node _T_3793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3792) node _T_3794 = bits(_T_3793, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3794 node _T_3795 = eq(UInt<5>(0h11), idx_29) when _T_3795 : node _T_3796 = shl(UInt<5>(0h1d), 3) node _T_3797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3796) node _T_3798 = bits(_T_3797, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3798 node _T_3799 = eq(UInt<5>(0h12), idx_29) when _T_3799 : node _T_3800 = shl(UInt<5>(0h1d), 3) node _T_3801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3800) node _T_3802 = bits(_T_3801, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3802 node _T_3803 = eq(UInt<5>(0h13), idx_29) when _T_3803 : node _T_3804 = shl(UInt<5>(0h1d), 3) node _T_3805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3804) node _T_3806 = bits(_T_3805, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3806 node _T_3807 = eq(UInt<5>(0h14), idx_29) when _T_3807 : node _T_3808 = shl(UInt<5>(0h1d), 3) node _T_3809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3808) node _T_3810 = bits(_T_3809, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3810 node _T_3811 = eq(UInt<5>(0h15), idx_29) when _T_3811 : node _T_3812 = shl(UInt<5>(0h1d), 3) node _T_3813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3812) node _T_3814 = bits(_T_3813, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3814 node _T_3815 = eq(UInt<5>(0h16), idx_29) when _T_3815 : node _T_3816 = shl(UInt<5>(0h1d), 3) node _T_3817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3816) node _T_3818 = bits(_T_3817, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3818 node _T_3819 = eq(UInt<5>(0h17), idx_29) when _T_3819 : node _T_3820 = shl(UInt<5>(0h1d), 3) node _T_3821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3820) node _T_3822 = bits(_T_3821, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3822 node _T_3823 = eq(UInt<5>(0h18), idx_29) when _T_3823 : node _T_3824 = shl(UInt<5>(0h1d), 3) node _T_3825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3824) node _T_3826 = bits(_T_3825, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3826 node _T_3827 = eq(UInt<5>(0h19), idx_29) when _T_3827 : node _T_3828 = shl(UInt<5>(0h1d), 3) node _T_3829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3828) node _T_3830 = bits(_T_3829, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3830 node _T_3831 = eq(UInt<5>(0h1a), idx_29) when _T_3831 : node _T_3832 = shl(UInt<5>(0h1d), 3) node _T_3833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3832) node _T_3834 = bits(_T_3833, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3834 node _T_3835 = eq(UInt<5>(0h1b), idx_29) when _T_3835 : node _T_3836 = shl(UInt<5>(0h1d), 3) node _T_3837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3836) node _T_3838 = bits(_T_3837, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3838 node _T_3839 = eq(UInt<5>(0h1c), idx_29) when _T_3839 : node _T_3840 = shl(UInt<5>(0h1d), 3) node _T_3841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3840) node _T_3842 = bits(_T_3841, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3842 node _T_3843 = eq(UInt<5>(0h1d), idx_29) when _T_3843 : node _T_3844 = shl(UInt<5>(0h1d), 3) node _T_3845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3844) node _T_3846 = bits(_T_3845, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3846 node _T_3847 = eq(UInt<5>(0h1e), idx_29) when _T_3847 : node _T_3848 = shl(UInt<5>(0h1d), 3) node _T_3849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3848) node _T_3850 = bits(_T_3849, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3850 node _T_3851 = eq(UInt<5>(0h1f), idx_29) when _T_3851 : node _T_3852 = shl(UInt<5>(0h1d), 3) node _T_3853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3852) node _T_3854 = bits(_T_3853, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3854 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_3855 = eq(UInt<1>(0h0), idx_30) when _T_3855 : node _T_3856 = shl(UInt<5>(0h1e), 3) node _T_3857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3856) node _T_3858 = bits(_T_3857, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3858 node _T_3859 = eq(UInt<1>(0h1), idx_30) when _T_3859 : node _T_3860 = shl(UInt<5>(0h1e), 3) node _T_3861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3860) node _T_3862 = bits(_T_3861, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3862 node _T_3863 = eq(UInt<2>(0h2), idx_30) when _T_3863 : node _T_3864 = shl(UInt<5>(0h1e), 3) node _T_3865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3864) node _T_3866 = bits(_T_3865, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3866 node _T_3867 = eq(UInt<2>(0h3), idx_30) when _T_3867 : node _T_3868 = shl(UInt<5>(0h1e), 3) node _T_3869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3868) node _T_3870 = bits(_T_3869, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3870 node _T_3871 = eq(UInt<3>(0h4), idx_30) when _T_3871 : node _T_3872 = shl(UInt<5>(0h1e), 3) node _T_3873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3872) node _T_3874 = bits(_T_3873, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_3874 node _T_3875 = eq(UInt<3>(0h5), idx_30) when _T_3875 : node _T_3876 = shl(UInt<5>(0h1e), 3) node _T_3877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3876) node _T_3878 = bits(_T_3877, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_3878 node _T_3879 = eq(UInt<3>(0h6), idx_30) when _T_3879 : node _T_3880 = shl(UInt<5>(0h1e), 3) node _T_3881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3880) node _T_3882 = bits(_T_3881, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_3882 node _T_3883 = eq(UInt<3>(0h7), idx_30) when _T_3883 : node _T_3884 = shl(UInt<5>(0h1e), 3) node _T_3885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3884) node _T_3886 = bits(_T_3885, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_3886 node _T_3887 = eq(UInt<4>(0h8), idx_30) when _T_3887 : node _T_3888 = shl(UInt<5>(0h1e), 3) node _T_3889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3888) node _T_3890 = bits(_T_3889, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_3890 node _T_3891 = eq(UInt<4>(0h9), idx_30) when _T_3891 : node _T_3892 = shl(UInt<5>(0h1e), 3) node _T_3893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3892) node _T_3894 = bits(_T_3893, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_3894 node _T_3895 = eq(UInt<4>(0ha), idx_30) when _T_3895 : node _T_3896 = shl(UInt<5>(0h1e), 3) node _T_3897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3896) node _T_3898 = bits(_T_3897, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_3898 node _T_3899 = eq(UInt<4>(0hb), idx_30) when _T_3899 : node _T_3900 = shl(UInt<5>(0h1e), 3) node _T_3901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3900) node _T_3902 = bits(_T_3901, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_3902 node _T_3903 = eq(UInt<4>(0hc), idx_30) when _T_3903 : node _T_3904 = shl(UInt<5>(0h1e), 3) node _T_3905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3904) node _T_3906 = bits(_T_3905, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_3906 node _T_3907 = eq(UInt<4>(0hd), idx_30) when _T_3907 : node _T_3908 = shl(UInt<5>(0h1e), 3) node _T_3909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3908) node _T_3910 = bits(_T_3909, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_3910 node _T_3911 = eq(UInt<4>(0he), idx_30) when _T_3911 : node _T_3912 = shl(UInt<5>(0h1e), 3) node _T_3913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3912) node _T_3914 = bits(_T_3913, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_3914 node _T_3915 = eq(UInt<4>(0hf), idx_30) when _T_3915 : node _T_3916 = shl(UInt<5>(0h1e), 3) node _T_3917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3916) node _T_3918 = bits(_T_3917, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_3918 node _T_3919 = eq(UInt<5>(0h10), idx_30) when _T_3919 : node _T_3920 = shl(UInt<5>(0h1e), 3) node _T_3921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3920) node _T_3922 = bits(_T_3921, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_3922 node _T_3923 = eq(UInt<5>(0h11), idx_30) when _T_3923 : node _T_3924 = shl(UInt<5>(0h1e), 3) node _T_3925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3924) node _T_3926 = bits(_T_3925, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_3926 node _T_3927 = eq(UInt<5>(0h12), idx_30) when _T_3927 : node _T_3928 = shl(UInt<5>(0h1e), 3) node _T_3929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3928) node _T_3930 = bits(_T_3929, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_3930 node _T_3931 = eq(UInt<5>(0h13), idx_30) when _T_3931 : node _T_3932 = shl(UInt<5>(0h1e), 3) node _T_3933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3932) node _T_3934 = bits(_T_3933, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_3934 node _T_3935 = eq(UInt<5>(0h14), idx_30) when _T_3935 : node _T_3936 = shl(UInt<5>(0h1e), 3) node _T_3937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3936) node _T_3938 = bits(_T_3937, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_3938 node _T_3939 = eq(UInt<5>(0h15), idx_30) when _T_3939 : node _T_3940 = shl(UInt<5>(0h1e), 3) node _T_3941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3940) node _T_3942 = bits(_T_3941, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_3942 node _T_3943 = eq(UInt<5>(0h16), idx_30) when _T_3943 : node _T_3944 = shl(UInt<5>(0h1e), 3) node _T_3945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3944) node _T_3946 = bits(_T_3945, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_3946 node _T_3947 = eq(UInt<5>(0h17), idx_30) when _T_3947 : node _T_3948 = shl(UInt<5>(0h1e), 3) node _T_3949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3948) node _T_3950 = bits(_T_3949, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_3950 node _T_3951 = eq(UInt<5>(0h18), idx_30) when _T_3951 : node _T_3952 = shl(UInt<5>(0h1e), 3) node _T_3953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3952) node _T_3954 = bits(_T_3953, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_3954 node _T_3955 = eq(UInt<5>(0h19), idx_30) when _T_3955 : node _T_3956 = shl(UInt<5>(0h1e), 3) node _T_3957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3956) node _T_3958 = bits(_T_3957, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_3958 node _T_3959 = eq(UInt<5>(0h1a), idx_30) when _T_3959 : node _T_3960 = shl(UInt<5>(0h1e), 3) node _T_3961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3960) node _T_3962 = bits(_T_3961, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_3962 node _T_3963 = eq(UInt<5>(0h1b), idx_30) when _T_3963 : node _T_3964 = shl(UInt<5>(0h1e), 3) node _T_3965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3964) node _T_3966 = bits(_T_3965, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_3966 node _T_3967 = eq(UInt<5>(0h1c), idx_30) when _T_3967 : node _T_3968 = shl(UInt<5>(0h1e), 3) node _T_3969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3968) node _T_3970 = bits(_T_3969, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_3970 node _T_3971 = eq(UInt<5>(0h1d), idx_30) when _T_3971 : node _T_3972 = shl(UInt<5>(0h1e), 3) node _T_3973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3972) node _T_3974 = bits(_T_3973, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_3974 node _T_3975 = eq(UInt<5>(0h1e), idx_30) when _T_3975 : node _T_3976 = shl(UInt<5>(0h1e), 3) node _T_3977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3976) node _T_3978 = bits(_T_3977, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_3978 node _T_3979 = eq(UInt<5>(0h1f), idx_30) when _T_3979 : node _T_3980 = shl(UInt<5>(0h1e), 3) node _T_3981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3980) node _T_3982 = bits(_T_3981, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_3982 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_3983 = eq(UInt<1>(0h0), idx_31) when _T_3983 : node _T_3984 = shl(UInt<5>(0h1f), 3) node _T_3985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3984) node _T_3986 = bits(_T_3985, 7, 0) connect Queue2_UInt8.io.enq.bits, _T_3986 node _T_3987 = eq(UInt<1>(0h1), idx_31) when _T_3987 : node _T_3988 = shl(UInt<5>(0h1f), 3) node _T_3989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3988) node _T_3990 = bits(_T_3989, 7, 0) connect Queue2_UInt8_1.io.enq.bits, _T_3990 node _T_3991 = eq(UInt<2>(0h2), idx_31) when _T_3991 : node _T_3992 = shl(UInt<5>(0h1f), 3) node _T_3993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3992) node _T_3994 = bits(_T_3993, 7, 0) connect Queue2_UInt8_2.io.enq.bits, _T_3994 node _T_3995 = eq(UInt<2>(0h3), idx_31) when _T_3995 : node _T_3996 = shl(UInt<5>(0h1f), 3) node _T_3997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3996) node _T_3998 = bits(_T_3997, 7, 0) connect Queue2_UInt8_3.io.enq.bits, _T_3998 node _T_3999 = eq(UInt<3>(0h4), idx_31) when _T_3999 : node _T_4000 = shl(UInt<5>(0h1f), 3) node _T_4001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4000) node _T_4002 = bits(_T_4001, 7, 0) connect Queue2_UInt8_4.io.enq.bits, _T_4002 node _T_4003 = eq(UInt<3>(0h5), idx_31) when _T_4003 : node _T_4004 = shl(UInt<5>(0h1f), 3) node _T_4005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4004) node _T_4006 = bits(_T_4005, 7, 0) connect Queue2_UInt8_5.io.enq.bits, _T_4006 node _T_4007 = eq(UInt<3>(0h6), idx_31) when _T_4007 : node _T_4008 = shl(UInt<5>(0h1f), 3) node _T_4009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4008) node _T_4010 = bits(_T_4009, 7, 0) connect Queue2_UInt8_6.io.enq.bits, _T_4010 node _T_4011 = eq(UInt<3>(0h7), idx_31) when _T_4011 : node _T_4012 = shl(UInt<5>(0h1f), 3) node _T_4013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4012) node _T_4014 = bits(_T_4013, 7, 0) connect Queue2_UInt8_7.io.enq.bits, _T_4014 node _T_4015 = eq(UInt<4>(0h8), idx_31) when _T_4015 : node _T_4016 = shl(UInt<5>(0h1f), 3) node _T_4017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4016) node _T_4018 = bits(_T_4017, 7, 0) connect Queue2_UInt8_8.io.enq.bits, _T_4018 node _T_4019 = eq(UInt<4>(0h9), idx_31) when _T_4019 : node _T_4020 = shl(UInt<5>(0h1f), 3) node _T_4021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4020) node _T_4022 = bits(_T_4021, 7, 0) connect Queue2_UInt8_9.io.enq.bits, _T_4022 node _T_4023 = eq(UInt<4>(0ha), idx_31) when _T_4023 : node _T_4024 = shl(UInt<5>(0h1f), 3) node _T_4025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4024) node _T_4026 = bits(_T_4025, 7, 0) connect Queue2_UInt8_10.io.enq.bits, _T_4026 node _T_4027 = eq(UInt<4>(0hb), idx_31) when _T_4027 : node _T_4028 = shl(UInt<5>(0h1f), 3) node _T_4029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4028) node _T_4030 = bits(_T_4029, 7, 0) connect Queue2_UInt8_11.io.enq.bits, _T_4030 node _T_4031 = eq(UInt<4>(0hc), idx_31) when _T_4031 : node _T_4032 = shl(UInt<5>(0h1f), 3) node _T_4033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4032) node _T_4034 = bits(_T_4033, 7, 0) connect Queue2_UInt8_12.io.enq.bits, _T_4034 node _T_4035 = eq(UInt<4>(0hd), idx_31) when _T_4035 : node _T_4036 = shl(UInt<5>(0h1f), 3) node _T_4037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4036) node _T_4038 = bits(_T_4037, 7, 0) connect Queue2_UInt8_13.io.enq.bits, _T_4038 node _T_4039 = eq(UInt<4>(0he), idx_31) when _T_4039 : node _T_4040 = shl(UInt<5>(0h1f), 3) node _T_4041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4040) node _T_4042 = bits(_T_4041, 7, 0) connect Queue2_UInt8_14.io.enq.bits, _T_4042 node _T_4043 = eq(UInt<4>(0hf), idx_31) when _T_4043 : node _T_4044 = shl(UInt<5>(0h1f), 3) node _T_4045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4044) node _T_4046 = bits(_T_4045, 7, 0) connect Queue2_UInt8_15.io.enq.bits, _T_4046 node _T_4047 = eq(UInt<5>(0h10), idx_31) when _T_4047 : node _T_4048 = shl(UInt<5>(0h1f), 3) node _T_4049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4048) node _T_4050 = bits(_T_4049, 7, 0) connect Queue2_UInt8_16.io.enq.bits, _T_4050 node _T_4051 = eq(UInt<5>(0h11), idx_31) when _T_4051 : node _T_4052 = shl(UInt<5>(0h1f), 3) node _T_4053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4052) node _T_4054 = bits(_T_4053, 7, 0) connect Queue2_UInt8_17.io.enq.bits, _T_4054 node _T_4055 = eq(UInt<5>(0h12), idx_31) when _T_4055 : node _T_4056 = shl(UInt<5>(0h1f), 3) node _T_4057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4056) node _T_4058 = bits(_T_4057, 7, 0) connect Queue2_UInt8_18.io.enq.bits, _T_4058 node _T_4059 = eq(UInt<5>(0h13), idx_31) when _T_4059 : node _T_4060 = shl(UInt<5>(0h1f), 3) node _T_4061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4060) node _T_4062 = bits(_T_4061, 7, 0) connect Queue2_UInt8_19.io.enq.bits, _T_4062 node _T_4063 = eq(UInt<5>(0h14), idx_31) when _T_4063 : node _T_4064 = shl(UInt<5>(0h1f), 3) node _T_4065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4064) node _T_4066 = bits(_T_4065, 7, 0) connect Queue2_UInt8_20.io.enq.bits, _T_4066 node _T_4067 = eq(UInt<5>(0h15), idx_31) when _T_4067 : node _T_4068 = shl(UInt<5>(0h1f), 3) node _T_4069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4068) node _T_4070 = bits(_T_4069, 7, 0) connect Queue2_UInt8_21.io.enq.bits, _T_4070 node _T_4071 = eq(UInt<5>(0h16), idx_31) when _T_4071 : node _T_4072 = shl(UInt<5>(0h1f), 3) node _T_4073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4072) node _T_4074 = bits(_T_4073, 7, 0) connect Queue2_UInt8_22.io.enq.bits, _T_4074 node _T_4075 = eq(UInt<5>(0h17), idx_31) when _T_4075 : node _T_4076 = shl(UInt<5>(0h1f), 3) node _T_4077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4076) node _T_4078 = bits(_T_4077, 7, 0) connect Queue2_UInt8_23.io.enq.bits, _T_4078 node _T_4079 = eq(UInt<5>(0h18), idx_31) when _T_4079 : node _T_4080 = shl(UInt<5>(0h1f), 3) node _T_4081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4080) node _T_4082 = bits(_T_4081, 7, 0) connect Queue2_UInt8_24.io.enq.bits, _T_4082 node _T_4083 = eq(UInt<5>(0h19), idx_31) when _T_4083 : node _T_4084 = shl(UInt<5>(0h1f), 3) node _T_4085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4084) node _T_4086 = bits(_T_4085, 7, 0) connect Queue2_UInt8_25.io.enq.bits, _T_4086 node _T_4087 = eq(UInt<5>(0h1a), idx_31) when _T_4087 : node _T_4088 = shl(UInt<5>(0h1f), 3) node _T_4089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4088) node _T_4090 = bits(_T_4089, 7, 0) connect Queue2_UInt8_26.io.enq.bits, _T_4090 node _T_4091 = eq(UInt<5>(0h1b), idx_31) when _T_4091 : node _T_4092 = shl(UInt<5>(0h1f), 3) node _T_4093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4092) node _T_4094 = bits(_T_4093, 7, 0) connect Queue2_UInt8_27.io.enq.bits, _T_4094 node _T_4095 = eq(UInt<5>(0h1c), idx_31) when _T_4095 : node _T_4096 = shl(UInt<5>(0h1f), 3) node _T_4097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4096) node _T_4098 = bits(_T_4097, 7, 0) connect Queue2_UInt8_28.io.enq.bits, _T_4098 node _T_4099 = eq(UInt<5>(0h1d), idx_31) when _T_4099 : node _T_4100 = shl(UInt<5>(0h1f), 3) node _T_4101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4100) node _T_4102 = bits(_T_4101, 7, 0) connect Queue2_UInt8_29.io.enq.bits, _T_4102 node _T_4103 = eq(UInt<5>(0h1e), idx_31) when _T_4103 : node _T_4104 = shl(UInt<5>(0h1f), 3) node _T_4105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4104) node _T_4106 = bits(_T_4105, 7, 0) connect Queue2_UInt8_30.io.enq.bits, _T_4106 node _T_4107 = eq(UInt<5>(0h1f), idx_31) when _T_4107 : node _T_4108 = shl(UInt<5>(0h1f), 3) node _T_4109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4108) node _T_4110 = bits(_T_4109, 7, 0) connect Queue2_UInt8_31.io.enq.bits, _T_4110 node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) node _all_queues_ready_T = and(Queue2_UInt8.io.enq.ready, Queue2_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue2_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue2_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue2_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue2_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue2_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue2_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue2_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue2_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue2_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue2_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue2_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue2_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue2_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue2_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue2_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue2_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue2_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue2_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue2_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue2_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue2_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue2_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue2_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue2_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue2_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue2_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue2_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue2_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue2_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue2_UInt8_31.io.enq.ready) node _account_for_buf_lens_Q_T = eq(incoming_writes_Q.io.deq.bits.end_of_message, UInt<1>(0h0)) node _account_for_buf_lens_Q_T_1 = and(incoming_writes_Q.io.deq.bits.end_of_message, buf_lens_Q.io.enq.ready) node account_for_buf_lens_Q = or(_account_for_buf_lens_Q_T, _account_for_buf_lens_Q_T_1) node _buf_lens_Q_io_enq_valid_T = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _buf_lens_Q_io_enq_valid_T_1 = and(_buf_lens_Q_io_enq_valid_T, incoming_writes_Q.io.deq.bits.end_of_message) connect buf_lens_Q.io.enq.valid, _buf_lens_Q_io_enq_valid_T_1 node _buf_lens_Q_io_enq_bits_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes) connect buf_lens_Q.io.enq.bits, _buf_lens_Q_io_enq_bits_T node _incoming_writes_Q_io_deq_ready_T = and(all_queues_ready, account_for_buf_lens_Q) connect incoming_writes_Q.io.deq.ready, _incoming_writes_Q_io_deq_ready_T node _T_4111 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4112 = and(_T_4111, account_for_buf_lens_Q) when _T_4112 : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_4113 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4114 = and(_T_4113, account_for_buf_lens_Q) node _T_4115 = and(_T_4114, use_this_queue) connect Queue2_UInt8.io.enq.valid, _T_4115 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_4116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4117 = and(_T_4116, account_for_buf_lens_Q) node _T_4118 = and(_T_4117, use_this_queue_1) connect Queue2_UInt8_1.io.enq.valid, _T_4118 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_4119 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4120 = and(_T_4119, account_for_buf_lens_Q) node _T_4121 = and(_T_4120, use_this_queue_2) connect Queue2_UInt8_2.io.enq.valid, _T_4121 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_4122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4123 = and(_T_4122, account_for_buf_lens_Q) node _T_4124 = and(_T_4123, use_this_queue_3) connect Queue2_UInt8_3.io.enq.valid, _T_4124 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_4125 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4126 = and(_T_4125, account_for_buf_lens_Q) node _T_4127 = and(_T_4126, use_this_queue_4) connect Queue2_UInt8_4.io.enq.valid, _T_4127 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_4128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4129 = and(_T_4128, account_for_buf_lens_Q) node _T_4130 = and(_T_4129, use_this_queue_5) connect Queue2_UInt8_5.io.enq.valid, _T_4130 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_4131 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4132 = and(_T_4131, account_for_buf_lens_Q) node _T_4133 = and(_T_4132, use_this_queue_6) connect Queue2_UInt8_6.io.enq.valid, _T_4133 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_4134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4135 = and(_T_4134, account_for_buf_lens_Q) node _T_4136 = and(_T_4135, use_this_queue_7) connect Queue2_UInt8_7.io.enq.valid, _T_4136 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_4137 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4138 = and(_T_4137, account_for_buf_lens_Q) node _T_4139 = and(_T_4138, use_this_queue_8) connect Queue2_UInt8_8.io.enq.valid, _T_4139 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_4140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4141 = and(_T_4140, account_for_buf_lens_Q) node _T_4142 = and(_T_4141, use_this_queue_9) connect Queue2_UInt8_9.io.enq.valid, _T_4142 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_4143 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4144 = and(_T_4143, account_for_buf_lens_Q) node _T_4145 = and(_T_4144, use_this_queue_10) connect Queue2_UInt8_10.io.enq.valid, _T_4145 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_4146 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4147 = and(_T_4146, account_for_buf_lens_Q) node _T_4148 = and(_T_4147, use_this_queue_11) connect Queue2_UInt8_11.io.enq.valid, _T_4148 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_4149 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4150 = and(_T_4149, account_for_buf_lens_Q) node _T_4151 = and(_T_4150, use_this_queue_12) connect Queue2_UInt8_12.io.enq.valid, _T_4151 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_4152 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4153 = and(_T_4152, account_for_buf_lens_Q) node _T_4154 = and(_T_4153, use_this_queue_13) connect Queue2_UInt8_13.io.enq.valid, _T_4154 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_4155 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4156 = and(_T_4155, account_for_buf_lens_Q) node _T_4157 = and(_T_4156, use_this_queue_14) connect Queue2_UInt8_14.io.enq.valid, _T_4157 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_4158 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4159 = and(_T_4158, account_for_buf_lens_Q) node _T_4160 = and(_T_4159, use_this_queue_15) connect Queue2_UInt8_15.io.enq.valid, _T_4160 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_4161 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4162 = and(_T_4161, account_for_buf_lens_Q) node _T_4163 = and(_T_4162, use_this_queue_16) connect Queue2_UInt8_16.io.enq.valid, _T_4163 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_4164 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4165 = and(_T_4164, account_for_buf_lens_Q) node _T_4166 = and(_T_4165, use_this_queue_17) connect Queue2_UInt8_17.io.enq.valid, _T_4166 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_4167 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4168 = and(_T_4167, account_for_buf_lens_Q) node _T_4169 = and(_T_4168, use_this_queue_18) connect Queue2_UInt8_18.io.enq.valid, _T_4169 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_4170 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4171 = and(_T_4170, account_for_buf_lens_Q) node _T_4172 = and(_T_4171, use_this_queue_19) connect Queue2_UInt8_19.io.enq.valid, _T_4172 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_4173 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4174 = and(_T_4173, account_for_buf_lens_Q) node _T_4175 = and(_T_4174, use_this_queue_20) connect Queue2_UInt8_20.io.enq.valid, _T_4175 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_4176 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4177 = and(_T_4176, account_for_buf_lens_Q) node _T_4178 = and(_T_4177, use_this_queue_21) connect Queue2_UInt8_21.io.enq.valid, _T_4178 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_4179 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4180 = and(_T_4179, account_for_buf_lens_Q) node _T_4181 = and(_T_4180, use_this_queue_22) connect Queue2_UInt8_22.io.enq.valid, _T_4181 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_4182 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4183 = and(_T_4182, account_for_buf_lens_Q) node _T_4184 = and(_T_4183, use_this_queue_23) connect Queue2_UInt8_23.io.enq.valid, _T_4184 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_4185 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4186 = and(_T_4185, account_for_buf_lens_Q) node _T_4187 = and(_T_4186, use_this_queue_24) connect Queue2_UInt8_24.io.enq.valid, _T_4187 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_4188 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4189 = and(_T_4188, account_for_buf_lens_Q) node _T_4190 = and(_T_4189, use_this_queue_25) connect Queue2_UInt8_25.io.enq.valid, _T_4190 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_4191 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4192 = and(_T_4191, account_for_buf_lens_Q) node _T_4193 = and(_T_4192, use_this_queue_26) connect Queue2_UInt8_26.io.enq.valid, _T_4193 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_4194 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4195 = and(_T_4194, account_for_buf_lens_Q) node _T_4196 = and(_T_4195, use_this_queue_27) connect Queue2_UInt8_27.io.enq.valid, _T_4196 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_4197 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4198 = and(_T_4197, account_for_buf_lens_Q) node _T_4199 = and(_T_4198, use_this_queue_28) connect Queue2_UInt8_28.io.enq.valid, _T_4199 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_4200 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4201 = and(_T_4200, account_for_buf_lens_Q) node _T_4202 = and(_T_4201, use_this_queue_29) connect Queue2_UInt8_29.io.enq.valid, _T_4202 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_4203 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4204 = and(_T_4203, account_for_buf_lens_Q) node _T_4205 = and(_T_4204, use_this_queue_30) connect Queue2_UInt8_30.io.enq.valid, _T_4205 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_4206 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_4207 = and(_T_4206, account_for_buf_lens_Q) node _T_4208 = and(_T_4207, use_this_queue_31) connect Queue2_UInt8_31.io.enq.valid, _T_4208 when Queue2_UInt8.io.deq.valid : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_4209 = asUInt(reset) node _T_4210 = eq(_T_4209, UInt<1>(0h0)) when _T_4210 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_4211 = asUInt(reset) node _T_4212 = eq(_T_4211, UInt<1>(0h0)) when _T_4212 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h0), Queue2_UInt8.io.deq.bits) : printf_7 when Queue2_UInt8_1.io.deq.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_4213 = asUInt(reset) node _T_4214 = eq(_T_4213, UInt<1>(0h0)) when _T_4214 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_4215 = asUInt(reset) node _T_4216 = eq(_T_4215, UInt<1>(0h0)) when _T_4216 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h1), Queue2_UInt8_1.io.deq.bits) : printf_9 when Queue2_UInt8_2.io.deq.valid : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_4217 = asUInt(reset) node _T_4218 = eq(_T_4217, UInt<1>(0h0)) when _T_4218 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_4219 = asUInt(reset) node _T_4220 = eq(_T_4219, UInt<1>(0h0)) when _T_4220 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h2), Queue2_UInt8_2.io.deq.bits) : printf_11 when Queue2_UInt8_3.io.deq.valid : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_4221 = asUInt(reset) node _T_4222 = eq(_T_4221, UInt<1>(0h0)) when _T_4222 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_4223 = asUInt(reset) node _T_4224 = eq(_T_4223, UInt<1>(0h0)) when _T_4224 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h3), Queue2_UInt8_3.io.deq.bits) : printf_13 when Queue2_UInt8_4.io.deq.valid : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_4225 = asUInt(reset) node _T_4226 = eq(_T_4225, UInt<1>(0h0)) when _T_4226 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_4227 = asUInt(reset) node _T_4228 = eq(_T_4227, UInt<1>(0h0)) when _T_4228 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h4), Queue2_UInt8_4.io.deq.bits) : printf_15 when Queue2_UInt8_5.io.deq.valid : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_4229 = asUInt(reset) node _T_4230 = eq(_T_4229, UInt<1>(0h0)) when _T_4230 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_4231 = asUInt(reset) node _T_4232 = eq(_T_4231, UInt<1>(0h0)) when _T_4232 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h5), Queue2_UInt8_5.io.deq.bits) : printf_17 when Queue2_UInt8_6.io.deq.valid : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_4233 = asUInt(reset) node _T_4234 = eq(_T_4233, UInt<1>(0h0)) when _T_4234 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_4235 = asUInt(reset) node _T_4236 = eq(_T_4235, UInt<1>(0h0)) when _T_4236 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h6), Queue2_UInt8_6.io.deq.bits) : printf_19 when Queue2_UInt8_7.io.deq.valid : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_4237 = asUInt(reset) node _T_4238 = eq(_T_4237, UInt<1>(0h0)) when _T_4238 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_4239 = asUInt(reset) node _T_4240 = eq(_T_4239, UInt<1>(0h0)) when _T_4240 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h7), Queue2_UInt8_7.io.deq.bits) : printf_21 when Queue2_UInt8_8.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_4241 = asUInt(reset) node _T_4242 = eq(_T_4241, UInt<1>(0h0)) when _T_4242 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_4243 = asUInt(reset) node _T_4244 = eq(_T_4243, UInt<1>(0h0)) when _T_4244 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h8), Queue2_UInt8_8.io.deq.bits) : printf_23 when Queue2_UInt8_9.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_4245 = asUInt(reset) node _T_4246 = eq(_T_4245, UInt<1>(0h0)) when _T_4246 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_4247 = asUInt(reset) node _T_4248 = eq(_T_4247, UInt<1>(0h0)) when _T_4248 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h9), Queue2_UInt8_9.io.deq.bits) : printf_25 when Queue2_UInt8_10.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_4249 = asUInt(reset) node _T_4250 = eq(_T_4249, UInt<1>(0h0)) when _T_4250 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_4251 = asUInt(reset) node _T_4252 = eq(_T_4251, UInt<1>(0h0)) when _T_4252 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0ha), Queue2_UInt8_10.io.deq.bits) : printf_27 when Queue2_UInt8_11.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_4253 = asUInt(reset) node _T_4254 = eq(_T_4253, UInt<1>(0h0)) when _T_4254 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_4255 = asUInt(reset) node _T_4256 = eq(_T_4255, UInt<1>(0h0)) when _T_4256 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hb), Queue2_UInt8_11.io.deq.bits) : printf_29 when Queue2_UInt8_12.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_4257 = asUInt(reset) node _T_4258 = eq(_T_4257, UInt<1>(0h0)) when _T_4258 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_4259 = asUInt(reset) node _T_4260 = eq(_T_4259, UInt<1>(0h0)) when _T_4260 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hc), Queue2_UInt8_12.io.deq.bits) : printf_31 when Queue2_UInt8_13.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_4261 = asUInt(reset) node _T_4262 = eq(_T_4261, UInt<1>(0h0)) when _T_4262 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_4263 = asUInt(reset) node _T_4264 = eq(_T_4263, UInt<1>(0h0)) when _T_4264 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hd), Queue2_UInt8_13.io.deq.bits) : printf_33 when Queue2_UInt8_14.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_4265 = asUInt(reset) node _T_4266 = eq(_T_4265, UInt<1>(0h0)) when _T_4266 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_4267 = asUInt(reset) node _T_4268 = eq(_T_4267, UInt<1>(0h0)) when _T_4268 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0he), Queue2_UInt8_14.io.deq.bits) : printf_35 when Queue2_UInt8_15.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_4269 = asUInt(reset) node _T_4270 = eq(_T_4269, UInt<1>(0h0)) when _T_4270 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_4271 = asUInt(reset) node _T_4272 = eq(_T_4271, UInt<1>(0h0)) when _T_4272 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hf), Queue2_UInt8_15.io.deq.bits) : printf_37 when Queue2_UInt8_16.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_4273 = asUInt(reset) node _T_4274 = eq(_T_4273, UInt<1>(0h0)) when _T_4274 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_4275 = asUInt(reset) node _T_4276 = eq(_T_4275, UInt<1>(0h0)) when _T_4276 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h10), Queue2_UInt8_16.io.deq.bits) : printf_39 when Queue2_UInt8_17.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_4277 = asUInt(reset) node _T_4278 = eq(_T_4277, UInt<1>(0h0)) when _T_4278 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_4279 = asUInt(reset) node _T_4280 = eq(_T_4279, UInt<1>(0h0)) when _T_4280 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h11), Queue2_UInt8_17.io.deq.bits) : printf_41 when Queue2_UInt8_18.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_4281 = asUInt(reset) node _T_4282 = eq(_T_4281, UInt<1>(0h0)) when _T_4282 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_4283 = asUInt(reset) node _T_4284 = eq(_T_4283, UInt<1>(0h0)) when _T_4284 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h12), Queue2_UInt8_18.io.deq.bits) : printf_43 when Queue2_UInt8_19.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_4285 = asUInt(reset) node _T_4286 = eq(_T_4285, UInt<1>(0h0)) when _T_4286 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_4287 = asUInt(reset) node _T_4288 = eq(_T_4287, UInt<1>(0h0)) when _T_4288 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h13), Queue2_UInt8_19.io.deq.bits) : printf_45 when Queue2_UInt8_20.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_4289 = asUInt(reset) node _T_4290 = eq(_T_4289, UInt<1>(0h0)) when _T_4290 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_4291 = asUInt(reset) node _T_4292 = eq(_T_4291, UInt<1>(0h0)) when _T_4292 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h14), Queue2_UInt8_20.io.deq.bits) : printf_47 when Queue2_UInt8_21.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_4293 = asUInt(reset) node _T_4294 = eq(_T_4293, UInt<1>(0h0)) when _T_4294 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h15), Queue2_UInt8_21.io.deq.bits) : printf_49 when Queue2_UInt8_22.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_4297 = asUInt(reset) node _T_4298 = eq(_T_4297, UInt<1>(0h0)) when _T_4298 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_4299 = asUInt(reset) node _T_4300 = eq(_T_4299, UInt<1>(0h0)) when _T_4300 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h16), Queue2_UInt8_22.io.deq.bits) : printf_51 when Queue2_UInt8_23.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_4301 = asUInt(reset) node _T_4302 = eq(_T_4301, UInt<1>(0h0)) when _T_4302 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_4303 = asUInt(reset) node _T_4304 = eq(_T_4303, UInt<1>(0h0)) when _T_4304 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h17), Queue2_UInt8_23.io.deq.bits) : printf_53 when Queue2_UInt8_24.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_4305 = asUInt(reset) node _T_4306 = eq(_T_4305, UInt<1>(0h0)) when _T_4306 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_4307 = asUInt(reset) node _T_4308 = eq(_T_4307, UInt<1>(0h0)) when _T_4308 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h18), Queue2_UInt8_24.io.deq.bits) : printf_55 when Queue2_UInt8_25.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_4309 = asUInt(reset) node _T_4310 = eq(_T_4309, UInt<1>(0h0)) when _T_4310 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_4311 = asUInt(reset) node _T_4312 = eq(_T_4311, UInt<1>(0h0)) when _T_4312 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h19), Queue2_UInt8_25.io.deq.bits) : printf_57 when Queue2_UInt8_26.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_4313 = asUInt(reset) node _T_4314 = eq(_T_4313, UInt<1>(0h0)) when _T_4314 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_4315 = asUInt(reset) node _T_4316 = eq(_T_4315, UInt<1>(0h0)) when _T_4316 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1a), Queue2_UInt8_26.io.deq.bits) : printf_59 when Queue2_UInt8_27.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_4317 = asUInt(reset) node _T_4318 = eq(_T_4317, UInt<1>(0h0)) when _T_4318 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_4319 = asUInt(reset) node _T_4320 = eq(_T_4319, UInt<1>(0h0)) when _T_4320 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1b), Queue2_UInt8_27.io.deq.bits) : printf_61 when Queue2_UInt8_28.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_4321 = asUInt(reset) node _T_4322 = eq(_T_4321, UInt<1>(0h0)) when _T_4322 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_4323 = asUInt(reset) node _T_4324 = eq(_T_4323, UInt<1>(0h0)) when _T_4324 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1c), Queue2_UInt8_28.io.deq.bits) : printf_63 when Queue2_UInt8_29.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_4325 = asUInt(reset) node _T_4326 = eq(_T_4325, UInt<1>(0h0)) when _T_4326 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_4327 = asUInt(reset) node _T_4328 = eq(_T_4327, UInt<1>(0h0)) when _T_4328 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1d), Queue2_UInt8_29.io.deq.bits) : printf_65 when Queue2_UInt8_30.io.deq.valid : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_4329 = asUInt(reset) node _T_4330 = eq(_T_4329, UInt<1>(0h0)) when _T_4330 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_4331 = asUInt(reset) node _T_4332 = eq(_T_4331, UInt<1>(0h0)) when _T_4332 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1e), Queue2_UInt8_30.io.deq.bits) : printf_67 when Queue2_UInt8_31.io.deq.valid : regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_4333 = asUInt(reset) node _T_4334 = eq(_T_4333, UInt<1>(0h0)) when _T_4334 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_4335 = asUInt(reset) node _T_4336 = eq(_T_4335, UInt<1>(0h0)) when _T_4336 : printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1f), Queue2_UInt8_31.io.deq.bits) : printf_69 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue2_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue2_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue2_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue2_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue2_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue2_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue2_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue2_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue2_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue2_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue2_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue2_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue2_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue2_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue2_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue2_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue2_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue2_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue2_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue2_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue2_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue2_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue2_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue2_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue2_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue2_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue2_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue2_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue2_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue2_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue2_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue2_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_4337 = eq(UInt<1>(0h0), remapindex) when _T_4337 : connect remapVecData[0], Queue2_UInt8.io.deq.bits connect remapVecValids[0], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[0] node _T_4338 = eq(UInt<1>(0h1), remapindex) when _T_4338 : connect remapVecData[0], Queue2_UInt8_1.io.deq.bits connect remapVecValids[0], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_4339 = eq(UInt<2>(0h2), remapindex) when _T_4339 : connect remapVecData[0], Queue2_UInt8_2.io.deq.bits connect remapVecValids[0], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_4340 = eq(UInt<2>(0h3), remapindex) when _T_4340 : connect remapVecData[0], Queue2_UInt8_3.io.deq.bits connect remapVecValids[0], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_4341 = eq(UInt<3>(0h4), remapindex) when _T_4341 : connect remapVecData[0], Queue2_UInt8_4.io.deq.bits connect remapVecValids[0], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_4342 = eq(UInt<3>(0h5), remapindex) when _T_4342 : connect remapVecData[0], Queue2_UInt8_5.io.deq.bits connect remapVecValids[0], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_4343 = eq(UInt<3>(0h6), remapindex) when _T_4343 : connect remapVecData[0], Queue2_UInt8_6.io.deq.bits connect remapVecValids[0], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_4344 = eq(UInt<3>(0h7), remapindex) when _T_4344 : connect remapVecData[0], Queue2_UInt8_7.io.deq.bits connect remapVecValids[0], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_4345 = eq(UInt<4>(0h8), remapindex) when _T_4345 : connect remapVecData[0], Queue2_UInt8_8.io.deq.bits connect remapVecValids[0], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_4346 = eq(UInt<4>(0h9), remapindex) when _T_4346 : connect remapVecData[0], Queue2_UInt8_9.io.deq.bits connect remapVecValids[0], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_4347 = eq(UInt<4>(0ha), remapindex) when _T_4347 : connect remapVecData[0], Queue2_UInt8_10.io.deq.bits connect remapVecValids[0], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_4348 = eq(UInt<4>(0hb), remapindex) when _T_4348 : connect remapVecData[0], Queue2_UInt8_11.io.deq.bits connect remapVecValids[0], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_4349 = eq(UInt<4>(0hc), remapindex) when _T_4349 : connect remapVecData[0], Queue2_UInt8_12.io.deq.bits connect remapVecValids[0], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_4350 = eq(UInt<4>(0hd), remapindex) when _T_4350 : connect remapVecData[0], Queue2_UInt8_13.io.deq.bits connect remapVecValids[0], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_4351 = eq(UInt<4>(0he), remapindex) when _T_4351 : connect remapVecData[0], Queue2_UInt8_14.io.deq.bits connect remapVecValids[0], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_4352 = eq(UInt<4>(0hf), remapindex) when _T_4352 : connect remapVecData[0], Queue2_UInt8_15.io.deq.bits connect remapVecValids[0], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_4353 = eq(UInt<5>(0h10), remapindex) when _T_4353 : connect remapVecData[0], Queue2_UInt8_16.io.deq.bits connect remapVecValids[0], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_4354 = eq(UInt<5>(0h11), remapindex) when _T_4354 : connect remapVecData[0], Queue2_UInt8_17.io.deq.bits connect remapVecValids[0], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_4355 = eq(UInt<5>(0h12), remapindex) when _T_4355 : connect remapVecData[0], Queue2_UInt8_18.io.deq.bits connect remapVecValids[0], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_4356 = eq(UInt<5>(0h13), remapindex) when _T_4356 : connect remapVecData[0], Queue2_UInt8_19.io.deq.bits connect remapVecValids[0], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_4357 = eq(UInt<5>(0h14), remapindex) when _T_4357 : connect remapVecData[0], Queue2_UInt8_20.io.deq.bits connect remapVecValids[0], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_4358 = eq(UInt<5>(0h15), remapindex) when _T_4358 : connect remapVecData[0], Queue2_UInt8_21.io.deq.bits connect remapVecValids[0], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_4359 = eq(UInt<5>(0h16), remapindex) when _T_4359 : connect remapVecData[0], Queue2_UInt8_22.io.deq.bits connect remapVecValids[0], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_4360 = eq(UInt<5>(0h17), remapindex) when _T_4360 : connect remapVecData[0], Queue2_UInt8_23.io.deq.bits connect remapVecValids[0], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_4361 = eq(UInt<5>(0h18), remapindex) when _T_4361 : connect remapVecData[0], Queue2_UInt8_24.io.deq.bits connect remapVecValids[0], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_4362 = eq(UInt<5>(0h19), remapindex) when _T_4362 : connect remapVecData[0], Queue2_UInt8_25.io.deq.bits connect remapVecValids[0], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_4363 = eq(UInt<5>(0h1a), remapindex) when _T_4363 : connect remapVecData[0], Queue2_UInt8_26.io.deq.bits connect remapVecValids[0], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_4364 = eq(UInt<5>(0h1b), remapindex) when _T_4364 : connect remapVecData[0], Queue2_UInt8_27.io.deq.bits connect remapVecValids[0], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_4365 = eq(UInt<5>(0h1c), remapindex) when _T_4365 : connect remapVecData[0], Queue2_UInt8_28.io.deq.bits connect remapVecValids[0], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_4366 = eq(UInt<5>(0h1d), remapindex) when _T_4366 : connect remapVecData[0], Queue2_UInt8_29.io.deq.bits connect remapVecValids[0], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_4367 = eq(UInt<5>(0h1e), remapindex) when _T_4367 : connect remapVecData[0], Queue2_UInt8_30.io.deq.bits connect remapVecValids[0], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_4368 = eq(UInt<5>(0h1f), remapindex) when _T_4368 : connect remapVecData[0], Queue2_UInt8_31.io.deq.bits connect remapVecValids[0], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_4369 = eq(UInt<1>(0h0), remapindex_1) when _T_4369 : connect remapVecData[1], Queue2_UInt8.io.deq.bits connect remapVecValids[1], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[1] node _T_4370 = eq(UInt<1>(0h1), remapindex_1) when _T_4370 : connect remapVecData[1], Queue2_UInt8_1.io.deq.bits connect remapVecValids[1], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_4371 = eq(UInt<2>(0h2), remapindex_1) when _T_4371 : connect remapVecData[1], Queue2_UInt8_2.io.deq.bits connect remapVecValids[1], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_4372 = eq(UInt<2>(0h3), remapindex_1) when _T_4372 : connect remapVecData[1], Queue2_UInt8_3.io.deq.bits connect remapVecValids[1], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_4373 = eq(UInt<3>(0h4), remapindex_1) when _T_4373 : connect remapVecData[1], Queue2_UInt8_4.io.deq.bits connect remapVecValids[1], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_4374 = eq(UInt<3>(0h5), remapindex_1) when _T_4374 : connect remapVecData[1], Queue2_UInt8_5.io.deq.bits connect remapVecValids[1], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_4375 = eq(UInt<3>(0h6), remapindex_1) when _T_4375 : connect remapVecData[1], Queue2_UInt8_6.io.deq.bits connect remapVecValids[1], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_4376 = eq(UInt<3>(0h7), remapindex_1) when _T_4376 : connect remapVecData[1], Queue2_UInt8_7.io.deq.bits connect remapVecValids[1], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_4377 = eq(UInt<4>(0h8), remapindex_1) when _T_4377 : connect remapVecData[1], Queue2_UInt8_8.io.deq.bits connect remapVecValids[1], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_4378 = eq(UInt<4>(0h9), remapindex_1) when _T_4378 : connect remapVecData[1], Queue2_UInt8_9.io.deq.bits connect remapVecValids[1], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_4379 = eq(UInt<4>(0ha), remapindex_1) when _T_4379 : connect remapVecData[1], Queue2_UInt8_10.io.deq.bits connect remapVecValids[1], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_4380 = eq(UInt<4>(0hb), remapindex_1) when _T_4380 : connect remapVecData[1], Queue2_UInt8_11.io.deq.bits connect remapVecValids[1], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_4381 = eq(UInt<4>(0hc), remapindex_1) when _T_4381 : connect remapVecData[1], Queue2_UInt8_12.io.deq.bits connect remapVecValids[1], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_4382 = eq(UInt<4>(0hd), remapindex_1) when _T_4382 : connect remapVecData[1], Queue2_UInt8_13.io.deq.bits connect remapVecValids[1], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_4383 = eq(UInt<4>(0he), remapindex_1) when _T_4383 : connect remapVecData[1], Queue2_UInt8_14.io.deq.bits connect remapVecValids[1], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_4384 = eq(UInt<4>(0hf), remapindex_1) when _T_4384 : connect remapVecData[1], Queue2_UInt8_15.io.deq.bits connect remapVecValids[1], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_4385 = eq(UInt<5>(0h10), remapindex_1) when _T_4385 : connect remapVecData[1], Queue2_UInt8_16.io.deq.bits connect remapVecValids[1], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_4386 = eq(UInt<5>(0h11), remapindex_1) when _T_4386 : connect remapVecData[1], Queue2_UInt8_17.io.deq.bits connect remapVecValids[1], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_4387 = eq(UInt<5>(0h12), remapindex_1) when _T_4387 : connect remapVecData[1], Queue2_UInt8_18.io.deq.bits connect remapVecValids[1], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_4388 = eq(UInt<5>(0h13), remapindex_1) when _T_4388 : connect remapVecData[1], Queue2_UInt8_19.io.deq.bits connect remapVecValids[1], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_4389 = eq(UInt<5>(0h14), remapindex_1) when _T_4389 : connect remapVecData[1], Queue2_UInt8_20.io.deq.bits connect remapVecValids[1], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_4390 = eq(UInt<5>(0h15), remapindex_1) when _T_4390 : connect remapVecData[1], Queue2_UInt8_21.io.deq.bits connect remapVecValids[1], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_4391 = eq(UInt<5>(0h16), remapindex_1) when _T_4391 : connect remapVecData[1], Queue2_UInt8_22.io.deq.bits connect remapVecValids[1], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_4392 = eq(UInt<5>(0h17), remapindex_1) when _T_4392 : connect remapVecData[1], Queue2_UInt8_23.io.deq.bits connect remapVecValids[1], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_4393 = eq(UInt<5>(0h18), remapindex_1) when _T_4393 : connect remapVecData[1], Queue2_UInt8_24.io.deq.bits connect remapVecValids[1], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_4394 = eq(UInt<5>(0h19), remapindex_1) when _T_4394 : connect remapVecData[1], Queue2_UInt8_25.io.deq.bits connect remapVecValids[1], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_4395 = eq(UInt<5>(0h1a), remapindex_1) when _T_4395 : connect remapVecData[1], Queue2_UInt8_26.io.deq.bits connect remapVecValids[1], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_4396 = eq(UInt<5>(0h1b), remapindex_1) when _T_4396 : connect remapVecData[1], Queue2_UInt8_27.io.deq.bits connect remapVecValids[1], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_4397 = eq(UInt<5>(0h1c), remapindex_1) when _T_4397 : connect remapVecData[1], Queue2_UInt8_28.io.deq.bits connect remapVecValids[1], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_4398 = eq(UInt<5>(0h1d), remapindex_1) when _T_4398 : connect remapVecData[1], Queue2_UInt8_29.io.deq.bits connect remapVecValids[1], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_4399 = eq(UInt<5>(0h1e), remapindex_1) when _T_4399 : connect remapVecData[1], Queue2_UInt8_30.io.deq.bits connect remapVecValids[1], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_4400 = eq(UInt<5>(0h1f), remapindex_1) when _T_4400 : connect remapVecData[1], Queue2_UInt8_31.io.deq.bits connect remapVecValids[1], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_4401 = eq(UInt<1>(0h0), remapindex_2) when _T_4401 : connect remapVecData[2], Queue2_UInt8.io.deq.bits connect remapVecValids[2], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[2] node _T_4402 = eq(UInt<1>(0h1), remapindex_2) when _T_4402 : connect remapVecData[2], Queue2_UInt8_1.io.deq.bits connect remapVecValids[2], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_4403 = eq(UInt<2>(0h2), remapindex_2) when _T_4403 : connect remapVecData[2], Queue2_UInt8_2.io.deq.bits connect remapVecValids[2], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_4404 = eq(UInt<2>(0h3), remapindex_2) when _T_4404 : connect remapVecData[2], Queue2_UInt8_3.io.deq.bits connect remapVecValids[2], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_4405 = eq(UInt<3>(0h4), remapindex_2) when _T_4405 : connect remapVecData[2], Queue2_UInt8_4.io.deq.bits connect remapVecValids[2], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_4406 = eq(UInt<3>(0h5), remapindex_2) when _T_4406 : connect remapVecData[2], Queue2_UInt8_5.io.deq.bits connect remapVecValids[2], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_4407 = eq(UInt<3>(0h6), remapindex_2) when _T_4407 : connect remapVecData[2], Queue2_UInt8_6.io.deq.bits connect remapVecValids[2], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_4408 = eq(UInt<3>(0h7), remapindex_2) when _T_4408 : connect remapVecData[2], Queue2_UInt8_7.io.deq.bits connect remapVecValids[2], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_4409 = eq(UInt<4>(0h8), remapindex_2) when _T_4409 : connect remapVecData[2], Queue2_UInt8_8.io.deq.bits connect remapVecValids[2], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_4410 = eq(UInt<4>(0h9), remapindex_2) when _T_4410 : connect remapVecData[2], Queue2_UInt8_9.io.deq.bits connect remapVecValids[2], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_4411 = eq(UInt<4>(0ha), remapindex_2) when _T_4411 : connect remapVecData[2], Queue2_UInt8_10.io.deq.bits connect remapVecValids[2], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_4412 = eq(UInt<4>(0hb), remapindex_2) when _T_4412 : connect remapVecData[2], Queue2_UInt8_11.io.deq.bits connect remapVecValids[2], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_4413 = eq(UInt<4>(0hc), remapindex_2) when _T_4413 : connect remapVecData[2], Queue2_UInt8_12.io.deq.bits connect remapVecValids[2], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_4414 = eq(UInt<4>(0hd), remapindex_2) when _T_4414 : connect remapVecData[2], Queue2_UInt8_13.io.deq.bits connect remapVecValids[2], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_4415 = eq(UInt<4>(0he), remapindex_2) when _T_4415 : connect remapVecData[2], Queue2_UInt8_14.io.deq.bits connect remapVecValids[2], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_4416 = eq(UInt<4>(0hf), remapindex_2) when _T_4416 : connect remapVecData[2], Queue2_UInt8_15.io.deq.bits connect remapVecValids[2], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_4417 = eq(UInt<5>(0h10), remapindex_2) when _T_4417 : connect remapVecData[2], Queue2_UInt8_16.io.deq.bits connect remapVecValids[2], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_4418 = eq(UInt<5>(0h11), remapindex_2) when _T_4418 : connect remapVecData[2], Queue2_UInt8_17.io.deq.bits connect remapVecValids[2], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_4419 = eq(UInt<5>(0h12), remapindex_2) when _T_4419 : connect remapVecData[2], Queue2_UInt8_18.io.deq.bits connect remapVecValids[2], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_4420 = eq(UInt<5>(0h13), remapindex_2) when _T_4420 : connect remapVecData[2], Queue2_UInt8_19.io.deq.bits connect remapVecValids[2], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_4421 = eq(UInt<5>(0h14), remapindex_2) when _T_4421 : connect remapVecData[2], Queue2_UInt8_20.io.deq.bits connect remapVecValids[2], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_4422 = eq(UInt<5>(0h15), remapindex_2) when _T_4422 : connect remapVecData[2], Queue2_UInt8_21.io.deq.bits connect remapVecValids[2], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_4423 = eq(UInt<5>(0h16), remapindex_2) when _T_4423 : connect remapVecData[2], Queue2_UInt8_22.io.deq.bits connect remapVecValids[2], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_4424 = eq(UInt<5>(0h17), remapindex_2) when _T_4424 : connect remapVecData[2], Queue2_UInt8_23.io.deq.bits connect remapVecValids[2], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_4425 = eq(UInt<5>(0h18), remapindex_2) when _T_4425 : connect remapVecData[2], Queue2_UInt8_24.io.deq.bits connect remapVecValids[2], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_4426 = eq(UInt<5>(0h19), remapindex_2) when _T_4426 : connect remapVecData[2], Queue2_UInt8_25.io.deq.bits connect remapVecValids[2], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_4427 = eq(UInt<5>(0h1a), remapindex_2) when _T_4427 : connect remapVecData[2], Queue2_UInt8_26.io.deq.bits connect remapVecValids[2], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_4428 = eq(UInt<5>(0h1b), remapindex_2) when _T_4428 : connect remapVecData[2], Queue2_UInt8_27.io.deq.bits connect remapVecValids[2], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_4429 = eq(UInt<5>(0h1c), remapindex_2) when _T_4429 : connect remapVecData[2], Queue2_UInt8_28.io.deq.bits connect remapVecValids[2], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_4430 = eq(UInt<5>(0h1d), remapindex_2) when _T_4430 : connect remapVecData[2], Queue2_UInt8_29.io.deq.bits connect remapVecValids[2], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_4431 = eq(UInt<5>(0h1e), remapindex_2) when _T_4431 : connect remapVecData[2], Queue2_UInt8_30.io.deq.bits connect remapVecValids[2], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_4432 = eq(UInt<5>(0h1f), remapindex_2) when _T_4432 : connect remapVecData[2], Queue2_UInt8_31.io.deq.bits connect remapVecValids[2], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_4433 = eq(UInt<1>(0h0), remapindex_3) when _T_4433 : connect remapVecData[3], Queue2_UInt8.io.deq.bits connect remapVecValids[3], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[3] node _T_4434 = eq(UInt<1>(0h1), remapindex_3) when _T_4434 : connect remapVecData[3], Queue2_UInt8_1.io.deq.bits connect remapVecValids[3], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_4435 = eq(UInt<2>(0h2), remapindex_3) when _T_4435 : connect remapVecData[3], Queue2_UInt8_2.io.deq.bits connect remapVecValids[3], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_4436 = eq(UInt<2>(0h3), remapindex_3) when _T_4436 : connect remapVecData[3], Queue2_UInt8_3.io.deq.bits connect remapVecValids[3], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_4437 = eq(UInt<3>(0h4), remapindex_3) when _T_4437 : connect remapVecData[3], Queue2_UInt8_4.io.deq.bits connect remapVecValids[3], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_4438 = eq(UInt<3>(0h5), remapindex_3) when _T_4438 : connect remapVecData[3], Queue2_UInt8_5.io.deq.bits connect remapVecValids[3], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_4439 = eq(UInt<3>(0h6), remapindex_3) when _T_4439 : connect remapVecData[3], Queue2_UInt8_6.io.deq.bits connect remapVecValids[3], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_4440 = eq(UInt<3>(0h7), remapindex_3) when _T_4440 : connect remapVecData[3], Queue2_UInt8_7.io.deq.bits connect remapVecValids[3], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_4441 = eq(UInt<4>(0h8), remapindex_3) when _T_4441 : connect remapVecData[3], Queue2_UInt8_8.io.deq.bits connect remapVecValids[3], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_4442 = eq(UInt<4>(0h9), remapindex_3) when _T_4442 : connect remapVecData[3], Queue2_UInt8_9.io.deq.bits connect remapVecValids[3], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_4443 = eq(UInt<4>(0ha), remapindex_3) when _T_4443 : connect remapVecData[3], Queue2_UInt8_10.io.deq.bits connect remapVecValids[3], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_4444 = eq(UInt<4>(0hb), remapindex_3) when _T_4444 : connect remapVecData[3], Queue2_UInt8_11.io.deq.bits connect remapVecValids[3], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_4445 = eq(UInt<4>(0hc), remapindex_3) when _T_4445 : connect remapVecData[3], Queue2_UInt8_12.io.deq.bits connect remapVecValids[3], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_4446 = eq(UInt<4>(0hd), remapindex_3) when _T_4446 : connect remapVecData[3], Queue2_UInt8_13.io.deq.bits connect remapVecValids[3], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_4447 = eq(UInt<4>(0he), remapindex_3) when _T_4447 : connect remapVecData[3], Queue2_UInt8_14.io.deq.bits connect remapVecValids[3], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_4448 = eq(UInt<4>(0hf), remapindex_3) when _T_4448 : connect remapVecData[3], Queue2_UInt8_15.io.deq.bits connect remapVecValids[3], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_4449 = eq(UInt<5>(0h10), remapindex_3) when _T_4449 : connect remapVecData[3], Queue2_UInt8_16.io.deq.bits connect remapVecValids[3], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_4450 = eq(UInt<5>(0h11), remapindex_3) when _T_4450 : connect remapVecData[3], Queue2_UInt8_17.io.deq.bits connect remapVecValids[3], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_4451 = eq(UInt<5>(0h12), remapindex_3) when _T_4451 : connect remapVecData[3], Queue2_UInt8_18.io.deq.bits connect remapVecValids[3], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_4452 = eq(UInt<5>(0h13), remapindex_3) when _T_4452 : connect remapVecData[3], Queue2_UInt8_19.io.deq.bits connect remapVecValids[3], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_4453 = eq(UInt<5>(0h14), remapindex_3) when _T_4453 : connect remapVecData[3], Queue2_UInt8_20.io.deq.bits connect remapVecValids[3], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_4454 = eq(UInt<5>(0h15), remapindex_3) when _T_4454 : connect remapVecData[3], Queue2_UInt8_21.io.deq.bits connect remapVecValids[3], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_4455 = eq(UInt<5>(0h16), remapindex_3) when _T_4455 : connect remapVecData[3], Queue2_UInt8_22.io.deq.bits connect remapVecValids[3], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_4456 = eq(UInt<5>(0h17), remapindex_3) when _T_4456 : connect remapVecData[3], Queue2_UInt8_23.io.deq.bits connect remapVecValids[3], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_4457 = eq(UInt<5>(0h18), remapindex_3) when _T_4457 : connect remapVecData[3], Queue2_UInt8_24.io.deq.bits connect remapVecValids[3], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_4458 = eq(UInt<5>(0h19), remapindex_3) when _T_4458 : connect remapVecData[3], Queue2_UInt8_25.io.deq.bits connect remapVecValids[3], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_4459 = eq(UInt<5>(0h1a), remapindex_3) when _T_4459 : connect remapVecData[3], Queue2_UInt8_26.io.deq.bits connect remapVecValids[3], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_4460 = eq(UInt<5>(0h1b), remapindex_3) when _T_4460 : connect remapVecData[3], Queue2_UInt8_27.io.deq.bits connect remapVecValids[3], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_4461 = eq(UInt<5>(0h1c), remapindex_3) when _T_4461 : connect remapVecData[3], Queue2_UInt8_28.io.deq.bits connect remapVecValids[3], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_4462 = eq(UInt<5>(0h1d), remapindex_3) when _T_4462 : connect remapVecData[3], Queue2_UInt8_29.io.deq.bits connect remapVecValids[3], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_4463 = eq(UInt<5>(0h1e), remapindex_3) when _T_4463 : connect remapVecData[3], Queue2_UInt8_30.io.deq.bits connect remapVecValids[3], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_4464 = eq(UInt<5>(0h1f), remapindex_3) when _T_4464 : connect remapVecData[3], Queue2_UInt8_31.io.deq.bits connect remapVecValids[3], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_4465 = eq(UInt<1>(0h0), remapindex_4) when _T_4465 : connect remapVecData[4], Queue2_UInt8.io.deq.bits connect remapVecValids[4], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[4] node _T_4466 = eq(UInt<1>(0h1), remapindex_4) when _T_4466 : connect remapVecData[4], Queue2_UInt8_1.io.deq.bits connect remapVecValids[4], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_4467 = eq(UInt<2>(0h2), remapindex_4) when _T_4467 : connect remapVecData[4], Queue2_UInt8_2.io.deq.bits connect remapVecValids[4], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_4468 = eq(UInt<2>(0h3), remapindex_4) when _T_4468 : connect remapVecData[4], Queue2_UInt8_3.io.deq.bits connect remapVecValids[4], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_4469 = eq(UInt<3>(0h4), remapindex_4) when _T_4469 : connect remapVecData[4], Queue2_UInt8_4.io.deq.bits connect remapVecValids[4], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_4470 = eq(UInt<3>(0h5), remapindex_4) when _T_4470 : connect remapVecData[4], Queue2_UInt8_5.io.deq.bits connect remapVecValids[4], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_4471 = eq(UInt<3>(0h6), remapindex_4) when _T_4471 : connect remapVecData[4], Queue2_UInt8_6.io.deq.bits connect remapVecValids[4], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_4472 = eq(UInt<3>(0h7), remapindex_4) when _T_4472 : connect remapVecData[4], Queue2_UInt8_7.io.deq.bits connect remapVecValids[4], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_4473 = eq(UInt<4>(0h8), remapindex_4) when _T_4473 : connect remapVecData[4], Queue2_UInt8_8.io.deq.bits connect remapVecValids[4], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_4474 = eq(UInt<4>(0h9), remapindex_4) when _T_4474 : connect remapVecData[4], Queue2_UInt8_9.io.deq.bits connect remapVecValids[4], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_4475 = eq(UInt<4>(0ha), remapindex_4) when _T_4475 : connect remapVecData[4], Queue2_UInt8_10.io.deq.bits connect remapVecValids[4], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_4476 = eq(UInt<4>(0hb), remapindex_4) when _T_4476 : connect remapVecData[4], Queue2_UInt8_11.io.deq.bits connect remapVecValids[4], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_4477 = eq(UInt<4>(0hc), remapindex_4) when _T_4477 : connect remapVecData[4], Queue2_UInt8_12.io.deq.bits connect remapVecValids[4], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_4478 = eq(UInt<4>(0hd), remapindex_4) when _T_4478 : connect remapVecData[4], Queue2_UInt8_13.io.deq.bits connect remapVecValids[4], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_4479 = eq(UInt<4>(0he), remapindex_4) when _T_4479 : connect remapVecData[4], Queue2_UInt8_14.io.deq.bits connect remapVecValids[4], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_4480 = eq(UInt<4>(0hf), remapindex_4) when _T_4480 : connect remapVecData[4], Queue2_UInt8_15.io.deq.bits connect remapVecValids[4], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_4481 = eq(UInt<5>(0h10), remapindex_4) when _T_4481 : connect remapVecData[4], Queue2_UInt8_16.io.deq.bits connect remapVecValids[4], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_4482 = eq(UInt<5>(0h11), remapindex_4) when _T_4482 : connect remapVecData[4], Queue2_UInt8_17.io.deq.bits connect remapVecValids[4], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_4483 = eq(UInt<5>(0h12), remapindex_4) when _T_4483 : connect remapVecData[4], Queue2_UInt8_18.io.deq.bits connect remapVecValids[4], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_4484 = eq(UInt<5>(0h13), remapindex_4) when _T_4484 : connect remapVecData[4], Queue2_UInt8_19.io.deq.bits connect remapVecValids[4], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_4485 = eq(UInt<5>(0h14), remapindex_4) when _T_4485 : connect remapVecData[4], Queue2_UInt8_20.io.deq.bits connect remapVecValids[4], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_4486 = eq(UInt<5>(0h15), remapindex_4) when _T_4486 : connect remapVecData[4], Queue2_UInt8_21.io.deq.bits connect remapVecValids[4], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_4487 = eq(UInt<5>(0h16), remapindex_4) when _T_4487 : connect remapVecData[4], Queue2_UInt8_22.io.deq.bits connect remapVecValids[4], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_4488 = eq(UInt<5>(0h17), remapindex_4) when _T_4488 : connect remapVecData[4], Queue2_UInt8_23.io.deq.bits connect remapVecValids[4], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_4489 = eq(UInt<5>(0h18), remapindex_4) when _T_4489 : connect remapVecData[4], Queue2_UInt8_24.io.deq.bits connect remapVecValids[4], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_4490 = eq(UInt<5>(0h19), remapindex_4) when _T_4490 : connect remapVecData[4], Queue2_UInt8_25.io.deq.bits connect remapVecValids[4], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_4491 = eq(UInt<5>(0h1a), remapindex_4) when _T_4491 : connect remapVecData[4], Queue2_UInt8_26.io.deq.bits connect remapVecValids[4], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_4492 = eq(UInt<5>(0h1b), remapindex_4) when _T_4492 : connect remapVecData[4], Queue2_UInt8_27.io.deq.bits connect remapVecValids[4], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_4493 = eq(UInt<5>(0h1c), remapindex_4) when _T_4493 : connect remapVecData[4], Queue2_UInt8_28.io.deq.bits connect remapVecValids[4], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_4494 = eq(UInt<5>(0h1d), remapindex_4) when _T_4494 : connect remapVecData[4], Queue2_UInt8_29.io.deq.bits connect remapVecValids[4], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_4495 = eq(UInt<5>(0h1e), remapindex_4) when _T_4495 : connect remapVecData[4], Queue2_UInt8_30.io.deq.bits connect remapVecValids[4], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_4496 = eq(UInt<5>(0h1f), remapindex_4) when _T_4496 : connect remapVecData[4], Queue2_UInt8_31.io.deq.bits connect remapVecValids[4], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_4497 = eq(UInt<1>(0h0), remapindex_5) when _T_4497 : connect remapVecData[5], Queue2_UInt8.io.deq.bits connect remapVecValids[5], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[5] node _T_4498 = eq(UInt<1>(0h1), remapindex_5) when _T_4498 : connect remapVecData[5], Queue2_UInt8_1.io.deq.bits connect remapVecValids[5], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_4499 = eq(UInt<2>(0h2), remapindex_5) when _T_4499 : connect remapVecData[5], Queue2_UInt8_2.io.deq.bits connect remapVecValids[5], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_4500 = eq(UInt<2>(0h3), remapindex_5) when _T_4500 : connect remapVecData[5], Queue2_UInt8_3.io.deq.bits connect remapVecValids[5], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_4501 = eq(UInt<3>(0h4), remapindex_5) when _T_4501 : connect remapVecData[5], Queue2_UInt8_4.io.deq.bits connect remapVecValids[5], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_4502 = eq(UInt<3>(0h5), remapindex_5) when _T_4502 : connect remapVecData[5], Queue2_UInt8_5.io.deq.bits connect remapVecValids[5], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_4503 = eq(UInt<3>(0h6), remapindex_5) when _T_4503 : connect remapVecData[5], Queue2_UInt8_6.io.deq.bits connect remapVecValids[5], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_4504 = eq(UInt<3>(0h7), remapindex_5) when _T_4504 : connect remapVecData[5], Queue2_UInt8_7.io.deq.bits connect remapVecValids[5], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_4505 = eq(UInt<4>(0h8), remapindex_5) when _T_4505 : connect remapVecData[5], Queue2_UInt8_8.io.deq.bits connect remapVecValids[5], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_4506 = eq(UInt<4>(0h9), remapindex_5) when _T_4506 : connect remapVecData[5], Queue2_UInt8_9.io.deq.bits connect remapVecValids[5], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_4507 = eq(UInt<4>(0ha), remapindex_5) when _T_4507 : connect remapVecData[5], Queue2_UInt8_10.io.deq.bits connect remapVecValids[5], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_4508 = eq(UInt<4>(0hb), remapindex_5) when _T_4508 : connect remapVecData[5], Queue2_UInt8_11.io.deq.bits connect remapVecValids[5], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_4509 = eq(UInt<4>(0hc), remapindex_5) when _T_4509 : connect remapVecData[5], Queue2_UInt8_12.io.deq.bits connect remapVecValids[5], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_4510 = eq(UInt<4>(0hd), remapindex_5) when _T_4510 : connect remapVecData[5], Queue2_UInt8_13.io.deq.bits connect remapVecValids[5], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_4511 = eq(UInt<4>(0he), remapindex_5) when _T_4511 : connect remapVecData[5], Queue2_UInt8_14.io.deq.bits connect remapVecValids[5], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_4512 = eq(UInt<4>(0hf), remapindex_5) when _T_4512 : connect remapVecData[5], Queue2_UInt8_15.io.deq.bits connect remapVecValids[5], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_4513 = eq(UInt<5>(0h10), remapindex_5) when _T_4513 : connect remapVecData[5], Queue2_UInt8_16.io.deq.bits connect remapVecValids[5], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_4514 = eq(UInt<5>(0h11), remapindex_5) when _T_4514 : connect remapVecData[5], Queue2_UInt8_17.io.deq.bits connect remapVecValids[5], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_4515 = eq(UInt<5>(0h12), remapindex_5) when _T_4515 : connect remapVecData[5], Queue2_UInt8_18.io.deq.bits connect remapVecValids[5], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_4516 = eq(UInt<5>(0h13), remapindex_5) when _T_4516 : connect remapVecData[5], Queue2_UInt8_19.io.deq.bits connect remapVecValids[5], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_4517 = eq(UInt<5>(0h14), remapindex_5) when _T_4517 : connect remapVecData[5], Queue2_UInt8_20.io.deq.bits connect remapVecValids[5], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_4518 = eq(UInt<5>(0h15), remapindex_5) when _T_4518 : connect remapVecData[5], Queue2_UInt8_21.io.deq.bits connect remapVecValids[5], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_4519 = eq(UInt<5>(0h16), remapindex_5) when _T_4519 : connect remapVecData[5], Queue2_UInt8_22.io.deq.bits connect remapVecValids[5], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_4520 = eq(UInt<5>(0h17), remapindex_5) when _T_4520 : connect remapVecData[5], Queue2_UInt8_23.io.deq.bits connect remapVecValids[5], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_4521 = eq(UInt<5>(0h18), remapindex_5) when _T_4521 : connect remapVecData[5], Queue2_UInt8_24.io.deq.bits connect remapVecValids[5], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_4522 = eq(UInt<5>(0h19), remapindex_5) when _T_4522 : connect remapVecData[5], Queue2_UInt8_25.io.deq.bits connect remapVecValids[5], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_4523 = eq(UInt<5>(0h1a), remapindex_5) when _T_4523 : connect remapVecData[5], Queue2_UInt8_26.io.deq.bits connect remapVecValids[5], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_4524 = eq(UInt<5>(0h1b), remapindex_5) when _T_4524 : connect remapVecData[5], Queue2_UInt8_27.io.deq.bits connect remapVecValids[5], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_4525 = eq(UInt<5>(0h1c), remapindex_5) when _T_4525 : connect remapVecData[5], Queue2_UInt8_28.io.deq.bits connect remapVecValids[5], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_4526 = eq(UInt<5>(0h1d), remapindex_5) when _T_4526 : connect remapVecData[5], Queue2_UInt8_29.io.deq.bits connect remapVecValids[5], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_4527 = eq(UInt<5>(0h1e), remapindex_5) when _T_4527 : connect remapVecData[5], Queue2_UInt8_30.io.deq.bits connect remapVecValids[5], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_4528 = eq(UInt<5>(0h1f), remapindex_5) when _T_4528 : connect remapVecData[5], Queue2_UInt8_31.io.deq.bits connect remapVecValids[5], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_4529 = eq(UInt<1>(0h0), remapindex_6) when _T_4529 : connect remapVecData[6], Queue2_UInt8.io.deq.bits connect remapVecValids[6], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[6] node _T_4530 = eq(UInt<1>(0h1), remapindex_6) when _T_4530 : connect remapVecData[6], Queue2_UInt8_1.io.deq.bits connect remapVecValids[6], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_4531 = eq(UInt<2>(0h2), remapindex_6) when _T_4531 : connect remapVecData[6], Queue2_UInt8_2.io.deq.bits connect remapVecValids[6], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_4532 = eq(UInt<2>(0h3), remapindex_6) when _T_4532 : connect remapVecData[6], Queue2_UInt8_3.io.deq.bits connect remapVecValids[6], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_4533 = eq(UInt<3>(0h4), remapindex_6) when _T_4533 : connect remapVecData[6], Queue2_UInt8_4.io.deq.bits connect remapVecValids[6], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_4534 = eq(UInt<3>(0h5), remapindex_6) when _T_4534 : connect remapVecData[6], Queue2_UInt8_5.io.deq.bits connect remapVecValids[6], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_4535 = eq(UInt<3>(0h6), remapindex_6) when _T_4535 : connect remapVecData[6], Queue2_UInt8_6.io.deq.bits connect remapVecValids[6], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_4536 = eq(UInt<3>(0h7), remapindex_6) when _T_4536 : connect remapVecData[6], Queue2_UInt8_7.io.deq.bits connect remapVecValids[6], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_4537 = eq(UInt<4>(0h8), remapindex_6) when _T_4537 : connect remapVecData[6], Queue2_UInt8_8.io.deq.bits connect remapVecValids[6], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_4538 = eq(UInt<4>(0h9), remapindex_6) when _T_4538 : connect remapVecData[6], Queue2_UInt8_9.io.deq.bits connect remapVecValids[6], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_4539 = eq(UInt<4>(0ha), remapindex_6) when _T_4539 : connect remapVecData[6], Queue2_UInt8_10.io.deq.bits connect remapVecValids[6], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_4540 = eq(UInt<4>(0hb), remapindex_6) when _T_4540 : connect remapVecData[6], Queue2_UInt8_11.io.deq.bits connect remapVecValids[6], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_4541 = eq(UInt<4>(0hc), remapindex_6) when _T_4541 : connect remapVecData[6], Queue2_UInt8_12.io.deq.bits connect remapVecValids[6], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_4542 = eq(UInt<4>(0hd), remapindex_6) when _T_4542 : connect remapVecData[6], Queue2_UInt8_13.io.deq.bits connect remapVecValids[6], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_4543 = eq(UInt<4>(0he), remapindex_6) when _T_4543 : connect remapVecData[6], Queue2_UInt8_14.io.deq.bits connect remapVecValids[6], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_4544 = eq(UInt<4>(0hf), remapindex_6) when _T_4544 : connect remapVecData[6], Queue2_UInt8_15.io.deq.bits connect remapVecValids[6], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_4545 = eq(UInt<5>(0h10), remapindex_6) when _T_4545 : connect remapVecData[6], Queue2_UInt8_16.io.deq.bits connect remapVecValids[6], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_4546 = eq(UInt<5>(0h11), remapindex_6) when _T_4546 : connect remapVecData[6], Queue2_UInt8_17.io.deq.bits connect remapVecValids[6], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_4547 = eq(UInt<5>(0h12), remapindex_6) when _T_4547 : connect remapVecData[6], Queue2_UInt8_18.io.deq.bits connect remapVecValids[6], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_4548 = eq(UInt<5>(0h13), remapindex_6) when _T_4548 : connect remapVecData[6], Queue2_UInt8_19.io.deq.bits connect remapVecValids[6], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_4549 = eq(UInt<5>(0h14), remapindex_6) when _T_4549 : connect remapVecData[6], Queue2_UInt8_20.io.deq.bits connect remapVecValids[6], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_4550 = eq(UInt<5>(0h15), remapindex_6) when _T_4550 : connect remapVecData[6], Queue2_UInt8_21.io.deq.bits connect remapVecValids[6], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_4551 = eq(UInt<5>(0h16), remapindex_6) when _T_4551 : connect remapVecData[6], Queue2_UInt8_22.io.deq.bits connect remapVecValids[6], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_4552 = eq(UInt<5>(0h17), remapindex_6) when _T_4552 : connect remapVecData[6], Queue2_UInt8_23.io.deq.bits connect remapVecValids[6], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_4553 = eq(UInt<5>(0h18), remapindex_6) when _T_4553 : connect remapVecData[6], Queue2_UInt8_24.io.deq.bits connect remapVecValids[6], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_4554 = eq(UInt<5>(0h19), remapindex_6) when _T_4554 : connect remapVecData[6], Queue2_UInt8_25.io.deq.bits connect remapVecValids[6], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_4555 = eq(UInt<5>(0h1a), remapindex_6) when _T_4555 : connect remapVecData[6], Queue2_UInt8_26.io.deq.bits connect remapVecValids[6], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_4556 = eq(UInt<5>(0h1b), remapindex_6) when _T_4556 : connect remapVecData[6], Queue2_UInt8_27.io.deq.bits connect remapVecValids[6], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_4557 = eq(UInt<5>(0h1c), remapindex_6) when _T_4557 : connect remapVecData[6], Queue2_UInt8_28.io.deq.bits connect remapVecValids[6], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_4558 = eq(UInt<5>(0h1d), remapindex_6) when _T_4558 : connect remapVecData[6], Queue2_UInt8_29.io.deq.bits connect remapVecValids[6], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_4559 = eq(UInt<5>(0h1e), remapindex_6) when _T_4559 : connect remapVecData[6], Queue2_UInt8_30.io.deq.bits connect remapVecValids[6], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_4560 = eq(UInt<5>(0h1f), remapindex_6) when _T_4560 : connect remapVecData[6], Queue2_UInt8_31.io.deq.bits connect remapVecValids[6], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_4561 = eq(UInt<1>(0h0), remapindex_7) when _T_4561 : connect remapVecData[7], Queue2_UInt8.io.deq.bits connect remapVecValids[7], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[7] node _T_4562 = eq(UInt<1>(0h1), remapindex_7) when _T_4562 : connect remapVecData[7], Queue2_UInt8_1.io.deq.bits connect remapVecValids[7], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_4563 = eq(UInt<2>(0h2), remapindex_7) when _T_4563 : connect remapVecData[7], Queue2_UInt8_2.io.deq.bits connect remapVecValids[7], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_4564 = eq(UInt<2>(0h3), remapindex_7) when _T_4564 : connect remapVecData[7], Queue2_UInt8_3.io.deq.bits connect remapVecValids[7], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_4565 = eq(UInt<3>(0h4), remapindex_7) when _T_4565 : connect remapVecData[7], Queue2_UInt8_4.io.deq.bits connect remapVecValids[7], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_4566 = eq(UInt<3>(0h5), remapindex_7) when _T_4566 : connect remapVecData[7], Queue2_UInt8_5.io.deq.bits connect remapVecValids[7], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_4567 = eq(UInt<3>(0h6), remapindex_7) when _T_4567 : connect remapVecData[7], Queue2_UInt8_6.io.deq.bits connect remapVecValids[7], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_4568 = eq(UInt<3>(0h7), remapindex_7) when _T_4568 : connect remapVecData[7], Queue2_UInt8_7.io.deq.bits connect remapVecValids[7], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_4569 = eq(UInt<4>(0h8), remapindex_7) when _T_4569 : connect remapVecData[7], Queue2_UInt8_8.io.deq.bits connect remapVecValids[7], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_4570 = eq(UInt<4>(0h9), remapindex_7) when _T_4570 : connect remapVecData[7], Queue2_UInt8_9.io.deq.bits connect remapVecValids[7], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_4571 = eq(UInt<4>(0ha), remapindex_7) when _T_4571 : connect remapVecData[7], Queue2_UInt8_10.io.deq.bits connect remapVecValids[7], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_4572 = eq(UInt<4>(0hb), remapindex_7) when _T_4572 : connect remapVecData[7], Queue2_UInt8_11.io.deq.bits connect remapVecValids[7], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_4573 = eq(UInt<4>(0hc), remapindex_7) when _T_4573 : connect remapVecData[7], Queue2_UInt8_12.io.deq.bits connect remapVecValids[7], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_4574 = eq(UInt<4>(0hd), remapindex_7) when _T_4574 : connect remapVecData[7], Queue2_UInt8_13.io.deq.bits connect remapVecValids[7], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_4575 = eq(UInt<4>(0he), remapindex_7) when _T_4575 : connect remapVecData[7], Queue2_UInt8_14.io.deq.bits connect remapVecValids[7], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_4576 = eq(UInt<4>(0hf), remapindex_7) when _T_4576 : connect remapVecData[7], Queue2_UInt8_15.io.deq.bits connect remapVecValids[7], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_4577 = eq(UInt<5>(0h10), remapindex_7) when _T_4577 : connect remapVecData[7], Queue2_UInt8_16.io.deq.bits connect remapVecValids[7], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_4578 = eq(UInt<5>(0h11), remapindex_7) when _T_4578 : connect remapVecData[7], Queue2_UInt8_17.io.deq.bits connect remapVecValids[7], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_4579 = eq(UInt<5>(0h12), remapindex_7) when _T_4579 : connect remapVecData[7], Queue2_UInt8_18.io.deq.bits connect remapVecValids[7], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_4580 = eq(UInt<5>(0h13), remapindex_7) when _T_4580 : connect remapVecData[7], Queue2_UInt8_19.io.deq.bits connect remapVecValids[7], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_4581 = eq(UInt<5>(0h14), remapindex_7) when _T_4581 : connect remapVecData[7], Queue2_UInt8_20.io.deq.bits connect remapVecValids[7], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_4582 = eq(UInt<5>(0h15), remapindex_7) when _T_4582 : connect remapVecData[7], Queue2_UInt8_21.io.deq.bits connect remapVecValids[7], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_4583 = eq(UInt<5>(0h16), remapindex_7) when _T_4583 : connect remapVecData[7], Queue2_UInt8_22.io.deq.bits connect remapVecValids[7], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_4584 = eq(UInt<5>(0h17), remapindex_7) when _T_4584 : connect remapVecData[7], Queue2_UInt8_23.io.deq.bits connect remapVecValids[7], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_4585 = eq(UInt<5>(0h18), remapindex_7) when _T_4585 : connect remapVecData[7], Queue2_UInt8_24.io.deq.bits connect remapVecValids[7], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_4586 = eq(UInt<5>(0h19), remapindex_7) when _T_4586 : connect remapVecData[7], Queue2_UInt8_25.io.deq.bits connect remapVecValids[7], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_4587 = eq(UInt<5>(0h1a), remapindex_7) when _T_4587 : connect remapVecData[7], Queue2_UInt8_26.io.deq.bits connect remapVecValids[7], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_4588 = eq(UInt<5>(0h1b), remapindex_7) when _T_4588 : connect remapVecData[7], Queue2_UInt8_27.io.deq.bits connect remapVecValids[7], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_4589 = eq(UInt<5>(0h1c), remapindex_7) when _T_4589 : connect remapVecData[7], Queue2_UInt8_28.io.deq.bits connect remapVecValids[7], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_4590 = eq(UInt<5>(0h1d), remapindex_7) when _T_4590 : connect remapVecData[7], Queue2_UInt8_29.io.deq.bits connect remapVecValids[7], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_4591 = eq(UInt<5>(0h1e), remapindex_7) when _T_4591 : connect remapVecData[7], Queue2_UInt8_30.io.deq.bits connect remapVecValids[7], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_4592 = eq(UInt<5>(0h1f), remapindex_7) when _T_4592 : connect remapVecData[7], Queue2_UInt8_31.io.deq.bits connect remapVecValids[7], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_4593 = eq(UInt<1>(0h0), remapindex_8) when _T_4593 : connect remapVecData[8], Queue2_UInt8.io.deq.bits connect remapVecValids[8], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[8] node _T_4594 = eq(UInt<1>(0h1), remapindex_8) when _T_4594 : connect remapVecData[8], Queue2_UInt8_1.io.deq.bits connect remapVecValids[8], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_4595 = eq(UInt<2>(0h2), remapindex_8) when _T_4595 : connect remapVecData[8], Queue2_UInt8_2.io.deq.bits connect remapVecValids[8], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_4596 = eq(UInt<2>(0h3), remapindex_8) when _T_4596 : connect remapVecData[8], Queue2_UInt8_3.io.deq.bits connect remapVecValids[8], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_4597 = eq(UInt<3>(0h4), remapindex_8) when _T_4597 : connect remapVecData[8], Queue2_UInt8_4.io.deq.bits connect remapVecValids[8], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_4598 = eq(UInt<3>(0h5), remapindex_8) when _T_4598 : connect remapVecData[8], Queue2_UInt8_5.io.deq.bits connect remapVecValids[8], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_4599 = eq(UInt<3>(0h6), remapindex_8) when _T_4599 : connect remapVecData[8], Queue2_UInt8_6.io.deq.bits connect remapVecValids[8], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_4600 = eq(UInt<3>(0h7), remapindex_8) when _T_4600 : connect remapVecData[8], Queue2_UInt8_7.io.deq.bits connect remapVecValids[8], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_4601 = eq(UInt<4>(0h8), remapindex_8) when _T_4601 : connect remapVecData[8], Queue2_UInt8_8.io.deq.bits connect remapVecValids[8], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_4602 = eq(UInt<4>(0h9), remapindex_8) when _T_4602 : connect remapVecData[8], Queue2_UInt8_9.io.deq.bits connect remapVecValids[8], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_4603 = eq(UInt<4>(0ha), remapindex_8) when _T_4603 : connect remapVecData[8], Queue2_UInt8_10.io.deq.bits connect remapVecValids[8], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_4604 = eq(UInt<4>(0hb), remapindex_8) when _T_4604 : connect remapVecData[8], Queue2_UInt8_11.io.deq.bits connect remapVecValids[8], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_4605 = eq(UInt<4>(0hc), remapindex_8) when _T_4605 : connect remapVecData[8], Queue2_UInt8_12.io.deq.bits connect remapVecValids[8], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_4606 = eq(UInt<4>(0hd), remapindex_8) when _T_4606 : connect remapVecData[8], Queue2_UInt8_13.io.deq.bits connect remapVecValids[8], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_4607 = eq(UInt<4>(0he), remapindex_8) when _T_4607 : connect remapVecData[8], Queue2_UInt8_14.io.deq.bits connect remapVecValids[8], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_4608 = eq(UInt<4>(0hf), remapindex_8) when _T_4608 : connect remapVecData[8], Queue2_UInt8_15.io.deq.bits connect remapVecValids[8], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_4609 = eq(UInt<5>(0h10), remapindex_8) when _T_4609 : connect remapVecData[8], Queue2_UInt8_16.io.deq.bits connect remapVecValids[8], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_4610 = eq(UInt<5>(0h11), remapindex_8) when _T_4610 : connect remapVecData[8], Queue2_UInt8_17.io.deq.bits connect remapVecValids[8], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_4611 = eq(UInt<5>(0h12), remapindex_8) when _T_4611 : connect remapVecData[8], Queue2_UInt8_18.io.deq.bits connect remapVecValids[8], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_4612 = eq(UInt<5>(0h13), remapindex_8) when _T_4612 : connect remapVecData[8], Queue2_UInt8_19.io.deq.bits connect remapVecValids[8], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_4613 = eq(UInt<5>(0h14), remapindex_8) when _T_4613 : connect remapVecData[8], Queue2_UInt8_20.io.deq.bits connect remapVecValids[8], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_4614 = eq(UInt<5>(0h15), remapindex_8) when _T_4614 : connect remapVecData[8], Queue2_UInt8_21.io.deq.bits connect remapVecValids[8], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_4615 = eq(UInt<5>(0h16), remapindex_8) when _T_4615 : connect remapVecData[8], Queue2_UInt8_22.io.deq.bits connect remapVecValids[8], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_4616 = eq(UInt<5>(0h17), remapindex_8) when _T_4616 : connect remapVecData[8], Queue2_UInt8_23.io.deq.bits connect remapVecValids[8], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_4617 = eq(UInt<5>(0h18), remapindex_8) when _T_4617 : connect remapVecData[8], Queue2_UInt8_24.io.deq.bits connect remapVecValids[8], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_4618 = eq(UInt<5>(0h19), remapindex_8) when _T_4618 : connect remapVecData[8], Queue2_UInt8_25.io.deq.bits connect remapVecValids[8], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_4619 = eq(UInt<5>(0h1a), remapindex_8) when _T_4619 : connect remapVecData[8], Queue2_UInt8_26.io.deq.bits connect remapVecValids[8], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_4620 = eq(UInt<5>(0h1b), remapindex_8) when _T_4620 : connect remapVecData[8], Queue2_UInt8_27.io.deq.bits connect remapVecValids[8], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_4621 = eq(UInt<5>(0h1c), remapindex_8) when _T_4621 : connect remapVecData[8], Queue2_UInt8_28.io.deq.bits connect remapVecValids[8], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_4622 = eq(UInt<5>(0h1d), remapindex_8) when _T_4622 : connect remapVecData[8], Queue2_UInt8_29.io.deq.bits connect remapVecValids[8], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_4623 = eq(UInt<5>(0h1e), remapindex_8) when _T_4623 : connect remapVecData[8], Queue2_UInt8_30.io.deq.bits connect remapVecValids[8], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_4624 = eq(UInt<5>(0h1f), remapindex_8) when _T_4624 : connect remapVecData[8], Queue2_UInt8_31.io.deq.bits connect remapVecValids[8], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_4625 = eq(UInt<1>(0h0), remapindex_9) when _T_4625 : connect remapVecData[9], Queue2_UInt8.io.deq.bits connect remapVecValids[9], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[9] node _T_4626 = eq(UInt<1>(0h1), remapindex_9) when _T_4626 : connect remapVecData[9], Queue2_UInt8_1.io.deq.bits connect remapVecValids[9], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_4627 = eq(UInt<2>(0h2), remapindex_9) when _T_4627 : connect remapVecData[9], Queue2_UInt8_2.io.deq.bits connect remapVecValids[9], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_4628 = eq(UInt<2>(0h3), remapindex_9) when _T_4628 : connect remapVecData[9], Queue2_UInt8_3.io.deq.bits connect remapVecValids[9], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_4629 = eq(UInt<3>(0h4), remapindex_9) when _T_4629 : connect remapVecData[9], Queue2_UInt8_4.io.deq.bits connect remapVecValids[9], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_4630 = eq(UInt<3>(0h5), remapindex_9) when _T_4630 : connect remapVecData[9], Queue2_UInt8_5.io.deq.bits connect remapVecValids[9], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_4631 = eq(UInt<3>(0h6), remapindex_9) when _T_4631 : connect remapVecData[9], Queue2_UInt8_6.io.deq.bits connect remapVecValids[9], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_4632 = eq(UInt<3>(0h7), remapindex_9) when _T_4632 : connect remapVecData[9], Queue2_UInt8_7.io.deq.bits connect remapVecValids[9], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_4633 = eq(UInt<4>(0h8), remapindex_9) when _T_4633 : connect remapVecData[9], Queue2_UInt8_8.io.deq.bits connect remapVecValids[9], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_4634 = eq(UInt<4>(0h9), remapindex_9) when _T_4634 : connect remapVecData[9], Queue2_UInt8_9.io.deq.bits connect remapVecValids[9], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_4635 = eq(UInt<4>(0ha), remapindex_9) when _T_4635 : connect remapVecData[9], Queue2_UInt8_10.io.deq.bits connect remapVecValids[9], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_4636 = eq(UInt<4>(0hb), remapindex_9) when _T_4636 : connect remapVecData[9], Queue2_UInt8_11.io.deq.bits connect remapVecValids[9], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_4637 = eq(UInt<4>(0hc), remapindex_9) when _T_4637 : connect remapVecData[9], Queue2_UInt8_12.io.deq.bits connect remapVecValids[9], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_4638 = eq(UInt<4>(0hd), remapindex_9) when _T_4638 : connect remapVecData[9], Queue2_UInt8_13.io.deq.bits connect remapVecValids[9], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_4639 = eq(UInt<4>(0he), remapindex_9) when _T_4639 : connect remapVecData[9], Queue2_UInt8_14.io.deq.bits connect remapVecValids[9], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_4640 = eq(UInt<4>(0hf), remapindex_9) when _T_4640 : connect remapVecData[9], Queue2_UInt8_15.io.deq.bits connect remapVecValids[9], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_4641 = eq(UInt<5>(0h10), remapindex_9) when _T_4641 : connect remapVecData[9], Queue2_UInt8_16.io.deq.bits connect remapVecValids[9], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_4642 = eq(UInt<5>(0h11), remapindex_9) when _T_4642 : connect remapVecData[9], Queue2_UInt8_17.io.deq.bits connect remapVecValids[9], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_4643 = eq(UInt<5>(0h12), remapindex_9) when _T_4643 : connect remapVecData[9], Queue2_UInt8_18.io.deq.bits connect remapVecValids[9], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_4644 = eq(UInt<5>(0h13), remapindex_9) when _T_4644 : connect remapVecData[9], Queue2_UInt8_19.io.deq.bits connect remapVecValids[9], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_4645 = eq(UInt<5>(0h14), remapindex_9) when _T_4645 : connect remapVecData[9], Queue2_UInt8_20.io.deq.bits connect remapVecValids[9], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_4646 = eq(UInt<5>(0h15), remapindex_9) when _T_4646 : connect remapVecData[9], Queue2_UInt8_21.io.deq.bits connect remapVecValids[9], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_4647 = eq(UInt<5>(0h16), remapindex_9) when _T_4647 : connect remapVecData[9], Queue2_UInt8_22.io.deq.bits connect remapVecValids[9], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_4648 = eq(UInt<5>(0h17), remapindex_9) when _T_4648 : connect remapVecData[9], Queue2_UInt8_23.io.deq.bits connect remapVecValids[9], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_4649 = eq(UInt<5>(0h18), remapindex_9) when _T_4649 : connect remapVecData[9], Queue2_UInt8_24.io.deq.bits connect remapVecValids[9], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_4650 = eq(UInt<5>(0h19), remapindex_9) when _T_4650 : connect remapVecData[9], Queue2_UInt8_25.io.deq.bits connect remapVecValids[9], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_4651 = eq(UInt<5>(0h1a), remapindex_9) when _T_4651 : connect remapVecData[9], Queue2_UInt8_26.io.deq.bits connect remapVecValids[9], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_4652 = eq(UInt<5>(0h1b), remapindex_9) when _T_4652 : connect remapVecData[9], Queue2_UInt8_27.io.deq.bits connect remapVecValids[9], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_4653 = eq(UInt<5>(0h1c), remapindex_9) when _T_4653 : connect remapVecData[9], Queue2_UInt8_28.io.deq.bits connect remapVecValids[9], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_4654 = eq(UInt<5>(0h1d), remapindex_9) when _T_4654 : connect remapVecData[9], Queue2_UInt8_29.io.deq.bits connect remapVecValids[9], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_4655 = eq(UInt<5>(0h1e), remapindex_9) when _T_4655 : connect remapVecData[9], Queue2_UInt8_30.io.deq.bits connect remapVecValids[9], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_4656 = eq(UInt<5>(0h1f), remapindex_9) when _T_4656 : connect remapVecData[9], Queue2_UInt8_31.io.deq.bits connect remapVecValids[9], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_4657 = eq(UInt<1>(0h0), remapindex_10) when _T_4657 : connect remapVecData[10], Queue2_UInt8.io.deq.bits connect remapVecValids[10], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[10] node _T_4658 = eq(UInt<1>(0h1), remapindex_10) when _T_4658 : connect remapVecData[10], Queue2_UInt8_1.io.deq.bits connect remapVecValids[10], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_4659 = eq(UInt<2>(0h2), remapindex_10) when _T_4659 : connect remapVecData[10], Queue2_UInt8_2.io.deq.bits connect remapVecValids[10], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_4660 = eq(UInt<2>(0h3), remapindex_10) when _T_4660 : connect remapVecData[10], Queue2_UInt8_3.io.deq.bits connect remapVecValids[10], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_4661 = eq(UInt<3>(0h4), remapindex_10) when _T_4661 : connect remapVecData[10], Queue2_UInt8_4.io.deq.bits connect remapVecValids[10], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_4662 = eq(UInt<3>(0h5), remapindex_10) when _T_4662 : connect remapVecData[10], Queue2_UInt8_5.io.deq.bits connect remapVecValids[10], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_4663 = eq(UInt<3>(0h6), remapindex_10) when _T_4663 : connect remapVecData[10], Queue2_UInt8_6.io.deq.bits connect remapVecValids[10], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_4664 = eq(UInt<3>(0h7), remapindex_10) when _T_4664 : connect remapVecData[10], Queue2_UInt8_7.io.deq.bits connect remapVecValids[10], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_4665 = eq(UInt<4>(0h8), remapindex_10) when _T_4665 : connect remapVecData[10], Queue2_UInt8_8.io.deq.bits connect remapVecValids[10], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_4666 = eq(UInt<4>(0h9), remapindex_10) when _T_4666 : connect remapVecData[10], Queue2_UInt8_9.io.deq.bits connect remapVecValids[10], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_4667 = eq(UInt<4>(0ha), remapindex_10) when _T_4667 : connect remapVecData[10], Queue2_UInt8_10.io.deq.bits connect remapVecValids[10], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_4668 = eq(UInt<4>(0hb), remapindex_10) when _T_4668 : connect remapVecData[10], Queue2_UInt8_11.io.deq.bits connect remapVecValids[10], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_4669 = eq(UInt<4>(0hc), remapindex_10) when _T_4669 : connect remapVecData[10], Queue2_UInt8_12.io.deq.bits connect remapVecValids[10], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_4670 = eq(UInt<4>(0hd), remapindex_10) when _T_4670 : connect remapVecData[10], Queue2_UInt8_13.io.deq.bits connect remapVecValids[10], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_4671 = eq(UInt<4>(0he), remapindex_10) when _T_4671 : connect remapVecData[10], Queue2_UInt8_14.io.deq.bits connect remapVecValids[10], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_4672 = eq(UInt<4>(0hf), remapindex_10) when _T_4672 : connect remapVecData[10], Queue2_UInt8_15.io.deq.bits connect remapVecValids[10], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_4673 = eq(UInt<5>(0h10), remapindex_10) when _T_4673 : connect remapVecData[10], Queue2_UInt8_16.io.deq.bits connect remapVecValids[10], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_4674 = eq(UInt<5>(0h11), remapindex_10) when _T_4674 : connect remapVecData[10], Queue2_UInt8_17.io.deq.bits connect remapVecValids[10], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_4675 = eq(UInt<5>(0h12), remapindex_10) when _T_4675 : connect remapVecData[10], Queue2_UInt8_18.io.deq.bits connect remapVecValids[10], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_4676 = eq(UInt<5>(0h13), remapindex_10) when _T_4676 : connect remapVecData[10], Queue2_UInt8_19.io.deq.bits connect remapVecValids[10], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_4677 = eq(UInt<5>(0h14), remapindex_10) when _T_4677 : connect remapVecData[10], Queue2_UInt8_20.io.deq.bits connect remapVecValids[10], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_4678 = eq(UInt<5>(0h15), remapindex_10) when _T_4678 : connect remapVecData[10], Queue2_UInt8_21.io.deq.bits connect remapVecValids[10], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_4679 = eq(UInt<5>(0h16), remapindex_10) when _T_4679 : connect remapVecData[10], Queue2_UInt8_22.io.deq.bits connect remapVecValids[10], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_4680 = eq(UInt<5>(0h17), remapindex_10) when _T_4680 : connect remapVecData[10], Queue2_UInt8_23.io.deq.bits connect remapVecValids[10], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_4681 = eq(UInt<5>(0h18), remapindex_10) when _T_4681 : connect remapVecData[10], Queue2_UInt8_24.io.deq.bits connect remapVecValids[10], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_4682 = eq(UInt<5>(0h19), remapindex_10) when _T_4682 : connect remapVecData[10], Queue2_UInt8_25.io.deq.bits connect remapVecValids[10], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_4683 = eq(UInt<5>(0h1a), remapindex_10) when _T_4683 : connect remapVecData[10], Queue2_UInt8_26.io.deq.bits connect remapVecValids[10], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_4684 = eq(UInt<5>(0h1b), remapindex_10) when _T_4684 : connect remapVecData[10], Queue2_UInt8_27.io.deq.bits connect remapVecValids[10], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_4685 = eq(UInt<5>(0h1c), remapindex_10) when _T_4685 : connect remapVecData[10], Queue2_UInt8_28.io.deq.bits connect remapVecValids[10], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_4686 = eq(UInt<5>(0h1d), remapindex_10) when _T_4686 : connect remapVecData[10], Queue2_UInt8_29.io.deq.bits connect remapVecValids[10], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_4687 = eq(UInt<5>(0h1e), remapindex_10) when _T_4687 : connect remapVecData[10], Queue2_UInt8_30.io.deq.bits connect remapVecValids[10], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_4688 = eq(UInt<5>(0h1f), remapindex_10) when _T_4688 : connect remapVecData[10], Queue2_UInt8_31.io.deq.bits connect remapVecValids[10], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_4689 = eq(UInt<1>(0h0), remapindex_11) when _T_4689 : connect remapVecData[11], Queue2_UInt8.io.deq.bits connect remapVecValids[11], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[11] node _T_4690 = eq(UInt<1>(0h1), remapindex_11) when _T_4690 : connect remapVecData[11], Queue2_UInt8_1.io.deq.bits connect remapVecValids[11], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_4691 = eq(UInt<2>(0h2), remapindex_11) when _T_4691 : connect remapVecData[11], Queue2_UInt8_2.io.deq.bits connect remapVecValids[11], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_4692 = eq(UInt<2>(0h3), remapindex_11) when _T_4692 : connect remapVecData[11], Queue2_UInt8_3.io.deq.bits connect remapVecValids[11], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_4693 = eq(UInt<3>(0h4), remapindex_11) when _T_4693 : connect remapVecData[11], Queue2_UInt8_4.io.deq.bits connect remapVecValids[11], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_4694 = eq(UInt<3>(0h5), remapindex_11) when _T_4694 : connect remapVecData[11], Queue2_UInt8_5.io.deq.bits connect remapVecValids[11], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_4695 = eq(UInt<3>(0h6), remapindex_11) when _T_4695 : connect remapVecData[11], Queue2_UInt8_6.io.deq.bits connect remapVecValids[11], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_4696 = eq(UInt<3>(0h7), remapindex_11) when _T_4696 : connect remapVecData[11], Queue2_UInt8_7.io.deq.bits connect remapVecValids[11], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_4697 = eq(UInt<4>(0h8), remapindex_11) when _T_4697 : connect remapVecData[11], Queue2_UInt8_8.io.deq.bits connect remapVecValids[11], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_4698 = eq(UInt<4>(0h9), remapindex_11) when _T_4698 : connect remapVecData[11], Queue2_UInt8_9.io.deq.bits connect remapVecValids[11], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_4699 = eq(UInt<4>(0ha), remapindex_11) when _T_4699 : connect remapVecData[11], Queue2_UInt8_10.io.deq.bits connect remapVecValids[11], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_4700 = eq(UInt<4>(0hb), remapindex_11) when _T_4700 : connect remapVecData[11], Queue2_UInt8_11.io.deq.bits connect remapVecValids[11], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_4701 = eq(UInt<4>(0hc), remapindex_11) when _T_4701 : connect remapVecData[11], Queue2_UInt8_12.io.deq.bits connect remapVecValids[11], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_4702 = eq(UInt<4>(0hd), remapindex_11) when _T_4702 : connect remapVecData[11], Queue2_UInt8_13.io.deq.bits connect remapVecValids[11], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_4703 = eq(UInt<4>(0he), remapindex_11) when _T_4703 : connect remapVecData[11], Queue2_UInt8_14.io.deq.bits connect remapVecValids[11], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_4704 = eq(UInt<4>(0hf), remapindex_11) when _T_4704 : connect remapVecData[11], Queue2_UInt8_15.io.deq.bits connect remapVecValids[11], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_4705 = eq(UInt<5>(0h10), remapindex_11) when _T_4705 : connect remapVecData[11], Queue2_UInt8_16.io.deq.bits connect remapVecValids[11], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_4706 = eq(UInt<5>(0h11), remapindex_11) when _T_4706 : connect remapVecData[11], Queue2_UInt8_17.io.deq.bits connect remapVecValids[11], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_4707 = eq(UInt<5>(0h12), remapindex_11) when _T_4707 : connect remapVecData[11], Queue2_UInt8_18.io.deq.bits connect remapVecValids[11], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_4708 = eq(UInt<5>(0h13), remapindex_11) when _T_4708 : connect remapVecData[11], Queue2_UInt8_19.io.deq.bits connect remapVecValids[11], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_4709 = eq(UInt<5>(0h14), remapindex_11) when _T_4709 : connect remapVecData[11], Queue2_UInt8_20.io.deq.bits connect remapVecValids[11], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_4710 = eq(UInt<5>(0h15), remapindex_11) when _T_4710 : connect remapVecData[11], Queue2_UInt8_21.io.deq.bits connect remapVecValids[11], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_4711 = eq(UInt<5>(0h16), remapindex_11) when _T_4711 : connect remapVecData[11], Queue2_UInt8_22.io.deq.bits connect remapVecValids[11], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_4712 = eq(UInt<5>(0h17), remapindex_11) when _T_4712 : connect remapVecData[11], Queue2_UInt8_23.io.deq.bits connect remapVecValids[11], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_4713 = eq(UInt<5>(0h18), remapindex_11) when _T_4713 : connect remapVecData[11], Queue2_UInt8_24.io.deq.bits connect remapVecValids[11], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_4714 = eq(UInt<5>(0h19), remapindex_11) when _T_4714 : connect remapVecData[11], Queue2_UInt8_25.io.deq.bits connect remapVecValids[11], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_4715 = eq(UInt<5>(0h1a), remapindex_11) when _T_4715 : connect remapVecData[11], Queue2_UInt8_26.io.deq.bits connect remapVecValids[11], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_4716 = eq(UInt<5>(0h1b), remapindex_11) when _T_4716 : connect remapVecData[11], Queue2_UInt8_27.io.deq.bits connect remapVecValids[11], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_4717 = eq(UInt<5>(0h1c), remapindex_11) when _T_4717 : connect remapVecData[11], Queue2_UInt8_28.io.deq.bits connect remapVecValids[11], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_4718 = eq(UInt<5>(0h1d), remapindex_11) when _T_4718 : connect remapVecData[11], Queue2_UInt8_29.io.deq.bits connect remapVecValids[11], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_4719 = eq(UInt<5>(0h1e), remapindex_11) when _T_4719 : connect remapVecData[11], Queue2_UInt8_30.io.deq.bits connect remapVecValids[11], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_4720 = eq(UInt<5>(0h1f), remapindex_11) when _T_4720 : connect remapVecData[11], Queue2_UInt8_31.io.deq.bits connect remapVecValids[11], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_4721 = eq(UInt<1>(0h0), remapindex_12) when _T_4721 : connect remapVecData[12], Queue2_UInt8.io.deq.bits connect remapVecValids[12], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[12] node _T_4722 = eq(UInt<1>(0h1), remapindex_12) when _T_4722 : connect remapVecData[12], Queue2_UInt8_1.io.deq.bits connect remapVecValids[12], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_4723 = eq(UInt<2>(0h2), remapindex_12) when _T_4723 : connect remapVecData[12], Queue2_UInt8_2.io.deq.bits connect remapVecValids[12], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_4724 = eq(UInt<2>(0h3), remapindex_12) when _T_4724 : connect remapVecData[12], Queue2_UInt8_3.io.deq.bits connect remapVecValids[12], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_4725 = eq(UInt<3>(0h4), remapindex_12) when _T_4725 : connect remapVecData[12], Queue2_UInt8_4.io.deq.bits connect remapVecValids[12], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_4726 = eq(UInt<3>(0h5), remapindex_12) when _T_4726 : connect remapVecData[12], Queue2_UInt8_5.io.deq.bits connect remapVecValids[12], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_4727 = eq(UInt<3>(0h6), remapindex_12) when _T_4727 : connect remapVecData[12], Queue2_UInt8_6.io.deq.bits connect remapVecValids[12], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_4728 = eq(UInt<3>(0h7), remapindex_12) when _T_4728 : connect remapVecData[12], Queue2_UInt8_7.io.deq.bits connect remapVecValids[12], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_4729 = eq(UInt<4>(0h8), remapindex_12) when _T_4729 : connect remapVecData[12], Queue2_UInt8_8.io.deq.bits connect remapVecValids[12], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_4730 = eq(UInt<4>(0h9), remapindex_12) when _T_4730 : connect remapVecData[12], Queue2_UInt8_9.io.deq.bits connect remapVecValids[12], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_4731 = eq(UInt<4>(0ha), remapindex_12) when _T_4731 : connect remapVecData[12], Queue2_UInt8_10.io.deq.bits connect remapVecValids[12], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_4732 = eq(UInt<4>(0hb), remapindex_12) when _T_4732 : connect remapVecData[12], Queue2_UInt8_11.io.deq.bits connect remapVecValids[12], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_4733 = eq(UInt<4>(0hc), remapindex_12) when _T_4733 : connect remapVecData[12], Queue2_UInt8_12.io.deq.bits connect remapVecValids[12], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_4734 = eq(UInt<4>(0hd), remapindex_12) when _T_4734 : connect remapVecData[12], Queue2_UInt8_13.io.deq.bits connect remapVecValids[12], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_4735 = eq(UInt<4>(0he), remapindex_12) when _T_4735 : connect remapVecData[12], Queue2_UInt8_14.io.deq.bits connect remapVecValids[12], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_4736 = eq(UInt<4>(0hf), remapindex_12) when _T_4736 : connect remapVecData[12], Queue2_UInt8_15.io.deq.bits connect remapVecValids[12], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_4737 = eq(UInt<5>(0h10), remapindex_12) when _T_4737 : connect remapVecData[12], Queue2_UInt8_16.io.deq.bits connect remapVecValids[12], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_4738 = eq(UInt<5>(0h11), remapindex_12) when _T_4738 : connect remapVecData[12], Queue2_UInt8_17.io.deq.bits connect remapVecValids[12], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_4739 = eq(UInt<5>(0h12), remapindex_12) when _T_4739 : connect remapVecData[12], Queue2_UInt8_18.io.deq.bits connect remapVecValids[12], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_4740 = eq(UInt<5>(0h13), remapindex_12) when _T_4740 : connect remapVecData[12], Queue2_UInt8_19.io.deq.bits connect remapVecValids[12], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_4741 = eq(UInt<5>(0h14), remapindex_12) when _T_4741 : connect remapVecData[12], Queue2_UInt8_20.io.deq.bits connect remapVecValids[12], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_4742 = eq(UInt<5>(0h15), remapindex_12) when _T_4742 : connect remapVecData[12], Queue2_UInt8_21.io.deq.bits connect remapVecValids[12], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_4743 = eq(UInt<5>(0h16), remapindex_12) when _T_4743 : connect remapVecData[12], Queue2_UInt8_22.io.deq.bits connect remapVecValids[12], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_4744 = eq(UInt<5>(0h17), remapindex_12) when _T_4744 : connect remapVecData[12], Queue2_UInt8_23.io.deq.bits connect remapVecValids[12], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_4745 = eq(UInt<5>(0h18), remapindex_12) when _T_4745 : connect remapVecData[12], Queue2_UInt8_24.io.deq.bits connect remapVecValids[12], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_4746 = eq(UInt<5>(0h19), remapindex_12) when _T_4746 : connect remapVecData[12], Queue2_UInt8_25.io.deq.bits connect remapVecValids[12], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_4747 = eq(UInt<5>(0h1a), remapindex_12) when _T_4747 : connect remapVecData[12], Queue2_UInt8_26.io.deq.bits connect remapVecValids[12], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_4748 = eq(UInt<5>(0h1b), remapindex_12) when _T_4748 : connect remapVecData[12], Queue2_UInt8_27.io.deq.bits connect remapVecValids[12], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_4749 = eq(UInt<5>(0h1c), remapindex_12) when _T_4749 : connect remapVecData[12], Queue2_UInt8_28.io.deq.bits connect remapVecValids[12], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_4750 = eq(UInt<5>(0h1d), remapindex_12) when _T_4750 : connect remapVecData[12], Queue2_UInt8_29.io.deq.bits connect remapVecValids[12], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_4751 = eq(UInt<5>(0h1e), remapindex_12) when _T_4751 : connect remapVecData[12], Queue2_UInt8_30.io.deq.bits connect remapVecValids[12], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_4752 = eq(UInt<5>(0h1f), remapindex_12) when _T_4752 : connect remapVecData[12], Queue2_UInt8_31.io.deq.bits connect remapVecValids[12], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_4753 = eq(UInt<1>(0h0), remapindex_13) when _T_4753 : connect remapVecData[13], Queue2_UInt8.io.deq.bits connect remapVecValids[13], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[13] node _T_4754 = eq(UInt<1>(0h1), remapindex_13) when _T_4754 : connect remapVecData[13], Queue2_UInt8_1.io.deq.bits connect remapVecValids[13], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_4755 = eq(UInt<2>(0h2), remapindex_13) when _T_4755 : connect remapVecData[13], Queue2_UInt8_2.io.deq.bits connect remapVecValids[13], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_4756 = eq(UInt<2>(0h3), remapindex_13) when _T_4756 : connect remapVecData[13], Queue2_UInt8_3.io.deq.bits connect remapVecValids[13], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_4757 = eq(UInt<3>(0h4), remapindex_13) when _T_4757 : connect remapVecData[13], Queue2_UInt8_4.io.deq.bits connect remapVecValids[13], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_4758 = eq(UInt<3>(0h5), remapindex_13) when _T_4758 : connect remapVecData[13], Queue2_UInt8_5.io.deq.bits connect remapVecValids[13], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_4759 = eq(UInt<3>(0h6), remapindex_13) when _T_4759 : connect remapVecData[13], Queue2_UInt8_6.io.deq.bits connect remapVecValids[13], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_4760 = eq(UInt<3>(0h7), remapindex_13) when _T_4760 : connect remapVecData[13], Queue2_UInt8_7.io.deq.bits connect remapVecValids[13], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_4761 = eq(UInt<4>(0h8), remapindex_13) when _T_4761 : connect remapVecData[13], Queue2_UInt8_8.io.deq.bits connect remapVecValids[13], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_4762 = eq(UInt<4>(0h9), remapindex_13) when _T_4762 : connect remapVecData[13], Queue2_UInt8_9.io.deq.bits connect remapVecValids[13], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_4763 = eq(UInt<4>(0ha), remapindex_13) when _T_4763 : connect remapVecData[13], Queue2_UInt8_10.io.deq.bits connect remapVecValids[13], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_4764 = eq(UInt<4>(0hb), remapindex_13) when _T_4764 : connect remapVecData[13], Queue2_UInt8_11.io.deq.bits connect remapVecValids[13], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_4765 = eq(UInt<4>(0hc), remapindex_13) when _T_4765 : connect remapVecData[13], Queue2_UInt8_12.io.deq.bits connect remapVecValids[13], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_4766 = eq(UInt<4>(0hd), remapindex_13) when _T_4766 : connect remapVecData[13], Queue2_UInt8_13.io.deq.bits connect remapVecValids[13], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_4767 = eq(UInt<4>(0he), remapindex_13) when _T_4767 : connect remapVecData[13], Queue2_UInt8_14.io.deq.bits connect remapVecValids[13], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_4768 = eq(UInt<4>(0hf), remapindex_13) when _T_4768 : connect remapVecData[13], Queue2_UInt8_15.io.deq.bits connect remapVecValids[13], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_4769 = eq(UInt<5>(0h10), remapindex_13) when _T_4769 : connect remapVecData[13], Queue2_UInt8_16.io.deq.bits connect remapVecValids[13], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_4770 = eq(UInt<5>(0h11), remapindex_13) when _T_4770 : connect remapVecData[13], Queue2_UInt8_17.io.deq.bits connect remapVecValids[13], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_4771 = eq(UInt<5>(0h12), remapindex_13) when _T_4771 : connect remapVecData[13], Queue2_UInt8_18.io.deq.bits connect remapVecValids[13], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_4772 = eq(UInt<5>(0h13), remapindex_13) when _T_4772 : connect remapVecData[13], Queue2_UInt8_19.io.deq.bits connect remapVecValids[13], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_4773 = eq(UInt<5>(0h14), remapindex_13) when _T_4773 : connect remapVecData[13], Queue2_UInt8_20.io.deq.bits connect remapVecValids[13], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_4774 = eq(UInt<5>(0h15), remapindex_13) when _T_4774 : connect remapVecData[13], Queue2_UInt8_21.io.deq.bits connect remapVecValids[13], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_4775 = eq(UInt<5>(0h16), remapindex_13) when _T_4775 : connect remapVecData[13], Queue2_UInt8_22.io.deq.bits connect remapVecValids[13], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_4776 = eq(UInt<5>(0h17), remapindex_13) when _T_4776 : connect remapVecData[13], Queue2_UInt8_23.io.deq.bits connect remapVecValids[13], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_4777 = eq(UInt<5>(0h18), remapindex_13) when _T_4777 : connect remapVecData[13], Queue2_UInt8_24.io.deq.bits connect remapVecValids[13], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_4778 = eq(UInt<5>(0h19), remapindex_13) when _T_4778 : connect remapVecData[13], Queue2_UInt8_25.io.deq.bits connect remapVecValids[13], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_4779 = eq(UInt<5>(0h1a), remapindex_13) when _T_4779 : connect remapVecData[13], Queue2_UInt8_26.io.deq.bits connect remapVecValids[13], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_4780 = eq(UInt<5>(0h1b), remapindex_13) when _T_4780 : connect remapVecData[13], Queue2_UInt8_27.io.deq.bits connect remapVecValids[13], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_4781 = eq(UInt<5>(0h1c), remapindex_13) when _T_4781 : connect remapVecData[13], Queue2_UInt8_28.io.deq.bits connect remapVecValids[13], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_4782 = eq(UInt<5>(0h1d), remapindex_13) when _T_4782 : connect remapVecData[13], Queue2_UInt8_29.io.deq.bits connect remapVecValids[13], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_4783 = eq(UInt<5>(0h1e), remapindex_13) when _T_4783 : connect remapVecData[13], Queue2_UInt8_30.io.deq.bits connect remapVecValids[13], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_4784 = eq(UInt<5>(0h1f), remapindex_13) when _T_4784 : connect remapVecData[13], Queue2_UInt8_31.io.deq.bits connect remapVecValids[13], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_4785 = eq(UInt<1>(0h0), remapindex_14) when _T_4785 : connect remapVecData[14], Queue2_UInt8.io.deq.bits connect remapVecValids[14], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[14] node _T_4786 = eq(UInt<1>(0h1), remapindex_14) when _T_4786 : connect remapVecData[14], Queue2_UInt8_1.io.deq.bits connect remapVecValids[14], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_4787 = eq(UInt<2>(0h2), remapindex_14) when _T_4787 : connect remapVecData[14], Queue2_UInt8_2.io.deq.bits connect remapVecValids[14], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_4788 = eq(UInt<2>(0h3), remapindex_14) when _T_4788 : connect remapVecData[14], Queue2_UInt8_3.io.deq.bits connect remapVecValids[14], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_4789 = eq(UInt<3>(0h4), remapindex_14) when _T_4789 : connect remapVecData[14], Queue2_UInt8_4.io.deq.bits connect remapVecValids[14], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_4790 = eq(UInt<3>(0h5), remapindex_14) when _T_4790 : connect remapVecData[14], Queue2_UInt8_5.io.deq.bits connect remapVecValids[14], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_4791 = eq(UInt<3>(0h6), remapindex_14) when _T_4791 : connect remapVecData[14], Queue2_UInt8_6.io.deq.bits connect remapVecValids[14], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_4792 = eq(UInt<3>(0h7), remapindex_14) when _T_4792 : connect remapVecData[14], Queue2_UInt8_7.io.deq.bits connect remapVecValids[14], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_4793 = eq(UInt<4>(0h8), remapindex_14) when _T_4793 : connect remapVecData[14], Queue2_UInt8_8.io.deq.bits connect remapVecValids[14], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_4794 = eq(UInt<4>(0h9), remapindex_14) when _T_4794 : connect remapVecData[14], Queue2_UInt8_9.io.deq.bits connect remapVecValids[14], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_4795 = eq(UInt<4>(0ha), remapindex_14) when _T_4795 : connect remapVecData[14], Queue2_UInt8_10.io.deq.bits connect remapVecValids[14], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_4796 = eq(UInt<4>(0hb), remapindex_14) when _T_4796 : connect remapVecData[14], Queue2_UInt8_11.io.deq.bits connect remapVecValids[14], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_4797 = eq(UInt<4>(0hc), remapindex_14) when _T_4797 : connect remapVecData[14], Queue2_UInt8_12.io.deq.bits connect remapVecValids[14], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_4798 = eq(UInt<4>(0hd), remapindex_14) when _T_4798 : connect remapVecData[14], Queue2_UInt8_13.io.deq.bits connect remapVecValids[14], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_4799 = eq(UInt<4>(0he), remapindex_14) when _T_4799 : connect remapVecData[14], Queue2_UInt8_14.io.deq.bits connect remapVecValids[14], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_4800 = eq(UInt<4>(0hf), remapindex_14) when _T_4800 : connect remapVecData[14], Queue2_UInt8_15.io.deq.bits connect remapVecValids[14], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_4801 = eq(UInt<5>(0h10), remapindex_14) when _T_4801 : connect remapVecData[14], Queue2_UInt8_16.io.deq.bits connect remapVecValids[14], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_4802 = eq(UInt<5>(0h11), remapindex_14) when _T_4802 : connect remapVecData[14], Queue2_UInt8_17.io.deq.bits connect remapVecValids[14], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_4803 = eq(UInt<5>(0h12), remapindex_14) when _T_4803 : connect remapVecData[14], Queue2_UInt8_18.io.deq.bits connect remapVecValids[14], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_4804 = eq(UInt<5>(0h13), remapindex_14) when _T_4804 : connect remapVecData[14], Queue2_UInt8_19.io.deq.bits connect remapVecValids[14], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_4805 = eq(UInt<5>(0h14), remapindex_14) when _T_4805 : connect remapVecData[14], Queue2_UInt8_20.io.deq.bits connect remapVecValids[14], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_4806 = eq(UInt<5>(0h15), remapindex_14) when _T_4806 : connect remapVecData[14], Queue2_UInt8_21.io.deq.bits connect remapVecValids[14], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_4807 = eq(UInt<5>(0h16), remapindex_14) when _T_4807 : connect remapVecData[14], Queue2_UInt8_22.io.deq.bits connect remapVecValids[14], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_4808 = eq(UInt<5>(0h17), remapindex_14) when _T_4808 : connect remapVecData[14], Queue2_UInt8_23.io.deq.bits connect remapVecValids[14], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_4809 = eq(UInt<5>(0h18), remapindex_14) when _T_4809 : connect remapVecData[14], Queue2_UInt8_24.io.deq.bits connect remapVecValids[14], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_4810 = eq(UInt<5>(0h19), remapindex_14) when _T_4810 : connect remapVecData[14], Queue2_UInt8_25.io.deq.bits connect remapVecValids[14], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_4811 = eq(UInt<5>(0h1a), remapindex_14) when _T_4811 : connect remapVecData[14], Queue2_UInt8_26.io.deq.bits connect remapVecValids[14], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_4812 = eq(UInt<5>(0h1b), remapindex_14) when _T_4812 : connect remapVecData[14], Queue2_UInt8_27.io.deq.bits connect remapVecValids[14], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_4813 = eq(UInt<5>(0h1c), remapindex_14) when _T_4813 : connect remapVecData[14], Queue2_UInt8_28.io.deq.bits connect remapVecValids[14], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_4814 = eq(UInt<5>(0h1d), remapindex_14) when _T_4814 : connect remapVecData[14], Queue2_UInt8_29.io.deq.bits connect remapVecValids[14], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_4815 = eq(UInt<5>(0h1e), remapindex_14) when _T_4815 : connect remapVecData[14], Queue2_UInt8_30.io.deq.bits connect remapVecValids[14], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_4816 = eq(UInt<5>(0h1f), remapindex_14) when _T_4816 : connect remapVecData[14], Queue2_UInt8_31.io.deq.bits connect remapVecValids[14], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_4817 = eq(UInt<1>(0h0), remapindex_15) when _T_4817 : connect remapVecData[15], Queue2_UInt8.io.deq.bits connect remapVecValids[15], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[15] node _T_4818 = eq(UInt<1>(0h1), remapindex_15) when _T_4818 : connect remapVecData[15], Queue2_UInt8_1.io.deq.bits connect remapVecValids[15], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_4819 = eq(UInt<2>(0h2), remapindex_15) when _T_4819 : connect remapVecData[15], Queue2_UInt8_2.io.deq.bits connect remapVecValids[15], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_4820 = eq(UInt<2>(0h3), remapindex_15) when _T_4820 : connect remapVecData[15], Queue2_UInt8_3.io.deq.bits connect remapVecValids[15], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_4821 = eq(UInt<3>(0h4), remapindex_15) when _T_4821 : connect remapVecData[15], Queue2_UInt8_4.io.deq.bits connect remapVecValids[15], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_4822 = eq(UInt<3>(0h5), remapindex_15) when _T_4822 : connect remapVecData[15], Queue2_UInt8_5.io.deq.bits connect remapVecValids[15], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_4823 = eq(UInt<3>(0h6), remapindex_15) when _T_4823 : connect remapVecData[15], Queue2_UInt8_6.io.deq.bits connect remapVecValids[15], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_4824 = eq(UInt<3>(0h7), remapindex_15) when _T_4824 : connect remapVecData[15], Queue2_UInt8_7.io.deq.bits connect remapVecValids[15], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_4825 = eq(UInt<4>(0h8), remapindex_15) when _T_4825 : connect remapVecData[15], Queue2_UInt8_8.io.deq.bits connect remapVecValids[15], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_4826 = eq(UInt<4>(0h9), remapindex_15) when _T_4826 : connect remapVecData[15], Queue2_UInt8_9.io.deq.bits connect remapVecValids[15], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_4827 = eq(UInt<4>(0ha), remapindex_15) when _T_4827 : connect remapVecData[15], Queue2_UInt8_10.io.deq.bits connect remapVecValids[15], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_4828 = eq(UInt<4>(0hb), remapindex_15) when _T_4828 : connect remapVecData[15], Queue2_UInt8_11.io.deq.bits connect remapVecValids[15], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_4829 = eq(UInt<4>(0hc), remapindex_15) when _T_4829 : connect remapVecData[15], Queue2_UInt8_12.io.deq.bits connect remapVecValids[15], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_4830 = eq(UInt<4>(0hd), remapindex_15) when _T_4830 : connect remapVecData[15], Queue2_UInt8_13.io.deq.bits connect remapVecValids[15], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_4831 = eq(UInt<4>(0he), remapindex_15) when _T_4831 : connect remapVecData[15], Queue2_UInt8_14.io.deq.bits connect remapVecValids[15], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_4832 = eq(UInt<4>(0hf), remapindex_15) when _T_4832 : connect remapVecData[15], Queue2_UInt8_15.io.deq.bits connect remapVecValids[15], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_4833 = eq(UInt<5>(0h10), remapindex_15) when _T_4833 : connect remapVecData[15], Queue2_UInt8_16.io.deq.bits connect remapVecValids[15], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_4834 = eq(UInt<5>(0h11), remapindex_15) when _T_4834 : connect remapVecData[15], Queue2_UInt8_17.io.deq.bits connect remapVecValids[15], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_4835 = eq(UInt<5>(0h12), remapindex_15) when _T_4835 : connect remapVecData[15], Queue2_UInt8_18.io.deq.bits connect remapVecValids[15], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_4836 = eq(UInt<5>(0h13), remapindex_15) when _T_4836 : connect remapVecData[15], Queue2_UInt8_19.io.deq.bits connect remapVecValids[15], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_4837 = eq(UInt<5>(0h14), remapindex_15) when _T_4837 : connect remapVecData[15], Queue2_UInt8_20.io.deq.bits connect remapVecValids[15], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_4838 = eq(UInt<5>(0h15), remapindex_15) when _T_4838 : connect remapVecData[15], Queue2_UInt8_21.io.deq.bits connect remapVecValids[15], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_4839 = eq(UInt<5>(0h16), remapindex_15) when _T_4839 : connect remapVecData[15], Queue2_UInt8_22.io.deq.bits connect remapVecValids[15], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_4840 = eq(UInt<5>(0h17), remapindex_15) when _T_4840 : connect remapVecData[15], Queue2_UInt8_23.io.deq.bits connect remapVecValids[15], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_4841 = eq(UInt<5>(0h18), remapindex_15) when _T_4841 : connect remapVecData[15], Queue2_UInt8_24.io.deq.bits connect remapVecValids[15], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_4842 = eq(UInt<5>(0h19), remapindex_15) when _T_4842 : connect remapVecData[15], Queue2_UInt8_25.io.deq.bits connect remapVecValids[15], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_4843 = eq(UInt<5>(0h1a), remapindex_15) when _T_4843 : connect remapVecData[15], Queue2_UInt8_26.io.deq.bits connect remapVecValids[15], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_4844 = eq(UInt<5>(0h1b), remapindex_15) when _T_4844 : connect remapVecData[15], Queue2_UInt8_27.io.deq.bits connect remapVecValids[15], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_4845 = eq(UInt<5>(0h1c), remapindex_15) when _T_4845 : connect remapVecData[15], Queue2_UInt8_28.io.deq.bits connect remapVecValids[15], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_4846 = eq(UInt<5>(0h1d), remapindex_15) when _T_4846 : connect remapVecData[15], Queue2_UInt8_29.io.deq.bits connect remapVecValids[15], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_4847 = eq(UInt<5>(0h1e), remapindex_15) when _T_4847 : connect remapVecData[15], Queue2_UInt8_30.io.deq.bits connect remapVecValids[15], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_4848 = eq(UInt<5>(0h1f), remapindex_15) when _T_4848 : connect remapVecData[15], Queue2_UInt8_31.io.deq.bits connect remapVecValids[15], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_4849 = eq(UInt<1>(0h0), remapindex_16) when _T_4849 : connect remapVecData[16], Queue2_UInt8.io.deq.bits connect remapVecValids[16], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[16] node _T_4850 = eq(UInt<1>(0h1), remapindex_16) when _T_4850 : connect remapVecData[16], Queue2_UInt8_1.io.deq.bits connect remapVecValids[16], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_4851 = eq(UInt<2>(0h2), remapindex_16) when _T_4851 : connect remapVecData[16], Queue2_UInt8_2.io.deq.bits connect remapVecValids[16], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_4852 = eq(UInt<2>(0h3), remapindex_16) when _T_4852 : connect remapVecData[16], Queue2_UInt8_3.io.deq.bits connect remapVecValids[16], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_4853 = eq(UInt<3>(0h4), remapindex_16) when _T_4853 : connect remapVecData[16], Queue2_UInt8_4.io.deq.bits connect remapVecValids[16], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_4854 = eq(UInt<3>(0h5), remapindex_16) when _T_4854 : connect remapVecData[16], Queue2_UInt8_5.io.deq.bits connect remapVecValids[16], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_4855 = eq(UInt<3>(0h6), remapindex_16) when _T_4855 : connect remapVecData[16], Queue2_UInt8_6.io.deq.bits connect remapVecValids[16], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_4856 = eq(UInt<3>(0h7), remapindex_16) when _T_4856 : connect remapVecData[16], Queue2_UInt8_7.io.deq.bits connect remapVecValids[16], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_4857 = eq(UInt<4>(0h8), remapindex_16) when _T_4857 : connect remapVecData[16], Queue2_UInt8_8.io.deq.bits connect remapVecValids[16], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_4858 = eq(UInt<4>(0h9), remapindex_16) when _T_4858 : connect remapVecData[16], Queue2_UInt8_9.io.deq.bits connect remapVecValids[16], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_4859 = eq(UInt<4>(0ha), remapindex_16) when _T_4859 : connect remapVecData[16], Queue2_UInt8_10.io.deq.bits connect remapVecValids[16], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_4860 = eq(UInt<4>(0hb), remapindex_16) when _T_4860 : connect remapVecData[16], Queue2_UInt8_11.io.deq.bits connect remapVecValids[16], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_4861 = eq(UInt<4>(0hc), remapindex_16) when _T_4861 : connect remapVecData[16], Queue2_UInt8_12.io.deq.bits connect remapVecValids[16], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_4862 = eq(UInt<4>(0hd), remapindex_16) when _T_4862 : connect remapVecData[16], Queue2_UInt8_13.io.deq.bits connect remapVecValids[16], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_4863 = eq(UInt<4>(0he), remapindex_16) when _T_4863 : connect remapVecData[16], Queue2_UInt8_14.io.deq.bits connect remapVecValids[16], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_4864 = eq(UInt<4>(0hf), remapindex_16) when _T_4864 : connect remapVecData[16], Queue2_UInt8_15.io.deq.bits connect remapVecValids[16], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_4865 = eq(UInt<5>(0h10), remapindex_16) when _T_4865 : connect remapVecData[16], Queue2_UInt8_16.io.deq.bits connect remapVecValids[16], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_4866 = eq(UInt<5>(0h11), remapindex_16) when _T_4866 : connect remapVecData[16], Queue2_UInt8_17.io.deq.bits connect remapVecValids[16], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_4867 = eq(UInt<5>(0h12), remapindex_16) when _T_4867 : connect remapVecData[16], Queue2_UInt8_18.io.deq.bits connect remapVecValids[16], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_4868 = eq(UInt<5>(0h13), remapindex_16) when _T_4868 : connect remapVecData[16], Queue2_UInt8_19.io.deq.bits connect remapVecValids[16], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_4869 = eq(UInt<5>(0h14), remapindex_16) when _T_4869 : connect remapVecData[16], Queue2_UInt8_20.io.deq.bits connect remapVecValids[16], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_4870 = eq(UInt<5>(0h15), remapindex_16) when _T_4870 : connect remapVecData[16], Queue2_UInt8_21.io.deq.bits connect remapVecValids[16], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_4871 = eq(UInt<5>(0h16), remapindex_16) when _T_4871 : connect remapVecData[16], Queue2_UInt8_22.io.deq.bits connect remapVecValids[16], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_4872 = eq(UInt<5>(0h17), remapindex_16) when _T_4872 : connect remapVecData[16], Queue2_UInt8_23.io.deq.bits connect remapVecValids[16], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_4873 = eq(UInt<5>(0h18), remapindex_16) when _T_4873 : connect remapVecData[16], Queue2_UInt8_24.io.deq.bits connect remapVecValids[16], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_4874 = eq(UInt<5>(0h19), remapindex_16) when _T_4874 : connect remapVecData[16], Queue2_UInt8_25.io.deq.bits connect remapVecValids[16], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_4875 = eq(UInt<5>(0h1a), remapindex_16) when _T_4875 : connect remapVecData[16], Queue2_UInt8_26.io.deq.bits connect remapVecValids[16], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_4876 = eq(UInt<5>(0h1b), remapindex_16) when _T_4876 : connect remapVecData[16], Queue2_UInt8_27.io.deq.bits connect remapVecValids[16], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_4877 = eq(UInt<5>(0h1c), remapindex_16) when _T_4877 : connect remapVecData[16], Queue2_UInt8_28.io.deq.bits connect remapVecValids[16], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_4878 = eq(UInt<5>(0h1d), remapindex_16) when _T_4878 : connect remapVecData[16], Queue2_UInt8_29.io.deq.bits connect remapVecValids[16], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_4879 = eq(UInt<5>(0h1e), remapindex_16) when _T_4879 : connect remapVecData[16], Queue2_UInt8_30.io.deq.bits connect remapVecValids[16], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_4880 = eq(UInt<5>(0h1f), remapindex_16) when _T_4880 : connect remapVecData[16], Queue2_UInt8_31.io.deq.bits connect remapVecValids[16], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_4881 = eq(UInt<1>(0h0), remapindex_17) when _T_4881 : connect remapVecData[17], Queue2_UInt8.io.deq.bits connect remapVecValids[17], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[17] node _T_4882 = eq(UInt<1>(0h1), remapindex_17) when _T_4882 : connect remapVecData[17], Queue2_UInt8_1.io.deq.bits connect remapVecValids[17], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_4883 = eq(UInt<2>(0h2), remapindex_17) when _T_4883 : connect remapVecData[17], Queue2_UInt8_2.io.deq.bits connect remapVecValids[17], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_4884 = eq(UInt<2>(0h3), remapindex_17) when _T_4884 : connect remapVecData[17], Queue2_UInt8_3.io.deq.bits connect remapVecValids[17], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_4885 = eq(UInt<3>(0h4), remapindex_17) when _T_4885 : connect remapVecData[17], Queue2_UInt8_4.io.deq.bits connect remapVecValids[17], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_4886 = eq(UInt<3>(0h5), remapindex_17) when _T_4886 : connect remapVecData[17], Queue2_UInt8_5.io.deq.bits connect remapVecValids[17], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_4887 = eq(UInt<3>(0h6), remapindex_17) when _T_4887 : connect remapVecData[17], Queue2_UInt8_6.io.deq.bits connect remapVecValids[17], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_4888 = eq(UInt<3>(0h7), remapindex_17) when _T_4888 : connect remapVecData[17], Queue2_UInt8_7.io.deq.bits connect remapVecValids[17], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_4889 = eq(UInt<4>(0h8), remapindex_17) when _T_4889 : connect remapVecData[17], Queue2_UInt8_8.io.deq.bits connect remapVecValids[17], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_4890 = eq(UInt<4>(0h9), remapindex_17) when _T_4890 : connect remapVecData[17], Queue2_UInt8_9.io.deq.bits connect remapVecValids[17], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_4891 = eq(UInt<4>(0ha), remapindex_17) when _T_4891 : connect remapVecData[17], Queue2_UInt8_10.io.deq.bits connect remapVecValids[17], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_4892 = eq(UInt<4>(0hb), remapindex_17) when _T_4892 : connect remapVecData[17], Queue2_UInt8_11.io.deq.bits connect remapVecValids[17], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_4893 = eq(UInt<4>(0hc), remapindex_17) when _T_4893 : connect remapVecData[17], Queue2_UInt8_12.io.deq.bits connect remapVecValids[17], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_4894 = eq(UInt<4>(0hd), remapindex_17) when _T_4894 : connect remapVecData[17], Queue2_UInt8_13.io.deq.bits connect remapVecValids[17], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_4895 = eq(UInt<4>(0he), remapindex_17) when _T_4895 : connect remapVecData[17], Queue2_UInt8_14.io.deq.bits connect remapVecValids[17], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_4896 = eq(UInt<4>(0hf), remapindex_17) when _T_4896 : connect remapVecData[17], Queue2_UInt8_15.io.deq.bits connect remapVecValids[17], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_4897 = eq(UInt<5>(0h10), remapindex_17) when _T_4897 : connect remapVecData[17], Queue2_UInt8_16.io.deq.bits connect remapVecValids[17], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_4898 = eq(UInt<5>(0h11), remapindex_17) when _T_4898 : connect remapVecData[17], Queue2_UInt8_17.io.deq.bits connect remapVecValids[17], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_4899 = eq(UInt<5>(0h12), remapindex_17) when _T_4899 : connect remapVecData[17], Queue2_UInt8_18.io.deq.bits connect remapVecValids[17], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_4900 = eq(UInt<5>(0h13), remapindex_17) when _T_4900 : connect remapVecData[17], Queue2_UInt8_19.io.deq.bits connect remapVecValids[17], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_4901 = eq(UInt<5>(0h14), remapindex_17) when _T_4901 : connect remapVecData[17], Queue2_UInt8_20.io.deq.bits connect remapVecValids[17], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_4902 = eq(UInt<5>(0h15), remapindex_17) when _T_4902 : connect remapVecData[17], Queue2_UInt8_21.io.deq.bits connect remapVecValids[17], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_4903 = eq(UInt<5>(0h16), remapindex_17) when _T_4903 : connect remapVecData[17], Queue2_UInt8_22.io.deq.bits connect remapVecValids[17], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_4904 = eq(UInt<5>(0h17), remapindex_17) when _T_4904 : connect remapVecData[17], Queue2_UInt8_23.io.deq.bits connect remapVecValids[17], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_4905 = eq(UInt<5>(0h18), remapindex_17) when _T_4905 : connect remapVecData[17], Queue2_UInt8_24.io.deq.bits connect remapVecValids[17], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_4906 = eq(UInt<5>(0h19), remapindex_17) when _T_4906 : connect remapVecData[17], Queue2_UInt8_25.io.deq.bits connect remapVecValids[17], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_4907 = eq(UInt<5>(0h1a), remapindex_17) when _T_4907 : connect remapVecData[17], Queue2_UInt8_26.io.deq.bits connect remapVecValids[17], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_4908 = eq(UInt<5>(0h1b), remapindex_17) when _T_4908 : connect remapVecData[17], Queue2_UInt8_27.io.deq.bits connect remapVecValids[17], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_4909 = eq(UInt<5>(0h1c), remapindex_17) when _T_4909 : connect remapVecData[17], Queue2_UInt8_28.io.deq.bits connect remapVecValids[17], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_4910 = eq(UInt<5>(0h1d), remapindex_17) when _T_4910 : connect remapVecData[17], Queue2_UInt8_29.io.deq.bits connect remapVecValids[17], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_4911 = eq(UInt<5>(0h1e), remapindex_17) when _T_4911 : connect remapVecData[17], Queue2_UInt8_30.io.deq.bits connect remapVecValids[17], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_4912 = eq(UInt<5>(0h1f), remapindex_17) when _T_4912 : connect remapVecData[17], Queue2_UInt8_31.io.deq.bits connect remapVecValids[17], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_4913 = eq(UInt<1>(0h0), remapindex_18) when _T_4913 : connect remapVecData[18], Queue2_UInt8.io.deq.bits connect remapVecValids[18], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[18] node _T_4914 = eq(UInt<1>(0h1), remapindex_18) when _T_4914 : connect remapVecData[18], Queue2_UInt8_1.io.deq.bits connect remapVecValids[18], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_4915 = eq(UInt<2>(0h2), remapindex_18) when _T_4915 : connect remapVecData[18], Queue2_UInt8_2.io.deq.bits connect remapVecValids[18], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_4916 = eq(UInt<2>(0h3), remapindex_18) when _T_4916 : connect remapVecData[18], Queue2_UInt8_3.io.deq.bits connect remapVecValids[18], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_4917 = eq(UInt<3>(0h4), remapindex_18) when _T_4917 : connect remapVecData[18], Queue2_UInt8_4.io.deq.bits connect remapVecValids[18], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_4918 = eq(UInt<3>(0h5), remapindex_18) when _T_4918 : connect remapVecData[18], Queue2_UInt8_5.io.deq.bits connect remapVecValids[18], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_4919 = eq(UInt<3>(0h6), remapindex_18) when _T_4919 : connect remapVecData[18], Queue2_UInt8_6.io.deq.bits connect remapVecValids[18], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_4920 = eq(UInt<3>(0h7), remapindex_18) when _T_4920 : connect remapVecData[18], Queue2_UInt8_7.io.deq.bits connect remapVecValids[18], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_4921 = eq(UInt<4>(0h8), remapindex_18) when _T_4921 : connect remapVecData[18], Queue2_UInt8_8.io.deq.bits connect remapVecValids[18], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_4922 = eq(UInt<4>(0h9), remapindex_18) when _T_4922 : connect remapVecData[18], Queue2_UInt8_9.io.deq.bits connect remapVecValids[18], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_4923 = eq(UInt<4>(0ha), remapindex_18) when _T_4923 : connect remapVecData[18], Queue2_UInt8_10.io.deq.bits connect remapVecValids[18], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_4924 = eq(UInt<4>(0hb), remapindex_18) when _T_4924 : connect remapVecData[18], Queue2_UInt8_11.io.deq.bits connect remapVecValids[18], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_4925 = eq(UInt<4>(0hc), remapindex_18) when _T_4925 : connect remapVecData[18], Queue2_UInt8_12.io.deq.bits connect remapVecValids[18], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_4926 = eq(UInt<4>(0hd), remapindex_18) when _T_4926 : connect remapVecData[18], Queue2_UInt8_13.io.deq.bits connect remapVecValids[18], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_4927 = eq(UInt<4>(0he), remapindex_18) when _T_4927 : connect remapVecData[18], Queue2_UInt8_14.io.deq.bits connect remapVecValids[18], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_4928 = eq(UInt<4>(0hf), remapindex_18) when _T_4928 : connect remapVecData[18], Queue2_UInt8_15.io.deq.bits connect remapVecValids[18], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_4929 = eq(UInt<5>(0h10), remapindex_18) when _T_4929 : connect remapVecData[18], Queue2_UInt8_16.io.deq.bits connect remapVecValids[18], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_4930 = eq(UInt<5>(0h11), remapindex_18) when _T_4930 : connect remapVecData[18], Queue2_UInt8_17.io.deq.bits connect remapVecValids[18], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_4931 = eq(UInt<5>(0h12), remapindex_18) when _T_4931 : connect remapVecData[18], Queue2_UInt8_18.io.deq.bits connect remapVecValids[18], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_4932 = eq(UInt<5>(0h13), remapindex_18) when _T_4932 : connect remapVecData[18], Queue2_UInt8_19.io.deq.bits connect remapVecValids[18], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_4933 = eq(UInt<5>(0h14), remapindex_18) when _T_4933 : connect remapVecData[18], Queue2_UInt8_20.io.deq.bits connect remapVecValids[18], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_4934 = eq(UInt<5>(0h15), remapindex_18) when _T_4934 : connect remapVecData[18], Queue2_UInt8_21.io.deq.bits connect remapVecValids[18], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_4935 = eq(UInt<5>(0h16), remapindex_18) when _T_4935 : connect remapVecData[18], Queue2_UInt8_22.io.deq.bits connect remapVecValids[18], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_4936 = eq(UInt<5>(0h17), remapindex_18) when _T_4936 : connect remapVecData[18], Queue2_UInt8_23.io.deq.bits connect remapVecValids[18], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_4937 = eq(UInt<5>(0h18), remapindex_18) when _T_4937 : connect remapVecData[18], Queue2_UInt8_24.io.deq.bits connect remapVecValids[18], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_4938 = eq(UInt<5>(0h19), remapindex_18) when _T_4938 : connect remapVecData[18], Queue2_UInt8_25.io.deq.bits connect remapVecValids[18], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_4939 = eq(UInt<5>(0h1a), remapindex_18) when _T_4939 : connect remapVecData[18], Queue2_UInt8_26.io.deq.bits connect remapVecValids[18], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_4940 = eq(UInt<5>(0h1b), remapindex_18) when _T_4940 : connect remapVecData[18], Queue2_UInt8_27.io.deq.bits connect remapVecValids[18], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_4941 = eq(UInt<5>(0h1c), remapindex_18) when _T_4941 : connect remapVecData[18], Queue2_UInt8_28.io.deq.bits connect remapVecValids[18], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_4942 = eq(UInt<5>(0h1d), remapindex_18) when _T_4942 : connect remapVecData[18], Queue2_UInt8_29.io.deq.bits connect remapVecValids[18], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_4943 = eq(UInt<5>(0h1e), remapindex_18) when _T_4943 : connect remapVecData[18], Queue2_UInt8_30.io.deq.bits connect remapVecValids[18], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_4944 = eq(UInt<5>(0h1f), remapindex_18) when _T_4944 : connect remapVecData[18], Queue2_UInt8_31.io.deq.bits connect remapVecValids[18], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_4945 = eq(UInt<1>(0h0), remapindex_19) when _T_4945 : connect remapVecData[19], Queue2_UInt8.io.deq.bits connect remapVecValids[19], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[19] node _T_4946 = eq(UInt<1>(0h1), remapindex_19) when _T_4946 : connect remapVecData[19], Queue2_UInt8_1.io.deq.bits connect remapVecValids[19], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_4947 = eq(UInt<2>(0h2), remapindex_19) when _T_4947 : connect remapVecData[19], Queue2_UInt8_2.io.deq.bits connect remapVecValids[19], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_4948 = eq(UInt<2>(0h3), remapindex_19) when _T_4948 : connect remapVecData[19], Queue2_UInt8_3.io.deq.bits connect remapVecValids[19], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_4949 = eq(UInt<3>(0h4), remapindex_19) when _T_4949 : connect remapVecData[19], Queue2_UInt8_4.io.deq.bits connect remapVecValids[19], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_4950 = eq(UInt<3>(0h5), remapindex_19) when _T_4950 : connect remapVecData[19], Queue2_UInt8_5.io.deq.bits connect remapVecValids[19], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_4951 = eq(UInt<3>(0h6), remapindex_19) when _T_4951 : connect remapVecData[19], Queue2_UInt8_6.io.deq.bits connect remapVecValids[19], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_4952 = eq(UInt<3>(0h7), remapindex_19) when _T_4952 : connect remapVecData[19], Queue2_UInt8_7.io.deq.bits connect remapVecValids[19], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_4953 = eq(UInt<4>(0h8), remapindex_19) when _T_4953 : connect remapVecData[19], Queue2_UInt8_8.io.deq.bits connect remapVecValids[19], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_4954 = eq(UInt<4>(0h9), remapindex_19) when _T_4954 : connect remapVecData[19], Queue2_UInt8_9.io.deq.bits connect remapVecValids[19], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_4955 = eq(UInt<4>(0ha), remapindex_19) when _T_4955 : connect remapVecData[19], Queue2_UInt8_10.io.deq.bits connect remapVecValids[19], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_4956 = eq(UInt<4>(0hb), remapindex_19) when _T_4956 : connect remapVecData[19], Queue2_UInt8_11.io.deq.bits connect remapVecValids[19], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_4957 = eq(UInt<4>(0hc), remapindex_19) when _T_4957 : connect remapVecData[19], Queue2_UInt8_12.io.deq.bits connect remapVecValids[19], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_4958 = eq(UInt<4>(0hd), remapindex_19) when _T_4958 : connect remapVecData[19], Queue2_UInt8_13.io.deq.bits connect remapVecValids[19], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_4959 = eq(UInt<4>(0he), remapindex_19) when _T_4959 : connect remapVecData[19], Queue2_UInt8_14.io.deq.bits connect remapVecValids[19], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_4960 = eq(UInt<4>(0hf), remapindex_19) when _T_4960 : connect remapVecData[19], Queue2_UInt8_15.io.deq.bits connect remapVecValids[19], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_4961 = eq(UInt<5>(0h10), remapindex_19) when _T_4961 : connect remapVecData[19], Queue2_UInt8_16.io.deq.bits connect remapVecValids[19], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_4962 = eq(UInt<5>(0h11), remapindex_19) when _T_4962 : connect remapVecData[19], Queue2_UInt8_17.io.deq.bits connect remapVecValids[19], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_4963 = eq(UInt<5>(0h12), remapindex_19) when _T_4963 : connect remapVecData[19], Queue2_UInt8_18.io.deq.bits connect remapVecValids[19], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_4964 = eq(UInt<5>(0h13), remapindex_19) when _T_4964 : connect remapVecData[19], Queue2_UInt8_19.io.deq.bits connect remapVecValids[19], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_4965 = eq(UInt<5>(0h14), remapindex_19) when _T_4965 : connect remapVecData[19], Queue2_UInt8_20.io.deq.bits connect remapVecValids[19], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_4966 = eq(UInt<5>(0h15), remapindex_19) when _T_4966 : connect remapVecData[19], Queue2_UInt8_21.io.deq.bits connect remapVecValids[19], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_4967 = eq(UInt<5>(0h16), remapindex_19) when _T_4967 : connect remapVecData[19], Queue2_UInt8_22.io.deq.bits connect remapVecValids[19], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_4968 = eq(UInt<5>(0h17), remapindex_19) when _T_4968 : connect remapVecData[19], Queue2_UInt8_23.io.deq.bits connect remapVecValids[19], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_4969 = eq(UInt<5>(0h18), remapindex_19) when _T_4969 : connect remapVecData[19], Queue2_UInt8_24.io.deq.bits connect remapVecValids[19], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_4970 = eq(UInt<5>(0h19), remapindex_19) when _T_4970 : connect remapVecData[19], Queue2_UInt8_25.io.deq.bits connect remapVecValids[19], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_4971 = eq(UInt<5>(0h1a), remapindex_19) when _T_4971 : connect remapVecData[19], Queue2_UInt8_26.io.deq.bits connect remapVecValids[19], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_4972 = eq(UInt<5>(0h1b), remapindex_19) when _T_4972 : connect remapVecData[19], Queue2_UInt8_27.io.deq.bits connect remapVecValids[19], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_4973 = eq(UInt<5>(0h1c), remapindex_19) when _T_4973 : connect remapVecData[19], Queue2_UInt8_28.io.deq.bits connect remapVecValids[19], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_4974 = eq(UInt<5>(0h1d), remapindex_19) when _T_4974 : connect remapVecData[19], Queue2_UInt8_29.io.deq.bits connect remapVecValids[19], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_4975 = eq(UInt<5>(0h1e), remapindex_19) when _T_4975 : connect remapVecData[19], Queue2_UInt8_30.io.deq.bits connect remapVecValids[19], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_4976 = eq(UInt<5>(0h1f), remapindex_19) when _T_4976 : connect remapVecData[19], Queue2_UInt8_31.io.deq.bits connect remapVecValids[19], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_4977 = eq(UInt<1>(0h0), remapindex_20) when _T_4977 : connect remapVecData[20], Queue2_UInt8.io.deq.bits connect remapVecValids[20], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[20] node _T_4978 = eq(UInt<1>(0h1), remapindex_20) when _T_4978 : connect remapVecData[20], Queue2_UInt8_1.io.deq.bits connect remapVecValids[20], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_4979 = eq(UInt<2>(0h2), remapindex_20) when _T_4979 : connect remapVecData[20], Queue2_UInt8_2.io.deq.bits connect remapVecValids[20], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_4980 = eq(UInt<2>(0h3), remapindex_20) when _T_4980 : connect remapVecData[20], Queue2_UInt8_3.io.deq.bits connect remapVecValids[20], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_4981 = eq(UInt<3>(0h4), remapindex_20) when _T_4981 : connect remapVecData[20], Queue2_UInt8_4.io.deq.bits connect remapVecValids[20], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_4982 = eq(UInt<3>(0h5), remapindex_20) when _T_4982 : connect remapVecData[20], Queue2_UInt8_5.io.deq.bits connect remapVecValids[20], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_4983 = eq(UInt<3>(0h6), remapindex_20) when _T_4983 : connect remapVecData[20], Queue2_UInt8_6.io.deq.bits connect remapVecValids[20], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_4984 = eq(UInt<3>(0h7), remapindex_20) when _T_4984 : connect remapVecData[20], Queue2_UInt8_7.io.deq.bits connect remapVecValids[20], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_4985 = eq(UInt<4>(0h8), remapindex_20) when _T_4985 : connect remapVecData[20], Queue2_UInt8_8.io.deq.bits connect remapVecValids[20], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_4986 = eq(UInt<4>(0h9), remapindex_20) when _T_4986 : connect remapVecData[20], Queue2_UInt8_9.io.deq.bits connect remapVecValids[20], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_4987 = eq(UInt<4>(0ha), remapindex_20) when _T_4987 : connect remapVecData[20], Queue2_UInt8_10.io.deq.bits connect remapVecValids[20], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_4988 = eq(UInt<4>(0hb), remapindex_20) when _T_4988 : connect remapVecData[20], Queue2_UInt8_11.io.deq.bits connect remapVecValids[20], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_4989 = eq(UInt<4>(0hc), remapindex_20) when _T_4989 : connect remapVecData[20], Queue2_UInt8_12.io.deq.bits connect remapVecValids[20], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_4990 = eq(UInt<4>(0hd), remapindex_20) when _T_4990 : connect remapVecData[20], Queue2_UInt8_13.io.deq.bits connect remapVecValids[20], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_4991 = eq(UInt<4>(0he), remapindex_20) when _T_4991 : connect remapVecData[20], Queue2_UInt8_14.io.deq.bits connect remapVecValids[20], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_4992 = eq(UInt<4>(0hf), remapindex_20) when _T_4992 : connect remapVecData[20], Queue2_UInt8_15.io.deq.bits connect remapVecValids[20], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_4993 = eq(UInt<5>(0h10), remapindex_20) when _T_4993 : connect remapVecData[20], Queue2_UInt8_16.io.deq.bits connect remapVecValids[20], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_4994 = eq(UInt<5>(0h11), remapindex_20) when _T_4994 : connect remapVecData[20], Queue2_UInt8_17.io.deq.bits connect remapVecValids[20], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_4995 = eq(UInt<5>(0h12), remapindex_20) when _T_4995 : connect remapVecData[20], Queue2_UInt8_18.io.deq.bits connect remapVecValids[20], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_4996 = eq(UInt<5>(0h13), remapindex_20) when _T_4996 : connect remapVecData[20], Queue2_UInt8_19.io.deq.bits connect remapVecValids[20], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_4997 = eq(UInt<5>(0h14), remapindex_20) when _T_4997 : connect remapVecData[20], Queue2_UInt8_20.io.deq.bits connect remapVecValids[20], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_4998 = eq(UInt<5>(0h15), remapindex_20) when _T_4998 : connect remapVecData[20], Queue2_UInt8_21.io.deq.bits connect remapVecValids[20], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_4999 = eq(UInt<5>(0h16), remapindex_20) when _T_4999 : connect remapVecData[20], Queue2_UInt8_22.io.deq.bits connect remapVecValids[20], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_5000 = eq(UInt<5>(0h17), remapindex_20) when _T_5000 : connect remapVecData[20], Queue2_UInt8_23.io.deq.bits connect remapVecValids[20], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_5001 = eq(UInt<5>(0h18), remapindex_20) when _T_5001 : connect remapVecData[20], Queue2_UInt8_24.io.deq.bits connect remapVecValids[20], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_5002 = eq(UInt<5>(0h19), remapindex_20) when _T_5002 : connect remapVecData[20], Queue2_UInt8_25.io.deq.bits connect remapVecValids[20], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_5003 = eq(UInt<5>(0h1a), remapindex_20) when _T_5003 : connect remapVecData[20], Queue2_UInt8_26.io.deq.bits connect remapVecValids[20], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_5004 = eq(UInt<5>(0h1b), remapindex_20) when _T_5004 : connect remapVecData[20], Queue2_UInt8_27.io.deq.bits connect remapVecValids[20], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_5005 = eq(UInt<5>(0h1c), remapindex_20) when _T_5005 : connect remapVecData[20], Queue2_UInt8_28.io.deq.bits connect remapVecValids[20], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_5006 = eq(UInt<5>(0h1d), remapindex_20) when _T_5006 : connect remapVecData[20], Queue2_UInt8_29.io.deq.bits connect remapVecValids[20], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_5007 = eq(UInt<5>(0h1e), remapindex_20) when _T_5007 : connect remapVecData[20], Queue2_UInt8_30.io.deq.bits connect remapVecValids[20], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_5008 = eq(UInt<5>(0h1f), remapindex_20) when _T_5008 : connect remapVecData[20], Queue2_UInt8_31.io.deq.bits connect remapVecValids[20], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_5009 = eq(UInt<1>(0h0), remapindex_21) when _T_5009 : connect remapVecData[21], Queue2_UInt8.io.deq.bits connect remapVecValids[21], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[21] node _T_5010 = eq(UInt<1>(0h1), remapindex_21) when _T_5010 : connect remapVecData[21], Queue2_UInt8_1.io.deq.bits connect remapVecValids[21], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_5011 = eq(UInt<2>(0h2), remapindex_21) when _T_5011 : connect remapVecData[21], Queue2_UInt8_2.io.deq.bits connect remapVecValids[21], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_5012 = eq(UInt<2>(0h3), remapindex_21) when _T_5012 : connect remapVecData[21], Queue2_UInt8_3.io.deq.bits connect remapVecValids[21], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_5013 = eq(UInt<3>(0h4), remapindex_21) when _T_5013 : connect remapVecData[21], Queue2_UInt8_4.io.deq.bits connect remapVecValids[21], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_5014 = eq(UInt<3>(0h5), remapindex_21) when _T_5014 : connect remapVecData[21], Queue2_UInt8_5.io.deq.bits connect remapVecValids[21], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_5015 = eq(UInt<3>(0h6), remapindex_21) when _T_5015 : connect remapVecData[21], Queue2_UInt8_6.io.deq.bits connect remapVecValids[21], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_5016 = eq(UInt<3>(0h7), remapindex_21) when _T_5016 : connect remapVecData[21], Queue2_UInt8_7.io.deq.bits connect remapVecValids[21], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_5017 = eq(UInt<4>(0h8), remapindex_21) when _T_5017 : connect remapVecData[21], Queue2_UInt8_8.io.deq.bits connect remapVecValids[21], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_5018 = eq(UInt<4>(0h9), remapindex_21) when _T_5018 : connect remapVecData[21], Queue2_UInt8_9.io.deq.bits connect remapVecValids[21], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_5019 = eq(UInt<4>(0ha), remapindex_21) when _T_5019 : connect remapVecData[21], Queue2_UInt8_10.io.deq.bits connect remapVecValids[21], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_5020 = eq(UInt<4>(0hb), remapindex_21) when _T_5020 : connect remapVecData[21], Queue2_UInt8_11.io.deq.bits connect remapVecValids[21], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_5021 = eq(UInt<4>(0hc), remapindex_21) when _T_5021 : connect remapVecData[21], Queue2_UInt8_12.io.deq.bits connect remapVecValids[21], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_5022 = eq(UInt<4>(0hd), remapindex_21) when _T_5022 : connect remapVecData[21], Queue2_UInt8_13.io.deq.bits connect remapVecValids[21], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_5023 = eq(UInt<4>(0he), remapindex_21) when _T_5023 : connect remapVecData[21], Queue2_UInt8_14.io.deq.bits connect remapVecValids[21], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_5024 = eq(UInt<4>(0hf), remapindex_21) when _T_5024 : connect remapVecData[21], Queue2_UInt8_15.io.deq.bits connect remapVecValids[21], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_5025 = eq(UInt<5>(0h10), remapindex_21) when _T_5025 : connect remapVecData[21], Queue2_UInt8_16.io.deq.bits connect remapVecValids[21], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_5026 = eq(UInt<5>(0h11), remapindex_21) when _T_5026 : connect remapVecData[21], Queue2_UInt8_17.io.deq.bits connect remapVecValids[21], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_5027 = eq(UInt<5>(0h12), remapindex_21) when _T_5027 : connect remapVecData[21], Queue2_UInt8_18.io.deq.bits connect remapVecValids[21], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_5028 = eq(UInt<5>(0h13), remapindex_21) when _T_5028 : connect remapVecData[21], Queue2_UInt8_19.io.deq.bits connect remapVecValids[21], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_5029 = eq(UInt<5>(0h14), remapindex_21) when _T_5029 : connect remapVecData[21], Queue2_UInt8_20.io.deq.bits connect remapVecValids[21], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_5030 = eq(UInt<5>(0h15), remapindex_21) when _T_5030 : connect remapVecData[21], Queue2_UInt8_21.io.deq.bits connect remapVecValids[21], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_5031 = eq(UInt<5>(0h16), remapindex_21) when _T_5031 : connect remapVecData[21], Queue2_UInt8_22.io.deq.bits connect remapVecValids[21], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_5032 = eq(UInt<5>(0h17), remapindex_21) when _T_5032 : connect remapVecData[21], Queue2_UInt8_23.io.deq.bits connect remapVecValids[21], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_5033 = eq(UInt<5>(0h18), remapindex_21) when _T_5033 : connect remapVecData[21], Queue2_UInt8_24.io.deq.bits connect remapVecValids[21], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_5034 = eq(UInt<5>(0h19), remapindex_21) when _T_5034 : connect remapVecData[21], Queue2_UInt8_25.io.deq.bits connect remapVecValids[21], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_5035 = eq(UInt<5>(0h1a), remapindex_21) when _T_5035 : connect remapVecData[21], Queue2_UInt8_26.io.deq.bits connect remapVecValids[21], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_5036 = eq(UInt<5>(0h1b), remapindex_21) when _T_5036 : connect remapVecData[21], Queue2_UInt8_27.io.deq.bits connect remapVecValids[21], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_5037 = eq(UInt<5>(0h1c), remapindex_21) when _T_5037 : connect remapVecData[21], Queue2_UInt8_28.io.deq.bits connect remapVecValids[21], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_5038 = eq(UInt<5>(0h1d), remapindex_21) when _T_5038 : connect remapVecData[21], Queue2_UInt8_29.io.deq.bits connect remapVecValids[21], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_5039 = eq(UInt<5>(0h1e), remapindex_21) when _T_5039 : connect remapVecData[21], Queue2_UInt8_30.io.deq.bits connect remapVecValids[21], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_5040 = eq(UInt<5>(0h1f), remapindex_21) when _T_5040 : connect remapVecData[21], Queue2_UInt8_31.io.deq.bits connect remapVecValids[21], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_5041 = eq(UInt<1>(0h0), remapindex_22) when _T_5041 : connect remapVecData[22], Queue2_UInt8.io.deq.bits connect remapVecValids[22], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[22] node _T_5042 = eq(UInt<1>(0h1), remapindex_22) when _T_5042 : connect remapVecData[22], Queue2_UInt8_1.io.deq.bits connect remapVecValids[22], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_5043 = eq(UInt<2>(0h2), remapindex_22) when _T_5043 : connect remapVecData[22], Queue2_UInt8_2.io.deq.bits connect remapVecValids[22], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_5044 = eq(UInt<2>(0h3), remapindex_22) when _T_5044 : connect remapVecData[22], Queue2_UInt8_3.io.deq.bits connect remapVecValids[22], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_5045 = eq(UInt<3>(0h4), remapindex_22) when _T_5045 : connect remapVecData[22], Queue2_UInt8_4.io.deq.bits connect remapVecValids[22], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_5046 = eq(UInt<3>(0h5), remapindex_22) when _T_5046 : connect remapVecData[22], Queue2_UInt8_5.io.deq.bits connect remapVecValids[22], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_5047 = eq(UInt<3>(0h6), remapindex_22) when _T_5047 : connect remapVecData[22], Queue2_UInt8_6.io.deq.bits connect remapVecValids[22], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_5048 = eq(UInt<3>(0h7), remapindex_22) when _T_5048 : connect remapVecData[22], Queue2_UInt8_7.io.deq.bits connect remapVecValids[22], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_5049 = eq(UInt<4>(0h8), remapindex_22) when _T_5049 : connect remapVecData[22], Queue2_UInt8_8.io.deq.bits connect remapVecValids[22], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_5050 = eq(UInt<4>(0h9), remapindex_22) when _T_5050 : connect remapVecData[22], Queue2_UInt8_9.io.deq.bits connect remapVecValids[22], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_5051 = eq(UInt<4>(0ha), remapindex_22) when _T_5051 : connect remapVecData[22], Queue2_UInt8_10.io.deq.bits connect remapVecValids[22], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_5052 = eq(UInt<4>(0hb), remapindex_22) when _T_5052 : connect remapVecData[22], Queue2_UInt8_11.io.deq.bits connect remapVecValids[22], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_5053 = eq(UInt<4>(0hc), remapindex_22) when _T_5053 : connect remapVecData[22], Queue2_UInt8_12.io.deq.bits connect remapVecValids[22], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_5054 = eq(UInt<4>(0hd), remapindex_22) when _T_5054 : connect remapVecData[22], Queue2_UInt8_13.io.deq.bits connect remapVecValids[22], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_5055 = eq(UInt<4>(0he), remapindex_22) when _T_5055 : connect remapVecData[22], Queue2_UInt8_14.io.deq.bits connect remapVecValids[22], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_5056 = eq(UInt<4>(0hf), remapindex_22) when _T_5056 : connect remapVecData[22], Queue2_UInt8_15.io.deq.bits connect remapVecValids[22], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_5057 = eq(UInt<5>(0h10), remapindex_22) when _T_5057 : connect remapVecData[22], Queue2_UInt8_16.io.deq.bits connect remapVecValids[22], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_5058 = eq(UInt<5>(0h11), remapindex_22) when _T_5058 : connect remapVecData[22], Queue2_UInt8_17.io.deq.bits connect remapVecValids[22], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_5059 = eq(UInt<5>(0h12), remapindex_22) when _T_5059 : connect remapVecData[22], Queue2_UInt8_18.io.deq.bits connect remapVecValids[22], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_5060 = eq(UInt<5>(0h13), remapindex_22) when _T_5060 : connect remapVecData[22], Queue2_UInt8_19.io.deq.bits connect remapVecValids[22], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_5061 = eq(UInt<5>(0h14), remapindex_22) when _T_5061 : connect remapVecData[22], Queue2_UInt8_20.io.deq.bits connect remapVecValids[22], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_5062 = eq(UInt<5>(0h15), remapindex_22) when _T_5062 : connect remapVecData[22], Queue2_UInt8_21.io.deq.bits connect remapVecValids[22], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_5063 = eq(UInt<5>(0h16), remapindex_22) when _T_5063 : connect remapVecData[22], Queue2_UInt8_22.io.deq.bits connect remapVecValids[22], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_5064 = eq(UInt<5>(0h17), remapindex_22) when _T_5064 : connect remapVecData[22], Queue2_UInt8_23.io.deq.bits connect remapVecValids[22], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_5065 = eq(UInt<5>(0h18), remapindex_22) when _T_5065 : connect remapVecData[22], Queue2_UInt8_24.io.deq.bits connect remapVecValids[22], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_5066 = eq(UInt<5>(0h19), remapindex_22) when _T_5066 : connect remapVecData[22], Queue2_UInt8_25.io.deq.bits connect remapVecValids[22], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_5067 = eq(UInt<5>(0h1a), remapindex_22) when _T_5067 : connect remapVecData[22], Queue2_UInt8_26.io.deq.bits connect remapVecValids[22], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_5068 = eq(UInt<5>(0h1b), remapindex_22) when _T_5068 : connect remapVecData[22], Queue2_UInt8_27.io.deq.bits connect remapVecValids[22], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_5069 = eq(UInt<5>(0h1c), remapindex_22) when _T_5069 : connect remapVecData[22], Queue2_UInt8_28.io.deq.bits connect remapVecValids[22], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_5070 = eq(UInt<5>(0h1d), remapindex_22) when _T_5070 : connect remapVecData[22], Queue2_UInt8_29.io.deq.bits connect remapVecValids[22], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_5071 = eq(UInt<5>(0h1e), remapindex_22) when _T_5071 : connect remapVecData[22], Queue2_UInt8_30.io.deq.bits connect remapVecValids[22], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_5072 = eq(UInt<5>(0h1f), remapindex_22) when _T_5072 : connect remapVecData[22], Queue2_UInt8_31.io.deq.bits connect remapVecValids[22], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_5073 = eq(UInt<1>(0h0), remapindex_23) when _T_5073 : connect remapVecData[23], Queue2_UInt8.io.deq.bits connect remapVecValids[23], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[23] node _T_5074 = eq(UInt<1>(0h1), remapindex_23) when _T_5074 : connect remapVecData[23], Queue2_UInt8_1.io.deq.bits connect remapVecValids[23], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_5075 = eq(UInt<2>(0h2), remapindex_23) when _T_5075 : connect remapVecData[23], Queue2_UInt8_2.io.deq.bits connect remapVecValids[23], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_5076 = eq(UInt<2>(0h3), remapindex_23) when _T_5076 : connect remapVecData[23], Queue2_UInt8_3.io.deq.bits connect remapVecValids[23], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_5077 = eq(UInt<3>(0h4), remapindex_23) when _T_5077 : connect remapVecData[23], Queue2_UInt8_4.io.deq.bits connect remapVecValids[23], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_5078 = eq(UInt<3>(0h5), remapindex_23) when _T_5078 : connect remapVecData[23], Queue2_UInt8_5.io.deq.bits connect remapVecValids[23], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_5079 = eq(UInt<3>(0h6), remapindex_23) when _T_5079 : connect remapVecData[23], Queue2_UInt8_6.io.deq.bits connect remapVecValids[23], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_5080 = eq(UInt<3>(0h7), remapindex_23) when _T_5080 : connect remapVecData[23], Queue2_UInt8_7.io.deq.bits connect remapVecValids[23], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_5081 = eq(UInt<4>(0h8), remapindex_23) when _T_5081 : connect remapVecData[23], Queue2_UInt8_8.io.deq.bits connect remapVecValids[23], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_5082 = eq(UInt<4>(0h9), remapindex_23) when _T_5082 : connect remapVecData[23], Queue2_UInt8_9.io.deq.bits connect remapVecValids[23], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_5083 = eq(UInt<4>(0ha), remapindex_23) when _T_5083 : connect remapVecData[23], Queue2_UInt8_10.io.deq.bits connect remapVecValids[23], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_5084 = eq(UInt<4>(0hb), remapindex_23) when _T_5084 : connect remapVecData[23], Queue2_UInt8_11.io.deq.bits connect remapVecValids[23], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_5085 = eq(UInt<4>(0hc), remapindex_23) when _T_5085 : connect remapVecData[23], Queue2_UInt8_12.io.deq.bits connect remapVecValids[23], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_5086 = eq(UInt<4>(0hd), remapindex_23) when _T_5086 : connect remapVecData[23], Queue2_UInt8_13.io.deq.bits connect remapVecValids[23], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_5087 = eq(UInt<4>(0he), remapindex_23) when _T_5087 : connect remapVecData[23], Queue2_UInt8_14.io.deq.bits connect remapVecValids[23], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_5088 = eq(UInt<4>(0hf), remapindex_23) when _T_5088 : connect remapVecData[23], Queue2_UInt8_15.io.deq.bits connect remapVecValids[23], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_5089 = eq(UInt<5>(0h10), remapindex_23) when _T_5089 : connect remapVecData[23], Queue2_UInt8_16.io.deq.bits connect remapVecValids[23], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_5090 = eq(UInt<5>(0h11), remapindex_23) when _T_5090 : connect remapVecData[23], Queue2_UInt8_17.io.deq.bits connect remapVecValids[23], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_5091 = eq(UInt<5>(0h12), remapindex_23) when _T_5091 : connect remapVecData[23], Queue2_UInt8_18.io.deq.bits connect remapVecValids[23], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_5092 = eq(UInt<5>(0h13), remapindex_23) when _T_5092 : connect remapVecData[23], Queue2_UInt8_19.io.deq.bits connect remapVecValids[23], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_5093 = eq(UInt<5>(0h14), remapindex_23) when _T_5093 : connect remapVecData[23], Queue2_UInt8_20.io.deq.bits connect remapVecValids[23], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_5094 = eq(UInt<5>(0h15), remapindex_23) when _T_5094 : connect remapVecData[23], Queue2_UInt8_21.io.deq.bits connect remapVecValids[23], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_5095 = eq(UInt<5>(0h16), remapindex_23) when _T_5095 : connect remapVecData[23], Queue2_UInt8_22.io.deq.bits connect remapVecValids[23], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_5096 = eq(UInt<5>(0h17), remapindex_23) when _T_5096 : connect remapVecData[23], Queue2_UInt8_23.io.deq.bits connect remapVecValids[23], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_5097 = eq(UInt<5>(0h18), remapindex_23) when _T_5097 : connect remapVecData[23], Queue2_UInt8_24.io.deq.bits connect remapVecValids[23], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_5098 = eq(UInt<5>(0h19), remapindex_23) when _T_5098 : connect remapVecData[23], Queue2_UInt8_25.io.deq.bits connect remapVecValids[23], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_5099 = eq(UInt<5>(0h1a), remapindex_23) when _T_5099 : connect remapVecData[23], Queue2_UInt8_26.io.deq.bits connect remapVecValids[23], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_5100 = eq(UInt<5>(0h1b), remapindex_23) when _T_5100 : connect remapVecData[23], Queue2_UInt8_27.io.deq.bits connect remapVecValids[23], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_5101 = eq(UInt<5>(0h1c), remapindex_23) when _T_5101 : connect remapVecData[23], Queue2_UInt8_28.io.deq.bits connect remapVecValids[23], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_5102 = eq(UInt<5>(0h1d), remapindex_23) when _T_5102 : connect remapVecData[23], Queue2_UInt8_29.io.deq.bits connect remapVecValids[23], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_5103 = eq(UInt<5>(0h1e), remapindex_23) when _T_5103 : connect remapVecData[23], Queue2_UInt8_30.io.deq.bits connect remapVecValids[23], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_5104 = eq(UInt<5>(0h1f), remapindex_23) when _T_5104 : connect remapVecData[23], Queue2_UInt8_31.io.deq.bits connect remapVecValids[23], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_5105 = eq(UInt<1>(0h0), remapindex_24) when _T_5105 : connect remapVecData[24], Queue2_UInt8.io.deq.bits connect remapVecValids[24], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[24] node _T_5106 = eq(UInt<1>(0h1), remapindex_24) when _T_5106 : connect remapVecData[24], Queue2_UInt8_1.io.deq.bits connect remapVecValids[24], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_5107 = eq(UInt<2>(0h2), remapindex_24) when _T_5107 : connect remapVecData[24], Queue2_UInt8_2.io.deq.bits connect remapVecValids[24], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_5108 = eq(UInt<2>(0h3), remapindex_24) when _T_5108 : connect remapVecData[24], Queue2_UInt8_3.io.deq.bits connect remapVecValids[24], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_5109 = eq(UInt<3>(0h4), remapindex_24) when _T_5109 : connect remapVecData[24], Queue2_UInt8_4.io.deq.bits connect remapVecValids[24], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_5110 = eq(UInt<3>(0h5), remapindex_24) when _T_5110 : connect remapVecData[24], Queue2_UInt8_5.io.deq.bits connect remapVecValids[24], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_5111 = eq(UInt<3>(0h6), remapindex_24) when _T_5111 : connect remapVecData[24], Queue2_UInt8_6.io.deq.bits connect remapVecValids[24], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_5112 = eq(UInt<3>(0h7), remapindex_24) when _T_5112 : connect remapVecData[24], Queue2_UInt8_7.io.deq.bits connect remapVecValids[24], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_5113 = eq(UInt<4>(0h8), remapindex_24) when _T_5113 : connect remapVecData[24], Queue2_UInt8_8.io.deq.bits connect remapVecValids[24], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_5114 = eq(UInt<4>(0h9), remapindex_24) when _T_5114 : connect remapVecData[24], Queue2_UInt8_9.io.deq.bits connect remapVecValids[24], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_5115 = eq(UInt<4>(0ha), remapindex_24) when _T_5115 : connect remapVecData[24], Queue2_UInt8_10.io.deq.bits connect remapVecValids[24], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_5116 = eq(UInt<4>(0hb), remapindex_24) when _T_5116 : connect remapVecData[24], Queue2_UInt8_11.io.deq.bits connect remapVecValids[24], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_5117 = eq(UInt<4>(0hc), remapindex_24) when _T_5117 : connect remapVecData[24], Queue2_UInt8_12.io.deq.bits connect remapVecValids[24], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_5118 = eq(UInt<4>(0hd), remapindex_24) when _T_5118 : connect remapVecData[24], Queue2_UInt8_13.io.deq.bits connect remapVecValids[24], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_5119 = eq(UInt<4>(0he), remapindex_24) when _T_5119 : connect remapVecData[24], Queue2_UInt8_14.io.deq.bits connect remapVecValids[24], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_5120 = eq(UInt<4>(0hf), remapindex_24) when _T_5120 : connect remapVecData[24], Queue2_UInt8_15.io.deq.bits connect remapVecValids[24], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_5121 = eq(UInt<5>(0h10), remapindex_24) when _T_5121 : connect remapVecData[24], Queue2_UInt8_16.io.deq.bits connect remapVecValids[24], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_5122 = eq(UInt<5>(0h11), remapindex_24) when _T_5122 : connect remapVecData[24], Queue2_UInt8_17.io.deq.bits connect remapVecValids[24], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_5123 = eq(UInt<5>(0h12), remapindex_24) when _T_5123 : connect remapVecData[24], Queue2_UInt8_18.io.deq.bits connect remapVecValids[24], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_5124 = eq(UInt<5>(0h13), remapindex_24) when _T_5124 : connect remapVecData[24], Queue2_UInt8_19.io.deq.bits connect remapVecValids[24], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_5125 = eq(UInt<5>(0h14), remapindex_24) when _T_5125 : connect remapVecData[24], Queue2_UInt8_20.io.deq.bits connect remapVecValids[24], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_5126 = eq(UInt<5>(0h15), remapindex_24) when _T_5126 : connect remapVecData[24], Queue2_UInt8_21.io.deq.bits connect remapVecValids[24], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_5127 = eq(UInt<5>(0h16), remapindex_24) when _T_5127 : connect remapVecData[24], Queue2_UInt8_22.io.deq.bits connect remapVecValids[24], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_5128 = eq(UInt<5>(0h17), remapindex_24) when _T_5128 : connect remapVecData[24], Queue2_UInt8_23.io.deq.bits connect remapVecValids[24], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_5129 = eq(UInt<5>(0h18), remapindex_24) when _T_5129 : connect remapVecData[24], Queue2_UInt8_24.io.deq.bits connect remapVecValids[24], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_5130 = eq(UInt<5>(0h19), remapindex_24) when _T_5130 : connect remapVecData[24], Queue2_UInt8_25.io.deq.bits connect remapVecValids[24], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_5131 = eq(UInt<5>(0h1a), remapindex_24) when _T_5131 : connect remapVecData[24], Queue2_UInt8_26.io.deq.bits connect remapVecValids[24], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_5132 = eq(UInt<5>(0h1b), remapindex_24) when _T_5132 : connect remapVecData[24], Queue2_UInt8_27.io.deq.bits connect remapVecValids[24], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_5133 = eq(UInt<5>(0h1c), remapindex_24) when _T_5133 : connect remapVecData[24], Queue2_UInt8_28.io.deq.bits connect remapVecValids[24], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_5134 = eq(UInt<5>(0h1d), remapindex_24) when _T_5134 : connect remapVecData[24], Queue2_UInt8_29.io.deq.bits connect remapVecValids[24], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_5135 = eq(UInt<5>(0h1e), remapindex_24) when _T_5135 : connect remapVecData[24], Queue2_UInt8_30.io.deq.bits connect remapVecValids[24], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_5136 = eq(UInt<5>(0h1f), remapindex_24) when _T_5136 : connect remapVecData[24], Queue2_UInt8_31.io.deq.bits connect remapVecValids[24], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_5137 = eq(UInt<1>(0h0), remapindex_25) when _T_5137 : connect remapVecData[25], Queue2_UInt8.io.deq.bits connect remapVecValids[25], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[25] node _T_5138 = eq(UInt<1>(0h1), remapindex_25) when _T_5138 : connect remapVecData[25], Queue2_UInt8_1.io.deq.bits connect remapVecValids[25], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_5139 = eq(UInt<2>(0h2), remapindex_25) when _T_5139 : connect remapVecData[25], Queue2_UInt8_2.io.deq.bits connect remapVecValids[25], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_5140 = eq(UInt<2>(0h3), remapindex_25) when _T_5140 : connect remapVecData[25], Queue2_UInt8_3.io.deq.bits connect remapVecValids[25], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_5141 = eq(UInt<3>(0h4), remapindex_25) when _T_5141 : connect remapVecData[25], Queue2_UInt8_4.io.deq.bits connect remapVecValids[25], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_5142 = eq(UInt<3>(0h5), remapindex_25) when _T_5142 : connect remapVecData[25], Queue2_UInt8_5.io.deq.bits connect remapVecValids[25], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_5143 = eq(UInt<3>(0h6), remapindex_25) when _T_5143 : connect remapVecData[25], Queue2_UInt8_6.io.deq.bits connect remapVecValids[25], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_5144 = eq(UInt<3>(0h7), remapindex_25) when _T_5144 : connect remapVecData[25], Queue2_UInt8_7.io.deq.bits connect remapVecValids[25], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_5145 = eq(UInt<4>(0h8), remapindex_25) when _T_5145 : connect remapVecData[25], Queue2_UInt8_8.io.deq.bits connect remapVecValids[25], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_5146 = eq(UInt<4>(0h9), remapindex_25) when _T_5146 : connect remapVecData[25], Queue2_UInt8_9.io.deq.bits connect remapVecValids[25], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_5147 = eq(UInt<4>(0ha), remapindex_25) when _T_5147 : connect remapVecData[25], Queue2_UInt8_10.io.deq.bits connect remapVecValids[25], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_5148 = eq(UInt<4>(0hb), remapindex_25) when _T_5148 : connect remapVecData[25], Queue2_UInt8_11.io.deq.bits connect remapVecValids[25], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_5149 = eq(UInt<4>(0hc), remapindex_25) when _T_5149 : connect remapVecData[25], Queue2_UInt8_12.io.deq.bits connect remapVecValids[25], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_5150 = eq(UInt<4>(0hd), remapindex_25) when _T_5150 : connect remapVecData[25], Queue2_UInt8_13.io.deq.bits connect remapVecValids[25], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_5151 = eq(UInt<4>(0he), remapindex_25) when _T_5151 : connect remapVecData[25], Queue2_UInt8_14.io.deq.bits connect remapVecValids[25], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_5152 = eq(UInt<4>(0hf), remapindex_25) when _T_5152 : connect remapVecData[25], Queue2_UInt8_15.io.deq.bits connect remapVecValids[25], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_5153 = eq(UInt<5>(0h10), remapindex_25) when _T_5153 : connect remapVecData[25], Queue2_UInt8_16.io.deq.bits connect remapVecValids[25], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_5154 = eq(UInt<5>(0h11), remapindex_25) when _T_5154 : connect remapVecData[25], Queue2_UInt8_17.io.deq.bits connect remapVecValids[25], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_5155 = eq(UInt<5>(0h12), remapindex_25) when _T_5155 : connect remapVecData[25], Queue2_UInt8_18.io.deq.bits connect remapVecValids[25], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_5156 = eq(UInt<5>(0h13), remapindex_25) when _T_5156 : connect remapVecData[25], Queue2_UInt8_19.io.deq.bits connect remapVecValids[25], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_5157 = eq(UInt<5>(0h14), remapindex_25) when _T_5157 : connect remapVecData[25], Queue2_UInt8_20.io.deq.bits connect remapVecValids[25], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_5158 = eq(UInt<5>(0h15), remapindex_25) when _T_5158 : connect remapVecData[25], Queue2_UInt8_21.io.deq.bits connect remapVecValids[25], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_5159 = eq(UInt<5>(0h16), remapindex_25) when _T_5159 : connect remapVecData[25], Queue2_UInt8_22.io.deq.bits connect remapVecValids[25], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_5160 = eq(UInt<5>(0h17), remapindex_25) when _T_5160 : connect remapVecData[25], Queue2_UInt8_23.io.deq.bits connect remapVecValids[25], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_5161 = eq(UInt<5>(0h18), remapindex_25) when _T_5161 : connect remapVecData[25], Queue2_UInt8_24.io.deq.bits connect remapVecValids[25], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_5162 = eq(UInt<5>(0h19), remapindex_25) when _T_5162 : connect remapVecData[25], Queue2_UInt8_25.io.deq.bits connect remapVecValids[25], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_5163 = eq(UInt<5>(0h1a), remapindex_25) when _T_5163 : connect remapVecData[25], Queue2_UInt8_26.io.deq.bits connect remapVecValids[25], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_5164 = eq(UInt<5>(0h1b), remapindex_25) when _T_5164 : connect remapVecData[25], Queue2_UInt8_27.io.deq.bits connect remapVecValids[25], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_5165 = eq(UInt<5>(0h1c), remapindex_25) when _T_5165 : connect remapVecData[25], Queue2_UInt8_28.io.deq.bits connect remapVecValids[25], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_5166 = eq(UInt<5>(0h1d), remapindex_25) when _T_5166 : connect remapVecData[25], Queue2_UInt8_29.io.deq.bits connect remapVecValids[25], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_5167 = eq(UInt<5>(0h1e), remapindex_25) when _T_5167 : connect remapVecData[25], Queue2_UInt8_30.io.deq.bits connect remapVecValids[25], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_5168 = eq(UInt<5>(0h1f), remapindex_25) when _T_5168 : connect remapVecData[25], Queue2_UInt8_31.io.deq.bits connect remapVecValids[25], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_5169 = eq(UInt<1>(0h0), remapindex_26) when _T_5169 : connect remapVecData[26], Queue2_UInt8.io.deq.bits connect remapVecValids[26], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[26] node _T_5170 = eq(UInt<1>(0h1), remapindex_26) when _T_5170 : connect remapVecData[26], Queue2_UInt8_1.io.deq.bits connect remapVecValids[26], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_5171 = eq(UInt<2>(0h2), remapindex_26) when _T_5171 : connect remapVecData[26], Queue2_UInt8_2.io.deq.bits connect remapVecValids[26], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_5172 = eq(UInt<2>(0h3), remapindex_26) when _T_5172 : connect remapVecData[26], Queue2_UInt8_3.io.deq.bits connect remapVecValids[26], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_5173 = eq(UInt<3>(0h4), remapindex_26) when _T_5173 : connect remapVecData[26], Queue2_UInt8_4.io.deq.bits connect remapVecValids[26], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_5174 = eq(UInt<3>(0h5), remapindex_26) when _T_5174 : connect remapVecData[26], Queue2_UInt8_5.io.deq.bits connect remapVecValids[26], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_5175 = eq(UInt<3>(0h6), remapindex_26) when _T_5175 : connect remapVecData[26], Queue2_UInt8_6.io.deq.bits connect remapVecValids[26], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_5176 = eq(UInt<3>(0h7), remapindex_26) when _T_5176 : connect remapVecData[26], Queue2_UInt8_7.io.deq.bits connect remapVecValids[26], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_5177 = eq(UInt<4>(0h8), remapindex_26) when _T_5177 : connect remapVecData[26], Queue2_UInt8_8.io.deq.bits connect remapVecValids[26], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_5178 = eq(UInt<4>(0h9), remapindex_26) when _T_5178 : connect remapVecData[26], Queue2_UInt8_9.io.deq.bits connect remapVecValids[26], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_5179 = eq(UInt<4>(0ha), remapindex_26) when _T_5179 : connect remapVecData[26], Queue2_UInt8_10.io.deq.bits connect remapVecValids[26], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_5180 = eq(UInt<4>(0hb), remapindex_26) when _T_5180 : connect remapVecData[26], Queue2_UInt8_11.io.deq.bits connect remapVecValids[26], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_5181 = eq(UInt<4>(0hc), remapindex_26) when _T_5181 : connect remapVecData[26], Queue2_UInt8_12.io.deq.bits connect remapVecValids[26], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_5182 = eq(UInt<4>(0hd), remapindex_26) when _T_5182 : connect remapVecData[26], Queue2_UInt8_13.io.deq.bits connect remapVecValids[26], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_5183 = eq(UInt<4>(0he), remapindex_26) when _T_5183 : connect remapVecData[26], Queue2_UInt8_14.io.deq.bits connect remapVecValids[26], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_5184 = eq(UInt<4>(0hf), remapindex_26) when _T_5184 : connect remapVecData[26], Queue2_UInt8_15.io.deq.bits connect remapVecValids[26], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_5185 = eq(UInt<5>(0h10), remapindex_26) when _T_5185 : connect remapVecData[26], Queue2_UInt8_16.io.deq.bits connect remapVecValids[26], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_5186 = eq(UInt<5>(0h11), remapindex_26) when _T_5186 : connect remapVecData[26], Queue2_UInt8_17.io.deq.bits connect remapVecValids[26], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_5187 = eq(UInt<5>(0h12), remapindex_26) when _T_5187 : connect remapVecData[26], Queue2_UInt8_18.io.deq.bits connect remapVecValids[26], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_5188 = eq(UInt<5>(0h13), remapindex_26) when _T_5188 : connect remapVecData[26], Queue2_UInt8_19.io.deq.bits connect remapVecValids[26], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_5189 = eq(UInt<5>(0h14), remapindex_26) when _T_5189 : connect remapVecData[26], Queue2_UInt8_20.io.deq.bits connect remapVecValids[26], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_5190 = eq(UInt<5>(0h15), remapindex_26) when _T_5190 : connect remapVecData[26], Queue2_UInt8_21.io.deq.bits connect remapVecValids[26], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_5191 = eq(UInt<5>(0h16), remapindex_26) when _T_5191 : connect remapVecData[26], Queue2_UInt8_22.io.deq.bits connect remapVecValids[26], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_5192 = eq(UInt<5>(0h17), remapindex_26) when _T_5192 : connect remapVecData[26], Queue2_UInt8_23.io.deq.bits connect remapVecValids[26], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_5193 = eq(UInt<5>(0h18), remapindex_26) when _T_5193 : connect remapVecData[26], Queue2_UInt8_24.io.deq.bits connect remapVecValids[26], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_5194 = eq(UInt<5>(0h19), remapindex_26) when _T_5194 : connect remapVecData[26], Queue2_UInt8_25.io.deq.bits connect remapVecValids[26], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_5195 = eq(UInt<5>(0h1a), remapindex_26) when _T_5195 : connect remapVecData[26], Queue2_UInt8_26.io.deq.bits connect remapVecValids[26], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_5196 = eq(UInt<5>(0h1b), remapindex_26) when _T_5196 : connect remapVecData[26], Queue2_UInt8_27.io.deq.bits connect remapVecValids[26], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_5197 = eq(UInt<5>(0h1c), remapindex_26) when _T_5197 : connect remapVecData[26], Queue2_UInt8_28.io.deq.bits connect remapVecValids[26], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_5198 = eq(UInt<5>(0h1d), remapindex_26) when _T_5198 : connect remapVecData[26], Queue2_UInt8_29.io.deq.bits connect remapVecValids[26], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_5199 = eq(UInt<5>(0h1e), remapindex_26) when _T_5199 : connect remapVecData[26], Queue2_UInt8_30.io.deq.bits connect remapVecValids[26], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_5200 = eq(UInt<5>(0h1f), remapindex_26) when _T_5200 : connect remapVecData[26], Queue2_UInt8_31.io.deq.bits connect remapVecValids[26], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_5201 = eq(UInt<1>(0h0), remapindex_27) when _T_5201 : connect remapVecData[27], Queue2_UInt8.io.deq.bits connect remapVecValids[27], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[27] node _T_5202 = eq(UInt<1>(0h1), remapindex_27) when _T_5202 : connect remapVecData[27], Queue2_UInt8_1.io.deq.bits connect remapVecValids[27], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_5203 = eq(UInt<2>(0h2), remapindex_27) when _T_5203 : connect remapVecData[27], Queue2_UInt8_2.io.deq.bits connect remapVecValids[27], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_5204 = eq(UInt<2>(0h3), remapindex_27) when _T_5204 : connect remapVecData[27], Queue2_UInt8_3.io.deq.bits connect remapVecValids[27], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_5205 = eq(UInt<3>(0h4), remapindex_27) when _T_5205 : connect remapVecData[27], Queue2_UInt8_4.io.deq.bits connect remapVecValids[27], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_5206 = eq(UInt<3>(0h5), remapindex_27) when _T_5206 : connect remapVecData[27], Queue2_UInt8_5.io.deq.bits connect remapVecValids[27], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_5207 = eq(UInt<3>(0h6), remapindex_27) when _T_5207 : connect remapVecData[27], Queue2_UInt8_6.io.deq.bits connect remapVecValids[27], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_5208 = eq(UInt<3>(0h7), remapindex_27) when _T_5208 : connect remapVecData[27], Queue2_UInt8_7.io.deq.bits connect remapVecValids[27], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_5209 = eq(UInt<4>(0h8), remapindex_27) when _T_5209 : connect remapVecData[27], Queue2_UInt8_8.io.deq.bits connect remapVecValids[27], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_5210 = eq(UInt<4>(0h9), remapindex_27) when _T_5210 : connect remapVecData[27], Queue2_UInt8_9.io.deq.bits connect remapVecValids[27], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_5211 = eq(UInt<4>(0ha), remapindex_27) when _T_5211 : connect remapVecData[27], Queue2_UInt8_10.io.deq.bits connect remapVecValids[27], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_5212 = eq(UInt<4>(0hb), remapindex_27) when _T_5212 : connect remapVecData[27], Queue2_UInt8_11.io.deq.bits connect remapVecValids[27], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_5213 = eq(UInt<4>(0hc), remapindex_27) when _T_5213 : connect remapVecData[27], Queue2_UInt8_12.io.deq.bits connect remapVecValids[27], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_5214 = eq(UInt<4>(0hd), remapindex_27) when _T_5214 : connect remapVecData[27], Queue2_UInt8_13.io.deq.bits connect remapVecValids[27], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_5215 = eq(UInt<4>(0he), remapindex_27) when _T_5215 : connect remapVecData[27], Queue2_UInt8_14.io.deq.bits connect remapVecValids[27], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_5216 = eq(UInt<4>(0hf), remapindex_27) when _T_5216 : connect remapVecData[27], Queue2_UInt8_15.io.deq.bits connect remapVecValids[27], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_5217 = eq(UInt<5>(0h10), remapindex_27) when _T_5217 : connect remapVecData[27], Queue2_UInt8_16.io.deq.bits connect remapVecValids[27], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_5218 = eq(UInt<5>(0h11), remapindex_27) when _T_5218 : connect remapVecData[27], Queue2_UInt8_17.io.deq.bits connect remapVecValids[27], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_5219 = eq(UInt<5>(0h12), remapindex_27) when _T_5219 : connect remapVecData[27], Queue2_UInt8_18.io.deq.bits connect remapVecValids[27], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_5220 = eq(UInt<5>(0h13), remapindex_27) when _T_5220 : connect remapVecData[27], Queue2_UInt8_19.io.deq.bits connect remapVecValids[27], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_5221 = eq(UInt<5>(0h14), remapindex_27) when _T_5221 : connect remapVecData[27], Queue2_UInt8_20.io.deq.bits connect remapVecValids[27], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_5222 = eq(UInt<5>(0h15), remapindex_27) when _T_5222 : connect remapVecData[27], Queue2_UInt8_21.io.deq.bits connect remapVecValids[27], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_5223 = eq(UInt<5>(0h16), remapindex_27) when _T_5223 : connect remapVecData[27], Queue2_UInt8_22.io.deq.bits connect remapVecValids[27], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_5224 = eq(UInt<5>(0h17), remapindex_27) when _T_5224 : connect remapVecData[27], Queue2_UInt8_23.io.deq.bits connect remapVecValids[27], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_5225 = eq(UInt<5>(0h18), remapindex_27) when _T_5225 : connect remapVecData[27], Queue2_UInt8_24.io.deq.bits connect remapVecValids[27], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_5226 = eq(UInt<5>(0h19), remapindex_27) when _T_5226 : connect remapVecData[27], Queue2_UInt8_25.io.deq.bits connect remapVecValids[27], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_5227 = eq(UInt<5>(0h1a), remapindex_27) when _T_5227 : connect remapVecData[27], Queue2_UInt8_26.io.deq.bits connect remapVecValids[27], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_5228 = eq(UInt<5>(0h1b), remapindex_27) when _T_5228 : connect remapVecData[27], Queue2_UInt8_27.io.deq.bits connect remapVecValids[27], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_5229 = eq(UInt<5>(0h1c), remapindex_27) when _T_5229 : connect remapVecData[27], Queue2_UInt8_28.io.deq.bits connect remapVecValids[27], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_5230 = eq(UInt<5>(0h1d), remapindex_27) when _T_5230 : connect remapVecData[27], Queue2_UInt8_29.io.deq.bits connect remapVecValids[27], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_5231 = eq(UInt<5>(0h1e), remapindex_27) when _T_5231 : connect remapVecData[27], Queue2_UInt8_30.io.deq.bits connect remapVecValids[27], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_5232 = eq(UInt<5>(0h1f), remapindex_27) when _T_5232 : connect remapVecData[27], Queue2_UInt8_31.io.deq.bits connect remapVecValids[27], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_5233 = eq(UInt<1>(0h0), remapindex_28) when _T_5233 : connect remapVecData[28], Queue2_UInt8.io.deq.bits connect remapVecValids[28], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[28] node _T_5234 = eq(UInt<1>(0h1), remapindex_28) when _T_5234 : connect remapVecData[28], Queue2_UInt8_1.io.deq.bits connect remapVecValids[28], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_5235 = eq(UInt<2>(0h2), remapindex_28) when _T_5235 : connect remapVecData[28], Queue2_UInt8_2.io.deq.bits connect remapVecValids[28], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_5236 = eq(UInt<2>(0h3), remapindex_28) when _T_5236 : connect remapVecData[28], Queue2_UInt8_3.io.deq.bits connect remapVecValids[28], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_5237 = eq(UInt<3>(0h4), remapindex_28) when _T_5237 : connect remapVecData[28], Queue2_UInt8_4.io.deq.bits connect remapVecValids[28], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_5238 = eq(UInt<3>(0h5), remapindex_28) when _T_5238 : connect remapVecData[28], Queue2_UInt8_5.io.deq.bits connect remapVecValids[28], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_5239 = eq(UInt<3>(0h6), remapindex_28) when _T_5239 : connect remapVecData[28], Queue2_UInt8_6.io.deq.bits connect remapVecValids[28], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_5240 = eq(UInt<3>(0h7), remapindex_28) when _T_5240 : connect remapVecData[28], Queue2_UInt8_7.io.deq.bits connect remapVecValids[28], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_5241 = eq(UInt<4>(0h8), remapindex_28) when _T_5241 : connect remapVecData[28], Queue2_UInt8_8.io.deq.bits connect remapVecValids[28], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_5242 = eq(UInt<4>(0h9), remapindex_28) when _T_5242 : connect remapVecData[28], Queue2_UInt8_9.io.deq.bits connect remapVecValids[28], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_5243 = eq(UInt<4>(0ha), remapindex_28) when _T_5243 : connect remapVecData[28], Queue2_UInt8_10.io.deq.bits connect remapVecValids[28], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_5244 = eq(UInt<4>(0hb), remapindex_28) when _T_5244 : connect remapVecData[28], Queue2_UInt8_11.io.deq.bits connect remapVecValids[28], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_5245 = eq(UInt<4>(0hc), remapindex_28) when _T_5245 : connect remapVecData[28], Queue2_UInt8_12.io.deq.bits connect remapVecValids[28], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_5246 = eq(UInt<4>(0hd), remapindex_28) when _T_5246 : connect remapVecData[28], Queue2_UInt8_13.io.deq.bits connect remapVecValids[28], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_5247 = eq(UInt<4>(0he), remapindex_28) when _T_5247 : connect remapVecData[28], Queue2_UInt8_14.io.deq.bits connect remapVecValids[28], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_5248 = eq(UInt<4>(0hf), remapindex_28) when _T_5248 : connect remapVecData[28], Queue2_UInt8_15.io.deq.bits connect remapVecValids[28], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_5249 = eq(UInt<5>(0h10), remapindex_28) when _T_5249 : connect remapVecData[28], Queue2_UInt8_16.io.deq.bits connect remapVecValids[28], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_5250 = eq(UInt<5>(0h11), remapindex_28) when _T_5250 : connect remapVecData[28], Queue2_UInt8_17.io.deq.bits connect remapVecValids[28], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_5251 = eq(UInt<5>(0h12), remapindex_28) when _T_5251 : connect remapVecData[28], Queue2_UInt8_18.io.deq.bits connect remapVecValids[28], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_5252 = eq(UInt<5>(0h13), remapindex_28) when _T_5252 : connect remapVecData[28], Queue2_UInt8_19.io.deq.bits connect remapVecValids[28], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_5253 = eq(UInt<5>(0h14), remapindex_28) when _T_5253 : connect remapVecData[28], Queue2_UInt8_20.io.deq.bits connect remapVecValids[28], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_5254 = eq(UInt<5>(0h15), remapindex_28) when _T_5254 : connect remapVecData[28], Queue2_UInt8_21.io.deq.bits connect remapVecValids[28], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_5255 = eq(UInt<5>(0h16), remapindex_28) when _T_5255 : connect remapVecData[28], Queue2_UInt8_22.io.deq.bits connect remapVecValids[28], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_5256 = eq(UInt<5>(0h17), remapindex_28) when _T_5256 : connect remapVecData[28], Queue2_UInt8_23.io.deq.bits connect remapVecValids[28], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_5257 = eq(UInt<5>(0h18), remapindex_28) when _T_5257 : connect remapVecData[28], Queue2_UInt8_24.io.deq.bits connect remapVecValids[28], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_5258 = eq(UInt<5>(0h19), remapindex_28) when _T_5258 : connect remapVecData[28], Queue2_UInt8_25.io.deq.bits connect remapVecValids[28], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_5259 = eq(UInt<5>(0h1a), remapindex_28) when _T_5259 : connect remapVecData[28], Queue2_UInt8_26.io.deq.bits connect remapVecValids[28], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_5260 = eq(UInt<5>(0h1b), remapindex_28) when _T_5260 : connect remapVecData[28], Queue2_UInt8_27.io.deq.bits connect remapVecValids[28], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_5261 = eq(UInt<5>(0h1c), remapindex_28) when _T_5261 : connect remapVecData[28], Queue2_UInt8_28.io.deq.bits connect remapVecValids[28], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_5262 = eq(UInt<5>(0h1d), remapindex_28) when _T_5262 : connect remapVecData[28], Queue2_UInt8_29.io.deq.bits connect remapVecValids[28], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_5263 = eq(UInt<5>(0h1e), remapindex_28) when _T_5263 : connect remapVecData[28], Queue2_UInt8_30.io.deq.bits connect remapVecValids[28], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_5264 = eq(UInt<5>(0h1f), remapindex_28) when _T_5264 : connect remapVecData[28], Queue2_UInt8_31.io.deq.bits connect remapVecValids[28], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_5265 = eq(UInt<1>(0h0), remapindex_29) when _T_5265 : connect remapVecData[29], Queue2_UInt8.io.deq.bits connect remapVecValids[29], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[29] node _T_5266 = eq(UInt<1>(0h1), remapindex_29) when _T_5266 : connect remapVecData[29], Queue2_UInt8_1.io.deq.bits connect remapVecValids[29], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_5267 = eq(UInt<2>(0h2), remapindex_29) when _T_5267 : connect remapVecData[29], Queue2_UInt8_2.io.deq.bits connect remapVecValids[29], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_5268 = eq(UInt<2>(0h3), remapindex_29) when _T_5268 : connect remapVecData[29], Queue2_UInt8_3.io.deq.bits connect remapVecValids[29], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_5269 = eq(UInt<3>(0h4), remapindex_29) when _T_5269 : connect remapVecData[29], Queue2_UInt8_4.io.deq.bits connect remapVecValids[29], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_5270 = eq(UInt<3>(0h5), remapindex_29) when _T_5270 : connect remapVecData[29], Queue2_UInt8_5.io.deq.bits connect remapVecValids[29], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_5271 = eq(UInt<3>(0h6), remapindex_29) when _T_5271 : connect remapVecData[29], Queue2_UInt8_6.io.deq.bits connect remapVecValids[29], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_5272 = eq(UInt<3>(0h7), remapindex_29) when _T_5272 : connect remapVecData[29], Queue2_UInt8_7.io.deq.bits connect remapVecValids[29], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_5273 = eq(UInt<4>(0h8), remapindex_29) when _T_5273 : connect remapVecData[29], Queue2_UInt8_8.io.deq.bits connect remapVecValids[29], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_5274 = eq(UInt<4>(0h9), remapindex_29) when _T_5274 : connect remapVecData[29], Queue2_UInt8_9.io.deq.bits connect remapVecValids[29], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_5275 = eq(UInt<4>(0ha), remapindex_29) when _T_5275 : connect remapVecData[29], Queue2_UInt8_10.io.deq.bits connect remapVecValids[29], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_5276 = eq(UInt<4>(0hb), remapindex_29) when _T_5276 : connect remapVecData[29], Queue2_UInt8_11.io.deq.bits connect remapVecValids[29], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_5277 = eq(UInt<4>(0hc), remapindex_29) when _T_5277 : connect remapVecData[29], Queue2_UInt8_12.io.deq.bits connect remapVecValids[29], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_5278 = eq(UInt<4>(0hd), remapindex_29) when _T_5278 : connect remapVecData[29], Queue2_UInt8_13.io.deq.bits connect remapVecValids[29], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_5279 = eq(UInt<4>(0he), remapindex_29) when _T_5279 : connect remapVecData[29], Queue2_UInt8_14.io.deq.bits connect remapVecValids[29], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_5280 = eq(UInt<4>(0hf), remapindex_29) when _T_5280 : connect remapVecData[29], Queue2_UInt8_15.io.deq.bits connect remapVecValids[29], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_5281 = eq(UInt<5>(0h10), remapindex_29) when _T_5281 : connect remapVecData[29], Queue2_UInt8_16.io.deq.bits connect remapVecValids[29], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_5282 = eq(UInt<5>(0h11), remapindex_29) when _T_5282 : connect remapVecData[29], Queue2_UInt8_17.io.deq.bits connect remapVecValids[29], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_5283 = eq(UInt<5>(0h12), remapindex_29) when _T_5283 : connect remapVecData[29], Queue2_UInt8_18.io.deq.bits connect remapVecValids[29], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_5284 = eq(UInt<5>(0h13), remapindex_29) when _T_5284 : connect remapVecData[29], Queue2_UInt8_19.io.deq.bits connect remapVecValids[29], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_5285 = eq(UInt<5>(0h14), remapindex_29) when _T_5285 : connect remapVecData[29], Queue2_UInt8_20.io.deq.bits connect remapVecValids[29], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_5286 = eq(UInt<5>(0h15), remapindex_29) when _T_5286 : connect remapVecData[29], Queue2_UInt8_21.io.deq.bits connect remapVecValids[29], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_5287 = eq(UInt<5>(0h16), remapindex_29) when _T_5287 : connect remapVecData[29], Queue2_UInt8_22.io.deq.bits connect remapVecValids[29], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_5288 = eq(UInt<5>(0h17), remapindex_29) when _T_5288 : connect remapVecData[29], Queue2_UInt8_23.io.deq.bits connect remapVecValids[29], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_5289 = eq(UInt<5>(0h18), remapindex_29) when _T_5289 : connect remapVecData[29], Queue2_UInt8_24.io.deq.bits connect remapVecValids[29], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_5290 = eq(UInt<5>(0h19), remapindex_29) when _T_5290 : connect remapVecData[29], Queue2_UInt8_25.io.deq.bits connect remapVecValids[29], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_5291 = eq(UInt<5>(0h1a), remapindex_29) when _T_5291 : connect remapVecData[29], Queue2_UInt8_26.io.deq.bits connect remapVecValids[29], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_5292 = eq(UInt<5>(0h1b), remapindex_29) when _T_5292 : connect remapVecData[29], Queue2_UInt8_27.io.deq.bits connect remapVecValids[29], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_5293 = eq(UInt<5>(0h1c), remapindex_29) when _T_5293 : connect remapVecData[29], Queue2_UInt8_28.io.deq.bits connect remapVecValids[29], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_5294 = eq(UInt<5>(0h1d), remapindex_29) when _T_5294 : connect remapVecData[29], Queue2_UInt8_29.io.deq.bits connect remapVecValids[29], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_5295 = eq(UInt<5>(0h1e), remapindex_29) when _T_5295 : connect remapVecData[29], Queue2_UInt8_30.io.deq.bits connect remapVecValids[29], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_5296 = eq(UInt<5>(0h1f), remapindex_29) when _T_5296 : connect remapVecData[29], Queue2_UInt8_31.io.deq.bits connect remapVecValids[29], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_5297 = eq(UInt<1>(0h0), remapindex_30) when _T_5297 : connect remapVecData[30], Queue2_UInt8.io.deq.bits connect remapVecValids[30], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[30] node _T_5298 = eq(UInt<1>(0h1), remapindex_30) when _T_5298 : connect remapVecData[30], Queue2_UInt8_1.io.deq.bits connect remapVecValids[30], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_5299 = eq(UInt<2>(0h2), remapindex_30) when _T_5299 : connect remapVecData[30], Queue2_UInt8_2.io.deq.bits connect remapVecValids[30], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_5300 = eq(UInt<2>(0h3), remapindex_30) when _T_5300 : connect remapVecData[30], Queue2_UInt8_3.io.deq.bits connect remapVecValids[30], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_5301 = eq(UInt<3>(0h4), remapindex_30) when _T_5301 : connect remapVecData[30], Queue2_UInt8_4.io.deq.bits connect remapVecValids[30], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_5302 = eq(UInt<3>(0h5), remapindex_30) when _T_5302 : connect remapVecData[30], Queue2_UInt8_5.io.deq.bits connect remapVecValids[30], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_5303 = eq(UInt<3>(0h6), remapindex_30) when _T_5303 : connect remapVecData[30], Queue2_UInt8_6.io.deq.bits connect remapVecValids[30], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_5304 = eq(UInt<3>(0h7), remapindex_30) when _T_5304 : connect remapVecData[30], Queue2_UInt8_7.io.deq.bits connect remapVecValids[30], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_5305 = eq(UInt<4>(0h8), remapindex_30) when _T_5305 : connect remapVecData[30], Queue2_UInt8_8.io.deq.bits connect remapVecValids[30], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_5306 = eq(UInt<4>(0h9), remapindex_30) when _T_5306 : connect remapVecData[30], Queue2_UInt8_9.io.deq.bits connect remapVecValids[30], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_5307 = eq(UInt<4>(0ha), remapindex_30) when _T_5307 : connect remapVecData[30], Queue2_UInt8_10.io.deq.bits connect remapVecValids[30], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_5308 = eq(UInt<4>(0hb), remapindex_30) when _T_5308 : connect remapVecData[30], Queue2_UInt8_11.io.deq.bits connect remapVecValids[30], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_5309 = eq(UInt<4>(0hc), remapindex_30) when _T_5309 : connect remapVecData[30], Queue2_UInt8_12.io.deq.bits connect remapVecValids[30], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_5310 = eq(UInt<4>(0hd), remapindex_30) when _T_5310 : connect remapVecData[30], Queue2_UInt8_13.io.deq.bits connect remapVecValids[30], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_5311 = eq(UInt<4>(0he), remapindex_30) when _T_5311 : connect remapVecData[30], Queue2_UInt8_14.io.deq.bits connect remapVecValids[30], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_5312 = eq(UInt<4>(0hf), remapindex_30) when _T_5312 : connect remapVecData[30], Queue2_UInt8_15.io.deq.bits connect remapVecValids[30], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_5313 = eq(UInt<5>(0h10), remapindex_30) when _T_5313 : connect remapVecData[30], Queue2_UInt8_16.io.deq.bits connect remapVecValids[30], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_5314 = eq(UInt<5>(0h11), remapindex_30) when _T_5314 : connect remapVecData[30], Queue2_UInt8_17.io.deq.bits connect remapVecValids[30], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_5315 = eq(UInt<5>(0h12), remapindex_30) when _T_5315 : connect remapVecData[30], Queue2_UInt8_18.io.deq.bits connect remapVecValids[30], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_5316 = eq(UInt<5>(0h13), remapindex_30) when _T_5316 : connect remapVecData[30], Queue2_UInt8_19.io.deq.bits connect remapVecValids[30], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_5317 = eq(UInt<5>(0h14), remapindex_30) when _T_5317 : connect remapVecData[30], Queue2_UInt8_20.io.deq.bits connect remapVecValids[30], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_5318 = eq(UInt<5>(0h15), remapindex_30) when _T_5318 : connect remapVecData[30], Queue2_UInt8_21.io.deq.bits connect remapVecValids[30], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_5319 = eq(UInt<5>(0h16), remapindex_30) when _T_5319 : connect remapVecData[30], Queue2_UInt8_22.io.deq.bits connect remapVecValids[30], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_5320 = eq(UInt<5>(0h17), remapindex_30) when _T_5320 : connect remapVecData[30], Queue2_UInt8_23.io.deq.bits connect remapVecValids[30], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_5321 = eq(UInt<5>(0h18), remapindex_30) when _T_5321 : connect remapVecData[30], Queue2_UInt8_24.io.deq.bits connect remapVecValids[30], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_5322 = eq(UInt<5>(0h19), remapindex_30) when _T_5322 : connect remapVecData[30], Queue2_UInt8_25.io.deq.bits connect remapVecValids[30], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_5323 = eq(UInt<5>(0h1a), remapindex_30) when _T_5323 : connect remapVecData[30], Queue2_UInt8_26.io.deq.bits connect remapVecValids[30], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_5324 = eq(UInt<5>(0h1b), remapindex_30) when _T_5324 : connect remapVecData[30], Queue2_UInt8_27.io.deq.bits connect remapVecValids[30], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_5325 = eq(UInt<5>(0h1c), remapindex_30) when _T_5325 : connect remapVecData[30], Queue2_UInt8_28.io.deq.bits connect remapVecValids[30], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_5326 = eq(UInt<5>(0h1d), remapindex_30) when _T_5326 : connect remapVecData[30], Queue2_UInt8_29.io.deq.bits connect remapVecValids[30], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_5327 = eq(UInt<5>(0h1e), remapindex_30) when _T_5327 : connect remapVecData[30], Queue2_UInt8_30.io.deq.bits connect remapVecValids[30], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_5328 = eq(UInt<5>(0h1f), remapindex_30) when _T_5328 : connect remapVecData[30], Queue2_UInt8_31.io.deq.bits connect remapVecValids[30], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_5329 = eq(UInt<1>(0h0), remapindex_31) when _T_5329 : connect remapVecData[31], Queue2_UInt8.io.deq.bits connect remapVecValids[31], Queue2_UInt8.io.deq.valid connect Queue2_UInt8.io.deq.ready, remapVecReadys[31] node _T_5330 = eq(UInt<1>(0h1), remapindex_31) when _T_5330 : connect remapVecData[31], Queue2_UInt8_1.io.deq.bits connect remapVecValids[31], Queue2_UInt8_1.io.deq.valid connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_5331 = eq(UInt<2>(0h2), remapindex_31) when _T_5331 : connect remapVecData[31], Queue2_UInt8_2.io.deq.bits connect remapVecValids[31], Queue2_UInt8_2.io.deq.valid connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_5332 = eq(UInt<2>(0h3), remapindex_31) when _T_5332 : connect remapVecData[31], Queue2_UInt8_3.io.deq.bits connect remapVecValids[31], Queue2_UInt8_3.io.deq.valid connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_5333 = eq(UInt<3>(0h4), remapindex_31) when _T_5333 : connect remapVecData[31], Queue2_UInt8_4.io.deq.bits connect remapVecValids[31], Queue2_UInt8_4.io.deq.valid connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_5334 = eq(UInt<3>(0h5), remapindex_31) when _T_5334 : connect remapVecData[31], Queue2_UInt8_5.io.deq.bits connect remapVecValids[31], Queue2_UInt8_5.io.deq.valid connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_5335 = eq(UInt<3>(0h6), remapindex_31) when _T_5335 : connect remapVecData[31], Queue2_UInt8_6.io.deq.bits connect remapVecValids[31], Queue2_UInt8_6.io.deq.valid connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_5336 = eq(UInt<3>(0h7), remapindex_31) when _T_5336 : connect remapVecData[31], Queue2_UInt8_7.io.deq.bits connect remapVecValids[31], Queue2_UInt8_7.io.deq.valid connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_5337 = eq(UInt<4>(0h8), remapindex_31) when _T_5337 : connect remapVecData[31], Queue2_UInt8_8.io.deq.bits connect remapVecValids[31], Queue2_UInt8_8.io.deq.valid connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_5338 = eq(UInt<4>(0h9), remapindex_31) when _T_5338 : connect remapVecData[31], Queue2_UInt8_9.io.deq.bits connect remapVecValids[31], Queue2_UInt8_9.io.deq.valid connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_5339 = eq(UInt<4>(0ha), remapindex_31) when _T_5339 : connect remapVecData[31], Queue2_UInt8_10.io.deq.bits connect remapVecValids[31], Queue2_UInt8_10.io.deq.valid connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_5340 = eq(UInt<4>(0hb), remapindex_31) when _T_5340 : connect remapVecData[31], Queue2_UInt8_11.io.deq.bits connect remapVecValids[31], Queue2_UInt8_11.io.deq.valid connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_5341 = eq(UInt<4>(0hc), remapindex_31) when _T_5341 : connect remapVecData[31], Queue2_UInt8_12.io.deq.bits connect remapVecValids[31], Queue2_UInt8_12.io.deq.valid connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_5342 = eq(UInt<4>(0hd), remapindex_31) when _T_5342 : connect remapVecData[31], Queue2_UInt8_13.io.deq.bits connect remapVecValids[31], Queue2_UInt8_13.io.deq.valid connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_5343 = eq(UInt<4>(0he), remapindex_31) when _T_5343 : connect remapVecData[31], Queue2_UInt8_14.io.deq.bits connect remapVecValids[31], Queue2_UInt8_14.io.deq.valid connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_5344 = eq(UInt<4>(0hf), remapindex_31) when _T_5344 : connect remapVecData[31], Queue2_UInt8_15.io.deq.bits connect remapVecValids[31], Queue2_UInt8_15.io.deq.valid connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_5345 = eq(UInt<5>(0h10), remapindex_31) when _T_5345 : connect remapVecData[31], Queue2_UInt8_16.io.deq.bits connect remapVecValids[31], Queue2_UInt8_16.io.deq.valid connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_5346 = eq(UInt<5>(0h11), remapindex_31) when _T_5346 : connect remapVecData[31], Queue2_UInt8_17.io.deq.bits connect remapVecValids[31], Queue2_UInt8_17.io.deq.valid connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_5347 = eq(UInt<5>(0h12), remapindex_31) when _T_5347 : connect remapVecData[31], Queue2_UInt8_18.io.deq.bits connect remapVecValids[31], Queue2_UInt8_18.io.deq.valid connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_5348 = eq(UInt<5>(0h13), remapindex_31) when _T_5348 : connect remapVecData[31], Queue2_UInt8_19.io.deq.bits connect remapVecValids[31], Queue2_UInt8_19.io.deq.valid connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_5349 = eq(UInt<5>(0h14), remapindex_31) when _T_5349 : connect remapVecData[31], Queue2_UInt8_20.io.deq.bits connect remapVecValids[31], Queue2_UInt8_20.io.deq.valid connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_5350 = eq(UInt<5>(0h15), remapindex_31) when _T_5350 : connect remapVecData[31], Queue2_UInt8_21.io.deq.bits connect remapVecValids[31], Queue2_UInt8_21.io.deq.valid connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_5351 = eq(UInt<5>(0h16), remapindex_31) when _T_5351 : connect remapVecData[31], Queue2_UInt8_22.io.deq.bits connect remapVecValids[31], Queue2_UInt8_22.io.deq.valid connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_5352 = eq(UInt<5>(0h17), remapindex_31) when _T_5352 : connect remapVecData[31], Queue2_UInt8_23.io.deq.bits connect remapVecValids[31], Queue2_UInt8_23.io.deq.valid connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_5353 = eq(UInt<5>(0h18), remapindex_31) when _T_5353 : connect remapVecData[31], Queue2_UInt8_24.io.deq.bits connect remapVecValids[31], Queue2_UInt8_24.io.deq.valid connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_5354 = eq(UInt<5>(0h19), remapindex_31) when _T_5354 : connect remapVecData[31], Queue2_UInt8_25.io.deq.bits connect remapVecValids[31], Queue2_UInt8_25.io.deq.valid connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_5355 = eq(UInt<5>(0h1a), remapindex_31) when _T_5355 : connect remapVecData[31], Queue2_UInt8_26.io.deq.bits connect remapVecValids[31], Queue2_UInt8_26.io.deq.valid connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_5356 = eq(UInt<5>(0h1b), remapindex_31) when _T_5356 : connect remapVecData[31], Queue2_UInt8_27.io.deq.bits connect remapVecValids[31], Queue2_UInt8_27.io.deq.valid connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_5357 = eq(UInt<5>(0h1c), remapindex_31) when _T_5357 : connect remapVecData[31], Queue2_UInt8_28.io.deq.bits connect remapVecValids[31], Queue2_UInt8_28.io.deq.valid connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_5358 = eq(UInt<5>(0h1d), remapindex_31) when _T_5358 : connect remapVecData[31], Queue2_UInt8_29.io.deq.bits connect remapVecValids[31], Queue2_UInt8_29.io.deq.valid connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_5359 = eq(UInt<5>(0h1e), remapindex_31) when _T_5359 : connect remapVecData[31], Queue2_UInt8_30.io.deq.bits connect remapVecValids[31], Queue2_UInt8_30.io.deq.valid connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_5360 = eq(UInt<5>(0h1f), remapindex_31) when _T_5360 : connect remapVecData[31], Queue2_UInt8_31.io.deq.bits connect remapVecValids[31], Queue2_UInt8_31.io.deq.valid connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[31] node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) regreset backend_bytes_written : UInt<64>, clock, reset, UInt<64>(0h0) node _backend_next_write_addr_T = add(dest_info_Q.io.deq.bits.op, backend_bytes_written) node backend_next_write_addr = tail(_backend_next_write_addr_T, 1) node _throttle_end_T = sub(buf_lens_Q.io.deq.bits, backend_bytes_written) node _throttle_end_T_1 = tail(_throttle_end_T, 1) node throttle_end = mux(buf_lens_Q.io.deq.valid, _throttle_end_T_1, UInt<6>(0h20)) node _throttle_end_writeable_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_T_6 = mux(_throttle_end_writeable_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _throttle_end_writeable_T_7 = mux(_throttle_end_writeable_T_4, UInt<2>(0h2), _throttle_end_writeable_T_6) node _throttle_end_writeable_T_8 = mux(_throttle_end_writeable_T_3, UInt<3>(0h4), _throttle_end_writeable_T_7) node _throttle_end_writeable_T_9 = mux(_throttle_end_writeable_T_2, UInt<4>(0h8), _throttle_end_writeable_T_8) node _throttle_end_writeable_T_10 = mux(_throttle_end_writeable_T_1, UInt<5>(0h10), _throttle_end_writeable_T_9) node throttle_end_writeable = mux(_throttle_end_writeable_T, UInt<6>(0h20), _throttle_end_writeable_T_10) node _throttle_end_writeable_log2_T = geq(throttle_end, UInt<6>(0h20)) node _throttle_end_writeable_log2_T_1 = bits(throttle_end, 4, 4) node _throttle_end_writeable_log2_T_2 = bits(throttle_end, 3, 3) node _throttle_end_writeable_log2_T_3 = bits(throttle_end, 2, 2) node _throttle_end_writeable_log2_T_4 = bits(throttle_end, 1, 1) node _throttle_end_writeable_log2_T_5 = bits(throttle_end, 0, 0) node _throttle_end_writeable_log2_T_6 = mux(_throttle_end_writeable_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _throttle_end_writeable_log2_T_7 = mux(_throttle_end_writeable_log2_T_4, UInt<1>(0h1), _throttle_end_writeable_log2_T_6) node _throttle_end_writeable_log2_T_8 = mux(_throttle_end_writeable_log2_T_3, UInt<2>(0h2), _throttle_end_writeable_log2_T_7) node _throttle_end_writeable_log2_T_9 = mux(_throttle_end_writeable_log2_T_2, UInt<2>(0h3), _throttle_end_writeable_log2_T_8) node _throttle_end_writeable_log2_T_10 = mux(_throttle_end_writeable_log2_T_1, UInt<3>(0h4), _throttle_end_writeable_log2_T_9) node throttle_end_writeable_log2 = mux(_throttle_end_writeable_log2_T, UInt<3>(0h5), _throttle_end_writeable_log2_T_10) node _ptr_align_max_bytes_writeable_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_T_5 = mux(_ptr_align_max_bytes_writeable_T_4, UInt<5>(0h10), UInt<6>(0h20)) node _ptr_align_max_bytes_writeable_T_6 = mux(_ptr_align_max_bytes_writeable_T_3, UInt<4>(0h8), _ptr_align_max_bytes_writeable_T_5) node _ptr_align_max_bytes_writeable_T_7 = mux(_ptr_align_max_bytes_writeable_T_2, UInt<3>(0h4), _ptr_align_max_bytes_writeable_T_6) node _ptr_align_max_bytes_writeable_T_8 = mux(_ptr_align_max_bytes_writeable_T_1, UInt<2>(0h2), _ptr_align_max_bytes_writeable_T_7) node ptr_align_max_bytes_writeable = mux(_ptr_align_max_bytes_writeable_T, UInt<1>(0h1), _ptr_align_max_bytes_writeable_T_8) node _ptr_align_max_bytes_writeable_log2_T = bits(backend_next_write_addr, 0, 0) node _ptr_align_max_bytes_writeable_log2_T_1 = bits(backend_next_write_addr, 1, 1) node _ptr_align_max_bytes_writeable_log2_T_2 = bits(backend_next_write_addr, 2, 2) node _ptr_align_max_bytes_writeable_log2_T_3 = bits(backend_next_write_addr, 3, 3) node _ptr_align_max_bytes_writeable_log2_T_4 = bits(backend_next_write_addr, 4, 4) node _ptr_align_max_bytes_writeable_log2_T_5 = mux(_ptr_align_max_bytes_writeable_log2_T_4, UInt<3>(0h4), UInt<3>(0h5)) node _ptr_align_max_bytes_writeable_log2_T_6 = mux(_ptr_align_max_bytes_writeable_log2_T_3, UInt<2>(0h3), _ptr_align_max_bytes_writeable_log2_T_5) node _ptr_align_max_bytes_writeable_log2_T_7 = mux(_ptr_align_max_bytes_writeable_log2_T_2, UInt<2>(0h2), _ptr_align_max_bytes_writeable_log2_T_6) node _ptr_align_max_bytes_writeable_log2_T_8 = mux(_ptr_align_max_bytes_writeable_log2_T_1, UInt<1>(0h1), _ptr_align_max_bytes_writeable_log2_T_7) node ptr_align_max_bytes_writeable_log2 = mux(_ptr_align_max_bytes_writeable_log2_T, UInt<1>(0h0), _ptr_align_max_bytes_writeable_log2_T_8) node _count_valids_largest_aligned_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_T_6 = mux(_count_valids_largest_aligned_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _count_valids_largest_aligned_T_7 = mux(_count_valids_largest_aligned_T_4, UInt<2>(0h2), _count_valids_largest_aligned_T_6) node _count_valids_largest_aligned_T_8 = mux(_count_valids_largest_aligned_T_3, UInt<3>(0h4), _count_valids_largest_aligned_T_7) node _count_valids_largest_aligned_T_9 = mux(_count_valids_largest_aligned_T_2, UInt<4>(0h8), _count_valids_largest_aligned_T_8) node _count_valids_largest_aligned_T_10 = mux(_count_valids_largest_aligned_T_1, UInt<5>(0h10), _count_valids_largest_aligned_T_9) node count_valids_largest_aligned = mux(_count_valids_largest_aligned_T, UInt<6>(0h20), _count_valids_largest_aligned_T_10) node _count_valids_largest_aligned_log2_T = bits(count_valids, 5, 5) node _count_valids_largest_aligned_log2_T_1 = bits(count_valids, 4, 4) node _count_valids_largest_aligned_log2_T_2 = bits(count_valids, 3, 3) node _count_valids_largest_aligned_log2_T_3 = bits(count_valids, 2, 2) node _count_valids_largest_aligned_log2_T_4 = bits(count_valids, 1, 1) node _count_valids_largest_aligned_log2_T_5 = bits(count_valids, 0, 0) node _count_valids_largest_aligned_log2_T_6 = mux(_count_valids_largest_aligned_log2_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _count_valids_largest_aligned_log2_T_7 = mux(_count_valids_largest_aligned_log2_T_4, UInt<1>(0h1), _count_valids_largest_aligned_log2_T_6) node _count_valids_largest_aligned_log2_T_8 = mux(_count_valids_largest_aligned_log2_T_3, UInt<2>(0h2), _count_valids_largest_aligned_log2_T_7) node _count_valids_largest_aligned_log2_T_9 = mux(_count_valids_largest_aligned_log2_T_2, UInt<2>(0h3), _count_valids_largest_aligned_log2_T_8) node _count_valids_largest_aligned_log2_T_10 = mux(_count_valids_largest_aligned_log2_T_1, UInt<3>(0h4), _count_valids_largest_aligned_log2_T_9) node count_valids_largest_aligned_log2 = mux(_count_valids_largest_aligned_log2_T, UInt<3>(0h5), _count_valids_largest_aligned_log2_T_10) node _bytes_to_write_T = lt(ptr_align_max_bytes_writeable, count_valids_largest_aligned) node _bytes_to_write_T_1 = lt(ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_2 = mux(_bytes_to_write_T_1, ptr_align_max_bytes_writeable, throttle_end_writeable) node _bytes_to_write_T_3 = lt(count_valids_largest_aligned, throttle_end_writeable) node _bytes_to_write_T_4 = mux(_bytes_to_write_T_3, count_valids_largest_aligned, throttle_end_writeable) node bytes_to_write = mux(_bytes_to_write_T, _bytes_to_write_T_2, _bytes_to_write_T_4) node remapped_write_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node remapped_write_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node remapped_write_data_lo_lo_lo = cat(remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo) node remapped_write_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node remapped_write_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node remapped_write_data_lo_lo_hi = cat(remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo) node remapped_write_data_lo_lo = cat(remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo) node remapped_write_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node remapped_write_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node remapped_write_data_lo_hi_lo = cat(remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo) node remapped_write_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node remapped_write_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node remapped_write_data_lo_hi_hi = cat(remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo) node remapped_write_data_lo_hi = cat(remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo) node remapped_write_data_lo = cat(remapped_write_data_lo_hi, remapped_write_data_lo_lo) node remapped_write_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node remapped_write_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node remapped_write_data_hi_lo_lo = cat(remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo) node remapped_write_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node remapped_write_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node remapped_write_data_hi_lo_hi = cat(remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo) node remapped_write_data_hi_lo = cat(remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo) node remapped_write_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node remapped_write_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node remapped_write_data_hi_hi_lo = cat(remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo) node remapped_write_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node remapped_write_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node remapped_write_data_hi_hi_hi = cat(remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo) node remapped_write_data_hi_hi = cat(remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo) node remapped_write_data_hi = cat(remapped_write_data_hi_hi, remapped_write_data_hi_lo) node remapped_write_data = cat(remapped_write_data_hi, remapped_write_data_lo) node enough_data = neq(bytes_to_write, UInt<1>(0h0)) node _bytes_to_write_log2_T = lt(ptr_align_max_bytes_writeable_log2, count_valids_largest_aligned_log2) node _bytes_to_write_log2_T_1 = lt(ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_2 = mux(_bytes_to_write_log2_T_1, ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_3 = lt(count_valids_largest_aligned_log2, throttle_end_writeable_log2) node _bytes_to_write_log2_T_4 = mux(_bytes_to_write_log2_T_3, count_valids_largest_aligned_log2, throttle_end_writeable_log2) node bytes_to_write_log2 = mux(_bytes_to_write_log2_T, _bytes_to_write_log2_T_2, _bytes_to_write_log2_T_4) node _write_ptr_override_T = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node write_ptr_override = and(buf_lens_Q.io.deq.valid, _write_ptr_override_T) node _T_5361 = eq(write_ptr_override, UInt<1>(0h0)) node _T_5362 = eq(buf_lens_Q.io.deq.bits, backend_bytes_written) node _remapVecReadys_0_T = lt(UInt<1>(0h0), bytes_to_write) node _remapVecReadys_0_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, _T_5361) node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_0_T_4 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_3) connect remapVecReadys[0], _remapVecReadys_0_T_4 node _remapVecReadys_1_T = lt(UInt<1>(0h1), bytes_to_write) node _remapVecReadys_1_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, _T_5361) node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_1_T_4 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_3) connect remapVecReadys[1], _remapVecReadys_1_T_4 node _remapVecReadys_2_T = lt(UInt<2>(0h2), bytes_to_write) node _remapVecReadys_2_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, _T_5361) node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_2_T_4 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_3) connect remapVecReadys[2], _remapVecReadys_2_T_4 node _remapVecReadys_3_T = lt(UInt<2>(0h3), bytes_to_write) node _remapVecReadys_3_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, _T_5361) node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_3_T_4 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_3) connect remapVecReadys[3], _remapVecReadys_3_T_4 node _remapVecReadys_4_T = lt(UInt<3>(0h4), bytes_to_write) node _remapVecReadys_4_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, _T_5361) node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_4_T_4 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_3) connect remapVecReadys[4], _remapVecReadys_4_T_4 node _remapVecReadys_5_T = lt(UInt<3>(0h5), bytes_to_write) node _remapVecReadys_5_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, _T_5361) node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_5_T_4 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_3) connect remapVecReadys[5], _remapVecReadys_5_T_4 node _remapVecReadys_6_T = lt(UInt<3>(0h6), bytes_to_write) node _remapVecReadys_6_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, _T_5361) node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_6_T_4 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_3) connect remapVecReadys[6], _remapVecReadys_6_T_4 node _remapVecReadys_7_T = lt(UInt<3>(0h7), bytes_to_write) node _remapVecReadys_7_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, _T_5361) node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_7_T_4 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_3) connect remapVecReadys[7], _remapVecReadys_7_T_4 node _remapVecReadys_8_T = lt(UInt<4>(0h8), bytes_to_write) node _remapVecReadys_8_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, _T_5361) node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_8_T_4 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_3) connect remapVecReadys[8], _remapVecReadys_8_T_4 node _remapVecReadys_9_T = lt(UInt<4>(0h9), bytes_to_write) node _remapVecReadys_9_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, _T_5361) node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_9_T_4 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_3) connect remapVecReadys[9], _remapVecReadys_9_T_4 node _remapVecReadys_10_T = lt(UInt<4>(0ha), bytes_to_write) node _remapVecReadys_10_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, _T_5361) node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_10_T_4 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_3) connect remapVecReadys[10], _remapVecReadys_10_T_4 node _remapVecReadys_11_T = lt(UInt<4>(0hb), bytes_to_write) node _remapVecReadys_11_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, _T_5361) node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_11_T_4 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_3) connect remapVecReadys[11], _remapVecReadys_11_T_4 node _remapVecReadys_12_T = lt(UInt<4>(0hc), bytes_to_write) node _remapVecReadys_12_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, _T_5361) node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_12_T_4 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_3) connect remapVecReadys[12], _remapVecReadys_12_T_4 node _remapVecReadys_13_T = lt(UInt<4>(0hd), bytes_to_write) node _remapVecReadys_13_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, _T_5361) node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_13_T_4 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_3) connect remapVecReadys[13], _remapVecReadys_13_T_4 node _remapVecReadys_14_T = lt(UInt<4>(0he), bytes_to_write) node _remapVecReadys_14_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, _T_5361) node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_14_T_4 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_3) connect remapVecReadys[14], _remapVecReadys_14_T_4 node _remapVecReadys_15_T = lt(UInt<4>(0hf), bytes_to_write) node _remapVecReadys_15_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, _T_5361) node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_15_T_4 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_3) connect remapVecReadys[15], _remapVecReadys_15_T_4 node _remapVecReadys_16_T = lt(UInt<5>(0h10), bytes_to_write) node _remapVecReadys_16_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, _T_5361) node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_16_T_4 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_3) connect remapVecReadys[16], _remapVecReadys_16_T_4 node _remapVecReadys_17_T = lt(UInt<5>(0h11), bytes_to_write) node _remapVecReadys_17_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, _T_5361) node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_17_T_4 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_3) connect remapVecReadys[17], _remapVecReadys_17_T_4 node _remapVecReadys_18_T = lt(UInt<5>(0h12), bytes_to_write) node _remapVecReadys_18_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, _T_5361) node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_18_T_4 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_3) connect remapVecReadys[18], _remapVecReadys_18_T_4 node _remapVecReadys_19_T = lt(UInt<5>(0h13), bytes_to_write) node _remapVecReadys_19_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, _T_5361) node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_19_T_4 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_3) connect remapVecReadys[19], _remapVecReadys_19_T_4 node _remapVecReadys_20_T = lt(UInt<5>(0h14), bytes_to_write) node _remapVecReadys_20_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, _T_5361) node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_20_T_4 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_3) connect remapVecReadys[20], _remapVecReadys_20_T_4 node _remapVecReadys_21_T = lt(UInt<5>(0h15), bytes_to_write) node _remapVecReadys_21_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, _T_5361) node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_21_T_4 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_3) connect remapVecReadys[21], _remapVecReadys_21_T_4 node _remapVecReadys_22_T = lt(UInt<5>(0h16), bytes_to_write) node _remapVecReadys_22_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, _T_5361) node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_22_T_4 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_3) connect remapVecReadys[22], _remapVecReadys_22_T_4 node _remapVecReadys_23_T = lt(UInt<5>(0h17), bytes_to_write) node _remapVecReadys_23_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, _T_5361) node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_23_T_4 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_3) connect remapVecReadys[23], _remapVecReadys_23_T_4 node _remapVecReadys_24_T = lt(UInt<5>(0h18), bytes_to_write) node _remapVecReadys_24_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, _T_5361) node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_24_T_4 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_3) connect remapVecReadys[24], _remapVecReadys_24_T_4 node _remapVecReadys_25_T = lt(UInt<5>(0h19), bytes_to_write) node _remapVecReadys_25_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, _T_5361) node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_25_T_4 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_3) connect remapVecReadys[25], _remapVecReadys_25_T_4 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), bytes_to_write) node _remapVecReadys_26_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, _T_5361) node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_26_T_4 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_3) connect remapVecReadys[26], _remapVecReadys_26_T_4 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), bytes_to_write) node _remapVecReadys_27_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, _T_5361) node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_27_T_4 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_3) connect remapVecReadys[27], _remapVecReadys_27_T_4 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), bytes_to_write) node _remapVecReadys_28_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, _T_5361) node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_28_T_4 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_3) connect remapVecReadys[28], _remapVecReadys_28_T_4 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), bytes_to_write) node _remapVecReadys_29_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, _T_5361) node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_29_T_4 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_3) connect remapVecReadys[29], _remapVecReadys_29_T_4 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), bytes_to_write) node _remapVecReadys_30_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, _T_5361) node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_30_T_4 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_3) connect remapVecReadys[30], _remapVecReadys_30_T_4 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), bytes_to_write) node _remapVecReadys_31_T_1 = and(io.l2io.req.ready, enough_data) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, _T_5361) node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T_2, dest_info_Q.io.deq.valid) node _remapVecReadys_31_T_4 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_3) connect remapVecReadys[31], _remapVecReadys_31_T_4 node _T_5363 = and(io.l2io.req.ready, enough_data) node _T_5364 = and(_T_5363, _T_5361) node _T_5365 = and(_T_5364, dest_info_Q.io.deq.valid) when _T_5365 : node _read_start_index_T = add(read_start_index, bytes_to_write) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1 node _backend_bytes_written_T = add(backend_bytes_written, bytes_to_write) node _backend_bytes_written_T_1 = tail(_backend_bytes_written_T, 1) connect backend_bytes_written, _backend_bytes_written_T_1 regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_5366 = asUInt(reset) node _T_5367 = eq(_T_5366, UInt<1>(0h0)) when _T_5367 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70 node _T_5368 = asUInt(reset) node _T_5369 = eq(_T_5368, UInt<1>(0h0)) when _T_5369 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] writefire: addr: 0x%x, data 0x%x, size %d\n", io.l2io.req.bits.addr, io.l2io.req.bits.data, io.l2io.req.bits.size) : printf_71 node _io_l2io_req_valid_T = and(enough_data, _T_5361) node _io_l2io_req_valid_T_1 = and(_io_l2io_req_valid_T, dest_info_Q.io.deq.valid) node _io_l2io_req_valid_T_2 = and(buf_lens_Q.io.deq.valid, _T_5362) node _io_l2io_req_valid_T_3 = and(_io_l2io_req_valid_T_2, dest_info_Q.io.deq.valid) node _io_l2io_req_valid_T_4 = or(_io_l2io_req_valid_T_1, _io_l2io_req_valid_T_3) connect io.l2io.req.valid, _io_l2io_req_valid_T_4 node _io_l2io_req_bits_size_T = mux(write_ptr_override, UInt<2>(0h2), bytes_to_write_log2) connect io.l2io.req.bits.size, _io_l2io_req_bits_size_T node _io_l2io_req_bits_addr_T = mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr) connect io.l2io.req.bits.addr, _io_l2io_req_bits_addr_T node _io_l2io_req_bits_data_T = mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpval, remapped_write_data) connect io.l2io.req.bits.data, _io_l2io_req_bits_data_T connect io.l2io.req.bits.cmd, UInt<1>(0h1) node _buf_lens_Q_io_deq_ready_T = and(io.l2io.req.ready, _T_5362) node _buf_lens_Q_io_deq_ready_T_1 = and(_buf_lens_Q_io_deq_ready_T, dest_info_Q.io.deq.valid) connect buf_lens_Q.io.deq.ready, _buf_lens_Q_io_deq_ready_T_1 node _dest_info_Q_io_deq_ready_T = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _dest_info_Q_io_deq_ready_T_1 = and(_dest_info_Q_io_deq_ready_T, _T_5362) connect dest_info_Q.io.deq.ready, _dest_info_Q_io_deq_ready_T_1 regreset bufs_completed : UInt<64>, clock, reset, UInt<64>(0h0) connect io.bufs_completed, bufs_completed connect io.l2io.resp.ready, UInt<1>(0h1) connect io.no_writes_inflight, io.l2io.no_memops_inflight node _T_5370 = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid) node _T_5371 = and(_T_5370, _T_5362) node _T_5372 = and(_T_5371, dest_info_Q.io.deq.valid) when _T_5372 : node _bufs_completed_T = add(bufs_completed, UInt<1>(0h1)) node _bufs_completed_T_1 = tail(_bufs_completed_T, 1) connect bufs_completed, _bufs_completed_T_1 connect backend_bytes_written, UInt<1>(0h0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_5373 = asUInt(reset) node _T_5374 = eq(_T_5373, UInt<1>(0h0)) when _T_5374 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72 node _T_5375 = asUInt(reset) node _T_5376 = eq(_T_5375, UInt<1>(0h0)) when _T_5376 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] write cmpflag addr: 0x%x, write ptr val 0x%x\n", dest_info_Q.io.deq.bits.cmpflag, dest_info_Q.io.deq.bits.cmpval) : printf_73 node _T_5377 = neq(count_valids, UInt<1>(0h0)) when _T_5377 : regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_5378 = asUInt(reset) node _T_5379 = eq(_T_5378, UInt<1>(0h0)) when _T_5379 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74 node _T_5380 = asUInt(reset) node _T_5381 = eq(_T_5380, UInt<1>(0h0)) when _T_5381 : printf(clock, UInt<1>(0h1), "[bhdr_memwriter] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d\n", read_start_index, backend_bytes_written, count_valids, ptr_align_max_bytes_writeable, bytes_to_write, bytes_to_write_log2) : printf_75

module ZstdCompressorMemWriter_1( // @[ZstdCompressorMemWriter.scala:23:7] input clock, // @[ZstdCompressorMemWriter.scala:23:7] input reset, // @[ZstdCompressorMemWriter.scala:23:7] output io_memwrites_in_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_memwrites_in_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_req_ready, // @[ZstdCompressorMemWriter.scala:26:14] output io_l2io_req_valid, // @[ZstdCompressorMemWriter.scala:26:14] output [63:0] io_l2io_req_bits_addr, // @[ZstdCompressorMemWriter.scala:26:14] output [2:0] io_l2io_req_bits_size, // @[ZstdCompressorMemWriter.scala:26:14] output [255:0] io_l2io_req_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_resp_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_l2io_resp_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_no_memops_inflight, // @[ZstdCompressorMemWriter.scala:26:14] output io_dest_info_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_dest_info_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_op, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpflag, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpval // @[ZstdCompressorMemWriter.scala:26:14] ); wire _Queue2_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_31_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_31_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_30_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_30_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_29_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_29_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_28_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_28_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_27_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_27_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_26_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_26_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_25_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_25_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_24_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_24_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_23_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_23_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_22_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_22_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_21_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_21_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_20_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_20_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_19_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_19_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_18_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_18_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_17_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_17_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_16_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_16_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_15_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_15_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_14_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_14_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_13_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_13_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_12_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_12_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_11_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_11_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_10_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_10_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_9_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_9_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_7_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_7_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_6_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_6_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_5_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_5_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_4_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_4_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_3_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_3_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_2_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_2_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_1_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_1_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue2_UInt8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:52:26] wire _buf_lens_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:52:26] wire [63:0] _buf_lens_Q_io_deq_bits; // @[ZstdCompressorMemWriter.scala:52:26] wire _dest_info_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_op; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpval; // @[ZstdCompressorMemWriter.scala:39:27] wire _incoming_writes_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:35:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdCompressorMemWriter.scala:35:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdCompressorMemWriter.scala:35:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_valid_0 = io_dest_info_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_op_0 = io_dest_info_bits_op; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpflag_0 = io_dest_info_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpval_0 = io_dest_info_bits_cmpval; // @[ZstdCompressorMemWriter.scala:23:7] wire [5:0] io_memwrites_in_bits_validbytes = 6'h3; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_bits_end_of_message = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_bits_cmd = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_ready = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:187:50] wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:218:56] wire _io_l2io_req_valid_T_4; // @[ZstdCompressorMemWriter.scala:278:65] wire [63:0] _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:283:31] wire [2:0] _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:282:31] wire [255:0] _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:284:31] wire io_no_writes_inflight = io_l2io_no_memops_inflight_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_l2io_req_bits_addr_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [2:0] io_l2io_req_bits_size_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_req_bits_data_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_valid_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7] wire _dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53] wire _decompress_dest_last_fire_T = _dest_info_Q_io_deq_ready_T_1 & _dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35] reg decompress_dest_last_fire; // @[ZstdCompressorMemWriter.scala:42:42] reg decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43] wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43, :44:94] wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire | _decompress_dest_printhelp_T; // @[ZstdCompressorMemWriter.scala:42:42, :44:{90,94}] wire decompress_dest_printhelp = _dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[ZstdCompressorMemWriter.scala:39:27, :44:{60,90}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] buf_len_tracker; // @[ZstdCompressorMemWriter.scala:57:32] wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53] wire _T_10 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35] wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :57:32, :62:42] wire [64:0] _buf_len_tracker_T; // @[ZstdCompressorMemWriter.scala:62:42] assign _buf_len_tracker_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42] wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[ZstdCompressorMemWriter.scala:112:45] assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42, :112:45] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdCompressorMemWriter.scala:76:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdCompressorMemWriter.scala:76:34, :86:34] wire [6:0] _GEN_0 = _idx_T % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx = _GEN_0[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_1 = _idx_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_1 = _GEN_1[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_2 = _idx_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_2 = _GEN_2[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_3 = _idx_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_3 = _GEN_3[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_4 = _idx_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_4 = _GEN_4[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_5 = _idx_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_5 = _GEN_5[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_6 = _idx_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_6 = _GEN_6[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_7 = _idx_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_7 = _GEN_7[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_8 = _idx_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_8 = _GEN_8[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_9 = _idx_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_9 = _GEN_9[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_10 = _idx_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_10 = _GEN_10[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_11 = _idx_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_11 = _GEN_11[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_12 = _idx_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_12 = _GEN_12[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_13 = _idx_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_13 = _GEN_13[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_14 = _idx_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_14 = _GEN_14[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_15 = _idx_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_15 = _GEN_15[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_16 = _idx_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_16 = _GEN_16[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_17 = _idx_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_17 = _GEN_17[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_18 = _idx_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_18 = _GEN_18[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_19 = _idx_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_19 = _GEN_19[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_20 = _idx_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_20 = _GEN_20[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_21 = _idx_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_21 = _GEN_21[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_22 = _idx_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_22 = _GEN_22[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_23 = _idx_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_23 = _GEN_23[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_24 = _idx_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_24 = _GEN_24[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_25 = _idx_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_25 = _GEN_25[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_26 = _idx_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_26 = _GEN_26[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_27 = _idx_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_27 = _GEN_27[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_28 = _idx_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_28 = _GEN_28[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_29 = _idx_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_29 = _GEN_29[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_30 = _idx_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_30 = _GEN_30[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_31 = _idx_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_31 = _GEN_31[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :86:34, :95:47] wire [6:0] _GEN_32 = wrap_len_index_wide % 7'h20; // @[ZstdCompressorMemWriter.scala:95:47, :96:48] wire [5:0] wrap_len_index_end = _GEN_32[5:0]; // @[ZstdCompressorMemWriter.scala:96:48] wire wrapped = |(wrap_len_index_wide[6:5]); // @[ZstdCompressorMemWriter.scala:95:47, :97:37] wire _all_queues_ready_T = _Queue2_UInt8_io_enq_ready & _Queue2_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue2_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue2_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue2_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue2_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue2_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue2_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue2_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue2_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue2_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue2_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue2_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue2_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue2_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue2_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue2_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue2_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue2_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue2_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue2_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue2_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue2_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue2_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue2_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue2_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue2_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue2_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue2_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue2_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue2_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue2_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33, :103:33] wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:35:33, :52:26, :103:61] wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T | _account_for_buf_lens_Q_T_1; // @[ZstdCompressorMemWriter.scala:103:{33,46,61}] wire _buf_lens_Q_io_enq_valid_T = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53] assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53] wire _GEN_33 = write_start_index == 6'h0; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_3; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_3 = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_1 = |wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_4 = |wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_34 = write_start_index < 6'h2; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_6; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_6 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_9; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_9 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_35 = write_start_index < 6'h3; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_12; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_12 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_15; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_15 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_36 = wrap_len_index_end > 6'h2; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_13 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_16 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_37 = write_start_index < 6'h4; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_18; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_18 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_21; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_21 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_38 = write_start_index < 6'h5; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_24; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_24 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_27; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_27 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_39 = wrap_len_index_end > 6'h4; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_25 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_28 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_40 = write_start_index < 6'h6; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_30; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_30 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_33; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_33 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_41 = wrap_len_index_end > 6'h5; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_31 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_34 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_42 = write_start_index < 6'h7; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_36; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_36 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_39; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_39 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_43 = wrap_len_index_end > 6'h6; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_37 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_40 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_44 = write_start_index < 6'h8; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_42; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_42 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_45; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_45 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_45 = write_start_index < 6'h9; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_48; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_48 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_51; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_51 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_46 = wrap_len_index_end > 6'h8; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_49 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_52 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_47 = write_start_index < 6'hA; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_54; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_54 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_57; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_57 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_48 = wrap_len_index_end > 6'h9; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_55 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_58 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_49 = write_start_index < 6'hB; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_60; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_60 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_63; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_63 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_50 = wrap_len_index_end > 6'hA; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_61 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_64 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_51 = write_start_index < 6'hC; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_66; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_66 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_69; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_69 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_52 = wrap_len_index_end > 6'hB; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_67 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_70 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_53 = write_start_index < 6'hD; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_72; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_72 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_75; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_75 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_54 = wrap_len_index_end > 6'hC; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_73 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_76 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_55 = write_start_index < 6'hE; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_78; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_78 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_81; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_81 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_56 = wrap_len_index_end > 6'hD; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_79 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_82 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_57 = write_start_index < 6'hF; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_84; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_84 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_87; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_87 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_58 = wrap_len_index_end > 6'hE; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_85 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_88 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_59 = write_start_index < 6'h10; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_90; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_90 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_93; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_93 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_60 = write_start_index < 6'h11; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_96; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_96 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_99; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_99 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_61 = wrap_len_index_end > 6'h10; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_97 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_100 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_62 = write_start_index < 6'h12; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_102; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_102 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_105; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_105 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_63 = wrap_len_index_end > 6'h11; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_103 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_106 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_64 = write_start_index < 6'h13; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_108; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_108 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_111; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_111 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_65 = wrap_len_index_end > 6'h12; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_109 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_112 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_66 = write_start_index < 6'h14; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_114; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_114 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_117; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_117 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_67 = wrap_len_index_end > 6'h13; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_115 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_118 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_68 = write_start_index < 6'h15; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_120; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_120 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_123; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_123 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_69 = wrap_len_index_end > 6'h14; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_121 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_124 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_70 = write_start_index < 6'h16; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_126; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_126 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_129; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_129 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_71 = wrap_len_index_end > 6'h15; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_127 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_130 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_72 = write_start_index < 6'h17; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_132; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_132 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_135; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_135 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_73 = wrap_len_index_end > 6'h16; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_133 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_136 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_74 = write_start_index < 6'h18; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_138; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_138 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_141; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_141 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_75 = wrap_len_index_end > 6'h17; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_139 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_142 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_76 = write_start_index < 6'h19; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_144; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_144 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_147; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_147 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_77 = wrap_len_index_end > 6'h18; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_145 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_148 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_78 = write_start_index < 6'h1A; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_150; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_150 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_153; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_153 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_79 = wrap_len_index_end > 6'h19; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_151 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_154 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_80 = write_start_index < 6'h1B; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_156; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_156 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_159; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_159 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_81 = wrap_len_index_end > 6'h1A; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_157 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_160 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_82 = write_start_index < 6'h1C; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_162; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_162 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_165; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_165 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_83 = wrap_len_index_end > 6'h1B; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_163 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_166 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_84 = write_start_index < 6'h1D; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_168; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_168 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_171; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_171 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_85 = wrap_len_index_end > 6'h1C; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_169 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_172 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_86 = write_start_index < 6'h1E; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_174; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_174 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_177; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_177 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_87 = wrap_len_index_end > 6'h1D; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_175 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_178 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_88 = write_start_index < 6'h1F; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_180; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_180 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_183; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_183 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_89 = wrap_len_index_end > 6'h1E; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_181 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_184 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41, :125:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdCompressorMemWriter.scala:139:33] wire [7:0] remapVecData_0; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_1; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_2; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_3; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_4; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_5; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_6; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_7; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_8; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_9; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_10; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_11; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_12; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_13; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_14; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_15; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_16; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_17; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_18; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_19; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_20; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_21; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_22; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_23; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_24; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_25; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_26; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_27; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_28; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_29; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_30; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_31; // @[ZstdCompressorMemWriter.scala:141:26] wire remapVecValids_0; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_1; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_2; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_3; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_4; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_5; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_6; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_7; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_8; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_9; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_10; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_11; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_12; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_13; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_14; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_15; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_16; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_17; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_18; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_19; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_20; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_21; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_22; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_23; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_24; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_25; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_26; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_27; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_28; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_29; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_30; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_31; // @[ZstdCompressorMemWriter.scala:142:28] wire _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire remapVecReadys_0; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_1; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_2; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_3; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_4; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_5; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_6; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_7; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_8; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_9; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_10; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_11; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_12; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_13; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_14; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_15; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_16; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_17; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_18; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_19; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_20; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_21; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_22; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_23; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_24; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_25; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_26; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_27; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_28; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_29; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_30; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_31; // @[ZstdCompressorMemWriter.scala:143:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdCompressorMemWriter.scala:139:33, :153:33] wire [6:0] _GEN_90 = _remapindex_T % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex = _GEN_90[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4337 = remapindex == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4338 = remapindex == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4339 = remapindex == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4340 = remapindex == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4341 = remapindex == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4342 = remapindex == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4343 = remapindex == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4344 = remapindex == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4345 = remapindex == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4346 = remapindex == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4347 = remapindex == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4348 = remapindex == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4349 = remapindex == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4350 = remapindex == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4351 = remapindex == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4352 = remapindex == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4353 = remapindex == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4354 = remapindex == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4355 = remapindex == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4356 = remapindex == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4357 = remapindex == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4358 = remapindex == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4359 = remapindex == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4360 = remapindex == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4361 = remapindex == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4362 = remapindex == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4363 = remapindex == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4364 = remapindex == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4365 = remapindex == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4366 = remapindex == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4367 = remapindex == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4368 = remapindex == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_0 = _T_4368 ? _Queue2_UInt8_31_io_deq_bits : _T_4367 ? _Queue2_UInt8_30_io_deq_bits : _T_4366 ? _Queue2_UInt8_29_io_deq_bits : _T_4365 ? _Queue2_UInt8_28_io_deq_bits : _T_4364 ? _Queue2_UInt8_27_io_deq_bits : _T_4363 ? _Queue2_UInt8_26_io_deq_bits : _T_4362 ? _Queue2_UInt8_25_io_deq_bits : _T_4361 ? _Queue2_UInt8_24_io_deq_bits : _T_4360 ? _Queue2_UInt8_23_io_deq_bits : _T_4359 ? _Queue2_UInt8_22_io_deq_bits : _T_4358 ? _Queue2_UInt8_21_io_deq_bits : _T_4357 ? _Queue2_UInt8_20_io_deq_bits : _T_4356 ? _Queue2_UInt8_19_io_deq_bits : _T_4355 ? _Queue2_UInt8_18_io_deq_bits : _T_4354 ? _Queue2_UInt8_17_io_deq_bits : _T_4353 ? _Queue2_UInt8_16_io_deq_bits : _T_4352 ? _Queue2_UInt8_15_io_deq_bits : _T_4351 ? _Queue2_UInt8_14_io_deq_bits : _T_4350 ? _Queue2_UInt8_13_io_deq_bits : _T_4349 ? _Queue2_UInt8_12_io_deq_bits : _T_4348 ? _Queue2_UInt8_11_io_deq_bits : _T_4347 ? _Queue2_UInt8_10_io_deq_bits : _T_4346 ? _Queue2_UInt8_9_io_deq_bits : _T_4345 ? _Queue2_UInt8_8_io_deq_bits : _T_4344 ? _Queue2_UInt8_7_io_deq_bits : _T_4343 ? _Queue2_UInt8_6_io_deq_bits : _T_4342 ? _Queue2_UInt8_5_io_deq_bits : _T_4341 ? _Queue2_UInt8_4_io_deq_bits : _T_4340 ? _Queue2_UInt8_3_io_deq_bits : _T_4339 ? _Queue2_UInt8_2_io_deq_bits : _T_4338 ? _Queue2_UInt8_1_io_deq_bits : _T_4337 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_0 = _T_4368 ? _Queue2_UInt8_31_io_deq_valid : _T_4367 ? _Queue2_UInt8_30_io_deq_valid : _T_4366 ? _Queue2_UInt8_29_io_deq_valid : _T_4365 ? _Queue2_UInt8_28_io_deq_valid : _T_4364 ? _Queue2_UInt8_27_io_deq_valid : _T_4363 ? _Queue2_UInt8_26_io_deq_valid : _T_4362 ? _Queue2_UInt8_25_io_deq_valid : _T_4361 ? _Queue2_UInt8_24_io_deq_valid : _T_4360 ? _Queue2_UInt8_23_io_deq_valid : _T_4359 ? _Queue2_UInt8_22_io_deq_valid : _T_4358 ? _Queue2_UInt8_21_io_deq_valid : _T_4357 ? _Queue2_UInt8_20_io_deq_valid : _T_4356 ? _Queue2_UInt8_19_io_deq_valid : _T_4355 ? _Queue2_UInt8_18_io_deq_valid : _T_4354 ? _Queue2_UInt8_17_io_deq_valid : _T_4353 ? _Queue2_UInt8_16_io_deq_valid : _T_4352 ? _Queue2_UInt8_15_io_deq_valid : _T_4351 ? _Queue2_UInt8_14_io_deq_valid : _T_4350 ? _Queue2_UInt8_13_io_deq_valid : _T_4349 ? _Queue2_UInt8_12_io_deq_valid : _T_4348 ? _Queue2_UInt8_11_io_deq_valid : _T_4347 ? _Queue2_UInt8_10_io_deq_valid : _T_4346 ? _Queue2_UInt8_9_io_deq_valid : _T_4345 ? _Queue2_UInt8_8_io_deq_valid : _T_4344 ? _Queue2_UInt8_7_io_deq_valid : _T_4343 ? _Queue2_UInt8_6_io_deq_valid : _T_4342 ? _Queue2_UInt8_5_io_deq_valid : _T_4341 ? _Queue2_UInt8_4_io_deq_valid : _T_4340 ? _Queue2_UInt8_3_io_deq_valid : _T_4339 ? _Queue2_UInt8_2_io_deq_valid : _T_4338 ? _Queue2_UInt8_1_io_deq_valid : _T_4337 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_91 = _remapindex_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_1 = _GEN_91[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4369 = remapindex_1 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4370 = remapindex_1 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4371 = remapindex_1 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4372 = remapindex_1 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4373 = remapindex_1 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4374 = remapindex_1 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4375 = remapindex_1 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4376 = remapindex_1 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4377 = remapindex_1 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4378 = remapindex_1 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4379 = remapindex_1 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4380 = remapindex_1 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4381 = remapindex_1 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4382 = remapindex_1 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4383 = remapindex_1 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4384 = remapindex_1 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4385 = remapindex_1 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4386 = remapindex_1 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4387 = remapindex_1 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4388 = remapindex_1 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4389 = remapindex_1 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4390 = remapindex_1 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4391 = remapindex_1 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4392 = remapindex_1 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4393 = remapindex_1 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4394 = remapindex_1 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4395 = remapindex_1 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4396 = remapindex_1 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4397 = remapindex_1 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4398 = remapindex_1 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4399 = remapindex_1 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4400 = remapindex_1 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_1 = _T_4400 ? _Queue2_UInt8_31_io_deq_bits : _T_4399 ? _Queue2_UInt8_30_io_deq_bits : _T_4398 ? _Queue2_UInt8_29_io_deq_bits : _T_4397 ? _Queue2_UInt8_28_io_deq_bits : _T_4396 ? _Queue2_UInt8_27_io_deq_bits : _T_4395 ? _Queue2_UInt8_26_io_deq_bits : _T_4394 ? _Queue2_UInt8_25_io_deq_bits : _T_4393 ? _Queue2_UInt8_24_io_deq_bits : _T_4392 ? _Queue2_UInt8_23_io_deq_bits : _T_4391 ? _Queue2_UInt8_22_io_deq_bits : _T_4390 ? _Queue2_UInt8_21_io_deq_bits : _T_4389 ? _Queue2_UInt8_20_io_deq_bits : _T_4388 ? _Queue2_UInt8_19_io_deq_bits : _T_4387 ? _Queue2_UInt8_18_io_deq_bits : _T_4386 ? _Queue2_UInt8_17_io_deq_bits : _T_4385 ? _Queue2_UInt8_16_io_deq_bits : _T_4384 ? _Queue2_UInt8_15_io_deq_bits : _T_4383 ? _Queue2_UInt8_14_io_deq_bits : _T_4382 ? _Queue2_UInt8_13_io_deq_bits : _T_4381 ? _Queue2_UInt8_12_io_deq_bits : _T_4380 ? _Queue2_UInt8_11_io_deq_bits : _T_4379 ? _Queue2_UInt8_10_io_deq_bits : _T_4378 ? _Queue2_UInt8_9_io_deq_bits : _T_4377 ? _Queue2_UInt8_8_io_deq_bits : _T_4376 ? _Queue2_UInt8_7_io_deq_bits : _T_4375 ? _Queue2_UInt8_6_io_deq_bits : _T_4374 ? _Queue2_UInt8_5_io_deq_bits : _T_4373 ? _Queue2_UInt8_4_io_deq_bits : _T_4372 ? _Queue2_UInt8_3_io_deq_bits : _T_4371 ? _Queue2_UInt8_2_io_deq_bits : _T_4370 ? _Queue2_UInt8_1_io_deq_bits : _T_4369 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_1 = _T_4400 ? _Queue2_UInt8_31_io_deq_valid : _T_4399 ? _Queue2_UInt8_30_io_deq_valid : _T_4398 ? _Queue2_UInt8_29_io_deq_valid : _T_4397 ? _Queue2_UInt8_28_io_deq_valid : _T_4396 ? _Queue2_UInt8_27_io_deq_valid : _T_4395 ? _Queue2_UInt8_26_io_deq_valid : _T_4394 ? _Queue2_UInt8_25_io_deq_valid : _T_4393 ? _Queue2_UInt8_24_io_deq_valid : _T_4392 ? _Queue2_UInt8_23_io_deq_valid : _T_4391 ? _Queue2_UInt8_22_io_deq_valid : _T_4390 ? _Queue2_UInt8_21_io_deq_valid : _T_4389 ? _Queue2_UInt8_20_io_deq_valid : _T_4388 ? _Queue2_UInt8_19_io_deq_valid : _T_4387 ? _Queue2_UInt8_18_io_deq_valid : _T_4386 ? _Queue2_UInt8_17_io_deq_valid : _T_4385 ? _Queue2_UInt8_16_io_deq_valid : _T_4384 ? _Queue2_UInt8_15_io_deq_valid : _T_4383 ? _Queue2_UInt8_14_io_deq_valid : _T_4382 ? _Queue2_UInt8_13_io_deq_valid : _T_4381 ? _Queue2_UInt8_12_io_deq_valid : _T_4380 ? _Queue2_UInt8_11_io_deq_valid : _T_4379 ? _Queue2_UInt8_10_io_deq_valid : _T_4378 ? _Queue2_UInt8_9_io_deq_valid : _T_4377 ? _Queue2_UInt8_8_io_deq_valid : _T_4376 ? _Queue2_UInt8_7_io_deq_valid : _T_4375 ? _Queue2_UInt8_6_io_deq_valid : _T_4374 ? _Queue2_UInt8_5_io_deq_valid : _T_4373 ? _Queue2_UInt8_4_io_deq_valid : _T_4372 ? _Queue2_UInt8_3_io_deq_valid : _T_4371 ? _Queue2_UInt8_2_io_deq_valid : _T_4370 ? _Queue2_UInt8_1_io_deq_valid : _T_4369 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_92 = _remapindex_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_2 = _GEN_92[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4401 = remapindex_2 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4402 = remapindex_2 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4403 = remapindex_2 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4404 = remapindex_2 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4405 = remapindex_2 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4406 = remapindex_2 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4407 = remapindex_2 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4408 = remapindex_2 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4409 = remapindex_2 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4410 = remapindex_2 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4411 = remapindex_2 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4412 = remapindex_2 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4413 = remapindex_2 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4414 = remapindex_2 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4415 = remapindex_2 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4416 = remapindex_2 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4417 = remapindex_2 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4418 = remapindex_2 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4419 = remapindex_2 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4420 = remapindex_2 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4421 = remapindex_2 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4422 = remapindex_2 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4423 = remapindex_2 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4424 = remapindex_2 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4425 = remapindex_2 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4426 = remapindex_2 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4427 = remapindex_2 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4428 = remapindex_2 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4429 = remapindex_2 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4430 = remapindex_2 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4431 = remapindex_2 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4432 = remapindex_2 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_2 = _T_4432 ? _Queue2_UInt8_31_io_deq_bits : _T_4431 ? _Queue2_UInt8_30_io_deq_bits : _T_4430 ? _Queue2_UInt8_29_io_deq_bits : _T_4429 ? _Queue2_UInt8_28_io_deq_bits : _T_4428 ? _Queue2_UInt8_27_io_deq_bits : _T_4427 ? _Queue2_UInt8_26_io_deq_bits : _T_4426 ? _Queue2_UInt8_25_io_deq_bits : _T_4425 ? _Queue2_UInt8_24_io_deq_bits : _T_4424 ? _Queue2_UInt8_23_io_deq_bits : _T_4423 ? _Queue2_UInt8_22_io_deq_bits : _T_4422 ? _Queue2_UInt8_21_io_deq_bits : _T_4421 ? _Queue2_UInt8_20_io_deq_bits : _T_4420 ? _Queue2_UInt8_19_io_deq_bits : _T_4419 ? _Queue2_UInt8_18_io_deq_bits : _T_4418 ? _Queue2_UInt8_17_io_deq_bits : _T_4417 ? _Queue2_UInt8_16_io_deq_bits : _T_4416 ? _Queue2_UInt8_15_io_deq_bits : _T_4415 ? _Queue2_UInt8_14_io_deq_bits : _T_4414 ? _Queue2_UInt8_13_io_deq_bits : _T_4413 ? _Queue2_UInt8_12_io_deq_bits : _T_4412 ? _Queue2_UInt8_11_io_deq_bits : _T_4411 ? _Queue2_UInt8_10_io_deq_bits : _T_4410 ? _Queue2_UInt8_9_io_deq_bits : _T_4409 ? _Queue2_UInt8_8_io_deq_bits : _T_4408 ? _Queue2_UInt8_7_io_deq_bits : _T_4407 ? _Queue2_UInt8_6_io_deq_bits : _T_4406 ? _Queue2_UInt8_5_io_deq_bits : _T_4405 ? _Queue2_UInt8_4_io_deq_bits : _T_4404 ? _Queue2_UInt8_3_io_deq_bits : _T_4403 ? _Queue2_UInt8_2_io_deq_bits : _T_4402 ? _Queue2_UInt8_1_io_deq_bits : _T_4401 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_2 = _T_4432 ? _Queue2_UInt8_31_io_deq_valid : _T_4431 ? _Queue2_UInt8_30_io_deq_valid : _T_4430 ? _Queue2_UInt8_29_io_deq_valid : _T_4429 ? _Queue2_UInt8_28_io_deq_valid : _T_4428 ? _Queue2_UInt8_27_io_deq_valid : _T_4427 ? _Queue2_UInt8_26_io_deq_valid : _T_4426 ? _Queue2_UInt8_25_io_deq_valid : _T_4425 ? _Queue2_UInt8_24_io_deq_valid : _T_4424 ? _Queue2_UInt8_23_io_deq_valid : _T_4423 ? _Queue2_UInt8_22_io_deq_valid : _T_4422 ? _Queue2_UInt8_21_io_deq_valid : _T_4421 ? _Queue2_UInt8_20_io_deq_valid : _T_4420 ? _Queue2_UInt8_19_io_deq_valid : _T_4419 ? _Queue2_UInt8_18_io_deq_valid : _T_4418 ? _Queue2_UInt8_17_io_deq_valid : _T_4417 ? _Queue2_UInt8_16_io_deq_valid : _T_4416 ? _Queue2_UInt8_15_io_deq_valid : _T_4415 ? _Queue2_UInt8_14_io_deq_valid : _T_4414 ? _Queue2_UInt8_13_io_deq_valid : _T_4413 ? _Queue2_UInt8_12_io_deq_valid : _T_4412 ? _Queue2_UInt8_11_io_deq_valid : _T_4411 ? _Queue2_UInt8_10_io_deq_valid : _T_4410 ? _Queue2_UInt8_9_io_deq_valid : _T_4409 ? _Queue2_UInt8_8_io_deq_valid : _T_4408 ? _Queue2_UInt8_7_io_deq_valid : _T_4407 ? _Queue2_UInt8_6_io_deq_valid : _T_4406 ? _Queue2_UInt8_5_io_deq_valid : _T_4405 ? _Queue2_UInt8_4_io_deq_valid : _T_4404 ? _Queue2_UInt8_3_io_deq_valid : _T_4403 ? _Queue2_UInt8_2_io_deq_valid : _T_4402 ? _Queue2_UInt8_1_io_deq_valid : _T_4401 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_93 = _remapindex_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_3 = _GEN_93[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4433 = remapindex_3 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4434 = remapindex_3 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4435 = remapindex_3 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4436 = remapindex_3 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4437 = remapindex_3 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4438 = remapindex_3 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4439 = remapindex_3 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4440 = remapindex_3 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4441 = remapindex_3 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4442 = remapindex_3 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4443 = remapindex_3 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4444 = remapindex_3 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4445 = remapindex_3 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4446 = remapindex_3 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4447 = remapindex_3 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4448 = remapindex_3 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4449 = remapindex_3 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4450 = remapindex_3 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4451 = remapindex_3 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4452 = remapindex_3 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4453 = remapindex_3 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4454 = remapindex_3 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4455 = remapindex_3 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4456 = remapindex_3 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4457 = remapindex_3 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4458 = remapindex_3 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4459 = remapindex_3 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4460 = remapindex_3 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4461 = remapindex_3 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4462 = remapindex_3 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4463 = remapindex_3 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4464 = remapindex_3 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_3 = _T_4464 ? _Queue2_UInt8_31_io_deq_bits : _T_4463 ? _Queue2_UInt8_30_io_deq_bits : _T_4462 ? _Queue2_UInt8_29_io_deq_bits : _T_4461 ? _Queue2_UInt8_28_io_deq_bits : _T_4460 ? _Queue2_UInt8_27_io_deq_bits : _T_4459 ? _Queue2_UInt8_26_io_deq_bits : _T_4458 ? _Queue2_UInt8_25_io_deq_bits : _T_4457 ? _Queue2_UInt8_24_io_deq_bits : _T_4456 ? _Queue2_UInt8_23_io_deq_bits : _T_4455 ? _Queue2_UInt8_22_io_deq_bits : _T_4454 ? _Queue2_UInt8_21_io_deq_bits : _T_4453 ? _Queue2_UInt8_20_io_deq_bits : _T_4452 ? _Queue2_UInt8_19_io_deq_bits : _T_4451 ? _Queue2_UInt8_18_io_deq_bits : _T_4450 ? _Queue2_UInt8_17_io_deq_bits : _T_4449 ? _Queue2_UInt8_16_io_deq_bits : _T_4448 ? _Queue2_UInt8_15_io_deq_bits : _T_4447 ? _Queue2_UInt8_14_io_deq_bits : _T_4446 ? _Queue2_UInt8_13_io_deq_bits : _T_4445 ? _Queue2_UInt8_12_io_deq_bits : _T_4444 ? _Queue2_UInt8_11_io_deq_bits : _T_4443 ? _Queue2_UInt8_10_io_deq_bits : _T_4442 ? _Queue2_UInt8_9_io_deq_bits : _T_4441 ? _Queue2_UInt8_8_io_deq_bits : _T_4440 ? _Queue2_UInt8_7_io_deq_bits : _T_4439 ? _Queue2_UInt8_6_io_deq_bits : _T_4438 ? _Queue2_UInt8_5_io_deq_bits : _T_4437 ? _Queue2_UInt8_4_io_deq_bits : _T_4436 ? _Queue2_UInt8_3_io_deq_bits : _T_4435 ? _Queue2_UInt8_2_io_deq_bits : _T_4434 ? _Queue2_UInt8_1_io_deq_bits : _T_4433 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_3 = _T_4464 ? _Queue2_UInt8_31_io_deq_valid : _T_4463 ? _Queue2_UInt8_30_io_deq_valid : _T_4462 ? _Queue2_UInt8_29_io_deq_valid : _T_4461 ? _Queue2_UInt8_28_io_deq_valid : _T_4460 ? _Queue2_UInt8_27_io_deq_valid : _T_4459 ? _Queue2_UInt8_26_io_deq_valid : _T_4458 ? _Queue2_UInt8_25_io_deq_valid : _T_4457 ? _Queue2_UInt8_24_io_deq_valid : _T_4456 ? _Queue2_UInt8_23_io_deq_valid : _T_4455 ? _Queue2_UInt8_22_io_deq_valid : _T_4454 ? _Queue2_UInt8_21_io_deq_valid : _T_4453 ? _Queue2_UInt8_20_io_deq_valid : _T_4452 ? _Queue2_UInt8_19_io_deq_valid : _T_4451 ? _Queue2_UInt8_18_io_deq_valid : _T_4450 ? _Queue2_UInt8_17_io_deq_valid : _T_4449 ? _Queue2_UInt8_16_io_deq_valid : _T_4448 ? _Queue2_UInt8_15_io_deq_valid : _T_4447 ? _Queue2_UInt8_14_io_deq_valid : _T_4446 ? _Queue2_UInt8_13_io_deq_valid : _T_4445 ? _Queue2_UInt8_12_io_deq_valid : _T_4444 ? _Queue2_UInt8_11_io_deq_valid : _T_4443 ? _Queue2_UInt8_10_io_deq_valid : _T_4442 ? _Queue2_UInt8_9_io_deq_valid : _T_4441 ? _Queue2_UInt8_8_io_deq_valid : _T_4440 ? _Queue2_UInt8_7_io_deq_valid : _T_4439 ? _Queue2_UInt8_6_io_deq_valid : _T_4438 ? _Queue2_UInt8_5_io_deq_valid : _T_4437 ? _Queue2_UInt8_4_io_deq_valid : _T_4436 ? _Queue2_UInt8_3_io_deq_valid : _T_4435 ? _Queue2_UInt8_2_io_deq_valid : _T_4434 ? _Queue2_UInt8_1_io_deq_valid : _T_4433 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_94 = _remapindex_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_4 = _GEN_94[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4465 = remapindex_4 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4466 = remapindex_4 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4467 = remapindex_4 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4468 = remapindex_4 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4469 = remapindex_4 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4470 = remapindex_4 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4471 = remapindex_4 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4472 = remapindex_4 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4473 = remapindex_4 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4474 = remapindex_4 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4475 = remapindex_4 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4476 = remapindex_4 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4477 = remapindex_4 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4478 = remapindex_4 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4479 = remapindex_4 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4480 = remapindex_4 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4481 = remapindex_4 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4482 = remapindex_4 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4483 = remapindex_4 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4484 = remapindex_4 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4485 = remapindex_4 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4486 = remapindex_4 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4487 = remapindex_4 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4488 = remapindex_4 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4489 = remapindex_4 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4490 = remapindex_4 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4491 = remapindex_4 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4492 = remapindex_4 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4493 = remapindex_4 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4494 = remapindex_4 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4495 = remapindex_4 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4496 = remapindex_4 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_4 = _T_4496 ? _Queue2_UInt8_31_io_deq_bits : _T_4495 ? _Queue2_UInt8_30_io_deq_bits : _T_4494 ? _Queue2_UInt8_29_io_deq_bits : _T_4493 ? _Queue2_UInt8_28_io_deq_bits : _T_4492 ? _Queue2_UInt8_27_io_deq_bits : _T_4491 ? _Queue2_UInt8_26_io_deq_bits : _T_4490 ? _Queue2_UInt8_25_io_deq_bits : _T_4489 ? _Queue2_UInt8_24_io_deq_bits : _T_4488 ? _Queue2_UInt8_23_io_deq_bits : _T_4487 ? _Queue2_UInt8_22_io_deq_bits : _T_4486 ? _Queue2_UInt8_21_io_deq_bits : _T_4485 ? _Queue2_UInt8_20_io_deq_bits : _T_4484 ? _Queue2_UInt8_19_io_deq_bits : _T_4483 ? _Queue2_UInt8_18_io_deq_bits : _T_4482 ? _Queue2_UInt8_17_io_deq_bits : _T_4481 ? _Queue2_UInt8_16_io_deq_bits : _T_4480 ? _Queue2_UInt8_15_io_deq_bits : _T_4479 ? _Queue2_UInt8_14_io_deq_bits : _T_4478 ? _Queue2_UInt8_13_io_deq_bits : _T_4477 ? _Queue2_UInt8_12_io_deq_bits : _T_4476 ? _Queue2_UInt8_11_io_deq_bits : _T_4475 ? _Queue2_UInt8_10_io_deq_bits : _T_4474 ? _Queue2_UInt8_9_io_deq_bits : _T_4473 ? _Queue2_UInt8_8_io_deq_bits : _T_4472 ? _Queue2_UInt8_7_io_deq_bits : _T_4471 ? _Queue2_UInt8_6_io_deq_bits : _T_4470 ? _Queue2_UInt8_5_io_deq_bits : _T_4469 ? _Queue2_UInt8_4_io_deq_bits : _T_4468 ? _Queue2_UInt8_3_io_deq_bits : _T_4467 ? _Queue2_UInt8_2_io_deq_bits : _T_4466 ? _Queue2_UInt8_1_io_deq_bits : _T_4465 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_4 = _T_4496 ? _Queue2_UInt8_31_io_deq_valid : _T_4495 ? _Queue2_UInt8_30_io_deq_valid : _T_4494 ? _Queue2_UInt8_29_io_deq_valid : _T_4493 ? _Queue2_UInt8_28_io_deq_valid : _T_4492 ? _Queue2_UInt8_27_io_deq_valid : _T_4491 ? _Queue2_UInt8_26_io_deq_valid : _T_4490 ? _Queue2_UInt8_25_io_deq_valid : _T_4489 ? _Queue2_UInt8_24_io_deq_valid : _T_4488 ? _Queue2_UInt8_23_io_deq_valid : _T_4487 ? _Queue2_UInt8_22_io_deq_valid : _T_4486 ? _Queue2_UInt8_21_io_deq_valid : _T_4485 ? _Queue2_UInt8_20_io_deq_valid : _T_4484 ? _Queue2_UInt8_19_io_deq_valid : _T_4483 ? _Queue2_UInt8_18_io_deq_valid : _T_4482 ? _Queue2_UInt8_17_io_deq_valid : _T_4481 ? _Queue2_UInt8_16_io_deq_valid : _T_4480 ? _Queue2_UInt8_15_io_deq_valid : _T_4479 ? _Queue2_UInt8_14_io_deq_valid : _T_4478 ? _Queue2_UInt8_13_io_deq_valid : _T_4477 ? _Queue2_UInt8_12_io_deq_valid : _T_4476 ? _Queue2_UInt8_11_io_deq_valid : _T_4475 ? _Queue2_UInt8_10_io_deq_valid : _T_4474 ? _Queue2_UInt8_9_io_deq_valid : _T_4473 ? _Queue2_UInt8_8_io_deq_valid : _T_4472 ? _Queue2_UInt8_7_io_deq_valid : _T_4471 ? _Queue2_UInt8_6_io_deq_valid : _T_4470 ? _Queue2_UInt8_5_io_deq_valid : _T_4469 ? _Queue2_UInt8_4_io_deq_valid : _T_4468 ? _Queue2_UInt8_3_io_deq_valid : _T_4467 ? _Queue2_UInt8_2_io_deq_valid : _T_4466 ? _Queue2_UInt8_1_io_deq_valid : _T_4465 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_95 = _remapindex_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_5 = _GEN_95[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4497 = remapindex_5 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4498 = remapindex_5 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4499 = remapindex_5 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4500 = remapindex_5 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4501 = remapindex_5 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4502 = remapindex_5 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4503 = remapindex_5 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4504 = remapindex_5 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4505 = remapindex_5 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4506 = remapindex_5 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4507 = remapindex_5 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4508 = remapindex_5 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4509 = remapindex_5 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4510 = remapindex_5 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4511 = remapindex_5 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4512 = remapindex_5 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4513 = remapindex_5 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4514 = remapindex_5 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4515 = remapindex_5 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4516 = remapindex_5 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4517 = remapindex_5 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4518 = remapindex_5 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4519 = remapindex_5 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4520 = remapindex_5 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4521 = remapindex_5 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4522 = remapindex_5 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4523 = remapindex_5 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4524 = remapindex_5 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4525 = remapindex_5 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4526 = remapindex_5 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4527 = remapindex_5 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4528 = remapindex_5 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_5 = _T_4528 ? _Queue2_UInt8_31_io_deq_bits : _T_4527 ? _Queue2_UInt8_30_io_deq_bits : _T_4526 ? _Queue2_UInt8_29_io_deq_bits : _T_4525 ? _Queue2_UInt8_28_io_deq_bits : _T_4524 ? _Queue2_UInt8_27_io_deq_bits : _T_4523 ? _Queue2_UInt8_26_io_deq_bits : _T_4522 ? _Queue2_UInt8_25_io_deq_bits : _T_4521 ? _Queue2_UInt8_24_io_deq_bits : _T_4520 ? _Queue2_UInt8_23_io_deq_bits : _T_4519 ? _Queue2_UInt8_22_io_deq_bits : _T_4518 ? _Queue2_UInt8_21_io_deq_bits : _T_4517 ? _Queue2_UInt8_20_io_deq_bits : _T_4516 ? _Queue2_UInt8_19_io_deq_bits : _T_4515 ? _Queue2_UInt8_18_io_deq_bits : _T_4514 ? _Queue2_UInt8_17_io_deq_bits : _T_4513 ? _Queue2_UInt8_16_io_deq_bits : _T_4512 ? _Queue2_UInt8_15_io_deq_bits : _T_4511 ? _Queue2_UInt8_14_io_deq_bits : _T_4510 ? _Queue2_UInt8_13_io_deq_bits : _T_4509 ? _Queue2_UInt8_12_io_deq_bits : _T_4508 ? _Queue2_UInt8_11_io_deq_bits : _T_4507 ? _Queue2_UInt8_10_io_deq_bits : _T_4506 ? _Queue2_UInt8_9_io_deq_bits : _T_4505 ? _Queue2_UInt8_8_io_deq_bits : _T_4504 ? _Queue2_UInt8_7_io_deq_bits : _T_4503 ? _Queue2_UInt8_6_io_deq_bits : _T_4502 ? _Queue2_UInt8_5_io_deq_bits : _T_4501 ? _Queue2_UInt8_4_io_deq_bits : _T_4500 ? _Queue2_UInt8_3_io_deq_bits : _T_4499 ? _Queue2_UInt8_2_io_deq_bits : _T_4498 ? _Queue2_UInt8_1_io_deq_bits : _T_4497 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_5 = _T_4528 ? _Queue2_UInt8_31_io_deq_valid : _T_4527 ? _Queue2_UInt8_30_io_deq_valid : _T_4526 ? _Queue2_UInt8_29_io_deq_valid : _T_4525 ? _Queue2_UInt8_28_io_deq_valid : _T_4524 ? _Queue2_UInt8_27_io_deq_valid : _T_4523 ? _Queue2_UInt8_26_io_deq_valid : _T_4522 ? _Queue2_UInt8_25_io_deq_valid : _T_4521 ? _Queue2_UInt8_24_io_deq_valid : _T_4520 ? _Queue2_UInt8_23_io_deq_valid : _T_4519 ? _Queue2_UInt8_22_io_deq_valid : _T_4518 ? _Queue2_UInt8_21_io_deq_valid : _T_4517 ? _Queue2_UInt8_20_io_deq_valid : _T_4516 ? _Queue2_UInt8_19_io_deq_valid : _T_4515 ? _Queue2_UInt8_18_io_deq_valid : _T_4514 ? _Queue2_UInt8_17_io_deq_valid : _T_4513 ? _Queue2_UInt8_16_io_deq_valid : _T_4512 ? _Queue2_UInt8_15_io_deq_valid : _T_4511 ? _Queue2_UInt8_14_io_deq_valid : _T_4510 ? _Queue2_UInt8_13_io_deq_valid : _T_4509 ? _Queue2_UInt8_12_io_deq_valid : _T_4508 ? _Queue2_UInt8_11_io_deq_valid : _T_4507 ? _Queue2_UInt8_10_io_deq_valid : _T_4506 ? _Queue2_UInt8_9_io_deq_valid : _T_4505 ? _Queue2_UInt8_8_io_deq_valid : _T_4504 ? _Queue2_UInt8_7_io_deq_valid : _T_4503 ? _Queue2_UInt8_6_io_deq_valid : _T_4502 ? _Queue2_UInt8_5_io_deq_valid : _T_4501 ? _Queue2_UInt8_4_io_deq_valid : _T_4500 ? _Queue2_UInt8_3_io_deq_valid : _T_4499 ? _Queue2_UInt8_2_io_deq_valid : _T_4498 ? _Queue2_UInt8_1_io_deq_valid : _T_4497 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_96 = _remapindex_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_6 = _GEN_96[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4529 = remapindex_6 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4530 = remapindex_6 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4531 = remapindex_6 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4532 = remapindex_6 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4533 = remapindex_6 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4534 = remapindex_6 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4535 = remapindex_6 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4536 = remapindex_6 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4537 = remapindex_6 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4538 = remapindex_6 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4539 = remapindex_6 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4540 = remapindex_6 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4541 = remapindex_6 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4542 = remapindex_6 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4543 = remapindex_6 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4544 = remapindex_6 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4545 = remapindex_6 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4546 = remapindex_6 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4547 = remapindex_6 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4548 = remapindex_6 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4549 = remapindex_6 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4550 = remapindex_6 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4551 = remapindex_6 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4552 = remapindex_6 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4553 = remapindex_6 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4554 = remapindex_6 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4555 = remapindex_6 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4556 = remapindex_6 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4557 = remapindex_6 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4558 = remapindex_6 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4559 = remapindex_6 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4560 = remapindex_6 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_6 = _T_4560 ? _Queue2_UInt8_31_io_deq_bits : _T_4559 ? _Queue2_UInt8_30_io_deq_bits : _T_4558 ? _Queue2_UInt8_29_io_deq_bits : _T_4557 ? _Queue2_UInt8_28_io_deq_bits : _T_4556 ? _Queue2_UInt8_27_io_deq_bits : _T_4555 ? _Queue2_UInt8_26_io_deq_bits : _T_4554 ? _Queue2_UInt8_25_io_deq_bits : _T_4553 ? _Queue2_UInt8_24_io_deq_bits : _T_4552 ? _Queue2_UInt8_23_io_deq_bits : _T_4551 ? _Queue2_UInt8_22_io_deq_bits : _T_4550 ? _Queue2_UInt8_21_io_deq_bits : _T_4549 ? _Queue2_UInt8_20_io_deq_bits : _T_4548 ? _Queue2_UInt8_19_io_deq_bits : _T_4547 ? _Queue2_UInt8_18_io_deq_bits : _T_4546 ? _Queue2_UInt8_17_io_deq_bits : _T_4545 ? _Queue2_UInt8_16_io_deq_bits : _T_4544 ? _Queue2_UInt8_15_io_deq_bits : _T_4543 ? _Queue2_UInt8_14_io_deq_bits : _T_4542 ? _Queue2_UInt8_13_io_deq_bits : _T_4541 ? _Queue2_UInt8_12_io_deq_bits : _T_4540 ? _Queue2_UInt8_11_io_deq_bits : _T_4539 ? _Queue2_UInt8_10_io_deq_bits : _T_4538 ? _Queue2_UInt8_9_io_deq_bits : _T_4537 ? _Queue2_UInt8_8_io_deq_bits : _T_4536 ? _Queue2_UInt8_7_io_deq_bits : _T_4535 ? _Queue2_UInt8_6_io_deq_bits : _T_4534 ? _Queue2_UInt8_5_io_deq_bits : _T_4533 ? _Queue2_UInt8_4_io_deq_bits : _T_4532 ? _Queue2_UInt8_3_io_deq_bits : _T_4531 ? _Queue2_UInt8_2_io_deq_bits : _T_4530 ? _Queue2_UInt8_1_io_deq_bits : _T_4529 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_6 = _T_4560 ? _Queue2_UInt8_31_io_deq_valid : _T_4559 ? _Queue2_UInt8_30_io_deq_valid : _T_4558 ? _Queue2_UInt8_29_io_deq_valid : _T_4557 ? _Queue2_UInt8_28_io_deq_valid : _T_4556 ? _Queue2_UInt8_27_io_deq_valid : _T_4555 ? _Queue2_UInt8_26_io_deq_valid : _T_4554 ? _Queue2_UInt8_25_io_deq_valid : _T_4553 ? _Queue2_UInt8_24_io_deq_valid : _T_4552 ? _Queue2_UInt8_23_io_deq_valid : _T_4551 ? _Queue2_UInt8_22_io_deq_valid : _T_4550 ? _Queue2_UInt8_21_io_deq_valid : _T_4549 ? _Queue2_UInt8_20_io_deq_valid : _T_4548 ? _Queue2_UInt8_19_io_deq_valid : _T_4547 ? _Queue2_UInt8_18_io_deq_valid : _T_4546 ? _Queue2_UInt8_17_io_deq_valid : _T_4545 ? _Queue2_UInt8_16_io_deq_valid : _T_4544 ? _Queue2_UInt8_15_io_deq_valid : _T_4543 ? _Queue2_UInt8_14_io_deq_valid : _T_4542 ? _Queue2_UInt8_13_io_deq_valid : _T_4541 ? _Queue2_UInt8_12_io_deq_valid : _T_4540 ? _Queue2_UInt8_11_io_deq_valid : _T_4539 ? _Queue2_UInt8_10_io_deq_valid : _T_4538 ? _Queue2_UInt8_9_io_deq_valid : _T_4537 ? _Queue2_UInt8_8_io_deq_valid : _T_4536 ? _Queue2_UInt8_7_io_deq_valid : _T_4535 ? _Queue2_UInt8_6_io_deq_valid : _T_4534 ? _Queue2_UInt8_5_io_deq_valid : _T_4533 ? _Queue2_UInt8_4_io_deq_valid : _T_4532 ? _Queue2_UInt8_3_io_deq_valid : _T_4531 ? _Queue2_UInt8_2_io_deq_valid : _T_4530 ? _Queue2_UInt8_1_io_deq_valid : _T_4529 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_97 = _remapindex_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_7 = _GEN_97[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4561 = remapindex_7 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4562 = remapindex_7 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4563 = remapindex_7 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4564 = remapindex_7 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4565 = remapindex_7 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4566 = remapindex_7 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4567 = remapindex_7 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4568 = remapindex_7 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4569 = remapindex_7 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4570 = remapindex_7 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4571 = remapindex_7 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4572 = remapindex_7 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4573 = remapindex_7 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4574 = remapindex_7 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4575 = remapindex_7 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4576 = remapindex_7 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4577 = remapindex_7 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4578 = remapindex_7 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4579 = remapindex_7 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4580 = remapindex_7 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4581 = remapindex_7 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4582 = remapindex_7 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4583 = remapindex_7 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4584 = remapindex_7 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4585 = remapindex_7 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4586 = remapindex_7 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4587 = remapindex_7 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4588 = remapindex_7 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4589 = remapindex_7 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4590 = remapindex_7 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4591 = remapindex_7 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4592 = remapindex_7 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_7 = _T_4592 ? _Queue2_UInt8_31_io_deq_bits : _T_4591 ? _Queue2_UInt8_30_io_deq_bits : _T_4590 ? _Queue2_UInt8_29_io_deq_bits : _T_4589 ? _Queue2_UInt8_28_io_deq_bits : _T_4588 ? _Queue2_UInt8_27_io_deq_bits : _T_4587 ? _Queue2_UInt8_26_io_deq_bits : _T_4586 ? _Queue2_UInt8_25_io_deq_bits : _T_4585 ? _Queue2_UInt8_24_io_deq_bits : _T_4584 ? _Queue2_UInt8_23_io_deq_bits : _T_4583 ? _Queue2_UInt8_22_io_deq_bits : _T_4582 ? _Queue2_UInt8_21_io_deq_bits : _T_4581 ? _Queue2_UInt8_20_io_deq_bits : _T_4580 ? _Queue2_UInt8_19_io_deq_bits : _T_4579 ? _Queue2_UInt8_18_io_deq_bits : _T_4578 ? _Queue2_UInt8_17_io_deq_bits : _T_4577 ? _Queue2_UInt8_16_io_deq_bits : _T_4576 ? _Queue2_UInt8_15_io_deq_bits : _T_4575 ? _Queue2_UInt8_14_io_deq_bits : _T_4574 ? _Queue2_UInt8_13_io_deq_bits : _T_4573 ? _Queue2_UInt8_12_io_deq_bits : _T_4572 ? _Queue2_UInt8_11_io_deq_bits : _T_4571 ? _Queue2_UInt8_10_io_deq_bits : _T_4570 ? _Queue2_UInt8_9_io_deq_bits : _T_4569 ? _Queue2_UInt8_8_io_deq_bits : _T_4568 ? _Queue2_UInt8_7_io_deq_bits : _T_4567 ? _Queue2_UInt8_6_io_deq_bits : _T_4566 ? _Queue2_UInt8_5_io_deq_bits : _T_4565 ? _Queue2_UInt8_4_io_deq_bits : _T_4564 ? _Queue2_UInt8_3_io_deq_bits : _T_4563 ? _Queue2_UInt8_2_io_deq_bits : _T_4562 ? _Queue2_UInt8_1_io_deq_bits : _T_4561 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_7 = _T_4592 ? _Queue2_UInt8_31_io_deq_valid : _T_4591 ? _Queue2_UInt8_30_io_deq_valid : _T_4590 ? _Queue2_UInt8_29_io_deq_valid : _T_4589 ? _Queue2_UInt8_28_io_deq_valid : _T_4588 ? _Queue2_UInt8_27_io_deq_valid : _T_4587 ? _Queue2_UInt8_26_io_deq_valid : _T_4586 ? _Queue2_UInt8_25_io_deq_valid : _T_4585 ? _Queue2_UInt8_24_io_deq_valid : _T_4584 ? _Queue2_UInt8_23_io_deq_valid : _T_4583 ? _Queue2_UInt8_22_io_deq_valid : _T_4582 ? _Queue2_UInt8_21_io_deq_valid : _T_4581 ? _Queue2_UInt8_20_io_deq_valid : _T_4580 ? _Queue2_UInt8_19_io_deq_valid : _T_4579 ? _Queue2_UInt8_18_io_deq_valid : _T_4578 ? _Queue2_UInt8_17_io_deq_valid : _T_4577 ? _Queue2_UInt8_16_io_deq_valid : _T_4576 ? _Queue2_UInt8_15_io_deq_valid : _T_4575 ? _Queue2_UInt8_14_io_deq_valid : _T_4574 ? _Queue2_UInt8_13_io_deq_valid : _T_4573 ? _Queue2_UInt8_12_io_deq_valid : _T_4572 ? _Queue2_UInt8_11_io_deq_valid : _T_4571 ? _Queue2_UInt8_10_io_deq_valid : _T_4570 ? _Queue2_UInt8_9_io_deq_valid : _T_4569 ? _Queue2_UInt8_8_io_deq_valid : _T_4568 ? _Queue2_UInt8_7_io_deq_valid : _T_4567 ? _Queue2_UInt8_6_io_deq_valid : _T_4566 ? _Queue2_UInt8_5_io_deq_valid : _T_4565 ? _Queue2_UInt8_4_io_deq_valid : _T_4564 ? _Queue2_UInt8_3_io_deq_valid : _T_4563 ? _Queue2_UInt8_2_io_deq_valid : _T_4562 ? _Queue2_UInt8_1_io_deq_valid : _T_4561 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_98 = _remapindex_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_8 = _GEN_98[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4593 = remapindex_8 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4594 = remapindex_8 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4595 = remapindex_8 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4596 = remapindex_8 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4597 = remapindex_8 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4598 = remapindex_8 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4599 = remapindex_8 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4600 = remapindex_8 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4601 = remapindex_8 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4602 = remapindex_8 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4603 = remapindex_8 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4604 = remapindex_8 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4605 = remapindex_8 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4606 = remapindex_8 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4607 = remapindex_8 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4608 = remapindex_8 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4609 = remapindex_8 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4610 = remapindex_8 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4611 = remapindex_8 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4612 = remapindex_8 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4613 = remapindex_8 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4614 = remapindex_8 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4615 = remapindex_8 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4616 = remapindex_8 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4617 = remapindex_8 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4618 = remapindex_8 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4619 = remapindex_8 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4620 = remapindex_8 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4621 = remapindex_8 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4622 = remapindex_8 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4623 = remapindex_8 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4624 = remapindex_8 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_8 = _T_4624 ? _Queue2_UInt8_31_io_deq_bits : _T_4623 ? _Queue2_UInt8_30_io_deq_bits : _T_4622 ? _Queue2_UInt8_29_io_deq_bits : _T_4621 ? _Queue2_UInt8_28_io_deq_bits : _T_4620 ? _Queue2_UInt8_27_io_deq_bits : _T_4619 ? _Queue2_UInt8_26_io_deq_bits : _T_4618 ? _Queue2_UInt8_25_io_deq_bits : _T_4617 ? _Queue2_UInt8_24_io_deq_bits : _T_4616 ? _Queue2_UInt8_23_io_deq_bits : _T_4615 ? _Queue2_UInt8_22_io_deq_bits : _T_4614 ? _Queue2_UInt8_21_io_deq_bits : _T_4613 ? _Queue2_UInt8_20_io_deq_bits : _T_4612 ? _Queue2_UInt8_19_io_deq_bits : _T_4611 ? _Queue2_UInt8_18_io_deq_bits : _T_4610 ? _Queue2_UInt8_17_io_deq_bits : _T_4609 ? _Queue2_UInt8_16_io_deq_bits : _T_4608 ? _Queue2_UInt8_15_io_deq_bits : _T_4607 ? _Queue2_UInt8_14_io_deq_bits : _T_4606 ? _Queue2_UInt8_13_io_deq_bits : _T_4605 ? _Queue2_UInt8_12_io_deq_bits : _T_4604 ? _Queue2_UInt8_11_io_deq_bits : _T_4603 ? _Queue2_UInt8_10_io_deq_bits : _T_4602 ? _Queue2_UInt8_9_io_deq_bits : _T_4601 ? _Queue2_UInt8_8_io_deq_bits : _T_4600 ? _Queue2_UInt8_7_io_deq_bits : _T_4599 ? _Queue2_UInt8_6_io_deq_bits : _T_4598 ? _Queue2_UInt8_5_io_deq_bits : _T_4597 ? _Queue2_UInt8_4_io_deq_bits : _T_4596 ? _Queue2_UInt8_3_io_deq_bits : _T_4595 ? _Queue2_UInt8_2_io_deq_bits : _T_4594 ? _Queue2_UInt8_1_io_deq_bits : _T_4593 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_8 = _T_4624 ? _Queue2_UInt8_31_io_deq_valid : _T_4623 ? _Queue2_UInt8_30_io_deq_valid : _T_4622 ? _Queue2_UInt8_29_io_deq_valid : _T_4621 ? _Queue2_UInt8_28_io_deq_valid : _T_4620 ? _Queue2_UInt8_27_io_deq_valid : _T_4619 ? _Queue2_UInt8_26_io_deq_valid : _T_4618 ? _Queue2_UInt8_25_io_deq_valid : _T_4617 ? _Queue2_UInt8_24_io_deq_valid : _T_4616 ? _Queue2_UInt8_23_io_deq_valid : _T_4615 ? _Queue2_UInt8_22_io_deq_valid : _T_4614 ? _Queue2_UInt8_21_io_deq_valid : _T_4613 ? _Queue2_UInt8_20_io_deq_valid : _T_4612 ? _Queue2_UInt8_19_io_deq_valid : _T_4611 ? _Queue2_UInt8_18_io_deq_valid : _T_4610 ? _Queue2_UInt8_17_io_deq_valid : _T_4609 ? _Queue2_UInt8_16_io_deq_valid : _T_4608 ? _Queue2_UInt8_15_io_deq_valid : _T_4607 ? _Queue2_UInt8_14_io_deq_valid : _T_4606 ? _Queue2_UInt8_13_io_deq_valid : _T_4605 ? _Queue2_UInt8_12_io_deq_valid : _T_4604 ? _Queue2_UInt8_11_io_deq_valid : _T_4603 ? _Queue2_UInt8_10_io_deq_valid : _T_4602 ? _Queue2_UInt8_9_io_deq_valid : _T_4601 ? _Queue2_UInt8_8_io_deq_valid : _T_4600 ? _Queue2_UInt8_7_io_deq_valid : _T_4599 ? _Queue2_UInt8_6_io_deq_valid : _T_4598 ? _Queue2_UInt8_5_io_deq_valid : _T_4597 ? _Queue2_UInt8_4_io_deq_valid : _T_4596 ? _Queue2_UInt8_3_io_deq_valid : _T_4595 ? _Queue2_UInt8_2_io_deq_valid : _T_4594 ? _Queue2_UInt8_1_io_deq_valid : _T_4593 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_99 = _remapindex_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_9 = _GEN_99[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4625 = remapindex_9 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4626 = remapindex_9 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4627 = remapindex_9 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4628 = remapindex_9 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4629 = remapindex_9 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4630 = remapindex_9 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4631 = remapindex_9 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4632 = remapindex_9 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4633 = remapindex_9 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4634 = remapindex_9 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4635 = remapindex_9 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4636 = remapindex_9 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4637 = remapindex_9 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4638 = remapindex_9 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4639 = remapindex_9 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4640 = remapindex_9 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4641 = remapindex_9 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4642 = remapindex_9 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4643 = remapindex_9 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4644 = remapindex_9 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4645 = remapindex_9 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4646 = remapindex_9 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4647 = remapindex_9 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4648 = remapindex_9 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4649 = remapindex_9 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4650 = remapindex_9 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4651 = remapindex_9 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4652 = remapindex_9 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4653 = remapindex_9 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4654 = remapindex_9 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4655 = remapindex_9 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4656 = remapindex_9 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_9 = _T_4656 ? _Queue2_UInt8_31_io_deq_bits : _T_4655 ? _Queue2_UInt8_30_io_deq_bits : _T_4654 ? _Queue2_UInt8_29_io_deq_bits : _T_4653 ? _Queue2_UInt8_28_io_deq_bits : _T_4652 ? _Queue2_UInt8_27_io_deq_bits : _T_4651 ? _Queue2_UInt8_26_io_deq_bits : _T_4650 ? _Queue2_UInt8_25_io_deq_bits : _T_4649 ? _Queue2_UInt8_24_io_deq_bits : _T_4648 ? _Queue2_UInt8_23_io_deq_bits : _T_4647 ? _Queue2_UInt8_22_io_deq_bits : _T_4646 ? _Queue2_UInt8_21_io_deq_bits : _T_4645 ? _Queue2_UInt8_20_io_deq_bits : _T_4644 ? _Queue2_UInt8_19_io_deq_bits : _T_4643 ? _Queue2_UInt8_18_io_deq_bits : _T_4642 ? _Queue2_UInt8_17_io_deq_bits : _T_4641 ? _Queue2_UInt8_16_io_deq_bits : _T_4640 ? _Queue2_UInt8_15_io_deq_bits : _T_4639 ? _Queue2_UInt8_14_io_deq_bits : _T_4638 ? _Queue2_UInt8_13_io_deq_bits : _T_4637 ? _Queue2_UInt8_12_io_deq_bits : _T_4636 ? _Queue2_UInt8_11_io_deq_bits : _T_4635 ? _Queue2_UInt8_10_io_deq_bits : _T_4634 ? _Queue2_UInt8_9_io_deq_bits : _T_4633 ? _Queue2_UInt8_8_io_deq_bits : _T_4632 ? _Queue2_UInt8_7_io_deq_bits : _T_4631 ? _Queue2_UInt8_6_io_deq_bits : _T_4630 ? _Queue2_UInt8_5_io_deq_bits : _T_4629 ? _Queue2_UInt8_4_io_deq_bits : _T_4628 ? _Queue2_UInt8_3_io_deq_bits : _T_4627 ? _Queue2_UInt8_2_io_deq_bits : _T_4626 ? _Queue2_UInt8_1_io_deq_bits : _T_4625 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_9 = _T_4656 ? _Queue2_UInt8_31_io_deq_valid : _T_4655 ? _Queue2_UInt8_30_io_deq_valid : _T_4654 ? _Queue2_UInt8_29_io_deq_valid : _T_4653 ? _Queue2_UInt8_28_io_deq_valid : _T_4652 ? _Queue2_UInt8_27_io_deq_valid : _T_4651 ? _Queue2_UInt8_26_io_deq_valid : _T_4650 ? _Queue2_UInt8_25_io_deq_valid : _T_4649 ? _Queue2_UInt8_24_io_deq_valid : _T_4648 ? _Queue2_UInt8_23_io_deq_valid : _T_4647 ? _Queue2_UInt8_22_io_deq_valid : _T_4646 ? _Queue2_UInt8_21_io_deq_valid : _T_4645 ? _Queue2_UInt8_20_io_deq_valid : _T_4644 ? _Queue2_UInt8_19_io_deq_valid : _T_4643 ? _Queue2_UInt8_18_io_deq_valid : _T_4642 ? _Queue2_UInt8_17_io_deq_valid : _T_4641 ? _Queue2_UInt8_16_io_deq_valid : _T_4640 ? _Queue2_UInt8_15_io_deq_valid : _T_4639 ? _Queue2_UInt8_14_io_deq_valid : _T_4638 ? _Queue2_UInt8_13_io_deq_valid : _T_4637 ? _Queue2_UInt8_12_io_deq_valid : _T_4636 ? _Queue2_UInt8_11_io_deq_valid : _T_4635 ? _Queue2_UInt8_10_io_deq_valid : _T_4634 ? _Queue2_UInt8_9_io_deq_valid : _T_4633 ? _Queue2_UInt8_8_io_deq_valid : _T_4632 ? _Queue2_UInt8_7_io_deq_valid : _T_4631 ? _Queue2_UInt8_6_io_deq_valid : _T_4630 ? _Queue2_UInt8_5_io_deq_valid : _T_4629 ? _Queue2_UInt8_4_io_deq_valid : _T_4628 ? _Queue2_UInt8_3_io_deq_valid : _T_4627 ? _Queue2_UInt8_2_io_deq_valid : _T_4626 ? _Queue2_UInt8_1_io_deq_valid : _T_4625 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_100 = _remapindex_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_10 = _GEN_100[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4657 = remapindex_10 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4658 = remapindex_10 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4659 = remapindex_10 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4660 = remapindex_10 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4661 = remapindex_10 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4662 = remapindex_10 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4663 = remapindex_10 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4664 = remapindex_10 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4665 = remapindex_10 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4666 = remapindex_10 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4667 = remapindex_10 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4668 = remapindex_10 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4669 = remapindex_10 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4670 = remapindex_10 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4671 = remapindex_10 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4672 = remapindex_10 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4673 = remapindex_10 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4674 = remapindex_10 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4675 = remapindex_10 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4676 = remapindex_10 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4677 = remapindex_10 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4678 = remapindex_10 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4679 = remapindex_10 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4680 = remapindex_10 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4681 = remapindex_10 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4682 = remapindex_10 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4683 = remapindex_10 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4684 = remapindex_10 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4685 = remapindex_10 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4686 = remapindex_10 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4687 = remapindex_10 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4688 = remapindex_10 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_10 = _T_4688 ? _Queue2_UInt8_31_io_deq_bits : _T_4687 ? _Queue2_UInt8_30_io_deq_bits : _T_4686 ? _Queue2_UInt8_29_io_deq_bits : _T_4685 ? _Queue2_UInt8_28_io_deq_bits : _T_4684 ? _Queue2_UInt8_27_io_deq_bits : _T_4683 ? _Queue2_UInt8_26_io_deq_bits : _T_4682 ? _Queue2_UInt8_25_io_deq_bits : _T_4681 ? _Queue2_UInt8_24_io_deq_bits : _T_4680 ? _Queue2_UInt8_23_io_deq_bits : _T_4679 ? _Queue2_UInt8_22_io_deq_bits : _T_4678 ? _Queue2_UInt8_21_io_deq_bits : _T_4677 ? _Queue2_UInt8_20_io_deq_bits : _T_4676 ? _Queue2_UInt8_19_io_deq_bits : _T_4675 ? _Queue2_UInt8_18_io_deq_bits : _T_4674 ? _Queue2_UInt8_17_io_deq_bits : _T_4673 ? _Queue2_UInt8_16_io_deq_bits : _T_4672 ? _Queue2_UInt8_15_io_deq_bits : _T_4671 ? _Queue2_UInt8_14_io_deq_bits : _T_4670 ? _Queue2_UInt8_13_io_deq_bits : _T_4669 ? _Queue2_UInt8_12_io_deq_bits : _T_4668 ? _Queue2_UInt8_11_io_deq_bits : _T_4667 ? _Queue2_UInt8_10_io_deq_bits : _T_4666 ? _Queue2_UInt8_9_io_deq_bits : _T_4665 ? _Queue2_UInt8_8_io_deq_bits : _T_4664 ? _Queue2_UInt8_7_io_deq_bits : _T_4663 ? _Queue2_UInt8_6_io_deq_bits : _T_4662 ? _Queue2_UInt8_5_io_deq_bits : _T_4661 ? _Queue2_UInt8_4_io_deq_bits : _T_4660 ? _Queue2_UInt8_3_io_deq_bits : _T_4659 ? _Queue2_UInt8_2_io_deq_bits : _T_4658 ? _Queue2_UInt8_1_io_deq_bits : _T_4657 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_10 = _T_4688 ? _Queue2_UInt8_31_io_deq_valid : _T_4687 ? _Queue2_UInt8_30_io_deq_valid : _T_4686 ? _Queue2_UInt8_29_io_deq_valid : _T_4685 ? _Queue2_UInt8_28_io_deq_valid : _T_4684 ? _Queue2_UInt8_27_io_deq_valid : _T_4683 ? _Queue2_UInt8_26_io_deq_valid : _T_4682 ? _Queue2_UInt8_25_io_deq_valid : _T_4681 ? _Queue2_UInt8_24_io_deq_valid : _T_4680 ? _Queue2_UInt8_23_io_deq_valid : _T_4679 ? _Queue2_UInt8_22_io_deq_valid : _T_4678 ? _Queue2_UInt8_21_io_deq_valid : _T_4677 ? _Queue2_UInt8_20_io_deq_valid : _T_4676 ? _Queue2_UInt8_19_io_deq_valid : _T_4675 ? _Queue2_UInt8_18_io_deq_valid : _T_4674 ? _Queue2_UInt8_17_io_deq_valid : _T_4673 ? _Queue2_UInt8_16_io_deq_valid : _T_4672 ? _Queue2_UInt8_15_io_deq_valid : _T_4671 ? _Queue2_UInt8_14_io_deq_valid : _T_4670 ? _Queue2_UInt8_13_io_deq_valid : _T_4669 ? _Queue2_UInt8_12_io_deq_valid : _T_4668 ? _Queue2_UInt8_11_io_deq_valid : _T_4667 ? _Queue2_UInt8_10_io_deq_valid : _T_4666 ? _Queue2_UInt8_9_io_deq_valid : _T_4665 ? _Queue2_UInt8_8_io_deq_valid : _T_4664 ? _Queue2_UInt8_7_io_deq_valid : _T_4663 ? _Queue2_UInt8_6_io_deq_valid : _T_4662 ? _Queue2_UInt8_5_io_deq_valid : _T_4661 ? _Queue2_UInt8_4_io_deq_valid : _T_4660 ? _Queue2_UInt8_3_io_deq_valid : _T_4659 ? _Queue2_UInt8_2_io_deq_valid : _T_4658 ? _Queue2_UInt8_1_io_deq_valid : _T_4657 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_101 = _remapindex_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_11 = _GEN_101[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4689 = remapindex_11 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4690 = remapindex_11 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4691 = remapindex_11 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4692 = remapindex_11 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4693 = remapindex_11 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4694 = remapindex_11 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4695 = remapindex_11 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4696 = remapindex_11 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4697 = remapindex_11 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4698 = remapindex_11 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4699 = remapindex_11 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4700 = remapindex_11 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4701 = remapindex_11 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4702 = remapindex_11 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4703 = remapindex_11 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4704 = remapindex_11 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4705 = remapindex_11 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4706 = remapindex_11 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4707 = remapindex_11 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4708 = remapindex_11 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4709 = remapindex_11 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4710 = remapindex_11 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4711 = remapindex_11 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4712 = remapindex_11 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4713 = remapindex_11 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4714 = remapindex_11 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4715 = remapindex_11 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4716 = remapindex_11 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4717 = remapindex_11 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4718 = remapindex_11 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4719 = remapindex_11 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4720 = remapindex_11 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_11 = _T_4720 ? _Queue2_UInt8_31_io_deq_bits : _T_4719 ? _Queue2_UInt8_30_io_deq_bits : _T_4718 ? _Queue2_UInt8_29_io_deq_bits : _T_4717 ? _Queue2_UInt8_28_io_deq_bits : _T_4716 ? _Queue2_UInt8_27_io_deq_bits : _T_4715 ? _Queue2_UInt8_26_io_deq_bits : _T_4714 ? _Queue2_UInt8_25_io_deq_bits : _T_4713 ? _Queue2_UInt8_24_io_deq_bits : _T_4712 ? _Queue2_UInt8_23_io_deq_bits : _T_4711 ? _Queue2_UInt8_22_io_deq_bits : _T_4710 ? _Queue2_UInt8_21_io_deq_bits : _T_4709 ? _Queue2_UInt8_20_io_deq_bits : _T_4708 ? _Queue2_UInt8_19_io_deq_bits : _T_4707 ? _Queue2_UInt8_18_io_deq_bits : _T_4706 ? _Queue2_UInt8_17_io_deq_bits : _T_4705 ? _Queue2_UInt8_16_io_deq_bits : _T_4704 ? _Queue2_UInt8_15_io_deq_bits : _T_4703 ? _Queue2_UInt8_14_io_deq_bits : _T_4702 ? _Queue2_UInt8_13_io_deq_bits : _T_4701 ? _Queue2_UInt8_12_io_deq_bits : _T_4700 ? _Queue2_UInt8_11_io_deq_bits : _T_4699 ? _Queue2_UInt8_10_io_deq_bits : _T_4698 ? _Queue2_UInt8_9_io_deq_bits : _T_4697 ? _Queue2_UInt8_8_io_deq_bits : _T_4696 ? _Queue2_UInt8_7_io_deq_bits : _T_4695 ? _Queue2_UInt8_6_io_deq_bits : _T_4694 ? _Queue2_UInt8_5_io_deq_bits : _T_4693 ? _Queue2_UInt8_4_io_deq_bits : _T_4692 ? _Queue2_UInt8_3_io_deq_bits : _T_4691 ? _Queue2_UInt8_2_io_deq_bits : _T_4690 ? _Queue2_UInt8_1_io_deq_bits : _T_4689 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_11 = _T_4720 ? _Queue2_UInt8_31_io_deq_valid : _T_4719 ? _Queue2_UInt8_30_io_deq_valid : _T_4718 ? _Queue2_UInt8_29_io_deq_valid : _T_4717 ? _Queue2_UInt8_28_io_deq_valid : _T_4716 ? _Queue2_UInt8_27_io_deq_valid : _T_4715 ? _Queue2_UInt8_26_io_deq_valid : _T_4714 ? _Queue2_UInt8_25_io_deq_valid : _T_4713 ? _Queue2_UInt8_24_io_deq_valid : _T_4712 ? _Queue2_UInt8_23_io_deq_valid : _T_4711 ? _Queue2_UInt8_22_io_deq_valid : _T_4710 ? _Queue2_UInt8_21_io_deq_valid : _T_4709 ? _Queue2_UInt8_20_io_deq_valid : _T_4708 ? _Queue2_UInt8_19_io_deq_valid : _T_4707 ? _Queue2_UInt8_18_io_deq_valid : _T_4706 ? _Queue2_UInt8_17_io_deq_valid : _T_4705 ? _Queue2_UInt8_16_io_deq_valid : _T_4704 ? _Queue2_UInt8_15_io_deq_valid : _T_4703 ? _Queue2_UInt8_14_io_deq_valid : _T_4702 ? _Queue2_UInt8_13_io_deq_valid : _T_4701 ? _Queue2_UInt8_12_io_deq_valid : _T_4700 ? _Queue2_UInt8_11_io_deq_valid : _T_4699 ? _Queue2_UInt8_10_io_deq_valid : _T_4698 ? _Queue2_UInt8_9_io_deq_valid : _T_4697 ? _Queue2_UInt8_8_io_deq_valid : _T_4696 ? _Queue2_UInt8_7_io_deq_valid : _T_4695 ? _Queue2_UInt8_6_io_deq_valid : _T_4694 ? _Queue2_UInt8_5_io_deq_valid : _T_4693 ? _Queue2_UInt8_4_io_deq_valid : _T_4692 ? _Queue2_UInt8_3_io_deq_valid : _T_4691 ? _Queue2_UInt8_2_io_deq_valid : _T_4690 ? _Queue2_UInt8_1_io_deq_valid : _T_4689 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_102 = _remapindex_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_12 = _GEN_102[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4721 = remapindex_12 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4722 = remapindex_12 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4723 = remapindex_12 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4724 = remapindex_12 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4725 = remapindex_12 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4726 = remapindex_12 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4727 = remapindex_12 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4728 = remapindex_12 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4729 = remapindex_12 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4730 = remapindex_12 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4731 = remapindex_12 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4732 = remapindex_12 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4733 = remapindex_12 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4734 = remapindex_12 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4735 = remapindex_12 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4736 = remapindex_12 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4737 = remapindex_12 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4738 = remapindex_12 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4739 = remapindex_12 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4740 = remapindex_12 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4741 = remapindex_12 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4742 = remapindex_12 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4743 = remapindex_12 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4744 = remapindex_12 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4745 = remapindex_12 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4746 = remapindex_12 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4747 = remapindex_12 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4748 = remapindex_12 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4749 = remapindex_12 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4750 = remapindex_12 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4751 = remapindex_12 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4752 = remapindex_12 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_12 = _T_4752 ? _Queue2_UInt8_31_io_deq_bits : _T_4751 ? _Queue2_UInt8_30_io_deq_bits : _T_4750 ? _Queue2_UInt8_29_io_deq_bits : _T_4749 ? _Queue2_UInt8_28_io_deq_bits : _T_4748 ? _Queue2_UInt8_27_io_deq_bits : _T_4747 ? _Queue2_UInt8_26_io_deq_bits : _T_4746 ? _Queue2_UInt8_25_io_deq_bits : _T_4745 ? _Queue2_UInt8_24_io_deq_bits : _T_4744 ? _Queue2_UInt8_23_io_deq_bits : _T_4743 ? _Queue2_UInt8_22_io_deq_bits : _T_4742 ? _Queue2_UInt8_21_io_deq_bits : _T_4741 ? _Queue2_UInt8_20_io_deq_bits : _T_4740 ? _Queue2_UInt8_19_io_deq_bits : _T_4739 ? _Queue2_UInt8_18_io_deq_bits : _T_4738 ? _Queue2_UInt8_17_io_deq_bits : _T_4737 ? _Queue2_UInt8_16_io_deq_bits : _T_4736 ? _Queue2_UInt8_15_io_deq_bits : _T_4735 ? _Queue2_UInt8_14_io_deq_bits : _T_4734 ? _Queue2_UInt8_13_io_deq_bits : _T_4733 ? _Queue2_UInt8_12_io_deq_bits : _T_4732 ? _Queue2_UInt8_11_io_deq_bits : _T_4731 ? _Queue2_UInt8_10_io_deq_bits : _T_4730 ? _Queue2_UInt8_9_io_deq_bits : _T_4729 ? _Queue2_UInt8_8_io_deq_bits : _T_4728 ? _Queue2_UInt8_7_io_deq_bits : _T_4727 ? _Queue2_UInt8_6_io_deq_bits : _T_4726 ? _Queue2_UInt8_5_io_deq_bits : _T_4725 ? _Queue2_UInt8_4_io_deq_bits : _T_4724 ? _Queue2_UInt8_3_io_deq_bits : _T_4723 ? _Queue2_UInt8_2_io_deq_bits : _T_4722 ? _Queue2_UInt8_1_io_deq_bits : _T_4721 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_12 = _T_4752 ? _Queue2_UInt8_31_io_deq_valid : _T_4751 ? _Queue2_UInt8_30_io_deq_valid : _T_4750 ? _Queue2_UInt8_29_io_deq_valid : _T_4749 ? _Queue2_UInt8_28_io_deq_valid : _T_4748 ? _Queue2_UInt8_27_io_deq_valid : _T_4747 ? _Queue2_UInt8_26_io_deq_valid : _T_4746 ? _Queue2_UInt8_25_io_deq_valid : _T_4745 ? _Queue2_UInt8_24_io_deq_valid : _T_4744 ? _Queue2_UInt8_23_io_deq_valid : _T_4743 ? _Queue2_UInt8_22_io_deq_valid : _T_4742 ? _Queue2_UInt8_21_io_deq_valid : _T_4741 ? _Queue2_UInt8_20_io_deq_valid : _T_4740 ? _Queue2_UInt8_19_io_deq_valid : _T_4739 ? _Queue2_UInt8_18_io_deq_valid : _T_4738 ? _Queue2_UInt8_17_io_deq_valid : _T_4737 ? _Queue2_UInt8_16_io_deq_valid : _T_4736 ? _Queue2_UInt8_15_io_deq_valid : _T_4735 ? _Queue2_UInt8_14_io_deq_valid : _T_4734 ? _Queue2_UInt8_13_io_deq_valid : _T_4733 ? _Queue2_UInt8_12_io_deq_valid : _T_4732 ? _Queue2_UInt8_11_io_deq_valid : _T_4731 ? _Queue2_UInt8_10_io_deq_valid : _T_4730 ? _Queue2_UInt8_9_io_deq_valid : _T_4729 ? _Queue2_UInt8_8_io_deq_valid : _T_4728 ? _Queue2_UInt8_7_io_deq_valid : _T_4727 ? _Queue2_UInt8_6_io_deq_valid : _T_4726 ? _Queue2_UInt8_5_io_deq_valid : _T_4725 ? _Queue2_UInt8_4_io_deq_valid : _T_4724 ? _Queue2_UInt8_3_io_deq_valid : _T_4723 ? _Queue2_UInt8_2_io_deq_valid : _T_4722 ? _Queue2_UInt8_1_io_deq_valid : _T_4721 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_103 = _remapindex_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_13 = _GEN_103[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4753 = remapindex_13 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4754 = remapindex_13 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4755 = remapindex_13 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4756 = remapindex_13 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4757 = remapindex_13 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4758 = remapindex_13 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4759 = remapindex_13 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4760 = remapindex_13 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4761 = remapindex_13 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4762 = remapindex_13 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4763 = remapindex_13 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4764 = remapindex_13 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4765 = remapindex_13 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4766 = remapindex_13 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4767 = remapindex_13 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4768 = remapindex_13 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4769 = remapindex_13 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4770 = remapindex_13 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4771 = remapindex_13 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4772 = remapindex_13 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4773 = remapindex_13 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4774 = remapindex_13 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4775 = remapindex_13 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4776 = remapindex_13 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4777 = remapindex_13 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4778 = remapindex_13 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4779 = remapindex_13 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4780 = remapindex_13 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4781 = remapindex_13 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4782 = remapindex_13 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4783 = remapindex_13 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4784 = remapindex_13 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_13 = _T_4784 ? _Queue2_UInt8_31_io_deq_bits : _T_4783 ? _Queue2_UInt8_30_io_deq_bits : _T_4782 ? _Queue2_UInt8_29_io_deq_bits : _T_4781 ? _Queue2_UInt8_28_io_deq_bits : _T_4780 ? _Queue2_UInt8_27_io_deq_bits : _T_4779 ? _Queue2_UInt8_26_io_deq_bits : _T_4778 ? _Queue2_UInt8_25_io_deq_bits : _T_4777 ? _Queue2_UInt8_24_io_deq_bits : _T_4776 ? _Queue2_UInt8_23_io_deq_bits : _T_4775 ? _Queue2_UInt8_22_io_deq_bits : _T_4774 ? _Queue2_UInt8_21_io_deq_bits : _T_4773 ? _Queue2_UInt8_20_io_deq_bits : _T_4772 ? _Queue2_UInt8_19_io_deq_bits : _T_4771 ? _Queue2_UInt8_18_io_deq_bits : _T_4770 ? _Queue2_UInt8_17_io_deq_bits : _T_4769 ? _Queue2_UInt8_16_io_deq_bits : _T_4768 ? _Queue2_UInt8_15_io_deq_bits : _T_4767 ? _Queue2_UInt8_14_io_deq_bits : _T_4766 ? _Queue2_UInt8_13_io_deq_bits : _T_4765 ? _Queue2_UInt8_12_io_deq_bits : _T_4764 ? _Queue2_UInt8_11_io_deq_bits : _T_4763 ? _Queue2_UInt8_10_io_deq_bits : _T_4762 ? _Queue2_UInt8_9_io_deq_bits : _T_4761 ? _Queue2_UInt8_8_io_deq_bits : _T_4760 ? _Queue2_UInt8_7_io_deq_bits : _T_4759 ? _Queue2_UInt8_6_io_deq_bits : _T_4758 ? _Queue2_UInt8_5_io_deq_bits : _T_4757 ? _Queue2_UInt8_4_io_deq_bits : _T_4756 ? _Queue2_UInt8_3_io_deq_bits : _T_4755 ? _Queue2_UInt8_2_io_deq_bits : _T_4754 ? _Queue2_UInt8_1_io_deq_bits : _T_4753 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_13 = _T_4784 ? _Queue2_UInt8_31_io_deq_valid : _T_4783 ? _Queue2_UInt8_30_io_deq_valid : _T_4782 ? _Queue2_UInt8_29_io_deq_valid : _T_4781 ? _Queue2_UInt8_28_io_deq_valid : _T_4780 ? _Queue2_UInt8_27_io_deq_valid : _T_4779 ? _Queue2_UInt8_26_io_deq_valid : _T_4778 ? _Queue2_UInt8_25_io_deq_valid : _T_4777 ? _Queue2_UInt8_24_io_deq_valid : _T_4776 ? _Queue2_UInt8_23_io_deq_valid : _T_4775 ? _Queue2_UInt8_22_io_deq_valid : _T_4774 ? _Queue2_UInt8_21_io_deq_valid : _T_4773 ? _Queue2_UInt8_20_io_deq_valid : _T_4772 ? _Queue2_UInt8_19_io_deq_valid : _T_4771 ? _Queue2_UInt8_18_io_deq_valid : _T_4770 ? _Queue2_UInt8_17_io_deq_valid : _T_4769 ? _Queue2_UInt8_16_io_deq_valid : _T_4768 ? _Queue2_UInt8_15_io_deq_valid : _T_4767 ? _Queue2_UInt8_14_io_deq_valid : _T_4766 ? _Queue2_UInt8_13_io_deq_valid : _T_4765 ? _Queue2_UInt8_12_io_deq_valid : _T_4764 ? _Queue2_UInt8_11_io_deq_valid : _T_4763 ? _Queue2_UInt8_10_io_deq_valid : _T_4762 ? _Queue2_UInt8_9_io_deq_valid : _T_4761 ? _Queue2_UInt8_8_io_deq_valid : _T_4760 ? _Queue2_UInt8_7_io_deq_valid : _T_4759 ? _Queue2_UInt8_6_io_deq_valid : _T_4758 ? _Queue2_UInt8_5_io_deq_valid : _T_4757 ? _Queue2_UInt8_4_io_deq_valid : _T_4756 ? _Queue2_UInt8_3_io_deq_valid : _T_4755 ? _Queue2_UInt8_2_io_deq_valid : _T_4754 ? _Queue2_UInt8_1_io_deq_valid : _T_4753 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_104 = _remapindex_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_14 = _GEN_104[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4785 = remapindex_14 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4786 = remapindex_14 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4787 = remapindex_14 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4788 = remapindex_14 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4789 = remapindex_14 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4790 = remapindex_14 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4791 = remapindex_14 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4792 = remapindex_14 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4793 = remapindex_14 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4794 = remapindex_14 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4795 = remapindex_14 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4796 = remapindex_14 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4797 = remapindex_14 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4798 = remapindex_14 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4799 = remapindex_14 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4800 = remapindex_14 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4801 = remapindex_14 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4802 = remapindex_14 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4803 = remapindex_14 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4804 = remapindex_14 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4805 = remapindex_14 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4806 = remapindex_14 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4807 = remapindex_14 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4808 = remapindex_14 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4809 = remapindex_14 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4810 = remapindex_14 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4811 = remapindex_14 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4812 = remapindex_14 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4813 = remapindex_14 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4814 = remapindex_14 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4815 = remapindex_14 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4816 = remapindex_14 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_14 = _T_4816 ? _Queue2_UInt8_31_io_deq_bits : _T_4815 ? _Queue2_UInt8_30_io_deq_bits : _T_4814 ? _Queue2_UInt8_29_io_deq_bits : _T_4813 ? _Queue2_UInt8_28_io_deq_bits : _T_4812 ? _Queue2_UInt8_27_io_deq_bits : _T_4811 ? _Queue2_UInt8_26_io_deq_bits : _T_4810 ? _Queue2_UInt8_25_io_deq_bits : _T_4809 ? _Queue2_UInt8_24_io_deq_bits : _T_4808 ? _Queue2_UInt8_23_io_deq_bits : _T_4807 ? _Queue2_UInt8_22_io_deq_bits : _T_4806 ? _Queue2_UInt8_21_io_deq_bits : _T_4805 ? _Queue2_UInt8_20_io_deq_bits : _T_4804 ? _Queue2_UInt8_19_io_deq_bits : _T_4803 ? _Queue2_UInt8_18_io_deq_bits : _T_4802 ? _Queue2_UInt8_17_io_deq_bits : _T_4801 ? _Queue2_UInt8_16_io_deq_bits : _T_4800 ? _Queue2_UInt8_15_io_deq_bits : _T_4799 ? _Queue2_UInt8_14_io_deq_bits : _T_4798 ? _Queue2_UInt8_13_io_deq_bits : _T_4797 ? _Queue2_UInt8_12_io_deq_bits : _T_4796 ? _Queue2_UInt8_11_io_deq_bits : _T_4795 ? _Queue2_UInt8_10_io_deq_bits : _T_4794 ? _Queue2_UInt8_9_io_deq_bits : _T_4793 ? _Queue2_UInt8_8_io_deq_bits : _T_4792 ? _Queue2_UInt8_7_io_deq_bits : _T_4791 ? _Queue2_UInt8_6_io_deq_bits : _T_4790 ? _Queue2_UInt8_5_io_deq_bits : _T_4789 ? _Queue2_UInt8_4_io_deq_bits : _T_4788 ? _Queue2_UInt8_3_io_deq_bits : _T_4787 ? _Queue2_UInt8_2_io_deq_bits : _T_4786 ? _Queue2_UInt8_1_io_deq_bits : _T_4785 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_14 = _T_4816 ? _Queue2_UInt8_31_io_deq_valid : _T_4815 ? _Queue2_UInt8_30_io_deq_valid : _T_4814 ? _Queue2_UInt8_29_io_deq_valid : _T_4813 ? _Queue2_UInt8_28_io_deq_valid : _T_4812 ? _Queue2_UInt8_27_io_deq_valid : _T_4811 ? _Queue2_UInt8_26_io_deq_valid : _T_4810 ? _Queue2_UInt8_25_io_deq_valid : _T_4809 ? _Queue2_UInt8_24_io_deq_valid : _T_4808 ? _Queue2_UInt8_23_io_deq_valid : _T_4807 ? _Queue2_UInt8_22_io_deq_valid : _T_4806 ? _Queue2_UInt8_21_io_deq_valid : _T_4805 ? _Queue2_UInt8_20_io_deq_valid : _T_4804 ? _Queue2_UInt8_19_io_deq_valid : _T_4803 ? _Queue2_UInt8_18_io_deq_valid : _T_4802 ? _Queue2_UInt8_17_io_deq_valid : _T_4801 ? _Queue2_UInt8_16_io_deq_valid : _T_4800 ? _Queue2_UInt8_15_io_deq_valid : _T_4799 ? _Queue2_UInt8_14_io_deq_valid : _T_4798 ? _Queue2_UInt8_13_io_deq_valid : _T_4797 ? _Queue2_UInt8_12_io_deq_valid : _T_4796 ? _Queue2_UInt8_11_io_deq_valid : _T_4795 ? _Queue2_UInt8_10_io_deq_valid : _T_4794 ? _Queue2_UInt8_9_io_deq_valid : _T_4793 ? _Queue2_UInt8_8_io_deq_valid : _T_4792 ? _Queue2_UInt8_7_io_deq_valid : _T_4791 ? _Queue2_UInt8_6_io_deq_valid : _T_4790 ? _Queue2_UInt8_5_io_deq_valid : _T_4789 ? _Queue2_UInt8_4_io_deq_valid : _T_4788 ? _Queue2_UInt8_3_io_deq_valid : _T_4787 ? _Queue2_UInt8_2_io_deq_valid : _T_4786 ? _Queue2_UInt8_1_io_deq_valid : _T_4785 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_105 = _remapindex_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_15 = _GEN_105[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4817 = remapindex_15 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4818 = remapindex_15 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4819 = remapindex_15 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4820 = remapindex_15 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4821 = remapindex_15 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4822 = remapindex_15 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4823 = remapindex_15 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4824 = remapindex_15 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4825 = remapindex_15 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4826 = remapindex_15 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4827 = remapindex_15 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4828 = remapindex_15 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4829 = remapindex_15 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4830 = remapindex_15 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4831 = remapindex_15 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4832 = remapindex_15 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4833 = remapindex_15 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4834 = remapindex_15 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4835 = remapindex_15 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4836 = remapindex_15 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4837 = remapindex_15 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4838 = remapindex_15 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4839 = remapindex_15 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4840 = remapindex_15 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4841 = remapindex_15 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4842 = remapindex_15 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4843 = remapindex_15 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4844 = remapindex_15 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4845 = remapindex_15 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4846 = remapindex_15 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4847 = remapindex_15 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4848 = remapindex_15 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_15 = _T_4848 ? _Queue2_UInt8_31_io_deq_bits : _T_4847 ? _Queue2_UInt8_30_io_deq_bits : _T_4846 ? _Queue2_UInt8_29_io_deq_bits : _T_4845 ? _Queue2_UInt8_28_io_deq_bits : _T_4844 ? _Queue2_UInt8_27_io_deq_bits : _T_4843 ? _Queue2_UInt8_26_io_deq_bits : _T_4842 ? _Queue2_UInt8_25_io_deq_bits : _T_4841 ? _Queue2_UInt8_24_io_deq_bits : _T_4840 ? _Queue2_UInt8_23_io_deq_bits : _T_4839 ? _Queue2_UInt8_22_io_deq_bits : _T_4838 ? _Queue2_UInt8_21_io_deq_bits : _T_4837 ? _Queue2_UInt8_20_io_deq_bits : _T_4836 ? _Queue2_UInt8_19_io_deq_bits : _T_4835 ? _Queue2_UInt8_18_io_deq_bits : _T_4834 ? _Queue2_UInt8_17_io_deq_bits : _T_4833 ? _Queue2_UInt8_16_io_deq_bits : _T_4832 ? _Queue2_UInt8_15_io_deq_bits : _T_4831 ? _Queue2_UInt8_14_io_deq_bits : _T_4830 ? _Queue2_UInt8_13_io_deq_bits : _T_4829 ? _Queue2_UInt8_12_io_deq_bits : _T_4828 ? _Queue2_UInt8_11_io_deq_bits : _T_4827 ? _Queue2_UInt8_10_io_deq_bits : _T_4826 ? _Queue2_UInt8_9_io_deq_bits : _T_4825 ? _Queue2_UInt8_8_io_deq_bits : _T_4824 ? _Queue2_UInt8_7_io_deq_bits : _T_4823 ? _Queue2_UInt8_6_io_deq_bits : _T_4822 ? _Queue2_UInt8_5_io_deq_bits : _T_4821 ? _Queue2_UInt8_4_io_deq_bits : _T_4820 ? _Queue2_UInt8_3_io_deq_bits : _T_4819 ? _Queue2_UInt8_2_io_deq_bits : _T_4818 ? _Queue2_UInt8_1_io_deq_bits : _T_4817 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_15 = _T_4848 ? _Queue2_UInt8_31_io_deq_valid : _T_4847 ? _Queue2_UInt8_30_io_deq_valid : _T_4846 ? _Queue2_UInt8_29_io_deq_valid : _T_4845 ? _Queue2_UInt8_28_io_deq_valid : _T_4844 ? _Queue2_UInt8_27_io_deq_valid : _T_4843 ? _Queue2_UInt8_26_io_deq_valid : _T_4842 ? _Queue2_UInt8_25_io_deq_valid : _T_4841 ? _Queue2_UInt8_24_io_deq_valid : _T_4840 ? _Queue2_UInt8_23_io_deq_valid : _T_4839 ? _Queue2_UInt8_22_io_deq_valid : _T_4838 ? _Queue2_UInt8_21_io_deq_valid : _T_4837 ? _Queue2_UInt8_20_io_deq_valid : _T_4836 ? _Queue2_UInt8_19_io_deq_valid : _T_4835 ? _Queue2_UInt8_18_io_deq_valid : _T_4834 ? _Queue2_UInt8_17_io_deq_valid : _T_4833 ? _Queue2_UInt8_16_io_deq_valid : _T_4832 ? _Queue2_UInt8_15_io_deq_valid : _T_4831 ? _Queue2_UInt8_14_io_deq_valid : _T_4830 ? _Queue2_UInt8_13_io_deq_valid : _T_4829 ? _Queue2_UInt8_12_io_deq_valid : _T_4828 ? _Queue2_UInt8_11_io_deq_valid : _T_4827 ? _Queue2_UInt8_10_io_deq_valid : _T_4826 ? _Queue2_UInt8_9_io_deq_valid : _T_4825 ? _Queue2_UInt8_8_io_deq_valid : _T_4824 ? _Queue2_UInt8_7_io_deq_valid : _T_4823 ? _Queue2_UInt8_6_io_deq_valid : _T_4822 ? _Queue2_UInt8_5_io_deq_valid : _T_4821 ? _Queue2_UInt8_4_io_deq_valid : _T_4820 ? _Queue2_UInt8_3_io_deq_valid : _T_4819 ? _Queue2_UInt8_2_io_deq_valid : _T_4818 ? _Queue2_UInt8_1_io_deq_valid : _T_4817 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_106 = _remapindex_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_16 = _GEN_106[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4849 = remapindex_16 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4850 = remapindex_16 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4851 = remapindex_16 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4852 = remapindex_16 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4853 = remapindex_16 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4854 = remapindex_16 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4855 = remapindex_16 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4856 = remapindex_16 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4857 = remapindex_16 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4858 = remapindex_16 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4859 = remapindex_16 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4860 = remapindex_16 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4861 = remapindex_16 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4862 = remapindex_16 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4863 = remapindex_16 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4864 = remapindex_16 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4865 = remapindex_16 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4866 = remapindex_16 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4867 = remapindex_16 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4868 = remapindex_16 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4869 = remapindex_16 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4870 = remapindex_16 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4871 = remapindex_16 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4872 = remapindex_16 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4873 = remapindex_16 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4874 = remapindex_16 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4875 = remapindex_16 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4876 = remapindex_16 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4877 = remapindex_16 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4878 = remapindex_16 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4879 = remapindex_16 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4880 = remapindex_16 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_16 = _T_4880 ? _Queue2_UInt8_31_io_deq_bits : _T_4879 ? _Queue2_UInt8_30_io_deq_bits : _T_4878 ? _Queue2_UInt8_29_io_deq_bits : _T_4877 ? _Queue2_UInt8_28_io_deq_bits : _T_4876 ? _Queue2_UInt8_27_io_deq_bits : _T_4875 ? _Queue2_UInt8_26_io_deq_bits : _T_4874 ? _Queue2_UInt8_25_io_deq_bits : _T_4873 ? _Queue2_UInt8_24_io_deq_bits : _T_4872 ? _Queue2_UInt8_23_io_deq_bits : _T_4871 ? _Queue2_UInt8_22_io_deq_bits : _T_4870 ? _Queue2_UInt8_21_io_deq_bits : _T_4869 ? _Queue2_UInt8_20_io_deq_bits : _T_4868 ? _Queue2_UInt8_19_io_deq_bits : _T_4867 ? _Queue2_UInt8_18_io_deq_bits : _T_4866 ? _Queue2_UInt8_17_io_deq_bits : _T_4865 ? _Queue2_UInt8_16_io_deq_bits : _T_4864 ? _Queue2_UInt8_15_io_deq_bits : _T_4863 ? _Queue2_UInt8_14_io_deq_bits : _T_4862 ? _Queue2_UInt8_13_io_deq_bits : _T_4861 ? _Queue2_UInt8_12_io_deq_bits : _T_4860 ? _Queue2_UInt8_11_io_deq_bits : _T_4859 ? _Queue2_UInt8_10_io_deq_bits : _T_4858 ? _Queue2_UInt8_9_io_deq_bits : _T_4857 ? _Queue2_UInt8_8_io_deq_bits : _T_4856 ? _Queue2_UInt8_7_io_deq_bits : _T_4855 ? _Queue2_UInt8_6_io_deq_bits : _T_4854 ? _Queue2_UInt8_5_io_deq_bits : _T_4853 ? _Queue2_UInt8_4_io_deq_bits : _T_4852 ? _Queue2_UInt8_3_io_deq_bits : _T_4851 ? _Queue2_UInt8_2_io_deq_bits : _T_4850 ? _Queue2_UInt8_1_io_deq_bits : _T_4849 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_16 = _T_4880 ? _Queue2_UInt8_31_io_deq_valid : _T_4879 ? _Queue2_UInt8_30_io_deq_valid : _T_4878 ? _Queue2_UInt8_29_io_deq_valid : _T_4877 ? _Queue2_UInt8_28_io_deq_valid : _T_4876 ? _Queue2_UInt8_27_io_deq_valid : _T_4875 ? _Queue2_UInt8_26_io_deq_valid : _T_4874 ? _Queue2_UInt8_25_io_deq_valid : _T_4873 ? _Queue2_UInt8_24_io_deq_valid : _T_4872 ? _Queue2_UInt8_23_io_deq_valid : _T_4871 ? _Queue2_UInt8_22_io_deq_valid : _T_4870 ? _Queue2_UInt8_21_io_deq_valid : _T_4869 ? _Queue2_UInt8_20_io_deq_valid : _T_4868 ? _Queue2_UInt8_19_io_deq_valid : _T_4867 ? _Queue2_UInt8_18_io_deq_valid : _T_4866 ? _Queue2_UInt8_17_io_deq_valid : _T_4865 ? _Queue2_UInt8_16_io_deq_valid : _T_4864 ? _Queue2_UInt8_15_io_deq_valid : _T_4863 ? _Queue2_UInt8_14_io_deq_valid : _T_4862 ? _Queue2_UInt8_13_io_deq_valid : _T_4861 ? _Queue2_UInt8_12_io_deq_valid : _T_4860 ? _Queue2_UInt8_11_io_deq_valid : _T_4859 ? _Queue2_UInt8_10_io_deq_valid : _T_4858 ? _Queue2_UInt8_9_io_deq_valid : _T_4857 ? _Queue2_UInt8_8_io_deq_valid : _T_4856 ? _Queue2_UInt8_7_io_deq_valid : _T_4855 ? _Queue2_UInt8_6_io_deq_valid : _T_4854 ? _Queue2_UInt8_5_io_deq_valid : _T_4853 ? _Queue2_UInt8_4_io_deq_valid : _T_4852 ? _Queue2_UInt8_3_io_deq_valid : _T_4851 ? _Queue2_UInt8_2_io_deq_valid : _T_4850 ? _Queue2_UInt8_1_io_deq_valid : _T_4849 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_107 = _remapindex_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_17 = _GEN_107[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4881 = remapindex_17 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4882 = remapindex_17 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4883 = remapindex_17 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4884 = remapindex_17 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4885 = remapindex_17 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4886 = remapindex_17 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4887 = remapindex_17 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4888 = remapindex_17 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4889 = remapindex_17 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4890 = remapindex_17 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4891 = remapindex_17 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4892 = remapindex_17 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4893 = remapindex_17 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4894 = remapindex_17 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4895 = remapindex_17 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4896 = remapindex_17 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4897 = remapindex_17 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4898 = remapindex_17 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4899 = remapindex_17 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4900 = remapindex_17 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4901 = remapindex_17 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4902 = remapindex_17 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4903 = remapindex_17 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4904 = remapindex_17 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4905 = remapindex_17 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4906 = remapindex_17 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4907 = remapindex_17 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4908 = remapindex_17 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4909 = remapindex_17 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4910 = remapindex_17 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4911 = remapindex_17 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4912 = remapindex_17 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_17 = _T_4912 ? _Queue2_UInt8_31_io_deq_bits : _T_4911 ? _Queue2_UInt8_30_io_deq_bits : _T_4910 ? _Queue2_UInt8_29_io_deq_bits : _T_4909 ? _Queue2_UInt8_28_io_deq_bits : _T_4908 ? _Queue2_UInt8_27_io_deq_bits : _T_4907 ? _Queue2_UInt8_26_io_deq_bits : _T_4906 ? _Queue2_UInt8_25_io_deq_bits : _T_4905 ? _Queue2_UInt8_24_io_deq_bits : _T_4904 ? _Queue2_UInt8_23_io_deq_bits : _T_4903 ? _Queue2_UInt8_22_io_deq_bits : _T_4902 ? _Queue2_UInt8_21_io_deq_bits : _T_4901 ? _Queue2_UInt8_20_io_deq_bits : _T_4900 ? _Queue2_UInt8_19_io_deq_bits : _T_4899 ? _Queue2_UInt8_18_io_deq_bits : _T_4898 ? _Queue2_UInt8_17_io_deq_bits : _T_4897 ? _Queue2_UInt8_16_io_deq_bits : _T_4896 ? _Queue2_UInt8_15_io_deq_bits : _T_4895 ? _Queue2_UInt8_14_io_deq_bits : _T_4894 ? _Queue2_UInt8_13_io_deq_bits : _T_4893 ? _Queue2_UInt8_12_io_deq_bits : _T_4892 ? _Queue2_UInt8_11_io_deq_bits : _T_4891 ? _Queue2_UInt8_10_io_deq_bits : _T_4890 ? _Queue2_UInt8_9_io_deq_bits : _T_4889 ? _Queue2_UInt8_8_io_deq_bits : _T_4888 ? _Queue2_UInt8_7_io_deq_bits : _T_4887 ? _Queue2_UInt8_6_io_deq_bits : _T_4886 ? _Queue2_UInt8_5_io_deq_bits : _T_4885 ? _Queue2_UInt8_4_io_deq_bits : _T_4884 ? _Queue2_UInt8_3_io_deq_bits : _T_4883 ? _Queue2_UInt8_2_io_deq_bits : _T_4882 ? _Queue2_UInt8_1_io_deq_bits : _T_4881 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_17 = _T_4912 ? _Queue2_UInt8_31_io_deq_valid : _T_4911 ? _Queue2_UInt8_30_io_deq_valid : _T_4910 ? _Queue2_UInt8_29_io_deq_valid : _T_4909 ? _Queue2_UInt8_28_io_deq_valid : _T_4908 ? _Queue2_UInt8_27_io_deq_valid : _T_4907 ? _Queue2_UInt8_26_io_deq_valid : _T_4906 ? _Queue2_UInt8_25_io_deq_valid : _T_4905 ? _Queue2_UInt8_24_io_deq_valid : _T_4904 ? _Queue2_UInt8_23_io_deq_valid : _T_4903 ? _Queue2_UInt8_22_io_deq_valid : _T_4902 ? _Queue2_UInt8_21_io_deq_valid : _T_4901 ? _Queue2_UInt8_20_io_deq_valid : _T_4900 ? _Queue2_UInt8_19_io_deq_valid : _T_4899 ? _Queue2_UInt8_18_io_deq_valid : _T_4898 ? _Queue2_UInt8_17_io_deq_valid : _T_4897 ? _Queue2_UInt8_16_io_deq_valid : _T_4896 ? _Queue2_UInt8_15_io_deq_valid : _T_4895 ? _Queue2_UInt8_14_io_deq_valid : _T_4894 ? _Queue2_UInt8_13_io_deq_valid : _T_4893 ? _Queue2_UInt8_12_io_deq_valid : _T_4892 ? _Queue2_UInt8_11_io_deq_valid : _T_4891 ? _Queue2_UInt8_10_io_deq_valid : _T_4890 ? _Queue2_UInt8_9_io_deq_valid : _T_4889 ? _Queue2_UInt8_8_io_deq_valid : _T_4888 ? _Queue2_UInt8_7_io_deq_valid : _T_4887 ? _Queue2_UInt8_6_io_deq_valid : _T_4886 ? _Queue2_UInt8_5_io_deq_valid : _T_4885 ? _Queue2_UInt8_4_io_deq_valid : _T_4884 ? _Queue2_UInt8_3_io_deq_valid : _T_4883 ? _Queue2_UInt8_2_io_deq_valid : _T_4882 ? _Queue2_UInt8_1_io_deq_valid : _T_4881 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_108 = _remapindex_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_18 = _GEN_108[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4913 = remapindex_18 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4914 = remapindex_18 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4915 = remapindex_18 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4916 = remapindex_18 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4917 = remapindex_18 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4918 = remapindex_18 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4919 = remapindex_18 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4920 = remapindex_18 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4921 = remapindex_18 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4922 = remapindex_18 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4923 = remapindex_18 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4924 = remapindex_18 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4925 = remapindex_18 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4926 = remapindex_18 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4927 = remapindex_18 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4928 = remapindex_18 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4929 = remapindex_18 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4930 = remapindex_18 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4931 = remapindex_18 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4932 = remapindex_18 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4933 = remapindex_18 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4934 = remapindex_18 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4935 = remapindex_18 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4936 = remapindex_18 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4937 = remapindex_18 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4938 = remapindex_18 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4939 = remapindex_18 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4940 = remapindex_18 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4941 = remapindex_18 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4942 = remapindex_18 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4943 = remapindex_18 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4944 = remapindex_18 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_18 = _T_4944 ? _Queue2_UInt8_31_io_deq_bits : _T_4943 ? _Queue2_UInt8_30_io_deq_bits : _T_4942 ? _Queue2_UInt8_29_io_deq_bits : _T_4941 ? _Queue2_UInt8_28_io_deq_bits : _T_4940 ? _Queue2_UInt8_27_io_deq_bits : _T_4939 ? _Queue2_UInt8_26_io_deq_bits : _T_4938 ? _Queue2_UInt8_25_io_deq_bits : _T_4937 ? _Queue2_UInt8_24_io_deq_bits : _T_4936 ? _Queue2_UInt8_23_io_deq_bits : _T_4935 ? _Queue2_UInt8_22_io_deq_bits : _T_4934 ? _Queue2_UInt8_21_io_deq_bits : _T_4933 ? _Queue2_UInt8_20_io_deq_bits : _T_4932 ? _Queue2_UInt8_19_io_deq_bits : _T_4931 ? _Queue2_UInt8_18_io_deq_bits : _T_4930 ? _Queue2_UInt8_17_io_deq_bits : _T_4929 ? _Queue2_UInt8_16_io_deq_bits : _T_4928 ? _Queue2_UInt8_15_io_deq_bits : _T_4927 ? _Queue2_UInt8_14_io_deq_bits : _T_4926 ? _Queue2_UInt8_13_io_deq_bits : _T_4925 ? _Queue2_UInt8_12_io_deq_bits : _T_4924 ? _Queue2_UInt8_11_io_deq_bits : _T_4923 ? _Queue2_UInt8_10_io_deq_bits : _T_4922 ? _Queue2_UInt8_9_io_deq_bits : _T_4921 ? _Queue2_UInt8_8_io_deq_bits : _T_4920 ? _Queue2_UInt8_7_io_deq_bits : _T_4919 ? _Queue2_UInt8_6_io_deq_bits : _T_4918 ? _Queue2_UInt8_5_io_deq_bits : _T_4917 ? _Queue2_UInt8_4_io_deq_bits : _T_4916 ? _Queue2_UInt8_3_io_deq_bits : _T_4915 ? _Queue2_UInt8_2_io_deq_bits : _T_4914 ? _Queue2_UInt8_1_io_deq_bits : _T_4913 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_18 = _T_4944 ? _Queue2_UInt8_31_io_deq_valid : _T_4943 ? _Queue2_UInt8_30_io_deq_valid : _T_4942 ? _Queue2_UInt8_29_io_deq_valid : _T_4941 ? _Queue2_UInt8_28_io_deq_valid : _T_4940 ? _Queue2_UInt8_27_io_deq_valid : _T_4939 ? _Queue2_UInt8_26_io_deq_valid : _T_4938 ? _Queue2_UInt8_25_io_deq_valid : _T_4937 ? _Queue2_UInt8_24_io_deq_valid : _T_4936 ? _Queue2_UInt8_23_io_deq_valid : _T_4935 ? _Queue2_UInt8_22_io_deq_valid : _T_4934 ? _Queue2_UInt8_21_io_deq_valid : _T_4933 ? _Queue2_UInt8_20_io_deq_valid : _T_4932 ? _Queue2_UInt8_19_io_deq_valid : _T_4931 ? _Queue2_UInt8_18_io_deq_valid : _T_4930 ? _Queue2_UInt8_17_io_deq_valid : _T_4929 ? _Queue2_UInt8_16_io_deq_valid : _T_4928 ? _Queue2_UInt8_15_io_deq_valid : _T_4927 ? _Queue2_UInt8_14_io_deq_valid : _T_4926 ? _Queue2_UInt8_13_io_deq_valid : _T_4925 ? _Queue2_UInt8_12_io_deq_valid : _T_4924 ? _Queue2_UInt8_11_io_deq_valid : _T_4923 ? _Queue2_UInt8_10_io_deq_valid : _T_4922 ? _Queue2_UInt8_9_io_deq_valid : _T_4921 ? _Queue2_UInt8_8_io_deq_valid : _T_4920 ? _Queue2_UInt8_7_io_deq_valid : _T_4919 ? _Queue2_UInt8_6_io_deq_valid : _T_4918 ? _Queue2_UInt8_5_io_deq_valid : _T_4917 ? _Queue2_UInt8_4_io_deq_valid : _T_4916 ? _Queue2_UInt8_3_io_deq_valid : _T_4915 ? _Queue2_UInt8_2_io_deq_valid : _T_4914 ? _Queue2_UInt8_1_io_deq_valid : _T_4913 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_109 = _remapindex_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_19 = _GEN_109[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4945 = remapindex_19 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4946 = remapindex_19 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4947 = remapindex_19 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4948 = remapindex_19 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4949 = remapindex_19 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4950 = remapindex_19 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4951 = remapindex_19 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4952 = remapindex_19 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4953 = remapindex_19 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4954 = remapindex_19 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4955 = remapindex_19 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4956 = remapindex_19 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4957 = remapindex_19 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4958 = remapindex_19 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4959 = remapindex_19 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4960 = remapindex_19 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4961 = remapindex_19 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4962 = remapindex_19 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4963 = remapindex_19 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4964 = remapindex_19 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4965 = remapindex_19 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4966 = remapindex_19 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4967 = remapindex_19 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4968 = remapindex_19 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4969 = remapindex_19 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4970 = remapindex_19 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4971 = remapindex_19 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4972 = remapindex_19 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4973 = remapindex_19 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4974 = remapindex_19 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4975 = remapindex_19 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4976 = remapindex_19 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_19 = _T_4976 ? _Queue2_UInt8_31_io_deq_bits : _T_4975 ? _Queue2_UInt8_30_io_deq_bits : _T_4974 ? _Queue2_UInt8_29_io_deq_bits : _T_4973 ? _Queue2_UInt8_28_io_deq_bits : _T_4972 ? _Queue2_UInt8_27_io_deq_bits : _T_4971 ? _Queue2_UInt8_26_io_deq_bits : _T_4970 ? _Queue2_UInt8_25_io_deq_bits : _T_4969 ? _Queue2_UInt8_24_io_deq_bits : _T_4968 ? _Queue2_UInt8_23_io_deq_bits : _T_4967 ? _Queue2_UInt8_22_io_deq_bits : _T_4966 ? _Queue2_UInt8_21_io_deq_bits : _T_4965 ? _Queue2_UInt8_20_io_deq_bits : _T_4964 ? _Queue2_UInt8_19_io_deq_bits : _T_4963 ? _Queue2_UInt8_18_io_deq_bits : _T_4962 ? _Queue2_UInt8_17_io_deq_bits : _T_4961 ? _Queue2_UInt8_16_io_deq_bits : _T_4960 ? _Queue2_UInt8_15_io_deq_bits : _T_4959 ? _Queue2_UInt8_14_io_deq_bits : _T_4958 ? _Queue2_UInt8_13_io_deq_bits : _T_4957 ? _Queue2_UInt8_12_io_deq_bits : _T_4956 ? _Queue2_UInt8_11_io_deq_bits : _T_4955 ? _Queue2_UInt8_10_io_deq_bits : _T_4954 ? _Queue2_UInt8_9_io_deq_bits : _T_4953 ? _Queue2_UInt8_8_io_deq_bits : _T_4952 ? _Queue2_UInt8_7_io_deq_bits : _T_4951 ? _Queue2_UInt8_6_io_deq_bits : _T_4950 ? _Queue2_UInt8_5_io_deq_bits : _T_4949 ? _Queue2_UInt8_4_io_deq_bits : _T_4948 ? _Queue2_UInt8_3_io_deq_bits : _T_4947 ? _Queue2_UInt8_2_io_deq_bits : _T_4946 ? _Queue2_UInt8_1_io_deq_bits : _T_4945 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_19 = _T_4976 ? _Queue2_UInt8_31_io_deq_valid : _T_4975 ? _Queue2_UInt8_30_io_deq_valid : _T_4974 ? _Queue2_UInt8_29_io_deq_valid : _T_4973 ? _Queue2_UInt8_28_io_deq_valid : _T_4972 ? _Queue2_UInt8_27_io_deq_valid : _T_4971 ? _Queue2_UInt8_26_io_deq_valid : _T_4970 ? _Queue2_UInt8_25_io_deq_valid : _T_4969 ? _Queue2_UInt8_24_io_deq_valid : _T_4968 ? _Queue2_UInt8_23_io_deq_valid : _T_4967 ? _Queue2_UInt8_22_io_deq_valid : _T_4966 ? _Queue2_UInt8_21_io_deq_valid : _T_4965 ? _Queue2_UInt8_20_io_deq_valid : _T_4964 ? _Queue2_UInt8_19_io_deq_valid : _T_4963 ? _Queue2_UInt8_18_io_deq_valid : _T_4962 ? _Queue2_UInt8_17_io_deq_valid : _T_4961 ? _Queue2_UInt8_16_io_deq_valid : _T_4960 ? _Queue2_UInt8_15_io_deq_valid : _T_4959 ? _Queue2_UInt8_14_io_deq_valid : _T_4958 ? _Queue2_UInt8_13_io_deq_valid : _T_4957 ? _Queue2_UInt8_12_io_deq_valid : _T_4956 ? _Queue2_UInt8_11_io_deq_valid : _T_4955 ? _Queue2_UInt8_10_io_deq_valid : _T_4954 ? _Queue2_UInt8_9_io_deq_valid : _T_4953 ? _Queue2_UInt8_8_io_deq_valid : _T_4952 ? _Queue2_UInt8_7_io_deq_valid : _T_4951 ? _Queue2_UInt8_6_io_deq_valid : _T_4950 ? _Queue2_UInt8_5_io_deq_valid : _T_4949 ? _Queue2_UInt8_4_io_deq_valid : _T_4948 ? _Queue2_UInt8_3_io_deq_valid : _T_4947 ? _Queue2_UInt8_2_io_deq_valid : _T_4946 ? _Queue2_UInt8_1_io_deq_valid : _T_4945 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_110 = _remapindex_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_20 = _GEN_110[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4977 = remapindex_20 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4978 = remapindex_20 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4979 = remapindex_20 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4980 = remapindex_20 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4981 = remapindex_20 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4982 = remapindex_20 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4983 = remapindex_20 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4984 = remapindex_20 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4985 = remapindex_20 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4986 = remapindex_20 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4987 = remapindex_20 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4988 = remapindex_20 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4989 = remapindex_20 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4990 = remapindex_20 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4991 = remapindex_20 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4992 = remapindex_20 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4993 = remapindex_20 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4994 = remapindex_20 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4995 = remapindex_20 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4996 = remapindex_20 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4997 = remapindex_20 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4998 = remapindex_20 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4999 = remapindex_20 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5000 = remapindex_20 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5001 = remapindex_20 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5002 = remapindex_20 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5003 = remapindex_20 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5004 = remapindex_20 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5005 = remapindex_20 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5006 = remapindex_20 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5007 = remapindex_20 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5008 = remapindex_20 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_20 = _T_5008 ? _Queue2_UInt8_31_io_deq_bits : _T_5007 ? _Queue2_UInt8_30_io_deq_bits : _T_5006 ? _Queue2_UInt8_29_io_deq_bits : _T_5005 ? _Queue2_UInt8_28_io_deq_bits : _T_5004 ? _Queue2_UInt8_27_io_deq_bits : _T_5003 ? _Queue2_UInt8_26_io_deq_bits : _T_5002 ? _Queue2_UInt8_25_io_deq_bits : _T_5001 ? _Queue2_UInt8_24_io_deq_bits : _T_5000 ? _Queue2_UInt8_23_io_deq_bits : _T_4999 ? _Queue2_UInt8_22_io_deq_bits : _T_4998 ? _Queue2_UInt8_21_io_deq_bits : _T_4997 ? _Queue2_UInt8_20_io_deq_bits : _T_4996 ? _Queue2_UInt8_19_io_deq_bits : _T_4995 ? _Queue2_UInt8_18_io_deq_bits : _T_4994 ? _Queue2_UInt8_17_io_deq_bits : _T_4993 ? _Queue2_UInt8_16_io_deq_bits : _T_4992 ? _Queue2_UInt8_15_io_deq_bits : _T_4991 ? _Queue2_UInt8_14_io_deq_bits : _T_4990 ? _Queue2_UInt8_13_io_deq_bits : _T_4989 ? _Queue2_UInt8_12_io_deq_bits : _T_4988 ? _Queue2_UInt8_11_io_deq_bits : _T_4987 ? _Queue2_UInt8_10_io_deq_bits : _T_4986 ? _Queue2_UInt8_9_io_deq_bits : _T_4985 ? _Queue2_UInt8_8_io_deq_bits : _T_4984 ? _Queue2_UInt8_7_io_deq_bits : _T_4983 ? _Queue2_UInt8_6_io_deq_bits : _T_4982 ? _Queue2_UInt8_5_io_deq_bits : _T_4981 ? _Queue2_UInt8_4_io_deq_bits : _T_4980 ? _Queue2_UInt8_3_io_deq_bits : _T_4979 ? _Queue2_UInt8_2_io_deq_bits : _T_4978 ? _Queue2_UInt8_1_io_deq_bits : _T_4977 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_20 = _T_5008 ? _Queue2_UInt8_31_io_deq_valid : _T_5007 ? _Queue2_UInt8_30_io_deq_valid : _T_5006 ? _Queue2_UInt8_29_io_deq_valid : _T_5005 ? _Queue2_UInt8_28_io_deq_valid : _T_5004 ? _Queue2_UInt8_27_io_deq_valid : _T_5003 ? _Queue2_UInt8_26_io_deq_valid : _T_5002 ? _Queue2_UInt8_25_io_deq_valid : _T_5001 ? _Queue2_UInt8_24_io_deq_valid : _T_5000 ? _Queue2_UInt8_23_io_deq_valid : _T_4999 ? _Queue2_UInt8_22_io_deq_valid : _T_4998 ? _Queue2_UInt8_21_io_deq_valid : _T_4997 ? _Queue2_UInt8_20_io_deq_valid : _T_4996 ? _Queue2_UInt8_19_io_deq_valid : _T_4995 ? _Queue2_UInt8_18_io_deq_valid : _T_4994 ? _Queue2_UInt8_17_io_deq_valid : _T_4993 ? _Queue2_UInt8_16_io_deq_valid : _T_4992 ? _Queue2_UInt8_15_io_deq_valid : _T_4991 ? _Queue2_UInt8_14_io_deq_valid : _T_4990 ? _Queue2_UInt8_13_io_deq_valid : _T_4989 ? _Queue2_UInt8_12_io_deq_valid : _T_4988 ? _Queue2_UInt8_11_io_deq_valid : _T_4987 ? _Queue2_UInt8_10_io_deq_valid : _T_4986 ? _Queue2_UInt8_9_io_deq_valid : _T_4985 ? _Queue2_UInt8_8_io_deq_valid : _T_4984 ? _Queue2_UInt8_7_io_deq_valid : _T_4983 ? _Queue2_UInt8_6_io_deq_valid : _T_4982 ? _Queue2_UInt8_5_io_deq_valid : _T_4981 ? _Queue2_UInt8_4_io_deq_valid : _T_4980 ? _Queue2_UInt8_3_io_deq_valid : _T_4979 ? _Queue2_UInt8_2_io_deq_valid : _T_4978 ? _Queue2_UInt8_1_io_deq_valid : _T_4977 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_111 = _remapindex_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_21 = _GEN_111[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5009 = remapindex_21 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5010 = remapindex_21 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5011 = remapindex_21 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5012 = remapindex_21 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5013 = remapindex_21 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5014 = remapindex_21 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5015 = remapindex_21 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5016 = remapindex_21 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5017 = remapindex_21 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5018 = remapindex_21 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5019 = remapindex_21 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5020 = remapindex_21 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5021 = remapindex_21 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5022 = remapindex_21 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5023 = remapindex_21 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5024 = remapindex_21 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5025 = remapindex_21 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5026 = remapindex_21 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5027 = remapindex_21 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5028 = remapindex_21 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5029 = remapindex_21 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5030 = remapindex_21 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5031 = remapindex_21 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5032 = remapindex_21 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5033 = remapindex_21 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5034 = remapindex_21 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5035 = remapindex_21 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5036 = remapindex_21 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5037 = remapindex_21 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5038 = remapindex_21 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5039 = remapindex_21 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5040 = remapindex_21 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_21 = _T_5040 ? _Queue2_UInt8_31_io_deq_bits : _T_5039 ? _Queue2_UInt8_30_io_deq_bits : _T_5038 ? _Queue2_UInt8_29_io_deq_bits : _T_5037 ? _Queue2_UInt8_28_io_deq_bits : _T_5036 ? _Queue2_UInt8_27_io_deq_bits : _T_5035 ? _Queue2_UInt8_26_io_deq_bits : _T_5034 ? _Queue2_UInt8_25_io_deq_bits : _T_5033 ? _Queue2_UInt8_24_io_deq_bits : _T_5032 ? _Queue2_UInt8_23_io_deq_bits : _T_5031 ? _Queue2_UInt8_22_io_deq_bits : _T_5030 ? _Queue2_UInt8_21_io_deq_bits : _T_5029 ? _Queue2_UInt8_20_io_deq_bits : _T_5028 ? _Queue2_UInt8_19_io_deq_bits : _T_5027 ? _Queue2_UInt8_18_io_deq_bits : _T_5026 ? _Queue2_UInt8_17_io_deq_bits : _T_5025 ? _Queue2_UInt8_16_io_deq_bits : _T_5024 ? _Queue2_UInt8_15_io_deq_bits : _T_5023 ? _Queue2_UInt8_14_io_deq_bits : _T_5022 ? _Queue2_UInt8_13_io_deq_bits : _T_5021 ? _Queue2_UInt8_12_io_deq_bits : _T_5020 ? _Queue2_UInt8_11_io_deq_bits : _T_5019 ? _Queue2_UInt8_10_io_deq_bits : _T_5018 ? _Queue2_UInt8_9_io_deq_bits : _T_5017 ? _Queue2_UInt8_8_io_deq_bits : _T_5016 ? _Queue2_UInt8_7_io_deq_bits : _T_5015 ? _Queue2_UInt8_6_io_deq_bits : _T_5014 ? _Queue2_UInt8_5_io_deq_bits : _T_5013 ? _Queue2_UInt8_4_io_deq_bits : _T_5012 ? _Queue2_UInt8_3_io_deq_bits : _T_5011 ? _Queue2_UInt8_2_io_deq_bits : _T_5010 ? _Queue2_UInt8_1_io_deq_bits : _T_5009 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_21 = _T_5040 ? _Queue2_UInt8_31_io_deq_valid : _T_5039 ? _Queue2_UInt8_30_io_deq_valid : _T_5038 ? _Queue2_UInt8_29_io_deq_valid : _T_5037 ? _Queue2_UInt8_28_io_deq_valid : _T_5036 ? _Queue2_UInt8_27_io_deq_valid : _T_5035 ? _Queue2_UInt8_26_io_deq_valid : _T_5034 ? _Queue2_UInt8_25_io_deq_valid : _T_5033 ? _Queue2_UInt8_24_io_deq_valid : _T_5032 ? _Queue2_UInt8_23_io_deq_valid : _T_5031 ? _Queue2_UInt8_22_io_deq_valid : _T_5030 ? _Queue2_UInt8_21_io_deq_valid : _T_5029 ? _Queue2_UInt8_20_io_deq_valid : _T_5028 ? _Queue2_UInt8_19_io_deq_valid : _T_5027 ? _Queue2_UInt8_18_io_deq_valid : _T_5026 ? _Queue2_UInt8_17_io_deq_valid : _T_5025 ? _Queue2_UInt8_16_io_deq_valid : _T_5024 ? _Queue2_UInt8_15_io_deq_valid : _T_5023 ? _Queue2_UInt8_14_io_deq_valid : _T_5022 ? _Queue2_UInt8_13_io_deq_valid : _T_5021 ? _Queue2_UInt8_12_io_deq_valid : _T_5020 ? _Queue2_UInt8_11_io_deq_valid : _T_5019 ? _Queue2_UInt8_10_io_deq_valid : _T_5018 ? _Queue2_UInt8_9_io_deq_valid : _T_5017 ? _Queue2_UInt8_8_io_deq_valid : _T_5016 ? _Queue2_UInt8_7_io_deq_valid : _T_5015 ? _Queue2_UInt8_6_io_deq_valid : _T_5014 ? _Queue2_UInt8_5_io_deq_valid : _T_5013 ? _Queue2_UInt8_4_io_deq_valid : _T_5012 ? _Queue2_UInt8_3_io_deq_valid : _T_5011 ? _Queue2_UInt8_2_io_deq_valid : _T_5010 ? _Queue2_UInt8_1_io_deq_valid : _T_5009 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_112 = _remapindex_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_22 = _GEN_112[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5041 = remapindex_22 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5042 = remapindex_22 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5043 = remapindex_22 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5044 = remapindex_22 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5045 = remapindex_22 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5046 = remapindex_22 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5047 = remapindex_22 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5048 = remapindex_22 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5049 = remapindex_22 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5050 = remapindex_22 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5051 = remapindex_22 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5052 = remapindex_22 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5053 = remapindex_22 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5054 = remapindex_22 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5055 = remapindex_22 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5056 = remapindex_22 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5057 = remapindex_22 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5058 = remapindex_22 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5059 = remapindex_22 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5060 = remapindex_22 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5061 = remapindex_22 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5062 = remapindex_22 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5063 = remapindex_22 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5064 = remapindex_22 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5065 = remapindex_22 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5066 = remapindex_22 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5067 = remapindex_22 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5068 = remapindex_22 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5069 = remapindex_22 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5070 = remapindex_22 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5071 = remapindex_22 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5072 = remapindex_22 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_22 = _T_5072 ? _Queue2_UInt8_31_io_deq_bits : _T_5071 ? _Queue2_UInt8_30_io_deq_bits : _T_5070 ? _Queue2_UInt8_29_io_deq_bits : _T_5069 ? _Queue2_UInt8_28_io_deq_bits : _T_5068 ? _Queue2_UInt8_27_io_deq_bits : _T_5067 ? _Queue2_UInt8_26_io_deq_bits : _T_5066 ? _Queue2_UInt8_25_io_deq_bits : _T_5065 ? _Queue2_UInt8_24_io_deq_bits : _T_5064 ? _Queue2_UInt8_23_io_deq_bits : _T_5063 ? _Queue2_UInt8_22_io_deq_bits : _T_5062 ? _Queue2_UInt8_21_io_deq_bits : _T_5061 ? _Queue2_UInt8_20_io_deq_bits : _T_5060 ? _Queue2_UInt8_19_io_deq_bits : _T_5059 ? _Queue2_UInt8_18_io_deq_bits : _T_5058 ? _Queue2_UInt8_17_io_deq_bits : _T_5057 ? _Queue2_UInt8_16_io_deq_bits : _T_5056 ? _Queue2_UInt8_15_io_deq_bits : _T_5055 ? _Queue2_UInt8_14_io_deq_bits : _T_5054 ? _Queue2_UInt8_13_io_deq_bits : _T_5053 ? _Queue2_UInt8_12_io_deq_bits : _T_5052 ? _Queue2_UInt8_11_io_deq_bits : _T_5051 ? _Queue2_UInt8_10_io_deq_bits : _T_5050 ? _Queue2_UInt8_9_io_deq_bits : _T_5049 ? _Queue2_UInt8_8_io_deq_bits : _T_5048 ? _Queue2_UInt8_7_io_deq_bits : _T_5047 ? _Queue2_UInt8_6_io_deq_bits : _T_5046 ? _Queue2_UInt8_5_io_deq_bits : _T_5045 ? _Queue2_UInt8_4_io_deq_bits : _T_5044 ? _Queue2_UInt8_3_io_deq_bits : _T_5043 ? _Queue2_UInt8_2_io_deq_bits : _T_5042 ? _Queue2_UInt8_1_io_deq_bits : _T_5041 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_22 = _T_5072 ? _Queue2_UInt8_31_io_deq_valid : _T_5071 ? _Queue2_UInt8_30_io_deq_valid : _T_5070 ? _Queue2_UInt8_29_io_deq_valid : _T_5069 ? _Queue2_UInt8_28_io_deq_valid : _T_5068 ? _Queue2_UInt8_27_io_deq_valid : _T_5067 ? _Queue2_UInt8_26_io_deq_valid : _T_5066 ? _Queue2_UInt8_25_io_deq_valid : _T_5065 ? _Queue2_UInt8_24_io_deq_valid : _T_5064 ? _Queue2_UInt8_23_io_deq_valid : _T_5063 ? _Queue2_UInt8_22_io_deq_valid : _T_5062 ? _Queue2_UInt8_21_io_deq_valid : _T_5061 ? _Queue2_UInt8_20_io_deq_valid : _T_5060 ? _Queue2_UInt8_19_io_deq_valid : _T_5059 ? _Queue2_UInt8_18_io_deq_valid : _T_5058 ? _Queue2_UInt8_17_io_deq_valid : _T_5057 ? _Queue2_UInt8_16_io_deq_valid : _T_5056 ? _Queue2_UInt8_15_io_deq_valid : _T_5055 ? _Queue2_UInt8_14_io_deq_valid : _T_5054 ? _Queue2_UInt8_13_io_deq_valid : _T_5053 ? _Queue2_UInt8_12_io_deq_valid : _T_5052 ? _Queue2_UInt8_11_io_deq_valid : _T_5051 ? _Queue2_UInt8_10_io_deq_valid : _T_5050 ? _Queue2_UInt8_9_io_deq_valid : _T_5049 ? _Queue2_UInt8_8_io_deq_valid : _T_5048 ? _Queue2_UInt8_7_io_deq_valid : _T_5047 ? _Queue2_UInt8_6_io_deq_valid : _T_5046 ? _Queue2_UInt8_5_io_deq_valid : _T_5045 ? _Queue2_UInt8_4_io_deq_valid : _T_5044 ? _Queue2_UInt8_3_io_deq_valid : _T_5043 ? _Queue2_UInt8_2_io_deq_valid : _T_5042 ? _Queue2_UInt8_1_io_deq_valid : _T_5041 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_113 = _remapindex_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_23 = _GEN_113[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5073 = remapindex_23 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5074 = remapindex_23 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5075 = remapindex_23 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5076 = remapindex_23 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5077 = remapindex_23 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5078 = remapindex_23 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5079 = remapindex_23 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5080 = remapindex_23 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5081 = remapindex_23 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5082 = remapindex_23 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5083 = remapindex_23 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5084 = remapindex_23 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5085 = remapindex_23 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5086 = remapindex_23 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5087 = remapindex_23 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5088 = remapindex_23 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5089 = remapindex_23 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5090 = remapindex_23 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5091 = remapindex_23 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5092 = remapindex_23 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5093 = remapindex_23 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5094 = remapindex_23 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5095 = remapindex_23 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5096 = remapindex_23 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5097 = remapindex_23 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5098 = remapindex_23 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5099 = remapindex_23 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5100 = remapindex_23 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5101 = remapindex_23 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5102 = remapindex_23 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5103 = remapindex_23 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5104 = remapindex_23 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_23 = _T_5104 ? _Queue2_UInt8_31_io_deq_bits : _T_5103 ? _Queue2_UInt8_30_io_deq_bits : _T_5102 ? _Queue2_UInt8_29_io_deq_bits : _T_5101 ? _Queue2_UInt8_28_io_deq_bits : _T_5100 ? _Queue2_UInt8_27_io_deq_bits : _T_5099 ? _Queue2_UInt8_26_io_deq_bits : _T_5098 ? _Queue2_UInt8_25_io_deq_bits : _T_5097 ? _Queue2_UInt8_24_io_deq_bits : _T_5096 ? _Queue2_UInt8_23_io_deq_bits : _T_5095 ? _Queue2_UInt8_22_io_deq_bits : _T_5094 ? _Queue2_UInt8_21_io_deq_bits : _T_5093 ? _Queue2_UInt8_20_io_deq_bits : _T_5092 ? _Queue2_UInt8_19_io_deq_bits : _T_5091 ? _Queue2_UInt8_18_io_deq_bits : _T_5090 ? _Queue2_UInt8_17_io_deq_bits : _T_5089 ? _Queue2_UInt8_16_io_deq_bits : _T_5088 ? _Queue2_UInt8_15_io_deq_bits : _T_5087 ? _Queue2_UInt8_14_io_deq_bits : _T_5086 ? _Queue2_UInt8_13_io_deq_bits : _T_5085 ? _Queue2_UInt8_12_io_deq_bits : _T_5084 ? _Queue2_UInt8_11_io_deq_bits : _T_5083 ? _Queue2_UInt8_10_io_deq_bits : _T_5082 ? _Queue2_UInt8_9_io_deq_bits : _T_5081 ? _Queue2_UInt8_8_io_deq_bits : _T_5080 ? _Queue2_UInt8_7_io_deq_bits : _T_5079 ? _Queue2_UInt8_6_io_deq_bits : _T_5078 ? _Queue2_UInt8_5_io_deq_bits : _T_5077 ? _Queue2_UInt8_4_io_deq_bits : _T_5076 ? _Queue2_UInt8_3_io_deq_bits : _T_5075 ? _Queue2_UInt8_2_io_deq_bits : _T_5074 ? _Queue2_UInt8_1_io_deq_bits : _T_5073 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_23 = _T_5104 ? _Queue2_UInt8_31_io_deq_valid : _T_5103 ? _Queue2_UInt8_30_io_deq_valid : _T_5102 ? _Queue2_UInt8_29_io_deq_valid : _T_5101 ? _Queue2_UInt8_28_io_deq_valid : _T_5100 ? _Queue2_UInt8_27_io_deq_valid : _T_5099 ? _Queue2_UInt8_26_io_deq_valid : _T_5098 ? _Queue2_UInt8_25_io_deq_valid : _T_5097 ? _Queue2_UInt8_24_io_deq_valid : _T_5096 ? _Queue2_UInt8_23_io_deq_valid : _T_5095 ? _Queue2_UInt8_22_io_deq_valid : _T_5094 ? _Queue2_UInt8_21_io_deq_valid : _T_5093 ? _Queue2_UInt8_20_io_deq_valid : _T_5092 ? _Queue2_UInt8_19_io_deq_valid : _T_5091 ? _Queue2_UInt8_18_io_deq_valid : _T_5090 ? _Queue2_UInt8_17_io_deq_valid : _T_5089 ? _Queue2_UInt8_16_io_deq_valid : _T_5088 ? _Queue2_UInt8_15_io_deq_valid : _T_5087 ? _Queue2_UInt8_14_io_deq_valid : _T_5086 ? _Queue2_UInt8_13_io_deq_valid : _T_5085 ? _Queue2_UInt8_12_io_deq_valid : _T_5084 ? _Queue2_UInt8_11_io_deq_valid : _T_5083 ? _Queue2_UInt8_10_io_deq_valid : _T_5082 ? _Queue2_UInt8_9_io_deq_valid : _T_5081 ? _Queue2_UInt8_8_io_deq_valid : _T_5080 ? _Queue2_UInt8_7_io_deq_valid : _T_5079 ? _Queue2_UInt8_6_io_deq_valid : _T_5078 ? _Queue2_UInt8_5_io_deq_valid : _T_5077 ? _Queue2_UInt8_4_io_deq_valid : _T_5076 ? _Queue2_UInt8_3_io_deq_valid : _T_5075 ? _Queue2_UInt8_2_io_deq_valid : _T_5074 ? _Queue2_UInt8_1_io_deq_valid : _T_5073 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_114 = _remapindex_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_24 = _GEN_114[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5105 = remapindex_24 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5106 = remapindex_24 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5107 = remapindex_24 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5108 = remapindex_24 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5109 = remapindex_24 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5110 = remapindex_24 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5111 = remapindex_24 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5112 = remapindex_24 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5113 = remapindex_24 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5114 = remapindex_24 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5115 = remapindex_24 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5116 = remapindex_24 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5117 = remapindex_24 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5118 = remapindex_24 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5119 = remapindex_24 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5120 = remapindex_24 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5121 = remapindex_24 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5122 = remapindex_24 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5123 = remapindex_24 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5124 = remapindex_24 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5125 = remapindex_24 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5126 = remapindex_24 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5127 = remapindex_24 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5128 = remapindex_24 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5129 = remapindex_24 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5130 = remapindex_24 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5131 = remapindex_24 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5132 = remapindex_24 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5133 = remapindex_24 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5134 = remapindex_24 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5135 = remapindex_24 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5136 = remapindex_24 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_24 = _T_5136 ? _Queue2_UInt8_31_io_deq_bits : _T_5135 ? _Queue2_UInt8_30_io_deq_bits : _T_5134 ? _Queue2_UInt8_29_io_deq_bits : _T_5133 ? _Queue2_UInt8_28_io_deq_bits : _T_5132 ? _Queue2_UInt8_27_io_deq_bits : _T_5131 ? _Queue2_UInt8_26_io_deq_bits : _T_5130 ? _Queue2_UInt8_25_io_deq_bits : _T_5129 ? _Queue2_UInt8_24_io_deq_bits : _T_5128 ? _Queue2_UInt8_23_io_deq_bits : _T_5127 ? _Queue2_UInt8_22_io_deq_bits : _T_5126 ? _Queue2_UInt8_21_io_deq_bits : _T_5125 ? _Queue2_UInt8_20_io_deq_bits : _T_5124 ? _Queue2_UInt8_19_io_deq_bits : _T_5123 ? _Queue2_UInt8_18_io_deq_bits : _T_5122 ? _Queue2_UInt8_17_io_deq_bits : _T_5121 ? _Queue2_UInt8_16_io_deq_bits : _T_5120 ? _Queue2_UInt8_15_io_deq_bits : _T_5119 ? _Queue2_UInt8_14_io_deq_bits : _T_5118 ? _Queue2_UInt8_13_io_deq_bits : _T_5117 ? _Queue2_UInt8_12_io_deq_bits : _T_5116 ? _Queue2_UInt8_11_io_deq_bits : _T_5115 ? _Queue2_UInt8_10_io_deq_bits : _T_5114 ? _Queue2_UInt8_9_io_deq_bits : _T_5113 ? _Queue2_UInt8_8_io_deq_bits : _T_5112 ? _Queue2_UInt8_7_io_deq_bits : _T_5111 ? _Queue2_UInt8_6_io_deq_bits : _T_5110 ? _Queue2_UInt8_5_io_deq_bits : _T_5109 ? _Queue2_UInt8_4_io_deq_bits : _T_5108 ? _Queue2_UInt8_3_io_deq_bits : _T_5107 ? _Queue2_UInt8_2_io_deq_bits : _T_5106 ? _Queue2_UInt8_1_io_deq_bits : _T_5105 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_24 = _T_5136 ? _Queue2_UInt8_31_io_deq_valid : _T_5135 ? _Queue2_UInt8_30_io_deq_valid : _T_5134 ? _Queue2_UInt8_29_io_deq_valid : _T_5133 ? _Queue2_UInt8_28_io_deq_valid : _T_5132 ? _Queue2_UInt8_27_io_deq_valid : _T_5131 ? _Queue2_UInt8_26_io_deq_valid : _T_5130 ? _Queue2_UInt8_25_io_deq_valid : _T_5129 ? _Queue2_UInt8_24_io_deq_valid : _T_5128 ? _Queue2_UInt8_23_io_deq_valid : _T_5127 ? _Queue2_UInt8_22_io_deq_valid : _T_5126 ? _Queue2_UInt8_21_io_deq_valid : _T_5125 ? _Queue2_UInt8_20_io_deq_valid : _T_5124 ? _Queue2_UInt8_19_io_deq_valid : _T_5123 ? _Queue2_UInt8_18_io_deq_valid : _T_5122 ? _Queue2_UInt8_17_io_deq_valid : _T_5121 ? _Queue2_UInt8_16_io_deq_valid : _T_5120 ? _Queue2_UInt8_15_io_deq_valid : _T_5119 ? _Queue2_UInt8_14_io_deq_valid : _T_5118 ? _Queue2_UInt8_13_io_deq_valid : _T_5117 ? _Queue2_UInt8_12_io_deq_valid : _T_5116 ? _Queue2_UInt8_11_io_deq_valid : _T_5115 ? _Queue2_UInt8_10_io_deq_valid : _T_5114 ? _Queue2_UInt8_9_io_deq_valid : _T_5113 ? _Queue2_UInt8_8_io_deq_valid : _T_5112 ? _Queue2_UInt8_7_io_deq_valid : _T_5111 ? _Queue2_UInt8_6_io_deq_valid : _T_5110 ? _Queue2_UInt8_5_io_deq_valid : _T_5109 ? _Queue2_UInt8_4_io_deq_valid : _T_5108 ? _Queue2_UInt8_3_io_deq_valid : _T_5107 ? _Queue2_UInt8_2_io_deq_valid : _T_5106 ? _Queue2_UInt8_1_io_deq_valid : _T_5105 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_115 = _remapindex_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_25 = _GEN_115[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5137 = remapindex_25 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5138 = remapindex_25 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5139 = remapindex_25 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5140 = remapindex_25 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5141 = remapindex_25 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5142 = remapindex_25 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5143 = remapindex_25 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5144 = remapindex_25 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5145 = remapindex_25 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5146 = remapindex_25 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5147 = remapindex_25 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5148 = remapindex_25 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5149 = remapindex_25 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5150 = remapindex_25 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5151 = remapindex_25 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5152 = remapindex_25 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5153 = remapindex_25 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5154 = remapindex_25 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5155 = remapindex_25 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5156 = remapindex_25 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5157 = remapindex_25 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5158 = remapindex_25 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5159 = remapindex_25 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5160 = remapindex_25 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5161 = remapindex_25 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5162 = remapindex_25 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5163 = remapindex_25 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5164 = remapindex_25 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5165 = remapindex_25 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5166 = remapindex_25 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5167 = remapindex_25 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5168 = remapindex_25 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_25 = _T_5168 ? _Queue2_UInt8_31_io_deq_bits : _T_5167 ? _Queue2_UInt8_30_io_deq_bits : _T_5166 ? _Queue2_UInt8_29_io_deq_bits : _T_5165 ? _Queue2_UInt8_28_io_deq_bits : _T_5164 ? _Queue2_UInt8_27_io_deq_bits : _T_5163 ? _Queue2_UInt8_26_io_deq_bits : _T_5162 ? _Queue2_UInt8_25_io_deq_bits : _T_5161 ? _Queue2_UInt8_24_io_deq_bits : _T_5160 ? _Queue2_UInt8_23_io_deq_bits : _T_5159 ? _Queue2_UInt8_22_io_deq_bits : _T_5158 ? _Queue2_UInt8_21_io_deq_bits : _T_5157 ? _Queue2_UInt8_20_io_deq_bits : _T_5156 ? _Queue2_UInt8_19_io_deq_bits : _T_5155 ? _Queue2_UInt8_18_io_deq_bits : _T_5154 ? _Queue2_UInt8_17_io_deq_bits : _T_5153 ? _Queue2_UInt8_16_io_deq_bits : _T_5152 ? _Queue2_UInt8_15_io_deq_bits : _T_5151 ? _Queue2_UInt8_14_io_deq_bits : _T_5150 ? _Queue2_UInt8_13_io_deq_bits : _T_5149 ? _Queue2_UInt8_12_io_deq_bits : _T_5148 ? _Queue2_UInt8_11_io_deq_bits : _T_5147 ? _Queue2_UInt8_10_io_deq_bits : _T_5146 ? _Queue2_UInt8_9_io_deq_bits : _T_5145 ? _Queue2_UInt8_8_io_deq_bits : _T_5144 ? _Queue2_UInt8_7_io_deq_bits : _T_5143 ? _Queue2_UInt8_6_io_deq_bits : _T_5142 ? _Queue2_UInt8_5_io_deq_bits : _T_5141 ? _Queue2_UInt8_4_io_deq_bits : _T_5140 ? _Queue2_UInt8_3_io_deq_bits : _T_5139 ? _Queue2_UInt8_2_io_deq_bits : _T_5138 ? _Queue2_UInt8_1_io_deq_bits : _T_5137 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_25 = _T_5168 ? _Queue2_UInt8_31_io_deq_valid : _T_5167 ? _Queue2_UInt8_30_io_deq_valid : _T_5166 ? _Queue2_UInt8_29_io_deq_valid : _T_5165 ? _Queue2_UInt8_28_io_deq_valid : _T_5164 ? _Queue2_UInt8_27_io_deq_valid : _T_5163 ? _Queue2_UInt8_26_io_deq_valid : _T_5162 ? _Queue2_UInt8_25_io_deq_valid : _T_5161 ? _Queue2_UInt8_24_io_deq_valid : _T_5160 ? _Queue2_UInt8_23_io_deq_valid : _T_5159 ? _Queue2_UInt8_22_io_deq_valid : _T_5158 ? _Queue2_UInt8_21_io_deq_valid : _T_5157 ? _Queue2_UInt8_20_io_deq_valid : _T_5156 ? _Queue2_UInt8_19_io_deq_valid : _T_5155 ? _Queue2_UInt8_18_io_deq_valid : _T_5154 ? _Queue2_UInt8_17_io_deq_valid : _T_5153 ? _Queue2_UInt8_16_io_deq_valid : _T_5152 ? _Queue2_UInt8_15_io_deq_valid : _T_5151 ? _Queue2_UInt8_14_io_deq_valid : _T_5150 ? _Queue2_UInt8_13_io_deq_valid : _T_5149 ? _Queue2_UInt8_12_io_deq_valid : _T_5148 ? _Queue2_UInt8_11_io_deq_valid : _T_5147 ? _Queue2_UInt8_10_io_deq_valid : _T_5146 ? _Queue2_UInt8_9_io_deq_valid : _T_5145 ? _Queue2_UInt8_8_io_deq_valid : _T_5144 ? _Queue2_UInt8_7_io_deq_valid : _T_5143 ? _Queue2_UInt8_6_io_deq_valid : _T_5142 ? _Queue2_UInt8_5_io_deq_valid : _T_5141 ? _Queue2_UInt8_4_io_deq_valid : _T_5140 ? _Queue2_UInt8_3_io_deq_valid : _T_5139 ? _Queue2_UInt8_2_io_deq_valid : _T_5138 ? _Queue2_UInt8_1_io_deq_valid : _T_5137 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_116 = _remapindex_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_26 = _GEN_116[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5169 = remapindex_26 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5170 = remapindex_26 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5171 = remapindex_26 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5172 = remapindex_26 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5173 = remapindex_26 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5174 = remapindex_26 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5175 = remapindex_26 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5176 = remapindex_26 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5177 = remapindex_26 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5178 = remapindex_26 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5179 = remapindex_26 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5180 = remapindex_26 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5181 = remapindex_26 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5182 = remapindex_26 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5183 = remapindex_26 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5184 = remapindex_26 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5185 = remapindex_26 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5186 = remapindex_26 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5187 = remapindex_26 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5188 = remapindex_26 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5189 = remapindex_26 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5190 = remapindex_26 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5191 = remapindex_26 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5192 = remapindex_26 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5193 = remapindex_26 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5194 = remapindex_26 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5195 = remapindex_26 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5196 = remapindex_26 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5197 = remapindex_26 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5198 = remapindex_26 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5199 = remapindex_26 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5200 = remapindex_26 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_26 = _T_5200 ? _Queue2_UInt8_31_io_deq_bits : _T_5199 ? _Queue2_UInt8_30_io_deq_bits : _T_5198 ? _Queue2_UInt8_29_io_deq_bits : _T_5197 ? _Queue2_UInt8_28_io_deq_bits : _T_5196 ? _Queue2_UInt8_27_io_deq_bits : _T_5195 ? _Queue2_UInt8_26_io_deq_bits : _T_5194 ? _Queue2_UInt8_25_io_deq_bits : _T_5193 ? _Queue2_UInt8_24_io_deq_bits : _T_5192 ? _Queue2_UInt8_23_io_deq_bits : _T_5191 ? _Queue2_UInt8_22_io_deq_bits : _T_5190 ? _Queue2_UInt8_21_io_deq_bits : _T_5189 ? _Queue2_UInt8_20_io_deq_bits : _T_5188 ? _Queue2_UInt8_19_io_deq_bits : _T_5187 ? _Queue2_UInt8_18_io_deq_bits : _T_5186 ? _Queue2_UInt8_17_io_deq_bits : _T_5185 ? _Queue2_UInt8_16_io_deq_bits : _T_5184 ? _Queue2_UInt8_15_io_deq_bits : _T_5183 ? _Queue2_UInt8_14_io_deq_bits : _T_5182 ? _Queue2_UInt8_13_io_deq_bits : _T_5181 ? _Queue2_UInt8_12_io_deq_bits : _T_5180 ? _Queue2_UInt8_11_io_deq_bits : _T_5179 ? _Queue2_UInt8_10_io_deq_bits : _T_5178 ? _Queue2_UInt8_9_io_deq_bits : _T_5177 ? _Queue2_UInt8_8_io_deq_bits : _T_5176 ? _Queue2_UInt8_7_io_deq_bits : _T_5175 ? _Queue2_UInt8_6_io_deq_bits : _T_5174 ? _Queue2_UInt8_5_io_deq_bits : _T_5173 ? _Queue2_UInt8_4_io_deq_bits : _T_5172 ? _Queue2_UInt8_3_io_deq_bits : _T_5171 ? _Queue2_UInt8_2_io_deq_bits : _T_5170 ? _Queue2_UInt8_1_io_deq_bits : _T_5169 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_26 = _T_5200 ? _Queue2_UInt8_31_io_deq_valid : _T_5199 ? _Queue2_UInt8_30_io_deq_valid : _T_5198 ? _Queue2_UInt8_29_io_deq_valid : _T_5197 ? _Queue2_UInt8_28_io_deq_valid : _T_5196 ? _Queue2_UInt8_27_io_deq_valid : _T_5195 ? _Queue2_UInt8_26_io_deq_valid : _T_5194 ? _Queue2_UInt8_25_io_deq_valid : _T_5193 ? _Queue2_UInt8_24_io_deq_valid : _T_5192 ? _Queue2_UInt8_23_io_deq_valid : _T_5191 ? _Queue2_UInt8_22_io_deq_valid : _T_5190 ? _Queue2_UInt8_21_io_deq_valid : _T_5189 ? _Queue2_UInt8_20_io_deq_valid : _T_5188 ? _Queue2_UInt8_19_io_deq_valid : _T_5187 ? _Queue2_UInt8_18_io_deq_valid : _T_5186 ? _Queue2_UInt8_17_io_deq_valid : _T_5185 ? _Queue2_UInt8_16_io_deq_valid : _T_5184 ? _Queue2_UInt8_15_io_deq_valid : _T_5183 ? _Queue2_UInt8_14_io_deq_valid : _T_5182 ? _Queue2_UInt8_13_io_deq_valid : _T_5181 ? _Queue2_UInt8_12_io_deq_valid : _T_5180 ? _Queue2_UInt8_11_io_deq_valid : _T_5179 ? _Queue2_UInt8_10_io_deq_valid : _T_5178 ? _Queue2_UInt8_9_io_deq_valid : _T_5177 ? _Queue2_UInt8_8_io_deq_valid : _T_5176 ? _Queue2_UInt8_7_io_deq_valid : _T_5175 ? _Queue2_UInt8_6_io_deq_valid : _T_5174 ? _Queue2_UInt8_5_io_deq_valid : _T_5173 ? _Queue2_UInt8_4_io_deq_valid : _T_5172 ? _Queue2_UInt8_3_io_deq_valid : _T_5171 ? _Queue2_UInt8_2_io_deq_valid : _T_5170 ? _Queue2_UInt8_1_io_deq_valid : _T_5169 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_117 = _remapindex_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_27 = _GEN_117[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5201 = remapindex_27 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5202 = remapindex_27 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5203 = remapindex_27 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5204 = remapindex_27 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5205 = remapindex_27 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5206 = remapindex_27 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5207 = remapindex_27 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5208 = remapindex_27 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5209 = remapindex_27 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5210 = remapindex_27 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5211 = remapindex_27 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5212 = remapindex_27 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5213 = remapindex_27 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5214 = remapindex_27 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5215 = remapindex_27 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5216 = remapindex_27 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5217 = remapindex_27 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5218 = remapindex_27 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5219 = remapindex_27 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5220 = remapindex_27 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5221 = remapindex_27 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5222 = remapindex_27 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5223 = remapindex_27 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5224 = remapindex_27 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5225 = remapindex_27 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5226 = remapindex_27 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5227 = remapindex_27 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5228 = remapindex_27 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5229 = remapindex_27 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5230 = remapindex_27 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5231 = remapindex_27 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5232 = remapindex_27 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_27 = _T_5232 ? _Queue2_UInt8_31_io_deq_bits : _T_5231 ? _Queue2_UInt8_30_io_deq_bits : _T_5230 ? _Queue2_UInt8_29_io_deq_bits : _T_5229 ? _Queue2_UInt8_28_io_deq_bits : _T_5228 ? _Queue2_UInt8_27_io_deq_bits : _T_5227 ? _Queue2_UInt8_26_io_deq_bits : _T_5226 ? _Queue2_UInt8_25_io_deq_bits : _T_5225 ? _Queue2_UInt8_24_io_deq_bits : _T_5224 ? _Queue2_UInt8_23_io_deq_bits : _T_5223 ? _Queue2_UInt8_22_io_deq_bits : _T_5222 ? _Queue2_UInt8_21_io_deq_bits : _T_5221 ? _Queue2_UInt8_20_io_deq_bits : _T_5220 ? _Queue2_UInt8_19_io_deq_bits : _T_5219 ? _Queue2_UInt8_18_io_deq_bits : _T_5218 ? _Queue2_UInt8_17_io_deq_bits : _T_5217 ? _Queue2_UInt8_16_io_deq_bits : _T_5216 ? _Queue2_UInt8_15_io_deq_bits : _T_5215 ? _Queue2_UInt8_14_io_deq_bits : _T_5214 ? _Queue2_UInt8_13_io_deq_bits : _T_5213 ? _Queue2_UInt8_12_io_deq_bits : _T_5212 ? _Queue2_UInt8_11_io_deq_bits : _T_5211 ? _Queue2_UInt8_10_io_deq_bits : _T_5210 ? _Queue2_UInt8_9_io_deq_bits : _T_5209 ? _Queue2_UInt8_8_io_deq_bits : _T_5208 ? _Queue2_UInt8_7_io_deq_bits : _T_5207 ? _Queue2_UInt8_6_io_deq_bits : _T_5206 ? _Queue2_UInt8_5_io_deq_bits : _T_5205 ? _Queue2_UInt8_4_io_deq_bits : _T_5204 ? _Queue2_UInt8_3_io_deq_bits : _T_5203 ? _Queue2_UInt8_2_io_deq_bits : _T_5202 ? _Queue2_UInt8_1_io_deq_bits : _T_5201 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_27 = _T_5232 ? _Queue2_UInt8_31_io_deq_valid : _T_5231 ? _Queue2_UInt8_30_io_deq_valid : _T_5230 ? _Queue2_UInt8_29_io_deq_valid : _T_5229 ? _Queue2_UInt8_28_io_deq_valid : _T_5228 ? _Queue2_UInt8_27_io_deq_valid : _T_5227 ? _Queue2_UInt8_26_io_deq_valid : _T_5226 ? _Queue2_UInt8_25_io_deq_valid : _T_5225 ? _Queue2_UInt8_24_io_deq_valid : _T_5224 ? _Queue2_UInt8_23_io_deq_valid : _T_5223 ? _Queue2_UInt8_22_io_deq_valid : _T_5222 ? _Queue2_UInt8_21_io_deq_valid : _T_5221 ? _Queue2_UInt8_20_io_deq_valid : _T_5220 ? _Queue2_UInt8_19_io_deq_valid : _T_5219 ? _Queue2_UInt8_18_io_deq_valid : _T_5218 ? _Queue2_UInt8_17_io_deq_valid : _T_5217 ? _Queue2_UInt8_16_io_deq_valid : _T_5216 ? _Queue2_UInt8_15_io_deq_valid : _T_5215 ? _Queue2_UInt8_14_io_deq_valid : _T_5214 ? _Queue2_UInt8_13_io_deq_valid : _T_5213 ? _Queue2_UInt8_12_io_deq_valid : _T_5212 ? _Queue2_UInt8_11_io_deq_valid : _T_5211 ? _Queue2_UInt8_10_io_deq_valid : _T_5210 ? _Queue2_UInt8_9_io_deq_valid : _T_5209 ? _Queue2_UInt8_8_io_deq_valid : _T_5208 ? _Queue2_UInt8_7_io_deq_valid : _T_5207 ? _Queue2_UInt8_6_io_deq_valid : _T_5206 ? _Queue2_UInt8_5_io_deq_valid : _T_5205 ? _Queue2_UInt8_4_io_deq_valid : _T_5204 ? _Queue2_UInt8_3_io_deq_valid : _T_5203 ? _Queue2_UInt8_2_io_deq_valid : _T_5202 ? _Queue2_UInt8_1_io_deq_valid : _T_5201 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_118 = _remapindex_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_28 = _GEN_118[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5233 = remapindex_28 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5234 = remapindex_28 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5235 = remapindex_28 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5236 = remapindex_28 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5237 = remapindex_28 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5238 = remapindex_28 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5239 = remapindex_28 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5240 = remapindex_28 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5241 = remapindex_28 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5242 = remapindex_28 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5243 = remapindex_28 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5244 = remapindex_28 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5245 = remapindex_28 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5246 = remapindex_28 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5247 = remapindex_28 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5248 = remapindex_28 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5249 = remapindex_28 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5250 = remapindex_28 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5251 = remapindex_28 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5252 = remapindex_28 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5253 = remapindex_28 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5254 = remapindex_28 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5255 = remapindex_28 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5256 = remapindex_28 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5257 = remapindex_28 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5258 = remapindex_28 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5259 = remapindex_28 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5260 = remapindex_28 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5261 = remapindex_28 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5262 = remapindex_28 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5263 = remapindex_28 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5264 = remapindex_28 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_28 = _T_5264 ? _Queue2_UInt8_31_io_deq_bits : _T_5263 ? _Queue2_UInt8_30_io_deq_bits : _T_5262 ? _Queue2_UInt8_29_io_deq_bits : _T_5261 ? _Queue2_UInt8_28_io_deq_bits : _T_5260 ? _Queue2_UInt8_27_io_deq_bits : _T_5259 ? _Queue2_UInt8_26_io_deq_bits : _T_5258 ? _Queue2_UInt8_25_io_deq_bits : _T_5257 ? _Queue2_UInt8_24_io_deq_bits : _T_5256 ? _Queue2_UInt8_23_io_deq_bits : _T_5255 ? _Queue2_UInt8_22_io_deq_bits : _T_5254 ? _Queue2_UInt8_21_io_deq_bits : _T_5253 ? _Queue2_UInt8_20_io_deq_bits : _T_5252 ? _Queue2_UInt8_19_io_deq_bits : _T_5251 ? _Queue2_UInt8_18_io_deq_bits : _T_5250 ? _Queue2_UInt8_17_io_deq_bits : _T_5249 ? _Queue2_UInt8_16_io_deq_bits : _T_5248 ? _Queue2_UInt8_15_io_deq_bits : _T_5247 ? _Queue2_UInt8_14_io_deq_bits : _T_5246 ? _Queue2_UInt8_13_io_deq_bits : _T_5245 ? _Queue2_UInt8_12_io_deq_bits : _T_5244 ? _Queue2_UInt8_11_io_deq_bits : _T_5243 ? _Queue2_UInt8_10_io_deq_bits : _T_5242 ? _Queue2_UInt8_9_io_deq_bits : _T_5241 ? _Queue2_UInt8_8_io_deq_bits : _T_5240 ? _Queue2_UInt8_7_io_deq_bits : _T_5239 ? _Queue2_UInt8_6_io_deq_bits : _T_5238 ? _Queue2_UInt8_5_io_deq_bits : _T_5237 ? _Queue2_UInt8_4_io_deq_bits : _T_5236 ? _Queue2_UInt8_3_io_deq_bits : _T_5235 ? _Queue2_UInt8_2_io_deq_bits : _T_5234 ? _Queue2_UInt8_1_io_deq_bits : _T_5233 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_28 = _T_5264 ? _Queue2_UInt8_31_io_deq_valid : _T_5263 ? _Queue2_UInt8_30_io_deq_valid : _T_5262 ? _Queue2_UInt8_29_io_deq_valid : _T_5261 ? _Queue2_UInt8_28_io_deq_valid : _T_5260 ? _Queue2_UInt8_27_io_deq_valid : _T_5259 ? _Queue2_UInt8_26_io_deq_valid : _T_5258 ? _Queue2_UInt8_25_io_deq_valid : _T_5257 ? _Queue2_UInt8_24_io_deq_valid : _T_5256 ? _Queue2_UInt8_23_io_deq_valid : _T_5255 ? _Queue2_UInt8_22_io_deq_valid : _T_5254 ? _Queue2_UInt8_21_io_deq_valid : _T_5253 ? _Queue2_UInt8_20_io_deq_valid : _T_5252 ? _Queue2_UInt8_19_io_deq_valid : _T_5251 ? _Queue2_UInt8_18_io_deq_valid : _T_5250 ? _Queue2_UInt8_17_io_deq_valid : _T_5249 ? _Queue2_UInt8_16_io_deq_valid : _T_5248 ? _Queue2_UInt8_15_io_deq_valid : _T_5247 ? _Queue2_UInt8_14_io_deq_valid : _T_5246 ? _Queue2_UInt8_13_io_deq_valid : _T_5245 ? _Queue2_UInt8_12_io_deq_valid : _T_5244 ? _Queue2_UInt8_11_io_deq_valid : _T_5243 ? _Queue2_UInt8_10_io_deq_valid : _T_5242 ? _Queue2_UInt8_9_io_deq_valid : _T_5241 ? _Queue2_UInt8_8_io_deq_valid : _T_5240 ? _Queue2_UInt8_7_io_deq_valid : _T_5239 ? _Queue2_UInt8_6_io_deq_valid : _T_5238 ? _Queue2_UInt8_5_io_deq_valid : _T_5237 ? _Queue2_UInt8_4_io_deq_valid : _T_5236 ? _Queue2_UInt8_3_io_deq_valid : _T_5235 ? _Queue2_UInt8_2_io_deq_valid : _T_5234 ? _Queue2_UInt8_1_io_deq_valid : _T_5233 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_119 = _remapindex_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_29 = _GEN_119[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5265 = remapindex_29 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5266 = remapindex_29 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5267 = remapindex_29 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5268 = remapindex_29 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5269 = remapindex_29 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5270 = remapindex_29 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5271 = remapindex_29 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5272 = remapindex_29 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5273 = remapindex_29 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5274 = remapindex_29 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5275 = remapindex_29 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5276 = remapindex_29 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5277 = remapindex_29 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5278 = remapindex_29 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5279 = remapindex_29 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5280 = remapindex_29 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5281 = remapindex_29 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5282 = remapindex_29 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5283 = remapindex_29 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5284 = remapindex_29 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5285 = remapindex_29 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5286 = remapindex_29 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5287 = remapindex_29 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5288 = remapindex_29 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5289 = remapindex_29 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5290 = remapindex_29 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5291 = remapindex_29 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5292 = remapindex_29 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5293 = remapindex_29 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5294 = remapindex_29 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5295 = remapindex_29 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5296 = remapindex_29 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_29 = _T_5296 ? _Queue2_UInt8_31_io_deq_bits : _T_5295 ? _Queue2_UInt8_30_io_deq_bits : _T_5294 ? _Queue2_UInt8_29_io_deq_bits : _T_5293 ? _Queue2_UInt8_28_io_deq_bits : _T_5292 ? _Queue2_UInt8_27_io_deq_bits : _T_5291 ? _Queue2_UInt8_26_io_deq_bits : _T_5290 ? _Queue2_UInt8_25_io_deq_bits : _T_5289 ? _Queue2_UInt8_24_io_deq_bits : _T_5288 ? _Queue2_UInt8_23_io_deq_bits : _T_5287 ? _Queue2_UInt8_22_io_deq_bits : _T_5286 ? _Queue2_UInt8_21_io_deq_bits : _T_5285 ? _Queue2_UInt8_20_io_deq_bits : _T_5284 ? _Queue2_UInt8_19_io_deq_bits : _T_5283 ? _Queue2_UInt8_18_io_deq_bits : _T_5282 ? _Queue2_UInt8_17_io_deq_bits : _T_5281 ? _Queue2_UInt8_16_io_deq_bits : _T_5280 ? _Queue2_UInt8_15_io_deq_bits : _T_5279 ? _Queue2_UInt8_14_io_deq_bits : _T_5278 ? _Queue2_UInt8_13_io_deq_bits : _T_5277 ? _Queue2_UInt8_12_io_deq_bits : _T_5276 ? _Queue2_UInt8_11_io_deq_bits : _T_5275 ? _Queue2_UInt8_10_io_deq_bits : _T_5274 ? _Queue2_UInt8_9_io_deq_bits : _T_5273 ? _Queue2_UInt8_8_io_deq_bits : _T_5272 ? _Queue2_UInt8_7_io_deq_bits : _T_5271 ? _Queue2_UInt8_6_io_deq_bits : _T_5270 ? _Queue2_UInt8_5_io_deq_bits : _T_5269 ? _Queue2_UInt8_4_io_deq_bits : _T_5268 ? _Queue2_UInt8_3_io_deq_bits : _T_5267 ? _Queue2_UInt8_2_io_deq_bits : _T_5266 ? _Queue2_UInt8_1_io_deq_bits : _T_5265 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_29 = _T_5296 ? _Queue2_UInt8_31_io_deq_valid : _T_5295 ? _Queue2_UInt8_30_io_deq_valid : _T_5294 ? _Queue2_UInt8_29_io_deq_valid : _T_5293 ? _Queue2_UInt8_28_io_deq_valid : _T_5292 ? _Queue2_UInt8_27_io_deq_valid : _T_5291 ? _Queue2_UInt8_26_io_deq_valid : _T_5290 ? _Queue2_UInt8_25_io_deq_valid : _T_5289 ? _Queue2_UInt8_24_io_deq_valid : _T_5288 ? _Queue2_UInt8_23_io_deq_valid : _T_5287 ? _Queue2_UInt8_22_io_deq_valid : _T_5286 ? _Queue2_UInt8_21_io_deq_valid : _T_5285 ? _Queue2_UInt8_20_io_deq_valid : _T_5284 ? _Queue2_UInt8_19_io_deq_valid : _T_5283 ? _Queue2_UInt8_18_io_deq_valid : _T_5282 ? _Queue2_UInt8_17_io_deq_valid : _T_5281 ? _Queue2_UInt8_16_io_deq_valid : _T_5280 ? _Queue2_UInt8_15_io_deq_valid : _T_5279 ? _Queue2_UInt8_14_io_deq_valid : _T_5278 ? _Queue2_UInt8_13_io_deq_valid : _T_5277 ? _Queue2_UInt8_12_io_deq_valid : _T_5276 ? _Queue2_UInt8_11_io_deq_valid : _T_5275 ? _Queue2_UInt8_10_io_deq_valid : _T_5274 ? _Queue2_UInt8_9_io_deq_valid : _T_5273 ? _Queue2_UInt8_8_io_deq_valid : _T_5272 ? _Queue2_UInt8_7_io_deq_valid : _T_5271 ? _Queue2_UInt8_6_io_deq_valid : _T_5270 ? _Queue2_UInt8_5_io_deq_valid : _T_5269 ? _Queue2_UInt8_4_io_deq_valid : _T_5268 ? _Queue2_UInt8_3_io_deq_valid : _T_5267 ? _Queue2_UInt8_2_io_deq_valid : _T_5266 ? _Queue2_UInt8_1_io_deq_valid : _T_5265 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_120 = _remapindex_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_30 = _GEN_120[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5297 = remapindex_30 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5298 = remapindex_30 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5299 = remapindex_30 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5300 = remapindex_30 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5301 = remapindex_30 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5302 = remapindex_30 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5303 = remapindex_30 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5304 = remapindex_30 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5305 = remapindex_30 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5306 = remapindex_30 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5307 = remapindex_30 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5308 = remapindex_30 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5309 = remapindex_30 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5310 = remapindex_30 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5311 = remapindex_30 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5312 = remapindex_30 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5313 = remapindex_30 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5314 = remapindex_30 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5315 = remapindex_30 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5316 = remapindex_30 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5317 = remapindex_30 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5318 = remapindex_30 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5319 = remapindex_30 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5320 = remapindex_30 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5321 = remapindex_30 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5322 = remapindex_30 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5323 = remapindex_30 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5324 = remapindex_30 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5325 = remapindex_30 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5326 = remapindex_30 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5327 = remapindex_30 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5328 = remapindex_30 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_30 = _T_5328 ? _Queue2_UInt8_31_io_deq_bits : _T_5327 ? _Queue2_UInt8_30_io_deq_bits : _T_5326 ? _Queue2_UInt8_29_io_deq_bits : _T_5325 ? _Queue2_UInt8_28_io_deq_bits : _T_5324 ? _Queue2_UInt8_27_io_deq_bits : _T_5323 ? _Queue2_UInt8_26_io_deq_bits : _T_5322 ? _Queue2_UInt8_25_io_deq_bits : _T_5321 ? _Queue2_UInt8_24_io_deq_bits : _T_5320 ? _Queue2_UInt8_23_io_deq_bits : _T_5319 ? _Queue2_UInt8_22_io_deq_bits : _T_5318 ? _Queue2_UInt8_21_io_deq_bits : _T_5317 ? _Queue2_UInt8_20_io_deq_bits : _T_5316 ? _Queue2_UInt8_19_io_deq_bits : _T_5315 ? _Queue2_UInt8_18_io_deq_bits : _T_5314 ? _Queue2_UInt8_17_io_deq_bits : _T_5313 ? _Queue2_UInt8_16_io_deq_bits : _T_5312 ? _Queue2_UInt8_15_io_deq_bits : _T_5311 ? _Queue2_UInt8_14_io_deq_bits : _T_5310 ? _Queue2_UInt8_13_io_deq_bits : _T_5309 ? _Queue2_UInt8_12_io_deq_bits : _T_5308 ? _Queue2_UInt8_11_io_deq_bits : _T_5307 ? _Queue2_UInt8_10_io_deq_bits : _T_5306 ? _Queue2_UInt8_9_io_deq_bits : _T_5305 ? _Queue2_UInt8_8_io_deq_bits : _T_5304 ? _Queue2_UInt8_7_io_deq_bits : _T_5303 ? _Queue2_UInt8_6_io_deq_bits : _T_5302 ? _Queue2_UInt8_5_io_deq_bits : _T_5301 ? _Queue2_UInt8_4_io_deq_bits : _T_5300 ? _Queue2_UInt8_3_io_deq_bits : _T_5299 ? _Queue2_UInt8_2_io_deq_bits : _T_5298 ? _Queue2_UInt8_1_io_deq_bits : _T_5297 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_30 = _T_5328 ? _Queue2_UInt8_31_io_deq_valid : _T_5327 ? _Queue2_UInt8_30_io_deq_valid : _T_5326 ? _Queue2_UInt8_29_io_deq_valid : _T_5325 ? _Queue2_UInt8_28_io_deq_valid : _T_5324 ? _Queue2_UInt8_27_io_deq_valid : _T_5323 ? _Queue2_UInt8_26_io_deq_valid : _T_5322 ? _Queue2_UInt8_25_io_deq_valid : _T_5321 ? _Queue2_UInt8_24_io_deq_valid : _T_5320 ? _Queue2_UInt8_23_io_deq_valid : _T_5319 ? _Queue2_UInt8_22_io_deq_valid : _T_5318 ? _Queue2_UInt8_21_io_deq_valid : _T_5317 ? _Queue2_UInt8_20_io_deq_valid : _T_5316 ? _Queue2_UInt8_19_io_deq_valid : _T_5315 ? _Queue2_UInt8_18_io_deq_valid : _T_5314 ? _Queue2_UInt8_17_io_deq_valid : _T_5313 ? _Queue2_UInt8_16_io_deq_valid : _T_5312 ? _Queue2_UInt8_15_io_deq_valid : _T_5311 ? _Queue2_UInt8_14_io_deq_valid : _T_5310 ? _Queue2_UInt8_13_io_deq_valid : _T_5309 ? _Queue2_UInt8_12_io_deq_valid : _T_5308 ? _Queue2_UInt8_11_io_deq_valid : _T_5307 ? _Queue2_UInt8_10_io_deq_valid : _T_5306 ? _Queue2_UInt8_9_io_deq_valid : _T_5305 ? _Queue2_UInt8_8_io_deq_valid : _T_5304 ? _Queue2_UInt8_7_io_deq_valid : _T_5303 ? _Queue2_UInt8_6_io_deq_valid : _T_5302 ? _Queue2_UInt8_5_io_deq_valid : _T_5301 ? _Queue2_UInt8_4_io_deq_valid : _T_5300 ? _Queue2_UInt8_3_io_deq_valid : _T_5299 ? _Queue2_UInt8_2_io_deq_valid : _T_5298 ? _Queue2_UInt8_1_io_deq_valid : _T_5297 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_121 = _remapindex_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_31 = _GEN_121[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5329 = remapindex_31 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5330 = remapindex_31 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5331 = remapindex_31 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5332 = remapindex_31 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5333 = remapindex_31 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5334 = remapindex_31 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5335 = remapindex_31 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5336 = remapindex_31 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5337 = remapindex_31 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5338 = remapindex_31 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5339 = remapindex_31 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5340 = remapindex_31 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5341 = remapindex_31 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5342 = remapindex_31 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5343 = remapindex_31 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5344 = remapindex_31 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5345 = remapindex_31 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5346 = remapindex_31 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5347 = remapindex_31 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5348 = remapindex_31 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5349 = remapindex_31 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5350 = remapindex_31 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5351 = remapindex_31 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5352 = remapindex_31 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5353 = remapindex_31 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5354 = remapindex_31 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5355 = remapindex_31 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5356 = remapindex_31 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5357 = remapindex_31 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5358 = remapindex_31 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5359 = remapindex_31 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5360 = remapindex_31 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_31 = _T_5360 ? _Queue2_UInt8_31_io_deq_bits : _T_5359 ? _Queue2_UInt8_30_io_deq_bits : _T_5358 ? _Queue2_UInt8_29_io_deq_bits : _T_5357 ? _Queue2_UInt8_28_io_deq_bits : _T_5356 ? _Queue2_UInt8_27_io_deq_bits : _T_5355 ? _Queue2_UInt8_26_io_deq_bits : _T_5354 ? _Queue2_UInt8_25_io_deq_bits : _T_5353 ? _Queue2_UInt8_24_io_deq_bits : _T_5352 ? _Queue2_UInt8_23_io_deq_bits : _T_5351 ? _Queue2_UInt8_22_io_deq_bits : _T_5350 ? _Queue2_UInt8_21_io_deq_bits : _T_5349 ? _Queue2_UInt8_20_io_deq_bits : _T_5348 ? _Queue2_UInt8_19_io_deq_bits : _T_5347 ? _Queue2_UInt8_18_io_deq_bits : _T_5346 ? _Queue2_UInt8_17_io_deq_bits : _T_5345 ? _Queue2_UInt8_16_io_deq_bits : _T_5344 ? _Queue2_UInt8_15_io_deq_bits : _T_5343 ? _Queue2_UInt8_14_io_deq_bits : _T_5342 ? _Queue2_UInt8_13_io_deq_bits : _T_5341 ? _Queue2_UInt8_12_io_deq_bits : _T_5340 ? _Queue2_UInt8_11_io_deq_bits : _T_5339 ? _Queue2_UInt8_10_io_deq_bits : _T_5338 ? _Queue2_UInt8_9_io_deq_bits : _T_5337 ? _Queue2_UInt8_8_io_deq_bits : _T_5336 ? _Queue2_UInt8_7_io_deq_bits : _T_5335 ? _Queue2_UInt8_6_io_deq_bits : _T_5334 ? _Queue2_UInt8_5_io_deq_bits : _T_5333 ? _Queue2_UInt8_4_io_deq_bits : _T_5332 ? _Queue2_UInt8_3_io_deq_bits : _T_5331 ? _Queue2_UInt8_2_io_deq_bits : _T_5330 ? _Queue2_UInt8_1_io_deq_bits : _T_5329 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_31 = _T_5360 ? _Queue2_UInt8_31_io_deq_valid : _T_5359 ? _Queue2_UInt8_30_io_deq_valid : _T_5358 ? _Queue2_UInt8_29_io_deq_valid : _T_5357 ? _Queue2_UInt8_28_io_deq_valid : _T_5356 ? _Queue2_UInt8_27_io_deq_valid : _T_5355 ? _Queue2_UInt8_26_io_deq_valid : _T_5354 ? _Queue2_UInt8_25_io_deq_valid : _T_5353 ? _Queue2_UInt8_24_io_deq_valid : _T_5352 ? _Queue2_UInt8_23_io_deq_valid : _T_5351 ? _Queue2_UInt8_22_io_deq_valid : _T_5350 ? _Queue2_UInt8_21_io_deq_valid : _T_5349 ? _Queue2_UInt8_20_io_deq_valid : _T_5348 ? _Queue2_UInt8_19_io_deq_valid : _T_5347 ? _Queue2_UInt8_18_io_deq_valid : _T_5346 ? _Queue2_UInt8_17_io_deq_valid : _T_5345 ? _Queue2_UInt8_16_io_deq_valid : _T_5344 ? _Queue2_UInt8_15_io_deq_valid : _T_5343 ? _Queue2_UInt8_14_io_deq_valid : _T_5342 ? _Queue2_UInt8_13_io_deq_valid : _T_5341 ? _Queue2_UInt8_12_io_deq_valid : _T_5340 ? _Queue2_UInt8_11_io_deq_valid : _T_5339 ? _Queue2_UInt8_10_io_deq_valid : _T_5338 ? _Queue2_UInt8_9_io_deq_valid : _T_5337 ? _Queue2_UInt8_8_io_deq_valid : _T_5336 ? _Queue2_UInt8_7_io_deq_valid : _T_5335 ? _Queue2_UInt8_6_io_deq_valid : _T_5334 ? _Queue2_UInt8_5_io_deq_valid : _T_5333 ? _Queue2_UInt8_4_io_deq_valid : _T_5332 ? _Queue2_UInt8_3_io_deq_valid : _T_5331 ? _Queue2_UInt8_2_io_deq_valid : _T_5330 ? _Queue2_UInt8_1_io_deq_valid : _T_5329 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] reg [63:0] backend_bytes_written; // @[ZstdCompressorMemWriter.scala:167:38] wire [64:0] _GEN_122 = {1'h0, backend_bytes_written}; // @[ZstdCompressorMemWriter.scala:167:38, :168:60] wire [64:0] _backend_next_write_addr_T = {1'h0, _dest_info_Q_io_deq_bits_op} + _GEN_122; // @[ZstdCompressorMemWriter.scala:39:27, :168:60] wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[ZstdCompressorMemWriter.scala:168:60] wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_122; // @[ZstdCompressorMemWriter.scala:52:26, :168:60, :171:28] wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[ZstdCompressorMemWriter.scala:171:28] wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[ZstdCompressorMemWriter.scala:52:26, :170:25, :171:28] wire _throttle_end_writeable_T = |(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49] wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53] wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53, :183:55] wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55] wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55, :184:57] wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57] wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57, :185:59] wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59] wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59, :186:61] wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61] wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61, :187:63] wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[ZstdCompressorMemWriter.scala:179:{48,61}] wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[ZstdCompressorMemWriter.scala:178:{46,59}, :179:48] wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[ZstdCompressorMemWriter.scala:177:{44,57}, :178:46] wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[ZstdCompressorMemWriter.scala:176:{42,55}, :177:44] wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[ZstdCompressorMemWriter.scala:175:{40,53}, :176:42] wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[ZstdCompressorMemWriter.scala:174:{35,49}, :175:40] wire _throttle_end_writeable_log2_T = |(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49, :182:54] wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[ZstdCompressorMemWriter.scala:186:{48,61}] wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[ZstdCompressorMemWriter.scala:185:{46,59}, :186:48] wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:184:{44,57}, :185:46] wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[ZstdCompressorMemWriter.scala:183:{42,55}, :184:44] wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[ZstdCompressorMemWriter.scala:182:{40,54}, :183:42] wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66] wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66, :198:71] wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68] wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68, :199:72] wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70] wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70, :200:74] wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72] wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72, :201:76] wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74] wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74, :202:78] wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[ZstdCompressorMemWriter.scala:195:{50,74}] wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[ZstdCompressorMemWriter.scala:194:{48,72}, :195:50] wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[ZstdCompressorMemWriter.scala:193:{46,70}, :194:48] wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[ZstdCompressorMemWriter.scala:192:{44,68}, :193:46] wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[ZstdCompressorMemWriter.scala:191:{42,66}, :192:44] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[ZstdCompressorMemWriter.scala:202:{54,78}] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[ZstdCompressorMemWriter.scala:201:{52,76}, :202:54] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[ZstdCompressorMemWriter.scala:200:{50,74}, :201:52] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[ZstdCompressorMemWriter.scala:199:{48,72}, :200:50] wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:198:{47,71}, :199:48] wire _count_valids_largest_aligned_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54] wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54, :213:59] wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55] wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55, :214:61] wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57] wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57, :215:63] wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59] wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59, :216:65] wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61] wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61, :217:67] wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63] wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63, :218:69] wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[ZstdCompressorMemWriter.scala:210:{50,63}] wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[ZstdCompressorMemWriter.scala:209:{48,61}, :210:50] wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[ZstdCompressorMemWriter.scala:208:{46,59}, :209:48] wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[ZstdCompressorMemWriter.scala:207:{44,57}, :208:46] wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[ZstdCompressorMemWriter.scala:206:{42,55}, :207:44] wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[ZstdCompressorMemWriter.scala:205:{41,54}, :206:42] wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[ZstdCompressorMemWriter.scala:217:{54,67}] wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[ZstdCompressorMemWriter.scala:216:{52,65}, :217:54] wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[ZstdCompressorMemWriter.scala:215:{50,63}, :216:52] wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[ZstdCompressorMemWriter.scala:214:{48,61}, :215:50] wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[ZstdCompressorMemWriter.scala:213:{46,59}, :214:48] wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[ZstdCompressorMemWriter.scala:191:42, :205:41, :225:35] wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:39] wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:{8,39}] wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:38] wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:{8,38}] wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[ZstdCompressorMemWriter.scala:224:27, :225:35, :226:8, :229:8] wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire enough_data = |bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36] wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[ZstdCompressorMemWriter.scala:198:47, :213:46, :238:40] wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:44] wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:{8,44}] wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:43] wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:{8,43}] wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[ZstdCompressorMemWriter.scala:237:32, :238:40, :239:8, :242:8] wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[ZstdCompressorMemWriter.scala:52:26, :167:38, :247:79] wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[ZstdCompressorMemWriter.scala:52:26, :247:{52,79}] wire _remapVecReadys_0_T = |bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36, :264:43] wire _T_5363 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_1_T = |(bytes_to_write[5:1]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_3_T = |(bytes_to_write[5:2]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_7_T = |(bytes_to_write[5:3]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_15_T = |(bytes_to_write[5:4]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_31_T = bytes_to_write[5]; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _T_5365 = _T_5363 & ~write_ptr_override & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:153:33, :224:27, :268:43] wire [6:0] _GEN_123 = _read_start_index_T % 7'h20; // @[ZstdCompressorMemWriter.scala:268:{43,62}] wire [5:0] _read_start_index_T_1 = _GEN_123[5:0]; // @[ZstdCompressorMemWriter.scala:268:62] wire [64:0] _backend_bytes_written_T = _GEN_122 + {59'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:168:60, :224:27, :269:52] wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[ZstdCompressorMemWriter.scala:269:52] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53] wire _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _io_l2io_req_valid_T_2 = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[Misc.scala:26:53] wire _io_l2io_req_valid_T_3 = _io_l2io_req_valid_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] assign _io_l2io_req_valid_T_4 = _io_l2io_req_valid_T_1 | _io_l2io_req_valid_T_3; // @[Misc.scala:26:53] assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_4; // @[ZstdCompressorMemWriter.scala:23:7, :278:65] assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h2 : bytes_to_write_log2; // @[ZstdCompressorMemWriter.scala:237:32, :247:52, :282:31] assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:23:7, :282:31] assign _io_l2io_req_bits_addr_T = write_ptr_override ? _dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[ZstdCompressorMemWriter.scala:39:27, :168:60, :247:52, :283:31] assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:23:7, :283:31] assign _io_l2io_req_bits_data_T = write_ptr_override ? {192'h0, _dest_info_Q_io_deq_bits_cmpval} : remapped_write_data; // @[ZstdCompressorMemWriter.scala:39:27, :89:{76,90}, :233:32, :247:52, :284:31] assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:23:7, :284:31] wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53] wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53] assign _dest_info_Q_io_deq_ready_T_1 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53] reg [63:0] bufs_completed; // @[ZstdCompressorMemWriter.scala:290:31] assign io_bufs_completed = bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7, :290:31] wire _T_5372 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18] wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[ZstdCompressorMemWriter.scala:290:31, :298:38] wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[ZstdCompressorMemWriter.scala:298:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to this FIRRTL code module IDPool_7 : input clock : Clock input reset : Reset output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}} regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff) regreset select : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid : UInt<1>, clock, reset, UInt<1>(0h1) connect io.alloc.valid, valid connect io.alloc.bits, select node taken_shiftAmount = bits(io.alloc.bits, 2, 0) node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount) node _taken_T_1 = bits(_taken_T, 7, 0) node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0)) node allocated_shiftAmount = bits(io.free.bits, 2, 0) node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount) node _allocated_T_1 = bits(_allocated_T, 7, 0) node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0)) node _bitmap1_T = not(taken) node _bitmap1_T_1 = and(bitmap, _bitmap1_T) node bitmap1 = or(_bitmap1_T_1, allocated) node _select1_T = bits(bitmap1, 0, 0) node _select1_T_1 = bits(bitmap1, 1, 1) node _select1_T_2 = bits(bitmap1, 2, 2) node _select1_T_3 = bits(bitmap1, 3, 3) node _select1_T_4 = bits(bitmap1, 4, 4) node _select1_T_5 = bits(bitmap1, 5, 5) node _select1_T_6 = bits(bitmap1, 6, 6) node _select1_T_7 = bits(bitmap1, 7, 7) node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8) node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9) node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10) node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11) node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12) node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13) node _valid1_T = orr(bitmap) node _valid1_T_1 = bits(bitmap, 0, 0) node _valid1_T_2 = bits(bitmap, 1, 1) node _valid1_T_3 = bits(bitmap, 2, 2) node _valid1_T_4 = bits(bitmap, 3, 3) node _valid1_T_5 = bits(bitmap, 4, 4) node _valid1_T_6 = bits(bitmap, 5, 5) node _valid1_T_7 = bits(bitmap, 6, 6) node _valid1_T_8 = bits(bitmap, 7, 7) node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2) node _valid1_T_10 = bits(_valid1_T_9, 1, 0) node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4) node _valid1_T_12 = bits(_valid1_T_11, 1, 0) node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12) node _valid1_T_14 = bits(_valid1_T_13, 2, 0) node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6) node _valid1_T_16 = bits(_valid1_T_15, 1, 0) node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8) node _valid1_T_18 = bits(_valid1_T_17, 1, 0) node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18) node _valid1_T_20 = bits(_valid1_T_19, 2, 0) node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20) node _valid1_T_22 = bits(_valid1_T_21, 3, 0) node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1)) node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready) node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0)) node _valid1_T_26 = and(_valid1_T, _valid1_T_25) node valid1 = or(_valid1_T_26, io.free.valid) node _T = or(io.alloc.ready, io.free.valid) when _T : connect bitmap, bitmap1 connect valid, valid1 node _T_1 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_2 = and(_T_1, io.free.valid) node _T_3 = or(io.alloc.ready, _T_2) when _T_3 : connect select, select1 node _T_4 = eq(io.free.valid, UInt<1>(0h0)) node _T_5 = not(taken) node _T_6 = and(bitmap, _T_5) node _T_7 = dshr(_T_6, io.free.bits) node _T_8 = bits(_T_7, 0, 0) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_4, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = orr(bitmap) node _T_15 = eq(valid, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node _T_19 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_20 = and(_T_19, io.free.valid) node _T_21 = or(io.alloc.ready, _T_20) reg REG : UInt<1>, clock connect REG, _T_21 node _T_22 = and(io.alloc.valid, REG) when _T_22 : node _T_23 = bits(bitmap, 0, 0) node _T_24 = bits(bitmap, 1, 1) node _T_25 = bits(bitmap, 2, 2) node _T_26 = bits(bitmap, 3, 3) node _T_27 = bits(bitmap, 4, 4) node _T_28 = bits(bitmap, 5, 5) node _T_29 = bits(bitmap, 6, 6) node _T_30 = bits(bitmap, 7, 7) node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7)) node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31) node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32) node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33) node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34) node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35) node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36) node _T_38 = eq(select, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2 assert(clock, _T_38, UInt<1>(0h1), "") : assert_2

module IDPool_7( // @[IDPool.scala:8:7] input clock, // @[IDPool.scala:8:7] input reset, // @[IDPool.scala:8:7] input io_free_valid, // @[IDPool.scala:12:14] input [2:0] io_free_bits, // @[IDPool.scala:12:14] input io_alloc_ready, // @[IDPool.scala:12:14] output io_alloc_valid, // @[IDPool.scala:12:14] output [2:0] io_alloc_bits // @[IDPool.scala:12:14] ); wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7] wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7] wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7] wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7] wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49] wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49] wire io_alloc_valid_0; // @[IDPool.scala:8:7] reg [7:0] bitmap; // @[IDPool.scala:18:23] reg [2:0] select; // @[IDPool.scala:19:23] assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23] reg valid; // @[IDPool.scala:20:23] assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23] wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}] wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}] wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27] wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}] wire [7:0] bitmap1 = _bitmap1_T_1 | allocated; // @[IDPool.scala:26:22, :27:{25,35}] wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45] wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45] wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45] wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45] wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45] wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45] wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45] wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45] wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45] wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45] wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45] wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45] wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45] wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45] wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45] wire _valid1_T = |bitmap; // @[IDPool.scala:18:23, :29:28] wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46] wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46] wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}] wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}] wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}] wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}] wire valid1 = _valid1_T_26 | io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17] reg REG; // @[IDPool.scala:51:36]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_6 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 connect _source_ok_WIRE[9], _source_ok_T_44 connect _source_ok_WIRE[10], _source_ok_T_45 node _source_ok_T_46 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[2]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[3]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[4]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[5]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[6]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[7]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[8]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_54, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h3)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<2>(0h2)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<4>(0h8)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_112 = eq(_T_111, UInt<1>(0h0)) node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_114 = cvt(_T_113) node _T_115 = and(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = asSInt(_T_115) node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0))) node _T_118 = or(_T_112, _T_117) node _T_119 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _T_127 = and(_T_11, _T_24) node _T_128 = and(_T_127, _T_37) node _T_129 = and(_T_128, _T_50) node _T_130 = and(_T_129, _T_63) node _T_131 = and(_T_130, _T_76) node _T_132 = and(_T_131, _T_89) node _T_133 = and(_T_132, _T_102) node _T_134 = and(_T_133, _T_110) node _T_135 = and(_T_134, _T_118) node _T_136 = and(_T_135, _T_126) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_136, UInt<1>(0h1), "") : assert_1 node _T_140 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_140 : node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_7) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<1>(0h1)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_8) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h2)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_9) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<2>(0h3)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_10) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_169 = shr(io.in.a.bits.source, 3) node _T_170 = eq(_T_169, UInt<2>(0h3)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_11) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_175 = shr(io.in.a.bits.source, 3) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_12) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_181 = shr(io.in.a.bits.source, 3) node _T_182 = eq(_T_181, UInt<4>(0h8)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_188 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_190 = or(_T_144, _T_150) node _T_191 = or(_T_190, _T_156) node _T_192 = or(_T_191, _T_162) node _T_193 = or(_T_192, _T_168) node _T_194 = or(_T_193, _T_174) node _T_195 = or(_T_194, _T_180) node _T_196 = or(_T_195, _T_186) node _T_197 = or(_T_196, _T_187) node _T_198 = or(_T_197, _T_188) node _T_199 = or(_T_198, _T_189) node _T_200 = and(_T_143, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = or(_T_207, _T_212) node _T_219 = or(_T_218, _T_217) node _T_220 = and(_T_202, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_201, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_222, UInt<1>(0h1), "") : assert_2 node _T_226 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_227 = shr(io.in.a.bits.source, 2) node _T_228 = eq(_T_227, UInt<1>(0h0)) node _T_229 = leq(UInt<1>(0h0), uncommonBits_14) node _T_230 = and(_T_228, _T_229) node _T_231 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<1>(0h1)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_15) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_239 = shr(io.in.a.bits.source, 2) node _T_240 = eq(_T_239, UInt<2>(0h2)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_16) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_245 = shr(io.in.a.bits.source, 2) node _T_246 = eq(_T_245, UInt<2>(0h3)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_17) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_251 = shr(io.in.a.bits.source, 3) node _T_252 = eq(_T_251, UInt<2>(0h3)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_18) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_257 = shr(io.in.a.bits.source, 3) node _T_258 = eq(_T_257, UInt<2>(0h2)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_19) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_263 = shr(io.in.a.bits.source, 3) node _T_264 = eq(_T_263, UInt<4>(0h8)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_20) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_20, UInt<3>(0h4)) node _T_268 = and(_T_266, _T_267) node _T_269 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_270 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_271 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_226 connect _WIRE[1], _T_232 connect _WIRE[2], _T_238 connect _WIRE[3], _T_244 connect _WIRE[4], _T_250 connect _WIRE[5], _T_256 connect _WIRE[6], _T_262 connect _WIRE[7], _T_268 connect _WIRE[8], _T_269 connect _WIRE[9], _T_270 connect _WIRE[10], _T_271 node _T_272 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_273 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_274 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_275 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_276 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_278 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_279 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_280 = mux(_WIRE[7], _T_272, UInt<1>(0h0)) node _T_281 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_282 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_284 = or(_T_273, _T_274) node _T_285 = or(_T_284, _T_275) node _T_286 = or(_T_285, _T_276) node _T_287 = or(_T_286, _T_277) node _T_288 = or(_T_287, _T_278) node _T_289 = or(_T_288, _T_279) node _T_290 = or(_T_289, _T_280) node _T_291 = or(_T_290, _T_281) node _T_292 = or(_T_291, _T_282) node _T_293 = or(_T_292, _T_283) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_293 node _T_294 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_295 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_296 = and(_T_294, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_302, _T_307) node _T_314 = or(_T_313, _T_312) node _T_315 = and(_T_297, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_WIRE_1, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_317, UInt<1>(0h1), "") : assert_3 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(source_ok, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_324 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_324, UInt<1>(0h1), "") : assert_5 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(is_aligned, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_331 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_331, UInt<1>(0h1), "") : assert_7 node _T_335 = not(io.in.a.bits.mask) node _T_336 = eq(_T_335, UInt<1>(0h0)) node _T_337 = asUInt(reset) node _T_338 = eq(_T_337, UInt<1>(0h0)) when _T_338 : node _T_339 = eq(_T_336, UInt<1>(0h0)) when _T_339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_336, UInt<1>(0h1), "") : assert_8 node _T_340 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_T_340, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_340, UInt<1>(0h1), "") : assert_9 node _T_344 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_344 : node _T_345 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_346 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_349 = shr(io.in.a.bits.source, 2) node _T_350 = eq(_T_349, UInt<1>(0h0)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_21) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_355 = shr(io.in.a.bits.source, 2) node _T_356 = eq(_T_355, UInt<1>(0h1)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_22) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_361 = shr(io.in.a.bits.source, 2) node _T_362 = eq(_T_361, UInt<2>(0h2)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_23) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_366 = and(_T_364, _T_365) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_367 = shr(io.in.a.bits.source, 2) node _T_368 = eq(_T_367, UInt<2>(0h3)) node _T_369 = leq(UInt<1>(0h0), uncommonBits_24) node _T_370 = and(_T_368, _T_369) node _T_371 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_372 = and(_T_370, _T_371) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_373 = shr(io.in.a.bits.source, 3) node _T_374 = eq(_T_373, UInt<2>(0h3)) node _T_375 = leq(UInt<1>(0h0), uncommonBits_25) node _T_376 = and(_T_374, _T_375) node _T_377 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_378 = and(_T_376, _T_377) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_379 = shr(io.in.a.bits.source, 3) node _T_380 = eq(_T_379, UInt<2>(0h2)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_26) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_385 = shr(io.in.a.bits.source, 3) node _T_386 = eq(_T_385, UInt<4>(0h8)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_27) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_27, UInt<3>(0h4)) node _T_390 = and(_T_388, _T_389) node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_392 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_393 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_394 = or(_T_348, _T_354) node _T_395 = or(_T_394, _T_360) node _T_396 = or(_T_395, _T_366) node _T_397 = or(_T_396, _T_372) node _T_398 = or(_T_397, _T_378) node _T_399 = or(_T_398, _T_384) node _T_400 = or(_T_399, _T_390) node _T_401 = or(_T_400, _T_391) node _T_402 = or(_T_401, _T_392) node _T_403 = or(_T_402, _T_393) node _T_404 = and(_T_347, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_407 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = or(_T_411, _T_416) node _T_423 = or(_T_422, _T_421) node _T_424 = and(_T_406, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_405, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_426, UInt<1>(0h1), "") : assert_10 node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_431 = shr(io.in.a.bits.source, 2) node _T_432 = eq(_T_431, UInt<1>(0h0)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_28) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_436 = and(_T_434, _T_435) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_437 = shr(io.in.a.bits.source, 2) node _T_438 = eq(_T_437, UInt<1>(0h1)) node _T_439 = leq(UInt<1>(0h0), uncommonBits_29) node _T_440 = and(_T_438, _T_439) node _T_441 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_442 = and(_T_440, _T_441) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_443 = shr(io.in.a.bits.source, 2) node _T_444 = eq(_T_443, UInt<2>(0h2)) node _T_445 = leq(UInt<1>(0h0), uncommonBits_30) node _T_446 = and(_T_444, _T_445) node _T_447 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_448 = and(_T_446, _T_447) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_449 = shr(io.in.a.bits.source, 2) node _T_450 = eq(_T_449, UInt<2>(0h3)) node _T_451 = leq(UInt<1>(0h0), uncommonBits_31) node _T_452 = and(_T_450, _T_451) node _T_453 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_454 = and(_T_452, _T_453) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_455 = shr(io.in.a.bits.source, 3) node _T_456 = eq(_T_455, UInt<2>(0h3)) node _T_457 = leq(UInt<1>(0h0), uncommonBits_32) node _T_458 = and(_T_456, _T_457) node _T_459 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_460 = and(_T_458, _T_459) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_461 = shr(io.in.a.bits.source, 3) node _T_462 = eq(_T_461, UInt<2>(0h2)) node _T_463 = leq(UInt<1>(0h0), uncommonBits_33) node _T_464 = and(_T_462, _T_463) node _T_465 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_466 = and(_T_464, _T_465) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_467 = shr(io.in.a.bits.source, 3) node _T_468 = eq(_T_467, UInt<4>(0h8)) node _T_469 = leq(UInt<1>(0h0), uncommonBits_34) node _T_470 = and(_T_468, _T_469) node _T_471 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_474 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_475 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_430 connect _WIRE_2[1], _T_436 connect _WIRE_2[2], _T_442 connect _WIRE_2[3], _T_448 connect _WIRE_2[4], _T_454 connect _WIRE_2[5], _T_460 connect _WIRE_2[6], _T_466 connect _WIRE_2[7], _T_472 connect _WIRE_2[8], _T_473 connect _WIRE_2[9], _T_474 connect _WIRE_2[10], _T_475 node _T_476 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_477 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_478 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_481 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_482 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_483 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_484 = mux(_WIRE_2[7], _T_476, UInt<1>(0h0)) node _T_485 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_486 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_487 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_488 = or(_T_477, _T_478) node _T_489 = or(_T_488, _T_479) node _T_490 = or(_T_489, _T_480) node _T_491 = or(_T_490, _T_481) node _T_492 = or(_T_491, _T_482) node _T_493 = or(_T_492, _T_483) node _T_494 = or(_T_493, _T_484) node _T_495 = or(_T_494, _T_485) node _T_496 = or(_T_495, _T_486) node _T_497 = or(_T_496, _T_487) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_497 node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<13>(0h1000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<13>(0h1000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_506, _T_511) node _T_518 = or(_T_517, _T_516) node _T_519 = and(_T_501, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_WIRE_3, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_521, UInt<1>(0h1), "") : assert_11 node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(source_ok, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_528, UInt<1>(0h1), "") : assert_13 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(is_aligned, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_535, UInt<1>(0h1), "") : assert_15 node _T_539 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_540 = asUInt(reset) node _T_541 = eq(_T_540, UInt<1>(0h0)) when _T_541 : node _T_542 = eq(_T_539, UInt<1>(0h0)) when _T_542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_539, UInt<1>(0h1), "") : assert_16 node _T_543 = not(io.in.a.bits.mask) node _T_544 = eq(_T_543, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_544, UInt<1>(0h1), "") : assert_17 node _T_548 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_548, UInt<1>(0h1), "") : assert_18 node _T_552 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_552 : node _T_553 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_554 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_35) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_563 = shr(io.in.a.bits.source, 2) node _T_564 = eq(_T_563, UInt<1>(0h1)) node _T_565 = leq(UInt<1>(0h0), uncommonBits_36) node _T_566 = and(_T_564, _T_565) node _T_567 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_568 = and(_T_566, _T_567) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<2>(0h2)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_37) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<2>(0h3)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_38) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_581 = shr(io.in.a.bits.source, 3) node _T_582 = eq(_T_581, UInt<2>(0h3)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_39) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_587 = shr(io.in.a.bits.source, 3) node _T_588 = eq(_T_587, UInt<2>(0h2)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_40) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_593 = shr(io.in.a.bits.source, 3) node _T_594 = eq(_T_593, UInt<4>(0h8)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_41) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_601 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_602 = or(_T_556, _T_562) node _T_603 = or(_T_602, _T_568) node _T_604 = or(_T_603, _T_574) node _T_605 = or(_T_604, _T_580) node _T_606 = or(_T_605, _T_586) node _T_607 = or(_T_606, _T_592) node _T_608 = or(_T_607, _T_598) node _T_609 = or(_T_608, _T_599) node _T_610 = or(_T_609, _T_600) node _T_611 = or(_T_610, _T_601) node _T_612 = and(_T_555, _T_611) node _T_613 = or(UInt<1>(0h0), _T_612) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_613, UInt<1>(0h1), "") : assert_19 node _T_617 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_618 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_619 = and(_T_617, _T_618) node _T_620 = or(UInt<1>(0h0), _T_619) node _T_621 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_622 = cvt(_T_621) node _T_623 = and(_T_622, asSInt(UInt<13>(0h1000))) node _T_624 = asSInt(_T_623) node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0))) node _T_626 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_627 = cvt(_T_626) node _T_628 = and(_T_627, asSInt(UInt<13>(0h1000))) node _T_629 = asSInt(_T_628) node _T_630 = eq(_T_629, asSInt(UInt<1>(0h0))) node _T_631 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_632 = cvt(_T_631) node _T_633 = and(_T_632, asSInt(UInt<13>(0h1000))) node _T_634 = asSInt(_T_633) node _T_635 = eq(_T_634, asSInt(UInt<1>(0h0))) node _T_636 = or(_T_625, _T_630) node _T_637 = or(_T_636, _T_635) node _T_638 = and(_T_620, _T_637) node _T_639 = or(UInt<1>(0h0), _T_638) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_639, UInt<1>(0h1), "") : assert_20 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(source_ok, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(is_aligned, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(_T_649, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_649, UInt<1>(0h1), "") : assert_23 node _T_653 = eq(io.in.a.bits.mask, mask) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_653, UInt<1>(0h1), "") : assert_24 node _T_657 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(_T_657, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_657, UInt<1>(0h1), "") : assert_25 node _T_661 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_661 : node _T_662 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_663 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h0)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_42) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<1>(0h1)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_43) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h2)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_44) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_684 = shr(io.in.a.bits.source, 2) node _T_685 = eq(_T_684, UInt<2>(0h3)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_45) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_689 = and(_T_687, _T_688) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_690 = shr(io.in.a.bits.source, 3) node _T_691 = eq(_T_690, UInt<2>(0h3)) node _T_692 = leq(UInt<1>(0h0), uncommonBits_46) node _T_693 = and(_T_691, _T_692) node _T_694 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_695 = and(_T_693, _T_694) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_696 = shr(io.in.a.bits.source, 3) node _T_697 = eq(_T_696, UInt<2>(0h2)) node _T_698 = leq(UInt<1>(0h0), uncommonBits_47) node _T_699 = and(_T_697, _T_698) node _T_700 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_701 = and(_T_699, _T_700) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_702 = shr(io.in.a.bits.source, 3) node _T_703 = eq(_T_702, UInt<4>(0h8)) node _T_704 = leq(UInt<1>(0h0), uncommonBits_48) node _T_705 = and(_T_703, _T_704) node _T_706 = leq(uncommonBits_48, UInt<3>(0h4)) node _T_707 = and(_T_705, _T_706) node _T_708 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_709 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_710 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_711 = or(_T_665, _T_671) node _T_712 = or(_T_711, _T_677) node _T_713 = or(_T_712, _T_683) node _T_714 = or(_T_713, _T_689) node _T_715 = or(_T_714, _T_695) node _T_716 = or(_T_715, _T_701) node _T_717 = or(_T_716, _T_707) node _T_718 = or(_T_717, _T_708) node _T_719 = or(_T_718, _T_709) node _T_720 = or(_T_719, _T_710) node _T_721 = and(_T_664, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_725 = and(_T_723, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_728 = cvt(_T_727) node _T_729 = and(_T_728, asSInt(UInt<13>(0h1000))) node _T_730 = asSInt(_T_729) node _T_731 = eq(_T_730, asSInt(UInt<1>(0h0))) node _T_732 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_733 = cvt(_T_732) node _T_734 = and(_T_733, asSInt(UInt<13>(0h1000))) node _T_735 = asSInt(_T_734) node _T_736 = eq(_T_735, asSInt(UInt<1>(0h0))) node _T_737 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_738 = cvt(_T_737) node _T_739 = and(_T_738, asSInt(UInt<13>(0h1000))) node _T_740 = asSInt(_T_739) node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0))) node _T_742 = or(_T_731, _T_736) node _T_743 = or(_T_742, _T_741) node _T_744 = and(_T_726, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = and(_T_722, _T_745) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_746, UInt<1>(0h1), "") : assert_26 node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(source_ok, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(is_aligned, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_756 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(_T_756, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_756, UInt<1>(0h1), "") : assert_29 node _T_760 = eq(io.in.a.bits.mask, mask) node _T_761 = asUInt(reset) node _T_762 = eq(_T_761, UInt<1>(0h0)) when _T_762 : node _T_763 = eq(_T_760, UInt<1>(0h0)) when _T_763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_760, UInt<1>(0h1), "") : assert_30 node _T_764 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_764 : node _T_765 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_766 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_769 = shr(io.in.a.bits.source, 2) node _T_770 = eq(_T_769, UInt<1>(0h0)) node _T_771 = leq(UInt<1>(0h0), uncommonBits_49) node _T_772 = and(_T_770, _T_771) node _T_773 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_774 = and(_T_772, _T_773) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_775 = shr(io.in.a.bits.source, 2) node _T_776 = eq(_T_775, UInt<1>(0h1)) node _T_777 = leq(UInt<1>(0h0), uncommonBits_50) node _T_778 = and(_T_776, _T_777) node _T_779 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_780 = and(_T_778, _T_779) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_781 = shr(io.in.a.bits.source, 2) node _T_782 = eq(_T_781, UInt<2>(0h2)) node _T_783 = leq(UInt<1>(0h0), uncommonBits_51) node _T_784 = and(_T_782, _T_783) node _T_785 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_786 = and(_T_784, _T_785) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_787 = shr(io.in.a.bits.source, 2) node _T_788 = eq(_T_787, UInt<2>(0h3)) node _T_789 = leq(UInt<1>(0h0), uncommonBits_52) node _T_790 = and(_T_788, _T_789) node _T_791 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_792 = and(_T_790, _T_791) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_793 = shr(io.in.a.bits.source, 3) node _T_794 = eq(_T_793, UInt<2>(0h3)) node _T_795 = leq(UInt<1>(0h0), uncommonBits_53) node _T_796 = and(_T_794, _T_795) node _T_797 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_798 = and(_T_796, _T_797) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_799 = shr(io.in.a.bits.source, 3) node _T_800 = eq(_T_799, UInt<2>(0h2)) node _T_801 = leq(UInt<1>(0h0), uncommonBits_54) node _T_802 = and(_T_800, _T_801) node _T_803 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_804 = and(_T_802, _T_803) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_805 = shr(io.in.a.bits.source, 3) node _T_806 = eq(_T_805, UInt<4>(0h8)) node _T_807 = leq(UInt<1>(0h0), uncommonBits_55) node _T_808 = and(_T_806, _T_807) node _T_809 = leq(uncommonBits_55, UInt<3>(0h4)) node _T_810 = and(_T_808, _T_809) node _T_811 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_812 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_813 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_814 = or(_T_768, _T_774) node _T_815 = or(_T_814, _T_780) node _T_816 = or(_T_815, _T_786) node _T_817 = or(_T_816, _T_792) node _T_818 = or(_T_817, _T_798) node _T_819 = or(_T_818, _T_804) node _T_820 = or(_T_819, _T_810) node _T_821 = or(_T_820, _T_811) node _T_822 = or(_T_821, _T_812) node _T_823 = or(_T_822, _T_813) node _T_824 = and(_T_767, _T_823) node _T_825 = or(UInt<1>(0h0), _T_824) node _T_826 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_827 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_828 = and(_T_826, _T_827) node _T_829 = or(UInt<1>(0h0), _T_828) node _T_830 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<13>(0h1000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = or(_T_834, _T_839) node _T_846 = or(_T_845, _T_844) node _T_847 = and(_T_829, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = and(_T_825, _T_848) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_849, UInt<1>(0h1), "") : assert_31 node _T_853 = asUInt(reset) node _T_854 = eq(_T_853, UInt<1>(0h0)) when _T_854 : node _T_855 = eq(source_ok, UInt<1>(0h0)) when _T_855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(is_aligned, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_859 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_859, UInt<1>(0h1), "") : assert_34 node _T_863 = not(mask) node _T_864 = and(io.in.a.bits.mask, _T_863) node _T_865 = eq(_T_864, UInt<1>(0h0)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_865, UInt<1>(0h1), "") : assert_35 node _T_869 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_869 : node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_872 = and(_T_870, _T_871) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<1>(0h0)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_56) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h1)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_57) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_886 = shr(io.in.a.bits.source, 2) node _T_887 = eq(_T_886, UInt<2>(0h2)) node _T_888 = leq(UInt<1>(0h0), uncommonBits_58) node _T_889 = and(_T_887, _T_888) node _T_890 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_891 = and(_T_889, _T_890) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_892 = shr(io.in.a.bits.source, 2) node _T_893 = eq(_T_892, UInt<2>(0h3)) node _T_894 = leq(UInt<1>(0h0), uncommonBits_59) node _T_895 = and(_T_893, _T_894) node _T_896 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_897 = and(_T_895, _T_896) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_898 = shr(io.in.a.bits.source, 3) node _T_899 = eq(_T_898, UInt<2>(0h3)) node _T_900 = leq(UInt<1>(0h0), uncommonBits_60) node _T_901 = and(_T_899, _T_900) node _T_902 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_903 = and(_T_901, _T_902) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_904 = shr(io.in.a.bits.source, 3) node _T_905 = eq(_T_904, UInt<2>(0h2)) node _T_906 = leq(UInt<1>(0h0), uncommonBits_61) node _T_907 = and(_T_905, _T_906) node _T_908 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_909 = and(_T_907, _T_908) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_910 = shr(io.in.a.bits.source, 3) node _T_911 = eq(_T_910, UInt<4>(0h8)) node _T_912 = leq(UInt<1>(0h0), uncommonBits_62) node _T_913 = and(_T_911, _T_912) node _T_914 = leq(uncommonBits_62, UInt<3>(0h4)) node _T_915 = and(_T_913, _T_914) node _T_916 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_917 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_918 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_919 = or(_T_873, _T_879) node _T_920 = or(_T_919, _T_885) node _T_921 = or(_T_920, _T_891) node _T_922 = or(_T_921, _T_897) node _T_923 = or(_T_922, _T_903) node _T_924 = or(_T_923, _T_909) node _T_925 = or(_T_924, _T_915) node _T_926 = or(_T_925, _T_916) node _T_927 = or(_T_926, _T_917) node _T_928 = or(_T_927, _T_918) node _T_929 = and(_T_872, _T_928) node _T_930 = or(UInt<1>(0h0), _T_929) node _T_931 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_932 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_933 = and(_T_931, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_936 = cvt(_T_935) node _T_937 = and(_T_936, asSInt(UInt<13>(0h1000))) node _T_938 = asSInt(_T_937) node _T_939 = eq(_T_938, asSInt(UInt<1>(0h0))) node _T_940 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<13>(0h1000))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<13>(0h1000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_939, _T_944) node _T_951 = or(_T_950, _T_949) node _T_952 = and(_T_934, _T_951) node _T_953 = or(UInt<1>(0h0), _T_952) node _T_954 = and(_T_930, _T_953) node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(_T_954, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_954, UInt<1>(0h1), "") : assert_36 node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(source_ok, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(is_aligned, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_964 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_964, UInt<1>(0h1), "") : assert_39 node _T_968 = eq(io.in.a.bits.mask, mask) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_968, UInt<1>(0h1), "") : assert_40 node _T_972 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_972 : node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_974 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_975 = and(_T_973, _T_974) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_977 = shr(io.in.a.bits.source, 2) node _T_978 = eq(_T_977, UInt<1>(0h0)) node _T_979 = leq(UInt<1>(0h0), uncommonBits_63) node _T_980 = and(_T_978, _T_979) node _T_981 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_982 = and(_T_980, _T_981) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_983 = shr(io.in.a.bits.source, 2) node _T_984 = eq(_T_983, UInt<1>(0h1)) node _T_985 = leq(UInt<1>(0h0), uncommonBits_64) node _T_986 = and(_T_984, _T_985) node _T_987 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_988 = and(_T_986, _T_987) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_989 = shr(io.in.a.bits.source, 2) node _T_990 = eq(_T_989, UInt<2>(0h2)) node _T_991 = leq(UInt<1>(0h0), uncommonBits_65) node _T_992 = and(_T_990, _T_991) node _T_993 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_994 = and(_T_992, _T_993) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_995 = shr(io.in.a.bits.source, 2) node _T_996 = eq(_T_995, UInt<2>(0h3)) node _T_997 = leq(UInt<1>(0h0), uncommonBits_66) node _T_998 = and(_T_996, _T_997) node _T_999 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1000 = and(_T_998, _T_999) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_1001 = shr(io.in.a.bits.source, 3) node _T_1002 = eq(_T_1001, UInt<2>(0h3)) node _T_1003 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1004 = and(_T_1002, _T_1003) node _T_1005 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_1006 = and(_T_1004, _T_1005) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_1007 = shr(io.in.a.bits.source, 3) node _T_1008 = eq(_T_1007, UInt<2>(0h2)) node _T_1009 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1010 = and(_T_1008, _T_1009) node _T_1011 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_1012 = and(_T_1010, _T_1011) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1013 = shr(io.in.a.bits.source, 3) node _T_1014 = eq(_T_1013, UInt<4>(0h8)) node _T_1015 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1016 = and(_T_1014, _T_1015) node _T_1017 = leq(uncommonBits_69, UInt<3>(0h4)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1020 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1021 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1022 = or(_T_976, _T_982) node _T_1023 = or(_T_1022, _T_988) node _T_1024 = or(_T_1023, _T_994) node _T_1025 = or(_T_1024, _T_1000) node _T_1026 = or(_T_1025, _T_1006) node _T_1027 = or(_T_1026, _T_1012) node _T_1028 = or(_T_1027, _T_1018) node _T_1029 = or(_T_1028, _T_1019) node _T_1030 = or(_T_1029, _T_1020) node _T_1031 = or(_T_1030, _T_1021) node _T_1032 = and(_T_975, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1035 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = or(UInt<1>(0h0), _T_1036) node _T_1038 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<13>(0h1000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1044 = cvt(_T_1043) node _T_1045 = and(_T_1044, asSInt(UInt<13>(0h1000))) node _T_1046 = asSInt(_T_1045) node _T_1047 = eq(_T_1046, asSInt(UInt<1>(0h0))) node _T_1048 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1049 = cvt(_T_1048) node _T_1050 = and(_T_1049, asSInt(UInt<13>(0h1000))) node _T_1051 = asSInt(_T_1050) node _T_1052 = eq(_T_1051, asSInt(UInt<1>(0h0))) node _T_1053 = or(_T_1042, _T_1047) node _T_1054 = or(_T_1053, _T_1052) node _T_1055 = and(_T_1037, _T_1054) node _T_1056 = or(UInt<1>(0h0), _T_1055) node _T_1057 = and(_T_1033, _T_1056) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_41 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(source_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(is_aligned, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_44 node _T_1071 = eq(io.in.a.bits.mask, mask) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_45 node _T_1075 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1075 : node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1080 = shr(io.in.a.bits.source, 2) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) node _T_1082 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1085 = and(_T_1083, _T_1084) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1086 = shr(io.in.a.bits.source, 2) node _T_1087 = eq(_T_1086, UInt<1>(0h1)) node _T_1088 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1091 = and(_T_1089, _T_1090) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1092 = shr(io.in.a.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1098 = shr(io.in.a.bits.source, 2) node _T_1099 = eq(_T_1098, UInt<2>(0h3)) node _T_1100 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1103 = and(_T_1101, _T_1102) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1104 = shr(io.in.a.bits.source, 3) node _T_1105 = eq(_T_1104, UInt<2>(0h3)) node _T_1106 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1109 = and(_T_1107, _T_1108) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_1110 = shr(io.in.a.bits.source, 3) node _T_1111 = eq(_T_1110, UInt<2>(0h2)) node _T_1112 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1113 = and(_T_1111, _T_1112) node _T_1114 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1115 = and(_T_1113, _T_1114) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1116 = shr(io.in.a.bits.source, 3) node _T_1117 = eq(_T_1116, UInt<4>(0h8)) node _T_1118 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1119 = and(_T_1117, _T_1118) node _T_1120 = leq(uncommonBits_76, UInt<3>(0h4)) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1123 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1124 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1125 = or(_T_1079, _T_1085) node _T_1126 = or(_T_1125, _T_1091) node _T_1127 = or(_T_1126, _T_1097) node _T_1128 = or(_T_1127, _T_1103) node _T_1129 = or(_T_1128, _T_1109) node _T_1130 = or(_T_1129, _T_1115) node _T_1131 = or(_T_1130, _T_1121) node _T_1132 = or(_T_1131, _T_1122) node _T_1133 = or(_T_1132, _T_1123) node _T_1134 = or(_T_1133, _T_1124) node _T_1135 = and(_T_1078, _T_1134) node _T_1136 = or(UInt<1>(0h0), _T_1135) node _T_1137 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1138 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1139 = cvt(_T_1138) node _T_1140 = and(_T_1139, asSInt(UInt<13>(0h1000))) node _T_1141 = asSInt(_T_1140) node _T_1142 = eq(_T_1141, asSInt(UInt<1>(0h0))) node _T_1143 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1144 = cvt(_T_1143) node _T_1145 = and(_T_1144, asSInt(UInt<13>(0h1000))) node _T_1146 = asSInt(_T_1145) node _T_1147 = eq(_T_1146, asSInt(UInt<1>(0h0))) node _T_1148 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<13>(0h1000))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = or(_T_1142, _T_1147) node _T_1154 = or(_T_1153, _T_1152) node _T_1155 = and(_T_1137, _T_1154) node _T_1156 = or(UInt<1>(0h0), _T_1155) node _T_1157 = and(_T_1136, _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_46 node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(source_ok, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(is_aligned, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1167 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_49 node _T_1171 = eq(io.in.a.bits.mask, mask) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_50 node _T_1175 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1179 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_52 node _source_ok_T_55 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<1>(0h0)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<1>(0h1)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 2) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<2>(0h2)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_74 = shr(io.in.d.bits.source, 2) node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h3)) node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_T_78 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_80 = shr(io.in.d.bits.source, 3) node _source_ok_T_81 = eq(_source_ok_T_80, UInt<2>(0h3)) node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_T_84 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_86 = shr(io.in.d.bits.source, 3) node _source_ok_T_87 = eq(_source_ok_T_86, UInt<2>(0h2)) node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_T_90 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_92 = shr(io.in.d.bits.source, 3) node _source_ok_T_93 = eq(_source_ok_T_92, UInt<4>(0h8)) node _source_ok_T_94 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_T_96 = leq(source_ok_uncommonBits_13, UInt<3>(0h4)) node _source_ok_T_97 = and(_source_ok_T_95, _source_ok_T_96) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_55 connect _source_ok_WIRE_1[1], _source_ok_T_61 connect _source_ok_WIRE_1[2], _source_ok_T_67 connect _source_ok_WIRE_1[3], _source_ok_T_73 connect _source_ok_WIRE_1[4], _source_ok_T_79 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_91 connect _source_ok_WIRE_1[7], _source_ok_T_97 connect _source_ok_WIRE_1[8], _source_ok_T_98 connect _source_ok_WIRE_1[9], _source_ok_T_99 connect _source_ok_WIRE_1[10], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1183 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1183 : node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(source_ok_1, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1187 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_54 node _T_1191 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_55 node _T_1195 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_56 node _T_1199 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_57 node _T_1203 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1203 : node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(source_ok_1, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(sink_ok, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1210 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_60 node _T_1214 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_61 node _T_1218 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_62 node _T_1222 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(_T_1222, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1222, UInt<1>(0h1), "") : assert_63 node _T_1226 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1227 = or(UInt<1>(0h0), _T_1226) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_64 node _T_1231 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1231 : node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(source_ok_1, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(sink_ok, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1238 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_67 node _T_1242 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_68 node _T_1246 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_69 node _T_1250 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1251 = or(_T_1250, io.in.d.bits.corrupt) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_70 node _T_1255 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1256 = or(UInt<1>(0h0), _T_1255) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_71 node _T_1260 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1260 : node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(source_ok_1, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1264 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_73 node _T_1268 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_74 node _T_1272 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1273 = or(UInt<1>(0h0), _T_1272) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_75 node _T_1277 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1277 : node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(source_ok_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1281 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_77 node _T_1285 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1286 = or(_T_1285, io.in.d.bits.corrupt) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_78 node _T_1290 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1291 = or(UInt<1>(0h0), _T_1290) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_79 node _T_1295 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1295 : node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(source_ok_1, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1299 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_81 node _T_1303 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_82 node _T_1307 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1308 = or(UInt<1>(0h0), _T_1307) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1312 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1316 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1320 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1324 = eq(a_first, UInt<1>(0h0)) node _T_1325 = and(io.in.a.valid, _T_1324) when _T_1325 : node _T_1326 = eq(io.in.a.bits.opcode, opcode) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_87 node _T_1330 = eq(io.in.a.bits.param, param) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_88 node _T_1334 = eq(io.in.a.bits.size, size) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_89 node _T_1338 = eq(io.in.a.bits.source, source) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_90 node _T_1342 = eq(io.in.a.bits.address, address) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_91 node _T_1346 = and(io.in.a.ready, io.in.a.valid) node _T_1347 = and(_T_1346, a_first) when _T_1347 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1348 = eq(d_first, UInt<1>(0h0)) node _T_1349 = and(io.in.d.valid, _T_1348) when _T_1349 : node _T_1350 = eq(io.in.d.bits.opcode, opcode_1) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_92 node _T_1354 = eq(io.in.d.bits.param, param_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_93 node _T_1358 = eq(io.in.d.bits.size, size_1) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_94 node _T_1362 = eq(io.in.d.bits.source, source_1) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_95 node _T_1366 = eq(io.in.d.bits.sink, sink) node _T_1367 = asUInt(reset) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) when _T_1368 : node _T_1369 = eq(_T_1366, UInt<1>(0h0)) when _T_1369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1366, UInt<1>(0h1), "") : assert_96 node _T_1370 = eq(io.in.d.bits.denied, denied) node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(_T_1370, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1370, UInt<1>(0h1), "") : assert_97 node _T_1374 = and(io.in.d.ready, io.in.d.valid) node _T_1375 = and(_T_1374, d_first) when _T_1375 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1376 = and(io.in.a.valid, a_first_1) node _T_1377 = and(_T_1376, UInt<1>(0h1)) when _T_1377 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1378 = and(io.in.a.ready, io.in.a.valid) node _T_1379 = and(_T_1378, a_first_1) node _T_1380 = and(_T_1379, UInt<1>(0h1)) when _T_1380 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1381 = dshr(inflight, io.in.a.bits.source) node _T_1382 = bits(_T_1381, 0, 0) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1387 = and(io.in.d.valid, d_first_1) node _T_1388 = and(_T_1387, UInt<1>(0h1)) node _T_1389 = eq(d_release_ack, UInt<1>(0h0)) node _T_1390 = and(_T_1388, _T_1389) when _T_1390 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1391 = and(io.in.d.ready, io.in.d.valid) node _T_1392 = and(_T_1391, d_first_1) node _T_1393 = and(_T_1392, UInt<1>(0h1)) node _T_1394 = eq(d_release_ack, UInt<1>(0h0)) node _T_1395 = and(_T_1393, _T_1394) when _T_1395 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1396 = and(io.in.d.valid, d_first_1) node _T_1397 = and(_T_1396, UInt<1>(0h1)) node _T_1398 = eq(d_release_ack, UInt<1>(0h0)) node _T_1399 = and(_T_1397, _T_1398) when _T_1399 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1400 = dshr(inflight, io.in.d.bits.source) node _T_1401 = bits(_T_1400, 0, 0) node _T_1402 = or(_T_1401, same_cycle_resp) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1406 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1407 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1408 = or(_T_1406, _T_1407) node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(_T_1408, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1408, UInt<1>(0h1), "") : assert_100 node _T_1412 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_101 else : node _T_1416 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1417 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1418 = or(_T_1416, _T_1417) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_102 node _T_1422 = eq(io.in.d.bits.size, a_size_lookup) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_103 node _T_1426 = and(io.in.d.valid, d_first_1) node _T_1427 = and(_T_1426, a_first_1) node _T_1428 = and(_T_1427, io.in.a.valid) node _T_1429 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1430 = and(_T_1428, _T_1429) node _T_1431 = eq(d_release_ack, UInt<1>(0h0)) node _T_1432 = and(_T_1430, _T_1431) when _T_1432 : node _T_1433 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1434 = or(_T_1433, io.in.a.ready) node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(_T_1434, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1434, UInt<1>(0h1), "") : assert_104 node _T_1438 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1439 = orr(a_set_wo_ready) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) node _T_1441 = or(_T_1438, _T_1440) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_12 node _T_1445 = orr(inflight) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) node _T_1447 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1448 = or(_T_1446, _T_1447) node _T_1449 = lt(watchdog, plusarg_reader.out) node _T_1450 = or(_T_1448, _T_1449) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1454 = and(io.in.a.ready, io.in.a.valid) node _T_1455 = and(io.in.d.ready, io.in.d.valid) node _T_1456 = or(_T_1454, _T_1455) when _T_1456 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1457 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1458 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1459 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1460 = and(_T_1458, _T_1459) node _T_1461 = and(_T_1457, _T_1460) when _T_1461 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1462 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1463 = and(_T_1462, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1464 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1465 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1466 = and(_T_1464, _T_1465) node _T_1467 = and(_T_1463, _T_1466) when _T_1467 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1468 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1469 = bits(_T_1468, 0, 0) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1474 = and(io.in.d.valid, d_first_2) node _T_1475 = and(_T_1474, UInt<1>(0h1)) node _T_1476 = and(_T_1475, d_release_ack_1) when _T_1476 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1477 = and(io.in.d.ready, io.in.d.valid) node _T_1478 = and(_T_1477, d_first_2) node _T_1479 = and(_T_1478, UInt<1>(0h1)) node _T_1480 = and(_T_1479, d_release_ack_1) when _T_1480 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1481 = and(io.in.d.valid, d_first_2) node _T_1482 = and(_T_1481, UInt<1>(0h1)) node _T_1483 = and(_T_1482, d_release_ack_1) when _T_1483 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1484 = dshr(inflight_1, io.in.d.bits.source) node _T_1485 = bits(_T_1484, 0, 0) node _T_1486 = or(_T_1485, same_cycle_resp_1) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1490 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(_T_1490, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1490, UInt<1>(0h1), "") : assert_109 else : node _T_1494 = eq(io.in.d.bits.size, c_size_lookup) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_110 node _T_1498 = and(io.in.d.valid, d_first_2) node _T_1499 = and(_T_1498, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1500 = and(_T_1499, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1501 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1502 = and(_T_1500, _T_1501) node _T_1503 = and(_T_1502, d_release_ack_1) node _T_1504 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1505 = and(_T_1503, _T_1504) when _T_1505 : node _T_1506 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1507 = or(_T_1506, _WIRE_27.ready) node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(_T_1507, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1507, UInt<1>(0h1), "") : assert_111 node _T_1511 = orr(c_set_wo_ready) when _T_1511 : node _T_1512 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_13 node _T_1516 = orr(inflight_1) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) node _T_1518 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1519 = or(_T_1517, _T_1518) node _T_1520 = lt(watchdog_1, plusarg_reader_1.out) node _T_1521 = or(_T_1519, _T_1520) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1525 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1526 = and(io.in.d.ready, io.in.d.valid) node _T_1527 = or(_T_1525, _T_1526) when _T_1527 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1454 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1454; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1454; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1527 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1527; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1527; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1527; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1380 = _T_1454 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1380 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1380 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1380 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1380 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1380 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1426 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1426 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1395 = _T_1527 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1395 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1395 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1395 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1498 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1498 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1480 = _T_1527 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1480 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1480 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1480 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_139 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_154 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_139( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_154 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module LatencyInjectionQueue_1 : input clock : Clock input reset : Reset output io : { flip latency_cycles : UInt<64>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst queue of Queue8_TLBundleD_a32d256s2k3z4u connect queue.clock, clock connect queue.reset, reset inst release_ready_cycle_q of Queue8_UInt64_1 connect release_ready_cycle_q.clock, clock connect release_ready_cycle_q.reset, reset node _release_ready_cycle_q_io_enq_bits_T = add(cur_cycle, io.latency_cycles) node _release_ready_cycle_q_io_enq_bits_T_1 = tail(_release_ready_cycle_q_io_enq_bits_T, 1) connect release_ready_cycle_q.io.enq.bits, _release_ready_cycle_q_io_enq_bits_T_1 connect queue.io.enq.bits.corrupt, io.enq.bits.corrupt connect queue.io.enq.bits.data, io.enq.bits.data connect queue.io.enq.bits.denied, io.enq.bits.denied connect queue.io.enq.bits.sink, io.enq.bits.sink connect queue.io.enq.bits.source, io.enq.bits.source connect queue.io.enq.bits.size, io.enq.bits.size connect queue.io.enq.bits.param, io.enq.bits.param connect queue.io.enq.bits.opcode, io.enq.bits.opcode connect io.deq.bits, queue.io.deq.bits node _queue_io_enq_valid_T = and(release_ready_cycle_q.io.enq.ready, io.enq.valid) connect queue.io.enq.valid, _queue_io_enq_valid_T node _release_ready_cycle_q_io_enq_valid_T = and(queue.io.enq.ready, io.enq.valid) connect release_ready_cycle_q.io.enq.valid, _release_ready_cycle_q_io_enq_valid_T node _io_enq_ready_T = and(queue.io.enq.ready, release_ready_cycle_q.io.enq.ready) connect io.enq.ready, _io_enq_ready_T node _T = leq(release_ready_cycle_q.io.deq.bits, cur_cycle) node _queue_io_deq_ready_T = and(release_ready_cycle_q.io.deq.valid, _T) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, io.deq.ready) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _release_ready_cycle_q_io_deq_ready_T = and(queue.io.deq.valid, _T) node _release_ready_cycle_q_io_deq_ready_T_1 = and(_release_ready_cycle_q_io_deq_ready_T, io.deq.ready) connect release_ready_cycle_q.io.deq.ready, _release_ready_cycle_q_io_deq_ready_T_1 node _io_deq_valid_T = and(queue.io.deq.valid, release_ready_cycle_q.io.deq.valid) node _io_deq_valid_T_1 = and(_io_deq_valid_T, _T) connect io.deq.valid, _io_deq_valid_T_1

module LatencyInjectionQueue_1( // @[LatencyInjectionQueue.scala:9:7] input clock, // @[LatencyInjectionQueue.scala:9:7] input reset, // @[LatencyInjectionQueue.scala:9:7] input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14] output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14] input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14] input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14] input [1:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14] input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14] input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14] output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14] output [1:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14] output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14] ); wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37] wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37] wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37] wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21] wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21] wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7] wire _io_enq_ready_T; // @[Misc.scala:26:53] wire _io_deq_valid_T_1; // @[Misc.scala:26:53] wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26] wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26] wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26] wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50] wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50] wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53] assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53] wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39] wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53] always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7] if (reset) // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26] else // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26] always @(posedge) Queue8_TLBundleD_a32d256s2k3z4u queue ( // @[LatencyInjectionQueue.scala:18:21] .clock (clock), .reset (reset), .io_enq_ready (_queue_io_enq_ready), .io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7] .io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits_opcode (io_deq_bits_opcode), .io_deq_bits_param (io_deq_bits_param), .io_deq_bits_size (io_deq_bits_size), .io_deq_bits_source (io_deq_bits_source_0), .io_deq_bits_sink (io_deq_bits_sink), .io_deq_bits_denied (io_deq_bits_denied), .io_deq_bits_data (io_deq_bits_data_0), .io_deq_bits_corrupt (io_deq_bits_corrupt) ); // @[LatencyInjectionQueue.scala:18:21] Queue8_UInt64_1 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37] .clock (clock), .reset (reset), .io_enq_ready (_release_ready_cycle_q_io_enq_ready), .io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50] .io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_release_ready_cycle_q_io_deq_valid), .io_deq_bits (_release_ready_cycle_q_io_deq_bits) ); // @[LatencyInjectionQueue.scala:19:37] assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_95 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_valid, slot_uop.iw_issued) when _T_40 : connect next_valid, rebusied

module IssueSlot_95( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]

Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_15 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} [16] wire _valids_WIRE : UInt<1>[16] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) connect _valids_WIRE[15], UInt<1>(0h0) regreset valids : UInt<1>[16], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = and(valids[3], _valids_3_T_2) node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0)) node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5) connect valids[3], _valids_3_T_6 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = and(valids[4], _valids_4_T_2) node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0)) node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5) connect valids[4], _valids_4_T_6 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = and(valids[5], _valids_5_T_2) node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0)) node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5) connect valids[5], _valids_5_T_6 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = and(valids[6], _valids_6_T_2) node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0)) node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5) connect valids[6], _valids_6_T_6 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = and(valids[7], _valids_7_T_2) node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0)) node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5) connect valids[7], _valids_7_T_6 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = and(valids[8], _valids_8_T_2) node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0)) node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5) connect valids[8], _valids_8_T_6 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = and(valids[9], _valids_9_T_2) node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0)) node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5) connect valids[9], _valids_9_T_6 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = and(valids[10], _valids_10_T_2) node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0)) node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5) connect valids[10], _valids_10_T_6 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = and(valids[11], _valids_11_T_2) node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0)) node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5) connect valids[11], _valids_11_T_6 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = and(valids[12], _valids_12_T_2) node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0)) node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5) connect valids[12], _valids_12_T_6 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = and(valids[13], _valids_13_T_2) node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0)) node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5) connect valids[13], _valids_13_T_6 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = and(valids[14], _valids_14_T_2) node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0)) node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5) connect valids[14], _valids_14_T_6 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask) node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0)) node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0)) node _valids_15_T_3 = and(valids[15], _valids_15_T_2) node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq) node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0)) node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5) connect valids[15], _valids_15_T_6 when valids[15] : node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T) connect uops[15].br_mask, _uops_15_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0hf)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = cat(_io_count_T, ptr_diff) connect io.count, _io_count_T_1

module BranchKillableQueue_15( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [33:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [1:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [33:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [3:0] out_uop_br_mask; // @[util.scala:506:17] wire [130:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire _valids_0_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_0_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_1_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_1_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_2_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_2_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_3_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_3_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_4_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_4_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_5_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_5_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_6_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_6_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_7_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_7_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_8_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_8_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_9_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_9_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_10_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_10_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_11_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_11_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_12_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_12_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_13_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_13_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_14_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_14_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_15_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_15_T_5 = 1'h1; // @[util.scala:481:72] wire _io_deq_valid_T_4 = 1'h1; // @[util.scala:509:68] wire _io_deq_valid_T_7 = 1'h1; // @[util.scala:509:111] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_15_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _io_deq_bits_uop_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[util.scala:448:7, :453:14] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:448:7, :453:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:448:7, :453:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:448:7, :453:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_valid = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:448:7] wire io_flush = 1'h0; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _valids_0_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_0_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_1_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_1_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_2_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_2_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_3_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_3_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_4_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_4_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_5_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_5_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_6_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_6_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_7_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_7_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_8_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_8_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_9_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_9_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_10_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_10_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_11_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_11_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_12_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_12_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_13_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_13_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_14_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_14_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_15_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_15_T_4 = 1'h0; // @[util.scala:481:83] wire _io_deq_valid_T_3 = 1'h0; // @[util.scala:118:59] wire _io_deq_valid_T_6 = 1'h0; // @[util.scala:509:122] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[util.scala:448:7, :453:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:448:7] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_15_T = 4'h0; // @[util.scala:118:51] wire _io_enq_ready_T; // @[util.scala:504:19] wire [3:0] _io_deq_valid_T_2 = 4'h0; // @[util.scala:118:51] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:85:25, :448:7] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [33:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [3:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [1:0] out_uop_br_tag; // @[util.scala:506:17] wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [5:0] out_uop_rob_idx; // @[util.scala:506:17] wire [3:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [3:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [3:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [33:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [21:0] out_old_meta_tag; // @[util.scala:506:17] wire [1:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] wire _valids_0_T_3 = valids_0; // @[util.scala:465:24, :481:29] reg valids_1; // @[util.scala:465:24] wire _valids_1_T_3 = valids_1; // @[util.scala:465:24, :481:29] reg valids_2; // @[util.scala:465:24] wire _valids_2_T_3 = valids_2; // @[util.scala:465:24, :481:29] reg valids_3; // @[util.scala:465:24] wire _valids_3_T_3 = valids_3; // @[util.scala:465:24, :481:29] reg valids_4; // @[util.scala:465:24] wire _valids_4_T_3 = valids_4; // @[util.scala:465:24, :481:29] reg valids_5; // @[util.scala:465:24] wire _valids_5_T_3 = valids_5; // @[util.scala:465:24, :481:29] reg valids_6; // @[util.scala:465:24] wire _valids_6_T_3 = valids_6; // @[util.scala:465:24, :481:29] reg valids_7; // @[util.scala:465:24] wire _valids_7_T_3 = valids_7; // @[util.scala:465:24, :481:29] reg valids_8; // @[util.scala:465:24] wire _valids_8_T_3 = valids_8; // @[util.scala:465:24, :481:29] reg valids_9; // @[util.scala:465:24] wire _valids_9_T_3 = valids_9; // @[util.scala:465:24, :481:29] reg valids_10; // @[util.scala:465:24] wire _valids_10_T_3 = valids_10; // @[util.scala:465:24, :481:29] reg valids_11; // @[util.scala:465:24] wire _valids_11_T_3 = valids_11; // @[util.scala:465:24, :481:29] reg valids_12; // @[util.scala:465:24] wire _valids_12_T_3 = valids_12; // @[util.scala:465:24, :481:29] reg valids_13; // @[util.scala:465:24] wire _valids_13_T_3 = valids_13; // @[util.scala:465:24, :481:29] reg valids_14; // @[util.scala:465:24] wire _valids_14_T_3 = valids_14; // @[util.scala:465:24, :481:29] reg valids_15; // @[util.scala:465:24] wire _valids_15_T_3 = valids_15; // @[util.scala:465:24, :481:29] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [33:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [3:0] uops_0_br_mask; // @[util.scala:466:20] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_0_br_tag; // @[util.scala:466:20] reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [5:0] uops_0_rob_idx; // @[util.scala:466:20] reg [3:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [3:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [33:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [3:0] uops_1_br_mask; // @[util.scala:466:20] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_1_br_tag; // @[util.scala:466:20] reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [5:0] uops_1_rob_idx; // @[util.scala:466:20] reg [3:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [3:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [33:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [3:0] uops_2_br_mask; // @[util.scala:466:20] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_2_br_tag; // @[util.scala:466:20] reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [5:0] uops_2_rob_idx; // @[util.scala:466:20] reg [3:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [3:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [33:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [3:0] uops_3_br_mask; // @[util.scala:466:20] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_3_br_tag; // @[util.scala:466:20] reg [3:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [5:0] uops_3_rob_idx; // @[util.scala:466:20] reg [3:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [3:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [33:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [3:0] uops_4_br_mask; // @[util.scala:466:20] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_4_br_tag; // @[util.scala:466:20] reg [3:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [5:0] uops_4_rob_idx; // @[util.scala:466:20] reg [3:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [3:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [33:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [3:0] uops_5_br_mask; // @[util.scala:466:20] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_5_br_tag; // @[util.scala:466:20] reg [3:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [5:0] uops_5_rob_idx; // @[util.scala:466:20] reg [3:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [3:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [33:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [3:0] uops_6_br_mask; // @[util.scala:466:20] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_6_br_tag; // @[util.scala:466:20] reg [3:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [5:0] uops_6_rob_idx; // @[util.scala:466:20] reg [3:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [3:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [33:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [3:0] uops_7_br_mask; // @[util.scala:466:20] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_7_br_tag; // @[util.scala:466:20] reg [3:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [5:0] uops_7_rob_idx; // @[util.scala:466:20] reg [3:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [3:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [33:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [3:0] uops_8_br_mask; // @[util.scala:466:20] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_8_br_tag; // @[util.scala:466:20] reg [3:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [5:0] uops_8_rob_idx; // @[util.scala:466:20] reg [3:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [3:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [33:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [3:0] uops_9_br_mask; // @[util.scala:466:20] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_9_br_tag; // @[util.scala:466:20] reg [3:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [5:0] uops_9_rob_idx; // @[util.scala:466:20] reg [3:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [3:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [33:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [3:0] uops_10_br_mask; // @[util.scala:466:20] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_10_br_tag; // @[util.scala:466:20] reg [3:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [5:0] uops_10_rob_idx; // @[util.scala:466:20] reg [3:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [3:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [33:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [3:0] uops_11_br_mask; // @[util.scala:466:20] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_11_br_tag; // @[util.scala:466:20] reg [3:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [5:0] uops_11_rob_idx; // @[util.scala:466:20] reg [3:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [3:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [33:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [3:0] uops_12_br_mask; // @[util.scala:466:20] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_12_br_tag; // @[util.scala:466:20] reg [3:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [5:0] uops_12_rob_idx; // @[util.scala:466:20] reg [3:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [3:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [33:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [3:0] uops_13_br_mask; // @[util.scala:466:20] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_13_br_tag; // @[util.scala:466:20] reg [3:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [5:0] uops_13_rob_idx; // @[util.scala:466:20] reg [3:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [3:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [33:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [3:0] uops_14_br_mask; // @[util.scala:466:20] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_14_br_tag; // @[util.scala:466:20] reg [3:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [5:0] uops_14_rob_idx; // @[util.scala:466:20] reg [3:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [3:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [33:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [3:0] uops_15_br_mask; // @[util.scala:466:20] wire [3:0] _uops_15_br_mask_T_1 = uops_15_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_15_br_tag; // @[util.scala:466:20] reg [3:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [5:0] uops_15_rob_idx; // @[util.scala:466:20] reg [3:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [3:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire _valids_0_T_6 = _valids_0_T_3; // @[util.scala:481:{29,69}] wire _valids_1_T_6 = _valids_1_T_3; // @[util.scala:481:{29,69}] wire _valids_2_T_6 = _valids_2_T_3; // @[util.scala:481:{29,69}] wire _valids_3_T_6 = _valids_3_T_3; // @[util.scala:481:{29,69}] wire _valids_4_T_6 = _valids_4_T_3; // @[util.scala:481:{29,69}] wire _valids_5_T_6 = _valids_5_T_3; // @[util.scala:481:{29,69}] wire _valids_6_T_6 = _valids_6_T_3; // @[util.scala:481:{29,69}] wire _valids_7_T_6 = _valids_7_T_3; // @[util.scala:481:{29,69}] wire _valids_8_T_6 = _valids_8_T_3; // @[util.scala:481:{29,69}] wire _valids_9_T_6 = _valids_9_T_3; // @[util.scala:481:{29,69}] wire _valids_10_T_6 = _valids_10_T_3; // @[util.scala:481:{29,69}] wire _valids_11_T_6 = _valids_11_T_3; // @[util.scala:481:{29,69}] wire _valids_12_T_6 = _valids_12_T_3; // @[util.scala:481:{29,69}] wire _valids_13_T_6 = _valids_13_T_3; // @[util.scala:481:{29,69}] wire _valids_14_T_6 = _valids_14_T_3; // @[util.scala:481:{29,69}] wire _valids_15_T_6 = _valids_15_T_3; // @[util.scala:481:{29,69}] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask; // @[util.scala:85:25, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire _io_deq_valid_T_5 = _io_deq_valid_T_1; // @[util.scala:509:{40,65}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5; // @[util.scala:509:{65,108}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x131 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_9 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<18>(0h20000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<18>(0h21000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<18>(0h22000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<18>(0h23000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<18>(0h24000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<17>(0h10000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) node _legal_address_T_60 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_61 = cvt(_legal_address_T_60) node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000))) node _legal_address_T_63 = asSInt(_legal_address_T_62) node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0))) node _legal_address_T_65 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_66 = cvt(_legal_address_T_65) node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<17>(0h10000))) node _legal_address_T_68 = asSInt(_legal_address_T_67) node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0))) node _legal_address_T_70 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_71 = cvt(_legal_address_T_70) node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<27>(0h4000000))) node _legal_address_T_73 = asSInt(_legal_address_T_72) node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0))) node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_76 = cvt(_legal_address_T_75) node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000))) node _legal_address_T_78 = asSInt(_legal_address_T_77) node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0))) node _legal_address_T_80 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_81 = cvt(_legal_address_T_80) node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<29>(0h10000000))) node _legal_address_T_83 = asSInt(_legal_address_T_82) node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[17] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 connect _legal_address_WIRE[12], _legal_address_T_64 connect _legal_address_WIRE[13], _legal_address_T_69 connect _legal_address_WIRE[14], _legal_address_T_74 connect _legal_address_WIRE[15], _legal_address_T_79 connect _legal_address_WIRE[16], _legal_address_T_84 node _legal_address_T_85 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_86 = or(_legal_address_T_85, _legal_address_WIRE[2]) node _legal_address_T_87 = or(_legal_address_T_86, _legal_address_WIRE[3]) node _legal_address_T_88 = or(_legal_address_T_87, _legal_address_WIRE[4]) node _legal_address_T_89 = or(_legal_address_T_88, _legal_address_WIRE[5]) node _legal_address_T_90 = or(_legal_address_T_89, _legal_address_WIRE[6]) node _legal_address_T_91 = or(_legal_address_T_90, _legal_address_WIRE[7]) node _legal_address_T_92 = or(_legal_address_T_91, _legal_address_WIRE[8]) node _legal_address_T_93 = or(_legal_address_T_92, _legal_address_WIRE[9]) node _legal_address_T_94 = or(_legal_address_T_93, _legal_address_WIRE[10]) node _legal_address_T_95 = or(_legal_address_T_94, _legal_address_WIRE[11]) node _legal_address_T_96 = or(_legal_address_T_95, _legal_address_WIRE[12]) node _legal_address_T_97 = or(_legal_address_T_96, _legal_address_WIRE[13]) node _legal_address_T_98 = or(_legal_address_T_97, _legal_address_WIRE[14]) node _legal_address_T_99 = or(_legal_address_T_98, _legal_address_WIRE[15]) node legal_address = or(_legal_address_T_99, _legal_address_WIRE[16]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c020000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c031000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<18>(0h20000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c030000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_16 = cvt(_io_resp_cacheable_T_15) node _io_resp_cacheable_T_17 = and(_io_resp_cacheable_T_16, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_18 = asSInt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = eq(_io_resp_cacheable_T_18, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_20 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_21 = or(_io_resp_cacheable_T_20, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_22 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_19) node _io_resp_cacheable_T_23 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_24 = cvt(_io_resp_cacheable_T_23) node _io_resp_cacheable_T_25 = and(_io_resp_cacheable_T_24, asSInt(UInt<33>(0h8c030000))) node _io_resp_cacheable_T_26 = asSInt(_io_resp_cacheable_T_25) node _io_resp_cacheable_T_27 = eq(_io_resp_cacheable_T_26, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_28 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_29 = cvt(_io_resp_cacheable_T_28) node _io_resp_cacheable_T_30 = and(_io_resp_cacheable_T_29, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_31 = asSInt(_io_resp_cacheable_T_30) node _io_resp_cacheable_T_32 = eq(_io_resp_cacheable_T_31, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_33 = or(_io_resp_cacheable_T_27, _io_resp_cacheable_T_32) node _io_resp_cacheable_T_34 = mux(_io_resp_cacheable_T_22, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_35 = mux(_io_resp_cacheable_T_33, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_36 = or(_io_resp_cacheable_T_34, _io_resp_cacheable_T_35) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_36 node _io_resp_cacheable_T_37 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_37 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_36 = cvt(_io_resp_w_T_35) node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37) node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0))) node _io_resp_w_T_40 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_41 = or(_io_resp_w_T_40, _io_resp_w_T_14) node _io_resp_w_T_42 = or(_io_resp_w_T_41, _io_resp_w_T_19) node _io_resp_w_T_43 = or(_io_resp_w_T_42, _io_resp_w_T_24) node _io_resp_w_T_44 = or(_io_resp_w_T_43, _io_resp_w_T_29) node _io_resp_w_T_45 = or(_io_resp_w_T_44, _io_resp_w_T_34) node _io_resp_w_T_46 = or(_io_resp_w_T_45, _io_resp_w_T_39) node _io_resp_w_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_48 = cvt(_io_resp_w_T_47) node _io_resp_w_T_49 = and(_io_resp_w_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_w_T_50 = asSInt(_io_resp_w_T_49) node _io_resp_w_T_51 = eq(_io_resp_w_T_50, asSInt(UInt<1>(0h0))) node _io_resp_w_T_52 = mux(_io_resp_w_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_53 = mux(_io_resp_w_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_54 = or(_io_resp_w_T_52, _io_resp_w_T_53) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_54 node _io_resp_w_T_55 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_55 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35) node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37) node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_40 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_41 = or(_io_resp_pp_T_40, _io_resp_pp_T_14) node _io_resp_pp_T_42 = or(_io_resp_pp_T_41, _io_resp_pp_T_19) node _io_resp_pp_T_43 = or(_io_resp_pp_T_42, _io_resp_pp_T_24) node _io_resp_pp_T_44 = or(_io_resp_pp_T_43, _io_resp_pp_T_29) node _io_resp_pp_T_45 = or(_io_resp_pp_T_44, _io_resp_pp_T_34) node _io_resp_pp_T_46 = or(_io_resp_pp_T_45, _io_resp_pp_T_39) node _io_resp_pp_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_48 = cvt(_io_resp_pp_T_47) node _io_resp_pp_T_49 = and(_io_resp_pp_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_pp_T_50 = asSInt(_io_resp_pp_T_49) node _io_resp_pp_T_51 = eq(_io_resp_pp_T_50, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_52 = mux(_io_resp_pp_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_53 = mux(_io_resp_pp_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_54 = or(_io_resp_pp_T_52, _io_resp_pp_T_53) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_54 node _io_resp_pp_T_55 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_55 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_36 = cvt(_io_resp_al_T_35) node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37) node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0))) node _io_resp_al_T_40 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_41 = or(_io_resp_al_T_40, _io_resp_al_T_14) node _io_resp_al_T_42 = or(_io_resp_al_T_41, _io_resp_al_T_19) node _io_resp_al_T_43 = or(_io_resp_al_T_42, _io_resp_al_T_24) node _io_resp_al_T_44 = or(_io_resp_al_T_43, _io_resp_al_T_29) node _io_resp_al_T_45 = or(_io_resp_al_T_44, _io_resp_al_T_34) node _io_resp_al_T_46 = or(_io_resp_al_T_45, _io_resp_al_T_39) node _io_resp_al_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_48 = cvt(_io_resp_al_T_47) node _io_resp_al_T_49 = and(_io_resp_al_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_al_T_50 = asSInt(_io_resp_al_T_49) node _io_resp_al_T_51 = eq(_io_resp_al_T_50, asSInt(UInt<1>(0h0))) node _io_resp_al_T_52 = mux(_io_resp_al_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_53 = mux(_io_resp_al_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_54 = or(_io_resp_al_T_52, _io_resp_al_T_53) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_54 node _io_resp_al_T_55 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_55 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0hfffd8000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hfffe9000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hffff9000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hffff0000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0hffff9000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35) node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf0000000))) node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37) node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_40 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_41 = or(_io_resp_aa_T_40, _io_resp_aa_T_14) node _io_resp_aa_T_42 = or(_io_resp_aa_T_41, _io_resp_aa_T_19) node _io_resp_aa_T_43 = or(_io_resp_aa_T_42, _io_resp_aa_T_24) node _io_resp_aa_T_44 = or(_io_resp_aa_T_43, _io_resp_aa_T_29) node _io_resp_aa_T_45 = or(_io_resp_aa_T_44, _io_resp_aa_T_34) node _io_resp_aa_T_46 = or(_io_resp_aa_T_45, _io_resp_aa_T_39) node _io_resp_aa_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_48 = cvt(_io_resp_aa_T_47) node _io_resp_aa_T_49 = and(_io_resp_aa_T_48, asSInt(UInt<33>(0hffff0000))) node _io_resp_aa_T_50 = asSInt(_io_resp_aa_T_49) node _io_resp_aa_T_51 = eq(_io_resp_aa_T_50, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_52 = mux(_io_resp_aa_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_53 = mux(_io_resp_aa_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_54 = or(_io_resp_aa_T_52, _io_resp_aa_T_53) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_54 node _io_resp_aa_T_55 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_55 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0hffff0000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0hffff0000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0hf0000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<18>(0h20000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0hffffc000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<18>(0h24000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0hfffef000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0hffff0000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_60 = cvt(_io_resp_x_T_59) node _io_resp_x_T_61 = and(_io_resp_x_T_60, asSInt(UInt<33>(0hfc000000))) node _io_resp_x_T_62 = asSInt(_io_resp_x_T_61) node _io_resp_x_T_63 = eq(_io_resp_x_T_62, asSInt(UInt<1>(0h0))) node _io_resp_x_T_64 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_x_T_65 = cvt(_io_resp_x_T_64) node _io_resp_x_T_66 = and(_io_resp_x_T_65, asSInt(UInt<33>(0hfffff000))) node _io_resp_x_T_67 = asSInt(_io_resp_x_T_66) node _io_resp_x_T_68 = eq(_io_resp_x_T_67, asSInt(UInt<1>(0h0))) node _io_resp_x_T_69 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_70 = or(_io_resp_x_T_69, _io_resp_x_T_43) node _io_resp_x_T_71 = or(_io_resp_x_T_70, _io_resp_x_T_48) node _io_resp_x_T_72 = or(_io_resp_x_T_71, _io_resp_x_T_53) node _io_resp_x_T_73 = or(_io_resp_x_T_72, _io_resp_x_T_58) node _io_resp_x_T_74 = or(_io_resp_x_T_73, _io_resp_x_T_63) node _io_resp_x_T_75 = or(_io_resp_x_T_74, _io_resp_x_T_68) node _io_resp_x_T_76 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_77 = mux(_io_resp_x_T_75, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_78 = or(_io_resp_x_T_76, _io_resp_x_T_77) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_78 node _io_resp_x_T_79 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_79 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hffffa000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<18>(0h20000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hffff8000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hfffeb000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hffff0000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hffffb000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfc000000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10020000)) node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30) node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hffffb000))) node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32) node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14) node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19) node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24) node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29) node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34) node _io_resp_eff_T_41 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41) node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hffffb000))) node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43) node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46) node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hffff0000))) node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48) node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_51 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51) node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hffff0000))) node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53) node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_56 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_57 = cvt(_io_resp_eff_T_56) node _io_resp_eff_T_58 = and(_io_resp_eff_T_57, asSInt(UInt<33>(0hf0000000))) node _io_resp_eff_T_59 = asSInt(_io_resp_eff_T_58) node _io_resp_eff_T_60 = eq(_io_resp_eff_T_59, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_61 = or(_io_resp_eff_T_45, _io_resp_eff_T_50) node _io_resp_eff_T_62 = or(_io_resp_eff_T_61, _io_resp_eff_T_55) node _io_resp_eff_T_63 = or(_io_resp_eff_T_62, _io_resp_eff_T_60) node _io_resp_eff_T_64 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_65 = mux(_io_resp_eff_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_66 = or(_io_resp_eff_T_64, _io_resp_eff_T_65) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_66 node _io_resp_eff_T_67 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_67

module PMAChecker_9( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_37; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_55; // @[PMA.scala:39:19] wire _io_resp_pp_T_55; // @[PMA.scala:39:19] wire _io_resp_al_T_55; // @[PMA.scala:39:19] wire _io_resp_aa_T_55; // @[PMA.scala:39:19] wire _io_resp_x_T_79; // @[PMA.scala:39:19] wire _io_resp_eff_T_67; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31] assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_47; // @[Parameters.scala:137:31] assign _io_resp_w_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_47; // @[Parameters.scala:137:31] assign _io_resp_pp_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_47; // @[Parameters.scala:137:31] assign _io_resp_al_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_47; // @[Parameters.scala:137:31] assign _io_resp_aa_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31] assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h20000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h21000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_30 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h22000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_35 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h23000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h24000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31] assign _legal_address_T_60 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46] wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_65; // @[Parameters.scala:137:31] assign _legal_address_T_65 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_23; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_23 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31] assign _io_resp_eff_T_51 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46] wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40] wire [39:0] _GEN_8 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_70; // @[Parameters.scala:137:31] assign _legal_address_T_70 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_15; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_15 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31] assign _io_resp_x_T_59 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46] wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40] wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_75; // @[Parameters.scala:137:31] assign _legal_address_T_75 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_64; // @[Parameters.scala:137:31] assign _io_resp_x_T_64 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31] assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46] wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40] wire [39:0] _GEN_10 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31] assign _legal_address_T_80 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_28; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_28 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31] assign _io_resp_w_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31] assign _io_resp_pp_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31] assign _io_resp_al_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31] assign _io_resp_aa_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31] assign _io_resp_eff_T_56 = _GEN_10; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46] wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40] wire _legal_address_T_85 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_86 = _legal_address_T_85 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_87 = _legal_address_T_86 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_88 = _legal_address_T_87 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_89 = _legal_address_T_88 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_90 = _legal_address_T_89 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_91 = _legal_address_T_90 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_92 = _legal_address_T_91 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_93 = _legal_address_T_92 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_94 = _legal_address_T_93 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire _legal_address_T_95 = _legal_address_T_94 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire _legal_address_T_96 = _legal_address_T_95 | _legal_address_WIRE_12; // @[Parameters.scala:612:40] wire _legal_address_T_97 = _legal_address_T_96 | _legal_address_WIRE_13; // @[Parameters.scala:612:40] wire _legal_address_T_98 = _legal_address_T_97 | _legal_address_WIRE_14; // @[Parameters.scala:612:40] wire _legal_address_T_99 = _legal_address_T_98 | _legal_address_WIRE_15; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_99 | _legal_address_WIRE_16; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C020000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C031000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_16 = {1'h0, _io_resp_cacheable_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_17 = _io_resp_cacheable_T_16 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_22 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_19; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_24 = {1'h0, _io_resp_cacheable_T_23}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_26 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_29 = {1'h0, _io_resp_cacheable_T_28}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_31 = _io_resp_cacheable_T_30; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_32 = _io_resp_cacheable_T_31 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_33 = _io_resp_cacheable_T_27 | _io_resp_cacheable_T_32; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_35 = _io_resp_cacheable_T_33; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_36 = _io_resp_cacheable_T_35; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_36; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_37 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_37; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46] wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_40 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_41 = _io_resp_w_T_40 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_42 = _io_resp_w_T_41 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_43 = _io_resp_w_T_42 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_44 = _io_resp_w_T_43 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_45 = _io_resp_w_T_44 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_45 | _io_resp_w_T_39; // @[Parameters.scala:629:89] wire _io_resp_w_T_52 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_48 = {1'h0, _io_resp_w_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_49 = _io_resp_w_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_50 = _io_resp_w_T_49; // @[Parameters.scala:137:46] wire _io_resp_w_T_51 = _io_resp_w_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_54 = _io_resp_w_T_52; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_54; // @[Mux.scala:30:73] assign _io_resp_w_T_55 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_40 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_41 = _io_resp_pp_T_40 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_42 = _io_resp_pp_T_41 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_43 = _io_resp_pp_T_42 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_44 = _io_resp_pp_T_43 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_45 | _io_resp_pp_T_39; // @[Parameters.scala:629:89] wire _io_resp_pp_T_52 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_48 = {1'h0, _io_resp_pp_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_49 = _io_resp_pp_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_50 = _io_resp_pp_T_49; // @[Parameters.scala:137:46] wire _io_resp_pp_T_51 = _io_resp_pp_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_54 = _io_resp_pp_T_52; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_54; // @[Mux.scala:30:73] assign _io_resp_pp_T_55 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46] wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_40 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_41 = _io_resp_al_T_40 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_42 = _io_resp_al_T_41 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_43 = _io_resp_al_T_42 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_44 = _io_resp_al_T_43 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_45 = _io_resp_al_T_44 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_45 | _io_resp_al_T_39; // @[Parameters.scala:629:89] wire _io_resp_al_T_52 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_48 = {1'h0, _io_resp_al_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_49 = _io_resp_al_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_50 = _io_resp_al_T_49; // @[Parameters.scala:137:46] wire _io_resp_al_T_51 = _io_resp_al_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_54 = _io_resp_al_T_52; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_54; // @[Mux.scala:30:73] assign _io_resp_al_T_55 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_40 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_41 = _io_resp_aa_T_40 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_42 = _io_resp_aa_T_41 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_43 = _io_resp_aa_T_42 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_44 = _io_resp_aa_T_43 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_45 | _io_resp_aa_T_39; // @[Parameters.scala:629:89] wire _io_resp_aa_T_52 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_48 = {1'h0, _io_resp_aa_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_49 = _io_resp_aa_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_50 = _io_resp_aa_T_49; // @[Parameters.scala:137:46] wire _io_resp_aa_T_51 = _io_resp_aa_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_54 = _io_resp_aa_T_52; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_54; // @[Mux.scala:30:73] assign _io_resp_aa_T_55 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_76 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFFC000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46] wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_65 = {1'h0, _io_resp_x_T_64}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_66 = _io_resp_x_T_65 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_67 = _io_resp_x_T_66; // @[Parameters.scala:137:46] wire _io_resp_x_T_68 = _io_resp_x_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_69 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_70 = _io_resp_x_T_69 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_71 = _io_resp_x_T_70 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_72 = _io_resp_x_T_71 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_73 = _io_resp_x_T_72 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_74 = _io_resp_x_T_73 | _io_resp_x_T_63; // @[Parameters.scala:629:89] wire _io_resp_x_T_75 = _io_resp_x_T_74 | _io_resp_x_T_68; // @[Parameters.scala:629:89] wire _io_resp_x_T_78 = _io_resp_x_T_76; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_78; // @[Mux.scala:30:73] assign _io_resp_x_T_79 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_79; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_35 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_36 = _io_resp_eff_T_35 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_37 = _io_resp_eff_T_36 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_38 = _io_resp_eff_T_37 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_40 = _io_resp_eff_T_39 | _io_resp_eff_T_34; // @[Parameters.scala:629:89] wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46] wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46] wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46] wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46] wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_61 = _io_resp_eff_T_45 | _io_resp_eff_T_50; // @[Parameters.scala:629:89] wire _io_resp_eff_T_62 = _io_resp_eff_T_61 | _io_resp_eff_T_55; // @[Parameters.scala:629:89] wire _io_resp_eff_T_63 = _io_resp_eff_T_62 | _io_resp_eff_T_60; // @[Parameters.scala:629:89] wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73] assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_11 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_22 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_23 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_11( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_207 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_207( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module FlitToPhit_f32_p32_9 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}} reg data : UInt<32>[0], clock regreset beat : UInt<0>, clock, reset, UInt<0>(0h0) node _io_in_ready_T = eq(beat, UInt<1>(0h0)) node _io_in_ready_T_1 = and(io.out.ready, _io_in_ready_T) connect io.in.ready, _io_in_ready_T_1 node _io_out_valid_T = neq(beat, UInt<1>(0h0)) node _io_out_valid_T_1 = or(io.in.valid, _io_out_valid_T) connect io.out.valid, _io_out_valid_T_1 connect io.out.bits.phit, io.in.bits.flit node _T = and(io.out.ready, io.out.valid) when _T : node _beat_T = eq(beat, UInt<1>(0h0)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = eq(beat, UInt<1>(0h0)) when _T_1 : wire _WIRE : UInt<32>[1] wire _WIRE_1 : UInt<32> connect _WIRE_1, io.in.bits.flit node _T_2 = bits(_WIRE_1, 31, 0) connect _WIRE[0], _T_2

module FlitToPhit_f32_p32_9( // @[Serdes.scala:71:7] input clock, // @[Serdes.scala:71:7] input reset, // @[Serdes.scala:71:7] output io_in_ready, // @[Serdes.scala:73:14] input io_in_valid, // @[Serdes.scala:73:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:73:14] input io_out_ready, // @[Serdes.scala:73:14] output io_out_valid, // @[Serdes.scala:73:14] output [31:0] io_out_bits_phit // @[Serdes.scala:73:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:71:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:71:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:71:7] wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T = 1'h1; // @[Serdes.scala:83:39] wire _beat_T = 1'h1; // @[Serdes.scala:88:22] wire _beat_T_2 = 1'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T_1; // @[Serdes.scala:83:31] wire _io_out_valid_T = 1'h0; // @[Serdes.scala:84:39] wire _beat_T_3 = 1'h0; // @[Serdes.scala:88:16] wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:71:7, :84:31] wire [31:0] io_out_bits_phit_0 = io_in_bits_flit_0; // @[Serdes.scala:71:7] assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:71:7, :83:31] wire io_in_ready_0; // @[Serdes.scala:71:7] wire io_out_valid_0; // @[Serdes.scala:71:7] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:71:7, :83:31] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:71:7, :84:31] assign io_in_ready = io_in_ready_0; // @[Serdes.scala:71:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:71:7] assign io_out_bits_phit = io_out_bits_phit_0; // @[Serdes.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Router_8 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_24 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_25 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_26 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[5], sa_stall : UInt[5]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.sa_stall[4] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] invalidate debugNodeOut.va_stall[4] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_4 of InputUnit_24 connect input_unit_0_from_4.clock, clock connect input_unit_0_from_4.reset, reset inst input_unit_1_from_9 of InputUnit_25 connect input_unit_1_from_9.clock, clock connect input_unit_1_from_9.reset, reset inst input_unit_2_from_12 of InputUnit_26 connect input_unit_2_from_12.clock, clock connect input_unit_2_from_12.reset, reset inst ingress_unit_3_from_14 of IngressUnit_17 connect ingress_unit_3_from_14.clock, clock connect ingress_unit_3_from_14.reset, reset inst ingress_unit_4_from_15 of IngressUnit_18 connect ingress_unit_4_from_15.clock, clock connect ingress_unit_4_from_15.reset, reset inst output_unit_0_to_4 of OutputUnit_24 connect output_unit_0_to_4.clock, clock connect output_unit_0_to_4.reset, reset inst output_unit_1_to_9 of OutputUnit_25 connect output_unit_1_to_9.clock, clock connect output_unit_1_to_9.reset, reset inst output_unit_2_to_12 of OutputUnit_26 connect output_unit_2_to_12.clock, clock connect output_unit_2_to_12.reset, reset inst egress_unit_3_to_7 of EgressUnit_13 connect egress_unit_3_to_7.clock, clock connect egress_unit_3_to_7.reset, reset inst switch of Switch_8 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_8 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_8 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_8 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = and(vc_allocator.io.req.`4`.ready, vc_allocator.io.req.`4`.valid) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) node _fires_count_T_7 = add(_fires_count_T_3, _fires_count_T_4) node _fires_count_T_8 = bits(_fires_count_T_7, 1, 0) node _fires_count_T_9 = add(_fires_count_T_2, _fires_count_T_8) node _fires_count_T_10 = bits(_fires_count_T_9, 1, 0) node _fires_count_T_11 = add(_fires_count_T_6, _fires_count_T_10) node _fires_count_T_12 = bits(_fires_count_T_11, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_12 connect input_unit_0_from_4.io.in, destNodesIn connect input_unit_1_from_9.io.in, destNodesIn_1 connect input_unit_2_from_12.io.in, destNodesIn_2 connect ingress_unit_3_from_14.io.in, ingressNodesIn.flit connect ingress_unit_4_from_15.io.in, ingressNodesIn_1.flit connect output_unit_0_to_4.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_4.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_4.io.out.flit connect output_unit_1_to_9.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_9.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_9.io.out.flit connect output_unit_2_to_12.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_12.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_12.io.out.flit connect egressNodesOut.flit.bits, egress_unit_3_to_7.io.out.bits connect egressNodesOut.flit.valid, egress_unit_3_to_7.io.out.valid connect egress_unit_3_to_7.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_4.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_9.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_12.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_14.io.router_req connect route_computer.io.req.`4`, ingress_unit_4_from_15.io.router_req connect input_unit_0_from_4.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_9.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_12.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_14.io.router_resp, route_computer.io.resp.`3` connect ingress_unit_4_from_15.io.router_resp, route_computer.io.resp.`4` connect vc_allocator.io.req.`0`, input_unit_0_from_4.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_9.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_12.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_14.io.vcalloc_req connect vc_allocator.io.req.`4`, ingress_unit_4_from_15.io.vcalloc_req connect input_unit_0_from_4.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_9.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_12.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_14.io.vcalloc_resp, vc_allocator.io.resp.`3` connect ingress_unit_4_from_15.io.vcalloc_resp, vc_allocator.io.resp.`4` connect output_unit_0_to_4.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_9.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_12.io.allocs, vc_allocator.io.out_allocs.`2` connect egress_unit_3_to_7.io.allocs, vc_allocator.io.out_allocs.`3` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_4.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_4.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_4.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_4.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_4.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_4.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_4.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_4.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_4.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_4.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_4.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_4.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_4.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_4.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_4.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_9.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_9.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_9.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_9.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_9.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_9.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_9.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_9.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_9.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_9.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_9.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_9.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_9.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_9.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_9.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_9.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_9.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_9.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_12.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_12.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_12.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_12.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_12.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_12.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_12.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_12.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_12.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_12.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_12.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_7.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_7.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_7.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_7.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_7.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_7.io.channel_status[0].occupied connect input_unit_0_from_4.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_1_from_9.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_1_from_9.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect input_unit_1_from_9.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect input_unit_1_from_9.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_1_from_9.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_1_from_9.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_1_from_9.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect ingress_unit_4_from_15.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect ingress_unit_4_from_15.io.out_credit_available.`1`[0], output_unit_1_to_9.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`1`[1], output_unit_1_to_9.io.credit_available[1] connect ingress_unit_4_from_15.io.out_credit_available.`1`[2], output_unit_1_to_9.io.credit_available[2] connect ingress_unit_4_from_15.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect ingress_unit_4_from_15.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect ingress_unit_4_from_15.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect ingress_unit_4_from_15.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_4.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_9.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_12.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_14.io.salloc_req[0] connect switch_allocator.io.req.`4`[0], ingress_unit_4_from_15.io.salloc_req[0] connect output_unit_0_to_4.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_4.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_4.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_4.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_4.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_4.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_1_to_9.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_9.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_9.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_9.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_9.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_9.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_2_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect egress_unit_3_to_7.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail connect egress_unit_3_to_7.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_4.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_9.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_12.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_14.io.out[0] connect switch.io.in.`4`[0], ingress_unit_4_from_15.io.out[0] connect output_unit_0_to_4.io.in, switch.io.out.`0` connect output_unit_1_to_9.io.in, switch.io.out.`1` connect output_unit_2_to_12.io.in, switch.io.out.`2` connect egress_unit_3_to_7.io.in, switch.io.out.`3` connect switch.io.sel.`0`[0].`0`[0], switch_allocator.io.switch_sel.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], switch_allocator.io.switch_sel.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], switch_allocator.io.switch_sel.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], switch_allocator.io.switch_sel.`0`[0].`3`[0] connect switch.io.sel.`0`[0].`4`[0], switch_allocator.io.switch_sel.`0`[0].`4`[0] connect switch.io.sel.`1`[0].`0`[0], switch_allocator.io.switch_sel.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], switch_allocator.io.switch_sel.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], switch_allocator.io.switch_sel.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], switch_allocator.io.switch_sel.`1`[0].`3`[0] connect switch.io.sel.`1`[0].`4`[0], switch_allocator.io.switch_sel.`1`[0].`4`[0] connect switch.io.sel.`2`[0].`0`[0], switch_allocator.io.switch_sel.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], switch_allocator.io.switch_sel.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], switch_allocator.io.switch_sel.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], switch_allocator.io.switch_sel.`2`[0].`3`[0] connect switch.io.sel.`2`[0].`4`[0], switch_allocator.io.switch_sel.`2`[0].`4`[0] connect switch.io.sel.`3`[0].`0`[0], switch_allocator.io.switch_sel.`3`[0].`0`[0] connect switch.io.sel.`3`[0].`1`[0], switch_allocator.io.switch_sel.`3`[0].`1`[0] connect switch.io.sel.`3`[0].`2`[0], switch_allocator.io.switch_sel.`3`[0].`2`[0] connect switch.io.sel.`3`[0].`3`[0], switch_allocator.io.switch_sel.`3`[0].`3`[0] connect switch.io.sel.`3`[0].`4`[0], switch_allocator.io.switch_sel.`3`[0].`4`[0] connect input_unit_0_from_4.io.block, UInt<1>(0h0) connect input_unit_1_from_9.io.block, UInt<1>(0h0) connect input_unit_2_from_12.io.block, UInt<1>(0h0) connect ingress_unit_3_from_14.io.block, UInt<1>(0h0) connect ingress_unit_4_from_15.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_4.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_9.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_12.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_14.io.debug.va_stall connect debugNodeOut.va_stall[4], ingress_unit_4_from_15.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_4.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_9.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_12.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_14.io.debug.sa_stall connect debugNodeOut.sa_stall[4], ingress_unit_4_from_15.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_34 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 4 8 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 9 8 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 12 8 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid node _T_27 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_27) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_27) connect fired_3, _fired_T_3 node _T_28 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_29 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_30 = tail(_T_29, 1) node _T_31 = eq(debug_sample, _T_30) node _T_32 = and(_T_28, _T_31) node _T_33 = and(_T_32, fired_3) when _T_33 : node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "nocsample %d i14 8 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_27 node _T_36 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_36) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_36) connect fired_4, _fired_T_4 node _T_37 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_38 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_39 = tail(_T_38, 1) node _T_40 = eq(debug_sample, _T_39) node _T_41 = and(_T_37, _T_40) node _T_42 = and(_T_41, fired_4) when _T_42 : node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "nocsample %d i15 8 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_36 node _T_45 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_45) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_45) connect fired_5, _fired_T_5 node _T_46 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_47 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_48 = tail(_T_47, 1) node _T_49 = eq(debug_sample, _T_48) node _T_50 = and(_T_46, _T_49) node _T_51 = and(_T_50, fired_5) when _T_51 : node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "nocsample %d 8 e7 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_45

module Router_8( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_3_to_7_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_3_to_7_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_3_to_7_io_out_valid; // @[Router.scala:125:13] wire _output_unit_2_to_12_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_2_to_12_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_9_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _ingress_unit_4_from_15_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_4_from_15_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_in_ready; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_3_from_14_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_2_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_9_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_9_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_1_from_9_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_0_from_4_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_9_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_14_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_15_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module RegisterReadDecode_2 : input clock : Clock input reset : Reset output io : { flip iss_valid : UInt<1>, flip iss_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rrd_valid : UInt<1>, rrd_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}} connect io.rrd_uop, io.iss_uop wire rrd_cs : { br_type : UInt<4>, use_alupipe : UInt<1>, use_muldivpipe : UInt<1>, use_mempipe : UInt<1>, op_fcn : UInt<5>, fcn_dw : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, rf_wen : UInt<1>, csr_cmd : UInt<3>} wire rrd_cs_decoder_decoded_plaInput : UInt<7> node rrd_cs_decoder_decoded_invInputs = not(rrd_cs_decoder_decoded_plaInput) wire rrd_cs_decoder_decoded : UInt<24> node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo) node rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1) node rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2) node rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3) node rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4) node rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5) node rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6) node rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_6) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7) node rrd_cs_decoder_decoded_andMatrixOutputs_66_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_7) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8) node rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_8) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9) node rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_9) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10) node rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_10) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11) node rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_11) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12) node rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_12) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13) node rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_13) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14) node rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_14) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15) node rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_15) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16) node rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_16) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17) node rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_17) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18) node rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_18) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19) node rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_19) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20) node rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_20) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21) node rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_21) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22) node rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_22) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23) node rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_23) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24) node rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_24) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24) node rrd_cs_decoder_decoded_andMatrixOutputs_71_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_25) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26) node rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_26) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25) node rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_27) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26) node rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_28) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27) node rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_29) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28) node rrd_cs_decoder_decoded_andMatrixOutputs_68_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_30) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29) node rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_31) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30) node rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_32) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31) node rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_33) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32) node rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_34) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33) node rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_35) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34) node rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_36) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35) node rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_37) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36) node rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_38) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37) node rrd_cs_decoder_decoded_andMatrixOutputs_67_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_39) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38) node rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_40) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39) node rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_41) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40) node rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_42) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41) node rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_43) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42) node rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_44) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43) node rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_45) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44) node rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_46) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45) node rrd_cs_decoder_decoded_andMatrixOutputs_70_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_47) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46) node rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_48) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47) node rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_49) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48) node rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_50) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49) node rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_51) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50) node rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_52) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51) node rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_53) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52) node rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_54) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53) node rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_55) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54) node rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_56) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_57) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55) node rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_58) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56) node rrd_cs_decoder_decoded_andMatrixOutputs_69_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_59) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57) node rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_60) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58) node rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_61) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59) node rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60) node rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_63) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61) node rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_64) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62) node rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_65) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_66 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_66 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_66, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63) node rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_66) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_67 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_67 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_67, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64) node rrd_cs_decoder_decoded_andMatrixOutputs_72_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_67) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_68 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_68 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_68, rrd_cs_decoder_decoded_andMatrixOutputs_lo_65) node rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_68) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_66 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_69 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_69 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_69, rrd_cs_decoder_decoded_andMatrixOutputs_lo_66) node rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_69) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_67 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_70 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_70 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_70, rrd_cs_decoder_decoded_andMatrixOutputs_lo_67) node rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_70) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_68 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_71 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_71 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_71, rrd_cs_decoder_decoded_andMatrixOutputs_lo_68) node rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_71) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_69 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_72 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_72 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_72, rrd_cs_decoder_decoded_andMatrixOutputs_lo_69) node rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_72) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_53_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_29_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_45_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_2_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_63_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_22_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_15_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_7) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_9) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_5_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_0_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_69_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_60_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_13) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_69_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_35_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_49_2, rrd_cs_decoder_decoded_andMatrixOutputs_1_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_48_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_66_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_15) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_10_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_26_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_39_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_17) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_43_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_72_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_68_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_37_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_19) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_51_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_57_2, rrd_cs_decoder_decoded_andMatrixOutputs_71_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_21) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_23) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_25) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_70_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_67_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_27) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_70_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_29) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_70_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_31) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_13_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_6) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_12, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_18, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_14) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_22) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_28, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_24) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_32) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_30) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7) node rrd_cs_decoder_decoded_orMatrixOutputs = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 0, 0) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 1, 1) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 2, 2) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 3, 3) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 4, 4) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 5, 5) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 6, 6) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 7, 7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 8, 8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 9, 9) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 10, 10) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 11, 11) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 12, 12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 13, 13) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 14, 14) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 15, 15) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 16, 16) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 17, 17) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 18, 18) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 19, 19) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 20, 20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 21, 21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 22, 22) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 23, 23) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_21) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_25, _rrd_cs_decoder_decoded_invMatrixOutputs_T_24) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo) connect rrd_cs_decoder_decoded, rrd_cs_decoder_decoded_invMatrixOutputs connect rrd_cs_decoder_decoded_plaInput, io.rrd_uop.uopc node rrd_cs_decoder_0 = bits(rrd_cs_decoder_decoded, 23, 20) node rrd_cs_decoder_1 = bits(rrd_cs_decoder_decoded, 19, 19) node rrd_cs_decoder_2 = bits(rrd_cs_decoder_decoded, 18, 18) node rrd_cs_decoder_3 = bits(rrd_cs_decoder_decoded, 17, 17) node rrd_cs_decoder_4 = bits(rrd_cs_decoder_decoded, 16, 13) node rrd_cs_decoder_5 = bits(rrd_cs_decoder_decoded, 12, 12) node rrd_cs_decoder_6 = bits(rrd_cs_decoder_decoded, 11, 10) node rrd_cs_decoder_7 = bits(rrd_cs_decoder_decoded, 9, 7) node rrd_cs_decoder_8 = bits(rrd_cs_decoder_decoded, 6, 4) node rrd_cs_decoder_9 = bits(rrd_cs_decoder_decoded, 3, 3) node rrd_cs_decoder_10 = bits(rrd_cs_decoder_decoded, 2, 0) connect rrd_cs.br_type, rrd_cs_decoder_0 connect rrd_cs.use_alupipe, rrd_cs_decoder_1 connect rrd_cs.use_muldivpipe, rrd_cs_decoder_2 connect rrd_cs.use_mempipe, rrd_cs_decoder_3 connect rrd_cs.op_fcn, rrd_cs_decoder_4 connect rrd_cs.fcn_dw, rrd_cs_decoder_5 connect rrd_cs.op1_sel, rrd_cs_decoder_6 connect rrd_cs.op2_sel, rrd_cs_decoder_7 connect rrd_cs.imm_sel, rrd_cs_decoder_8 connect rrd_cs.rf_wen, rrd_cs_decoder_9 connect rrd_cs.csr_cmd, rrd_cs_decoder_10 connect io.rrd_uop.ctrl.br_type, rrd_cs.br_type connect io.rrd_uop.ctrl.op1_sel, rrd_cs.op1_sel connect io.rrd_uop.ctrl.op2_sel, rrd_cs.op2_sel connect io.rrd_uop.ctrl.imm_sel, rrd_cs.imm_sel connect io.rrd_uop.ctrl.op_fcn, rrd_cs.op_fcn connect io.rrd_uop.ctrl.fcn_dw, rrd_cs.fcn_dw node _io_rrd_uop_ctrl_is_load_T = eq(io.rrd_uop.uopc, UInt<7>(0h1)) connect io.rrd_uop.ctrl.is_load, _io_rrd_uop_ctrl_is_load_T node _io_rrd_uop_ctrl_is_sta_T = eq(io.rrd_uop.uopc, UInt<7>(0h2)) node _io_rrd_uop_ctrl_is_sta_T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _io_rrd_uop_ctrl_is_sta_T_2 = or(_io_rrd_uop_ctrl_is_sta_T, _io_rrd_uop_ctrl_is_sta_T_1) connect io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_sta_T_2 node _io_rrd_uop_ctrl_is_std_T = eq(io.rrd_uop.uopc, UInt<7>(0h3)) node _io_rrd_uop_ctrl_is_std_T_1 = eq(io.rrd_uop.lrs2_rtype, UInt<2>(0h0)) node _io_rrd_uop_ctrl_is_std_T_2 = and(io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_std_T_1) node _io_rrd_uop_ctrl_is_std_T_3 = or(_io_rrd_uop_ctrl_is_std_T, _io_rrd_uop_ctrl_is_std_T_2) connect io.rrd_uop.ctrl.is_std, _io_rrd_uop_ctrl_is_std_T_3 node _T = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h1)) node _T_2 = eq(io.rrd_uop.mem_cmd, UInt<3>(0h6)) node _T_3 = and(_T_1, _T_2) node _T_4 = or(_T, _T_3) when _T_4 : connect io.rrd_uop.imm_packed, UInt<1>(0h0) node _csr_ren_T = eq(rrd_cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(io.rrd_uop.prs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node _io_rrd_uop_ctrl_csr_cmd_T = mux(csr_ren, UInt<3>(0h2), rrd_cs.csr_cmd) connect io.rrd_uop.ctrl.csr_cmd, _io_rrd_uop_ctrl_csr_cmd_T connect io.rrd_valid, io.iss_valid

module RegisterReadDecode_2( // @[func-unit-decode.scala:307:7] input clock, // @[func-unit-decode.scala:307:7] input reset, // @[func-unit-decode.scala:307:7] input io_iss_valid, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_uopc, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_inst, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_debug_inst, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_rvc, // @[func-unit-decode.scala:310:14] input [39:0] io_iss_uop_debug_pc, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_iq_type, // @[func-unit-decode.scala:310:14] input [9:0] io_iss_uop_fu_code, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_iw_state, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_br, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jalr, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jal, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sfb, // @[func-unit-decode.scala:310:14] input [15:0] io_iss_uop_br_mask, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_br_tag, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ftq_idx, // @[func-unit-decode.scala:310:14] input io_iss_uop_edge_inst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pc_lob, // @[func-unit-decode.scala:310:14] input io_iss_uop_taken, // @[func-unit-decode.scala:310:14] input [19:0] io_iss_uop_imm_packed, // @[func-unit-decode.scala:310:14] input [11:0] io_iss_uop_csr_addr, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_rob_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ldq_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_stq_idx, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_rxq_idx, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_pdst, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs1, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs2, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs3, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ppred, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs1_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs2_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs3_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_ppred_busy, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_stale_pdst, // @[func-unit-decode.scala:310:14] input io_iss_uop_exception, // @[func-unit-decode.scala:310:14] input [63:0] io_iss_uop_exc_cause, // @[func-unit-decode.scala:310:14] input io_iss_uop_bypassable, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_mem_cmd, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_mem_size, // @[func-unit-decode.scala:310:14] input io_iss_uop_mem_signed, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fence, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fencei, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_amo, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_ldq, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_stq, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_unique, // @[func-unit-decode.scala:310:14] input io_iss_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_ldst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs3, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_val, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_dst_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] input io_iss_uop_frs3_en, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_val, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_single, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_tsrc, // @[func-unit-decode.scala:310:14] output io_rrd_valid, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_uopc, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_inst, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_debug_inst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_rvc, // @[func-unit-decode.scala:310:14] output [39:0] io_rrd_uop_debug_pc, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_iq_type, // @[func-unit-decode.scala:310:14] output [9:0] io_rrd_uop_fu_code, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_iw_state, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_br, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jalr, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jal, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sfb, // @[func-unit-decode.scala:310:14] output [15:0] io_rrd_uop_br_mask, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_br_tag, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ftq_idx, // @[func-unit-decode.scala:310:14] output io_rrd_uop_edge_inst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pc_lob, // @[func-unit-decode.scala:310:14] output io_rrd_uop_taken, // @[func-unit-decode.scala:310:14] output [19:0] io_rrd_uop_imm_packed, // @[func-unit-decode.scala:310:14] output [11:0] io_rrd_uop_csr_addr, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_rob_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ldq_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_stq_idx, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_rxq_idx, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_pdst, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs1, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs2, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs3, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ppred, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs1_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs2_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs3_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ppred_busy, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_stale_pdst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_exception, // @[func-unit-decode.scala:310:14] output [63:0] io_rrd_uop_exc_cause, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bypassable, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_mem_cmd, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_mem_size, // @[func-unit-decode.scala:310:14] output io_rrd_uop_mem_signed, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fence, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fencei, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_amo, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_ldq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_stq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_unique, // @[func-unit-decode.scala:310:14] output io_rrd_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_ldst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs3, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_val, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_dst_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] output io_rrd_uop_frs3_en, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_val, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_single, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_tsrc // @[func-unit-decode.scala:310:14] ); wire io_iss_valid_0 = io_iss_valid; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_uopc_0 = io_iss_uop_uopc; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_inst_0 = io_iss_uop_inst; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_debug_inst_0 = io_iss_uop_debug_inst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_rvc_0 = io_iss_uop_is_rvc; // @[func-unit-decode.scala:307:7] wire [39:0] io_iss_uop_debug_pc_0 = io_iss_uop_debug_pc; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_iq_type_0 = io_iss_uop_iq_type; // @[func-unit-decode.scala:307:7] wire [9:0] io_iss_uop_fu_code_0 = io_iss_uop_fu_code; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ctrl_br_type_0 = io_iss_uop_ctrl_br_type; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_ctrl_op1_sel_0 = io_iss_uop_ctrl_op1_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_op2_sel_0 = io_iss_uop_ctrl_op2_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_imm_sel_0 = io_iss_uop_ctrl_imm_sel; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ctrl_op_fcn_0 = io_iss_uop_ctrl_op_fcn; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_fcn_dw_0 = io_iss_uop_ctrl_fcn_dw; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_csr_cmd_0 = io_iss_uop_ctrl_csr_cmd; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_load_0 = io_iss_uop_ctrl_is_load; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_sta_0 = io_iss_uop_ctrl_is_sta; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_std_0 = io_iss_uop_ctrl_is_std; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_iw_state_0 = io_iss_uop_iw_state; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_br_0 = io_iss_uop_is_br; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jalr_0 = io_iss_uop_is_jalr; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jal_0 = io_iss_uop_is_jal; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sfb_0 = io_iss_uop_is_sfb; // @[func-unit-decode.scala:307:7] wire [15:0] io_iss_uop_br_mask_0 = io_iss_uop_br_mask; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_br_tag_0 = io_iss_uop_br_tag; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ftq_idx_0 = io_iss_uop_ftq_idx; // @[func-unit-decode.scala:307:7] wire io_iss_uop_edge_inst_0 = io_iss_uop_edge_inst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pc_lob_0 = io_iss_uop_pc_lob; // @[func-unit-decode.scala:307:7] wire io_iss_uop_taken_0 = io_iss_uop_taken; // @[func-unit-decode.scala:307:7] wire [19:0] io_iss_uop_imm_packed_0 = io_iss_uop_imm_packed; // @[func-unit-decode.scala:307:7] wire [11:0] io_iss_uop_csr_addr_0 = io_iss_uop_csr_addr; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_rob_idx_0 = io_iss_uop_rob_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ldq_idx_0 = io_iss_uop_ldq_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_stq_idx_0 = io_iss_uop_stq_idx; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_rxq_idx_0 = io_iss_uop_rxq_idx; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_pdst_0 = io_iss_uop_pdst; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs1_0 = io_iss_uop_prs1; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs2; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs3_0 = io_iss_uop_prs3; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ppred_0 = io_iss_uop_ppred; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs1_busy_0 = io_iss_uop_prs1_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs2_busy_0 = io_iss_uop_prs2_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs3_busy_0 = io_iss_uop_prs3_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ppred_busy_0 = io_iss_uop_ppred_busy; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_stale_pdst_0 = io_iss_uop_stale_pdst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_exception_0 = io_iss_uop_exception; // @[func-unit-decode.scala:307:7] wire [63:0] io_iss_uop_exc_cause_0 = io_iss_uop_exc_cause; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bypassable_0 = io_iss_uop_bypassable; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_mem_cmd_0 = io_iss_uop_mem_cmd; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_mem_size_0 = io_iss_uop_mem_size; // @[func-unit-decode.scala:307:7] wire io_iss_uop_mem_signed_0 = io_iss_uop_mem_signed; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fence_0 = io_iss_uop_is_fence; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fencei_0 = io_iss_uop_is_fencei; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_amo_0 = io_iss_uop_is_amo; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_ldq_0 = io_iss_uop_uses_ldq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_stq_0 = io_iss_uop_uses_stq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_unique_0 = io_iss_uop_is_unique; // @[func-unit-decode.scala:307:7] wire io_iss_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_ldst_0 = io_iss_uop_ldst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs1_0 = io_iss_uop_lrs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs2_0 = io_iss_uop_lrs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs3_0 = io_iss_uop_lrs3; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_val_0 = io_iss_uop_ldst_val; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_dst_rtype_0 = io_iss_uop_dst_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype; // @[func-unit-decode.scala:307:7] wire io_iss_uop_frs3_en_0 = io_iss_uop_frs3_en; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_val_0 = io_iss_uop_fp_val; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_single_0 = io_iss_uop_fp_single; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc; // @[func-unit-decode.scala:307:7] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = 2'h0; // @[pla.scala:102:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = 3'h0; // @[pla.scala:102:36] wire io_iss_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_iss_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_valid_0 = io_iss_valid_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_uopc_0 = io_iss_uop_uopc_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_inst_0 = io_iss_uop_inst_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_debug_inst_0 = io_iss_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_rvc_0 = io_iss_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] wire [39:0] io_rrd_uop_debug_pc_0 = io_iss_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_iq_type_0 = io_iss_uop_iq_type_0; // @[func-unit-decode.scala:307:7] wire [9:0] io_rrd_uop_fu_code_0 = io_iss_uop_fu_code_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_iw_state_0 = io_iss_uop_iw_state_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_br_0 = io_iss_uop_is_br_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jalr_0 = io_iss_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jal_0 = io_iss_uop_is_jal_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sfb_0 = io_iss_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] wire [15:0] io_rrd_uop_br_mask_0 = io_iss_uop_br_mask_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_br_tag_0 = io_iss_uop_br_tag_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ftq_idx_0 = io_iss_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_edge_inst_0 = io_iss_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pc_lob_0 = io_iss_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_taken_0 = io_iss_uop_taken_0; // @[func-unit-decode.scala:307:7] wire [11:0] io_rrd_uop_csr_addr_0 = io_iss_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_rob_idx_0 = io_iss_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ldq_idx_0 = io_iss_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_stq_idx_0 = io_iss_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_rxq_idx_0 = io_iss_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_pdst_0 = io_iss_uop_pdst_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs1_0 = io_iss_uop_prs1_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs2_0 = io_iss_uop_prs2_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs3_0 = io_iss_uop_prs3_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ppred_0 = io_iss_uop_ppred_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs1_busy_0 = io_iss_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs2_busy_0 = io_iss_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs3_busy_0 = io_iss_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ppred_busy_0 = io_iss_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_stale_pdst_0 = io_iss_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_exception_0 = io_iss_uop_exception_0; // @[func-unit-decode.scala:307:7] wire [63:0] io_rrd_uop_exc_cause_0 = io_iss_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bypassable_0 = io_iss_uop_bypassable_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_mem_cmd_0 = io_iss_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_mem_size_0 = io_iss_uop_mem_size_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_mem_signed_0 = io_iss_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fence_0 = io_iss_uop_is_fence_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fencei_0 = io_iss_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_amo_0 = io_iss_uop_is_amo_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_ldq_0 = io_iss_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_stq_0 = io_iss_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_unique_0 = io_iss_uop_is_unique_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_ldst_0 = io_iss_uop_ldst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs1_0 = io_iss_uop_lrs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs2_0 = io_iss_uop_lrs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs3_0 = io_iss_uop_lrs3_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_val_0 = io_iss_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_dst_rtype_0 = io_iss_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_frs3_en_0 = io_iss_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_val_0 = io_iss_uop_fp_val_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_single_0 = io_iss_uop_fp_single_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] wire [6:0] rrd_cs_decoder_decoded_plaInput = io_rrd_uop_uopc_0; // @[pla.scala:77:22] wire [3:0] rrd_cs_br_type; // @[func-unit-decode.scala:330:20] wire [1:0] rrd_cs_op1_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_op2_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_imm_sel; // @[func-unit-decode.scala:330:20] wire [4:0] rrd_cs_op_fcn; // @[func-unit-decode.scala:330:20] wire rrd_cs_fcn_dw; // @[func-unit-decode.scala:330:20] wire [2:0] _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:349:33] wire _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:339:46] wire _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:340:57] wire _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:341:57] wire [3:0] io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] wire [19:0] io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] wire [3:0] rrd_cs_decoder_0; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_br_type_0 = rrd_cs_br_type; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_1; // @[Decode.scala:50:77] wire rrd_cs_decoder_2; // @[Decode.scala:50:77] wire rrd_cs_decoder_3; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op_fcn_0 = rrd_cs_op_fcn; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_5; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_fcn_dw_0 = rrd_cs_fcn_dw; // @[func-unit-decode.scala:307:7, :330:20] wire [1:0] rrd_cs_decoder_6; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op1_sel_0 = rrd_cs_op1_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_7; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op2_sel_0 = rrd_cs_op2_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_8; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_imm_sel_0 = rrd_cs_imm_sel; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_9; // @[Decode.scala:50:77] wire [2:0] rrd_cs_decoder_10; // @[Decode.scala:50:77] wire rrd_cs_use_alupipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_muldivpipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_mempipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_rf_wen; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20] wire [6:0] rrd_cs_decoder_decoded_invInputs = ~rrd_cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [23:0] rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [23:0] rrd_cs_decoder_decoded; // @[pla.scala:81:23] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T = {rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = rrd_cs_decoder_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_66_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_71_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_68_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_67_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = rrd_cs_decoder_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = rrd_cs_decoder_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_70_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = rrd_cs_decoder_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_69_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_66 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_66 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_66, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_67 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_67 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_67, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_72_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_68 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_68 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_68, rrd_cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_66 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_69 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_69 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_69, rrd_cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_67 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_70 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_70 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_70, rrd_cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_68 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_71 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_71 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_71, rrd_cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_69 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_72 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_72 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_72, rrd_cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_53_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_29_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_45_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [8:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T = {rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_15_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_7; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_69_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_49_2, rrd_cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_66_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [10:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_43_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_72_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_51_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_57_2, rrd_cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [7:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_8; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = _GEN; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_9; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = _GEN; // @[pla.scala:114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_67_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, 3'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_12, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, 1'h0}; // @[pla.scala:102:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_18, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_14}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_28, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:102:36] wire [23:0] rrd_cs_decoder_decoded_orMatrixOutputs = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:102:36] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T = rrd_cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = rrd_cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = rrd_cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = rrd_cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = rrd_cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = rrd_cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = rrd_cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = rrd_cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = rrd_cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = rrd_cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = rrd_cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = rrd_cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = rrd_cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_12; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = rrd_cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = rrd_cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = rrd_cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = rrd_cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = rrd_cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = rrd_cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = rrd_cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_20; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = rrd_cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = rrd_cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = rrd_cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = rrd_cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :123:40] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_25, _rrd_cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded_invMatrixOutputs = {rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded = rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign rrd_cs_decoder_0 = rrd_cs_decoder_decoded[23:20]; // @[pla.scala:81:23] assign rrd_cs_br_type = rrd_cs_decoder_0; // @[Decode.scala:50:77] assign rrd_cs_decoder_1 = rrd_cs_decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_cs_use_alupipe = rrd_cs_decoder_1; // @[Decode.scala:50:77] assign rrd_cs_decoder_2 = rrd_cs_decoder_decoded[18]; // @[pla.scala:81:23] assign rrd_cs_use_muldivpipe = rrd_cs_decoder_2; // @[Decode.scala:50:77] assign rrd_cs_decoder_3 = rrd_cs_decoder_decoded[17]; // @[pla.scala:81:23] assign rrd_cs_use_mempipe = rrd_cs_decoder_3; // @[Decode.scala:50:77] wire [3:0] rrd_cs_decoder_4 = rrd_cs_decoder_decoded[16:13]; // @[pla.scala:81:23] assign rrd_cs_decoder_5 = rrd_cs_decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_cs_fcn_dw = rrd_cs_decoder_5; // @[Decode.scala:50:77] assign rrd_cs_decoder_6 = rrd_cs_decoder_decoded[11:10]; // @[pla.scala:81:23] assign rrd_cs_op1_sel = rrd_cs_decoder_6; // @[Decode.scala:50:77] assign rrd_cs_decoder_7 = rrd_cs_decoder_decoded[9:7]; // @[pla.scala:81:23] assign rrd_cs_op2_sel = rrd_cs_decoder_7; // @[Decode.scala:50:77] assign rrd_cs_decoder_8 = rrd_cs_decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_cs_imm_sel = rrd_cs_decoder_8; // @[Decode.scala:50:77] assign rrd_cs_decoder_9 = rrd_cs_decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_cs_rf_wen = rrd_cs_decoder_9; // @[Decode.scala:50:77] assign rrd_cs_decoder_10 = rrd_cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign rrd_cs_csr_cmd = rrd_cs_decoder_10; // @[Decode.scala:50:77] assign rrd_cs_op_fcn = {1'h0, rrd_cs_decoder_4}; // @[Decode.scala:50:77] assign _io_rrd_uop_ctrl_is_load_T = io_rrd_uop_uopc_0 == 7'h1; // @[func-unit-decode.scala:307:7, :339:46] assign io_rrd_uop_ctrl_is_load_0 = _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:307:7, :339:46] wire _io_rrd_uop_ctrl_is_sta_T = io_rrd_uop_uopc_0 == 7'h2; // @[func-unit-decode.scala:307:7, :340:46] wire _io_rrd_uop_ctrl_is_sta_T_1 = io_rrd_uop_uopc_0 == 7'h43; // @[func-unit-decode.scala:307:7, :340:76] assign _io_rrd_uop_ctrl_is_sta_T_2 = _io_rrd_uop_ctrl_is_sta_T | _io_rrd_uop_ctrl_is_sta_T_1; // @[func-unit-decode.scala:340:{46,57,76}] assign io_rrd_uop_ctrl_is_sta_0 = _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:307:7, :340:57] wire _io_rrd_uop_ctrl_is_std_T = io_rrd_uop_uopc_0 == 7'h3; // @[func-unit-decode.scala:307:7, :341:46] wire _io_rrd_uop_ctrl_is_std_T_1 = io_rrd_uop_lrs2_rtype_0 == 2'h0; // @[func-unit-decode.scala:307:7, :341:109] wire _io_rrd_uop_ctrl_is_std_T_2 = io_rrd_uop_ctrl_is_sta_0 & _io_rrd_uop_ctrl_is_std_T_1; // @[func-unit-decode.scala:307:7, :341:{84,109}] assign _io_rrd_uop_ctrl_is_std_T_3 = _io_rrd_uop_ctrl_is_std_T | _io_rrd_uop_ctrl_is_std_T_2; // @[func-unit-decode.scala:341:{46,57,84}] assign io_rrd_uop_ctrl_is_std_0 = _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:307:7, :341:57] assign io_rrd_uop_imm_packed_0 = _io_rrd_uop_ctrl_is_sta_T_1 | _io_rrd_uop_ctrl_is_load_T & io_rrd_uop_mem_cmd_0 == 5'h6 ? 20'h0 : io_iss_uop_imm_packed_0; // @[func-unit-decode.scala:307:7, :320:16, :339:46, :340:76, :343:{39,69,91,103}, :344:27] wire _csr_ren_T = rrd_cs_csr_cmd == 3'h6; // @[func-unit-decode.scala:330:20, :348:33] wire _csr_ren_T_1 = &rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:61] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[func-unit-decode.scala:348:{33,43,61}] wire _csr_ren_T_3 = io_rrd_uop_prs1_0 == 7'h0; // @[pla.scala:114:36] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[func-unit-decode.scala:348:{43,72,82}] assign _io_rrd_uop_ctrl_csr_cmd_T = csr_ren ? 3'h2 : rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:72, :349:33] assign io_rrd_uop_ctrl_csr_cmd_0 = _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:307:7, :349:33] assign io_rrd_valid = io_rrd_valid_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uopc = io_rrd_uop_uopc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_inst = io_rrd_uop_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_inst = io_rrd_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_rvc = io_rrd_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_pc = io_rrd_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iq_type = io_rrd_uop_iq_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fu_code = io_rrd_uop_fu_code_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_br_type = io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op1_sel = io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op2_sel = io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_imm_sel = io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op_fcn = io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_fcn_dw = io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_csr_cmd = io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_std = io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iw_state = io_rrd_uop_iw_state_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_br = io_rrd_uop_is_br_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jalr = io_rrd_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jal = io_rrd_uop_is_jal_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sfb = io_rrd_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_mask = io_rrd_uop_br_mask_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_tag = io_rrd_uop_br_tag_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ftq_idx = io_rrd_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_edge_inst = io_rrd_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pc_lob = io_rrd_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_taken = io_rrd_uop_taken_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_imm_packed = io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_csr_addr = io_rrd_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rob_idx = io_rrd_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldq_idx = io_rrd_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stq_idx = io_rrd_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rxq_idx = io_rrd_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pdst = io_rrd_uop_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1 = io_rrd_uop_prs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2 = io_rrd_uop_prs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3 = io_rrd_uop_prs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred = io_rrd_uop_ppred_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1_busy = io_rrd_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2_busy = io_rrd_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3_busy = io_rrd_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred_busy = io_rrd_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stale_pdst = io_rrd_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exception = io_rrd_uop_exception_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exc_cause = io_rrd_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bypassable = io_rrd_uop_bypassable_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_cmd = io_rrd_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_size = io_rrd_uop_mem_size_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_signed = io_rrd_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fence = io_rrd_uop_is_fence_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fencei = io_rrd_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_amo = io_rrd_uop_is_amo_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_ldq = io_rrd_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_stq = io_rrd_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sys_pc2epc = io_rrd_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_unique = io_rrd_uop_is_unique_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_flush_on_commit = io_rrd_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_is_rs1 = io_rrd_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst = io_rrd_uop_ldst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1 = io_rrd_uop_lrs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2 = io_rrd_uop_lrs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs3 = io_rrd_uop_lrs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_val = io_rrd_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_dst_rtype = io_rrd_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1_rtype = io_rrd_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2_rtype = io_rrd_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_frs3_en = io_rrd_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_val = io_rrd_uop_fp_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_single = io_rrd_uop_fp_single_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_pf_if = io_rrd_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ae_if = io_rrd_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ma_if = io_rrd_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_debug_if = io_rrd_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_xcpt_if = io_rrd_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_fsrc = io_rrd_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_tsrc = io_rrd_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_8 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_8 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_8 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_8 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d

module TLMasterACDToNoC_8( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [72:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_8 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_8 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_6 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<12>(0h780))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 11, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 64, 10) node _adjustedSig_T_1 = bits(io.in.sig, 9, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<12> wire common_fractOut : UInt<52> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<53>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 53) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 11, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 52, 1) node _common_fractOut_T_1 = bits(roundedSig, 51, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 54, 54) node _roundCarry_T_1 = bits(roundedSig, 53, 53) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<12>(0h3ce)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_6( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [53:0] _roundMask_T = 54'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [55:0] roundMask = 56'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [56:0] _shiftedRoundMask_T = 57'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [55:0] shiftedRoundMask = 56'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [55:0] _roundPosMask_T = 56'hFFFFFFFFFFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [55:0] roundPosMask = 56'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [55:0] _roundedSig_T_10 = 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [54:0] _roundedSig_T_6 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [54:0] _roundedSig_T_14 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [11:0] _expOut_T_6 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_9 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_12 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_5 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [11:0] _expOut_T_8 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [11:0] _expOut_T_11 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [11:0] _expOut_T_14 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [11:0] _expOut_T_16 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [11:0] _expOut_T_18 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [11:0] _expOut_T_20 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [51:0] _fractOut_T_2 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [51:0] _fractOut_T_4 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [12:0] _sAdjustedExp_T = {{4{io_in_sExp_0[8]}}, io_in_sExp_0} + 13'h780; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [11:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[11:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [12:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [54:0] _adjustedSig_T = io_in_sig_0[64:10]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [9:0] _adjustedSig_T_1 = io_in_sig_0[9:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [55:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [55:0] _roundPosBit_T = adjustedSig & 56'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & 56'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig | 56'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_7 = {54'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_11 = adjustedSig & 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_15 = {54'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {sAdjustedExp[12], sAdjustedExp} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [11:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [11:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [11:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [11:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [11:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [11:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? 52'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [51:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_273 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_273( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLEToNoC : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<5>, egress_id : UInt}}} inst q of Queue1_TLBundleE_a32d64s6k5z4c connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(UInt<1>(0h0), _head_count_T) when _head_T : node _head_counter_T = mux(head, UInt<1>(0h0), head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(UInt<1>(0h0), _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, UInt<1>(0h0), tail_counter1) connect tail_counter, _tail_counter_T regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 2, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<2>(0h3)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 2, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<2>(0h2)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 2, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<1>(0h1)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.sink, UInt<3>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 2, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.sink, 3) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<3>(0h7)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_T = mux(UInt<1>(0h0), UInt<4>(0hc), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hf), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h15), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h18), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, UInt<1>(0h0), q.io.deq.bits.sink) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) connect has_body, UInt<1>(0h0) connect q.io.enq, io.protocol

module TLEToNoC( // @[TilelinkAdapters.scala:191:7] input clock, // @[TilelinkAdapters.scala:191:7] input reset, // @[TilelinkAdapters.scala:191:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] reg is_body; // @[TilelinkAdapters.scala:39:24] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:191:7] if (reset) begin // @[TilelinkAdapters.scala:191:7] head_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :191:7] end else begin // @[TilelinkAdapters.scala:191:7] if (io_flit_ready & _q_io_deq_valid) // @[Decoupled.scala:51:35] head_counter <= head ? 9'h0 : head_counter - 9'h1; // @[Edges.scala:229:27, :230:28, :231:25, :236:21] is_body <= ~_GEN & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_23 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_23 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_23 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_10 : connect states[0].g, UInt<3>(0h2) connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_18 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_19 = and(io.router_req.ready, io.router_req.valid) when _T_19 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_21 = or(_T_20, vcalloc_vals[2]) when _T_21 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16 wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<4> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_21 : UInt<4> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].flow, states[0].flow node _T_22 = bits(vcalloc_sel, 0, 0) node _T_23 = and(vcalloc_vals[0], _T_22) node _T_24 = and(_T_23, io.vcalloc_req.ready) when _T_24 : connect states[0].g, UInt<3>(0h3) node _T_25 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_25 : connect vcalloc_vals[0], UInt<1>(0h1) connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`3`[0] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`3`[0] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_26 : node _T_27 = bits(vcalloc_sel, 0, 0) when _T_27 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_28 = bits(vcalloc_sel, 1, 1) when _T_28 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_29 = bits(vcalloc_sel, 2, 2) when _T_29 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_56 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[0].vc_sel.`2`[2], states[0].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[0].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_3 = cat(states[0].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo) node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0]) node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_30 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_31 = and(_T_30, input_buffer.io.deq[0].bits.tail) when _T_31 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[1] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 connect vc_sel.`3`, _vc_sel_WIRE_12 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16) node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17) node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_21 node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_32 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[0], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`3`[0] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`3`[0] invalidate states[2].g node _T_33 = asUInt(reset) when _T_33 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)

module InputUnit_23( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e11_s53_3 : output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 63, 63) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_3 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i64_e11_s53_3( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [64:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7] wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [64:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53] wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70] wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_3 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_181 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_181( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n0x0_4 : output auto : { } wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset

module IntSyncSyncCrossingSink_n0x0_4(); // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_119 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_136 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_119( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_136 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Queue1_RegMapperInput_i9_m8 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}, count : UInt<1>} cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}} [1] wire enq_ptr_value : UInt connect enq_ptr_value, UInt<1>(0h0) wire deq_ptr_value : UInt connect deq_ptr_value, UInt<1>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _empty_T = eq(maybe_full, UInt<1>(0h0)) node empty = and(ptr_match, _empty_T) node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> connect do_deq, _do_deq_T when do_enq : wire _WIRE : UInt connect _WIRE, UInt<1>(0h0) infer mport MPORT = ram[_WIRE], clock connect MPORT.extra, io.enq.bits.extra connect MPORT.mask, io.enq.bits.mask connect MPORT.data, io.enq.bits.data connect MPORT.index, io.enq.bits.index connect MPORT.read, io.enq.bits.read when do_deq : skip node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq when UInt<1>(0h0) : connect enq_ptr_value, UInt<1>(0h0) connect deq_ptr_value, UInt<1>(0h0) connect maybe_full, UInt<1>(0h0) node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire _io_deq_bits_WIRE : UInt connect _io_deq_bits_WIRE, UInt<1>(0h0) infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock connect io.deq.bits, io_deq_bits_MPORT node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) node _io_count_T_2 = or(_io_count_T_1, ptr_diff) connect io.count, _io_count_T_2

module Queue1_RegMapperInput_i9_m8( // @[RegMapper.scala:71:32] input clock, // @[RegMapper.scala:71:32] input reset, // @[RegMapper.scala:71:32] output io_enq_ready, // @[Decoupled.scala:255:14] input io_enq_valid, // @[Decoupled.scala:255:14] input io_enq_bits_read, // @[Decoupled.scala:255:14] input [8:0] io_enq_bits_index, // @[Decoupled.scala:255:14] input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14] input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14] input [11:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14] input [1:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14] input io_deq_ready, // @[Decoupled.scala:255:14] output io_deq_valid, // @[Decoupled.scala:255:14] output io_deq_bits_read, // @[Decoupled.scala:255:14] output [8:0] io_deq_bits_index, // @[Decoupled.scala:255:14] output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14] output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14] output [11:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14] output [1:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14] ); wire io_enq_valid_0 = io_enq_valid; // @[RegMapper.scala:71:32] wire io_enq_bits_read_0 = io_enq_bits_read; // @[RegMapper.scala:71:32] wire [8:0] io_enq_bits_index_0 = io_enq_bits_index; // @[RegMapper.scala:71:32] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[RegMapper.scala:71:32] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[RegMapper.scala:71:32] wire [11:0] io_enq_bits_extra_tlrr_extra_source_0 = io_enq_bits_extra_tlrr_extra_source; // @[RegMapper.scala:71:32] wire [1:0] io_enq_bits_extra_tlrr_extra_size_0 = io_enq_bits_extra_tlrr_extra_size; // @[RegMapper.scala:71:32] wire io_deq_ready_0 = io_deq_ready; // @[RegMapper.scala:71:32] wire ptr_match = 1'h1; // @[Decoupled.scala:260:33] wire [1:0] _ptr_diff_T = 2'h0; // @[Decoupled.scala:309:32] wire enq_ptr_value = 1'h0; // @[Counter.scala:61:73] wire deq_ptr_value = 1'h0; // @[Counter.scala:61:73] wire _io_enq_ready_T; // @[Decoupled.scala:286:19] wire _io_deq_bits_WIRE = 1'h0; // @[Decoupled.scala:293:23] wire ptr_diff = 1'h0; // @[Decoupled.scala:309:32] wire _io_deq_valid_T; // @[Decoupled.scala:285:19] wire _io_count_T_2; // @[Decoupled.scala:312:62] wire io_enq_ready_0; // @[RegMapper.scala:71:32] wire [11:0] io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32] wire [1:0] io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32] wire io_deq_bits_read_0; // @[RegMapper.scala:71:32] wire [8:0] io_deq_bits_index_0; // @[RegMapper.scala:71:32] wire [63:0] io_deq_bits_data_0; // @[RegMapper.scala:71:32] wire [7:0] io_deq_bits_mask_0; // @[RegMapper.scala:71:32] wire io_deq_valid_0; // @[RegMapper.scala:71:32] wire io_count; // @[RegMapper.scala:71:32] reg [95:0] ram; // @[Decoupled.scala:256:91] assign io_deq_bits_read_0 = ram[0]; // @[Decoupled.scala:256:91] assign io_deq_bits_index_0 = ram[9:1]; // @[Decoupled.scala:256:91] assign io_deq_bits_data_0 = ram[73:10]; // @[Decoupled.scala:256:91] assign io_deq_bits_mask_0 = ram[81:74]; // @[Decoupled.scala:256:91] assign io_deq_bits_extra_tlrr_extra_source_0 = ram[93:82]; // @[Decoupled.scala:256:91] assign io_deq_bits_extra_tlrr_extra_size_0 = ram[95:94]; // @[Decoupled.scala:256:91] reg maybe_full; // @[Decoupled.scala:259:27] wire full = maybe_full; // @[Decoupled.scala:259:27, :262:24] wire _io_count_T = maybe_full; // @[Decoupled.scala:259:27, :312:32] wire _empty_T = ~maybe_full; // @[Decoupled.scala:259:27, :261:28] wire empty = _empty_T; // @[Decoupled.scala:261:{25,28}] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35, :263:27] wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire do_deq = _do_deq_T; // @[Decoupled.scala:51:35, :264:27] assign _io_deq_valid_T = ~empty; // @[Decoupled.scala:261:25, :285:19] assign io_deq_valid_0 = _io_deq_valid_T; // @[Decoupled.scala:285:19] assign _io_enq_ready_T = ~full; // @[Decoupled.scala:262:24, :286:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[Decoupled.scala:286:19] wire _io_count_T_1 = _io_count_T; // @[Decoupled.scala:312:{20,32}] assign _io_count_T_2 = _io_count_T_1; // @[Decoupled.scala:312:{20,62}] assign io_count = _io_count_T_2; // @[Decoupled.scala:312:62] always @(posedge clock) begin // @[RegMapper.scala:71:32] if (do_enq) // @[Decoupled.scala:263:27] ram <= {io_enq_bits_extra_tlrr_extra_size_0, io_enq_bits_extra_tlrr_extra_source_0, io_enq_bits_mask_0, io_enq_bits_data_0, io_enq_bits_index_0, io_enq_bits_read_0}; // @[Decoupled.scala:256:91] if (reset) // @[RegMapper.scala:71:32] maybe_full <= 1'h0; // @[Decoupled.scala:259:27] else if (~(do_enq == do_deq)) // @[Decoupled.scala:259:27, :263:27, :264:27, :276:{15,27}, :277:16] maybe_full <= do_enq; // @[Decoupled.scala:259:27, :263:27] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[RegMapper.scala:71:32] assign io_deq_valid = io_deq_valid_0; // @[RegMapper.scala:71:32] assign io_deq_bits_read = io_deq_bits_read_0; // @[RegMapper.scala:71:32] assign io_deq_bits_index = io_deq_bits_index_0; // @[RegMapper.scala:71:32] assign io_deq_bits_data = io_deq_bits_data_0; // @[RegMapper.scala:71:32] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[RegMapper.scala:71:32] assign io_deq_bits_extra_tlrr_extra_source = io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32] assign io_deq_bits_extra_tlrr_extra_size = io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<13>(0h1000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = and(_T_150, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = and(_T_149, _T_163) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_164, UInt<1>(0h1), "") : assert_2 node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_8) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<1>(0h1)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_9) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h2)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_10) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_187 = shr(io.in.a.bits.source, 2) node _T_188 = eq(_T_187, UInt<2>(0h3)) node _T_189 = leq(UInt<1>(0h0), uncommonBits_11) node _T_190 = and(_T_188, _T_189) node _T_191 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_194 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_195 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_196 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_168 connect _WIRE[1], _T_174 connect _WIRE[2], _T_180 connect _WIRE[3], _T_186 connect _WIRE[4], _T_192 connect _WIRE[5], _T_193 connect _WIRE[6], _T_194 connect _WIRE[7], _T_195 connect _WIRE[8], _T_196 node _T_197 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_198 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_202 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[5], _T_197, UInt<1>(0h0)) node _T_204 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = or(_T_198, _T_199) node _T_208 = or(_T_207, _T_200) node _T_209 = or(_T_208, _T_201) node _T_210 = or(_T_209, _T_202) node _T_211 = or(_T_210, _T_203) node _T_212 = or(_T_211, _T_204) node _T_213 = or(_T_212, _T_205) node _T_214 = or(_T_213, _T_206) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_214 node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<13>(0h1000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = or(_T_223, _T_228) node _T_230 = and(_T_218, _T_229) node _T_231 = or(UInt<1>(0h0), _T_230) node _T_232 = and(_WIRE_1, _T_231) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_232, UInt<1>(0h1), "") : assert_3 node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(source_ok, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_239 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_239, UInt<1>(0h1), "") : assert_5 node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(is_aligned, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_246 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_246, UInt<1>(0h1), "") : assert_7 node _T_250 = not(io.in.a.bits.mask) node _T_251 = eq(_T_250, UInt<1>(0h0)) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_251, UInt<1>(0h1), "") : assert_8 node _T_255 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_255, UInt<1>(0h1), "") : assert_9 node _T_259 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_259 : node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_12) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<1>(0h1)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_13) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_276 = shr(io.in.a.bits.source, 2) node _T_277 = eq(_T_276, UInt<2>(0h2)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_14) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_281 = and(_T_279, _T_280) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_282 = shr(io.in.a.bits.source, 2) node _T_283 = eq(_T_282, UInt<2>(0h3)) node _T_284 = leq(UInt<1>(0h0), uncommonBits_15) node _T_285 = and(_T_283, _T_284) node _T_286 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_287 = and(_T_285, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_289 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_290 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_291 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_292 = or(_T_263, _T_269) node _T_293 = or(_T_292, _T_275) node _T_294 = or(_T_293, _T_281) node _T_295 = or(_T_294, _T_287) node _T_296 = or(_T_295, _T_288) node _T_297 = or(_T_296, _T_289) node _T_298 = or(_T_297, _T_290) node _T_299 = or(_T_298, _T_291) node _T_300 = and(_T_262, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_307, _T_312) node _T_314 = and(_T_302, _T_313) node _T_315 = or(UInt<1>(0h0), _T_314) node _T_316 = and(_T_301, _T_315) node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(_T_316, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_316, UInt<1>(0h1), "") : assert_10 node _T_320 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_16) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_327 = shr(io.in.a.bits.source, 2) node _T_328 = eq(_T_327, UInt<1>(0h1)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_17) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_333 = shr(io.in.a.bits.source, 2) node _T_334 = eq(_T_333, UInt<2>(0h2)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_18) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_338 = and(_T_336, _T_337) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<2>(0h3)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_19) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_320 connect _WIRE_2[1], _T_326 connect _WIRE_2[2], _T_332 connect _WIRE_2[3], _T_338 connect _WIRE_2[4], _T_344 connect _WIRE_2[5], _T_345 connect _WIRE_2[6], _T_346 connect _WIRE_2[7], _T_347 connect _WIRE_2[8], _T_348 node _T_349 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_350 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE_2[5], _T_349, UInt<1>(0h0)) node _T_356 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = or(_T_350, _T_351) node _T_360 = or(_T_359, _T_352) node _T_361 = or(_T_360, _T_353) node _T_362 = or(_T_361, _T_354) node _T_363 = or(_T_362, _T_355) node _T_364 = or(_T_363, _T_356) node _T_365 = or(_T_364, _T_357) node _T_366 = or(_T_365, _T_358) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_366 node _T_367 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_368 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_369 = and(_T_367, _T_368) node _T_370 = or(UInt<1>(0h0), _T_369) node _T_371 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_372 = cvt(_T_371) node _T_373 = and(_T_372, asSInt(UInt<13>(0h1000))) node _T_374 = asSInt(_T_373) node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0))) node _T_376 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_377 = cvt(_T_376) node _T_378 = and(_T_377, asSInt(UInt<13>(0h1000))) node _T_379 = asSInt(_T_378) node _T_380 = eq(_T_379, asSInt(UInt<1>(0h0))) node _T_381 = or(_T_375, _T_380) node _T_382 = and(_T_370, _T_381) node _T_383 = or(UInt<1>(0h0), _T_382) node _T_384 = and(_WIRE_3, _T_383) node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(_T_384, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_384, UInt<1>(0h1), "") : assert_11 node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(source_ok, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_391 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_391, UInt<1>(0h1), "") : assert_13 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(is_aligned, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_398 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_398, UInt<1>(0h1), "") : assert_15 node _T_402 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_402, UInt<1>(0h1), "") : assert_16 node _T_406 = not(io.in.a.bits.mask) node _T_407 = eq(_T_406, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_407, UInt<1>(0h1), "") : assert_17 node _T_411 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_411, UInt<1>(0h1), "") : assert_18 node _T_415 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_417 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_418 = and(_T_416, _T_417) node _T_419 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_420 = shr(io.in.a.bits.source, 2) node _T_421 = eq(_T_420, UInt<1>(0h0)) node _T_422 = leq(UInt<1>(0h0), uncommonBits_20) node _T_423 = and(_T_421, _T_422) node _T_424 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_425 = and(_T_423, _T_424) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_426 = shr(io.in.a.bits.source, 2) node _T_427 = eq(_T_426, UInt<1>(0h1)) node _T_428 = leq(UInt<1>(0h0), uncommonBits_21) node _T_429 = and(_T_427, _T_428) node _T_430 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_431 = and(_T_429, _T_430) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_432 = shr(io.in.a.bits.source, 2) node _T_433 = eq(_T_432, UInt<2>(0h2)) node _T_434 = leq(UInt<1>(0h0), uncommonBits_22) node _T_435 = and(_T_433, _T_434) node _T_436 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_437 = and(_T_435, _T_436) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_438 = shr(io.in.a.bits.source, 2) node _T_439 = eq(_T_438, UInt<2>(0h3)) node _T_440 = leq(UInt<1>(0h0), uncommonBits_23) node _T_441 = and(_T_439, _T_440) node _T_442 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_443 = and(_T_441, _T_442) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_447 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_448 = or(_T_419, _T_425) node _T_449 = or(_T_448, _T_431) node _T_450 = or(_T_449, _T_437) node _T_451 = or(_T_450, _T_443) node _T_452 = or(_T_451, _T_444) node _T_453 = or(_T_452, _T_445) node _T_454 = or(_T_453, _T_446) node _T_455 = or(_T_454, _T_447) node _T_456 = and(_T_418, _T_455) node _T_457 = or(UInt<1>(0h0), _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_457, UInt<1>(0h1), "") : assert_19 node _T_461 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_462 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_463 = and(_T_461, _T_462) node _T_464 = or(UInt<1>(0h0), _T_463) node _T_465 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_466 = cvt(_T_465) node _T_467 = and(_T_466, asSInt(UInt<13>(0h1000))) node _T_468 = asSInt(_T_467) node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0))) node _T_470 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<13>(0h1000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = or(_T_469, _T_474) node _T_476 = and(_T_464, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_24) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_25) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_26) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_27) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_529 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_530 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_531 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_532 = or(_T_503, _T_509) node _T_533 = or(_T_532, _T_515) node _T_534 = or(_T_533, _T_521) node _T_535 = or(_T_534, _T_527) node _T_536 = or(_T_535, _T_528) node _T_537 = or(_T_536, _T_529) node _T_538 = or(_T_537, _T_530) node _T_539 = or(_T_538, _T_531) node _T_540 = and(_T_502, _T_539) node _T_541 = or(UInt<1>(0h0), _T_540) node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_544 = and(_T_542, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<13>(0h1000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = or(_T_550, _T_555) node _T_557 = and(_T_545, _T_556) node _T_558 = or(UInt<1>(0h0), _T_557) node _T_559 = and(_T_541, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_559, UInt<1>(0h1), "") : assert_26 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_569, UInt<1>(0h1), "") : assert_29 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_573, UInt<1>(0h1), "") : assert_30 node _T_577 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_577 : node _T_578 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_579 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_580 = and(_T_578, _T_579) node _T_581 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_28) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<1>(0h1)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_29) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_594 = shr(io.in.a.bits.source, 2) node _T_595 = eq(_T_594, UInt<2>(0h2)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_30) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_599 = and(_T_597, _T_598) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_600 = shr(io.in.a.bits.source, 2) node _T_601 = eq(_T_600, UInt<2>(0h3)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_31) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_605 = and(_T_603, _T_604) node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_609 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_610 = or(_T_581, _T_587) node _T_611 = or(_T_610, _T_593) node _T_612 = or(_T_611, _T_599) node _T_613 = or(_T_612, _T_605) node _T_614 = or(_T_613, _T_606) node _T_615 = or(_T_614, _T_607) node _T_616 = or(_T_615, _T_608) node _T_617 = or(_T_616, _T_609) node _T_618 = and(_T_580, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_621 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<13>(0h1000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<13>(0h1000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_637, UInt<1>(0h1), "") : assert_31 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(source_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(is_aligned, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_647 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_647, UInt<1>(0h1), "") : assert_34 node _T_651 = not(mask) node _T_652 = and(io.in.a.bits.mask, _T_651) node _T_653 = eq(_T_652, UInt<1>(0h0)) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_653, UInt<1>(0h1), "") : assert_35 node _T_657 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_657 : node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_662 = shr(io.in.a.bits.source, 2) node _T_663 = eq(_T_662, UInt<1>(0h0)) node _T_664 = leq(UInt<1>(0h0), uncommonBits_32) node _T_665 = and(_T_663, _T_664) node _T_666 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_667 = and(_T_665, _T_666) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_668 = shr(io.in.a.bits.source, 2) node _T_669 = eq(_T_668, UInt<1>(0h1)) node _T_670 = leq(UInt<1>(0h0), uncommonBits_33) node _T_671 = and(_T_669, _T_670) node _T_672 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_673 = and(_T_671, _T_672) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_674 = shr(io.in.a.bits.source, 2) node _T_675 = eq(_T_674, UInt<2>(0h2)) node _T_676 = leq(UInt<1>(0h0), uncommonBits_34) node _T_677 = and(_T_675, _T_676) node _T_678 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_679 = and(_T_677, _T_678) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_680 = shr(io.in.a.bits.source, 2) node _T_681 = eq(_T_680, UInt<2>(0h3)) node _T_682 = leq(UInt<1>(0h0), uncommonBits_35) node _T_683 = and(_T_681, _T_682) node _T_684 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_689 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_690 = or(_T_661, _T_667) node _T_691 = or(_T_690, _T_673) node _T_692 = or(_T_691, _T_679) node _T_693 = or(_T_692, _T_685) node _T_694 = or(_T_693, _T_686) node _T_695 = or(_T_694, _T_687) node _T_696 = or(_T_695, _T_688) node _T_697 = or(_T_696, _T_689) node _T_698 = and(_T_660, _T_697) node _T_699 = or(UInt<1>(0h0), _T_698) node _T_700 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_701 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_702 = cvt(_T_701) node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000))) node _T_704 = asSInt(_T_703) node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0))) node _T_706 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<13>(0h1000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = or(_T_705, _T_710) node _T_712 = and(_T_700, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = and(_T_699, _T_713) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_714, UInt<1>(0h1), "") : assert_36 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(source_ok, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(is_aligned, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_724 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_724, UInt<1>(0h1), "") : assert_39 node _T_728 = eq(io.in.a.bits.mask, mask) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_728, UInt<1>(0h1), "") : assert_40 node _T_732 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_732 : node _T_733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<1>(0h0)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_36) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<1>(0h1)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_37) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_749 = shr(io.in.a.bits.source, 2) node _T_750 = eq(_T_749, UInt<2>(0h2)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_38) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_755 = shr(io.in.a.bits.source, 2) node _T_756 = eq(_T_755, UInt<2>(0h3)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_39) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_760 = and(_T_758, _T_759) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_764 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_765 = or(_T_736, _T_742) node _T_766 = or(_T_765, _T_748) node _T_767 = or(_T_766, _T_754) node _T_768 = or(_T_767, _T_760) node _T_769 = or(_T_768, _T_761) node _T_770 = or(_T_769, _T_762) node _T_771 = or(_T_770, _T_763) node _T_772 = or(_T_771, _T_764) node _T_773 = and(_T_735, _T_772) node _T_774 = or(UInt<1>(0h0), _T_773) node _T_775 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_776 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<13>(0h1000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = or(_T_780, _T_785) node _T_787 = and(_T_775, _T_786) node _T_788 = or(UInt<1>(0h0), _T_787) node _T_789 = and(_T_774, _T_788) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_789, UInt<1>(0h1), "") : assert_41 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(source_ok, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(is_aligned, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_799 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_799, UInt<1>(0h1), "") : assert_44 node _T_803 = eq(io.in.a.bits.mask, mask) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_803, UInt<1>(0h1), "") : assert_45 node _T_807 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_807 : node _T_808 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_809 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_810 = and(_T_808, _T_809) node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_812 = shr(io.in.a.bits.source, 2) node _T_813 = eq(_T_812, UInt<1>(0h0)) node _T_814 = leq(UInt<1>(0h0), uncommonBits_40) node _T_815 = and(_T_813, _T_814) node _T_816 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_818 = shr(io.in.a.bits.source, 2) node _T_819 = eq(_T_818, UInt<1>(0h1)) node _T_820 = leq(UInt<1>(0h0), uncommonBits_41) node _T_821 = and(_T_819, _T_820) node _T_822 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_823 = and(_T_821, _T_822) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_824 = shr(io.in.a.bits.source, 2) node _T_825 = eq(_T_824, UInt<2>(0h2)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_42) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_829 = and(_T_827, _T_828) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_830 = shr(io.in.a.bits.source, 2) node _T_831 = eq(_T_830, UInt<2>(0h3)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_43) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_835 = and(_T_833, _T_834) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_839 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_840 = or(_T_811, _T_817) node _T_841 = or(_T_840, _T_823) node _T_842 = or(_T_841, _T_829) node _T_843 = or(_T_842, _T_835) node _T_844 = or(_T_843, _T_836) node _T_845 = or(_T_844, _T_837) node _T_846 = or(_T_845, _T_838) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_810, _T_847) node _T_849 = or(UInt<1>(0h0), _T_848) node _T_850 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_851 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<13>(0h1000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = or(_T_855, _T_860) node _T_862 = and(_T_850, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = and(_T_849, _T_863) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_864, UInt<1>(0h1), "") : assert_46 node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(source_ok, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(is_aligned, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_874 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_874, UInt<1>(0h1), "") : assert_49 node _T_878 = eq(io.in.a.bits.mask, mask) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_878, UInt<1>(0h1), "") : assert_50 node _T_882 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_882, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_886 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_886, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_890 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_890 : node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(source_ok_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_894 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_894, UInt<1>(0h1), "") : assert_54 node _T_898 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_898, UInt<1>(0h1), "") : assert_55 node _T_902 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_902, UInt<1>(0h1), "") : assert_56 node _T_906 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_906, UInt<1>(0h1), "") : assert_57 node _T_910 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_910 : node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(source_ok_1, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(sink_ok, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_917 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_917, UInt<1>(0h1), "") : assert_60 node _T_921 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_921, UInt<1>(0h1), "") : assert_61 node _T_925 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_925, UInt<1>(0h1), "") : assert_62 node _T_929 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_929, UInt<1>(0h1), "") : assert_63 node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_934, UInt<1>(0h1), "") : assert_64 node _T_938 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_938 : node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(source_ok_1, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(sink_ok, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_945, UInt<1>(0h1), "") : assert_67 node _T_949 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_949, UInt<1>(0h1), "") : assert_68 node _T_953 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_953, UInt<1>(0h1), "") : assert_69 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = or(_T_957, io.in.d.bits.corrupt) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_958, UInt<1>(0h1), "") : assert_70 node _T_962 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_963 = or(UInt<1>(0h0), _T_962) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_963, UInt<1>(0h1), "") : assert_71 node _T_967 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_967 : node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(source_ok_1, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_971 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_971, UInt<1>(0h1), "") : assert_73 node _T_975 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_975, UInt<1>(0h1), "") : assert_74 node _T_979 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_980 = or(UInt<1>(0h0), _T_979) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_980, UInt<1>(0h1), "") : assert_75 node _T_984 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_984 : node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(source_ok_1, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_988 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_988, UInt<1>(0h1), "") : assert_77 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_993, UInt<1>(0h1), "") : assert_78 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h0), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_998, UInt<1>(0h1), "") : assert_79 node _T_1002 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_81 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_82 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h0), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1019 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1023 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1027 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1031 = eq(a_first, UInt<1>(0h0)) node _T_1032 = and(io.in.a.valid, _T_1031) when _T_1032 : node _T_1033 = eq(io.in.a.bits.opcode, opcode) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_87 node _T_1037 = eq(io.in.a.bits.param, param) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_88 node _T_1041 = eq(io.in.a.bits.size, size) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_89 node _T_1045 = eq(io.in.a.bits.source, source) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_90 node _T_1049 = eq(io.in.a.bits.address, address) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_91 node _T_1053 = and(io.in.a.ready, io.in.a.valid) node _T_1054 = and(_T_1053, a_first) when _T_1054 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1055 = eq(d_first, UInt<1>(0h0)) node _T_1056 = and(io.in.d.valid, _T_1055) when _T_1056 : node _T_1057 = eq(io.in.d.bits.opcode, opcode_1) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_92 node _T_1061 = eq(io.in.d.bits.param, param_1) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_93 node _T_1065 = eq(io.in.d.bits.size, size_1) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_94 node _T_1069 = eq(io.in.d.bits.source, source_1) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_95 node _T_1073 = eq(io.in.d.bits.sink, sink) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_96 node _T_1077 = eq(io.in.d.bits.denied, denied) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_97 node _T_1081 = and(io.in.d.ready, io.in.d.valid) node _T_1082 = and(_T_1081, d_first) when _T_1082 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1083 = and(io.in.a.valid, a_first_1) node _T_1084 = and(_T_1083, UInt<1>(0h1)) when _T_1084 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1085 = and(io.in.a.ready, io.in.a.valid) node _T_1086 = and(_T_1085, a_first_1) node _T_1087 = and(_T_1086, UInt<1>(0h1)) when _T_1087 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1088 = dshr(inflight, io.in.a.bits.source) node _T_1089 = bits(_T_1088, 0, 0) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1094 = and(io.in.d.valid, d_first_1) node _T_1095 = and(_T_1094, UInt<1>(0h1)) node _T_1096 = eq(d_release_ack, UInt<1>(0h0)) node _T_1097 = and(_T_1095, _T_1096) when _T_1097 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1098 = and(io.in.d.ready, io.in.d.valid) node _T_1099 = and(_T_1098, d_first_1) node _T_1100 = and(_T_1099, UInt<1>(0h1)) node _T_1101 = eq(d_release_ack, UInt<1>(0h0)) node _T_1102 = and(_T_1100, _T_1101) when _T_1102 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1103 = and(io.in.d.valid, d_first_1) node _T_1104 = and(_T_1103, UInt<1>(0h1)) node _T_1105 = eq(d_release_ack, UInt<1>(0h0)) node _T_1106 = and(_T_1104, _T_1105) when _T_1106 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1107 = dshr(inflight, io.in.d.bits.source) node _T_1108 = bits(_T_1107, 0, 0) node _T_1109 = or(_T_1108, same_cycle_resp) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1113 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1114 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1115 = or(_T_1113, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_100 node _T_1119 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_101 else : node _T_1123 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1124 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1125 = or(_T_1123, _T_1124) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_102 node _T_1129 = eq(io.in.d.bits.size, a_size_lookup) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_103 node _T_1133 = and(io.in.d.valid, d_first_1) node _T_1134 = and(_T_1133, a_first_1) node _T_1135 = and(_T_1134, io.in.a.valid) node _T_1136 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1137 = and(_T_1135, _T_1136) node _T_1138 = eq(d_release_ack, UInt<1>(0h0)) node _T_1139 = and(_T_1137, _T_1138) when _T_1139 : node _T_1140 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1141 = or(_T_1140, io.in.a.ready) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_104 node _T_1145 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1146 = orr(a_set_wo_ready) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) node _T_1148 = or(_T_1145, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_6 node _T_1152 = orr(inflight) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) node _T_1154 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1155 = or(_T_1153, _T_1154) node _T_1156 = lt(watchdog, plusarg_reader.out) node _T_1157 = or(_T_1155, _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1161 = and(io.in.a.ready, io.in.a.valid) node _T_1162 = and(io.in.d.ready, io.in.d.valid) node _T_1163 = or(_T_1161, _T_1162) when _T_1163 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1164 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1165 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1166 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = and(_T_1164, _T_1167) when _T_1168 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1169 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1170 = and(_T_1169, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1171 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1172 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1173 = and(_T_1171, _T_1172) node _T_1174 = and(_T_1170, _T_1173) when _T_1174 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1175 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1176 = bits(_T_1175, 0, 0) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1181 = and(io.in.d.valid, d_first_2) node _T_1182 = and(_T_1181, UInt<1>(0h1)) node _T_1183 = and(_T_1182, d_release_ack_1) when _T_1183 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1184 = and(io.in.d.ready, io.in.d.valid) node _T_1185 = and(_T_1184, d_first_2) node _T_1186 = and(_T_1185, UInt<1>(0h1)) node _T_1187 = and(_T_1186, d_release_ack_1) when _T_1187 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1188 = and(io.in.d.valid, d_first_2) node _T_1189 = and(_T_1188, UInt<1>(0h1)) node _T_1190 = and(_T_1189, d_release_ack_1) when _T_1190 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1191 = dshr(inflight_1, io.in.d.bits.source) node _T_1192 = bits(_T_1191, 0, 0) node _T_1193 = or(_T_1192, same_cycle_resp_1) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1197 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_109 else : node _T_1201 = eq(io.in.d.bits.size, c_size_lookup) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_110 node _T_1205 = and(io.in.d.valid, d_first_2) node _T_1206 = and(_T_1205, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1207 = and(_T_1206, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1208 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = and(_T_1209, d_release_ack_1) node _T_1211 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1212 = and(_T_1210, _T_1211) when _T_1212 : node _T_1213 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1214 = or(_T_1213, _WIRE_27.ready) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_111 node _T_1218 = orr(c_set_wo_ready) when _T_1218 : node _T_1219 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_7 node _T_1223 = orr(inflight_1) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) node _T_1225 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1226 = or(_T_1224, _T_1225) node _T_1227 = lt(watchdog_1, plusarg_reader_1.out) node _T_1228 = or(_T_1226, _T_1227) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1232 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1233 = and(io.in.d.ready, io.in.d.valid) node _T_1234 = or(_T_1232, _T_1233) when _T_1234 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1161 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1161; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1161; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1234 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1234; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1234; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1234; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1087 = _T_1161 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1087 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1087 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1087 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1087 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1087 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1133 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1133 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1102 = _T_1234 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1102 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1102 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1102 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1205 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1205 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1187 = _T_1234 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1187 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1187 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1187 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Tile_156 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_412 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_156( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_412 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SBToTL : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} input rf_reset : Reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset sbState : UInt, clock, reset, UInt<1>(0h0) inst d_q of Queue2_TLBundleD_a32d8s1k3z4u connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect d_q.io.enq.bits.data, nodeOut.d.bits.data connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect d_q.io.enq.bits.source, nodeOut.d.bits.source connect d_q.io.enq.bits.size, nodeOut.d.bits.size connect d_q.io.enq.bits.param, nodeOut.d.bits.param connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, d_q.io.enq.ready node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 wire muxedData : UInt<8> connect muxedData, UInt<8>(0h0) regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) wire vecData : UInt<8>[8] node _vecData_0_T = bits(io.dataIn, 7, 0) connect vecData[0], _vecData_0_T node _vecData_1_T = bits(io.dataIn, 15, 8) connect vecData[1], _vecData_1_T node _vecData_2_T = bits(io.dataIn, 23, 16) connect vecData[2], _vecData_2_T node _vecData_3_T = bits(io.dataIn, 31, 24) connect vecData[3], _vecData_3_T node _vecData_4_T = bits(io.dataIn, 39, 32) connect vecData[4], _vecData_4_T node _vecData_5_T = bits(io.dataIn, 47, 40) connect vecData[5], _vecData_5_T node _vecData_6_T = bits(io.dataIn, 55, 48) connect vecData[6], _vecData_6_T node _vecData_7_T = bits(io.dataIn, 63, 56) connect vecData[7], _vecData_7_T node _muxedData_T = bits(counter, 2, 0) connect muxedData, vecData[_muxedData_T] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2000)) node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<10>(0h200))) node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<18>(0h2f000))) node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<28>(0hc000000)) node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44) node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<27>(0h4000000))) node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46) node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<29>(0h10020000)) node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49) node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51) node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _rdLegal_addr_T_55 = cvt(_rdLegal_addr_T_54) node _rdLegal_addr_T_56 = and(_rdLegal_addr_T_55, asSInt(UInt<29>(0h10000000))) node _rdLegal_addr_T_57 = asSInt(_rdLegal_addr_T_56) node _rdLegal_addr_T_58 = eq(_rdLegal_addr_T_57, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_59 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) node _rdLegal_addr_T_60 = or(_rdLegal_addr_T_59, _rdLegal_addr_T_18) node _rdLegal_addr_T_61 = or(_rdLegal_addr_T_60, _rdLegal_addr_T_23) node _rdLegal_addr_T_62 = or(_rdLegal_addr_T_61, _rdLegal_addr_T_28) node _rdLegal_addr_T_63 = or(_rdLegal_addr_T_62, _rdLegal_addr_T_33) node _rdLegal_addr_T_64 = or(_rdLegal_addr_T_63, _rdLegal_addr_T_38) node _rdLegal_addr_T_65 = or(_rdLegal_addr_T_64, _rdLegal_addr_T_43) node _rdLegal_addr_T_66 = or(_rdLegal_addr_T_65, _rdLegal_addr_T_48) node _rdLegal_addr_T_67 = or(_rdLegal_addr_T_66, _rdLegal_addr_T_53) node _rdLegal_addr_T_68 = or(_rdLegal_addr_T_67, _rdLegal_addr_T_58) node _rdLegal_addr_T_69 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_68) node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_69) node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2000)) node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<10>(0h200))) node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<18>(0h2f000))) node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2010000)) node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0hc000000)) node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39) node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<27>(0h4000000))) node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41) node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h10020000)) node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44) node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46) node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) node _wrLegal_addr_T_50 = cvt(_wrLegal_addr_T_49) node _wrLegal_addr_T_51 = and(_wrLegal_addr_T_50, asSInt(UInt<29>(0h10000000))) node _wrLegal_addr_T_52 = asSInt(_wrLegal_addr_T_51) node _wrLegal_addr_T_53 = eq(_wrLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_54 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) node _wrLegal_addr_T_55 = or(_wrLegal_addr_T_54, _wrLegal_addr_T_18) node _wrLegal_addr_T_56 = or(_wrLegal_addr_T_55, _wrLegal_addr_T_23) node _wrLegal_addr_T_57 = or(_wrLegal_addr_T_56, _wrLegal_addr_T_28) node _wrLegal_addr_T_58 = or(_wrLegal_addr_T_57, _wrLegal_addr_T_33) node _wrLegal_addr_T_59 = or(_wrLegal_addr_T_58, _wrLegal_addr_T_38) node _wrLegal_addr_T_60 = or(_wrLegal_addr_T_59, _wrLegal_addr_T_43) node _wrLegal_addr_T_61 = or(_wrLegal_addr_T_60, _wrLegal_addr_T_48) node _wrLegal_addr_T_62 = or(_wrLegal_addr_T_61, _wrLegal_addr_T_53) node _wrLegal_addr_T_63 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_62) node _wrLegal_addr_T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) node _wrLegal_addr_T_65 = xor(io.addrIn, UInt<17>(0h10000)) node _wrLegal_addr_T_66 = cvt(_wrLegal_addr_T_65) node _wrLegal_addr_T_67 = and(_wrLegal_addr_T_66, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_68 = asSInt(_wrLegal_addr_T_67) node _wrLegal_addr_T_69 = eq(_wrLegal_addr_T_68, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_70 = and(_wrLegal_addr_T_64, _wrLegal_addr_T_69) node _wrLegal_addr_T_71 = or(UInt<1>(0h0), _wrLegal_addr_T_63) node wrLegal_addr = or(_wrLegal_addr_T_71, _wrLegal_addr_T_70) node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) node _gbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) node _gbits_legal_T_24 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h98013000))) node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) node _gbits_legal_T_29 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) node _gbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2000000)) node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) node _gbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) node _gbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_45 = cvt(_gbits_legal_T_44) node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46) node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0))) node _gbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _gbits_legal_T_50 = cvt(_gbits_legal_T_49) node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51) node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0))) node _gbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _gbits_legal_T_55 = cvt(_gbits_legal_T_54) node _gbits_legal_T_56 = and(_gbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _gbits_legal_T_57 = asSInt(_gbits_legal_T_56) node _gbits_legal_T_58 = eq(_gbits_legal_T_57, asSInt(UInt<1>(0h0))) node _gbits_legal_T_59 = or(_gbits_legal_T_18, _gbits_legal_T_23) node _gbits_legal_T_60 = or(_gbits_legal_T_59, _gbits_legal_T_28) node _gbits_legal_T_61 = or(_gbits_legal_T_60, _gbits_legal_T_33) node _gbits_legal_T_62 = or(_gbits_legal_T_61, _gbits_legal_T_38) node _gbits_legal_T_63 = or(_gbits_legal_T_62, _gbits_legal_T_43) node _gbits_legal_T_64 = or(_gbits_legal_T_63, _gbits_legal_T_48) node _gbits_legal_T_65 = or(_gbits_legal_T_64, _gbits_legal_T_53) node _gbits_legal_T_66 = or(_gbits_legal_T_65, _gbits_legal_T_58) node _gbits_legal_T_67 = and(_gbits_legal_T_13, _gbits_legal_T_66) node _gbits_legal_T_68 = or(UInt<1>(0h0), _gbits_legal_T_9) node gbits_legal = or(_gbits_legal_T_68, _gbits_legal_T_67) wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect gbits.opcode, UInt<3>(0h4) connect gbits.param, UInt<1>(0h0) connect gbits.size, io.sizeIn connect gbits.source, UInt<1>(0h0) connect gbits.address, io.addrIn node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect gbits.mask, UInt<1>(0h1) invalidate gbits.data connect gbits.corrupt, UInt<1>(0h0) node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h9a103000))) node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39) node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41) node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44) node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46) node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _pfbits_legal_T_50 = cvt(_pfbits_legal_T_49) node _pfbits_legal_T_51 = and(_pfbits_legal_T_50, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_52 = asSInt(_pfbits_legal_T_51) node _pfbits_legal_T_53 = eq(_pfbits_legal_T_52, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _pfbits_legal_T_55 = cvt(_pfbits_legal_T_54) node _pfbits_legal_T_56 = and(_pfbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _pfbits_legal_T_57 = asSInt(_pfbits_legal_T_56) node _pfbits_legal_T_58 = eq(_pfbits_legal_T_57, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_59 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) node _pfbits_legal_T_60 = or(_pfbits_legal_T_59, _pfbits_legal_T_28) node _pfbits_legal_T_61 = or(_pfbits_legal_T_60, _pfbits_legal_T_33) node _pfbits_legal_T_62 = or(_pfbits_legal_T_61, _pfbits_legal_T_38) node _pfbits_legal_T_63 = or(_pfbits_legal_T_62, _pfbits_legal_T_43) node _pfbits_legal_T_64 = or(_pfbits_legal_T_63, _pfbits_legal_T_48) node _pfbits_legal_T_65 = or(_pfbits_legal_T_64, _pfbits_legal_T_53) node _pfbits_legal_T_66 = or(_pfbits_legal_T_65, _pfbits_legal_T_58) node _pfbits_legal_T_67 = and(_pfbits_legal_T_13, _pfbits_legal_T_66) node _pfbits_legal_T_68 = or(UInt<1>(0h0), UInt<1>(0h0)) node _pfbits_legal_T_69 = xor(io.addrIn, UInt<17>(0h10000)) node _pfbits_legal_T_70 = cvt(_pfbits_legal_T_69) node _pfbits_legal_T_71 = and(_pfbits_legal_T_70, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_72 = asSInt(_pfbits_legal_T_71) node _pfbits_legal_T_73 = eq(_pfbits_legal_T_72, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_74 = and(_pfbits_legal_T_68, _pfbits_legal_T_73) node _pfbits_legal_T_75 = or(UInt<1>(0h0), _pfbits_legal_T_9) node _pfbits_legal_T_76 = or(_pfbits_legal_T_75, _pfbits_legal_T_67) node pfbits_legal = or(_pfbits_legal_T_76, _pfbits_legal_T_74) wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect pfbits.opcode, UInt<1>(0h0) connect pfbits.param, UInt<1>(0h0) connect pfbits.size, io.sizeIn connect pfbits.source, UInt<1>(0h0) connect pfbits.address, io.addrIn node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect pfbits.mask, UInt<1>(0h1) connect pfbits.data, muxedData connect pfbits.corrupt, UInt<1>(0h0) connect io.rdLegal, rdLegal_addr connect io.wrLegal, wrLegal_addr connect io.sbStateOut, sbState node _T = eq(sbState, UInt<1>(0h1)) when _T : connect nodeOut.a.bits, gbits else : connect nodeOut.a.bits, pfbits node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) connect io.respError, respError node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) node _txLast_T_2 = tail(_txLast_T_1, 1) node txLast = eq(counter, _txLast_T_2) node _counter_T = or(wrTxValid, rdTxValid) node _counter_T_1 = and(_counter_T, txLast) node _counter_T_2 = or(wrTxValid, rdTxValid) node _counter_T_3 = add(counter, UInt<1>(0h1)) node _counter_T_4 = tail(_counter_T_3, 1) node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) connect counter, _counter_T_6 node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) connect io.rdLoad[0], _io_rdLoad_0_T_1 node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) connect io.rdLoad[1], _io_rdLoad_1_T_1 node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) connect io.rdLoad[2], _io_rdLoad_2_T_1 node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) connect io.rdLoad[3], _io_rdLoad_3_T_1 node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) connect io.rdLoad[4], _io_rdLoad_4_T_1 node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) connect io.rdLoad[5], _io_rdLoad_5_T_1 node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) connect io.rdLoad[6], _io_rdLoad_6_T_1 node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) connect io.rdLoad[7], _io_rdLoad_7_T_1 node _T_1 = eq(sbState, UInt<1>(0h0)) when _T_1 : node _sbState_T = and(io.rdEn, io.rdLegal) node _sbState_T_1 = and(io.wrEn, io.wrLegal) node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) connect sbState, _sbState_T_3 else : node _T_2 = eq(sbState, UInt<1>(0h1)) when _T_2 : node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) connect sbState, _sbState_T_5 else : node _T_3 = eq(sbState, UInt<2>(0h2)) when _T_3 : node _sbState_T_6 = and(wrTxValid, txLast) node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) connect sbState, _sbState_T_7 else : node _T_4 = eq(sbState, UInt<2>(0h3)) when _T_4 : node _sbState_T_8 = and(rdTxValid, txLast) node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) connect sbState, _sbState_T_9 else : node _T_5 = eq(sbState, UInt<3>(0h4)) when _T_5 : node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) connect sbState, _sbState_T_11 node _io_rdDone_T = and(rdTxValid, txLast) connect io.rdDone, _io_rdDone_T node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) connect io.wrDone, _io_wrDone_T_2 connect io.dataOut, d_q.io.deq.bits.data node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T_6 = eq(sbState, UInt<1>(0h0)) node _T_7 = eq(sbState, UInt<1>(0h1)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(sbState, UInt<2>(0h2)) node _T_10 = or(_T_8, _T_9) node _T_11 = eq(sbState, UInt<2>(0h3)) node _T_12 = or(_T_10, _T_11) node _T_13 = eq(sbState, UInt<3>(0h4)) node _T_14 = or(_T_12, _T_13) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert node _T_18 = eq(sbState, UInt<1>(0h0)) node _T_19 = eq(sbState, UInt<1>(0h1)) node _T_20 = eq(sbState, UInt<2>(0h2)) node _T_21 = eq(sbState, UInt<2>(0h3)) node _T_22 = eq(sbState, UInt<3>(0h4)) node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) node _T_24 = and(io.rdEn, _T_23) node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) node _T_26 = and(io.wrEn, _T_25) extmodule plusarg_reader_97 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module SBToTL( // @[SBA.scala:273:9] input clock, // @[SBA.scala:273:9] input reset, // @[SBA.scala:273:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_rdEn, // @[SBA.scala:274:16] input io_wrEn, // @[SBA.scala:274:16] input [127:0] io_addrIn, // @[SBA.scala:274:16] input [127:0] io_dataIn, // @[SBA.scala:274:16] input [2:0] io_sizeIn, // @[SBA.scala:274:16] output io_rdLegal, // @[SBA.scala:274:16] output io_wrLegal, // @[SBA.scala:274:16] output io_rdDone, // @[SBA.scala:274:16] output io_wrDone, // @[SBA.scala:274:16] output io_respError, // @[SBA.scala:274:16] output [7:0] io_dataOut, // @[SBA.scala:274:16] output io_rdLoad_0, // @[SBA.scala:274:16] output io_rdLoad_1, // @[SBA.scala:274:16] output io_rdLoad_2, // @[SBA.scala:274:16] output io_rdLoad_3, // @[SBA.scala:274:16] output io_rdLoad_4, // @[SBA.scala:274:16] output io_rdLoad_5, // @[SBA.scala:274:16] output io_rdLoad_6, // @[SBA.scala:274:16] output io_rdLoad_7, // @[SBA.scala:274:16] output [2:0] io_sbStateOut // @[SBA.scala:274:16] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] reg [2:0] sbState; // @[SBA.scala:295:26] wire _rdTxValid_T = sbState == 3'h3; // @[SBA.scala:295:26, :299:25] wire _io_wrDone_T = sbState == 3'h4; // @[SBA.scala:295:26, :299:62] wire d_q_io_deq_ready = _rdTxValid_T | _io_wrDone_T; // @[SBA.scala:299:{25,50,62}] reg [3:0] counter; // @[SBA.scala:307:26] wire [7:0][7:0] _GEN = {{io_dataIn[63:56]}, {io_dataIn[55:48]}, {io_dataIn[47:40]}, {io_dataIn[39:32]}, {io_dataIn[31:24]}, {io_dataIn[23:16]}, {io_dataIn[15:8]}, {io_dataIn[7:0]}}; // @[SBA.scala:309:63, :310:15] wire [118:0] _GEN_0 = {io_addrIn[127:14], io_addrIn[13:9] ^ 5'h10}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_1 = {io_addrIn[127:14], ~(io_addrIn[13:12])}; // @[Parameters.scala:137:{31,41,46}] wire [114:0] _GEN_2 = {io_addrIn[127:21], io_addrIn[20:17] ^ 4'h8, io_addrIn[15:12]}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_3 = {io_addrIn[127:26], io_addrIn[25:16] ^ 10'h200}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_4 = {io_addrIn[127:26], io_addrIn[25:12] ^ 14'h2010}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_5 = {io_addrIn[127:28], io_addrIn[27:16] ^ 12'h800}; // @[Parameters.scala:137:{31,41,46}] wire [101:0] _GEN_6 = {io_addrIn[127:28], ~(io_addrIn[27:26])}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_7 = {io_addrIn[127:29], io_addrIn[28:12] ^ 17'h10020}; // @[Parameters.scala:137:{31,41,46}] wire [99:0] _GEN_8 = {io_addrIn[127:32], io_addrIn[31:28] ^ 4'h8}; // @[Parameters.scala:137:{31,41,46}] wire io_rdLegal_0 = ~(|(io_addrIn[127:13])) | ~(|_GEN_0) | ~(|_GEN_1) | {io_addrIn[127:17], ~(io_addrIn[16])} == 112'h0 | ~(|_GEN_2) | ~(|_GEN_3) | ~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8); // @[Parameters.scala:685:42] wire io_wrLegal_0 = ~(|(io_addrIn[127:13])) | ~(|_GEN_0) | ~(|_GEN_1) | ~(|_GEN_2) | ~(|_GEN_3) | ~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8); // @[Parameters.scala:685:42] wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18] wire _nodeOut_a_valid_T_1 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29] wire rdTxValid = _rdTxValid_T & _d_q_io_deq_valid & d_q_io_deq_ready; // @[Decoupled.scala:362:21] wire txLast = {4'h0, counter} == (8'h1 << io_sizeIn) - 8'h1; // @[SBA.scala:307:26, :340:{29,39,53}] wire _GEN_9 = sbState == 3'h0; // @[SBA.scala:295:26, :349:19] wire nodeOut_a_valid = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[SBA.scala:322:18, :338:29, :366:52]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e11_s53_4 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<107>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 106, 106) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 105, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 161, 54) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 54, 53) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 159, 55) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 53, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 54, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 107, 50) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 52, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 2) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[14] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 27, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node _CDom_reduced4SigExtra_reducedVec_7_T = bits(_CDom_reduced4SigExtra_T_1, 31, 28) node _CDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_7_T) connect CDom_reduced4SigExtra_reducedVec[7], _CDom_reduced4SigExtra_reducedVec_7_T_1 node _CDom_reduced4SigExtra_reducedVec_8_T = bits(_CDom_reduced4SigExtra_T_1, 35, 32) node _CDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_8_T) connect CDom_reduced4SigExtra_reducedVec[8], _CDom_reduced4SigExtra_reducedVec_8_T_1 node _CDom_reduced4SigExtra_reducedVec_9_T = bits(_CDom_reduced4SigExtra_T_1, 39, 36) node _CDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_9_T) connect CDom_reduced4SigExtra_reducedVec[9], _CDom_reduced4SigExtra_reducedVec_9_T_1 node _CDom_reduced4SigExtra_reducedVec_10_T = bits(_CDom_reduced4SigExtra_T_1, 43, 40) node _CDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_10_T) connect CDom_reduced4SigExtra_reducedVec[10], _CDom_reduced4SigExtra_reducedVec_10_T_1 node _CDom_reduced4SigExtra_reducedVec_11_T = bits(_CDom_reduced4SigExtra_T_1, 47, 44) node _CDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_11_T) connect CDom_reduced4SigExtra_reducedVec[11], _CDom_reduced4SigExtra_reducedVec_11_T_1 node _CDom_reduced4SigExtra_reducedVec_12_T = bits(_CDom_reduced4SigExtra_T_1, 51, 48) node _CDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_12_T) connect CDom_reduced4SigExtra_reducedVec[12], _CDom_reduced4SigExtra_reducedVec_12_T_1 node _CDom_reduced4SigExtra_reducedVec_13_T = bits(_CDom_reduced4SigExtra_T_1, 54, 52) node _CDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_13_T) connect CDom_reduced4SigExtra_reducedVec[13], _CDom_reduced4SigExtra_reducedVec_13_T_1 node CDom_reduced4SigExtra_lo_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo_lo = cat(CDom_reduced4SigExtra_lo_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_lo_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_lo_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_lo_hi_hi, CDom_reduced4SigExtra_lo_hi_lo) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_lo_lo) node CDom_reduced4SigExtra_hi_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[9], CDom_reduced4SigExtra_reducedVec[8]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_hi_lo_hi, CDom_reduced4SigExtra_reducedVec[7]) node CDom_reduced4SigExtra_hi_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[11], CDom_reduced4SigExtra_reducedVec[10]) node CDom_reduced4SigExtra_hi_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[13], CDom_reduced4SigExtra_reducedVec[12]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_hi_hi_hi, CDom_reduced4SigExtra_hi_hi_lo) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 13, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 7, 0) node _CDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) node _CDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _CDom_reduced4SigExtra_T_7) node _CDom_reduced4SigExtra_T_9 = shr(_CDom_reduced4SigExtra_T_6, 4) node _CDom_reduced4SigExtra_T_10 = and(_CDom_reduced4SigExtra_T_9, _CDom_reduced4SigExtra_T_8) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 0) node _CDom_reduced4SigExtra_T_12 = shl(_CDom_reduced4SigExtra_T_11, 4) node _CDom_reduced4SigExtra_T_13 = not(_CDom_reduced4SigExtra_T_8) node _CDom_reduced4SigExtra_T_14 = and(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = or(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_8, 5, 0) node _CDom_reduced4SigExtra_T_17 = shl(_CDom_reduced4SigExtra_T_16, 2) node _CDom_reduced4SigExtra_T_18 = xor(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_17) node _CDom_reduced4SigExtra_T_19 = shr(_CDom_reduced4SigExtra_T_15, 2) node _CDom_reduced4SigExtra_T_20 = and(_CDom_reduced4SigExtra_T_19, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_21 = bits(_CDom_reduced4SigExtra_T_15, 5, 0) node _CDom_reduced4SigExtra_T_22 = shl(_CDom_reduced4SigExtra_T_21, 2) node _CDom_reduced4SigExtra_T_23 = not(_CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_24 = and(_CDom_reduced4SigExtra_T_22, _CDom_reduced4SigExtra_T_23) node _CDom_reduced4SigExtra_T_25 = or(_CDom_reduced4SigExtra_T_20, _CDom_reduced4SigExtra_T_24) node _CDom_reduced4SigExtra_T_26 = bits(_CDom_reduced4SigExtra_T_18, 6, 0) node _CDom_reduced4SigExtra_T_27 = shl(_CDom_reduced4SigExtra_T_26, 1) node _CDom_reduced4SigExtra_T_28 = xor(_CDom_reduced4SigExtra_T_18, _CDom_reduced4SigExtra_T_27) node _CDom_reduced4SigExtra_T_29 = shr(_CDom_reduced4SigExtra_T_25, 1) node _CDom_reduced4SigExtra_T_30 = and(_CDom_reduced4SigExtra_T_29, _CDom_reduced4SigExtra_T_28) node _CDom_reduced4SigExtra_T_31 = bits(_CDom_reduced4SigExtra_T_25, 6, 0) node _CDom_reduced4SigExtra_T_32 = shl(_CDom_reduced4SigExtra_T_31, 1) node _CDom_reduced4SigExtra_T_33 = not(_CDom_reduced4SigExtra_T_28) node _CDom_reduced4SigExtra_T_34 = and(_CDom_reduced4SigExtra_T_32, _CDom_reduced4SigExtra_T_33) node _CDom_reduced4SigExtra_T_35 = or(_CDom_reduced4SigExtra_T_30, _CDom_reduced4SigExtra_T_34) node _CDom_reduced4SigExtra_T_36 = bits(_CDom_reduced4SigExtra_T_5, 12, 8) node _CDom_reduced4SigExtra_T_37 = bits(_CDom_reduced4SigExtra_T_36, 3, 0) node _CDom_reduced4SigExtra_T_38 = bits(_CDom_reduced4SigExtra_T_37, 1, 0) node _CDom_reduced4SigExtra_T_39 = bits(_CDom_reduced4SigExtra_T_38, 0, 0) node _CDom_reduced4SigExtra_T_40 = bits(_CDom_reduced4SigExtra_T_38, 1, 1) node _CDom_reduced4SigExtra_T_41 = cat(_CDom_reduced4SigExtra_T_39, _CDom_reduced4SigExtra_T_40) node _CDom_reduced4SigExtra_T_42 = bits(_CDom_reduced4SigExtra_T_37, 3, 2) node _CDom_reduced4SigExtra_T_43 = bits(_CDom_reduced4SigExtra_T_42, 0, 0) node _CDom_reduced4SigExtra_T_44 = bits(_CDom_reduced4SigExtra_T_42, 1, 1) node _CDom_reduced4SigExtra_T_45 = cat(_CDom_reduced4SigExtra_T_43, _CDom_reduced4SigExtra_T_44) node _CDom_reduced4SigExtra_T_46 = cat(_CDom_reduced4SigExtra_T_41, _CDom_reduced4SigExtra_T_45) node _CDom_reduced4SigExtra_T_47 = bits(_CDom_reduced4SigExtra_T_36, 4, 4) node _CDom_reduced4SigExtra_T_48 = cat(_CDom_reduced4SigExtra_T_46, _CDom_reduced4SigExtra_T_47) node _CDom_reduced4SigExtra_T_49 = cat(_CDom_reduced4SigExtra_T_35, _CDom_reduced4SigExtra_T_48) node _CDom_reduced4SigExtra_T_50 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_49) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_50) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 109, 109) node _notCDom_absSigSum_T = bits(sigSum, 108, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 108, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[55] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 51, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_26_T = bits(notCDom_absSigSum, 53, 52) node _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_26_T) connect notCDom_reduced2AbsSigSum_reducedVec[26], _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_27_T = bits(notCDom_absSigSum, 55, 54) node _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_27_T) connect notCDom_reduced2AbsSigSum_reducedVec[27], _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_28_T = bits(notCDom_absSigSum, 57, 56) node _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_28_T) connect notCDom_reduced2AbsSigSum_reducedVec[28], _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_29_T = bits(notCDom_absSigSum, 59, 58) node _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_29_T) connect notCDom_reduced2AbsSigSum_reducedVec[29], _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_30_T = bits(notCDom_absSigSum, 61, 60) node _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_30_T) connect notCDom_reduced2AbsSigSum_reducedVec[30], _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_31_T = bits(notCDom_absSigSum, 63, 62) node _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_31_T) connect notCDom_reduced2AbsSigSum_reducedVec[31], _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_32_T = bits(notCDom_absSigSum, 65, 64) node _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_32_T) connect notCDom_reduced2AbsSigSum_reducedVec[32], _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_33_T = bits(notCDom_absSigSum, 67, 66) node _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_33_T) connect notCDom_reduced2AbsSigSum_reducedVec[33], _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_34_T = bits(notCDom_absSigSum, 69, 68) node _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_34_T) connect notCDom_reduced2AbsSigSum_reducedVec[34], _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_35_T = bits(notCDom_absSigSum, 71, 70) node _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_35_T) connect notCDom_reduced2AbsSigSum_reducedVec[35], _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_36_T = bits(notCDom_absSigSum, 73, 72) node _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_36_T) connect notCDom_reduced2AbsSigSum_reducedVec[36], _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_37_T = bits(notCDom_absSigSum, 75, 74) node _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_37_T) connect notCDom_reduced2AbsSigSum_reducedVec[37], _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_38_T = bits(notCDom_absSigSum, 77, 76) node _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_38_T) connect notCDom_reduced2AbsSigSum_reducedVec[38], _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_39_T = bits(notCDom_absSigSum, 79, 78) node _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_39_T) connect notCDom_reduced2AbsSigSum_reducedVec[39], _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_40_T = bits(notCDom_absSigSum, 81, 80) node _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_40_T) connect notCDom_reduced2AbsSigSum_reducedVec[40], _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_41_T = bits(notCDom_absSigSum, 83, 82) node _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_41_T) connect notCDom_reduced2AbsSigSum_reducedVec[41], _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_42_T = bits(notCDom_absSigSum, 85, 84) node _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_42_T) connect notCDom_reduced2AbsSigSum_reducedVec[42], _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_43_T = bits(notCDom_absSigSum, 87, 86) node _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_43_T) connect notCDom_reduced2AbsSigSum_reducedVec[43], _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_44_T = bits(notCDom_absSigSum, 89, 88) node _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_44_T) connect notCDom_reduced2AbsSigSum_reducedVec[44], _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_45_T = bits(notCDom_absSigSum, 91, 90) node _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_45_T) connect notCDom_reduced2AbsSigSum_reducedVec[45], _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_46_T = bits(notCDom_absSigSum, 93, 92) node _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_46_T) connect notCDom_reduced2AbsSigSum_reducedVec[46], _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_47_T = bits(notCDom_absSigSum, 95, 94) node _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_47_T) connect notCDom_reduced2AbsSigSum_reducedVec[47], _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_48_T = bits(notCDom_absSigSum, 97, 96) node _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_48_T) connect notCDom_reduced2AbsSigSum_reducedVec[48], _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_49_T = bits(notCDom_absSigSum, 99, 98) node _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_49_T) connect notCDom_reduced2AbsSigSum_reducedVec[49], _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_50_T = bits(notCDom_absSigSum, 101, 100) node _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_50_T) connect notCDom_reduced2AbsSigSum_reducedVec[50], _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_51_T = bits(notCDom_absSigSum, 103, 102) node _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_51_T) connect notCDom_reduced2AbsSigSum_reducedVec[51], _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_52_T = bits(notCDom_absSigSum, 105, 104) node _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_52_T) connect notCDom_reduced2AbsSigSum_reducedVec[52], _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_53_T = bits(notCDom_absSigSum, 107, 106) node _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_53_T) connect notCDom_reduced2AbsSigSum_reducedVec[53], _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_54_T = bits(notCDom_absSigSum, 108, 108) node _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_54_T) connect notCDom_reduced2AbsSigSum_reducedVec[54], _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_lo_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[17], notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[19], notCDom_reduced2AbsSigSum_reducedVec[18]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[22], notCDom_reduced2AbsSigSum_reducedVec[21]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[24], notCDom_reduced2AbsSigSum_reducedVec[23]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[26], notCDom_reduced2AbsSigSum_reducedVec[25]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[29], notCDom_reduced2AbsSigSum_reducedVec[28]) node notCDom_reduced2AbsSigSum_hi_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[27]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[31], notCDom_reduced2AbsSigSum_reducedVec[30]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[33], notCDom_reduced2AbsSigSum_reducedVec[32]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[36], notCDom_reduced2AbsSigSum_reducedVec[35]) node notCDom_reduced2AbsSigSum_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[34]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[38], notCDom_reduced2AbsSigSum_reducedVec[37]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[40], notCDom_reduced2AbsSigSum_reducedVec[39]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[43], notCDom_reduced2AbsSigSum_reducedVec[42]) node notCDom_reduced2AbsSigSum_hi_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[41]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[45], notCDom_reduced2AbsSigSum_reducedVec[44]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[47], notCDom_reduced2AbsSigSum_reducedVec[46]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[50], notCDom_reduced2AbsSigSum_reducedVec[49]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[48]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[52], notCDom_reduced2AbsSigSum_reducedVec[51]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[54], notCDom_reduced2AbsSigSum_reducedVec[53]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = bits(notCDom_reduced2AbsSigSum, 26, 26) node _notCDom_normDistReduced2_T_27 = bits(notCDom_reduced2AbsSigSum, 27, 27) node _notCDom_normDistReduced2_T_28 = bits(notCDom_reduced2AbsSigSum, 28, 28) node _notCDom_normDistReduced2_T_29 = bits(notCDom_reduced2AbsSigSum, 29, 29) node _notCDom_normDistReduced2_T_30 = bits(notCDom_reduced2AbsSigSum, 30, 30) node _notCDom_normDistReduced2_T_31 = bits(notCDom_reduced2AbsSigSum, 31, 31) node _notCDom_normDistReduced2_T_32 = bits(notCDom_reduced2AbsSigSum, 32, 32) node _notCDom_normDistReduced2_T_33 = bits(notCDom_reduced2AbsSigSum, 33, 33) node _notCDom_normDistReduced2_T_34 = bits(notCDom_reduced2AbsSigSum, 34, 34) node _notCDom_normDistReduced2_T_35 = bits(notCDom_reduced2AbsSigSum, 35, 35) node _notCDom_normDistReduced2_T_36 = bits(notCDom_reduced2AbsSigSum, 36, 36) node _notCDom_normDistReduced2_T_37 = bits(notCDom_reduced2AbsSigSum, 37, 37) node _notCDom_normDistReduced2_T_38 = bits(notCDom_reduced2AbsSigSum, 38, 38) node _notCDom_normDistReduced2_T_39 = bits(notCDom_reduced2AbsSigSum, 39, 39) node _notCDom_normDistReduced2_T_40 = bits(notCDom_reduced2AbsSigSum, 40, 40) node _notCDom_normDistReduced2_T_41 = bits(notCDom_reduced2AbsSigSum, 41, 41) node _notCDom_normDistReduced2_T_42 = bits(notCDom_reduced2AbsSigSum, 42, 42) node _notCDom_normDistReduced2_T_43 = bits(notCDom_reduced2AbsSigSum, 43, 43) node _notCDom_normDistReduced2_T_44 = bits(notCDom_reduced2AbsSigSum, 44, 44) node _notCDom_normDistReduced2_T_45 = bits(notCDom_reduced2AbsSigSum, 45, 45) node _notCDom_normDistReduced2_T_46 = bits(notCDom_reduced2AbsSigSum, 46, 46) node _notCDom_normDistReduced2_T_47 = bits(notCDom_reduced2AbsSigSum, 47, 47) node _notCDom_normDistReduced2_T_48 = bits(notCDom_reduced2AbsSigSum, 48, 48) node _notCDom_normDistReduced2_T_49 = bits(notCDom_reduced2AbsSigSum, 49, 49) node _notCDom_normDistReduced2_T_50 = bits(notCDom_reduced2AbsSigSum, 50, 50) node _notCDom_normDistReduced2_T_51 = bits(notCDom_reduced2AbsSigSum, 51, 51) node _notCDom_normDistReduced2_T_52 = bits(notCDom_reduced2AbsSigSum, 52, 52) node _notCDom_normDistReduced2_T_53 = bits(notCDom_reduced2AbsSigSum, 53, 53) node _notCDom_normDistReduced2_T_54 = bits(notCDom_reduced2AbsSigSum, 54, 54) node _notCDom_normDistReduced2_T_55 = mux(_notCDom_normDistReduced2_T_1, UInt<6>(0h35), UInt<6>(0h36)) node _notCDom_normDistReduced2_T_56 = mux(_notCDom_normDistReduced2_T_2, UInt<6>(0h34), _notCDom_normDistReduced2_T_55) node _notCDom_normDistReduced2_T_57 = mux(_notCDom_normDistReduced2_T_3, UInt<6>(0h33), _notCDom_normDistReduced2_T_56) node _notCDom_normDistReduced2_T_58 = mux(_notCDom_normDistReduced2_T_4, UInt<6>(0h32), _notCDom_normDistReduced2_T_57) node _notCDom_normDistReduced2_T_59 = mux(_notCDom_normDistReduced2_T_5, UInt<6>(0h31), _notCDom_normDistReduced2_T_58) node _notCDom_normDistReduced2_T_60 = mux(_notCDom_normDistReduced2_T_6, UInt<6>(0h30), _notCDom_normDistReduced2_T_59) node _notCDom_normDistReduced2_T_61 = mux(_notCDom_normDistReduced2_T_7, UInt<6>(0h2f), _notCDom_normDistReduced2_T_60) node _notCDom_normDistReduced2_T_62 = mux(_notCDom_normDistReduced2_T_8, UInt<6>(0h2e), _notCDom_normDistReduced2_T_61) node _notCDom_normDistReduced2_T_63 = mux(_notCDom_normDistReduced2_T_9, UInt<6>(0h2d), _notCDom_normDistReduced2_T_62) node _notCDom_normDistReduced2_T_64 = mux(_notCDom_normDistReduced2_T_10, UInt<6>(0h2c), _notCDom_normDistReduced2_T_63) node _notCDom_normDistReduced2_T_65 = mux(_notCDom_normDistReduced2_T_11, UInt<6>(0h2b), _notCDom_normDistReduced2_T_64) node _notCDom_normDistReduced2_T_66 = mux(_notCDom_normDistReduced2_T_12, UInt<6>(0h2a), _notCDom_normDistReduced2_T_65) node _notCDom_normDistReduced2_T_67 = mux(_notCDom_normDistReduced2_T_13, UInt<6>(0h29), _notCDom_normDistReduced2_T_66) node _notCDom_normDistReduced2_T_68 = mux(_notCDom_normDistReduced2_T_14, UInt<6>(0h28), _notCDom_normDistReduced2_T_67) node _notCDom_normDistReduced2_T_69 = mux(_notCDom_normDistReduced2_T_15, UInt<6>(0h27), _notCDom_normDistReduced2_T_68) node _notCDom_normDistReduced2_T_70 = mux(_notCDom_normDistReduced2_T_16, UInt<6>(0h26), _notCDom_normDistReduced2_T_69) node _notCDom_normDistReduced2_T_71 = mux(_notCDom_normDistReduced2_T_17, UInt<6>(0h25), _notCDom_normDistReduced2_T_70) node _notCDom_normDistReduced2_T_72 = mux(_notCDom_normDistReduced2_T_18, UInt<6>(0h24), _notCDom_normDistReduced2_T_71) node _notCDom_normDistReduced2_T_73 = mux(_notCDom_normDistReduced2_T_19, UInt<6>(0h23), _notCDom_normDistReduced2_T_72) node _notCDom_normDistReduced2_T_74 = mux(_notCDom_normDistReduced2_T_20, UInt<6>(0h22), _notCDom_normDistReduced2_T_73) node _notCDom_normDistReduced2_T_75 = mux(_notCDom_normDistReduced2_T_21, UInt<6>(0h21), _notCDom_normDistReduced2_T_74) node _notCDom_normDistReduced2_T_76 = mux(_notCDom_normDistReduced2_T_22, UInt<6>(0h20), _notCDom_normDistReduced2_T_75) node _notCDom_normDistReduced2_T_77 = mux(_notCDom_normDistReduced2_T_23, UInt<5>(0h1f), _notCDom_normDistReduced2_T_76) node _notCDom_normDistReduced2_T_78 = mux(_notCDom_normDistReduced2_T_24, UInt<5>(0h1e), _notCDom_normDistReduced2_T_77) node _notCDom_normDistReduced2_T_79 = mux(_notCDom_normDistReduced2_T_25, UInt<5>(0h1d), _notCDom_normDistReduced2_T_78) node _notCDom_normDistReduced2_T_80 = mux(_notCDom_normDistReduced2_T_26, UInt<5>(0h1c), _notCDom_normDistReduced2_T_79) node _notCDom_normDistReduced2_T_81 = mux(_notCDom_normDistReduced2_T_27, UInt<5>(0h1b), _notCDom_normDistReduced2_T_80) node _notCDom_normDistReduced2_T_82 = mux(_notCDom_normDistReduced2_T_28, UInt<5>(0h1a), _notCDom_normDistReduced2_T_81) node _notCDom_normDistReduced2_T_83 = mux(_notCDom_normDistReduced2_T_29, UInt<5>(0h19), _notCDom_normDistReduced2_T_82) node _notCDom_normDistReduced2_T_84 = mux(_notCDom_normDistReduced2_T_30, UInt<5>(0h18), _notCDom_normDistReduced2_T_83) node _notCDom_normDistReduced2_T_85 = mux(_notCDom_normDistReduced2_T_31, UInt<5>(0h17), _notCDom_normDistReduced2_T_84) node _notCDom_normDistReduced2_T_86 = mux(_notCDom_normDistReduced2_T_32, UInt<5>(0h16), _notCDom_normDistReduced2_T_85) node _notCDom_normDistReduced2_T_87 = mux(_notCDom_normDistReduced2_T_33, UInt<5>(0h15), _notCDom_normDistReduced2_T_86) node _notCDom_normDistReduced2_T_88 = mux(_notCDom_normDistReduced2_T_34, UInt<5>(0h14), _notCDom_normDistReduced2_T_87) node _notCDom_normDistReduced2_T_89 = mux(_notCDom_normDistReduced2_T_35, UInt<5>(0h13), _notCDom_normDistReduced2_T_88) node _notCDom_normDistReduced2_T_90 = mux(_notCDom_normDistReduced2_T_36, UInt<5>(0h12), _notCDom_normDistReduced2_T_89) node _notCDom_normDistReduced2_T_91 = mux(_notCDom_normDistReduced2_T_37, UInt<5>(0h11), _notCDom_normDistReduced2_T_90) node _notCDom_normDistReduced2_T_92 = mux(_notCDom_normDistReduced2_T_38, UInt<5>(0h10), _notCDom_normDistReduced2_T_91) node _notCDom_normDistReduced2_T_93 = mux(_notCDom_normDistReduced2_T_39, UInt<4>(0hf), _notCDom_normDistReduced2_T_92) node _notCDom_normDistReduced2_T_94 = mux(_notCDom_normDistReduced2_T_40, UInt<4>(0he), _notCDom_normDistReduced2_T_93) node _notCDom_normDistReduced2_T_95 = mux(_notCDom_normDistReduced2_T_41, UInt<4>(0hd), _notCDom_normDistReduced2_T_94) node _notCDom_normDistReduced2_T_96 = mux(_notCDom_normDistReduced2_T_42, UInt<4>(0hc), _notCDom_normDistReduced2_T_95) node _notCDom_normDistReduced2_T_97 = mux(_notCDom_normDistReduced2_T_43, UInt<4>(0hb), _notCDom_normDistReduced2_T_96) node _notCDom_normDistReduced2_T_98 = mux(_notCDom_normDistReduced2_T_44, UInt<4>(0ha), _notCDom_normDistReduced2_T_97) node _notCDom_normDistReduced2_T_99 = mux(_notCDom_normDistReduced2_T_45, UInt<4>(0h9), _notCDom_normDistReduced2_T_98) node _notCDom_normDistReduced2_T_100 = mux(_notCDom_normDistReduced2_T_46, UInt<4>(0h8), _notCDom_normDistReduced2_T_99) node _notCDom_normDistReduced2_T_101 = mux(_notCDom_normDistReduced2_T_47, UInt<3>(0h7), _notCDom_normDistReduced2_T_100) node _notCDom_normDistReduced2_T_102 = mux(_notCDom_normDistReduced2_T_48, UInt<3>(0h6), _notCDom_normDistReduced2_T_101) node _notCDom_normDistReduced2_T_103 = mux(_notCDom_normDistReduced2_T_49, UInt<3>(0h5), _notCDom_normDistReduced2_T_102) node _notCDom_normDistReduced2_T_104 = mux(_notCDom_normDistReduced2_T_50, UInt<3>(0h4), _notCDom_normDistReduced2_T_103) node _notCDom_normDistReduced2_T_105 = mux(_notCDom_normDistReduced2_T_51, UInt<2>(0h3), _notCDom_normDistReduced2_T_104) node _notCDom_normDistReduced2_T_106 = mux(_notCDom_normDistReduced2_T_52, UInt<2>(0h2), _notCDom_normDistReduced2_T_105) node _notCDom_normDistReduced2_T_107 = mux(_notCDom_normDistReduced2_T_53, UInt<1>(0h1), _notCDom_normDistReduced2_T_106) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_54, UInt<1>(0h0), _notCDom_normDistReduced2_T_107) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 109, 52) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 26, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[14] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 13, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node _notCDom_reduced4SigExtra_reducedVec_7_T = bits(_notCDom_reduced4SigExtra_T_1, 15, 14) node _notCDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_7_T) connect notCDom_reduced4SigExtra_reducedVec[7], _notCDom_reduced4SigExtra_reducedVec_7_T_1 node _notCDom_reduced4SigExtra_reducedVec_8_T = bits(_notCDom_reduced4SigExtra_T_1, 17, 16) node _notCDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_8_T) connect notCDom_reduced4SigExtra_reducedVec[8], _notCDom_reduced4SigExtra_reducedVec_8_T_1 node _notCDom_reduced4SigExtra_reducedVec_9_T = bits(_notCDom_reduced4SigExtra_T_1, 19, 18) node _notCDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_9_T) connect notCDom_reduced4SigExtra_reducedVec[9], _notCDom_reduced4SigExtra_reducedVec_9_T_1 node _notCDom_reduced4SigExtra_reducedVec_10_T = bits(_notCDom_reduced4SigExtra_T_1, 21, 20) node _notCDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_10_T) connect notCDom_reduced4SigExtra_reducedVec[10], _notCDom_reduced4SigExtra_reducedVec_10_T_1 node _notCDom_reduced4SigExtra_reducedVec_11_T = bits(_notCDom_reduced4SigExtra_T_1, 23, 22) node _notCDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_11_T) connect notCDom_reduced4SigExtra_reducedVec[11], _notCDom_reduced4SigExtra_reducedVec_11_T_1 node _notCDom_reduced4SigExtra_reducedVec_12_T = bits(_notCDom_reduced4SigExtra_T_1, 25, 24) node _notCDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_12_T) connect notCDom_reduced4SigExtra_reducedVec[12], _notCDom_reduced4SigExtra_reducedVec_12_T_1 node _notCDom_reduced4SigExtra_reducedVec_13_T = bits(_notCDom_reduced4SigExtra_T_1, 26, 26) node _notCDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_13_T) connect notCDom_reduced4SigExtra_reducedVec[13], _notCDom_reduced4SigExtra_reducedVec_13_T_1 node notCDom_reduced4SigExtra_lo_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo_lo = cat(notCDom_reduced4SigExtra_lo_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_lo_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_lo_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_lo_hi_hi, notCDom_reduced4SigExtra_lo_hi_lo) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_lo_lo) node notCDom_reduced4SigExtra_hi_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[9], notCDom_reduced4SigExtra_reducedVec[8]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_hi_lo_hi, notCDom_reduced4SigExtra_reducedVec[7]) node notCDom_reduced4SigExtra_hi_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[11], notCDom_reduced4SigExtra_reducedVec[10]) node notCDom_reduced4SigExtra_hi_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[13], notCDom_reduced4SigExtra_reducedVec[12]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_hi_hi_hi, notCDom_reduced4SigExtra_hi_hi_lo) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 13, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 7, 0) node _notCDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) node _notCDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _notCDom_reduced4SigExtra_T_7) node _notCDom_reduced4SigExtra_T_9 = shr(_notCDom_reduced4SigExtra_T_6, 4) node _notCDom_reduced4SigExtra_T_10 = and(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_8) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 0) node _notCDom_reduced4SigExtra_T_12 = shl(_notCDom_reduced4SigExtra_T_11, 4) node _notCDom_reduced4SigExtra_T_13 = not(_notCDom_reduced4SigExtra_T_8) node _notCDom_reduced4SigExtra_T_14 = and(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = or(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_8, 5, 0) node _notCDom_reduced4SigExtra_T_17 = shl(_notCDom_reduced4SigExtra_T_16, 2) node _notCDom_reduced4SigExtra_T_18 = xor(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_17) node _notCDom_reduced4SigExtra_T_19 = shr(_notCDom_reduced4SigExtra_T_15, 2) node _notCDom_reduced4SigExtra_T_20 = and(_notCDom_reduced4SigExtra_T_19, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_21 = bits(_notCDom_reduced4SigExtra_T_15, 5, 0) node _notCDom_reduced4SigExtra_T_22 = shl(_notCDom_reduced4SigExtra_T_21, 2) node _notCDom_reduced4SigExtra_T_23 = not(_notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_24 = and(_notCDom_reduced4SigExtra_T_22, _notCDom_reduced4SigExtra_T_23) node _notCDom_reduced4SigExtra_T_25 = or(_notCDom_reduced4SigExtra_T_20, _notCDom_reduced4SigExtra_T_24) node _notCDom_reduced4SigExtra_T_26 = bits(_notCDom_reduced4SigExtra_T_18, 6, 0) node _notCDom_reduced4SigExtra_T_27 = shl(_notCDom_reduced4SigExtra_T_26, 1) node _notCDom_reduced4SigExtra_T_28 = xor(_notCDom_reduced4SigExtra_T_18, _notCDom_reduced4SigExtra_T_27) node _notCDom_reduced4SigExtra_T_29 = shr(_notCDom_reduced4SigExtra_T_25, 1) node _notCDom_reduced4SigExtra_T_30 = and(_notCDom_reduced4SigExtra_T_29, _notCDom_reduced4SigExtra_T_28) node _notCDom_reduced4SigExtra_T_31 = bits(_notCDom_reduced4SigExtra_T_25, 6, 0) node _notCDom_reduced4SigExtra_T_32 = shl(_notCDom_reduced4SigExtra_T_31, 1) node _notCDom_reduced4SigExtra_T_33 = not(_notCDom_reduced4SigExtra_T_28) node _notCDom_reduced4SigExtra_T_34 = and(_notCDom_reduced4SigExtra_T_32, _notCDom_reduced4SigExtra_T_33) node _notCDom_reduced4SigExtra_T_35 = or(_notCDom_reduced4SigExtra_T_30, _notCDom_reduced4SigExtra_T_34) node _notCDom_reduced4SigExtra_T_36 = bits(_notCDom_reduced4SigExtra_T_5, 12, 8) node _notCDom_reduced4SigExtra_T_37 = bits(_notCDom_reduced4SigExtra_T_36, 3, 0) node _notCDom_reduced4SigExtra_T_38 = bits(_notCDom_reduced4SigExtra_T_37, 1, 0) node _notCDom_reduced4SigExtra_T_39 = bits(_notCDom_reduced4SigExtra_T_38, 0, 0) node _notCDom_reduced4SigExtra_T_40 = bits(_notCDom_reduced4SigExtra_T_38, 1, 1) node _notCDom_reduced4SigExtra_T_41 = cat(_notCDom_reduced4SigExtra_T_39, _notCDom_reduced4SigExtra_T_40) node _notCDom_reduced4SigExtra_T_42 = bits(_notCDom_reduced4SigExtra_T_37, 3, 2) node _notCDom_reduced4SigExtra_T_43 = bits(_notCDom_reduced4SigExtra_T_42, 0, 0) node _notCDom_reduced4SigExtra_T_44 = bits(_notCDom_reduced4SigExtra_T_42, 1, 1) node _notCDom_reduced4SigExtra_T_45 = cat(_notCDom_reduced4SigExtra_T_43, _notCDom_reduced4SigExtra_T_44) node _notCDom_reduced4SigExtra_T_46 = cat(_notCDom_reduced4SigExtra_T_41, _notCDom_reduced4SigExtra_T_45) node _notCDom_reduced4SigExtra_T_47 = bits(_notCDom_reduced4SigExtra_T_36, 4, 4) node _notCDom_reduced4SigExtra_T_48 = cat(_notCDom_reduced4SigExtra_T_46, _notCDom_reduced4SigExtra_T_47) node _notCDom_reduced4SigExtra_T_49 = cat(_notCDom_reduced4SigExtra_T_35, _notCDom_reduced4SigExtra_T_48) node _notCDom_reduced4SigExtra_T_50 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_49) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_50) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 55, 54) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T

module MulAddRecFNToRaw_postMul_e11_s53_4( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [5:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [54:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [106:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [12:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [55:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [12:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [5:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [54:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [106:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire [7:0] _CDom_reduced4SigExtra_T_8 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_8 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_7 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_13 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_7 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_13 = 8'hF0; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_16 = 6'hF; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_16 = 6'hF; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_17 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_17 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_18 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_18 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_23 = 8'hCC; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_23 = 8'hCC; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_26 = 7'h33; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_26 = 7'h33; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_27 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_27 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_28 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_28 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_33 = 8'hAA; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_33 = 8'hAA; // @[primitives.scala:77:20] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [12:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [55:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [12:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [55:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[106]; // @[MulAddRecFN.scala:169:7, :192:32] wire [55:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 56'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [54:0] _sigSum_T_2 = _sigSum_T_1[54:0]; // @[MulAddRecFN.scala:193:47] wire [54:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [105:0] _sigSum_T_4 = io_mulAddResult_0[105:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [160:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [161:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [13:0] _GEN = {io_fromPreMul_sExpSum_0[12], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [13:0] _CDom_sExp_T_1 = _GEN - {{12{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [12:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[12:0]; // @[MulAddRecFN.scala:203:43] wire [12:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [107:0] _CDom_absSigSum_T = sigSum[161:54]; // @[MulAddRecFN.scala:192:12, :206:20] wire [107:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[54:53]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [104:0] _CDom_absSigSum_T_4 = sigSum[159:55]; // @[MulAddRecFN.scala:192:12, :210:23] wire [107:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [107:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [52:0] _CDom_absSigSumExtra_T = sigSum[53:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [52:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [53:0] _CDom_absSigSumExtra_T_3 = sigSum[54:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [57:0] CDom_mainSig = _CDom_mainSig_T[107:50]; // @[MulAddRecFN.scala:219:{24,56}] wire [52:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[52:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [54:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 2'h0}; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_7; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_8; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_9; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_10; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_11; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_12; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_13; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[27:24]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_7_T = _CDom_reduced4SigExtra_T_1[31:28]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_7_T_1 = |_CDom_reduced4SigExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_7 = _CDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_8_T = _CDom_reduced4SigExtra_T_1[35:32]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_8_T_1 = |_CDom_reduced4SigExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_8 = _CDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_9_T = _CDom_reduced4SigExtra_T_1[39:36]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_9_T_1 = |_CDom_reduced4SigExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_9 = _CDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_10_T = _CDom_reduced4SigExtra_T_1[43:40]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_10_T_1 = |_CDom_reduced4SigExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_10 = _CDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_11_T = _CDom_reduced4SigExtra_T_1[47:44]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_11_T_1 = |_CDom_reduced4SigExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_11 = _CDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_12_T = _CDom_reduced4SigExtra_T_1[51:48]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_12_T_1 = |_CDom_reduced4SigExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_12 = _CDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_13_T = _CDom_reduced4SigExtra_T_1[54:52]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_13_T_1 = |_CDom_reduced4SigExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_13 = _CDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo_lo = {CDom_reduced4SigExtra_lo_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_lo_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_lo_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_lo_hi_hi, CDom_reduced4SigExtra_lo_hi_lo}; // @[primitives.scala:124:20] wire [6:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_lo_lo}; // @[primitives.scala:124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo_hi = {CDom_reduced4SigExtra_reducedVec_9, CDom_reduced4SigExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_hi_lo_hi, CDom_reduced4SigExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi_lo = {CDom_reduced4SigExtra_reducedVec_11, CDom_reduced4SigExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi_hi = {CDom_reduced4SigExtra_reducedVec_13, CDom_reduced4SigExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_hi_hi_hi, CDom_reduced4SigExtra_hi_hi_lo}; // @[primitives.scala:124:20] wire [6:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [13:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [3:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[5:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [3:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] CDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [12:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[13:1]; // @[primitives.scala:76:56, :78:22] wire [7:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_6[7:4]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_10 = {4'h0, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20, :120:54] wire [3:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:0]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_12 = {_CDom_reduced4SigExtra_T_11, 4'h0}; // @[primitives.scala:77:20, :120:54] wire [7:0] _CDom_reduced4SigExtra_T_14 = _CDom_reduced4SigExtra_T_12 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_15 = _CDom_reduced4SigExtra_T_10 | _CDom_reduced4SigExtra_T_14; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_19 = _CDom_reduced4SigExtra_T_15[7:2]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_20 = {2'h0, _CDom_reduced4SigExtra_T_19 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_21 = _CDom_reduced4SigExtra_T_15[5:0]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_22 = {_CDom_reduced4SigExtra_T_21, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_24 = _CDom_reduced4SigExtra_T_22 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_25 = _CDom_reduced4SigExtra_T_20 | _CDom_reduced4SigExtra_T_24; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_29 = _CDom_reduced4SigExtra_T_25[7:1]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_30 = {1'h0, _CDom_reduced4SigExtra_T_29 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_31 = _CDom_reduced4SigExtra_T_25[6:0]; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_32 = {_CDom_reduced4SigExtra_T_31, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_34 = _CDom_reduced4SigExtra_T_32 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _CDom_reduced4SigExtra_T_35 = _CDom_reduced4SigExtra_T_30 | _CDom_reduced4SigExtra_T_34; // @[primitives.scala:77:20] wire [4:0] _CDom_reduced4SigExtra_T_36 = _CDom_reduced4SigExtra_T_5[12:8]; // @[primitives.scala:77:20, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_37 = _CDom_reduced4SigExtra_T_36[3:0]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_38 = _CDom_reduced4SigExtra_T_37[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_39 = _CDom_reduced4SigExtra_T_38[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_40 = _CDom_reduced4SigExtra_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_41 = {_CDom_reduced4SigExtra_T_39, _CDom_reduced4SigExtra_T_40}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_42 = _CDom_reduced4SigExtra_T_37[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_43 = _CDom_reduced4SigExtra_T_42[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_44 = _CDom_reduced4SigExtra_T_42[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_45 = {_CDom_reduced4SigExtra_T_43, _CDom_reduced4SigExtra_T_44}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_46 = {_CDom_reduced4SigExtra_T_41, _CDom_reduced4SigExtra_T_45}; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_47 = _CDom_reduced4SigExtra_T_36[4]; // @[primitives.scala:77:20] wire [4:0] _CDom_reduced4SigExtra_T_48 = {_CDom_reduced4SigExtra_T_46, _CDom_reduced4SigExtra_T_47}; // @[primitives.scala:77:20] wire [12:0] _CDom_reduced4SigExtra_T_49 = {_CDom_reduced4SigExtra_T_35, _CDom_reduced4SigExtra_T_48}; // @[primitives.scala:77:20] wire [13:0] _CDom_reduced4SigExtra_T_50 = {1'h0, _CDom_reduced4SigExtra_T_2[12:0] & _CDom_reduced4SigExtra_T_49}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_50; // @[MulAddRecFN.scala:222:72, :223:73] wire [54:0] _CDom_sig_T = CDom_mainSig[57:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [55:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[109]; // @[MulAddRecFN.scala:192:12, :232:36] wire [108:0] _notCDom_absSigSum_T = sigSum[108:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [108:0] _notCDom_absSigSum_T_2 = sigSum[108:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [108:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [109:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {109'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [108:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[108:0]; // @[MulAddRecFN.scala:236:41] wire [108:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_26_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_27_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_28_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_29_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_30_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_31_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_32_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_33_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_34_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_35_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_36_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_37_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_38_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_39_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_40_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_41_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_42_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_43_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_44_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_45_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_46_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_47_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_48_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_49_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_50_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_51_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_52_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_53_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_54_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_26; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_27; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_28; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_29; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_30; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_31; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_32; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_33; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_34; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_35; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_36; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_37; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_38; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_39; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_40; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_41; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_42; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_43; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_44; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_45; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_46; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_47; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_48; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_49; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_50; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_51; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_52; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_53; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_54; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[51:50]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_26_T = notCDom_absSigSum[53:52]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_26_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_26 = _notCDom_reduced2AbsSigSum_reducedVec_26_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_27_T = notCDom_absSigSum[55:54]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_27_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_27 = _notCDom_reduced2AbsSigSum_reducedVec_27_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_28_T = notCDom_absSigSum[57:56]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_28_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_28 = _notCDom_reduced2AbsSigSum_reducedVec_28_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_29_T = notCDom_absSigSum[59:58]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_29_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_29 = _notCDom_reduced2AbsSigSum_reducedVec_29_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_30_T = notCDom_absSigSum[61:60]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_30_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_30 = _notCDom_reduced2AbsSigSum_reducedVec_30_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_31_T = notCDom_absSigSum[63:62]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_31_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_31 = _notCDom_reduced2AbsSigSum_reducedVec_31_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_32_T = notCDom_absSigSum[65:64]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_32_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_32 = _notCDom_reduced2AbsSigSum_reducedVec_32_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_33_T = notCDom_absSigSum[67:66]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_33_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_33 = _notCDom_reduced2AbsSigSum_reducedVec_33_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_34_T = notCDom_absSigSum[69:68]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_34_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_34 = _notCDom_reduced2AbsSigSum_reducedVec_34_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_35_T = notCDom_absSigSum[71:70]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_35_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_35 = _notCDom_reduced2AbsSigSum_reducedVec_35_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_36_T = notCDom_absSigSum[73:72]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_36_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_36 = _notCDom_reduced2AbsSigSum_reducedVec_36_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_37_T = notCDom_absSigSum[75:74]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_37_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_37 = _notCDom_reduced2AbsSigSum_reducedVec_37_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_38_T = notCDom_absSigSum[77:76]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_38_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_38 = _notCDom_reduced2AbsSigSum_reducedVec_38_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_39_T = notCDom_absSigSum[79:78]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_39_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_39 = _notCDom_reduced2AbsSigSum_reducedVec_39_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_40_T = notCDom_absSigSum[81:80]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_40_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_40 = _notCDom_reduced2AbsSigSum_reducedVec_40_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_41_T = notCDom_absSigSum[83:82]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_41_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_41 = _notCDom_reduced2AbsSigSum_reducedVec_41_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_42_T = notCDom_absSigSum[85:84]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_42_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_42 = _notCDom_reduced2AbsSigSum_reducedVec_42_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_43_T = notCDom_absSigSum[87:86]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_43_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_43 = _notCDom_reduced2AbsSigSum_reducedVec_43_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_44_T = notCDom_absSigSum[89:88]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_44_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_44 = _notCDom_reduced2AbsSigSum_reducedVec_44_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_45_T = notCDom_absSigSum[91:90]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_45_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_45 = _notCDom_reduced2AbsSigSum_reducedVec_45_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_46_T = notCDom_absSigSum[93:92]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_46_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_46 = _notCDom_reduced2AbsSigSum_reducedVec_46_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_47_T = notCDom_absSigSum[95:94]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_47_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_47 = _notCDom_reduced2AbsSigSum_reducedVec_47_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_48_T = notCDom_absSigSum[97:96]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_48_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_48 = _notCDom_reduced2AbsSigSum_reducedVec_48_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_49_T = notCDom_absSigSum[99:98]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_49_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_49 = _notCDom_reduced2AbsSigSum_reducedVec_49_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_50_T = notCDom_absSigSum[101:100]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_50_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_50 = _notCDom_reduced2AbsSigSum_reducedVec_50_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_51_T = notCDom_absSigSum[103:102]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_51_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_51 = _notCDom_reduced2AbsSigSum_reducedVec_51_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_52_T = notCDom_absSigSum[105:104]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_52_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_52 = _notCDom_reduced2AbsSigSum_reducedVec_52_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_53_T = notCDom_absSigSum[107:106]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_53_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_53 = _notCDom_reduced2AbsSigSum_reducedVec_53_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_54_T = notCDom_absSigSum[108]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_54_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_54 = _notCDom_reduced2AbsSigSum_reducedVec_54_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_17, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_19, notCDom_reduced2AbsSigSum_reducedVec_18}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_22, notCDom_reduced2AbsSigSum_reducedVec_21}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_24, notCDom_reduced2AbsSigSum_reducedVec_23}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_26, notCDom_reduced2AbsSigSum_reducedVec_25}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [13:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [26:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_29, notCDom_reduced2AbsSigSum_reducedVec_28}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_27}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_31, notCDom_reduced2AbsSigSum_reducedVec_30}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_33, notCDom_reduced2AbsSigSum_reducedVec_32}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_36, notCDom_reduced2AbsSigSum_reducedVec_35}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_34}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_38, notCDom_reduced2AbsSigSum_reducedVec_37}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_40, notCDom_reduced2AbsSigSum_reducedVec_39}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_lo}; // @[primitives.scala:107:20] wire [13:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_43, notCDom_reduced2AbsSigSum_reducedVec_42}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_41}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_45, notCDom_reduced2AbsSigSum_reducedVec_44}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_47, notCDom_reduced2AbsSigSum_reducedVec_46}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_50, notCDom_reduced2AbsSigSum_reducedVec_49}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_48}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_52, notCDom_reduced2AbsSigSum_reducedVec_51}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_54, notCDom_reduced2AbsSigSum_reducedVec_53}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [13:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [27:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [54:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_26 = notCDom_reduced2AbsSigSum[26]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_27 = notCDom_reduced2AbsSigSum[27]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_28 = notCDom_reduced2AbsSigSum[28]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_29 = notCDom_reduced2AbsSigSum[29]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_30 = notCDom_reduced2AbsSigSum[30]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_31 = notCDom_reduced2AbsSigSum[31]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_32 = notCDom_reduced2AbsSigSum[32]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_33 = notCDom_reduced2AbsSigSum[33]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_34 = notCDom_reduced2AbsSigSum[34]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_35 = notCDom_reduced2AbsSigSum[35]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_36 = notCDom_reduced2AbsSigSum[36]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_37 = notCDom_reduced2AbsSigSum[37]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_38 = notCDom_reduced2AbsSigSum[38]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_39 = notCDom_reduced2AbsSigSum[39]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_40 = notCDom_reduced2AbsSigSum[40]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_41 = notCDom_reduced2AbsSigSum[41]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_42 = notCDom_reduced2AbsSigSum[42]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_43 = notCDom_reduced2AbsSigSum[43]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_44 = notCDom_reduced2AbsSigSum[44]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_45 = notCDom_reduced2AbsSigSum[45]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_46 = notCDom_reduced2AbsSigSum[46]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_47 = notCDom_reduced2AbsSigSum[47]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_48 = notCDom_reduced2AbsSigSum[48]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_49 = notCDom_reduced2AbsSigSum[49]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_50 = notCDom_reduced2AbsSigSum[50]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_51 = notCDom_reduced2AbsSigSum[51]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_52 = notCDom_reduced2AbsSigSum[52]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_53 = notCDom_reduced2AbsSigSum[53]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_54 = notCDom_reduced2AbsSigSum[54]; // @[primitives.scala:91:52, :107:20] wire [5:0] _notCDom_normDistReduced2_T_55 = _notCDom_normDistReduced2_T_1 ? 6'h35 : 6'h36; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_56 = _notCDom_normDistReduced2_T_2 ? 6'h34 : _notCDom_normDistReduced2_T_55; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_57 = _notCDom_normDistReduced2_T_3 ? 6'h33 : _notCDom_normDistReduced2_T_56; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_58 = _notCDom_normDistReduced2_T_4 ? 6'h32 : _notCDom_normDistReduced2_T_57; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_59 = _notCDom_normDistReduced2_T_5 ? 6'h31 : _notCDom_normDistReduced2_T_58; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_60 = _notCDom_normDistReduced2_T_6 ? 6'h30 : _notCDom_normDistReduced2_T_59; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_61 = _notCDom_normDistReduced2_T_7 ? 6'h2F : _notCDom_normDistReduced2_T_60; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_62 = _notCDom_normDistReduced2_T_8 ? 6'h2E : _notCDom_normDistReduced2_T_61; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_63 = _notCDom_normDistReduced2_T_9 ? 6'h2D : _notCDom_normDistReduced2_T_62; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_64 = _notCDom_normDistReduced2_T_10 ? 6'h2C : _notCDom_normDistReduced2_T_63; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_65 = _notCDom_normDistReduced2_T_11 ? 6'h2B : _notCDom_normDistReduced2_T_64; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_66 = _notCDom_normDistReduced2_T_12 ? 6'h2A : _notCDom_normDistReduced2_T_65; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_67 = _notCDom_normDistReduced2_T_13 ? 6'h29 : _notCDom_normDistReduced2_T_66; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_68 = _notCDom_normDistReduced2_T_14 ? 6'h28 : _notCDom_normDistReduced2_T_67; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_69 = _notCDom_normDistReduced2_T_15 ? 6'h27 : _notCDom_normDistReduced2_T_68; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_70 = _notCDom_normDistReduced2_T_16 ? 6'h26 : _notCDom_normDistReduced2_T_69; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_71 = _notCDom_normDistReduced2_T_17 ? 6'h25 : _notCDom_normDistReduced2_T_70; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_72 = _notCDom_normDistReduced2_T_18 ? 6'h24 : _notCDom_normDistReduced2_T_71; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_73 = _notCDom_normDistReduced2_T_19 ? 6'h23 : _notCDom_normDistReduced2_T_72; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_74 = _notCDom_normDistReduced2_T_20 ? 6'h22 : _notCDom_normDistReduced2_T_73; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_75 = _notCDom_normDistReduced2_T_21 ? 6'h21 : _notCDom_normDistReduced2_T_74; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_76 = _notCDom_normDistReduced2_T_22 ? 6'h20 : _notCDom_normDistReduced2_T_75; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_77 = _notCDom_normDistReduced2_T_23 ? 6'h1F : _notCDom_normDistReduced2_T_76; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_78 = _notCDom_normDistReduced2_T_24 ? 6'h1E : _notCDom_normDistReduced2_T_77; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_79 = _notCDom_normDistReduced2_T_25 ? 6'h1D : _notCDom_normDistReduced2_T_78; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_80 = _notCDom_normDistReduced2_T_26 ? 6'h1C : _notCDom_normDistReduced2_T_79; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_81 = _notCDom_normDistReduced2_T_27 ? 6'h1B : _notCDom_normDistReduced2_T_80; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_82 = _notCDom_normDistReduced2_T_28 ? 6'h1A : _notCDom_normDistReduced2_T_81; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_83 = _notCDom_normDistReduced2_T_29 ? 6'h19 : _notCDom_normDistReduced2_T_82; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_84 = _notCDom_normDistReduced2_T_30 ? 6'h18 : _notCDom_normDistReduced2_T_83; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_85 = _notCDom_normDistReduced2_T_31 ? 6'h17 : _notCDom_normDistReduced2_T_84; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_86 = _notCDom_normDistReduced2_T_32 ? 6'h16 : _notCDom_normDistReduced2_T_85; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_87 = _notCDom_normDistReduced2_T_33 ? 6'h15 : _notCDom_normDistReduced2_T_86; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_88 = _notCDom_normDistReduced2_T_34 ? 6'h14 : _notCDom_normDistReduced2_T_87; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_89 = _notCDom_normDistReduced2_T_35 ? 6'h13 : _notCDom_normDistReduced2_T_88; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_90 = _notCDom_normDistReduced2_T_36 ? 6'h12 : _notCDom_normDistReduced2_T_89; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_91 = _notCDom_normDistReduced2_T_37 ? 6'h11 : _notCDom_normDistReduced2_T_90; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_92 = _notCDom_normDistReduced2_T_38 ? 6'h10 : _notCDom_normDistReduced2_T_91; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_93 = _notCDom_normDistReduced2_T_39 ? 6'hF : _notCDom_normDistReduced2_T_92; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_94 = _notCDom_normDistReduced2_T_40 ? 6'hE : _notCDom_normDistReduced2_T_93; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_95 = _notCDom_normDistReduced2_T_41 ? 6'hD : _notCDom_normDistReduced2_T_94; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_96 = _notCDom_normDistReduced2_T_42 ? 6'hC : _notCDom_normDistReduced2_T_95; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_97 = _notCDom_normDistReduced2_T_43 ? 6'hB : _notCDom_normDistReduced2_T_96; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_98 = _notCDom_normDistReduced2_T_44 ? 6'hA : _notCDom_normDistReduced2_T_97; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_99 = _notCDom_normDistReduced2_T_45 ? 6'h9 : _notCDom_normDistReduced2_T_98; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_100 = _notCDom_normDistReduced2_T_46 ? 6'h8 : _notCDom_normDistReduced2_T_99; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_101 = _notCDom_normDistReduced2_T_47 ? 6'h7 : _notCDom_normDistReduced2_T_100; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_102 = _notCDom_normDistReduced2_T_48 ? 6'h6 : _notCDom_normDistReduced2_T_101; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_103 = _notCDom_normDistReduced2_T_49 ? 6'h5 : _notCDom_normDistReduced2_T_102; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_104 = _notCDom_normDistReduced2_T_50 ? 6'h4 : _notCDom_normDistReduced2_T_103; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_105 = _notCDom_normDistReduced2_T_51 ? 6'h3 : _notCDom_normDistReduced2_T_104; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_106 = _notCDom_normDistReduced2_T_52 ? 6'h2 : _notCDom_normDistReduced2_T_105; // @[Mux.scala:50:70] wire [5:0] _notCDom_normDistReduced2_T_107 = _notCDom_normDistReduced2_T_53 ? 6'h1 : _notCDom_normDistReduced2_T_106; // @[Mux.scala:50:70] wire [5:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_54 ? 6'h0 : _notCDom_normDistReduced2_T_107; // @[Mux.scala:50:70] wire [6:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [7:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [13:0] _notCDom_sExp_T_1 = _GEN - {{6{_notCDom_sExp_T[7]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [12:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[12:0]; // @[MulAddRecFN.scala:241:46] wire [12:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [235:0] _notCDom_mainSig_T = {127'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [57:0] notCDom_mainSig = _notCDom_mainSig_T[109:52]; // @[MulAddRecFN.scala:243:{27,50}] wire [26:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[26:0]; // @[primitives.scala:107:20] wire [26:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_13; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = |_notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_7_T = _notCDom_reduced4SigExtra_T_1[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_7_T_1 = |_notCDom_reduced4SigExtra_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_7 = _notCDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_8_T = _notCDom_reduced4SigExtra_T_1[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_8_T_1 = |_notCDom_reduced4SigExtra_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_8 = _notCDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_9_T = _notCDom_reduced4SigExtra_T_1[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_9_T_1 = |_notCDom_reduced4SigExtra_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_9 = _notCDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_10_T = _notCDom_reduced4SigExtra_T_1[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_10_T_1 = |_notCDom_reduced4SigExtra_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_10 = _notCDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_11_T = _notCDom_reduced4SigExtra_T_1[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_11_T_1 = |_notCDom_reduced4SigExtra_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_11 = _notCDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_12_T = _notCDom_reduced4SigExtra_T_1[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_12_T_1 = |_notCDom_reduced4SigExtra_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_12 = _notCDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_13_T = _notCDom_reduced4SigExtra_T_1[26]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_13_T_1 = _notCDom_reduced4SigExtra_reducedVec_13_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_13 = _notCDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo_lo = {notCDom_reduced4SigExtra_lo_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_lo_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_lo_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_lo_hi_hi, notCDom_reduced4SigExtra_lo_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo_hi = {notCDom_reduced4SigExtra_reducedVec_9, notCDom_reduced4SigExtra_reducedVec_8}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_hi_lo_hi, notCDom_reduced4SigExtra_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi_lo = {notCDom_reduced4SigExtra_reducedVec_11, notCDom_reduced4SigExtra_reducedVec_10}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi_hi = {notCDom_reduced4SigExtra_reducedVec_13, notCDom_reduced4SigExtra_reducedVec_12}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_hi_hi_hi, notCDom_reduced4SigExtra_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [13:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [4:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[5:1]; // @[Mux.scala:50:70] wire [4:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [32:0] notCDom_reduced4SigExtra_shift = $signed(33'sh100000000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [12:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[13:1]; // @[primitives.scala:76:56, :78:22] wire [7:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_6[7:4]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_10 = {4'h0, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20, :120:54] wire [3:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:0]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_12 = {_notCDom_reduced4SigExtra_T_11, 4'h0}; // @[primitives.scala:77:20, :120:54] wire [7:0] _notCDom_reduced4SigExtra_T_14 = _notCDom_reduced4SigExtra_T_12 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_15 = _notCDom_reduced4SigExtra_T_10 | _notCDom_reduced4SigExtra_T_14; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_19 = _notCDom_reduced4SigExtra_T_15[7:2]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_20 = {2'h0, _notCDom_reduced4SigExtra_T_19 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_21 = _notCDom_reduced4SigExtra_T_15[5:0]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_22 = {_notCDom_reduced4SigExtra_T_21, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_24 = _notCDom_reduced4SigExtra_T_22 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_25 = _notCDom_reduced4SigExtra_T_20 | _notCDom_reduced4SigExtra_T_24; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_29 = _notCDom_reduced4SigExtra_T_25[7:1]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_30 = {1'h0, _notCDom_reduced4SigExtra_T_29 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_31 = _notCDom_reduced4SigExtra_T_25[6:0]; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_32 = {_notCDom_reduced4SigExtra_T_31, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_34 = _notCDom_reduced4SigExtra_T_32 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _notCDom_reduced4SigExtra_T_35 = _notCDom_reduced4SigExtra_T_30 | _notCDom_reduced4SigExtra_T_34; // @[primitives.scala:77:20] wire [4:0] _notCDom_reduced4SigExtra_T_36 = _notCDom_reduced4SigExtra_T_5[12:8]; // @[primitives.scala:77:20, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_37 = _notCDom_reduced4SigExtra_T_36[3:0]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_38 = _notCDom_reduced4SigExtra_T_37[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_39 = _notCDom_reduced4SigExtra_T_38[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_40 = _notCDom_reduced4SigExtra_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_41 = {_notCDom_reduced4SigExtra_T_39, _notCDom_reduced4SigExtra_T_40}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_42 = _notCDom_reduced4SigExtra_T_37[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_43 = _notCDom_reduced4SigExtra_T_42[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_44 = _notCDom_reduced4SigExtra_T_42[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_45 = {_notCDom_reduced4SigExtra_T_43, _notCDom_reduced4SigExtra_T_44}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_46 = {_notCDom_reduced4SigExtra_T_41, _notCDom_reduced4SigExtra_T_45}; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_47 = _notCDom_reduced4SigExtra_T_36[4]; // @[primitives.scala:77:20] wire [4:0] _notCDom_reduced4SigExtra_T_48 = {_notCDom_reduced4SigExtra_T_46, _notCDom_reduced4SigExtra_T_47}; // @[primitives.scala:77:20] wire [12:0] _notCDom_reduced4SigExtra_T_49 = {_notCDom_reduced4SigExtra_T_35, _notCDom_reduced4SigExtra_T_48}; // @[primitives.scala:77:20] wire [13:0] _notCDom_reduced4SigExtra_T_50 = {1'h0, _notCDom_reduced4SigExtra_T_2[12:0] & _notCDom_reduced4SigExtra_T_49}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_50; // @[MulAddRecFN.scala:247:78, :249:11] wire [54:0] _notCDom_sig_T = notCDom_mainSig[57:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [55:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[55:54]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[MulAddRecFN.scala:222:53, :255:{21,50}] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PTW : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<36>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<48>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<49>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<49>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<49>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<48>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) wire l2_refill_wire : UInt<1> inst arb of Arbiter2_Valid_PTWReq connect arb.clock, clock connect arb.reset, reset connect arb.io.in[0], io.requestor[0].req connect arb.io.in[1], io.requestor[1].req node _arb_io_out_ready_T = eq(state, UInt<3>(0h0)) node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0)) node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1) connect arb.io.out.ready, _arb_io_out_ready_T_2 wire _resp_valid_WIRE : UInt<1>[2] connect _resp_valid_WIRE[0], UInt<1>(0h0) connect _resp_valid_WIRE[1], UInt<1>(0h0) reg resp_valid : UInt<1>[2], clock connect resp_valid, _resp_valid_WIRE node _clock_en_T = neq(state, UInt<3>(0h0)) node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire) node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid) node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid) node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0) node clock_en = or(_clock_en_T_3, _clock_en_T_4) node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en) connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T reg invalidated : UInt<1>, clock reg count : UInt<2>, clock reg resp_ae_ptw : UInt<1>, clock reg resp_ae_final : UInt<1>, clock reg resp_pf : UInt<1>, clock reg resp_gf : UInt<1>, clock reg resp_hr : UInt<1>, clock reg resp_hw : UInt<1>, clock reg resp_hx : UInt<1>, clock reg resp_fragmented_superpage : UInt<1>, clock reg r_req : { addr : UInt<36>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock reg r_req_dest : UInt, clock reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg aux_count : UInt<2>, clock reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg gpa_pgoff : UInt<12>, clock reg stage2 : UInt<1>, clock reg stage2_final : UInt<1>, clock node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) node _r_hgatp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1) node _r_hgatp_initial_count_T_2 = bits(r_hgatp.mode, 0, 0) node _r_hgatp_initial_count_T_3 = sub(_r_hgatp_initial_count_T_1, _r_hgatp_initial_count_T_2) node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_3, 1) node do_both_stages = and(r_req.vstage1, r_req.stage2) node _max_count_T = lt(count, aux_count) node max_count = mux(_max_count_T, aux_count, count) node _vpn_T = and(r_req.vstage1, stage2) node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr) reg mem_resp_valid : UInt<1>, clock connect mem_resp_valid, io.mem.resp.valid reg mem_resp_data : UInt, clock connect mem_resp_data, io.mem.resp.bits.data wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} wire _tmp_WIRE : UInt<64> connect _tmp_WIRE, mem_resp_data node _tmp_T = bits(_tmp_WIRE, 0, 0) connect tmp.v, _tmp_T node _tmp_T_1 = bits(_tmp_WIRE, 1, 1) connect tmp.r, _tmp_T_1 node _tmp_T_2 = bits(_tmp_WIRE, 2, 2) connect tmp.w, _tmp_T_2 node _tmp_T_3 = bits(_tmp_WIRE, 3, 3) connect tmp.x, _tmp_T_3 node _tmp_T_4 = bits(_tmp_WIRE, 4, 4) connect tmp.u, _tmp_T_4 node _tmp_T_5 = bits(_tmp_WIRE, 5, 5) connect tmp.g, _tmp_T_5 node _tmp_T_6 = bits(_tmp_WIRE, 6, 6) connect tmp.a, _tmp_T_6 node _tmp_T_7 = bits(_tmp_WIRE, 7, 7) connect tmp.d, _tmp_T_7 node _tmp_T_8 = bits(_tmp_WIRE, 9, 8) connect tmp.reserved_for_software, _tmp_T_8 node _tmp_T_9 = bits(_tmp_WIRE, 53, 10) connect tmp.ppn, _tmp_T_9 node _tmp_T_10 = bits(_tmp_WIRE, 63, 54) connect tmp.reserved_for_future, _tmp_T_10 wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect pte, tmp node _res_ppn_T = eq(stage2, UInt<1>(0h0)) node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T) node _res_ppn_T_2 = bits(tmp.ppn, 35, 0) node _res_ppn_T_3 = bits(tmp.ppn, 19, 0) node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3) connect pte.ppn, _res_ppn_T_4 node _T = or(tmp.r, tmp.w) node _T_1 = or(_T, tmp.x) when _T_1 : node _T_2 = leq(count, UInt<1>(0h0)) node _T_3 = bits(tmp.ppn, 26, 18) node _T_4 = neq(_T_3, UInt<1>(0h0)) node _T_5 = and(_T_2, _T_4) when _T_5 : connect pte.v, UInt<1>(0h0) node _T_6 = leq(count, UInt<1>(0h1)) node _T_7 = bits(tmp.ppn, 17, 9) node _T_8 = neq(_T_7, UInt<1>(0h0)) node _T_9 = and(_T_6, _T_8) when _T_9 : connect pte.v, UInt<1>(0h0) node _T_10 = leq(count, UInt<2>(0h2)) node _T_11 = bits(tmp.ppn, 8, 0) node _T_12 = neq(_T_11, UInt<1>(0h0)) node _T_13 = and(_T_10, _T_12) when _T_13 : connect pte.v, UInt<1>(0h0) node _T_14 = eq(stage2, UInt<1>(0h0)) node _T_15 = and(do_both_stages, _T_14) node _T_16 = shr(tmp.ppn, 36) node _T_17 = neq(_T_16, UInt<1>(0h0)) node _T_18 = shr(tmp.ppn, 20) node _T_19 = neq(_T_18, UInt<1>(0h0)) node invalid_paddr = mux(_T_15, _T_17, _T_19) node _T_20 = eq(stage2, UInt<1>(0h0)) node _T_21 = and(do_both_stages, _T_20) node _count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _count_T_1 = tail(_count_T, 1) node _count_T_2 = bits(r_hgatp.mode, 0, 0) node _count_T_3 = sub(_count_T_1, _count_T_2) node count_1 = tail(_count_T_3, 1) node idxs_0 = shr(tmp.ppn, 38) node idxs_1 = shr(tmp.ppn, 29) wire _WIRE : UInt<15>[2] connect _WIRE[0], idxs_0 connect _WIRE[1], idxs_1 node _T_22 = or(count_1, UInt<1>(0h0)) node _T_23 = bits(_T_22, 0, 0) node _T_24 = neq(_WIRE[_T_23], UInt<1>(0h0)) node invalid_gpa = and(_T_21, _T_24) node _traverse_T = eq(pte.r, UInt<1>(0h0)) node _traverse_T_1 = and(pte.v, _traverse_T) node _traverse_T_2 = eq(pte.w, UInt<1>(0h0)) node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2) node _traverse_T_4 = eq(pte.x, UInt<1>(0h0)) node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4) node _traverse_T_6 = eq(pte.d, UInt<1>(0h0)) node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6) node _traverse_T_8 = eq(pte.a, UInt<1>(0h0)) node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8) node _traverse_T_10 = eq(pte.u, UInt<1>(0h0)) node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10) node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12) node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0)) node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14) node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0)) node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16) node _traverse_T_18 = lt(count, UInt<2>(0h3)) node traverse = and(_traverse_T_17, _traverse_T_18) node _pte_addr_vpn_idxs_T = shr(vpn, 27) node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0) node _pte_addr_vpn_idxs_T_1 = shr(vpn, 18) node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0) node _pte_addr_vpn_idxs_T_2 = shr(vpn, 9) node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0) node _pte_addr_vpn_idxs_T_3 = shr(vpn, 0) node pte_addr_vpn_idxs_3 = bits(_pte_addr_vpn_idxs_T_3, 8, 0) node _pte_addr_mask_T = eq(count, r_hgatp_initial_count) node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T) node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff)) node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1)) node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0) node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2)) node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1) node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3)) node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_3, _pte_addr_vpn_idx_T_3) node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask) node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9) node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx) node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3) node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) regreset valid : UInt<8>, clock, reset, UInt<8>(0h0) reg tags : UInt<32>[8], clock reg data : UInt<20>[8], clock node _can_hit_T = lt(count, UInt<2>(0h3)) node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0)) node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1) node can_hit = and(_can_hit_T, _can_hit_T_2) node tag = cat(r_req.vstage1, pte_addr) node _hits_T = eq(tags[0], tag) node _hits_T_1 = eq(tags[1], tag) node _hits_T_2 = eq(tags[2], tag) node _hits_T_3 = eq(tags[3], tag) node _hits_T_4 = eq(tags[4], tag) node _hits_T_5 = eq(tags[5], tag) node _hits_T_6 = eq(tags[6], tag) node _hits_T_7 = eq(tags[7], tag) node hits_lo_lo = cat(_hits_T_1, _hits_T) node hits_lo_hi = cat(_hits_T_3, _hits_T_2) node hits_lo = cat(hits_lo_hi, hits_lo_lo) node hits_hi_lo = cat(_hits_T_5, _hits_T_4) node hits_hi_hi = cat(_hits_T_7, _hits_T_6) node hits_hi = cat(hits_hi_hi, hits_hi_lo) node _hits_T_8 = cat(hits_hi, hits_lo) node hits = and(_hits_T_8, valid) node _hit_T = orr(hits) node pte_cache_hit = and(_hit_T, can_hit) node _T_25 = and(mem_resp_valid, traverse) node _T_26 = and(_T_25, can_hit) node _T_27 = orr(hits) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = and(_T_26, _T_28) node _T_30 = eq(invalidated, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : node _r_T = andr(valid) node r_left_subtree_older = bits(state_reg, 6, 6) node r_left_subtree_state = bits(state_reg, 5, 3) node r_right_subtree_state = bits(state_reg, 2, 0) node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2) node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1) node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0) node _r_T_1 = bits(r_left_subtree_state_1, 0, 0) node _r_T_2 = bits(r_right_subtree_state_1, 0, 0) node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2) node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3) node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2) node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1) node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0) node _r_T_5 = bits(r_left_subtree_state_2, 0, 0) node _r_T_6 = bits(r_right_subtree_state_2, 0, 0) node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6) node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7) node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8) node _r_T_10 = cat(r_left_subtree_older, _r_T_9) node _r_T_11 = not(valid) node _r_T_12 = bits(_r_T_11, 0, 0) node _r_T_13 = bits(_r_T_11, 1, 1) node _r_T_14 = bits(_r_T_11, 2, 2) node _r_T_15 = bits(_r_T_11, 3, 3) node _r_T_16 = bits(_r_T_11, 4, 4) node _r_T_17 = bits(_r_T_11, 5, 5) node _r_T_18 = bits(_r_T_11, 6, 6) node _r_T_19 = bits(_r_T_11, 7, 7) node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20) node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21) node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22) node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23) node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24) node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25) node r = mux(_r_T, _r_T_10, _r_T_26) node _valid_T = dshl(UInt<1>(0h1), r) node _valid_T_1 = or(valid, _valid_T) connect valid, _valid_T_1 connect tags[r], tag connect data[r], pte.ppn node state_reg_touch_way_sized = bits(r, 2, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg, 5, 3) node state_reg_right_subtree_state = bits(state_reg, 2, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1) node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1) node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0)) node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3) node _state_reg_T_5 = bits(_state_reg_T, 0, 0) node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0) node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0)) node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1) node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4) node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8) node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9) node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1) node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1) node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0) node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0) node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0)) node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14) node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0) node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0)) node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2) node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15) node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19) node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state) node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10) node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21) connect state_reg, _state_reg_T_22 node _T_32 = eq(state, UInt<3>(0h1)) node _T_33 = and(pte_cache_hit, _T_32) when _T_33 : node hi = bits(hits, 7, 4) node lo = bits(hits, 3, 0) node _T_34 = orr(hi) node _T_35 = or(hi, lo) node hi_1 = bits(_T_35, 3, 2) node lo_1 = bits(_T_35, 1, 0) node _T_36 = orr(hi_1) node _T_37 = or(hi_1, lo_1) node _T_38 = bits(_T_37, 1, 1) node _T_39 = cat(_T_36, _T_38) node _T_40 = cat(_T_34, _T_39) node state_reg_touch_way_sized_1 = bits(_T_40, 2, 0) node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2) node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3) node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0) node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0) node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1) node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0)) node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1) node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0) node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0) node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0)) node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26) node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0) node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0)) node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4) node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27) node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31) node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32) node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0) node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1) node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0)) node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1) node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0) node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0) node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0) node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0)) node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37) node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0) node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0) node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0)) node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5) node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38) node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42) node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3) node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33) node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44) connect state_reg, _state_reg_T_45 node _T_41 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) node _T_42 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _T_43 = or(_T_41, _T_42) node _T_44 = and(io.dpath.sfence.valid, _T_43) when _T_44 : connect valid, UInt<1>(0h0) node _T_45 = eq(state, UInt<3>(0h1)) node _T_46 = and(pte_cache_hit, _T_45) node _T_47 = eq(count, UInt<1>(0h0)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(state, UInt<3>(0h1)) node _T_50 = and(pte_cache_hit, _T_49) node _T_51 = eq(count, UInt<1>(0h1)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(state, UInt<3>(0h1)) node _T_54 = and(pte_cache_hit, _T_53) node _T_55 = eq(count, UInt<2>(0h2)) node _T_56 = and(_T_54, _T_55) node _T_57 = bits(hits, 0, 0) node _T_58 = bits(hits, 1, 1) node _T_59 = bits(hits, 2, 2) node _T_60 = bits(hits, 3, 3) node _T_61 = bits(hits, 4, 4) node _T_62 = bits(hits, 5, 5) node _T_63 = bits(hits, 6, 6) node _T_64 = bits(hits, 7, 7) node _T_65 = mux(_T_57, data[0], UInt<1>(0h0)) node _T_66 = mux(_T_58, data[1], UInt<1>(0h0)) node _T_67 = mux(_T_59, data[2], UInt<1>(0h0)) node _T_68 = mux(_T_60, data[3], UInt<1>(0h0)) node _T_69 = mux(_T_61, data[4], UInt<1>(0h0)) node _T_70 = mux(_T_62, data[5], UInt<1>(0h0)) node _T_71 = mux(_T_63, data[6], UInt<1>(0h0)) node _T_72 = mux(_T_64, data[7], UInt<1>(0h0)) node _T_73 = or(_T_65, _T_66) node _T_74 = or(_T_73, _T_67) node _T_75 = or(_T_74, _T_68) node _T_76 = or(_T_75, _T_69) node _T_77 = or(_T_76, _T_70) node _T_78 = or(_T_77, _T_71) node _T_79 = or(_T_78, _T_72) wire pte_cache_data : UInt<20> connect pte_cache_data, _T_79 regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0) regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0) reg tags_1 : UInt<32>[8], clock reg data_1 : UInt<20>[8], clock node _can_hit_T_3 = eq(count, r_hgatp_initial_count) node _can_hit_T_4 = lt(aux_count, UInt<2>(0h3)) node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4) node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1) node _can_hit_T_7 = and(_can_hit_T_6, stage2) node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0)) node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8) node _can_refill_T = eq(stage2, UInt<1>(0h0)) node _can_refill_T_1 = and(do_both_stages, _can_refill_T) node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0)) node can_refill = and(_can_refill_T_1, _can_refill_T_2) node _tag_T = cat(UInt<47>(0h0), UInt<1>(0h0)) node tag_1 = cat(UInt<1>(0h1), _tag_T) node _hits_T_9 = eq(tags_1[0], tag_1) node _hits_T_10 = eq(tags_1[1], tag_1) node _hits_T_11 = eq(tags_1[2], tag_1) node _hits_T_12 = eq(tags_1[3], tag_1) node _hits_T_13 = eq(tags_1[4], tag_1) node _hits_T_14 = eq(tags_1[5], tag_1) node _hits_T_15 = eq(tags_1[6], tag_1) node _hits_T_16 = eq(tags_1[7], tag_1) node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9) node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11) node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1) node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13) node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15) node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1) node _hits_T_17 = cat(hits_hi_1, hits_lo_1) node hits_1 = and(_hits_T_17, valid_1) node _hit_T_1 = orr(hits_1) node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1) node _T_80 = and(mem_resp_valid, traverse) node _T_81 = and(_T_80, can_refill) node _T_82 = orr(hits_1) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = and(_T_81, _T_83) node _T_85 = eq(invalidated, UInt<1>(0h0)) node _T_86 = and(_T_84, _T_85) when _T_86 : node _r_T_27 = andr(valid_1) node r_left_subtree_older_3 = bits(state_reg_1, 6, 6) node r_left_subtree_state_3 = bits(state_reg_1, 5, 3) node r_right_subtree_state_3 = bits(state_reg_1, 2, 0) node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2) node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1) node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0) node _r_T_28 = bits(r_left_subtree_state_4, 0, 0) node _r_T_29 = bits(r_right_subtree_state_4, 0, 0) node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29) node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30) node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2) node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1) node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0) node _r_T_32 = bits(r_left_subtree_state_5, 0, 0) node _r_T_33 = bits(r_right_subtree_state_5, 0, 0) node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33) node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34) node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35) node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36) node _r_T_38 = not(valid_1) node _r_T_39 = bits(_r_T_38, 0, 0) node _r_T_40 = bits(_r_T_38, 1, 1) node _r_T_41 = bits(_r_T_38, 2, 2) node _r_T_42 = bits(_r_T_38, 3, 3) node _r_T_43 = bits(_r_T_38, 4, 4) node _r_T_44 = bits(_r_T_38, 5, 5) node _r_T_45 = bits(_r_T_38, 6, 6) node _r_T_46 = bits(_r_T_38, 7, 7) node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7)) node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47) node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48) node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49) node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50) node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51) node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52) node r_1 = mux(_r_T_27, _r_T_37, _r_T_53) node _valid_T_2 = dshl(UInt<1>(0h1), r_1) node _valid_T_3 = or(valid_1, _valid_T_2) connect valid_1, _valid_T_3 connect tags_1[r_1], tag_1 connect data_1[r_1], pte.ppn node state_reg_touch_way_sized_2 = bits(r_1, 2, 0) node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2) node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0)) node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3) node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0) node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0) node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1) node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0)) node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1) node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0) node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0) node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0)) node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49) node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0) node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0)) node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7) node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50) node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54) node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55) node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0) node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1) node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0)) node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1) node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0) node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0) node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0)) node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60) node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0) node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0)) node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8) node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61) node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65) node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6) node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56) node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67) connect state_reg_1, _state_reg_T_68 node _T_87 = eq(state, UInt<3>(0h1)) node _T_88 = and(stage2_pte_cache_hit, _T_87) when _T_88 : node hi_2 = bits(hits_1, 7, 4) node lo_2 = bits(hits_1, 3, 0) node _T_89 = orr(hi_2) node _T_90 = or(hi_2, lo_2) node hi_3 = bits(_T_90, 3, 2) node lo_3 = bits(_T_90, 1, 0) node _T_91 = orr(hi_3) node _T_92 = or(hi_3, lo_3) node _T_93 = bits(_T_92, 1, 1) node _T_94 = cat(_T_91, _T_93) node _T_95 = cat(_T_89, _T_94) node state_reg_touch_way_sized_3 = bits(_T_95, 2, 0) node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2) node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0)) node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3) node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0) node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0) node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1) node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0)) node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1) node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0) node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0) node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0) node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0)) node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72) node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0) node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0) node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0)) node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10) node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73) node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77) node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78) node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0) node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1) node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0)) node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1) node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0) node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0) node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0) node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0)) node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83) node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0) node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0) node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0)) node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11) node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84) node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88) node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9) node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79) node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90) connect state_reg_1, _state_reg_T_91 node _T_96 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) node _T_97 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _T_98 = or(_T_96, _T_97) node _T_99 = and(io.dpath.sfence.valid, _T_98) when _T_99 : connect valid_1, UInt<1>(0h0) node _T_100 = eq(state, UInt<3>(0h1)) node _T_101 = and(stage2_pte_cache_hit, _T_100) node _T_102 = eq(aux_count, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(state, UInt<3>(0h1)) node _T_105 = and(stage2_pte_cache_hit, _T_104) node _T_106 = eq(aux_count, UInt<1>(0h1)) node _T_107 = and(_T_105, _T_106) node _T_108 = eq(state, UInt<3>(0h1)) node _T_109 = and(stage2_pte_cache_hit, _T_108) node _T_110 = eq(aux_count, UInt<2>(0h2)) node _T_111 = and(_T_109, _T_110) node _T_112 = bits(hits_1, 0, 0) node _T_113 = bits(hits_1, 1, 1) node _T_114 = bits(hits_1, 2, 2) node _T_115 = bits(hits_1, 3, 3) node _T_116 = bits(hits_1, 4, 4) node _T_117 = bits(hits_1, 5, 5) node _T_118 = bits(hits_1, 6, 6) node _T_119 = bits(hits_1, 7, 7) node _T_120 = mux(_T_112, data_1[0], UInt<1>(0h0)) node _T_121 = mux(_T_113, data_1[1], UInt<1>(0h0)) node _T_122 = mux(_T_114, data_1[2], UInt<1>(0h0)) node _T_123 = mux(_T_115, data_1[3], UInt<1>(0h0)) node _T_124 = mux(_T_116, data_1[4], UInt<1>(0h0)) node _T_125 = mux(_T_117, data_1[5], UInt<1>(0h0)) node _T_126 = mux(_T_118, data_1[6], UInt<1>(0h0)) node _T_127 = mux(_T_119, data_1[7], UInt<1>(0h0)) node _T_128 = or(_T_120, _T_121) node _T_129 = or(_T_128, _T_122) node _T_130 = or(_T_129, _T_123) node _T_131 = or(_T_130, _T_124) node _T_132 = or(_T_131, _T_125) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) wire stage2_pte_cache_data : UInt<20> connect stage2_pte_cache_data, _T_134 reg pte_hit : UInt<1>, clock connect pte_hit, UInt<1>(0h0) connect io.dpath.perf.pte_miss, UInt<1>(0h0) node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1)) node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T) node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0)) node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2) connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3 node _T_135 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit) node _T_136 = and(io.dpath.perf.l2hit, _T_135) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf assert(clock, _T_137, UInt<1>(0h1), "") : assert reg l2_refill : UInt<1>, clock connect l2_refill, UInt<1>(0h0) connect l2_refill_wire, l2_refill connect io.dpath.perf.l2miss, UInt<1>(0h0) connect io.dpath.perf.l2hit, UInt<1>(0h0) wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect _WIRE_1.v, UInt<1>(0h0) connect _WIRE_1.r, UInt<1>(0h0) connect _WIRE_1.w, UInt<1>(0h0) connect _WIRE_1.x, UInt<1>(0h0) connect _WIRE_1.u, UInt<1>(0h0) connect _WIRE_1.g, UInt<1>(0h0) connect _WIRE_1.a, UInt<1>(0h0) connect _WIRE_1.d, UInt<1>(0h0) connect _WIRE_1.reserved_for_software, UInt<2>(0h0) connect _WIRE_1.ppn, UInt<44>(0h0) connect _WIRE_1.reserved_for_future, UInt<10>(0h0) wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect l2_pte, _WIRE_1 node _invalidated_T = neq(state, UInt<3>(0h0)) node _invalidated_T_1 = and(invalidated, _invalidated_T) node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1) connect invalidated, _invalidated_T_2 connect io.mem.keep_clock_enabled, UInt<1>(0h0) node _io_mem_req_valid_T = eq(state, UInt<3>(0h1)) node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3)) node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1) connect io.mem.req.valid, _io_mem_req_valid_T_2 connect io.mem.req.bits.phys, UInt<1>(0h1) connect io.mem.req.bits.cmd, UInt<1>(0h0) connect io.mem.req.bits.size, UInt<2>(0h3) connect io.mem.req.bits.signed, UInt<1>(0h0) connect io.mem.req.bits.addr, pte_addr connect io.mem.req.bits.dprv, UInt<1>(0h1) node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0)) node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T) connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1 invalidate io.mem.req.bits.tag connect io.mem.req.bits.no_resp, UInt<1>(0h0) invalidate io.mem.req.bits.no_alloc invalidate io.mem.req.bits.no_xcpt invalidate io.mem.req.bits.data invalidate io.mem.req.bits.mask node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2)) node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T) node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf) connect io.mem.s1_kill, _io_mem_s1_kill_T_2 invalidate io.mem.s1_data.mask invalidate io.mem.s1_data.data connect io.mem.s2_kill, UInt<1>(0h0) node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_10 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_13 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_14 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_15 = xor(_pmaPgLevelHomogeneous_T_14, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_16 = cvt(_pmaPgLevelHomogeneous_T_15) node _pmaPgLevelHomogeneous_T_17 = and(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_18 = asSInt(_pmaPgLevelHomogeneous_T_17) node _pmaPgLevelHomogeneous_T_19 = eq(_pmaPgLevelHomogeneous_T_18, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_20 = xor(_pmaPgLevelHomogeneous_T_14, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_21 = cvt(_pmaPgLevelHomogeneous_T_20) node _pmaPgLevelHomogeneous_T_22 = and(_pmaPgLevelHomogeneous_T_21, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_23 = asSInt(_pmaPgLevelHomogeneous_T_22) node _pmaPgLevelHomogeneous_T_24 = eq(_pmaPgLevelHomogeneous_T_23, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_25 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_19) node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_25, _pmaPgLevelHomogeneous_T_24) node _pmaPgLevelHomogeneous_T_26 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_27 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_14, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28) node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30) node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32) node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_35 = xor(_pmaPgLevelHomogeneous_T_14, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_36 = cvt(_pmaPgLevelHomogeneous_T_35) node _pmaPgLevelHomogeneous_T_37 = and(_pmaPgLevelHomogeneous_T_36, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_38 = asSInt(_pmaPgLevelHomogeneous_T_37) node _pmaPgLevelHomogeneous_T_39 = eq(_pmaPgLevelHomogeneous_T_38, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_40 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_39) node _pmaPgLevelHomogeneous_T_41 = eq(_pmaPgLevelHomogeneous_T_40, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_42 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_43 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_44 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_45 = xor(_pmaPgLevelHomogeneous_T_44, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_46 = cvt(_pmaPgLevelHomogeneous_T_45) node _pmaPgLevelHomogeneous_T_47 = and(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<14>(0h2000))) node _pmaPgLevelHomogeneous_T_48 = asSInt(_pmaPgLevelHomogeneous_T_47) node _pmaPgLevelHomogeneous_T_49 = eq(_pmaPgLevelHomogeneous_T_48, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_50 = xor(_pmaPgLevelHomogeneous_T_44, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_51 = cvt(_pmaPgLevelHomogeneous_T_50) node _pmaPgLevelHomogeneous_T_52 = and(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_53 = asSInt(_pmaPgLevelHomogeneous_T_52) node _pmaPgLevelHomogeneous_T_54 = eq(_pmaPgLevelHomogeneous_T_53, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_55 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_56 = cvt(_pmaPgLevelHomogeneous_T_55) node _pmaPgLevelHomogeneous_T_57 = and(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_58 = asSInt(_pmaPgLevelHomogeneous_T_57) node _pmaPgLevelHomogeneous_T_59 = eq(_pmaPgLevelHomogeneous_T_58, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_60 = xor(_pmaPgLevelHomogeneous_T_44, UInt<21>(0h100000)) node _pmaPgLevelHomogeneous_T_61 = cvt(_pmaPgLevelHomogeneous_T_60) node _pmaPgLevelHomogeneous_T_62 = and(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<18>(0h2f000))) node _pmaPgLevelHomogeneous_T_63 = asSInt(_pmaPgLevelHomogeneous_T_62) node _pmaPgLevelHomogeneous_T_64 = eq(_pmaPgLevelHomogeneous_T_63, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_65 = xor(_pmaPgLevelHomogeneous_T_44, UInt<26>(0h2000000)) node _pmaPgLevelHomogeneous_T_66 = cvt(_pmaPgLevelHomogeneous_T_65) node _pmaPgLevelHomogeneous_T_67 = and(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_68 = asSInt(_pmaPgLevelHomogeneous_T_67) node _pmaPgLevelHomogeneous_T_69 = eq(_pmaPgLevelHomogeneous_T_68, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_70 = xor(_pmaPgLevelHomogeneous_T_44, UInt<26>(0h2010000)) node _pmaPgLevelHomogeneous_T_71 = cvt(_pmaPgLevelHomogeneous_T_70) node _pmaPgLevelHomogeneous_T_72 = and(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_73 = asSInt(_pmaPgLevelHomogeneous_T_72) node _pmaPgLevelHomogeneous_T_74 = eq(_pmaPgLevelHomogeneous_T_73, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_75 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_76 = cvt(_pmaPgLevelHomogeneous_T_75) node _pmaPgLevelHomogeneous_T_77 = and(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_78 = asSInt(_pmaPgLevelHomogeneous_T_77) node _pmaPgLevelHomogeneous_T_79 = eq(_pmaPgLevelHomogeneous_T_78, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_80 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_81 = cvt(_pmaPgLevelHomogeneous_T_80) node _pmaPgLevelHomogeneous_T_82 = and(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_83 = asSInt(_pmaPgLevelHomogeneous_T_82) node _pmaPgLevelHomogeneous_T_84 = eq(_pmaPgLevelHomogeneous_T_83, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_85 = xor(_pmaPgLevelHomogeneous_T_44, UInt<29>(0h10020000)) node _pmaPgLevelHomogeneous_T_86 = cvt(_pmaPgLevelHomogeneous_T_85) node _pmaPgLevelHomogeneous_T_87 = and(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_88 = asSInt(_pmaPgLevelHomogeneous_T_87) node _pmaPgLevelHomogeneous_T_89 = eq(_pmaPgLevelHomogeneous_T_88, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_90 = xor(_pmaPgLevelHomogeneous_T_44, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_91 = cvt(_pmaPgLevelHomogeneous_T_90) node _pmaPgLevelHomogeneous_T_92 = and(_pmaPgLevelHomogeneous_T_91, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_93 = asSInt(_pmaPgLevelHomogeneous_T_92) node _pmaPgLevelHomogeneous_T_94 = eq(_pmaPgLevelHomogeneous_T_93, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_95 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_49) node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_54) node _pmaPgLevelHomogeneous_T_97 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_59) node _pmaPgLevelHomogeneous_T_98 = or(_pmaPgLevelHomogeneous_T_97, _pmaPgLevelHomogeneous_T_64) node _pmaPgLevelHomogeneous_T_99 = or(_pmaPgLevelHomogeneous_T_98, _pmaPgLevelHomogeneous_T_69) node _pmaPgLevelHomogeneous_T_100 = or(_pmaPgLevelHomogeneous_T_99, _pmaPgLevelHomogeneous_T_74) node _pmaPgLevelHomogeneous_T_101 = or(_pmaPgLevelHomogeneous_T_100, _pmaPgLevelHomogeneous_T_79) node _pmaPgLevelHomogeneous_T_102 = or(_pmaPgLevelHomogeneous_T_101, _pmaPgLevelHomogeneous_T_84) node _pmaPgLevelHomogeneous_T_103 = or(_pmaPgLevelHomogeneous_T_102, _pmaPgLevelHomogeneous_T_89) node pmaPgLevelHomogeneous_3 = or(_pmaPgLevelHomogeneous_T_103, _pmaPgLevelHomogeneous_T_94) node _pmaPgLevelHomogeneous_T_104 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105) node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107) node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_110 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109) node _pmaPgLevelHomogeneous_T_111 = eq(_pmaPgLevelHomogeneous_T_110, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_112 = xor(_pmaPgLevelHomogeneous_T_44, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_113 = cvt(_pmaPgLevelHomogeneous_T_112) node _pmaPgLevelHomogeneous_T_114 = and(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_115 = asSInt(_pmaPgLevelHomogeneous_T_114) node _pmaPgLevelHomogeneous_T_116 = eq(_pmaPgLevelHomogeneous_T_115, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_117 = xor(_pmaPgLevelHomogeneous_T_44, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_118 = cvt(_pmaPgLevelHomogeneous_T_117) node _pmaPgLevelHomogeneous_T_119 = and(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_120 = asSInt(_pmaPgLevelHomogeneous_T_119) node _pmaPgLevelHomogeneous_T_121 = eq(_pmaPgLevelHomogeneous_T_120, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_122 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_123 = cvt(_pmaPgLevelHomogeneous_T_122) node _pmaPgLevelHomogeneous_T_124 = and(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_125 = asSInt(_pmaPgLevelHomogeneous_T_124) node _pmaPgLevelHomogeneous_T_126 = eq(_pmaPgLevelHomogeneous_T_125, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_127 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_128 = cvt(_pmaPgLevelHomogeneous_T_127) node _pmaPgLevelHomogeneous_T_129 = and(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_130 = asSInt(_pmaPgLevelHomogeneous_T_129) node _pmaPgLevelHomogeneous_T_131 = eq(_pmaPgLevelHomogeneous_T_130, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_132 = xor(_pmaPgLevelHomogeneous_T_44, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_133 = cvt(_pmaPgLevelHomogeneous_T_132) node _pmaPgLevelHomogeneous_T_134 = and(_pmaPgLevelHomogeneous_T_133, asSInt(UInt<33>(0h90000000))) node _pmaPgLevelHomogeneous_T_135 = asSInt(_pmaPgLevelHomogeneous_T_134) node _pmaPgLevelHomogeneous_T_136 = eq(_pmaPgLevelHomogeneous_T_135, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_137 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_116) node _pmaPgLevelHomogeneous_T_138 = or(_pmaPgLevelHomogeneous_T_137, _pmaPgLevelHomogeneous_T_121) node _pmaPgLevelHomogeneous_T_139 = or(_pmaPgLevelHomogeneous_T_138, _pmaPgLevelHomogeneous_T_126) node _pmaPgLevelHomogeneous_T_140 = or(_pmaPgLevelHomogeneous_T_139, _pmaPgLevelHomogeneous_T_131) node _pmaPgLevelHomogeneous_T_141 = or(_pmaPgLevelHomogeneous_T_140, _pmaPgLevelHomogeneous_T_136) node _pmaPgLevelHomogeneous_T_142 = xor(_pmaPgLevelHomogeneous_T_44, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_143 = cvt(_pmaPgLevelHomogeneous_T_142) node _pmaPgLevelHomogeneous_T_144 = and(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<33>(0h8e000000))) node _pmaPgLevelHomogeneous_T_145 = asSInt(_pmaPgLevelHomogeneous_T_144) node _pmaPgLevelHomogeneous_T_146 = eq(_pmaPgLevelHomogeneous_T_145, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_44, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147) node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149) node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_146) node _pmaPgLevelHomogeneous_T_153 = or(_pmaPgLevelHomogeneous_T_152, _pmaPgLevelHomogeneous_T_151) node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154) node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156) node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158) node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_161 = xor(_pmaPgLevelHomogeneous_T_44, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_162 = cvt(_pmaPgLevelHomogeneous_T_161) node _pmaPgLevelHomogeneous_T_163 = and(_pmaPgLevelHomogeneous_T_162, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_164 = asSInt(_pmaPgLevelHomogeneous_T_163) node _pmaPgLevelHomogeneous_T_165 = eq(_pmaPgLevelHomogeneous_T_164, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_166 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_165) node _pmaPgLevelHomogeneous_T_167 = eq(_pmaPgLevelHomogeneous_T_166, UInt<1>(0h0)) node _pmaHomogeneous_T = eq(count, UInt<1>(0h1)) node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, UInt<1>(0h0), UInt<1>(0h0)) node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2)) node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1) node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3)) node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_3, _pmaHomogeneous_T_3) node _pmpHomogeneous_T = shl(r_pte.ppn, 12) wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0) connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0) connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0) node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T_4) node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6) node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2) node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3)) node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4) node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5) node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 39) node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0)) node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9) node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3)) node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11) node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12) node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 30) node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0)) node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16) node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3)) node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18) node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19) node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 21) node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0)) node _pmpHomogeneous_T_23 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_24 = not(_pmpHomogeneous_T_23) node _pmpHomogeneous_T_25 = or(_pmpHomogeneous_T_24, UInt<2>(0h3)) node _pmpHomogeneous_T_26 = not(_pmpHomogeneous_T_25) node _pmpHomogeneous_T_27 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_26) node _pmpHomogeneous_T_28 = shr(_pmpHomogeneous_T_27, 12) node _pmpHomogeneous_T_29 = neq(_pmpHomogeneous_T_28, UInt<1>(0h0)) node _pmpHomogeneous_T_30 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_31 = mux(_pmpHomogeneous_T_30, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8) node _pmpHomogeneous_T_32 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_33 = mux(_pmpHomogeneous_T_32, _pmpHomogeneous_T_22, _pmpHomogeneous_T_31) node _pmpHomogeneous_T_34 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_35 = mux(_pmpHomogeneous_T_34, _pmpHomogeneous_T_29, _pmpHomogeneous_T_33) node _pmpHomogeneous_T_36 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_35) node _pmpHomogeneous_T_37 = bits(io.dpath.pmp[0].cfg.a, 0, 0) node _pmpHomogeneous_T_38 = eq(_pmpHomogeneous_T_37, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T) node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2) node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3) node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T) node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2) node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3) node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_1) node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3) node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1) node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3) node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5) node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1) node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3) node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5) node _pmpHomogeneous_T_39 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper) node _pmpHomogeneous_T_40 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper) node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_39, _pmpHomogeneous_T_40) node _pmpHomogeneous_T_42 = or(_pmpHomogeneous_T_38, _pmpHomogeneous_T_41) node _pmpHomogeneous_T_43 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_36, _pmpHomogeneous_T_42) node _pmpHomogeneous_T_44 = and(UInt<1>(0h1), _pmpHomogeneous_T_43) node _pmpHomogeneous_T_45 = bits(io.dpath.pmp[1].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_8, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_12) node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14) node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46) node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3)) node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48) node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49) node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 39) node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0)) node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53) node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3)) node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55) node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56) node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 30) node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0)) node _pmpHomogeneous_T_60 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_61 = not(_pmpHomogeneous_T_60) node _pmpHomogeneous_T_62 = or(_pmpHomogeneous_T_61, UInt<2>(0h3)) node _pmpHomogeneous_T_63 = not(_pmpHomogeneous_T_62) node _pmpHomogeneous_T_64 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_63) node _pmpHomogeneous_T_65 = shr(_pmpHomogeneous_T_64, 21) node _pmpHomogeneous_T_66 = neq(_pmpHomogeneous_T_65, UInt<1>(0h0)) node _pmpHomogeneous_T_67 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_68 = not(_pmpHomogeneous_T_67) node _pmpHomogeneous_T_69 = or(_pmpHomogeneous_T_68, UInt<2>(0h3)) node _pmpHomogeneous_T_70 = not(_pmpHomogeneous_T_69) node _pmpHomogeneous_T_71 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_70) node _pmpHomogeneous_T_72 = shr(_pmpHomogeneous_T_71, 12) node _pmpHomogeneous_T_73 = neq(_pmpHomogeneous_T_72, UInt<1>(0h0)) node _pmpHomogeneous_T_74 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_75 = mux(_pmpHomogeneous_T_74, _pmpHomogeneous_T_59, _pmpHomogeneous_T_52) node _pmpHomogeneous_T_76 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_77 = mux(_pmpHomogeneous_T_76, _pmpHomogeneous_T_66, _pmpHomogeneous_T_75) node _pmpHomogeneous_T_78 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_79 = mux(_pmpHomogeneous_T_78, _pmpHomogeneous_T_73, _pmpHomogeneous_T_77) node _pmpHomogeneous_T_80 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_79) node _pmpHomogeneous_T_81 = bits(io.dpath.pmp[1].cfg.a, 0, 0) node _pmpHomogeneous_T_82 = eq(_pmpHomogeneous_T_81, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5) node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7) node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8) node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5) node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7) node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8) node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_6) node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8) node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7) node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9) node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11) node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7) node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9) node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11) node _pmpHomogeneous_T_83 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1) node _pmpHomogeneous_T_84 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1) node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_83, _pmpHomogeneous_T_84) node _pmpHomogeneous_T_86 = or(_pmpHomogeneous_T_82, _pmpHomogeneous_T_85) node _pmpHomogeneous_T_87 = mux(_pmpHomogeneous_T_45, _pmpHomogeneous_T_80, _pmpHomogeneous_T_86) node _pmpHomogeneous_T_88 = and(_pmpHomogeneous_T_44, _pmpHomogeneous_T_87) node _pmpHomogeneous_T_89 = bits(io.dpath.pmp[2].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_16, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_20) node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22) node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90) node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3)) node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92) node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93) node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 39) node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0)) node _pmpHomogeneous_T_97 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_98 = not(_pmpHomogeneous_T_97) node _pmpHomogeneous_T_99 = or(_pmpHomogeneous_T_98, UInt<2>(0h3)) node _pmpHomogeneous_T_100 = not(_pmpHomogeneous_T_99) node _pmpHomogeneous_T_101 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_100) node _pmpHomogeneous_T_102 = shr(_pmpHomogeneous_T_101, 30) node _pmpHomogeneous_T_103 = neq(_pmpHomogeneous_T_102, UInt<1>(0h0)) node _pmpHomogeneous_T_104 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_105 = not(_pmpHomogeneous_T_104) node _pmpHomogeneous_T_106 = or(_pmpHomogeneous_T_105, UInt<2>(0h3)) node _pmpHomogeneous_T_107 = not(_pmpHomogeneous_T_106) node _pmpHomogeneous_T_108 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_107) node _pmpHomogeneous_T_109 = shr(_pmpHomogeneous_T_108, 21) node _pmpHomogeneous_T_110 = neq(_pmpHomogeneous_T_109, UInt<1>(0h0)) node _pmpHomogeneous_T_111 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_112 = not(_pmpHomogeneous_T_111) node _pmpHomogeneous_T_113 = or(_pmpHomogeneous_T_112, UInt<2>(0h3)) node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113) node _pmpHomogeneous_T_115 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_114) node _pmpHomogeneous_T_116 = shr(_pmpHomogeneous_T_115, 12) node _pmpHomogeneous_T_117 = neq(_pmpHomogeneous_T_116, UInt<1>(0h0)) node _pmpHomogeneous_T_118 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_119 = mux(_pmpHomogeneous_T_118, _pmpHomogeneous_T_103, _pmpHomogeneous_T_96) node _pmpHomogeneous_T_120 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_121 = mux(_pmpHomogeneous_T_120, _pmpHomogeneous_T_110, _pmpHomogeneous_T_119) node _pmpHomogeneous_T_122 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_123 = mux(_pmpHomogeneous_T_122, _pmpHomogeneous_T_117, _pmpHomogeneous_T_121) node _pmpHomogeneous_T_124 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_123) node _pmpHomogeneous_T_125 = bits(io.dpath.pmp[2].cfg.a, 0, 0) node _pmpHomogeneous_T_126 = eq(_pmpHomogeneous_T_125, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10) node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12) node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13) node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10) node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12) node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13) node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_11) node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13) node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13) node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15) node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17) node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13) node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15) node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17) node _pmpHomogeneous_T_127 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2) node _pmpHomogeneous_T_128 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2) node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_127, _pmpHomogeneous_T_128) node _pmpHomogeneous_T_130 = or(_pmpHomogeneous_T_126, _pmpHomogeneous_T_129) node _pmpHomogeneous_T_131 = mux(_pmpHomogeneous_T_89, _pmpHomogeneous_T_124, _pmpHomogeneous_T_130) node _pmpHomogeneous_T_132 = and(_pmpHomogeneous_T_88, _pmpHomogeneous_T_131) node _pmpHomogeneous_T_133 = bits(io.dpath.pmp[3].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_24, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_28) node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30) node _pmpHomogeneous_T_134 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_135 = not(_pmpHomogeneous_T_134) node _pmpHomogeneous_T_136 = or(_pmpHomogeneous_T_135, UInt<2>(0h3)) node _pmpHomogeneous_T_137 = not(_pmpHomogeneous_T_136) node _pmpHomogeneous_T_138 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_137) node _pmpHomogeneous_T_139 = shr(_pmpHomogeneous_T_138, 39) node _pmpHomogeneous_T_140 = neq(_pmpHomogeneous_T_139, UInt<1>(0h0)) node _pmpHomogeneous_T_141 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_142 = not(_pmpHomogeneous_T_141) node _pmpHomogeneous_T_143 = or(_pmpHomogeneous_T_142, UInt<2>(0h3)) node _pmpHomogeneous_T_144 = not(_pmpHomogeneous_T_143) node _pmpHomogeneous_T_145 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_144) node _pmpHomogeneous_T_146 = shr(_pmpHomogeneous_T_145, 30) node _pmpHomogeneous_T_147 = neq(_pmpHomogeneous_T_146, UInt<1>(0h0)) node _pmpHomogeneous_T_148 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_149 = not(_pmpHomogeneous_T_148) node _pmpHomogeneous_T_150 = or(_pmpHomogeneous_T_149, UInt<2>(0h3)) node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150) node _pmpHomogeneous_T_152 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_151) node _pmpHomogeneous_T_153 = shr(_pmpHomogeneous_T_152, 21) node _pmpHomogeneous_T_154 = neq(_pmpHomogeneous_T_153, UInt<1>(0h0)) node _pmpHomogeneous_T_155 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_156 = not(_pmpHomogeneous_T_155) node _pmpHomogeneous_T_157 = or(_pmpHomogeneous_T_156, UInt<2>(0h3)) node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157) node _pmpHomogeneous_T_159 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_158) node _pmpHomogeneous_T_160 = shr(_pmpHomogeneous_T_159, 12) node _pmpHomogeneous_T_161 = neq(_pmpHomogeneous_T_160, UInt<1>(0h0)) node _pmpHomogeneous_T_162 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_163 = mux(_pmpHomogeneous_T_162, _pmpHomogeneous_T_147, _pmpHomogeneous_T_140) node _pmpHomogeneous_T_164 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_165 = mux(_pmpHomogeneous_T_164, _pmpHomogeneous_T_154, _pmpHomogeneous_T_163) node _pmpHomogeneous_T_166 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_167 = mux(_pmpHomogeneous_T_166, _pmpHomogeneous_T_161, _pmpHomogeneous_T_165) node _pmpHomogeneous_T_168 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_167) node _pmpHomogeneous_T_169 = bits(io.dpath.pmp[3].cfg.a, 0, 0) node _pmpHomogeneous_T_170 = eq(_pmpHomogeneous_T_169, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15) node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17) node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18) node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15) node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17) node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18) node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_16) node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18) node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19) node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21) node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23) node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19) node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21) node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23) node _pmpHomogeneous_T_171 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3) node _pmpHomogeneous_T_172 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3) node _pmpHomogeneous_T_173 = or(_pmpHomogeneous_T_171, _pmpHomogeneous_T_172) node _pmpHomogeneous_T_174 = or(_pmpHomogeneous_T_170, _pmpHomogeneous_T_173) node _pmpHomogeneous_T_175 = mux(_pmpHomogeneous_T_133, _pmpHomogeneous_T_168, _pmpHomogeneous_T_174) node _pmpHomogeneous_T_176 = and(_pmpHomogeneous_T_132, _pmpHomogeneous_T_175) node _pmpHomogeneous_T_177 = bits(io.dpath.pmp[4].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_32, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_36) node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38) node _pmpHomogeneous_T_178 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_179 = not(_pmpHomogeneous_T_178) node _pmpHomogeneous_T_180 = or(_pmpHomogeneous_T_179, UInt<2>(0h3)) node _pmpHomogeneous_T_181 = not(_pmpHomogeneous_T_180) node _pmpHomogeneous_T_182 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_181) node _pmpHomogeneous_T_183 = shr(_pmpHomogeneous_T_182, 39) node _pmpHomogeneous_T_184 = neq(_pmpHomogeneous_T_183, UInt<1>(0h0)) node _pmpHomogeneous_T_185 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_186 = not(_pmpHomogeneous_T_185) node _pmpHomogeneous_T_187 = or(_pmpHomogeneous_T_186, UInt<2>(0h3)) node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187) node _pmpHomogeneous_T_189 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_188) node _pmpHomogeneous_T_190 = shr(_pmpHomogeneous_T_189, 30) node _pmpHomogeneous_T_191 = neq(_pmpHomogeneous_T_190, UInt<1>(0h0)) node _pmpHomogeneous_T_192 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_193 = not(_pmpHomogeneous_T_192) node _pmpHomogeneous_T_194 = or(_pmpHomogeneous_T_193, UInt<2>(0h3)) node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194) node _pmpHomogeneous_T_196 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_195) node _pmpHomogeneous_T_197 = shr(_pmpHomogeneous_T_196, 21) node _pmpHomogeneous_T_198 = neq(_pmpHomogeneous_T_197, UInt<1>(0h0)) node _pmpHomogeneous_T_199 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_200 = not(_pmpHomogeneous_T_199) node _pmpHomogeneous_T_201 = or(_pmpHomogeneous_T_200, UInt<2>(0h3)) node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201) node _pmpHomogeneous_T_203 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_202) node _pmpHomogeneous_T_204 = shr(_pmpHomogeneous_T_203, 12) node _pmpHomogeneous_T_205 = neq(_pmpHomogeneous_T_204, UInt<1>(0h0)) node _pmpHomogeneous_T_206 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_207 = mux(_pmpHomogeneous_T_206, _pmpHomogeneous_T_191, _pmpHomogeneous_T_184) node _pmpHomogeneous_T_208 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_198, _pmpHomogeneous_T_207) node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_205, _pmpHomogeneous_T_209) node _pmpHomogeneous_T_212 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_211) node _pmpHomogeneous_T_213 = bits(io.dpath.pmp[4].cfg.a, 0, 0) node _pmpHomogeneous_T_214 = eq(_pmpHomogeneous_T_213, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20) node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22) node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23) node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20) node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22) node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23) node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_21) node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23) node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25) node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27) node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29) node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25) node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27) node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29) node _pmpHomogeneous_T_215 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4) node _pmpHomogeneous_T_216 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4) node _pmpHomogeneous_T_217 = or(_pmpHomogeneous_T_215, _pmpHomogeneous_T_216) node _pmpHomogeneous_T_218 = or(_pmpHomogeneous_T_214, _pmpHomogeneous_T_217) node _pmpHomogeneous_T_219 = mux(_pmpHomogeneous_T_177, _pmpHomogeneous_T_212, _pmpHomogeneous_T_218) node _pmpHomogeneous_T_220 = and(_pmpHomogeneous_T_176, _pmpHomogeneous_T_219) node _pmpHomogeneous_T_221 = bits(io.dpath.pmp[5].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_40, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_44) node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46) node _pmpHomogeneous_T_222 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_223 = not(_pmpHomogeneous_T_222) node _pmpHomogeneous_T_224 = or(_pmpHomogeneous_T_223, UInt<2>(0h3)) node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224) node _pmpHomogeneous_T_226 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_225) node _pmpHomogeneous_T_227 = shr(_pmpHomogeneous_T_226, 39) node _pmpHomogeneous_T_228 = neq(_pmpHomogeneous_T_227, UInt<1>(0h0)) node _pmpHomogeneous_T_229 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_230 = not(_pmpHomogeneous_T_229) node _pmpHomogeneous_T_231 = or(_pmpHomogeneous_T_230, UInt<2>(0h3)) node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231) node _pmpHomogeneous_T_233 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_232) node _pmpHomogeneous_T_234 = shr(_pmpHomogeneous_T_233, 30) node _pmpHomogeneous_T_235 = neq(_pmpHomogeneous_T_234, UInt<1>(0h0)) node _pmpHomogeneous_T_236 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_237 = not(_pmpHomogeneous_T_236) node _pmpHomogeneous_T_238 = or(_pmpHomogeneous_T_237, UInt<2>(0h3)) node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238) node _pmpHomogeneous_T_240 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_239) node _pmpHomogeneous_T_241 = shr(_pmpHomogeneous_T_240, 21) node _pmpHomogeneous_T_242 = neq(_pmpHomogeneous_T_241, UInt<1>(0h0)) node _pmpHomogeneous_T_243 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_244 = not(_pmpHomogeneous_T_243) node _pmpHomogeneous_T_245 = or(_pmpHomogeneous_T_244, UInt<2>(0h3)) node _pmpHomogeneous_T_246 = not(_pmpHomogeneous_T_245) node _pmpHomogeneous_T_247 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_246) node _pmpHomogeneous_T_248 = shr(_pmpHomogeneous_T_247, 12) node _pmpHomogeneous_T_249 = neq(_pmpHomogeneous_T_248, UInt<1>(0h0)) node _pmpHomogeneous_T_250 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_251 = mux(_pmpHomogeneous_T_250, _pmpHomogeneous_T_235, _pmpHomogeneous_T_228) node _pmpHomogeneous_T_252 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_253 = mux(_pmpHomogeneous_T_252, _pmpHomogeneous_T_242, _pmpHomogeneous_T_251) node _pmpHomogeneous_T_254 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_255 = mux(_pmpHomogeneous_T_254, _pmpHomogeneous_T_249, _pmpHomogeneous_T_253) node _pmpHomogeneous_T_256 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_255) node _pmpHomogeneous_T_257 = bits(io.dpath.pmp[5].cfg.a, 0, 0) node _pmpHomogeneous_T_258 = eq(_pmpHomogeneous_T_257, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25) node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27) node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28) node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25) node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27) node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28) node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_26) node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28) node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31) node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33) node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35) node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31) node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33) node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35) node _pmpHomogeneous_T_259 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5) node _pmpHomogeneous_T_260 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5) node _pmpHomogeneous_T_261 = or(_pmpHomogeneous_T_259, _pmpHomogeneous_T_260) node _pmpHomogeneous_T_262 = or(_pmpHomogeneous_T_258, _pmpHomogeneous_T_261) node _pmpHomogeneous_T_263 = mux(_pmpHomogeneous_T_221, _pmpHomogeneous_T_256, _pmpHomogeneous_T_262) node _pmpHomogeneous_T_264 = and(_pmpHomogeneous_T_220, _pmpHomogeneous_T_263) node _pmpHomogeneous_T_265 = bits(io.dpath.pmp[6].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_48, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_52) node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54) node _pmpHomogeneous_T_266 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_267 = not(_pmpHomogeneous_T_266) node _pmpHomogeneous_T_268 = or(_pmpHomogeneous_T_267, UInt<2>(0h3)) node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268) node _pmpHomogeneous_T_270 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_269) node _pmpHomogeneous_T_271 = shr(_pmpHomogeneous_T_270, 39) node _pmpHomogeneous_T_272 = neq(_pmpHomogeneous_T_271, UInt<1>(0h0)) node _pmpHomogeneous_T_273 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_274 = not(_pmpHomogeneous_T_273) node _pmpHomogeneous_T_275 = or(_pmpHomogeneous_T_274, UInt<2>(0h3)) node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275) node _pmpHomogeneous_T_277 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_276) node _pmpHomogeneous_T_278 = shr(_pmpHomogeneous_T_277, 30) node _pmpHomogeneous_T_279 = neq(_pmpHomogeneous_T_278, UInt<1>(0h0)) node _pmpHomogeneous_T_280 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_281 = not(_pmpHomogeneous_T_280) node _pmpHomogeneous_T_282 = or(_pmpHomogeneous_T_281, UInt<2>(0h3)) node _pmpHomogeneous_T_283 = not(_pmpHomogeneous_T_282) node _pmpHomogeneous_T_284 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_283) node _pmpHomogeneous_T_285 = shr(_pmpHomogeneous_T_284, 21) node _pmpHomogeneous_T_286 = neq(_pmpHomogeneous_T_285, UInt<1>(0h0)) node _pmpHomogeneous_T_287 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_288 = not(_pmpHomogeneous_T_287) node _pmpHomogeneous_T_289 = or(_pmpHomogeneous_T_288, UInt<2>(0h3)) node _pmpHomogeneous_T_290 = not(_pmpHomogeneous_T_289) node _pmpHomogeneous_T_291 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_290) node _pmpHomogeneous_T_292 = shr(_pmpHomogeneous_T_291, 12) node _pmpHomogeneous_T_293 = neq(_pmpHomogeneous_T_292, UInt<1>(0h0)) node _pmpHomogeneous_T_294 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_294, _pmpHomogeneous_T_279, _pmpHomogeneous_T_272) node _pmpHomogeneous_T_296 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_297 = mux(_pmpHomogeneous_T_296, _pmpHomogeneous_T_286, _pmpHomogeneous_T_295) node _pmpHomogeneous_T_298 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_299 = mux(_pmpHomogeneous_T_298, _pmpHomogeneous_T_293, _pmpHomogeneous_T_297) node _pmpHomogeneous_T_300 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_299) node _pmpHomogeneous_T_301 = bits(io.dpath.pmp[6].cfg.a, 0, 0) node _pmpHomogeneous_T_302 = eq(_pmpHomogeneous_T_301, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30) node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32) node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33) node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30) node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32) node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33) node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_31) node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33) node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37) node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39) node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41) node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37) node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39) node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41) node _pmpHomogeneous_T_303 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6) node _pmpHomogeneous_T_304 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6) node _pmpHomogeneous_T_305 = or(_pmpHomogeneous_T_303, _pmpHomogeneous_T_304) node _pmpHomogeneous_T_306 = or(_pmpHomogeneous_T_302, _pmpHomogeneous_T_305) node _pmpHomogeneous_T_307 = mux(_pmpHomogeneous_T_265, _pmpHomogeneous_T_300, _pmpHomogeneous_T_306) node _pmpHomogeneous_T_308 = and(_pmpHomogeneous_T_264, _pmpHomogeneous_T_307) node _pmpHomogeneous_T_309 = bits(io.dpath.pmp[7].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_56, UInt<1>(0h0)) node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_60) node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62) node _pmpHomogeneous_T_310 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_311 = not(_pmpHomogeneous_T_310) node _pmpHomogeneous_T_312 = or(_pmpHomogeneous_T_311, UInt<2>(0h3)) node _pmpHomogeneous_T_313 = not(_pmpHomogeneous_T_312) node _pmpHomogeneous_T_314 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_313) node _pmpHomogeneous_T_315 = shr(_pmpHomogeneous_T_314, 39) node _pmpHomogeneous_T_316 = neq(_pmpHomogeneous_T_315, UInt<1>(0h0)) node _pmpHomogeneous_T_317 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_318 = not(_pmpHomogeneous_T_317) node _pmpHomogeneous_T_319 = or(_pmpHomogeneous_T_318, UInt<2>(0h3)) node _pmpHomogeneous_T_320 = not(_pmpHomogeneous_T_319) node _pmpHomogeneous_T_321 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_320) node _pmpHomogeneous_T_322 = shr(_pmpHomogeneous_T_321, 30) node _pmpHomogeneous_T_323 = neq(_pmpHomogeneous_T_322, UInt<1>(0h0)) node _pmpHomogeneous_T_324 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_325 = not(_pmpHomogeneous_T_324) node _pmpHomogeneous_T_326 = or(_pmpHomogeneous_T_325, UInt<2>(0h3)) node _pmpHomogeneous_T_327 = not(_pmpHomogeneous_T_326) node _pmpHomogeneous_T_328 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_327) node _pmpHomogeneous_T_329 = shr(_pmpHomogeneous_T_328, 21) node _pmpHomogeneous_T_330 = neq(_pmpHomogeneous_T_329, UInt<1>(0h0)) node _pmpHomogeneous_T_331 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_332 = not(_pmpHomogeneous_T_331) node _pmpHomogeneous_T_333 = or(_pmpHomogeneous_T_332, UInt<2>(0h3)) node _pmpHomogeneous_T_334 = not(_pmpHomogeneous_T_333) node _pmpHomogeneous_T_335 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_334) node _pmpHomogeneous_T_336 = shr(_pmpHomogeneous_T_335, 12) node _pmpHomogeneous_T_337 = neq(_pmpHomogeneous_T_336, UInt<1>(0h0)) node _pmpHomogeneous_T_338 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_339 = mux(_pmpHomogeneous_T_338, _pmpHomogeneous_T_323, _pmpHomogeneous_T_316) node _pmpHomogeneous_T_340 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_341 = mux(_pmpHomogeneous_T_340, _pmpHomogeneous_T_330, _pmpHomogeneous_T_339) node _pmpHomogeneous_T_342 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_343 = mux(_pmpHomogeneous_T_342, _pmpHomogeneous_T_337, _pmpHomogeneous_T_341) node _pmpHomogeneous_T_344 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_343) node _pmpHomogeneous_T_345 = bits(io.dpath.pmp[7].cfg.a, 0, 0) node _pmpHomogeneous_T_346 = eq(_pmpHomogeneous_T_345, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35) node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37) node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38) node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35) node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37) node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38) node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hc0000000), UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hffe00000), _pmpHomogeneous_pgMask_T_36) node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38) node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43) node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45) node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47) node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43) node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45) node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47) node _pmpHomogeneous_T_347 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7) node _pmpHomogeneous_T_348 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7) node _pmpHomogeneous_T_349 = or(_pmpHomogeneous_T_347, _pmpHomogeneous_T_348) node _pmpHomogeneous_T_350 = or(_pmpHomogeneous_T_346, _pmpHomogeneous_T_349) node _pmpHomogeneous_T_351 = mux(_pmpHomogeneous_T_309, _pmpHomogeneous_T_344, _pmpHomogeneous_T_350) node pmpHomogeneous = and(_pmpHomogeneous_T_308, _pmpHomogeneous_T_351) node homogeneous = and(pmaHomogeneous, pmpHomogeneous) connect io.requestor[0].resp.valid, resp_valid[0] connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[0].resp.bits.ae_final, resp_ae_final connect io.requestor[0].resp.bits.pf, resp_pf connect io.requestor[0].resp.bits.gf, resp_gf connect io.requestor[0].resp.bits.hr, resp_hr connect io.requestor[0].resp.bits.hw, resp_hw connect io.requestor[0].resp.bits.hx, resp_hx connect io.requestor[0].resp.bits.pte, r_pte connect io.requestor[0].resp.bits.level, max_count node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1) node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3) node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 27) node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 26, 0) node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6) node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 18) node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 17, 0) node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9) node _io_requestor_0_resp_bits_gpa_bits_T_11 = shr(aux_pte.ppn, 9) node _io_requestor_0_resp_bits_gpa_bits_T_12 = bits(r_req.addr, 8, 0) node _io_requestor_0_resp_bits_gpa_bits_T_13 = cat(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_12) node _io_requestor_0_resp_bits_gpa_bits_T_14 = eq(aux_count, UInt<1>(0h1)) node _io_requestor_0_resp_bits_gpa_bits_T_15 = mux(_io_requestor_0_resp_bits_gpa_bits_T_14, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7) node _io_requestor_0_resp_bits_gpa_bits_T_16 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_0_resp_bits_gpa_bits_T_17 = mux(_io_requestor_0_resp_bits_gpa_bits_T_16, _io_requestor_0_resp_bits_gpa_bits_T_13, _io_requestor_0_resp_bits_gpa_bits_T_15) node _io_requestor_0_resp_bits_gpa_bits_T_18 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_0_resp_bits_gpa_bits_T_19 = mux(_io_requestor_0_resp_bits_gpa_bits_T_18, _io_requestor_0_resp_bits_gpa_bits_T_13, _io_requestor_0_resp_bits_gpa_bits_T_17) node _io_requestor_0_resp_bits_gpa_bits_T_20 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_19) node _io_requestor_0_resp_bits_gpa_bits_T_21 = cat(_io_requestor_0_resp_bits_gpa_bits_T_20, gpa_pgoff) connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_21 node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T connect io.requestor[0].ptbr, io.dpath.ptbr connect io.requestor[0].hgatp, io.dpath.hgatp connect io.requestor[0].vsatp, io.dpath.vsatp connect io.requestor[0].customCSRs, io.dpath.customCSRs connect io.requestor[0].status, io.dpath.status connect io.requestor[0].hstatus, io.dpath.hstatus connect io.requestor[0].gstatus, io.dpath.gstatus connect io.requestor[0].pmp, io.dpath.pmp connect io.requestor[1].resp.valid, resp_valid[1] connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[1].resp.bits.ae_final, resp_ae_final connect io.requestor[1].resp.bits.pf, resp_pf connect io.requestor[1].resp.bits.gf, resp_gf connect io.requestor[1].resp.bits.hr, resp_hr connect io.requestor[1].resp.bits.hw, resp_hw connect io.requestor[1].resp.bits.hx, resp_hx connect io.requestor[1].resp.bits.pte, r_pte connect io.requestor[1].resp.bits.level, max_count node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1) node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3) node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 27) node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 26, 0) node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6) node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 18) node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 17, 0) node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9) node _io_requestor_1_resp_bits_gpa_bits_T_11 = shr(aux_pte.ppn, 9) node _io_requestor_1_resp_bits_gpa_bits_T_12 = bits(r_req.addr, 8, 0) node _io_requestor_1_resp_bits_gpa_bits_T_13 = cat(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_12) node _io_requestor_1_resp_bits_gpa_bits_T_14 = eq(aux_count, UInt<1>(0h1)) node _io_requestor_1_resp_bits_gpa_bits_T_15 = mux(_io_requestor_1_resp_bits_gpa_bits_T_14, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7) node _io_requestor_1_resp_bits_gpa_bits_T_16 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_1_resp_bits_gpa_bits_T_17 = mux(_io_requestor_1_resp_bits_gpa_bits_T_16, _io_requestor_1_resp_bits_gpa_bits_T_13, _io_requestor_1_resp_bits_gpa_bits_T_15) node _io_requestor_1_resp_bits_gpa_bits_T_18 = eq(aux_count, UInt<2>(0h3)) node _io_requestor_1_resp_bits_gpa_bits_T_19 = mux(_io_requestor_1_resp_bits_gpa_bits_T_18, _io_requestor_1_resp_bits_gpa_bits_T_13, _io_requestor_1_resp_bits_gpa_bits_T_17) node _io_requestor_1_resp_bits_gpa_bits_T_20 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_19) node _io_requestor_1_resp_bits_gpa_bits_T_21 = cat(_io_requestor_1_resp_bits_gpa_bits_T_20, gpa_pgoff) connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_21 node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T connect io.requestor[1].ptbr, io.dpath.ptbr connect io.requestor[1].hgatp, io.dpath.hgatp connect io.requestor[1].vsatp, io.dpath.vsatp connect io.requestor[1].customCSRs, io.dpath.customCSRs connect io.requestor[1].status, io.dpath.status connect io.requestor[1].hstatus, io.dpath.hstatus connect io.requestor[1].gstatus, io.dpath.gstatus connect io.requestor[1].pmp, io.dpath.pmp wire next_state : UInt connect next_state, state inst state_barrier of OptimizationBarrier_UInt connect state_barrier.clock, clock connect state_barrier.reset, reset connect state_barrier.io.x, next_state connect state, state_barrier.io.y wire do_switch : UInt<1> connect do_switch, UInt<1>(0h0) node _T_141 = eq(UInt<3>(0h0), state) when _T_141 : node _T_142 = and(arb.io.out.ready, arb.io.out.valid) when _T_142 : node _satp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1) node _satp_initial_count_T_2 = bits(satp.mode, 0, 0) node _satp_initial_count_T_3 = sub(_satp_initial_count_T_1, _satp_initial_count_T_2) node satp_initial_count = tail(_satp_initial_count_T_3, 1) node _vsatp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1) node _vsatp_initial_count_T_2 = bits(io.dpath.vsatp.mode, 0, 0) node _vsatp_initial_count_T_3 = sub(_vsatp_initial_count_T_1, _vsatp_initial_count_T_2) node vsatp_initial_count = tail(_vsatp_initial_count_T_3, 1) node _hgatp_initial_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1) node _hgatp_initial_count_T_2 = bits(io.dpath.hgatp.mode, 0, 0) node _hgatp_initial_count_T_3 = sub(_hgatp_initial_count_T_1, _hgatp_initial_count_T_2) node hgatp_initial_count = tail(_hgatp_initial_count_T_3, 1) node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) connect r_req, arb.io.out.bits.bits connect r_req_dest, arb.io.chosen node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0)) connect next_state, _next_state_T connect stage2, arb.io.out.bits.bits.stage2 node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0)) node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T) connect stage2_final, _stage2_final_T_1 node _count_T_4 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) connect count, _count_T_4 node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0)) connect aux_count, _aux_count_T connect aux_pte.ppn, aux_ppn connect aux_pte.reserved_for_future, UInt<1>(0h0) connect resp_ae_ptw, UInt<1>(0h0) connect resp_ae_final, UInt<1>(0h0) connect resp_pf, UInt<1>(0h0) node _resp_gf_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1) node _resp_gf_count_T_2 = bits(io.dpath.hgatp.mode, 0, 0) node _resp_gf_count_T_3 = sub(_resp_gf_count_T_1, _resp_gf_count_T_2) node resp_gf_count = tail(_resp_gf_count_T_3, 1) node resp_gf_idxs_0 = shr(aux_ppn, 38) node resp_gf_idxs_1 = shr(aux_ppn, 29) wire _resp_gf_WIRE : UInt<15>[2] connect _resp_gf_WIRE[0], resp_gf_idxs_0 connect _resp_gf_WIRE[1], resp_gf_idxs_1 node _resp_gf_T = or(resp_gf_count, UInt<1>(0h0)) node _resp_gf_T_1 = bits(_resp_gf_T, 0, 0) node _resp_gf_T_2 = neq(_resp_gf_WIRE[_resp_gf_T_1], UInt<1>(0h0)) node _resp_gf_T_3 = and(_resp_gf_T_2, arb.io.out.bits.bits.stage2) connect resp_gf, _resp_gf_T_3 connect resp_hr, UInt<1>(0h1) connect resp_hw, UInt<1>(0h1) connect resp_hx, UInt<1>(0h1) connect resp_fragmented_superpage, UInt<1>(0h0) connect r_hgatp, io.dpath.hgatp node _T_143 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node _T_144 = or(_T_143, arb.io.out.bits.bits.stage2) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1 assert(clock, _T_144, UInt<1>(0h1), "") : assert_1 else : node _T_148 = eq(UInt<3>(0h1), state) when _T_148 : node _T_149 = eq(count, r_hgatp_initial_count) node _T_150 = and(stage2, _T_149) when _T_150 : node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h3)) node _gpa_pgoff_T_1 = shl(r_req.addr, 3) node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0)) connect gpa_pgoff, _gpa_pgoff_T_2 when stage2_pte_cache_hit : node _aux_count_T_1 = add(aux_count, UInt<1>(0h1)) node _aux_count_T_2 = tail(_aux_count_T_1, 1) connect aux_count, _aux_count_T_2 connect aux_pte.ppn, stage2_pte_cache_data connect aux_pte.reserved_for_future, UInt<1>(0h0) connect pte_hit, UInt<1>(0h1) else : when pte_cache_hit : node _count_T_5 = add(count, UInt<1>(0h1)) node _count_T_6 = tail(_count_T_5, 1) connect count, _count_T_6 connect pte_hit, UInt<1>(0h1) else : node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1)) connect next_state, _next_state_T_1 when resp_gf : connect next_state, UInt<3>(0h0) node _T_151 = or(r_req_dest, UInt<1>(0h0)) node _T_152 = bits(_T_151, 0, 0) connect resp_valid[_T_152], UInt<1>(0h1) else : node _T_153 = eq(UInt<3>(0h2), state) when _T_153 : node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4)) connect next_state, _next_state_T_2 else : node _T_154 = eq(UInt<3>(0h4), state) when _T_154 : connect next_state, UInt<3>(0h5) node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h3)) connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T when io.mem.s2_xcpt.ae.ld : connect resp_ae_ptw, UInt<1>(0h1) connect next_state, UInt<3>(0h0) node _T_155 = or(r_req_dest, UInt<1>(0h0)) node _T_156 = bits(_T_155, 0, 0) connect resp_valid[_T_156], UInt<1>(0h1) else : node _T_157 = eq(UInt<3>(0h7), state) when _T_157 : connect next_state, UInt<3>(0h0) node _T_158 = or(r_req_dest, UInt<1>(0h0)) node _T_159 = bits(_T_158, 0, 0) connect resp_valid[_T_159], UInt<1>(0h1) node _T_160 = eq(homogeneous, UInt<1>(0h0)) when _T_160 : connect count, UInt<2>(0h3) connect resp_fragmented_superpage, UInt<1>(0h1) when do_both_stages : connect resp_fragmented_superpage, UInt<1>(0h1) node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h3)) node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1)) node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffc0000), UInt<44>(0hffff8000000)) node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hffffffffe00), _merged_pte_superpage_mask_T_2) node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3)) node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4) node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 27) node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 26, 0) node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1) node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 18) node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 17, 0) node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3) node _merged_pte_stage1_ppns_T_4 = bits(pte.ppn, 43, 9) node _merged_pte_stage1_ppns_T_5 = bits(aux_pte.ppn, 8, 0) node merged_pte_stage1_ppns_2 = cat(_merged_pte_stage1_ppns_T_4, _merged_pte_stage1_ppns_T_5) node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1)) node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0) node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2)) node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, merged_pte_stage1_ppns_2, _merged_pte_stage1_ppn_T_1) node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3)) node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3) node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask) wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect merged_pte, aux_pte connect merged_pte.ppn, _merged_pte_T node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T) node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0)) node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2) node _r_pte_T_4 = eq(state, UInt<3>(0h1)) node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit) node _r_pte_count_T = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_pte_count_T_1 = tail(_r_pte_count_T, 1) node _r_pte_count_T_2 = bits(r_hgatp.mode, 0, 0) node _r_pte_count_T_3 = sub(_r_pte_count_T_1, _r_pte_count_T_2) node r_pte_count = tail(_r_pte_count_T_3, 1) node r_pte_idxs_0 = shr(stage2_pte_cache_data, 36) node r_pte_idxs_1 = shr(stage2_pte_cache_data, 27) node _r_pte_lsbs_truncIdx_T = or(r_pte_count, UInt<1>(0h0)) node r_pte_lsbs_truncIdx = bits(_r_pte_lsbs_truncIdx_T, 0, 0) node _r_pte_lsbs_T = eq(r_pte_lsbs_truncIdx, UInt<1>(0h1)) node _r_pte_lsbs_T_1 = mux(_r_pte_lsbs_T, r_pte_idxs_1, r_pte_idxs_0) wire r_pte_lsbs : UInt<2> connect r_pte_lsbs, _r_pte_lsbs_T_1 wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte, l2_pte node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs) connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1 node _r_pte_T_6 = eq(state, UInt<3>(0h1)) node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit) wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_1, l2_pte connect r_pte_pte_1.ppn, pte_cache_data node _r_pte_count_T_4 = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_pte_count_T_5 = tail(_r_pte_count_T_4, 1) node _r_pte_count_T_6 = bits(r_hgatp.mode, 0, 0) node _r_pte_count_T_7 = sub(_r_pte_count_T_5, _r_pte_count_T_6) node r_pte_count_1 = tail(_r_pte_count_T_7, 1) node r_pte_idxs_0_1 = shr(pte.ppn, 36) node r_pte_idxs_1_1 = shr(pte.ppn, 27) node _r_pte_lsbs_truncIdx_T_1 = or(r_pte_count_1, UInt<1>(0h0)) node r_pte_lsbs_truncIdx_1 = bits(_r_pte_lsbs_truncIdx_T_1, 0, 0) node _r_pte_lsbs_T_2 = eq(r_pte_lsbs_truncIdx_1, UInt<1>(0h1)) node _r_pte_lsbs_T_3 = mux(_r_pte_lsbs_T_2, r_pte_idxs_1_1, r_pte_idxs_0_1) wire r_pte_lsbs_1 : UInt<2> connect r_pte_lsbs_1, _r_pte_lsbs_T_3 wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_2, r_pte node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1) connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3 node _r_pte_T_8 = eq(traverse, UInt<1>(0h0)) node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1) node _r_pte_T_10 = and(_r_pte_T_9, stage2) node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte) node _r_pte_T_12 = eq(state, UInt<3>(0h7)) node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0)) node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13) node _r_pte_T_15 = neq(count, UInt<2>(0h3)) node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15) node _r_pte_T_17 = shr(r_pte.ppn, 27) node _r_pte_T_18 = bits(r_req.addr, 26, 0) node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18) node _r_pte_T_20 = shr(r_pte.ppn, 18) node _r_pte_T_21 = bits(r_req.addr, 17, 0) node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21) node _r_pte_T_23 = shr(r_pte.ppn, 9) node _r_pte_T_24 = bits(r_req.addr, 8, 0) node _r_pte_T_25 = cat(_r_pte_T_23, _r_pte_T_24) node _r_pte_T_26 = eq(count, UInt<1>(0h1)) node _r_pte_T_27 = mux(_r_pte_T_26, _r_pte_T_22, _r_pte_T_19) node _r_pte_T_28 = eq(count, UInt<2>(0h2)) node _r_pte_T_29 = mux(_r_pte_T_28, _r_pte_T_25, _r_pte_T_27) node _r_pte_T_30 = eq(count, UInt<2>(0h3)) node _r_pte_T_31 = mux(_r_pte_T_30, _r_pte_T_25, _r_pte_T_29) wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_3, r_pte connect r_pte_pte_3.ppn, _r_pte_T_31 node _r_pte_T_32 = and(arb.io.out.ready, arb.io.out.valid) node _r_pte_count_T_8 = sub(UInt<3>(0h4), UInt<2>(0h3)) node _r_pte_count_T_9 = tail(_r_pte_count_T_8, 1) node _r_pte_count_T_10 = bits(io.dpath.hgatp.mode, 0, 0) node _r_pte_count_T_11 = sub(_r_pte_count_T_9, _r_pte_count_T_10) node r_pte_count_2 = tail(_r_pte_count_T_11, 1) node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 36) node r_pte_idxs_1_2 = shr(io.dpath.vsatp.ppn, 27) node _r_pte_lsbs_truncIdx_T_2 = or(r_pte_count_2, UInt<1>(0h0)) node r_pte_lsbs_truncIdx_2 = bits(_r_pte_lsbs_truncIdx_T_2, 0, 0) node _r_pte_lsbs_T_4 = eq(r_pte_lsbs_truncIdx_2, UInt<1>(0h1)) node _r_pte_lsbs_T_5 = mux(_r_pte_lsbs_T_4, r_pte_idxs_1_2, r_pte_idxs_0_2) wire r_pte_lsbs_2 : UInt<2> connect r_pte_lsbs_2, _r_pte_lsbs_T_5 wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_4, r_pte node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2) node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2) connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5 wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_5, r_pte connect r_pte_pte_5.ppn, satp.ppn node _r_pte_T_33 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5) node _r_pte_T_34 = mux(_r_pte_T_32, _r_pte_T_33, r_pte) node _r_pte_T_35 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_34) node _r_pte_T_36 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_35) node _r_pte_T_37 = mux(do_switch, r_pte_pte_2, _r_pte_T_36) node _r_pte_T_38 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_37) node _r_pte_T_39 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_38) node _r_pte_T_40 = mux(_r_pte_T_3, l2_pte, _r_pte_T_39) inst r_pte_barrier of OptimizationBarrier_PTE connect r_pte_barrier.clock, clock connect r_pte_barrier.reset, reset connect r_pte_barrier.io.x.v, _r_pte_T_40.v connect r_pte_barrier.io.x.r, _r_pte_T_40.r connect r_pte_barrier.io.x.w, _r_pte_T_40.w connect r_pte_barrier.io.x.x, _r_pte_T_40.x connect r_pte_barrier.io.x.u, _r_pte_T_40.u connect r_pte_barrier.io.x.g, _r_pte_T_40.g connect r_pte_barrier.io.x.a, _r_pte_T_40.a connect r_pte_barrier.io.x.d, _r_pte_T_40.d connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_40.reserved_for_software connect r_pte_barrier.io.x.ppn, _r_pte_T_40.ppn connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_40.reserved_for_future connect r_pte, r_pte_barrier.io.y node _T_161 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_162 = and(UInt<1>(0h0), _T_161) node _T_163 = eq(resp_gf, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) when _T_164 : node _T_165 = eq(state, UInt<3>(0h1)) node _T_166 = eq(state, UInt<3>(0h2)) node _T_167 = or(_T_165, _T_166) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_2 assert(clock, _T_167, UInt<1>(0h1), "") : assert_2 connect next_state, UInt<3>(0h0) node _T_171 = or(r_req_dest, UInt<1>(0h0)) node _T_172 = bits(_T_171, 0, 0) connect resp_valid[_T_172], UInt<1>(0h1) connect count, UInt<2>(0h3) when mem_resp_valid : node _T_173 = eq(state, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3 assert(clock, _T_173, UInt<1>(0h1), "") : assert_3 connect next_state, UInt<3>(0h1) when traverse : node _T_177 = eq(stage2, UInt<1>(0h0)) node _T_178 = and(do_both_stages, _T_177) when _T_178 : connect do_switch, UInt<1>(0h1) node _count_T_7 = add(count, UInt<1>(0h1)) node _count_T_8 = tail(_count_T_7, 1) connect count, _count_T_8 else : node _gf_T = eq(stage2_final, UInt<1>(0h0)) node _gf_T_1 = and(stage2, _gf_T) node _gf_T_2 = eq(pte.w, UInt<1>(0h0)) node _gf_T_3 = and(pte.x, _gf_T_2) node _gf_T_4 = or(pte.r, _gf_T_3) node _gf_T_5 = and(pte.v, _gf_T_4) node _gf_T_6 = and(_gf_T_5, pte.a) node _gf_T_7 = and(_gf_T_6, pte.r) node _gf_T_8 = and(_gf_T_7, pte.u) node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0)) node _gf_T_10 = and(_gf_T_1, _gf_T_9) node _gf_T_11 = eq(pte.w, UInt<1>(0h0)) node _gf_T_12 = and(pte.x, _gf_T_11) node _gf_T_13 = or(pte.r, _gf_T_12) node _gf_T_14 = and(pte.v, _gf_T_13) node _gf_T_15 = and(_gf_T_14, pte.a) node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _gf_T_17 = and(_gf_T_15, _gf_T_16) node _gf_T_18 = and(_gf_T_17, invalid_gpa) node gf = or(_gf_T_10, _gf_T_18) node ae = and(pte.v, invalid_paddr) node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0)) node pf = and(pte.v, _pf_T) node _success_T = eq(ae, UInt<1>(0h0)) node _success_T_1 = and(pte.v, _success_T) node _success_T_2 = eq(pf, UInt<1>(0h0)) node _success_T_3 = and(_success_T_1, _success_T_2) node _success_T_4 = eq(gf, UInt<1>(0h0)) node success = and(_success_T_3, _success_T_4) node _T_179 = eq(stage2_final, UInt<1>(0h0)) node _T_180 = and(do_both_stages, _T_179) node _T_181 = and(_T_180, success) when _T_181 : when stage2 : connect stage2, UInt<1>(0h0) connect count, aux_count else : connect stage2_final, UInt<1>(0h1) connect do_switch, UInt<1>(0h1) else : node _l2_refill_T = eq(count, UInt<2>(0h3)) node _l2_refill_T_1 = and(success, _l2_refill_T) node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0)) node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2) node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0)) node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0)) node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5) node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h3)) node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7) node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9) node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10) node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11) node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a) node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w) node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d) node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u) node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17) node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18) node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19) node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a) node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x) node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u) node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23) node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24) node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25) node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26) connect l2_refill, _l2_refill_T_27 connect count, max_count node _T_182 = eq(count, UInt<2>(0h3)) node _T_183 = eq(do_both_stages, UInt<1>(0h0)) node _T_184 = eq(aux_count, UInt<2>(0h3)) node _T_185 = or(_T_183, _T_184) node _T_186 = and(_T_182, _T_185) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = and(UInt<1>(0h0), _T_187) when _T_188 : connect next_state, UInt<3>(0h7) else : connect next_state, UInt<3>(0h0) node _T_189 = or(r_req_dest, UInt<1>(0h0)) node _T_190 = bits(_T_189, 0, 0) connect resp_valid[_T_190], UInt<1>(0h1) node _resp_ae_ptw_T = lt(count, UInt<2>(0h3)) node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T) node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0)) node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2) node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4) node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0)) node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6) node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0)) node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8) node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0)) node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10) node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0)) node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12) node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14) node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15) connect resp_ae_ptw, _resp_ae_ptw_T_16 node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0)) node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T) node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1) node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2) node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a) node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4) connect resp_ae_final, _resp_ae_final_T_5 node _resp_pf_T = eq(stage2, UInt<1>(0h0)) node _resp_pf_T_1 = and(pf, _resp_pf_T) connect resp_pf, _resp_pf_T_1 node _resp_gf_T_4 = and(pf, stage2) node _resp_gf_T_5 = or(gf, _resp_gf_T_4) connect resp_gf, _resp_gf_T_5 node _resp_hr_T = eq(stage2, UInt<1>(0h0)) node _resp_hr_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hr_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2) node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4) node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5) node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6) node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a) node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r) node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u) node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10) node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11) connect resp_hr, _resp_hr_T_12 node _resp_hw_T = eq(stage2, UInt<1>(0h0)) node _resp_hw_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hw_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2) node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4) node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5) node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6) node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a) node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w) node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d) node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u) node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11) node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12) connect resp_hw, _resp_hw_T_13 node _resp_hx_T = eq(stage2, UInt<1>(0h0)) node _resp_hx_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hx_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2) node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4) node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5) node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6) node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a) node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x) node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u) node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10) node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11) connect resp_hx, _resp_hx_T_12 when io.mem.s2_nack : node _T_191 = eq(state, UInt<3>(0h4)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4 assert(clock, _T_191, UInt<1>(0h1), "") : assert_4 connect next_state, UInt<3>(0h1) when do_switch : node _aux_count_T_3 = add(count, UInt<1>(0h1)) node _aux_count_T_4 = tail(_aux_count_T_3, 1) node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count) connect aux_count, _aux_count_T_5 connect count, r_hgatp_initial_count node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 27) node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 26, 0) node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1) node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 18) node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 17, 0) node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3) node _aux_pte_s1_ppns_T_4 = bits(pte.ppn, 43, 9) node _aux_pte_s1_ppns_T_5 = bits(r_req.addr, 8, 0) node aux_pte_s1_ppns_2 = cat(_aux_pte_s1_ppns_T_4, _aux_pte_s1_ppns_T_5) node _aux_pte_T = eq(count, UInt<1>(0h1)) node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0) node _aux_pte_T_2 = eq(count, UInt<2>(0h2)) node _aux_pte_T_3 = mux(_aux_pte_T_2, aux_pte_s1_ppns_2, _aux_pte_T_1) node _aux_pte_T_4 = eq(count, UInt<2>(0h3)) node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3) wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect aux_pte_pte, pte connect aux_pte_pte.ppn, _aux_pte_T_5 node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte) connect aux_pte, _aux_pte_T_6 connect stage2, UInt<1>(0h1) node _leaf_T = eq(traverse, UInt<1>(0h0)) node _leaf_T_1 = and(mem_resp_valid, _leaf_T) node _leaf_T_2 = eq(count, UInt<1>(0h0)) node leaf = and(_leaf_T_1, _leaf_T_2) node _T_195 = and(leaf, pte.v) node _T_196 = eq(invalid_paddr, UInt<1>(0h0)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(invalid_gpa, UInt<1>(0h0)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_201 = and(_T_199, _T_200) node _T_202 = and(leaf, pte.v) node _T_203 = and(_T_202, invalid_paddr) node _T_204 = and(leaf, pte.v) node _T_205 = and(_T_204, invalid_gpa) node _T_206 = and(leaf, pte.v) node _T_207 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_208 = and(_T_206, _T_207) node _T_209 = bits(mem_resp_data, 0, 0) node _T_210 = eq(_T_209, UInt<1>(0h0)) node _T_211 = and(leaf, _T_210) node _T_212 = eq(pte.v, UInt<1>(0h0)) node _T_213 = and(leaf, _T_212) node _T_214 = bits(mem_resp_data, 0, 0) node _T_215 = and(_T_213, _T_214) node _leaf_T_3 = eq(traverse, UInt<1>(0h0)) node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3) node _leaf_T_5 = eq(count, UInt<1>(0h1)) node leaf_1 = and(_leaf_T_4, _leaf_T_5) node _T_216 = and(leaf_1, pte.v) node _T_217 = eq(invalid_paddr, UInt<1>(0h0)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(invalid_gpa, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_222 = and(_T_220, _T_221) node _T_223 = and(leaf_1, pte.v) node _T_224 = and(_T_223, invalid_paddr) node _T_225 = and(leaf_1, pte.v) node _T_226 = and(_T_225, invalid_gpa) node _T_227 = and(leaf_1, pte.v) node _T_228 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_229 = and(_T_227, _T_228) node _T_230 = bits(mem_resp_data, 0, 0) node _T_231 = eq(_T_230, UInt<1>(0h0)) node _T_232 = and(leaf_1, _T_231) node _T_233 = eq(pte.v, UInt<1>(0h0)) node _T_234 = and(leaf_1, _T_233) node _T_235 = bits(mem_resp_data, 0, 0) node _T_236 = and(_T_234, _T_235) node _leaf_T_6 = eq(traverse, UInt<1>(0h0)) node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6) node _leaf_T_8 = eq(count, UInt<2>(0h2)) node leaf_2 = and(_leaf_T_7, _leaf_T_8) node _T_237 = and(leaf_2, pte.v) node _T_238 = eq(invalid_paddr, UInt<1>(0h0)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(invalid_gpa, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_243 = and(_T_241, _T_242) node _T_244 = and(leaf_2, pte.v) node _T_245 = and(_T_244, invalid_paddr) node _T_246 = and(leaf_2, pte.v) node _T_247 = and(_T_246, invalid_gpa) node _T_248 = and(leaf_2, pte.v) node _T_249 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = bits(mem_resp_data, 0, 0) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = and(leaf_2, _T_252) node _T_254 = eq(pte.v, UInt<1>(0h0)) node _T_255 = and(leaf_2, _T_254) node _T_256 = bits(mem_resp_data, 0, 0) node _T_257 = and(_T_255, _T_256) node _leaf_T_9 = eq(traverse, UInt<1>(0h0)) node _leaf_T_10 = and(mem_resp_valid, _leaf_T_9) node _leaf_T_11 = eq(count, UInt<2>(0h3)) node leaf_3 = and(_leaf_T_10, _leaf_T_11) node _T_258 = and(leaf_3, pte.v) node _T_259 = eq(invalid_paddr, UInt<1>(0h0)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(invalid_gpa, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_264 = and(_T_262, _T_263) node _T_265 = and(leaf_3, pte.v) node _T_266 = and(_T_265, invalid_paddr) node _T_267 = and(leaf_3, pte.v) node _T_268 = and(_T_267, invalid_gpa) node _T_269 = and(leaf_3, pte.v) node _T_270 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_271 = and(_T_269, _T_270) node _T_272 = bits(mem_resp_data, 0, 0) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = and(leaf_3, _T_273) node _T_275 = eq(count, UInt<2>(0h3)) node _T_276 = and(mem_resp_valid, _T_275) node _T_277 = eq(pte.r, UInt<1>(0h0)) node _T_278 = and(pte.v, _T_277) node _T_279 = eq(pte.w, UInt<1>(0h0)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(pte.x, UInt<1>(0h0)) node _T_282 = and(_T_280, _T_281) node _T_283 = eq(pte.d, UInt<1>(0h0)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(pte.a, UInt<1>(0h0)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(pte.u, UInt<1>(0h0)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_290 = and(_T_288, _T_289) node _T_291 = and(_T_276, _T_290) node _T_292 = eq(state, UInt<3>(0h4)) node _T_293 = and(_T_292, io.mem.s2_xcpt.ae.ld)

module PTW( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] input io_requestor_0_req_valid, // @[PTW.scala:220:14] input [35:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [47:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_sd, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_v, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sd, // @[PTW.scala:220:14] output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] input io_requestor_1_req_valid, // @[PTW.scala:220:14] input io_requestor_1_req_bits_valid, // @[PTW.scala:220:14] input [35:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [47:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_sd, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_v, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sd, // @[PTW.scala:220:14] output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [48:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_req_bits_dv, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14] input io_mem_s2_uncached, // @[PTW.scala:220:14] input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [48:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14] input [6:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14] input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14] input io_mem_resp_bits_signed, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14] input io_mem_resp_bits_dv, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14] input io_mem_resp_bits_replay, // @[PTW.scala:220:14] input io_mem_resp_bits_has_data, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14] input io_mem_replay_next, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14] input [48:0] io_mem_s2_gpa, // @[PTW.scala:220:14] input io_mem_ordered, // @[PTW.scala:220:14] input io_mem_store_pending, // @[PTW.scala:220:14] input io_mem_perf_acquire, // @[PTW.scala:220:14] input io_mem_perf_release, // @[PTW.scala:220:14] input io_mem_perf_grant, // @[PTW.scala:220:14] input io_mem_perf_tlbMiss, // @[PTW.scala:220:14] input io_mem_perf_blocked, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14] input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [47:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_sd, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_hstatus_spvp, // @[PTW.scala:220:14] input io_dpath_hstatus_spv, // @[PTW.scala:220:14] input io_dpath_hstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_debug, // @[PTW.scala:220:14] input io_dpath_gstatus_cease, // @[PTW.scala:220:14] input io_dpath_gstatus_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14] input io_dpath_gstatus_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14] input io_dpath_gstatus_v, // @[PTW.scala:220:14] input io_dpath_gstatus_sd, // @[PTW.scala:220:14] input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14] input io_dpath_gstatus_mpv, // @[PTW.scala:220:14] input io_dpath_gstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_mbe, // @[PTW.scala:220:14] input io_dpath_gstatus_sbe, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14] input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14] input io_dpath_gstatus_tsr, // @[PTW.scala:220:14] input io_dpath_gstatus_tw, // @[PTW.scala:220:14] input io_dpath_gstatus_tvm, // @[PTW.scala:220:14] input io_dpath_gstatus_mxr, // @[PTW.scala:220:14] input io_dpath_gstatus_sum, // @[PTW.scala:220:14] input io_dpath_gstatus_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14] input io_dpath_gstatus_spp, // @[PTW.scala:220:14] input io_dpath_gstatus_mpie, // @[PTW.scala:220:14] input io_dpath_gstatus_ube, // @[PTW.scala:220:14] input io_dpath_gstatus_spie, // @[PTW.scala:220:14] input io_dpath_gstatus_upie, // @[PTW.scala:220:14] input io_dpath_gstatus_mie, // @[PTW.scala:220:14] input io_dpath_gstatus_hie, // @[PTW.scala:220:14] input io_dpath_gstatus_sie, // @[PTW.scala:220:14] input io_dpath_gstatus_uie, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_perf_pte_hit, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire _arb_io_out_bits_valid; // @[PTW.scala:236:19] wire [35:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7] wire [35:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_valid_0 = io_requestor_1_req_bits_valid; // @[PTW.scala:219:7] wire [35:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [48:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7] wire [48:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7] wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [47:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7] wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_0 = io_dpath_gstatus_sd; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27] wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20] wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24] wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17] wire l2_pte_d = 1'h0; // @[PTW.scala:403:113] wire l2_pte_a = 1'h0; // @[PTW.scala:403:113] wire l2_pte_g = 1'h0; // @[PTW.scala:403:113] wire l2_pte_u = 1'h0; // @[PTW.scala:403:113] wire l2_pte_x = 1'h0; // @[PTW.scala:403:113] wire l2_pte_w = 1'h0; // @[PTW.scala:403:113] wire l2_pte_r = 1'h0; // @[PTW.scala:403:113] wire l2_pte_v = 1'h0; // @[PTW.scala:403:113] wire _pmaHomogeneous_T_1 = 1'h0; // @[package.scala:39:76] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32] wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _vsatp_initial_count_T_2 = 1'h0; // @[package.scala:163:13] wire _hgatp_initial_count_T_2 = 1'h0; // @[package.scala:163:13] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_count_T_2 = 1'h0; // @[package.scala:163:13] wire _resp_gf_T_3 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16] wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire r_pte_idxs_1 = 1'h0; // @[PTW.scala:778:58] wire _r_pte_lsbs_T_1 = 1'h0; // @[package.scala:39:76] wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26] wire _r_pte_count_T_10 = 1'h0; // @[package.scala:163:13] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27] wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43] wire [7:0] r_pte_idxs_0_2 = 8'h0; // @[PTW.scala:778:58] wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13] wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7] wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33] wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16] wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16] wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_8 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_9 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_10 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_11 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_12 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_13 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_26 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_27 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_42 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_43 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_104 = 1'h1; // @[TLBPermissions.scala:87:22] wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire _resp_gf_T_1 = 1'h1; // @[package.scala:163:13] wire _r_pte_T = 1'h1; // @[PTW.scala:670:19] wire r_pte_lsbs_truncIdx_2 = 1'h1; // @[package.scala:38:47] wire _r_pte_lsbs_T_4 = 1'h1; // @[package.scala:39:86] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire [16:0] r_pte_idxs_1_2 = 17'h0; // @[PTW.scala:778:58] wire [16:0] _r_pte_lsbs_T_5 = 17'h0; // @[package.scala:39:76] wire [2:0] _r_hgatp_initial_count_T_1 = 3'h1; // @[PTW.scala:286:42] wire [2:0] _count_T_1 = 3'h1; // @[PTW.scala:786:28] wire [2:0] _satp_initial_count_T_1 = 3'h1; // @[PTW.scala:586:45] wire [2:0] _vsatp_initial_count_T_1 = 3'h1; // @[PTW.scala:587:46] wire [2:0] vsatp_initial_count = 3'h1; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T_1 = 3'h1; // @[PTW.scala:588:46] wire [2:0] hgatp_initial_count = 3'h1; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T_1 = 3'h1; // @[PTW.scala:786:28] wire [2:0] resp_gf_count = 3'h1; // @[PTW.scala:786:44] wire [2:0] _resp_gf_T = 3'h1; // @[package.scala:24:40] wire [2:0] _r_pte_count_T_1 = 3'h1; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h1; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_9 = 3'h1; // @[PTW.scala:777:28] wire [2:0] r_pte_count_2 = 3'h1; // @[PTW.scala:777:44] wire [2:0] _r_pte_lsbs_truncIdx_T_2 = 3'h1; // @[package.scala:38:21] wire [3:0] _r_hgatp_initial_count_T = 4'h1; // @[PTW.scala:286:42] wire [3:0] _count_T = 4'h1; // @[PTW.scala:786:28] wire [3:0] _satp_initial_count_T = 4'h1; // @[PTW.scala:586:45] wire [3:0] _vsatp_initial_count_T = 4'h1; // @[PTW.scala:587:46] wire [3:0] _vsatp_initial_count_T_3 = 4'h1; // @[PTW.scala:587:62] wire [3:0] _hgatp_initial_count_T = 4'h1; // @[PTW.scala:588:46] wire [3:0] _hgatp_initial_count_T_3 = 4'h1; // @[PTW.scala:588:62] wire [3:0] _resp_gf_count_T = 4'h1; // @[PTW.scala:786:28] wire [3:0] _resp_gf_count_T_3 = 4'h1; // @[PTW.scala:786:44] wire [3:0] _r_pte_count_T = 4'h1; // @[PTW.scala:777:28] wire [3:0] _r_pte_count_T_4 = 4'h1; // @[PTW.scala:777:28] wire [3:0] _r_pte_count_T_8 = 4'h1; // @[PTW.scala:777:28] wire [3:0] _r_pte_count_T_11 = 4'h1; // @[PTW.scala:777:44] wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13] wire [2:0] _aux_count_T = 3'h0; // @[PTW.scala:597:27] wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [48:0] tag_1 = 49'h1000000000000; // @[PTW.scala:363:18] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [47:0] _tag_T = 48'h0; // @[package.scala:138:15] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57] wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [47:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [47:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire [48:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61] wire clock_en = _clock_en_T_3 | _clock_en_T_4; // @[CustomCSRs.scala:43:61] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [35:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20] reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20] reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20] reg [1:0] aux_count; // @[PTW.scala:278:22] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire _r_hgatp_initial_count_T_2 = r_hgatp_mode[0]; // @[package.scala:163:13] wire _count_T_2 = r_hgatp_mode[0]; // @[package.scala:163:13] wire _r_pte_count_T_2 = r_hgatp_mode[0]; // @[package.scala:163:13] wire _r_pte_count_T_6 = r_hgatp_mode[0]; // @[package.scala:163:13] wire [3:0] _r_hgatp_initial_count_T_3 = 4'h1 - {3'h0, _r_hgatp_initial_count_T_2}; // @[package.scala:163:13] wire [2:0] r_hgatp_initial_count = _r_hgatp_initial_count_T_3[2:0]; // @[PTW.scala:286:58] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {8'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_3 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [35:0] _res_ppn_T_2 = tmp_ppn[35:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [35:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {16'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {8'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (count != 2'h3 & (|(tmp_ppn[8:0])) | ~(count[1]) & (|(tmp_ppn[17:9])) | count == 2'h0 & (|(tmp_ppn[26:18])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:36])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [3:0] _count_T_3 = 4'h1 - {3'h0, _count_T_2}; // @[package.scala:163:13] wire [2:0] count_1 = _count_T_3[2:0]; // @[PTW.scala:786:44] wire [5:0] idxs_0 = tmp_ppn[43:38]; // @[PTW.scala:304:37, :787:58] wire [14:0] idxs_1 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (|(count_1[0] ? idxs_1 : {9'h0, idxs_0})); // @[package.scala:43:40, :163:13] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _GEN = count != 2'h3; // @[PTW.scala:259:18, :317:73] wire _traverse_T_18; // @[PTW.scala:317:73] assign _traverse_T_18 = _GEN; // @[PTW.scala:317:73] wire _can_hit_T; // @[PTW.scala:358:18] assign _can_hit_T = _GEN; // @[PTW.scala:317:73, :358:18] wire _io_dpath_perf_pte_miss_T; // @[PTW.scala:640:39] assign _io_dpath_perf_pte_miss_T = _GEN; // @[PTW.scala:317:73, :640:39] wire _r_pte_T_15; // @[PTW.scala:680:65] assign _r_pte_T_15 = _GEN; // @[PTW.scala:317:73, :680:65] wire _resp_ae_ptw_T; // @[PTW.scala:725:36] assign _resp_ae_ptw_T = _GEN; // @[PTW.scala:317:73, :725:36] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [16:0] _pte_addr_vpn_idxs_T = vpn[43:27]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [25:0] _pte_addr_vpn_idxs_T_1 = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_2 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_3 = _pte_addr_vpn_idxs_T_3[8:0]; // @[PTW.scala:322:{12,48}] wire [2:0] _GEN_0 = {1'h0, count}; // @[PTW.scala:259:18, :324:40] wire _T_149 = _GEN_0 == r_hgatp_initial_count; // @[PTW.scala:286:58, :324:40] wire _pte_addr_mask_T; // @[PTW.scala:324:40] assign _pte_addr_mask_T = _T_149; // @[PTW.scala:324:40] wire _can_hit_T_3; // @[PTW.scala:357:21] assign _can_hit_T_3 = _T_149; // @[PTW.scala:324:40, :357:21] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _T_51 = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _T_51; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_T_30 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_74; // @[package.scala:39:86] assign _pmpHomogeneous_T_74 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_5 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_118; // @[package.scala:39:86] assign _pmpHomogeneous_T_118 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_10 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_162; // @[package.scala:39:86] assign _pmpHomogeneous_T_162 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_15 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_206; // @[package.scala:39:86] assign _pmpHomogeneous_T_206 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_20 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_250; // @[package.scala:39:86] assign _pmpHomogeneous_T_250 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_25 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_294; // @[package.scala:39:86] assign _pmpHomogeneous_T_294 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_30 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_T_338; // @[package.scala:39:86] assign _pmpHomogeneous_T_338 = _T_51; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_35 = _T_51; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _T_51; // @[package.scala:39:86] wire _r_pte_T_26; // @[package.scala:39:86] assign _r_pte_T_26 = _T_51; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _T_51; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _T_51; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_55 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_55; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_T_32 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_2 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_76; // @[package.scala:39:86] assign _pmpHomogeneous_T_76 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_7 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_120; // @[package.scala:39:86] assign _pmpHomogeneous_T_120 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_12 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_164; // @[package.scala:39:86] assign _pmpHomogeneous_T_164 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_17 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_208; // @[package.scala:39:86] assign _pmpHomogeneous_T_208 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_22 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_252; // @[package.scala:39:86] assign _pmpHomogeneous_T_252 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_27 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_296; // @[package.scala:39:86] assign _pmpHomogeneous_T_296 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_32 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_T_340; // @[package.scala:39:86] assign _pmpHomogeneous_T_340 = _T_55; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_37 = _T_55; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_55; // @[package.scala:39:86] wire _r_pte_T_28; // @[package.scala:39:86] assign _r_pte_T_28 = _T_55; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_55; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_55; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_3 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] reg [6:0] state_reg; // @[Replacement.scala:168:70] reg [7:0] valid; // @[PTW.scala:352:24] reg [31:0] tags_0; // @[PTW.scala:353:19] reg [31:0] tags_1; // @[PTW.scala:353:19] reg [31:0] tags_2; // @[PTW.scala:353:19] reg [31:0] tags_3; // @[PTW.scala:353:19] reg [31:0] tags_4; // @[PTW.scala:353:19] reg [31:0] tags_5; // @[PTW.scala:353:19] reg [31:0] tags_6; // @[PTW.scala:353:19] reg [31:0] tags_7; // @[PTW.scala:353:19] reg [19:0] data_0; // @[PTW.scala:355:19] reg [19:0] data_1; // @[PTW.scala:355:19] reg [19:0] data_2; // @[PTW.scala:355:19] reg [19:0] data_3; // @[PTW.scala:355:19] reg [19:0] data_4; // @[PTW.scala:355:19] reg [19:0] data_5; // @[PTW.scala:355:19] reg [19:0] data_6; // @[PTW.scala:355:19] reg [19:0] data_7; // @[PTW.scala:355:19] wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65] wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}] wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}] wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15] wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27] wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27] wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27] wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27] wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27] wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27] wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27] wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27] wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20] wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}] wire _r_T = &valid; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13] wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13] wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13] wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13] wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13] wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13] wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57] wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45] wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45] wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45] wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45] wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45] wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45] wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45] wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45] wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13] wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35] wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13] wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13] wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire _T_165 = state == 3'h1; // @[PTW.scala:233:22, :377:24] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_165; // @[PTW.scala:377:24, :394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_165; // @[PTW.scala:377:24, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_165; // @[PTW.scala:377:24, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_165; // @[PTW.scala:377:24, :674:15] wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18] wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18] wire [3:0] _T_35 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_1 = _T_35[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_1 = _T_35[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13] wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13] wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16] wire _leaf_T_2 = count == 2'h0; // @[PTW.scala:259:18, :382:47, :751:53] wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36] reg [6:0] state_reg_1; // @[Replacement.scala:168:70] reg [7:0] valid_1; // @[PTW.scala:352:24] reg [19:0] data_1_0; // @[PTW.scala:355:19] reg [19:0] data_1_1; // @[PTW.scala:355:19] reg [19:0] data_1_2; // @[PTW.scala:355:19] reg [19:0] data_1_3; // @[PTW.scala:355:19] reg [19:0] data_1_4; // @[PTW.scala:355:19] reg [19:0] data_1_5; // @[PTW.scala:355:19] reg [19:0] data_1_6; // @[PTW.scala:355:19] reg [19:0] data_1_7; // @[PTW.scala:355:19] wire _can_hit_T_4 = aux_count != 2'h3; // @[PTW.scala:278:22, :357:60] wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}] wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}] wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}] wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107] wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}] wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33] wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}] wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44] wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}] wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13] wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13] wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13] wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13] wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57] wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45] wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45] wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45] wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45] wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45] wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45] wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45] wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45] wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45] wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45] wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45] wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45] wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45] wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45] wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13] wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35] wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13] wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13] wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38] wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13] wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13] wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13] wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13] wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13] wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12] wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38] wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12] wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16] wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16] wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16] wire _T_106 = aux_count == 2'h1; // @[PTW.scala:278:22, :382:47] wire _io_requestor_0_resp_bits_gpa_bits_T_14; // @[package.scala:39:86] assign _io_requestor_0_resp_bits_gpa_bits_T_14 = _T_106; // @[package.scala:39:86] wire _io_requestor_1_resp_bits_gpa_bits_T_14; // @[package.scala:39:86] assign _io_requestor_1_resp_bits_gpa_bits_T_14 = _T_106; // @[package.scala:39:86] wire _T_110 = aux_count == 2'h2; // @[PTW.scala:278:22, :382:47] wire _io_requestor_0_resp_bits_gpa_bits_T_16; // @[package.scala:39:86] assign _io_requestor_0_resp_bits_gpa_bits_T_16 = _T_110; // @[package.scala:39:86] wire _io_requestor_1_resp_bits_gpa_bits_T_16; // @[package.scala:39:86] assign _io_requestor_1_resp_bits_gpa_bits_T_16 = _T_110; // @[package.scala:39:86] reg pte_hit; // @[PTW.scala:392:24] wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}] assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}] assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {17'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN_1 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_14; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_14 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_44; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_44 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN_1; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_14; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_35 = _pmaPgLevelHomogeneous_T_14; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_15 = {_pmaPgLevelHomogeneous_T_14[55:28], _pmaPgLevelHomogeneous_T_14[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_16 = {1'h0, _pmaPgLevelHomogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_17; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_19 = _pmaPgLevelHomogeneous_T_18 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_19; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_20 = {_pmaPgLevelHomogeneous_T_14[55:32], _pmaPgLevelHomogeneous_T_14[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_21 = {1'h0, _pmaPgLevelHomogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_22 = _pmaPgLevelHomogeneous_T_21 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_25 | _pmaPgLevelHomogeneous_T_24; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_36 = {1'h0, _pmaPgLevelHomogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_37 = _pmaPgLevelHomogeneous_T_36 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_39 = _pmaPgLevelHomogeneous_T_38 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_41 = ~_pmaPgLevelHomogeneous_T_40; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_44; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_46 = {1'h0, _pmaPgLevelHomogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_48 = _pmaPgLevelHomogeneous_T_47; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_49 = _pmaPgLevelHomogeneous_T_48 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_44[55:14], _pmaPgLevelHomogeneous_T_44[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_50 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_117 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_51 = {1'h0, _pmaPgLevelHomogeneous_T_50}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_53 = _pmaPgLevelHomogeneous_T_52; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_54 = _pmaPgLevelHomogeneous_T_53 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_44[55:17], _pmaPgLevelHomogeneous_T_44[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_55 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_105; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_105 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_122 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_154 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_161; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_161 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_56 = {1'h0, _pmaPgLevelHomogeneous_T_55}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_58 = _pmaPgLevelHomogeneous_T_57; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_59 = _pmaPgLevelHomogeneous_T_58 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_60 = {_pmaPgLevelHomogeneous_T_44[55:21], _pmaPgLevelHomogeneous_T_44[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_61 = {1'h0, _pmaPgLevelHomogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_63 = _pmaPgLevelHomogeneous_T_62; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_64 = _pmaPgLevelHomogeneous_T_63 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_65 = {_pmaPgLevelHomogeneous_T_44[55:26], _pmaPgLevelHomogeneous_T_44[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_66 = {1'h0, _pmaPgLevelHomogeneous_T_65}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_68 = _pmaPgLevelHomogeneous_T_67; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_69 = _pmaPgLevelHomogeneous_T_68 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_70 = {_pmaPgLevelHomogeneous_T_44[55:26], _pmaPgLevelHomogeneous_T_44[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_71 = {1'h0, _pmaPgLevelHomogeneous_T_70}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_73 = _pmaPgLevelHomogeneous_T_72; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_74 = _pmaPgLevelHomogeneous_T_73 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_44[55:28], _pmaPgLevelHomogeneous_T_44[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_75 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_127 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_142 = _GEN_4; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_76 = {1'h0, _pmaPgLevelHomogeneous_T_75}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_78 = _pmaPgLevelHomogeneous_T_77; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_79 = _pmaPgLevelHomogeneous_T_78 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_80 = {_pmaPgLevelHomogeneous_T_44[55:28], _pmaPgLevelHomogeneous_T_44[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_81 = {1'h0, _pmaPgLevelHomogeneous_T_80}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_83 = _pmaPgLevelHomogeneous_T_82; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_84 = _pmaPgLevelHomogeneous_T_83 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_85 = {_pmaPgLevelHomogeneous_T_44[55:29], _pmaPgLevelHomogeneous_T_44[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_86 = {1'h0, _pmaPgLevelHomogeneous_T_85}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_87; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_5 = {_pmaPgLevelHomogeneous_T_44[55:32], _pmaPgLevelHomogeneous_T_44[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_90; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_90 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_132; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_132 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_5; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_91 = {1'h0, _pmaPgLevelHomogeneous_T_90}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_54; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_97 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_59; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_98 = _pmaPgLevelHomogeneous_T_97 | _pmaPgLevelHomogeneous_T_64; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_99 = _pmaPgLevelHomogeneous_T_98 | _pmaPgLevelHomogeneous_T_69; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 | _pmaPgLevelHomogeneous_T_74; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100 | _pmaPgLevelHomogeneous_T_79; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 | _pmaPgLevelHomogeneous_T_84; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102 | _pmaPgLevelHomogeneous_T_89; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_3 = _pmaPgLevelHomogeneous_T_103 | _pmaPgLevelHomogeneous_T_94; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_110 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_111 = ~_pmaPgLevelHomogeneous_T_110; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = {1'h0, _pmaPgLevelHomogeneous_T_112}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_115 = _pmaPgLevelHomogeneous_T_114; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_116 = _pmaPgLevelHomogeneous_T_115 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_116; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_118 = {1'h0, _pmaPgLevelHomogeneous_T_117}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_120 = _pmaPgLevelHomogeneous_T_119; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_121 = _pmaPgLevelHomogeneous_T_120 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_123 = {1'h0, _pmaPgLevelHomogeneous_T_122}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_125 = _pmaPgLevelHomogeneous_T_124; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_126 = _pmaPgLevelHomogeneous_T_125 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = {1'h0, _pmaPgLevelHomogeneous_T_127}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_129; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_133 = {1'h0, _pmaPgLevelHomogeneous_T_132}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 & 57'h90000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_135 = _pmaPgLevelHomogeneous_T_134; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_136 = _pmaPgLevelHomogeneous_T_135 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137 | _pmaPgLevelHomogeneous_T_121; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 | _pmaPgLevelHomogeneous_T_126; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_140 = _pmaPgLevelHomogeneous_T_139 | _pmaPgLevelHomogeneous_T_131; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_141 = _pmaPgLevelHomogeneous_T_140 | _pmaPgLevelHomogeneous_T_136; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_143 = {1'h0, _pmaPgLevelHomogeneous_T_142}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 & 57'h8E000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_144; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_146; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_153 = _pmaPgLevelHomogeneous_T_152 | _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_162 = {1'h0, _pmaPgLevelHomogeneous_T_161}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_163 = _pmaPgLevelHomogeneous_T_162 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_164 = _pmaPgLevelHomogeneous_T_163; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_165 = _pmaPgLevelHomogeneous_T_164 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_166 = _pmaPgLevelHomogeneous_T_165; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_167 = ~_pmaPgLevelHomogeneous_T_166; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 & pmaPgLevelHomogeneous_2; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_3 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 & _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}] wire [31:0] _GEN_6 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_2 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_9 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_23; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_23 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_24 = ~_pmpHomogeneous_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_25 = {_pmpHomogeneous_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_26 = ~_pmpHomogeneous_T_25; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_27 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_26}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_29 = |_pmpHomogeneous_T_28; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_31 = _pmpHomogeneous_T_30 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_33 = _pmpHomogeneous_T_32 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_34 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_34 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_33; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_36 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_35; // @[package.scala:39:76] wire _pmpHomogeneous_T_37 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_38 = ~_pmpHomogeneous_T_37; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}] wire _pmpHomogeneous_T_39 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21] wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}] wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T = _GEN_7; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_7; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_40 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62] wire _pmpHomogeneous_T_41 = _pmpHomogeneous_T_39 | _pmpHomogeneous_T_40; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_42 = _pmpHomogeneous_T_38 | _pmpHomogeneous_T_41; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_43 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_36 : _pmpHomogeneous_T_42; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_45 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 & _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}] wire [31:0] _GEN_8 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_46 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_53 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_60; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_60 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_67; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_67 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_61 = ~_pmpHomogeneous_T_60; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_62 = {_pmpHomogeneous_T_61[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_63 = ~_pmpHomogeneous_T_62; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_64 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_63}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_66 = |_pmpHomogeneous_T_65; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_69 = {_pmpHomogeneous_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_70 = ~_pmpHomogeneous_T_69; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_71 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_70}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_72 = _pmpHomogeneous_T_71[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_73 = |_pmpHomogeneous_T_72; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_75 = _pmpHomogeneous_T_74 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_77 = _pmpHomogeneous_T_76 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_75; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_78 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_79 = _pmpHomogeneous_T_78 ? _pmpHomogeneous_T_73 : _pmpHomogeneous_T_77; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_80 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_79; // @[package.scala:39:76] wire _pmpHomogeneous_T_81 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_82 = ~_pmpHomogeneous_T_81; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}] wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_9; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_9; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_83 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_84 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_85 = _pmpHomogeneous_T_83 | _pmpHomogeneous_T_84; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_86 = _pmpHomogeneous_T_82 | _pmpHomogeneous_T_85; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_87 = _pmpHomogeneous_T_45 ? _pmpHomogeneous_T_80 : _pmpHomogeneous_T_86; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_88 = _pmpHomogeneous_T_44 & _pmpHomogeneous_T_87; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_89 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 & _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}] wire [31:0] _GEN_10 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_90 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_97; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_97 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_104; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_104 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_111; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_111 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_98 = ~_pmpHomogeneous_T_97; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_99 = {_pmpHomogeneous_T_98[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_100 = ~_pmpHomogeneous_T_99; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_101 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_100}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_103 = |_pmpHomogeneous_T_102; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_106 = {_pmpHomogeneous_T_105[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_107 = ~_pmpHomogeneous_T_106; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_108 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_107}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_109 = _pmpHomogeneous_T_108[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_110 = |_pmpHomogeneous_T_109; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_112 = ~_pmpHomogeneous_T_111; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_113 = {_pmpHomogeneous_T_112[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_114}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_116 = _pmpHomogeneous_T_115[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_117 = |_pmpHomogeneous_T_116; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_119 = _pmpHomogeneous_T_118 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_96; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_121 = _pmpHomogeneous_T_120 ? _pmpHomogeneous_T_110 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_122 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_123 = _pmpHomogeneous_T_122 ? _pmpHomogeneous_T_117 : _pmpHomogeneous_T_121; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_124 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_123; // @[package.scala:39:76] wire _pmpHomogeneous_T_125 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_126 = ~_pmpHomogeneous_T_125; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}] wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_11; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_11; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_127 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_128 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_129 = _pmpHomogeneous_T_127 | _pmpHomogeneous_T_128; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_130 = _pmpHomogeneous_T_126 | _pmpHomogeneous_T_129; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_131 = _pmpHomogeneous_T_89 ? _pmpHomogeneous_T_124 : _pmpHomogeneous_T_130; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_132 = _pmpHomogeneous_T_88 & _pmpHomogeneous_T_131; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_133 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 & _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}] wire [31:0] _GEN_12 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_134; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_134 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_141; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_141 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_148; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_148 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_155; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_155 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_135 = ~_pmpHomogeneous_T_134; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_136 = {_pmpHomogeneous_T_135[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_137 = ~_pmpHomogeneous_T_136; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_138 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_137}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_140 = |_pmpHomogeneous_T_139; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_143 = {_pmpHomogeneous_T_142[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_144 = ~_pmpHomogeneous_T_143; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_145 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_144}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_146 = _pmpHomogeneous_T_145[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_147 = |_pmpHomogeneous_T_146; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_149 = ~_pmpHomogeneous_T_148; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_150 = {_pmpHomogeneous_T_149[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_151}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_153 = _pmpHomogeneous_T_152[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_154 = |_pmpHomogeneous_T_153; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_156 = ~_pmpHomogeneous_T_155; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_157 = {_pmpHomogeneous_T_156[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_158}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_160 = _pmpHomogeneous_T_159[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_161 = |_pmpHomogeneous_T_160; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_163 = _pmpHomogeneous_T_162 ? _pmpHomogeneous_T_147 : _pmpHomogeneous_T_140; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_165 = _pmpHomogeneous_T_164 ? _pmpHomogeneous_T_154 : _pmpHomogeneous_T_163; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_166 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_167 = _pmpHomogeneous_T_166 ? _pmpHomogeneous_T_161 : _pmpHomogeneous_T_165; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_168 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_167; // @[package.scala:39:76] wire _pmpHomogeneous_T_169 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_170 = ~_pmpHomogeneous_T_169; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}] wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_13; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_13; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_171 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_172 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_173 = _pmpHomogeneous_T_171 | _pmpHomogeneous_T_172; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_170 | _pmpHomogeneous_T_173; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_175 = _pmpHomogeneous_T_133 ? _pmpHomogeneous_T_168 : _pmpHomogeneous_T_174; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_132 & _pmpHomogeneous_T_175; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_177 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 & _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}] wire [31:0] _GEN_14 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_178; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_178 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_185; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_185 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_192; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_192 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_199; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_199 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_180 = {_pmpHomogeneous_T_179[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_181 = ~_pmpHomogeneous_T_180; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_182 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_181}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_183 = _pmpHomogeneous_T_182[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_184 = |_pmpHomogeneous_T_183; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_186 = ~_pmpHomogeneous_T_185; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_187 = {_pmpHomogeneous_T_186[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_188}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_190 = _pmpHomogeneous_T_189[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_191 = |_pmpHomogeneous_T_190; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_193 = ~_pmpHomogeneous_T_192; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_194 = {_pmpHomogeneous_T_193[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_195}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_197 = _pmpHomogeneous_T_196[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_198 = |_pmpHomogeneous_T_197; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_200 = ~_pmpHomogeneous_T_199; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_201 = {_pmpHomogeneous_T_200[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_202}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_204 = _pmpHomogeneous_T_203[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_205 = |_pmpHomogeneous_T_204; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_207 = _pmpHomogeneous_T_206 ? _pmpHomogeneous_T_191 : _pmpHomogeneous_T_184; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_198 : _pmpHomogeneous_T_207; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_210 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_205 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_212 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_211; // @[package.scala:39:76] wire _pmpHomogeneous_T_213 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_214 = ~_pmpHomogeneous_T_213; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}] wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_15; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_15; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_215 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_216 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_217 = _pmpHomogeneous_T_215 | _pmpHomogeneous_T_216; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_218 = _pmpHomogeneous_T_214 | _pmpHomogeneous_T_217; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_177 ? _pmpHomogeneous_T_212 : _pmpHomogeneous_T_218; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_176 & _pmpHomogeneous_T_219; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_221 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 & _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}] wire [31:0] _GEN_16 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_222; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_222 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_229; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_229 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_236; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_236 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_243; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_243 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_223 = ~_pmpHomogeneous_T_222; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_224 = {_pmpHomogeneous_T_223[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_225}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_227 = _pmpHomogeneous_T_226[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_228 = |_pmpHomogeneous_T_227; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_230 = ~_pmpHomogeneous_T_229; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_231 = {_pmpHomogeneous_T_230[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_232}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_234 = _pmpHomogeneous_T_233[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_235 = |_pmpHomogeneous_T_234; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_237 = ~_pmpHomogeneous_T_236; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_238 = {_pmpHomogeneous_T_237[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_239}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_241 = _pmpHomogeneous_T_240[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_242 = |_pmpHomogeneous_T_241; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_244 = ~_pmpHomogeneous_T_243; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_245 = {_pmpHomogeneous_T_244[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_246 = ~_pmpHomogeneous_T_245; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_247 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_246}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_249 = |_pmpHomogeneous_T_248; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_251 = _pmpHomogeneous_T_250 ? _pmpHomogeneous_T_235 : _pmpHomogeneous_T_228; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_253 = _pmpHomogeneous_T_252 ? _pmpHomogeneous_T_242 : _pmpHomogeneous_T_251; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_254 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_255 = _pmpHomogeneous_T_254 ? _pmpHomogeneous_T_249 : _pmpHomogeneous_T_253; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_256 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_255; // @[package.scala:39:76] wire _pmpHomogeneous_T_257 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_258 = ~_pmpHomogeneous_T_257; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}] wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_17; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_17; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_259 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_260 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_261 = _pmpHomogeneous_T_259 | _pmpHomogeneous_T_260; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_262 = _pmpHomogeneous_T_258 | _pmpHomogeneous_T_261; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_263 = _pmpHomogeneous_T_221 ? _pmpHomogeneous_T_256 : _pmpHomogeneous_T_262; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_264 = _pmpHomogeneous_T_220 & _pmpHomogeneous_T_263; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_265 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 & _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}] wire [31:0] _GEN_18 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_266; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_266 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_273; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_273 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_280; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_280 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_287; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_287 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_267 = ~_pmpHomogeneous_T_266; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_268 = {_pmpHomogeneous_T_267[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_269}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_271 = _pmpHomogeneous_T_270[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_272 = |_pmpHomogeneous_T_271; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_274 = ~_pmpHomogeneous_T_273; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_275 = {_pmpHomogeneous_T_274[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_276}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_278 = _pmpHomogeneous_T_277[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_279 = |_pmpHomogeneous_T_278; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_281 = ~_pmpHomogeneous_T_280; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_282 = {_pmpHomogeneous_T_281[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_283 = ~_pmpHomogeneous_T_282; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_284 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_283}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_286 = |_pmpHomogeneous_T_285; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_288 = ~_pmpHomogeneous_T_287; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_289 = {_pmpHomogeneous_T_288[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_291 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_290}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_292 = _pmpHomogeneous_T_291[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_293 = |_pmpHomogeneous_T_292; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_294 ? _pmpHomogeneous_T_279 : _pmpHomogeneous_T_272; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_297 = _pmpHomogeneous_T_296 ? _pmpHomogeneous_T_286 : _pmpHomogeneous_T_295; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_298 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_299 = _pmpHomogeneous_T_298 ? _pmpHomogeneous_T_293 : _pmpHomogeneous_T_297; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_300 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_299; // @[package.scala:39:76] wire _pmpHomogeneous_T_301 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_302 = ~_pmpHomogeneous_T_301; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}] wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_19; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_19; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_303 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_304 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_305 = _pmpHomogeneous_T_303 | _pmpHomogeneous_T_304; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_306 = _pmpHomogeneous_T_302 | _pmpHomogeneous_T_305; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_307 = _pmpHomogeneous_T_265 ? _pmpHomogeneous_T_300 : _pmpHomogeneous_T_306; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_308 = _pmpHomogeneous_T_264 & _pmpHomogeneous_T_307; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_309 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 & _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}] wire [31:0] _GEN_20 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_310; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_310 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_317; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_317 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_324; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_324 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_331; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_331 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_311 = ~_pmpHomogeneous_T_310; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_312 = {_pmpHomogeneous_T_311[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_313 = ~_pmpHomogeneous_T_312; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_314 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_313}; // @[PTW.scala:548:80] wire [16:0] _pmpHomogeneous_T_315 = _pmpHomogeneous_T_314[55:39]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_316 = |_pmpHomogeneous_T_315; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_318 = ~_pmpHomogeneous_T_317; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_319 = {_pmpHomogeneous_T_318[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_320 = ~_pmpHomogeneous_T_319; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_321 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_320}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_322 = _pmpHomogeneous_T_321[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_323 = |_pmpHomogeneous_T_322; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_325 = ~_pmpHomogeneous_T_324; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_326 = {_pmpHomogeneous_T_325[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_327 = ~_pmpHomogeneous_T_326; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_328 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_327}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_329 = _pmpHomogeneous_T_328[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_330 = |_pmpHomogeneous_T_329; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_332 = ~_pmpHomogeneous_T_331; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_333 = {_pmpHomogeneous_T_332[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_334 = ~_pmpHomogeneous_T_333; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_335 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_334}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_336 = _pmpHomogeneous_T_335[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_337 = |_pmpHomogeneous_T_336; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_339 = _pmpHomogeneous_T_338 ? _pmpHomogeneous_T_323 : _pmpHomogeneous_T_316; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_341 = _pmpHomogeneous_T_340 ? _pmpHomogeneous_T_330 : _pmpHomogeneous_T_339; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_342 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_343 = _pmpHomogeneous_T_342 ? _pmpHomogeneous_T_337 : _pmpHomogeneous_T_341; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_344 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_343; // @[package.scala:39:76] wire _pmpHomogeneous_T_345 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_346 = ~_pmpHomogeneous_T_345; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hC0000000 : 32'h0; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFE00000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}] wire [55:0] _GEN_21 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_21; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_21; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_347 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_348 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_349 = _pmpHomogeneous_T_347 | _pmpHomogeneous_T_348; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_350 = _pmpHomogeneous_T_346 | _pmpHomogeneous_T_349; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_351 = _pmpHomogeneous_T_309 ? _pmpHomogeneous_T_344 : _pmpHomogeneous_T_350; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire pmpHomogeneous = _pmpHomogeneous_T_308 & _pmpHomogeneous_T_351; // @[PMP.scala:118:8, :138:10] wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_0_resp_bits_gpa_bits_T_3 = &aux_count; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [16:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:27]; // @[PTW.scala:280:20, :343:49] wire [16:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:27]; // @[PTW.scala:280:20, :343:49] wire [26:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79] wire [26:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79] wire [26:0] _r_pte_T_18 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79] wire [26:0] _aux_pte_s1_ppns_T_1 = r_req_addr[26:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_21 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_3 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_11 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_11 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _r_pte_T_24 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _aux_pte_s1_ppns_T_5 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = {_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_12}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_15 = _io_requestor_0_resp_bits_gpa_bits_T_14 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_17 = _io_requestor_0_resp_bits_gpa_bits_T_16 ? _io_requestor_0_resp_bits_gpa_bits_T_13 : _io_requestor_0_resp_bits_gpa_bits_T_15; // @[package.scala:39:{76,86}] wire _io_requestor_0_resp_bits_gpa_bits_T_18 = &aux_count; // @[package.scala:39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_19 = _io_requestor_0_resp_bits_gpa_bits_T_18 ? _io_requestor_0_resp_bits_gpa_bits_T_13 : _io_requestor_0_resp_bits_gpa_bits_T_17; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_20 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_19; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_21 = {_io_requestor_0_resp_bits_gpa_bits_T_20, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_21[47:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_3 = &aux_count; // @[PTW.scala:278:22, :566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = {_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_12}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_15 = _io_requestor_1_resp_bits_gpa_bits_T_14 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_17 = _io_requestor_1_resp_bits_gpa_bits_T_16 ? _io_requestor_1_resp_bits_gpa_bits_T_13 : _io_requestor_1_resp_bits_gpa_bits_T_15; // @[package.scala:39:{76,86}] wire _io_requestor_1_resp_bits_gpa_bits_T_18 = &aux_count; // @[package.scala:39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_19 = _io_requestor_1_resp_bits_gpa_bits_T_18 ? _io_requestor_1_resp_bits_gpa_bits_T_13 : _io_requestor_1_resp_bits_gpa_bits_T_17; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_20 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_19; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_21 = {_io_requestor_1_resp_bits_gpa_bits_T_20, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_21[47:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _T_142 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _GEN_22 = ~(|state) & _T_142; // @[Decoupled.scala:51:35] wire _satp_initial_count_T_2 = satp_mode[0]; // @[package.scala:163:13] wire [3:0] _satp_initial_count_T_3 = 4'h1 - {3'h0, _satp_initial_count_T_2}; // @[package.scala:163:13] wire [2:0] satp_initial_count = _satp_initial_count_T_3[2:0]; // @[PTW.scala:586:61] wire [2:0] _count_T_4 = satp_initial_count; // @[PTW.scala:586:61, :596:27] wire [43:0] aux_ppn = {8'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26] wire [5:0] resp_gf_idxs_0 = aux_ppn[43:38]; // @[PTW.scala:589:38, :787:58] wire [14:0] resp_gf_idxs_1 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_1 = resp_gf_idxs_1; // @[package.scala:43:40] wire [14:0] _resp_gf_WIRE_0 = {9'h0, resp_gf_idxs_0}; // @[package.scala:43:40] wire _resp_gf_T_2 = |_resp_gf_WIRE_1; // @[package.scala:43:40] wire _gpa_pgoff_T = &aux_count; // @[PTW.scala:278:22, :566:60, :615:36] wire [38:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [38:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 39'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_23 = _GEN_0 + 3'h1; // @[PTW.scala:324:40, :624:24] wire [2:0] _count_T_5; // @[PTW.scala:624:24] assign _count_T_5 = _GEN_23; // @[PTW.scala:624:24] wire [2:0] _count_T_7; // @[PTW.scala:696:22] assign _count_T_7 = _GEN_23; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_23; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_6 = _count_T_5[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_153 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire _T_154 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _GEN_24 = _T_165 | _T_153; // @[PTW.scala:377:24, :393:26, :583:18] assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_24) & _T_154 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h3; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFC0000 : 44'hFFFF8000000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFE00 : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [16:0] _merged_pte_stage1_ppns_T = pte_ppn[43:27]; // @[PTW.scala:305:26, :663:64] wire [16:0] r_pte_idxs_1_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :663:64, :778:58] wire [16:0] _aux_pte_s1_ppns_T = pte_ppn[43:27]; // @[PTW.scala:305:26, :663:64, :744:62] wire [26:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[26:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [25:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_4 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_4 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_5 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_2 = {_merged_pte_stage1_ppns_T_4, _merged_pte_stage1_ppns_T_5}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? merged_pte_stage1_ppns_2 : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire [3:0] _r_pte_count_T_3 = 4'h1 - {3'h0, _r_pte_count_T_2}; // @[package.scala:163:13] wire [2:0] r_pte_count = _r_pte_count_T_3[2:0]; // @[PTW.scala:777:44] wire [2:0] _r_pte_lsbs_truncIdx_T = r_pte_count; // @[package.scala:38:21] wire r_pte_lsbs_truncIdx = _r_pte_lsbs_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_lsbs_T = r_pte_lsbs_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26] wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}] assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}] wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26] assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73] wire [3:0] _r_pte_count_T_7 = 4'h1 - {3'h0, _r_pte_count_T_6}; // @[package.scala:163:13] wire [2:0] r_pte_count_1 = _r_pte_count_T_7[2:0]; // @[PTW.scala:777:44] wire [2:0] _r_pte_lsbs_truncIdx_T_1 = r_pte_count_1; // @[package.scala:38:21] wire [7:0] r_pte_idxs_0_1 = pte_ppn[43:36]; // @[PTW.scala:305:26, :778:58] wire r_pte_lsbs_truncIdx_1 = _r_pte_lsbs_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _r_pte_lsbs_T_2 = r_pte_lsbs_truncIdx_1; // @[package.scala:38:47, :39:86] wire [16:0] _r_pte_lsbs_T_3 = _r_pte_lsbs_T_2 ? r_pte_idxs_1_1 : {9'h0, r_pte_idxs_0_1}; // @[package.scala:39:{76,86}] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = _r_pte_lsbs_T_3[1:0]; // @[package.scala:39:76] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [16:0] _r_pte_T_17 = r_pte_ppn[43:27]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [25:0] _r_pte_T_20 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_23 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_25 = {_r_pte_T_23, _r_pte_T_24}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _r_pte_T_27 = _r_pte_T_26 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] _r_pte_T_29 = _r_pte_T_28 ? _r_pte_T_25 : _r_pte_T_27; // @[package.scala:39:{76,86}] wire _r_pte_T_30 = &count; // @[package.scala:39:86] wire [43:0] _r_pte_T_31 = _r_pte_T_30 ? _r_pte_T_25 : _r_pte_T_29; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_31; // @[package.scala:39:76] wire _r_pte_T_32 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_33_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_33_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_33_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_33_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_34_reserved_for_future = _r_pte_T_32 ? _r_pte_T_33_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_34_ppn = _r_pte_T_32 ? _r_pte_T_33_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_34_reserved_for_software = _r_pte_T_32 ? _r_pte_T_33_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_34_d = _r_pte_T_32 ? _r_pte_T_33_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_34_a = _r_pte_T_32 ? _r_pte_T_33_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_34_g = _r_pte_T_32 ? _r_pte_T_33_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_34_u = _r_pte_T_32 ? _r_pte_T_33_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_34_x = _r_pte_T_32 ? _r_pte_T_33_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_34_w = _r_pte_T_32 ? _r_pte_T_33_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_34_r = _r_pte_T_32 ? _r_pte_T_33_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_34_v = _r_pte_T_32 ? _r_pte_T_33_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_35_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_34_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_35_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_34_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_35_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_34_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_34_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_34_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_34_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_34_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_34_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_34_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_34_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_35_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_34_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_36_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_35_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_36_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_35_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_36_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_35_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_35_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_35_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_35_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_35_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_35_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_35_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_35_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_36_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_35_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_37_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_36_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_37_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_36_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_37_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_36_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_d = do_switch ? r_pte_pte_2_d : _r_pte_T_36_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_a = do_switch ? r_pte_pte_2_a : _r_pte_T_36_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_g = do_switch ? r_pte_pte_2_g : _r_pte_T_36_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_u = do_switch ? r_pte_pte_2_u : _r_pte_T_36_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_x = do_switch ? r_pte_pte_2_x : _r_pte_T_36_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_w = do_switch ? r_pte_pte_2_w : _r_pte_T_36_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_r = do_switch ? r_pte_pte_2_r : _r_pte_T_36_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_37_v = do_switch ? r_pte_pte_2_v : _r_pte_T_36_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_38_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_37_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8] wire [43:0] _r_pte_T_38_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_37_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire [1:0] _r_pte_T_38_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_37_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_d = ~_r_pte_T_7 & _r_pte_T_37_d; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_a = ~_r_pte_T_7 & _r_pte_T_37_a; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_g = ~_r_pte_T_7 & _r_pte_T_37_g; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_u = ~_r_pte_T_7 & _r_pte_T_37_u; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_x = ~_r_pte_T_7 & _r_pte_T_37_x; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_w = ~_r_pte_T_7 & _r_pte_T_37_w; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_r = ~_r_pte_T_7 & _r_pte_T_37_r; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_38_v = ~_r_pte_T_7 & _r_pte_T_37_v; // @[PTW.scala:674:{8,25}, :676:8] wire [9:0] _r_pte_T_39_reserved_for_future = _r_pte_T_38_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_39_ppn = _r_pte_T_38_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_39_reserved_for_software = _r_pte_T_38_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_d = _r_pte_T_38_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_a = _r_pte_T_38_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_g = _r_pte_T_38_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_u = _r_pte_T_38_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_x = _r_pte_T_38_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_w = _r_pte_T_38_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_r = _r_pte_T_38_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_39_v = _r_pte_T_38_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_40_reserved_for_future = _r_pte_T_39_reserved_for_future; // @[PTW.scala:670:8, :672:8] wire [43:0] _r_pte_T_40_ppn = _r_pte_T_39_ppn; // @[PTW.scala:670:8, :672:8] wire [1:0] _r_pte_T_40_reserved_for_software = _r_pte_T_39_reserved_for_software; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_d = _r_pte_T_39_d; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_a = _r_pte_T_39_a; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_g = _r_pte_T_39_g; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_u = _r_pte_T_39_u; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_x = _r_pte_T_39_x; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_w = _r_pte_T_39_w; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_r = _r_pte_T_39_r; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_40_v = _r_pte_T_39_v; // @[PTW.scala:670:8, :672:8] wire [1:0] _count_T_8 = _count_T_7[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_181 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_181 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T = &count; // @[package.scala:39:86] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_7 = &aux_count; // @[PTW.scala:278:22, :566:60, :715:40] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_25 = traverse | _T_181; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_4 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_5 = gf | _resp_gf_T_4; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_122 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} wire _in_flight_WIRE : UInt<1>[10] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) connect _in_flight_WIRE[8], UInt<1>(0h0) connect _in_flight_WIRE[9], UInt<1>(0h0) regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_22 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_23 = and(_T_21, _T_22) node _T_24 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_25 = and(_T_23, _T_24) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_27 = and(_T_25, _T_26) node _T_28 = or(_T_20, _T_27) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_28, UInt<1>(0h1), "") : assert_4 node _T_32 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(_T_32, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_51 = and(_T_49, _T_50) node _T_52 = or(_T_44, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_52, UInt<1>(0h1), "") : assert_6 node _T_56 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_58 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(_T_56, _T_63) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_64, UInt<1>(0h1), "") : assert_7 node _T_68 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_75 = and(_T_73, _T_74) node _T_76 = or(_T_68, _T_75) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_76, UInt<1>(0h1), "") : assert_8 node _T_80 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_87 = and(_T_85, _T_86) node _T_88 = or(_T_80, _T_87) node _T_89 = asUInt(reset) node _T_90 = eq(_T_89, UInt<1>(0h0)) when _T_90 : node _T_91 = eq(_T_88, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9 assert(clock, _T_88, UInt<1>(0h1), "") : assert_9 node _T_92 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_94 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_92, _T_99) node _T_101 = asUInt(reset) node _T_102 = eq(_T_101, UInt<1>(0h0)) when _T_102 : node _T_103 = eq(_T_100, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10 assert(clock, _T_100, UInt<1>(0h1), "") : assert_10

module NoCMonitor_122( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46]